1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_CMD_H 5 #define __HCLGE_CMD_H 6 #include <linux/types.h> 7 #include <linux/io.h> 8 9 #define HCLGE_CMDQ_TX_TIMEOUT 30000 10 11 struct hclge_dev; 12 struct hclge_desc { 13 __le16 opcode; 14 15 #define HCLGE_CMDQ_RX_INVLD_B 0 16 #define HCLGE_CMDQ_RX_OUTVLD_B 1 17 18 __le16 flag; 19 __le16 retval; 20 __le16 rsv; 21 __le32 data[6]; 22 }; 23 24 struct hclge_cmq_ring { 25 dma_addr_t desc_dma_addr; 26 struct hclge_desc *desc; 27 struct hclge_dev *dev; 28 u32 head; 29 u32 tail; 30 31 u16 buf_size; 32 u16 desc_num; 33 int next_to_use; 34 int next_to_clean; 35 u8 ring_type; /* cmq ring type */ 36 spinlock_t lock; /* Command queue lock */ 37 }; 38 39 enum hclge_cmd_return_status { 40 HCLGE_CMD_EXEC_SUCCESS = 0, 41 HCLGE_CMD_NO_AUTH = 1, 42 HCLGE_CMD_NOT_SUPPORTED = 2, 43 HCLGE_CMD_QUEUE_FULL = 3, 44 }; 45 46 enum hclge_cmd_status { 47 HCLGE_STATUS_SUCCESS = 0, 48 HCLGE_ERR_CSQ_FULL = -1, 49 HCLGE_ERR_CSQ_TIMEOUT = -2, 50 HCLGE_ERR_CSQ_ERROR = -3, 51 }; 52 53 struct hclge_misc_vector { 54 u8 __iomem *addr; 55 int vector_irq; 56 }; 57 58 struct hclge_cmq { 59 struct hclge_cmq_ring csq; 60 struct hclge_cmq_ring crq; 61 u16 tx_timeout; 62 enum hclge_cmd_status last_status; 63 }; 64 65 #define HCLGE_CMD_FLAG_IN BIT(0) 66 #define HCLGE_CMD_FLAG_OUT BIT(1) 67 #define HCLGE_CMD_FLAG_NEXT BIT(2) 68 #define HCLGE_CMD_FLAG_WR BIT(3) 69 #define HCLGE_CMD_FLAG_NO_INTR BIT(4) 70 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5) 71 72 enum hclge_opcode_type { 73 /* Generic commands */ 74 HCLGE_OPC_QUERY_FW_VER = 0x0001, 75 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, 76 HCLGE_OPC_GBL_RST_STATUS = 0x0021, 77 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, 78 HCLGE_OPC_QUERY_PF_RSRC = 0x0023, 79 HCLGE_OPC_QUERY_VF_RSRC = 0x0024, 80 HCLGE_OPC_GET_CFG_PARAM = 0x0025, 81 82 HCLGE_OPC_STATS_64_BIT = 0x0030, 83 HCLGE_OPC_STATS_32_BIT = 0x0031, 84 HCLGE_OPC_STATS_MAC = 0x0032, 85 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033, 86 HCLGE_OPC_STATS_MAC_ALL = 0x0034, 87 88 HCLGE_OPC_QUERY_REG_NUM = 0x0040, 89 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, 90 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, 91 HCLGE_OPC_DFX_BD_NUM = 0x0043, 92 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044, 93 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045, 94 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046, 95 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047, 96 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048, 97 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049, 98 HCLGE_OPC_DFX_NCSI_REG = 0x004A, 99 HCLGE_OPC_DFX_RTC_REG = 0x004B, 100 HCLGE_OPC_DFX_PPP_REG = 0x004C, 101 HCLGE_OPC_DFX_RCB_REG = 0x004D, 102 HCLGE_OPC_DFX_TQP_REG = 0x004E, 103 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F, 104 HCLGE_OPC_DFX_QUERY_CHIP_CAP = 0x0050, 105 106 /* MAC command */ 107 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, 108 HCLGE_OPC_CONFIG_AN_MODE = 0x0304, 109 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, 110 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, 111 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, 112 HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310, 113 HCLGE_OPC_MAC_TNL_INT_EN = 0x0311, 114 HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312, 115 HCLGE_OPC_SERDES_LOOPBACK = 0x0315, 116 HCLGE_OPC_CONFIG_FEC_MODE = 0x031A, 117 118 /* PFC/Pause commands */ 119 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, 120 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, 121 HCLGE_OPC_CFG_MAC_PARA = 0x0703, 122 HCLGE_OPC_CFG_PFC_PARA = 0x0704, 123 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, 124 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, 125 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, 126 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, 127 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, 128 HCLGE_OPC_QOS_MAP = 0x070A, 129 130 /* ETS/scheduler commands */ 131 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, 132 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, 133 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, 134 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, 135 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, 136 HCLGE_OPC_TM_PG_WEIGHT = 0x0809, 137 HCLGE_OPC_TM_QS_WEIGHT = 0x080A, 138 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, 139 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, 140 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, 141 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, 142 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, 143 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, 144 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, 145 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, 146 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, 147 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, 148 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843, 149 HCLGE_OPC_QSET_DFX_STS = 0x0844, 150 HCLGE_OPC_PRI_DFX_STS = 0x0845, 151 HCLGE_OPC_PG_DFX_STS = 0x0846, 152 HCLGE_OPC_PORT_DFX_STS = 0x0847, 153 HCLGE_OPC_SCH_NQ_CNT = 0x0848, 154 HCLGE_OPC_SCH_RQ_CNT = 0x0849, 155 HCLGE_OPC_TM_INTERNAL_STS = 0x0850, 156 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851, 157 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852, 158 159 /* Packet buffer allocate commands */ 160 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, 161 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, 162 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, 163 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, 164 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, 165 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, 166 167 /* TQP management command */ 168 HCLGE_OPC_SET_TQP_MAP = 0x0A01, 169 170 /* TQP commands */ 171 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, 172 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, 173 HCLGE_OPC_QUERY_TX_STATUS = 0x0B03, 174 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04, 175 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, 176 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, 177 HCLGE_OPC_QUERY_RX_STATUS = 0x0B13, 178 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, 179 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, 180 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 181 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, 182 183 /* PPU commands */ 184 HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A, 185 186 /* TSO command */ 187 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, 188 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10, 189 190 /* RSS commands */ 191 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, 192 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, 193 HCLGE_OPC_RSS_TC_MODE = 0x0D08, 194 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, 195 196 /* Promisuous mode command */ 197 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, 198 199 /* Vlan offload commands */ 200 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, 201 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, 202 203 /* Interrupts commands */ 204 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, 205 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, 206 207 /* MAC commands */ 208 HCLGE_OPC_MAC_VLAN_ADD = 0x1000, 209 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, 210 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, 211 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, 212 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004, 213 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, 214 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, 215 216 /* VLAN commands */ 217 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, 218 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, 219 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, 220 221 /* Flow Director commands */ 222 HCLGE_OPC_FD_MODE_CTRL = 0x1200, 223 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201, 224 HCLGE_OPC_FD_KEY_CONFIG = 0x1202, 225 HCLGE_OPC_FD_TCAM_OP = 0x1203, 226 HCLGE_OPC_FD_AD_OP = 0x1204, 227 228 /* MDIO command */ 229 HCLGE_OPC_MDIO_CONFIG = 0x1900, 230 231 /* QCN commands */ 232 HCLGE_OPC_QCN_MOD_CFG = 0x1A01, 233 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, 234 HCLGE_OPC_QCN_SHAPPING_IR_CFG = 0x1A03, 235 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, 236 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, 237 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, 238 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, 239 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, 240 241 /* Mailbox command */ 242 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, 243 244 /* Led command */ 245 HCLGE_OPC_LED_STATUS_CFG = 0xB000, 246 247 /* NCL config command */ 248 HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011, 249 /* M7 stats command */ 250 HCLGE_OPC_M7_STATS_BD = 0x7012, 251 HCLGE_OPC_M7_STATS_INFO = 0x7013, 252 253 /* SFP command */ 254 HCLGE_OPC_GET_SFP_INFO = 0x7104, 255 256 /* Error INT commands */ 257 HCLGE_MAC_COMMON_INT_EN = 0x030E, 258 HCLGE_TM_SCH_ECC_INT_EN = 0x0829, 259 HCLGE_SSU_ECC_INT_CMD = 0x0989, 260 HCLGE_SSU_COMMON_INT_CMD = 0x098C, 261 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40, 262 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41, 263 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42, 264 HCLGE_COMMON_ECC_INT_CFG = 0x1505, 265 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510, 266 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511, 267 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512, 268 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513, 269 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514, 270 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515, 271 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580, 272 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581, 273 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584, 274 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585, 275 HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586, 276 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803, 277 HCLGE_IGU_COMMON_INT_EN = 0x1806, 278 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14, 279 HCLGE_PPP_CMD0_INT_CMD = 0x2100, 280 HCLGE_PPP_CMD1_INT_CMD = 0x2101, 281 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105, 282 HCLGE_NCSI_INT_EN = 0x2401, 283 }; 284 285 #define HCLGE_TQP_REG_OFFSET 0x80000 286 #define HCLGE_TQP_REG_SIZE 0x200 287 288 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 289 #define HCLGE_RCB_INIT_FLAG_EN_B 0 290 #define HCLGE_RCB_INIT_FLAG_FINI_B 8 291 struct hclge_config_rcb_init_cmd { 292 __le16 rcb_init_flag; 293 u8 rsv[22]; 294 }; 295 296 struct hclge_tqp_map_cmd { 297 __le16 tqp_id; /* Absolute tqp id for in this pf */ 298 u8 tqp_vf; /* VF id */ 299 #define HCLGE_TQP_MAP_TYPE_PF 0 300 #define HCLGE_TQP_MAP_TYPE_VF 1 301 #define HCLGE_TQP_MAP_TYPE_B 0 302 #define HCLGE_TQP_MAP_EN_B 1 303 u8 tqp_flag; /* Indicate it's pf or vf tqp */ 304 __le16 tqp_vid; /* Virtual id in this pf/vf */ 305 u8 rsv[18]; 306 }; 307 308 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 309 310 enum hclge_int_type { 311 HCLGE_INT_TX, 312 HCLGE_INT_RX, 313 HCLGE_INT_EVENT, 314 }; 315 316 struct hclge_ctrl_vector_chain_cmd { 317 u8 int_vector_id; 318 u8 int_cause_num; 319 #define HCLGE_INT_TYPE_S 0 320 #define HCLGE_INT_TYPE_M GENMASK(1, 0) 321 #define HCLGE_TQP_ID_S 2 322 #define HCLGE_TQP_ID_M GENMASK(12, 2) 323 #define HCLGE_INT_GL_IDX_S 13 324 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) 325 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; 326 u8 vfid; 327 u8 rsv; 328 }; 329 330 #define HCLGE_MAX_TC_NUM 8 331 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ 332 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ 333 struct hclge_tx_buff_alloc_cmd { 334 __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM]; 335 u8 tx_buff_rsv[8]; 336 }; 337 338 struct hclge_rx_priv_buff_cmd { 339 __le16 buf_num[HCLGE_MAX_TC_NUM]; 340 __le16 shared_buf; 341 u8 rsv[6]; 342 }; 343 344 struct hclge_query_version_cmd { 345 __le32 firmware; 346 __le32 firmware_rsv[5]; 347 }; 348 349 #define HCLGE_RX_PRIV_EN_B 15 350 #define HCLGE_TC_NUM_ONE_DESC 4 351 struct hclge_priv_wl { 352 __le16 high; 353 __le16 low; 354 }; 355 356 struct hclge_rx_priv_wl_buf { 357 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; 358 }; 359 360 struct hclge_rx_com_thrd { 361 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; 362 }; 363 364 struct hclge_rx_com_wl { 365 struct hclge_priv_wl com_wl; 366 }; 367 368 struct hclge_waterline { 369 u32 low; 370 u32 high; 371 }; 372 373 struct hclge_tc_thrd { 374 u32 low; 375 u32 high; 376 }; 377 378 struct hclge_priv_buf { 379 struct hclge_waterline wl; /* Waterline for low and high*/ 380 u32 buf_size; /* TC private buffer size */ 381 u32 tx_buf_size; 382 u32 enable; /* Enable TC private buffer or not */ 383 }; 384 385 struct hclge_shared_buf { 386 struct hclge_waterline self; 387 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; 388 u32 buf_size; 389 }; 390 391 struct hclge_pkt_buf_alloc { 392 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; 393 struct hclge_shared_buf s_buf; 394 }; 395 396 #define HCLGE_RX_COM_WL_EN_B 15 397 struct hclge_rx_com_wl_buf_cmd { 398 __le16 high_wl; 399 __le16 low_wl; 400 u8 rsv[20]; 401 }; 402 403 #define HCLGE_RX_PKT_EN_B 15 404 struct hclge_rx_pkt_buf_cmd { 405 __le16 high_pkt; 406 __le16 low_pkt; 407 u8 rsv[20]; 408 }; 409 410 #define HCLGE_PF_STATE_DONE_B 0 411 #define HCLGE_PF_STATE_MAIN_B 1 412 #define HCLGE_PF_STATE_BOND_B 2 413 #define HCLGE_PF_STATE_MAC_N_B 6 414 #define HCLGE_PF_MAC_NUM_MASK 0x3 415 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) 416 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) 417 struct hclge_func_status_cmd { 418 __le32 vf_rst_state[4]; 419 u8 pf_state; 420 u8 mac_id; 421 u8 rsv1; 422 u8 pf_cnt_in_mac; 423 u8 pf_num; 424 u8 vf_num; 425 u8 rsv[2]; 426 }; 427 428 struct hclge_pf_res_cmd { 429 __le16 tqp_num; 430 __le16 buf_size; 431 __le16 msixcap_localid_ba_nic; 432 __le16 msixcap_localid_ba_rocee; 433 #define HCLGE_MSIX_OFT_ROCEE_S 0 434 #define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0) 435 #define HCLGE_PF_VEC_NUM_S 0 436 #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0) 437 __le16 pf_intr_vector_number; 438 __le16 pf_own_fun_number; 439 __le16 tx_buf_size; 440 __le16 dv_buf_size; 441 __le32 rsv[2]; 442 }; 443 444 #define HCLGE_CFG_OFFSET_S 0 445 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) 446 #define HCLGE_CFG_RD_LEN_S 24 447 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) 448 #define HCLGE_CFG_RD_LEN_BYTES 16 449 #define HCLGE_CFG_RD_LEN_UNIT 4 450 451 #define HCLGE_CFG_VMDQ_S 0 452 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0) 453 #define HCLGE_CFG_TC_NUM_S 8 454 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) 455 #define HCLGE_CFG_TQP_DESC_N_S 16 456 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) 457 #define HCLGE_CFG_PHY_ADDR_S 0 458 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) 459 #define HCLGE_CFG_MEDIA_TP_S 8 460 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) 461 #define HCLGE_CFG_RX_BUF_LEN_S 16 462 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) 463 #define HCLGE_CFG_MAC_ADDR_H_S 0 464 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) 465 #define HCLGE_CFG_DEFAULT_SPEED_S 16 466 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) 467 #define HCLGE_CFG_RSS_SIZE_S 24 468 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) 469 #define HCLGE_CFG_SPEED_ABILITY_S 0 470 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) 471 #define HCLGE_CFG_UMV_TBL_SPACE_S 16 472 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) 473 474 struct hclge_cfg_param_cmd { 475 __le32 offset; 476 __le32 rsv; 477 __le32 param[4]; 478 }; 479 480 #define HCLGE_MAC_MODE 0x0 481 #define HCLGE_DESC_NUM 0x40 482 483 #define HCLGE_ALLOC_VALID_B 0 484 struct hclge_vf_num_cmd { 485 u8 alloc_valid; 486 u8 rsv[23]; 487 }; 488 489 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 490 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 491 #define HCLGE_RSS_HASH_KEY_NUM 16 492 struct hclge_rss_config_cmd { 493 u8 hash_config; 494 u8 rsv[7]; 495 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; 496 }; 497 498 struct hclge_rss_input_tuple_cmd { 499 u8 ipv4_tcp_en; 500 u8 ipv4_udp_en; 501 u8 ipv4_sctp_en; 502 u8 ipv4_fragment_en; 503 u8 ipv6_tcp_en; 504 u8 ipv6_udp_en; 505 u8 ipv6_sctp_en; 506 u8 ipv6_fragment_en; 507 u8 rsv[16]; 508 }; 509 510 #define HCLGE_RSS_CFG_TBL_SIZE 16 511 512 struct hclge_rss_indirection_table_cmd { 513 __le16 start_table_index; 514 __le16 rss_set_bitmap; 515 u8 rsv[4]; 516 u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE]; 517 }; 518 519 #define HCLGE_RSS_TC_OFFSET_S 0 520 #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0) 521 #define HCLGE_RSS_TC_SIZE_S 12 522 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) 523 #define HCLGE_RSS_TC_VALID_B 15 524 struct hclge_rss_tc_mode_cmd { 525 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; 526 u8 rsv[8]; 527 }; 528 529 #define HCLGE_LINK_STATUS_UP_B 0 530 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B) 531 struct hclge_link_status_cmd { 532 u8 status; 533 u8 rsv[23]; 534 }; 535 536 struct hclge_promisc_param { 537 u8 vf_id; 538 u8 enable; 539 }; 540 541 #define HCLGE_PROMISC_TX_EN_B BIT(4) 542 #define HCLGE_PROMISC_RX_EN_B BIT(5) 543 #define HCLGE_PROMISC_EN_B 1 544 #define HCLGE_PROMISC_EN_ALL 0x7 545 #define HCLGE_PROMISC_EN_UC 0x1 546 #define HCLGE_PROMISC_EN_MC 0x2 547 #define HCLGE_PROMISC_EN_BC 0x4 548 struct hclge_promisc_cfg_cmd { 549 u8 flag; 550 u8 vf_id; 551 __le16 rsv0; 552 u8 rsv1[20]; 553 }; 554 555 enum hclge_promisc_type { 556 HCLGE_UNICAST = 1, 557 HCLGE_MULTICAST = 2, 558 HCLGE_BROADCAST = 3, 559 }; 560 561 #define HCLGE_MAC_TX_EN_B 6 562 #define HCLGE_MAC_RX_EN_B 7 563 #define HCLGE_MAC_PAD_TX_B 11 564 #define HCLGE_MAC_PAD_RX_B 12 565 #define HCLGE_MAC_1588_TX_B 13 566 #define HCLGE_MAC_1588_RX_B 14 567 #define HCLGE_MAC_APP_LP_B 15 568 #define HCLGE_MAC_LINE_LP_B 16 569 #define HCLGE_MAC_FCS_TX_B 17 570 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 571 #define HCLGE_MAC_RX_FCS_STRIP_B 19 572 #define HCLGE_MAC_RX_FCS_B 20 573 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 574 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 575 576 struct hclge_config_mac_mode_cmd { 577 __le32 txrx_pad_fcs_loop_en; 578 u8 rsv[20]; 579 }; 580 581 #define HCLGE_CFG_SPEED_S 0 582 #define HCLGE_CFG_SPEED_M GENMASK(5, 0) 583 584 #define HCLGE_CFG_DUPLEX_B 7 585 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) 586 587 struct hclge_config_mac_speed_dup_cmd { 588 u8 speed_dup; 589 590 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 591 u8 mac_change_fec_en; 592 u8 rsv[22]; 593 }; 594 595 #define HCLGE_RING_ID_MASK GENMASK(9, 0) 596 #define HCLGE_TQP_ENABLE_B 0 597 598 #define HCLGE_MAC_CFG_AN_EN_B 0 599 #define HCLGE_MAC_CFG_AN_INT_EN_B 1 600 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 601 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 602 #define HCLGE_MAC_CFG_AN_RST_B 4 603 604 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) 605 606 struct hclge_config_auto_neg_cmd { 607 __le32 cfg_an_cmd_flag; 608 u8 rsv[20]; 609 }; 610 611 struct hclge_sfp_info_cmd { 612 __le32 speed; 613 u8 query_type; /* 0: sfp speed, 1: active speed */ 614 u8 active_fec; 615 u8 autoneg; /* autoneg state */ 616 u8 autoneg_ability; /* whether support autoneg */ 617 __le32 speed_ability; /* speed ability for current media */ 618 __le32 module_type; 619 u8 rsv[8]; 620 }; 621 622 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0 623 #define HCLGE_MAC_CFG_FEC_MODE_S 1 624 #define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1) 625 #define HCLGE_MAC_CFG_FEC_SET_DEF_B 0 626 #define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1 627 628 #define HCLGE_MAC_FEC_OFF 0 629 #define HCLGE_MAC_FEC_BASER 1 630 #define HCLGE_MAC_FEC_RS 2 631 struct hclge_config_fec_cmd { 632 u8 fec_mode; 633 u8 default_config; 634 u8 rsv[22]; 635 }; 636 637 #define HCLGE_MAC_UPLINK_PORT 0x100 638 639 struct hclge_config_max_frm_size_cmd { 640 __le16 max_frm_size; 641 u8 min_frm_size; 642 u8 rsv[21]; 643 }; 644 645 enum hclge_mac_vlan_tbl_opcode { 646 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ 647 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ 648 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ 649 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ 650 }; 651 652 enum hclge_mac_vlan_add_resp_code { 653 HCLGE_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */ 654 HCLGE_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */ 655 }; 656 657 #define HCLGE_MAC_VLAN_BIT0_EN_B 0 658 #define HCLGE_MAC_VLAN_BIT1_EN_B 1 659 #define HCLGE_MAC_EPORT_SW_EN_B 12 660 #define HCLGE_MAC_EPORT_TYPE_B 11 661 #define HCLGE_MAC_EPORT_VFID_S 3 662 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) 663 #define HCLGE_MAC_EPORT_PFID_S 0 664 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) 665 struct hclge_mac_vlan_tbl_entry_cmd { 666 u8 flags; 667 u8 resp_code; 668 __le16 vlan_tag; 669 __le32 mac_addr_hi32; 670 __le16 mac_addr_lo16; 671 __le16 rsv1; 672 u8 entry_type; 673 u8 mc_mac_en; 674 __le16 egress_port; 675 __le16 egress_queue; 676 u8 rsv2[6]; 677 }; 678 679 #define HCLGE_UMV_SPC_ALC_B 0 680 struct hclge_umv_spc_alc_cmd { 681 u8 allocate; 682 u8 rsv1[3]; 683 __le32 space_size; 684 u8 rsv2[16]; 685 }; 686 687 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) 688 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) 689 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) 690 691 struct hclge_mac_mgr_tbl_entry_cmd { 692 u8 flags; 693 u8 resp_code; 694 __le16 vlan_tag; 695 __le32 mac_addr_hi32; 696 __le16 mac_addr_lo16; 697 __le16 rsv1; 698 __le16 ethter_type; 699 __le16 egress_port; 700 __le16 egress_queue; 701 u8 sw_port_id_aware; 702 u8 rsv2; 703 u8 i_port_bitmap; 704 u8 i_port_direction; 705 u8 rsv3[2]; 706 }; 707 708 struct hclge_mac_vlan_add_cmd { 709 __le16 flags; 710 __le16 mac_addr_hi16; 711 __le32 mac_addr_lo32; 712 __le32 mac_addr_msk_hi32; 713 __le16 mac_addr_msk_lo16; 714 __le16 vlan_tag; 715 __le16 ingress_port; 716 __le16 egress_port; 717 u8 rsv[4]; 718 }; 719 720 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0 721 struct hclge_mac_vlan_remove_cmd { 722 __le16 flags; 723 __le16 mac_addr_hi16; 724 __le32 mac_addr_lo32; 725 __le32 mac_addr_msk_hi32; 726 __le16 mac_addr_msk_lo16; 727 __le16 vlan_tag; 728 __le16 ingress_port; 729 __le16 egress_port; 730 u8 rsv[4]; 731 }; 732 733 struct hclge_vlan_filter_ctrl_cmd { 734 u8 vlan_type; 735 u8 vlan_fe; 736 u8 rsv1[2]; 737 u8 vf_id; 738 u8 rsv2[19]; 739 }; 740 741 struct hclge_vlan_filter_pf_cfg_cmd { 742 u8 vlan_offset; 743 u8 vlan_cfg; 744 u8 rsv[2]; 745 u8 vlan_offset_bitmap[20]; 746 }; 747 748 struct hclge_vlan_filter_vf_cfg_cmd { 749 __le16 vlan_id; 750 u8 resp_code; 751 u8 rsv; 752 u8 vlan_cfg; 753 u8 rsv1[3]; 754 u8 vf_bitmap[16]; 755 }; 756 757 #define HCLGE_ACCEPT_TAG1_B 0 758 #define HCLGE_ACCEPT_UNTAG1_B 1 759 #define HCLGE_PORT_INS_TAG1_EN_B 2 760 #define HCLGE_PORT_INS_TAG2_EN_B 3 761 #define HCLGE_CFG_NIC_ROCE_SEL_B 4 762 #define HCLGE_ACCEPT_TAG2_B 5 763 #define HCLGE_ACCEPT_UNTAG2_B 6 764 765 struct hclge_vport_vtag_tx_cfg_cmd { 766 u8 vport_vlan_cfg; 767 u8 vf_offset; 768 u8 rsv1[2]; 769 __le16 def_vlan_tag1; 770 __le16 def_vlan_tag2; 771 u8 vf_bitmap[8]; 772 u8 rsv2[8]; 773 }; 774 775 #define HCLGE_REM_TAG1_EN_B 0 776 #define HCLGE_REM_TAG2_EN_B 1 777 #define HCLGE_SHOW_TAG1_EN_B 2 778 #define HCLGE_SHOW_TAG2_EN_B 3 779 struct hclge_vport_vtag_rx_cfg_cmd { 780 u8 vport_vlan_cfg; 781 u8 vf_offset; 782 u8 rsv1[6]; 783 u8 vf_bitmap[8]; 784 u8 rsv2[8]; 785 }; 786 787 struct hclge_tx_vlan_type_cfg_cmd { 788 __le16 ot_vlan_type; 789 __le16 in_vlan_type; 790 u8 rsv[20]; 791 }; 792 793 struct hclge_rx_vlan_type_cfg_cmd { 794 __le16 ot_fst_vlan_type; 795 __le16 ot_sec_vlan_type; 796 __le16 in_fst_vlan_type; 797 __le16 in_sec_vlan_type; 798 u8 rsv[16]; 799 }; 800 801 struct hclge_cfg_com_tqp_queue_cmd { 802 __le16 tqp_id; 803 __le16 stream_id; 804 u8 enable; 805 u8 rsv[19]; 806 }; 807 808 struct hclge_cfg_tx_queue_pointer_cmd { 809 __le16 tqp_id; 810 __le16 tx_tail; 811 __le16 tx_head; 812 __le16 fbd_num; 813 __le16 ring_offset; 814 u8 rsv[14]; 815 }; 816 817 #pragma pack(1) 818 struct hclge_mac_ethertype_idx_rd_cmd { 819 u8 flags; 820 u8 resp_code; 821 __le16 vlan_tag; 822 u8 mac_add[6]; 823 __le16 index; 824 __le16 ethter_type; 825 __le16 egress_port; 826 __le16 egress_queue; 827 __le16 rev0; 828 u8 i_port_bitmap; 829 u8 i_port_direction; 830 u8 rev1[2]; 831 }; 832 833 #pragma pack() 834 835 #define HCLGE_TSO_MSS_MIN_S 0 836 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) 837 838 #define HCLGE_TSO_MSS_MAX_S 16 839 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) 840 841 struct hclge_cfg_tso_status_cmd { 842 __le16 tso_mss_min; 843 __le16 tso_mss_max; 844 u8 rsv[20]; 845 }; 846 847 #define HCLGE_GRO_EN_B 0 848 struct hclge_cfg_gro_status_cmd { 849 __le16 gro_en; 850 u8 rsv[22]; 851 }; 852 853 #define HCLGE_TSO_MSS_MIN 256 854 #define HCLGE_TSO_MSS_MAX 9668 855 856 #define HCLGE_TQP_RESET_B 0 857 struct hclge_reset_tqp_queue_cmd { 858 __le16 tqp_id; 859 u8 reset_req; 860 u8 ready_to_reset; 861 u8 rsv[20]; 862 }; 863 864 #define HCLGE_CFG_RESET_MAC_B 3 865 #define HCLGE_CFG_RESET_FUNC_B 7 866 struct hclge_reset_cmd { 867 u8 mac_func_reset; 868 u8 fun_reset_vfid; 869 u8 rsv[22]; 870 }; 871 872 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0) 873 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2) 874 #define HCLGE_CMD_SERDES_DONE_B BIT(0) 875 #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1) 876 struct hclge_serdes_lb_cmd { 877 u8 mask; 878 u8 enable; 879 u8 result; 880 u8 rsv[21]; 881 }; 882 883 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ 884 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ 885 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ 886 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ 887 #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x200 /* 512 byte */ 888 889 #define HCLGE_TYPE_CRQ 0 890 #define HCLGE_TYPE_CSQ 1 891 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 892 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 893 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 894 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 895 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 896 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 897 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c 898 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 899 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 900 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 901 #define HCLGE_NIC_CMQ_EN_B 16 902 #define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B) 903 #define HCLGE_NIC_CMQ_DESC_NUM 1024 904 #define HCLGE_NIC_CMQ_DESC_NUM_S 3 905 906 #define HCLGE_LED_LOCATE_STATE_S 0 907 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) 908 909 struct hclge_set_led_state_cmd { 910 u8 rsv1[3]; 911 u8 locate_led_config; 912 u8 rsv2[20]; 913 }; 914 915 struct hclge_get_fd_mode_cmd { 916 u8 mode; 917 u8 enable; 918 u8 rsv[22]; 919 }; 920 921 struct hclge_get_fd_allocation_cmd { 922 __le32 stage1_entry_num; 923 __le32 stage2_entry_num; 924 __le16 stage1_counter_num; 925 __le16 stage2_counter_num; 926 u8 rsv[12]; 927 }; 928 929 struct hclge_set_fd_key_config_cmd { 930 u8 stage; 931 u8 key_select; 932 u8 inner_sipv6_word_en; 933 u8 inner_dipv6_word_en; 934 u8 outer_sipv6_word_en; 935 u8 outer_dipv6_word_en; 936 u8 rsv1[2]; 937 __le32 tuple_mask; 938 __le32 meta_data_mask; 939 u8 rsv2[8]; 940 }; 941 942 #define HCLGE_FD_EPORT_SW_EN_B 0 943 struct hclge_fd_tcam_config_1_cmd { 944 u8 stage; 945 u8 xy_sel; 946 u8 port_info; 947 u8 rsv1[1]; 948 __le32 index; 949 u8 entry_vld; 950 u8 rsv2[7]; 951 u8 tcam_data[8]; 952 }; 953 954 struct hclge_fd_tcam_config_2_cmd { 955 u8 tcam_data[24]; 956 }; 957 958 struct hclge_fd_tcam_config_3_cmd { 959 u8 tcam_data[20]; 960 u8 rsv[4]; 961 }; 962 963 #define HCLGE_FD_AD_DROP_B 0 964 #define HCLGE_FD_AD_DIRECT_QID_B 1 965 #define HCLGE_FD_AD_QID_S 2 966 #define HCLGE_FD_AD_QID_M GENMASK(12, 2) 967 #define HCLGE_FD_AD_USE_COUNTER_B 12 968 #define HCLGE_FD_AD_COUNTER_NUM_S 13 969 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13) 970 #define HCLGE_FD_AD_NXT_STEP_B 20 971 #define HCLGE_FD_AD_NXT_KEY_S 21 972 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21) 973 #define HCLGE_FD_AD_WR_RULE_ID_B 0 974 #define HCLGE_FD_AD_RULE_ID_S 1 975 #define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1) 976 977 struct hclge_fd_ad_config_cmd { 978 u8 stage; 979 u8 rsv1[3]; 980 __le32 index; 981 __le64 ad_data; 982 u8 rsv2[8]; 983 }; 984 985 struct hclge_get_m7_bd_cmd { 986 __le32 bd_num; 987 u8 rsv[20]; 988 }; 989 990 struct hclge_query_ppu_pf_other_int_dfx_cmd { 991 __le16 over_8bd_no_fe_qid; 992 __le16 over_8bd_no_fe_vf_id; 993 __le16 tso_mss_cmp_min_err_qid; 994 __le16 tso_mss_cmp_min_err_vf_id; 995 __le16 tso_mss_cmp_max_err_qid; 996 __le16 tso_mss_cmp_max_err_vf_id; 997 __le16 tx_rd_fbd_poison_qid; 998 __le16 tx_rd_fbd_poison_vf_id; 999 __le16 rx_rd_fbd_poison_qid; 1000 __le16 rx_rd_fbd_poison_vf_id; 1001 u8 rsv[4]; 1002 }; 1003 1004 int hclge_cmd_init(struct hclge_dev *hdev); 1005 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) 1006 { 1007 writel(value, base + reg); 1008 } 1009 1010 #define hclge_write_dev(a, reg, value) \ 1011 hclge_write_reg((a)->io_base, (reg), (value)) 1012 #define hclge_read_dev(a, reg) \ 1013 hclge_read_reg((a)->io_base, (reg)) 1014 1015 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) 1016 { 1017 u8 __iomem *reg_addr = READ_ONCE(base); 1018 1019 return readl(reg_addr + reg); 1020 } 1021 1022 #define HCLGE_SEND_SYNC(flag) \ 1023 ((flag) & HCLGE_CMD_FLAG_NO_INTR) 1024 1025 struct hclge_hw; 1026 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); 1027 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, 1028 enum hclge_opcode_type opcode, bool is_read); 1029 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); 1030 1031 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, 1032 struct hclge_promisc_param *param); 1033 1034 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, 1035 struct hclge_desc *desc); 1036 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, 1037 struct hclge_desc *desc); 1038 1039 void hclge_cmd_uninit(struct hclge_dev *hdev); 1040 int hclge_cmd_queue_init(struct hclge_dev *hdev); 1041 #endif 1042