1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_CMD_H 5 #define __HCLGE_CMD_H 6 #include <linux/types.h> 7 #include <linux/io.h> 8 9 #define HCLGE_CMDQ_TX_TIMEOUT 30000 10 11 struct hclge_dev; 12 struct hclge_desc { 13 __le16 opcode; 14 15 #define HCLGE_CMDQ_RX_INVLD_B 0 16 #define HCLGE_CMDQ_RX_OUTVLD_B 1 17 18 __le16 flag; 19 __le16 retval; 20 __le16 rsv; 21 __le32 data[6]; 22 }; 23 24 struct hclge_cmq_ring { 25 dma_addr_t desc_dma_addr; 26 struct hclge_desc *desc; 27 struct hclge_dev *dev; 28 u32 head; 29 u32 tail; 30 31 u16 buf_size; 32 u16 desc_num; 33 int next_to_use; 34 int next_to_clean; 35 u8 ring_type; /* cmq ring type */ 36 spinlock_t lock; /* Command queue lock */ 37 }; 38 39 enum hclge_cmd_return_status { 40 HCLGE_CMD_EXEC_SUCCESS = 0, 41 HCLGE_CMD_NO_AUTH = 1, 42 HCLGE_CMD_NOT_SUPPORTED = 2, 43 HCLGE_CMD_QUEUE_FULL = 3, 44 HCLGE_CMD_NEXT_ERR = 4, 45 HCLGE_CMD_UNEXE_ERR = 5, 46 HCLGE_CMD_PARA_ERR = 6, 47 HCLGE_CMD_RESULT_ERR = 7, 48 HCLGE_CMD_TIMEOUT = 8, 49 HCLGE_CMD_HILINK_ERR = 9, 50 HCLGE_CMD_QUEUE_ILLEGAL = 10, 51 HCLGE_CMD_INVALID = 11, 52 }; 53 54 enum hclge_cmd_status { 55 HCLGE_STATUS_SUCCESS = 0, 56 HCLGE_ERR_CSQ_FULL = -1, 57 HCLGE_ERR_CSQ_TIMEOUT = -2, 58 HCLGE_ERR_CSQ_ERROR = -3, 59 }; 60 61 struct hclge_misc_vector { 62 u8 __iomem *addr; 63 int vector_irq; 64 }; 65 66 struct hclge_cmq { 67 struct hclge_cmq_ring csq; 68 struct hclge_cmq_ring crq; 69 u16 tx_timeout; 70 enum hclge_cmd_status last_status; 71 }; 72 73 #define HCLGE_CMD_FLAG_IN BIT(0) 74 #define HCLGE_CMD_FLAG_OUT BIT(1) 75 #define HCLGE_CMD_FLAG_NEXT BIT(2) 76 #define HCLGE_CMD_FLAG_WR BIT(3) 77 #define HCLGE_CMD_FLAG_NO_INTR BIT(4) 78 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5) 79 80 enum hclge_opcode_type { 81 /* Generic commands */ 82 HCLGE_OPC_QUERY_FW_VER = 0x0001, 83 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, 84 HCLGE_OPC_GBL_RST_STATUS = 0x0021, 85 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, 86 HCLGE_OPC_QUERY_PF_RSRC = 0x0023, 87 HCLGE_OPC_QUERY_VF_RSRC = 0x0024, 88 HCLGE_OPC_GET_CFG_PARAM = 0x0025, 89 HCLGE_OPC_PF_RST_DONE = 0x0026, 90 HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027, 91 92 HCLGE_OPC_STATS_64_BIT = 0x0030, 93 HCLGE_OPC_STATS_32_BIT = 0x0031, 94 HCLGE_OPC_STATS_MAC = 0x0032, 95 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033, 96 HCLGE_OPC_STATS_MAC_ALL = 0x0034, 97 98 HCLGE_OPC_QUERY_REG_NUM = 0x0040, 99 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, 100 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, 101 HCLGE_OPC_DFX_BD_NUM = 0x0043, 102 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044, 103 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045, 104 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046, 105 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047, 106 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048, 107 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049, 108 HCLGE_OPC_DFX_NCSI_REG = 0x004A, 109 HCLGE_OPC_DFX_RTC_REG = 0x004B, 110 HCLGE_OPC_DFX_PPP_REG = 0x004C, 111 HCLGE_OPC_DFX_RCB_REG = 0x004D, 112 HCLGE_OPC_DFX_TQP_REG = 0x004E, 113 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F, 114 HCLGE_OPC_DFX_QUERY_CHIP_CAP = 0x0050, 115 116 /* MAC command */ 117 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, 118 HCLGE_OPC_CONFIG_AN_MODE = 0x0304, 119 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, 120 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, 121 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, 122 HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310, 123 HCLGE_OPC_MAC_TNL_INT_EN = 0x0311, 124 HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312, 125 HCLGE_OPC_SERDES_LOOPBACK = 0x0315, 126 HCLGE_OPC_CONFIG_FEC_MODE = 0x031A, 127 128 /* PFC/Pause commands */ 129 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, 130 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, 131 HCLGE_OPC_CFG_MAC_PARA = 0x0703, 132 HCLGE_OPC_CFG_PFC_PARA = 0x0704, 133 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, 134 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, 135 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, 136 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, 137 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, 138 HCLGE_OPC_QOS_MAP = 0x070A, 139 140 /* ETS/scheduler commands */ 141 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, 142 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, 143 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, 144 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, 145 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, 146 HCLGE_OPC_TM_PG_WEIGHT = 0x0809, 147 HCLGE_OPC_TM_QS_WEIGHT = 0x080A, 148 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, 149 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, 150 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, 151 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, 152 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, 153 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, 154 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, 155 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, 156 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, 157 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, 158 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843, 159 HCLGE_OPC_QSET_DFX_STS = 0x0844, 160 HCLGE_OPC_PRI_DFX_STS = 0x0845, 161 HCLGE_OPC_PG_DFX_STS = 0x0846, 162 HCLGE_OPC_PORT_DFX_STS = 0x0847, 163 HCLGE_OPC_SCH_NQ_CNT = 0x0848, 164 HCLGE_OPC_SCH_RQ_CNT = 0x0849, 165 HCLGE_OPC_TM_INTERNAL_STS = 0x0850, 166 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851, 167 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852, 168 169 /* Packet buffer allocate commands */ 170 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, 171 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, 172 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, 173 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, 174 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, 175 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, 176 177 /* TQP management command */ 178 HCLGE_OPC_SET_TQP_MAP = 0x0A01, 179 180 /* TQP commands */ 181 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, 182 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, 183 HCLGE_OPC_QUERY_TX_STATUS = 0x0B03, 184 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04, 185 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, 186 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, 187 HCLGE_OPC_QUERY_RX_STATUS = 0x0B13, 188 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, 189 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, 190 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 191 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, 192 193 /* PPU commands */ 194 HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A, 195 196 /* TSO command */ 197 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, 198 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10, 199 200 /* RSS commands */ 201 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, 202 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, 203 HCLGE_OPC_RSS_TC_MODE = 0x0D08, 204 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, 205 206 /* Promisuous mode command */ 207 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, 208 209 /* Vlan offload commands */ 210 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, 211 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, 212 213 /* Interrupts commands */ 214 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, 215 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, 216 217 /* MAC commands */ 218 HCLGE_OPC_MAC_VLAN_ADD = 0x1000, 219 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, 220 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, 221 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, 222 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004, 223 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, 224 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, 225 226 /* VLAN commands */ 227 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, 228 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, 229 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, 230 231 /* Flow Director commands */ 232 HCLGE_OPC_FD_MODE_CTRL = 0x1200, 233 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201, 234 HCLGE_OPC_FD_KEY_CONFIG = 0x1202, 235 HCLGE_OPC_FD_TCAM_OP = 0x1203, 236 HCLGE_OPC_FD_AD_OP = 0x1204, 237 238 /* MDIO command */ 239 HCLGE_OPC_MDIO_CONFIG = 0x1900, 240 241 /* QCN commands */ 242 HCLGE_OPC_QCN_MOD_CFG = 0x1A01, 243 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, 244 HCLGE_OPC_QCN_SHAPPING_IR_CFG = 0x1A03, 245 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, 246 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, 247 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, 248 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, 249 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, 250 251 /* Mailbox command */ 252 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, 253 254 /* Led command */ 255 HCLGE_OPC_LED_STATUS_CFG = 0xB000, 256 257 /* NCL config command */ 258 HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011, 259 /* M7 stats command */ 260 HCLGE_OPC_M7_STATS_BD = 0x7012, 261 HCLGE_OPC_M7_STATS_INFO = 0x7013, 262 HCLGE_OPC_M7_COMPAT_CFG = 0x701A, 263 264 /* SFP command */ 265 HCLGE_OPC_GET_SFP_INFO = 0x7104, 266 267 /* Error INT commands */ 268 HCLGE_MAC_COMMON_INT_EN = 0x030E, 269 HCLGE_TM_SCH_ECC_INT_EN = 0x0829, 270 HCLGE_SSU_ECC_INT_CMD = 0x0989, 271 HCLGE_SSU_COMMON_INT_CMD = 0x098C, 272 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40, 273 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41, 274 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42, 275 HCLGE_COMMON_ECC_INT_CFG = 0x1505, 276 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510, 277 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511, 278 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512, 279 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513, 280 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514, 281 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515, 282 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580, 283 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581, 284 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584, 285 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585, 286 HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586, 287 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803, 288 HCLGE_IGU_COMMON_INT_EN = 0x1806, 289 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14, 290 HCLGE_PPP_CMD0_INT_CMD = 0x2100, 291 HCLGE_PPP_CMD1_INT_CMD = 0x2101, 292 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105, 293 HCLGE_NCSI_INT_EN = 0x2401, 294 }; 295 296 #define HCLGE_TQP_REG_OFFSET 0x80000 297 #define HCLGE_TQP_REG_SIZE 0x200 298 299 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 300 #define HCLGE_RCB_INIT_FLAG_EN_B 0 301 #define HCLGE_RCB_INIT_FLAG_FINI_B 8 302 struct hclge_config_rcb_init_cmd { 303 __le16 rcb_init_flag; 304 u8 rsv[22]; 305 }; 306 307 struct hclge_tqp_map_cmd { 308 __le16 tqp_id; /* Absolute tqp id for in this pf */ 309 u8 tqp_vf; /* VF id */ 310 #define HCLGE_TQP_MAP_TYPE_PF 0 311 #define HCLGE_TQP_MAP_TYPE_VF 1 312 #define HCLGE_TQP_MAP_TYPE_B 0 313 #define HCLGE_TQP_MAP_EN_B 1 314 u8 tqp_flag; /* Indicate it's pf or vf tqp */ 315 __le16 tqp_vid; /* Virtual id in this pf/vf */ 316 u8 rsv[18]; 317 }; 318 319 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 320 321 enum hclge_int_type { 322 HCLGE_INT_TX, 323 HCLGE_INT_RX, 324 HCLGE_INT_EVENT, 325 }; 326 327 struct hclge_ctrl_vector_chain_cmd { 328 u8 int_vector_id; 329 u8 int_cause_num; 330 #define HCLGE_INT_TYPE_S 0 331 #define HCLGE_INT_TYPE_M GENMASK(1, 0) 332 #define HCLGE_TQP_ID_S 2 333 #define HCLGE_TQP_ID_M GENMASK(12, 2) 334 #define HCLGE_INT_GL_IDX_S 13 335 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) 336 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; 337 u8 vfid; 338 u8 rsv; 339 }; 340 341 #define HCLGE_MAX_TC_NUM 8 342 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ 343 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ 344 struct hclge_tx_buff_alloc_cmd { 345 __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM]; 346 u8 tx_buff_rsv[8]; 347 }; 348 349 struct hclge_rx_priv_buff_cmd { 350 __le16 buf_num[HCLGE_MAX_TC_NUM]; 351 __le16 shared_buf; 352 u8 rsv[6]; 353 }; 354 355 struct hclge_query_version_cmd { 356 __le32 firmware; 357 __le32 firmware_rsv[5]; 358 }; 359 360 #define HCLGE_RX_PRIV_EN_B 15 361 #define HCLGE_TC_NUM_ONE_DESC 4 362 struct hclge_priv_wl { 363 __le16 high; 364 __le16 low; 365 }; 366 367 struct hclge_rx_priv_wl_buf { 368 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; 369 }; 370 371 struct hclge_rx_com_thrd { 372 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; 373 }; 374 375 struct hclge_rx_com_wl { 376 struct hclge_priv_wl com_wl; 377 }; 378 379 struct hclge_waterline { 380 u32 low; 381 u32 high; 382 }; 383 384 struct hclge_tc_thrd { 385 u32 low; 386 u32 high; 387 }; 388 389 struct hclge_priv_buf { 390 struct hclge_waterline wl; /* Waterline for low and high*/ 391 u32 buf_size; /* TC private buffer size */ 392 u32 tx_buf_size; 393 u32 enable; /* Enable TC private buffer or not */ 394 }; 395 396 struct hclge_shared_buf { 397 struct hclge_waterline self; 398 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; 399 u32 buf_size; 400 }; 401 402 struct hclge_pkt_buf_alloc { 403 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; 404 struct hclge_shared_buf s_buf; 405 }; 406 407 #define HCLGE_RX_COM_WL_EN_B 15 408 struct hclge_rx_com_wl_buf_cmd { 409 __le16 high_wl; 410 __le16 low_wl; 411 u8 rsv[20]; 412 }; 413 414 #define HCLGE_RX_PKT_EN_B 15 415 struct hclge_rx_pkt_buf_cmd { 416 __le16 high_pkt; 417 __le16 low_pkt; 418 u8 rsv[20]; 419 }; 420 421 #define HCLGE_PF_STATE_DONE_B 0 422 #define HCLGE_PF_STATE_MAIN_B 1 423 #define HCLGE_PF_STATE_BOND_B 2 424 #define HCLGE_PF_STATE_MAC_N_B 6 425 #define HCLGE_PF_MAC_NUM_MASK 0x3 426 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) 427 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) 428 struct hclge_func_status_cmd { 429 __le32 vf_rst_state[4]; 430 u8 pf_state; 431 u8 mac_id; 432 u8 rsv1; 433 u8 pf_cnt_in_mac; 434 u8 pf_num; 435 u8 vf_num; 436 u8 rsv[2]; 437 }; 438 439 struct hclge_pf_res_cmd { 440 __le16 tqp_num; 441 __le16 buf_size; 442 __le16 msixcap_localid_ba_nic; 443 __le16 msixcap_localid_ba_rocee; 444 #define HCLGE_MSIX_OFT_ROCEE_S 0 445 #define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0) 446 #define HCLGE_PF_VEC_NUM_S 0 447 #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0) 448 __le16 pf_intr_vector_number; 449 __le16 pf_own_fun_number; 450 __le16 tx_buf_size; 451 __le16 dv_buf_size; 452 __le32 rsv[2]; 453 }; 454 455 #define HCLGE_CFG_OFFSET_S 0 456 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) 457 #define HCLGE_CFG_RD_LEN_S 24 458 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) 459 #define HCLGE_CFG_RD_LEN_BYTES 16 460 #define HCLGE_CFG_RD_LEN_UNIT 4 461 462 #define HCLGE_CFG_VMDQ_S 0 463 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0) 464 #define HCLGE_CFG_TC_NUM_S 8 465 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) 466 #define HCLGE_CFG_TQP_DESC_N_S 16 467 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) 468 #define HCLGE_CFG_PHY_ADDR_S 0 469 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) 470 #define HCLGE_CFG_MEDIA_TP_S 8 471 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) 472 #define HCLGE_CFG_RX_BUF_LEN_S 16 473 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) 474 #define HCLGE_CFG_MAC_ADDR_H_S 0 475 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) 476 #define HCLGE_CFG_DEFAULT_SPEED_S 16 477 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) 478 #define HCLGE_CFG_RSS_SIZE_S 24 479 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) 480 #define HCLGE_CFG_SPEED_ABILITY_S 0 481 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) 482 #define HCLGE_CFG_UMV_TBL_SPACE_S 16 483 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) 484 485 struct hclge_cfg_param_cmd { 486 __le32 offset; 487 __le32 rsv; 488 __le32 param[4]; 489 }; 490 491 #define HCLGE_MAC_MODE 0x0 492 #define HCLGE_DESC_NUM 0x40 493 494 #define HCLGE_ALLOC_VALID_B 0 495 struct hclge_vf_num_cmd { 496 u8 alloc_valid; 497 u8 rsv[23]; 498 }; 499 500 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 501 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 502 #define HCLGE_RSS_HASH_KEY_NUM 16 503 struct hclge_rss_config_cmd { 504 u8 hash_config; 505 u8 rsv[7]; 506 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; 507 }; 508 509 struct hclge_rss_input_tuple_cmd { 510 u8 ipv4_tcp_en; 511 u8 ipv4_udp_en; 512 u8 ipv4_sctp_en; 513 u8 ipv4_fragment_en; 514 u8 ipv6_tcp_en; 515 u8 ipv6_udp_en; 516 u8 ipv6_sctp_en; 517 u8 ipv6_fragment_en; 518 u8 rsv[16]; 519 }; 520 521 #define HCLGE_RSS_CFG_TBL_SIZE 16 522 523 struct hclge_rss_indirection_table_cmd { 524 __le16 start_table_index; 525 __le16 rss_set_bitmap; 526 u8 rsv[4]; 527 u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE]; 528 }; 529 530 #define HCLGE_RSS_TC_OFFSET_S 0 531 #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0) 532 #define HCLGE_RSS_TC_SIZE_S 12 533 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) 534 #define HCLGE_RSS_TC_VALID_B 15 535 struct hclge_rss_tc_mode_cmd { 536 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; 537 u8 rsv[8]; 538 }; 539 540 #define HCLGE_LINK_STATUS_UP_B 0 541 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B) 542 struct hclge_link_status_cmd { 543 u8 status; 544 u8 rsv[23]; 545 }; 546 547 struct hclge_promisc_param { 548 u8 vf_id; 549 u8 enable; 550 }; 551 552 #define HCLGE_PROMISC_TX_EN_B BIT(4) 553 #define HCLGE_PROMISC_RX_EN_B BIT(5) 554 #define HCLGE_PROMISC_EN_B 1 555 #define HCLGE_PROMISC_EN_ALL 0x7 556 #define HCLGE_PROMISC_EN_UC 0x1 557 #define HCLGE_PROMISC_EN_MC 0x2 558 #define HCLGE_PROMISC_EN_BC 0x4 559 struct hclge_promisc_cfg_cmd { 560 u8 flag; 561 u8 vf_id; 562 __le16 rsv0; 563 u8 rsv1[20]; 564 }; 565 566 enum hclge_promisc_type { 567 HCLGE_UNICAST = 1, 568 HCLGE_MULTICAST = 2, 569 HCLGE_BROADCAST = 3, 570 }; 571 572 #define HCLGE_MAC_TX_EN_B 6 573 #define HCLGE_MAC_RX_EN_B 7 574 #define HCLGE_MAC_PAD_TX_B 11 575 #define HCLGE_MAC_PAD_RX_B 12 576 #define HCLGE_MAC_1588_TX_B 13 577 #define HCLGE_MAC_1588_RX_B 14 578 #define HCLGE_MAC_APP_LP_B 15 579 #define HCLGE_MAC_LINE_LP_B 16 580 #define HCLGE_MAC_FCS_TX_B 17 581 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 582 #define HCLGE_MAC_RX_FCS_STRIP_B 19 583 #define HCLGE_MAC_RX_FCS_B 20 584 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 585 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 586 587 struct hclge_config_mac_mode_cmd { 588 __le32 txrx_pad_fcs_loop_en; 589 u8 rsv[20]; 590 }; 591 592 struct hclge_pf_rst_sync_cmd { 593 #define HCLGE_PF_RST_ALL_VF_RDY_B 0 594 u8 all_vf_ready; 595 u8 rsv[23]; 596 }; 597 598 #define HCLGE_CFG_SPEED_S 0 599 #define HCLGE_CFG_SPEED_M GENMASK(5, 0) 600 601 #define HCLGE_CFG_DUPLEX_B 7 602 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) 603 604 struct hclge_config_mac_speed_dup_cmd { 605 u8 speed_dup; 606 607 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 608 u8 mac_change_fec_en; 609 u8 rsv[22]; 610 }; 611 612 #define HCLGE_RING_ID_MASK GENMASK(9, 0) 613 #define HCLGE_TQP_ENABLE_B 0 614 615 #define HCLGE_MAC_CFG_AN_EN_B 0 616 #define HCLGE_MAC_CFG_AN_INT_EN_B 1 617 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 618 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 619 #define HCLGE_MAC_CFG_AN_RST_B 4 620 621 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) 622 623 struct hclge_config_auto_neg_cmd { 624 __le32 cfg_an_cmd_flag; 625 u8 rsv[20]; 626 }; 627 628 struct hclge_sfp_info_cmd { 629 __le32 speed; 630 u8 query_type; /* 0: sfp speed, 1: active speed */ 631 u8 active_fec; 632 u8 autoneg; /* autoneg state */ 633 u8 autoneg_ability; /* whether support autoneg */ 634 __le32 speed_ability; /* speed ability for current media */ 635 __le32 module_type; 636 u8 rsv[8]; 637 }; 638 639 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0 640 #define HCLGE_MAC_CFG_FEC_MODE_S 1 641 #define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1) 642 #define HCLGE_MAC_CFG_FEC_SET_DEF_B 0 643 #define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1 644 645 #define HCLGE_MAC_FEC_OFF 0 646 #define HCLGE_MAC_FEC_BASER 1 647 #define HCLGE_MAC_FEC_RS 2 648 struct hclge_config_fec_cmd { 649 u8 fec_mode; 650 u8 default_config; 651 u8 rsv[22]; 652 }; 653 654 #define HCLGE_MAC_UPLINK_PORT 0x100 655 656 struct hclge_config_max_frm_size_cmd { 657 __le16 max_frm_size; 658 u8 min_frm_size; 659 u8 rsv[21]; 660 }; 661 662 enum hclge_mac_vlan_tbl_opcode { 663 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ 664 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ 665 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ 666 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ 667 }; 668 669 enum hclge_mac_vlan_add_resp_code { 670 HCLGE_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */ 671 HCLGE_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */ 672 }; 673 674 #define HCLGE_MAC_VLAN_BIT0_EN_B 0 675 #define HCLGE_MAC_VLAN_BIT1_EN_B 1 676 #define HCLGE_MAC_EPORT_SW_EN_B 12 677 #define HCLGE_MAC_EPORT_TYPE_B 11 678 #define HCLGE_MAC_EPORT_VFID_S 3 679 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) 680 #define HCLGE_MAC_EPORT_PFID_S 0 681 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) 682 struct hclge_mac_vlan_tbl_entry_cmd { 683 u8 flags; 684 u8 resp_code; 685 __le16 vlan_tag; 686 __le32 mac_addr_hi32; 687 __le16 mac_addr_lo16; 688 __le16 rsv1; 689 u8 entry_type; 690 u8 mc_mac_en; 691 __le16 egress_port; 692 __le16 egress_queue; 693 u8 rsv2[6]; 694 }; 695 696 #define HCLGE_UMV_SPC_ALC_B 0 697 struct hclge_umv_spc_alc_cmd { 698 u8 allocate; 699 u8 rsv1[3]; 700 __le32 space_size; 701 u8 rsv2[16]; 702 }; 703 704 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) 705 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) 706 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) 707 708 struct hclge_mac_mgr_tbl_entry_cmd { 709 u8 flags; 710 u8 resp_code; 711 __le16 vlan_tag; 712 __le32 mac_addr_hi32; 713 __le16 mac_addr_lo16; 714 __le16 rsv1; 715 __le16 ethter_type; 716 __le16 egress_port; 717 __le16 egress_queue; 718 u8 sw_port_id_aware; 719 u8 rsv2; 720 u8 i_port_bitmap; 721 u8 i_port_direction; 722 u8 rsv3[2]; 723 }; 724 725 struct hclge_mac_vlan_add_cmd { 726 __le16 flags; 727 __le16 mac_addr_hi16; 728 __le32 mac_addr_lo32; 729 __le32 mac_addr_msk_hi32; 730 __le16 mac_addr_msk_lo16; 731 __le16 vlan_tag; 732 __le16 ingress_port; 733 __le16 egress_port; 734 u8 rsv[4]; 735 }; 736 737 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0 738 struct hclge_mac_vlan_remove_cmd { 739 __le16 flags; 740 __le16 mac_addr_hi16; 741 __le32 mac_addr_lo32; 742 __le32 mac_addr_msk_hi32; 743 __le16 mac_addr_msk_lo16; 744 __le16 vlan_tag; 745 __le16 ingress_port; 746 __le16 egress_port; 747 u8 rsv[4]; 748 }; 749 750 struct hclge_vlan_filter_ctrl_cmd { 751 u8 vlan_type; 752 u8 vlan_fe; 753 u8 rsv1[2]; 754 u8 vf_id; 755 u8 rsv2[19]; 756 }; 757 758 struct hclge_vlan_filter_pf_cfg_cmd { 759 u8 vlan_offset; 760 u8 vlan_cfg; 761 u8 rsv[2]; 762 u8 vlan_offset_bitmap[20]; 763 }; 764 765 struct hclge_vlan_filter_vf_cfg_cmd { 766 __le16 vlan_id; 767 u8 resp_code; 768 u8 rsv; 769 u8 vlan_cfg; 770 u8 rsv1[3]; 771 u8 vf_bitmap[16]; 772 }; 773 774 #define HCLGE_ACCEPT_TAG1_B 0 775 #define HCLGE_ACCEPT_UNTAG1_B 1 776 #define HCLGE_PORT_INS_TAG1_EN_B 2 777 #define HCLGE_PORT_INS_TAG2_EN_B 3 778 #define HCLGE_CFG_NIC_ROCE_SEL_B 4 779 #define HCLGE_ACCEPT_TAG2_B 5 780 #define HCLGE_ACCEPT_UNTAG2_B 6 781 782 struct hclge_vport_vtag_tx_cfg_cmd { 783 u8 vport_vlan_cfg; 784 u8 vf_offset; 785 u8 rsv1[2]; 786 __le16 def_vlan_tag1; 787 __le16 def_vlan_tag2; 788 u8 vf_bitmap[8]; 789 u8 rsv2[8]; 790 }; 791 792 #define HCLGE_REM_TAG1_EN_B 0 793 #define HCLGE_REM_TAG2_EN_B 1 794 #define HCLGE_SHOW_TAG1_EN_B 2 795 #define HCLGE_SHOW_TAG2_EN_B 3 796 struct hclge_vport_vtag_rx_cfg_cmd { 797 u8 vport_vlan_cfg; 798 u8 vf_offset; 799 u8 rsv1[6]; 800 u8 vf_bitmap[8]; 801 u8 rsv2[8]; 802 }; 803 804 struct hclge_tx_vlan_type_cfg_cmd { 805 __le16 ot_vlan_type; 806 __le16 in_vlan_type; 807 u8 rsv[20]; 808 }; 809 810 struct hclge_rx_vlan_type_cfg_cmd { 811 __le16 ot_fst_vlan_type; 812 __le16 ot_sec_vlan_type; 813 __le16 in_fst_vlan_type; 814 __le16 in_sec_vlan_type; 815 u8 rsv[16]; 816 }; 817 818 struct hclge_cfg_com_tqp_queue_cmd { 819 __le16 tqp_id; 820 __le16 stream_id; 821 u8 enable; 822 u8 rsv[19]; 823 }; 824 825 struct hclge_cfg_tx_queue_pointer_cmd { 826 __le16 tqp_id; 827 __le16 tx_tail; 828 __le16 tx_head; 829 __le16 fbd_num; 830 __le16 ring_offset; 831 u8 rsv[14]; 832 }; 833 834 #pragma pack(1) 835 struct hclge_mac_ethertype_idx_rd_cmd { 836 u8 flags; 837 u8 resp_code; 838 __le16 vlan_tag; 839 u8 mac_addr[6]; 840 __le16 index; 841 __le16 ethter_type; 842 __le16 egress_port; 843 __le16 egress_queue; 844 __le16 rev0; 845 u8 i_port_bitmap; 846 u8 i_port_direction; 847 u8 rev1[2]; 848 }; 849 850 #pragma pack() 851 852 #define HCLGE_TSO_MSS_MIN_S 0 853 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) 854 855 #define HCLGE_TSO_MSS_MAX_S 16 856 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) 857 858 struct hclge_cfg_tso_status_cmd { 859 __le16 tso_mss_min; 860 __le16 tso_mss_max; 861 u8 rsv[20]; 862 }; 863 864 #define HCLGE_GRO_EN_B 0 865 struct hclge_cfg_gro_status_cmd { 866 __le16 gro_en; 867 u8 rsv[22]; 868 }; 869 870 #define HCLGE_TSO_MSS_MIN 256 871 #define HCLGE_TSO_MSS_MAX 9668 872 873 #define HCLGE_TQP_RESET_B 0 874 struct hclge_reset_tqp_queue_cmd { 875 __le16 tqp_id; 876 u8 reset_req; 877 u8 ready_to_reset; 878 u8 rsv[20]; 879 }; 880 881 #define HCLGE_CFG_RESET_MAC_B 3 882 #define HCLGE_CFG_RESET_FUNC_B 7 883 struct hclge_reset_cmd { 884 u8 mac_func_reset; 885 u8 fun_reset_vfid; 886 u8 rsv[22]; 887 }; 888 889 #define HCLGE_PF_RESET_DONE_BIT BIT(0) 890 891 struct hclge_pf_rst_done_cmd { 892 u8 pf_rst_done; 893 u8 rsv[23]; 894 }; 895 896 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0) 897 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2) 898 #define HCLGE_CMD_SERDES_DONE_B BIT(0) 899 #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1) 900 struct hclge_serdes_lb_cmd { 901 u8 mask; 902 u8 enable; 903 u8 result; 904 u8 rsv[21]; 905 }; 906 907 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ 908 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ 909 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ 910 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ 911 #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */ 912 913 #define HCLGE_TYPE_CRQ 0 914 #define HCLGE_TYPE_CSQ 1 915 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 916 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 917 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 918 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 919 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 920 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 921 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c 922 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 923 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 924 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 925 926 /* this bit indicates that the driver is ready for hardware reset */ 927 #define HCLGE_NIC_SW_RST_RDY_B 16 928 #define HCLGE_NIC_SW_RST_RDY BIT(HCLGE_NIC_SW_RST_RDY_B) 929 930 #define HCLGE_NIC_CMQ_DESC_NUM 1024 931 #define HCLGE_NIC_CMQ_DESC_NUM_S 3 932 933 #define HCLGE_LED_LOCATE_STATE_S 0 934 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) 935 936 struct hclge_set_led_state_cmd { 937 u8 rsv1[3]; 938 u8 locate_led_config; 939 u8 rsv2[20]; 940 }; 941 942 struct hclge_get_fd_mode_cmd { 943 u8 mode; 944 u8 enable; 945 u8 rsv[22]; 946 }; 947 948 struct hclge_get_fd_allocation_cmd { 949 __le32 stage1_entry_num; 950 __le32 stage2_entry_num; 951 __le16 stage1_counter_num; 952 __le16 stage2_counter_num; 953 u8 rsv[12]; 954 }; 955 956 struct hclge_set_fd_key_config_cmd { 957 u8 stage; 958 u8 key_select; 959 u8 inner_sipv6_word_en; 960 u8 inner_dipv6_word_en; 961 u8 outer_sipv6_word_en; 962 u8 outer_dipv6_word_en; 963 u8 rsv1[2]; 964 __le32 tuple_mask; 965 __le32 meta_data_mask; 966 u8 rsv2[8]; 967 }; 968 969 #define HCLGE_FD_EPORT_SW_EN_B 0 970 struct hclge_fd_tcam_config_1_cmd { 971 u8 stage; 972 u8 xy_sel; 973 u8 port_info; 974 u8 rsv1[1]; 975 __le32 index; 976 u8 entry_vld; 977 u8 rsv2[7]; 978 u8 tcam_data[8]; 979 }; 980 981 struct hclge_fd_tcam_config_2_cmd { 982 u8 tcam_data[24]; 983 }; 984 985 struct hclge_fd_tcam_config_3_cmd { 986 u8 tcam_data[20]; 987 u8 rsv[4]; 988 }; 989 990 #define HCLGE_FD_AD_DROP_B 0 991 #define HCLGE_FD_AD_DIRECT_QID_B 1 992 #define HCLGE_FD_AD_QID_S 2 993 #define HCLGE_FD_AD_QID_M GENMASK(12, 2) 994 #define HCLGE_FD_AD_USE_COUNTER_B 12 995 #define HCLGE_FD_AD_COUNTER_NUM_S 13 996 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13) 997 #define HCLGE_FD_AD_NXT_STEP_B 20 998 #define HCLGE_FD_AD_NXT_KEY_S 21 999 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21) 1000 #define HCLGE_FD_AD_WR_RULE_ID_B 0 1001 #define HCLGE_FD_AD_RULE_ID_S 1 1002 #define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1) 1003 1004 struct hclge_fd_ad_config_cmd { 1005 u8 stage; 1006 u8 rsv1[3]; 1007 __le32 index; 1008 __le64 ad_data; 1009 u8 rsv2[8]; 1010 }; 1011 1012 struct hclge_get_m7_bd_cmd { 1013 __le32 bd_num; 1014 u8 rsv[20]; 1015 }; 1016 1017 struct hclge_query_ppu_pf_other_int_dfx_cmd { 1018 __le16 over_8bd_no_fe_qid; 1019 __le16 over_8bd_no_fe_vf_id; 1020 __le16 tso_mss_cmp_min_err_qid; 1021 __le16 tso_mss_cmp_min_err_vf_id; 1022 __le16 tso_mss_cmp_max_err_qid; 1023 __le16 tso_mss_cmp_max_err_vf_id; 1024 __le16 tx_rd_fbd_poison_qid; 1025 __le16 tx_rd_fbd_poison_vf_id; 1026 __le16 rx_rd_fbd_poison_qid; 1027 __le16 rx_rd_fbd_poison_vf_id; 1028 u8 rsv[4]; 1029 }; 1030 1031 #define HCLGE_LINK_EVENT_REPORT_EN_B 0 1032 #define HCLGE_NCSI_ERROR_REPORT_EN_B 1 1033 struct hclge_firmware_compat_cmd { 1034 __le32 compat; 1035 u8 rsv[20]; 1036 }; 1037 1038 int hclge_cmd_init(struct hclge_dev *hdev); 1039 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) 1040 { 1041 writel(value, base + reg); 1042 } 1043 1044 #define hclge_write_dev(a, reg, value) \ 1045 hclge_write_reg((a)->io_base, (reg), (value)) 1046 #define hclge_read_dev(a, reg) \ 1047 hclge_read_reg((a)->io_base, (reg)) 1048 1049 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) 1050 { 1051 u8 __iomem *reg_addr = READ_ONCE(base); 1052 1053 return readl(reg_addr + reg); 1054 } 1055 1056 #define HCLGE_SEND_SYNC(flag) \ 1057 ((flag) & HCLGE_CMD_FLAG_NO_INTR) 1058 1059 struct hclge_hw; 1060 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); 1061 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, 1062 enum hclge_opcode_type opcode, bool is_read); 1063 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); 1064 1065 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, 1066 struct hclge_promisc_param *param); 1067 1068 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, 1069 struct hclge_desc *desc); 1070 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, 1071 struct hclge_desc *desc); 1072 1073 void hclge_cmd_uninit(struct hclge_dev *hdev); 1074 int hclge_cmd_queue_init(struct hclge_dev *hdev); 1075 #endif 1076