1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_CMD_H 5 #define __HCLGE_CMD_H 6 #include <linux/types.h> 7 #include <linux/io.h> 8 9 #define HCLGE_CMDQ_TX_TIMEOUT 30000 10 11 struct hclge_dev; 12 struct hclge_desc { 13 __le16 opcode; 14 15 #define HCLGE_CMDQ_RX_INVLD_B 0 16 #define HCLGE_CMDQ_RX_OUTVLD_B 1 17 18 __le16 flag; 19 __le16 retval; 20 __le16 rsv; 21 __le32 data[6]; 22 }; 23 24 struct hclge_cmq_ring { 25 dma_addr_t desc_dma_addr; 26 struct hclge_desc *desc; 27 struct hclge_dev *dev; 28 u32 head; 29 u32 tail; 30 31 u16 buf_size; 32 u16 desc_num; 33 int next_to_use; 34 int next_to_clean; 35 u8 ring_type; /* cmq ring type */ 36 spinlock_t lock; /* Command queue lock */ 37 }; 38 39 enum hclge_cmd_return_status { 40 HCLGE_CMD_EXEC_SUCCESS = 0, 41 HCLGE_CMD_NO_AUTH = 1, 42 HCLGE_CMD_NOT_EXEC = 2, 43 HCLGE_CMD_QUEUE_FULL = 3, 44 }; 45 46 enum hclge_cmd_status { 47 HCLGE_STATUS_SUCCESS = 0, 48 HCLGE_ERR_CSQ_FULL = -1, 49 HCLGE_ERR_CSQ_TIMEOUT = -2, 50 HCLGE_ERR_CSQ_ERROR = -3, 51 }; 52 53 struct hclge_misc_vector { 54 u8 __iomem *addr; 55 int vector_irq; 56 }; 57 58 struct hclge_cmq { 59 struct hclge_cmq_ring csq; 60 struct hclge_cmq_ring crq; 61 u16 tx_timeout; 62 enum hclge_cmd_status last_status; 63 }; 64 65 #define HCLGE_CMD_FLAG_IN BIT(0) 66 #define HCLGE_CMD_FLAG_OUT BIT(1) 67 #define HCLGE_CMD_FLAG_NEXT BIT(2) 68 #define HCLGE_CMD_FLAG_WR BIT(3) 69 #define HCLGE_CMD_FLAG_NO_INTR BIT(4) 70 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5) 71 72 enum hclge_opcode_type { 73 /* Generic commands */ 74 HCLGE_OPC_QUERY_FW_VER = 0x0001, 75 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, 76 HCLGE_OPC_GBL_RST_STATUS = 0x0021, 77 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, 78 HCLGE_OPC_QUERY_PF_RSRC = 0x0023, 79 HCLGE_OPC_QUERY_VF_RSRC = 0x0024, 80 HCLGE_OPC_GET_CFG_PARAM = 0x0025, 81 82 HCLGE_OPC_STATS_64_BIT = 0x0030, 83 HCLGE_OPC_STATS_32_BIT = 0x0031, 84 HCLGE_OPC_STATS_MAC = 0x0032, 85 86 HCLGE_OPC_QUERY_REG_NUM = 0x0040, 87 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, 88 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, 89 90 /* MAC command */ 91 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, 92 HCLGE_OPC_CONFIG_AN_MODE = 0x0304, 93 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, 94 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, 95 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, 96 HCLGE_OPC_SERDES_LOOPBACK = 0x0315, 97 98 /* PFC/Pause commands */ 99 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, 100 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, 101 HCLGE_OPC_CFG_MAC_PARA = 0x0703, 102 HCLGE_OPC_CFG_PFC_PARA = 0x0704, 103 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, 104 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, 105 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, 106 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, 107 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, 108 HCLGE_OPC_QOS_MAP = 0x070A, 109 110 /* ETS/scheduler commands */ 111 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, 112 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, 113 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, 114 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, 115 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, 116 HCLGE_OPC_TM_PG_WEIGHT = 0x0809, 117 HCLGE_OPC_TM_QS_WEIGHT = 0x080A, 118 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, 119 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, 120 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, 121 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, 122 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, 123 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, 124 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, 125 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, 126 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, 127 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, 128 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843, 129 130 /* Packet buffer allocate commands */ 131 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, 132 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, 133 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, 134 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, 135 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, 136 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, 137 138 /* TQP management command */ 139 HCLGE_OPC_SET_TQP_MAP = 0x0A01, 140 141 /* TQP commands */ 142 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, 143 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, 144 HCLGE_OPC_QUERY_TX_STATUS = 0x0B03, 145 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, 146 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, 147 HCLGE_OPC_QUERY_RX_STATUS = 0x0B13, 148 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, 149 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, 150 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 151 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, 152 153 /* TSO command */ 154 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, 155 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10, 156 157 /* RSS commands */ 158 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, 159 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, 160 HCLGE_OPC_RSS_TC_MODE = 0x0D08, 161 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, 162 163 /* Promisuous mode command */ 164 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, 165 166 /* Vlan offload commands */ 167 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, 168 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, 169 170 /* Interrupts commands */ 171 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, 172 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, 173 174 /* MAC commands */ 175 HCLGE_OPC_MAC_VLAN_ADD = 0x1000, 176 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, 177 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, 178 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, 179 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004, 180 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, 181 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, 182 183 /* VLAN commands */ 184 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, 185 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, 186 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, 187 188 /* Flow Director commands */ 189 HCLGE_OPC_FD_MODE_CTRL = 0x1200, 190 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201, 191 HCLGE_OPC_FD_KEY_CONFIG = 0x1202, 192 HCLGE_OPC_FD_TCAM_OP = 0x1203, 193 HCLGE_OPC_FD_AD_OP = 0x1204, 194 195 /* MDIO command */ 196 HCLGE_OPC_MDIO_CONFIG = 0x1900, 197 198 /* QCN commands */ 199 HCLGE_OPC_QCN_MOD_CFG = 0x1A01, 200 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, 201 HCLGE_OPC_QCN_SHAPPING_IR_CFG = 0x1A03, 202 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, 203 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, 204 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, 205 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, 206 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, 207 208 /* Mailbox command */ 209 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, 210 211 /* Led command */ 212 HCLGE_OPC_LED_STATUS_CFG = 0xB000, 213 214 /* SFP command */ 215 HCLGE_OPC_SFP_GET_SPEED = 0x7104, 216 217 /* Error INT commands */ 218 HCLGE_MAC_COMMON_INT_EN = 0x030E, 219 HCLGE_TM_SCH_ECC_INT_EN = 0x0829, 220 HCLGE_SSU_ECC_INT_CMD = 0x0989, 221 HCLGE_SSU_COMMON_INT_CMD = 0x098C, 222 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40, 223 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41, 224 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42, 225 HCLGE_COMMON_ECC_INT_CFG = 0x1505, 226 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510, 227 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511, 228 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512, 229 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513, 230 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514, 231 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515, 232 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580, 233 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581, 234 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584, 235 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803, 236 HCLGE_IGU_COMMON_INT_EN = 0x1806, 237 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14, 238 HCLGE_PPP_CMD0_INT_CMD = 0x2100, 239 HCLGE_PPP_CMD1_INT_CMD = 0x2101, 240 HCLGE_NCSI_INT_EN = 0x2401, 241 }; 242 243 #define HCLGE_TQP_REG_OFFSET 0x80000 244 #define HCLGE_TQP_REG_SIZE 0x200 245 246 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 247 #define HCLGE_RCB_INIT_FLAG_EN_B 0 248 #define HCLGE_RCB_INIT_FLAG_FINI_B 8 249 struct hclge_config_rcb_init_cmd { 250 __le16 rcb_init_flag; 251 u8 rsv[22]; 252 }; 253 254 struct hclge_tqp_map_cmd { 255 __le16 tqp_id; /* Absolute tqp id for in this pf */ 256 u8 tqp_vf; /* VF id */ 257 #define HCLGE_TQP_MAP_TYPE_PF 0 258 #define HCLGE_TQP_MAP_TYPE_VF 1 259 #define HCLGE_TQP_MAP_TYPE_B 0 260 #define HCLGE_TQP_MAP_EN_B 1 261 u8 tqp_flag; /* Indicate it's pf or vf tqp */ 262 __le16 tqp_vid; /* Virtual id in this pf/vf */ 263 u8 rsv[18]; 264 }; 265 266 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 267 268 enum hclge_int_type { 269 HCLGE_INT_TX, 270 HCLGE_INT_RX, 271 HCLGE_INT_EVENT, 272 }; 273 274 struct hclge_ctrl_vector_chain_cmd { 275 u8 int_vector_id; 276 u8 int_cause_num; 277 #define HCLGE_INT_TYPE_S 0 278 #define HCLGE_INT_TYPE_M GENMASK(1, 0) 279 #define HCLGE_TQP_ID_S 2 280 #define HCLGE_TQP_ID_M GENMASK(12, 2) 281 #define HCLGE_INT_GL_IDX_S 13 282 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) 283 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; 284 u8 vfid; 285 u8 rsv; 286 }; 287 288 #define HCLGE_TC_NUM 8 289 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ 290 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ 291 struct hclge_tx_buff_alloc_cmd { 292 __le16 tx_pkt_buff[HCLGE_TC_NUM]; 293 u8 tx_buff_rsv[8]; 294 }; 295 296 struct hclge_rx_priv_buff_cmd { 297 __le16 buf_num[HCLGE_TC_NUM]; 298 __le16 shared_buf; 299 u8 rsv[6]; 300 }; 301 302 struct hclge_query_version_cmd { 303 __le32 firmware; 304 __le32 firmware_rsv[5]; 305 }; 306 307 #define HCLGE_RX_PRIV_EN_B 15 308 #define HCLGE_TC_NUM_ONE_DESC 4 309 struct hclge_priv_wl { 310 __le16 high; 311 __le16 low; 312 }; 313 314 struct hclge_rx_priv_wl_buf { 315 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; 316 }; 317 318 struct hclge_rx_com_thrd { 319 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; 320 }; 321 322 struct hclge_rx_com_wl { 323 struct hclge_priv_wl com_wl; 324 }; 325 326 struct hclge_waterline { 327 u32 low; 328 u32 high; 329 }; 330 331 struct hclge_tc_thrd { 332 u32 low; 333 u32 high; 334 }; 335 336 struct hclge_priv_buf { 337 struct hclge_waterline wl; /* Waterline for low and high*/ 338 u32 buf_size; /* TC private buffer size */ 339 u32 tx_buf_size; 340 u32 enable; /* Enable TC private buffer or not */ 341 }; 342 343 #define HCLGE_MAX_TC_NUM 8 344 struct hclge_shared_buf { 345 struct hclge_waterline self; 346 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; 347 u32 buf_size; 348 }; 349 350 struct hclge_pkt_buf_alloc { 351 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; 352 struct hclge_shared_buf s_buf; 353 }; 354 355 #define HCLGE_RX_COM_WL_EN_B 15 356 struct hclge_rx_com_wl_buf_cmd { 357 __le16 high_wl; 358 __le16 low_wl; 359 u8 rsv[20]; 360 }; 361 362 #define HCLGE_RX_PKT_EN_B 15 363 struct hclge_rx_pkt_buf_cmd { 364 __le16 high_pkt; 365 __le16 low_pkt; 366 u8 rsv[20]; 367 }; 368 369 #define HCLGE_PF_STATE_DONE_B 0 370 #define HCLGE_PF_STATE_MAIN_B 1 371 #define HCLGE_PF_STATE_BOND_B 2 372 #define HCLGE_PF_STATE_MAC_N_B 6 373 #define HCLGE_PF_MAC_NUM_MASK 0x3 374 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) 375 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) 376 struct hclge_func_status_cmd { 377 __le32 vf_rst_state[4]; 378 u8 pf_state; 379 u8 mac_id; 380 u8 rsv1; 381 u8 pf_cnt_in_mac; 382 u8 pf_num; 383 u8 vf_num; 384 u8 rsv[2]; 385 }; 386 387 struct hclge_pf_res_cmd { 388 __le16 tqp_num; 389 __le16 buf_size; 390 __le16 msixcap_localid_ba_nic; 391 __le16 msixcap_localid_ba_rocee; 392 #define HCLGE_MSIX_OFT_ROCEE_S 0 393 #define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0) 394 #define HCLGE_PF_VEC_NUM_S 0 395 #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0) 396 __le16 pf_intr_vector_number; 397 __le16 pf_own_fun_number; 398 __le32 rsv[3]; 399 }; 400 401 #define HCLGE_CFG_OFFSET_S 0 402 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) 403 #define HCLGE_CFG_RD_LEN_S 24 404 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) 405 #define HCLGE_CFG_RD_LEN_BYTES 16 406 #define HCLGE_CFG_RD_LEN_UNIT 4 407 408 #define HCLGE_CFG_VMDQ_S 0 409 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0) 410 #define HCLGE_CFG_TC_NUM_S 8 411 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) 412 #define HCLGE_CFG_TQP_DESC_N_S 16 413 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) 414 #define HCLGE_CFG_PHY_ADDR_S 0 415 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) 416 #define HCLGE_CFG_MEDIA_TP_S 8 417 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) 418 #define HCLGE_CFG_RX_BUF_LEN_S 16 419 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) 420 #define HCLGE_CFG_MAC_ADDR_H_S 0 421 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) 422 #define HCLGE_CFG_DEFAULT_SPEED_S 16 423 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) 424 #define HCLGE_CFG_RSS_SIZE_S 24 425 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) 426 #define HCLGE_CFG_SPEED_ABILITY_S 0 427 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) 428 #define HCLGE_CFG_UMV_TBL_SPACE_S 16 429 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) 430 431 struct hclge_cfg_param_cmd { 432 __le32 offset; 433 __le32 rsv; 434 __le32 param[4]; 435 }; 436 437 #define HCLGE_MAC_MODE 0x0 438 #define HCLGE_DESC_NUM 0x40 439 440 #define HCLGE_ALLOC_VALID_B 0 441 struct hclge_vf_num_cmd { 442 u8 alloc_valid; 443 u8 rsv[23]; 444 }; 445 446 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 447 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 448 #define HCLGE_RSS_HASH_KEY_NUM 16 449 struct hclge_rss_config_cmd { 450 u8 hash_config; 451 u8 rsv[7]; 452 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; 453 }; 454 455 struct hclge_rss_input_tuple_cmd { 456 u8 ipv4_tcp_en; 457 u8 ipv4_udp_en; 458 u8 ipv4_sctp_en; 459 u8 ipv4_fragment_en; 460 u8 ipv6_tcp_en; 461 u8 ipv6_udp_en; 462 u8 ipv6_sctp_en; 463 u8 ipv6_fragment_en; 464 u8 rsv[16]; 465 }; 466 467 #define HCLGE_RSS_CFG_TBL_SIZE 16 468 469 struct hclge_rss_indirection_table_cmd { 470 __le16 start_table_index; 471 __le16 rss_set_bitmap; 472 u8 rsv[4]; 473 u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE]; 474 }; 475 476 #define HCLGE_RSS_TC_OFFSET_S 0 477 #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0) 478 #define HCLGE_RSS_TC_SIZE_S 12 479 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) 480 #define HCLGE_RSS_TC_VALID_B 15 481 struct hclge_rss_tc_mode_cmd { 482 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; 483 u8 rsv[8]; 484 }; 485 486 #define HCLGE_LINK_STATUS_UP_B 0 487 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B) 488 struct hclge_link_status_cmd { 489 u8 status; 490 u8 rsv[23]; 491 }; 492 493 struct hclge_promisc_param { 494 u8 vf_id; 495 u8 enable; 496 }; 497 498 #define HCLGE_PROMISC_TX_EN_B BIT(4) 499 #define HCLGE_PROMISC_RX_EN_B BIT(5) 500 #define HCLGE_PROMISC_EN_B 1 501 #define HCLGE_PROMISC_EN_ALL 0x7 502 #define HCLGE_PROMISC_EN_UC 0x1 503 #define HCLGE_PROMISC_EN_MC 0x2 504 #define HCLGE_PROMISC_EN_BC 0x4 505 struct hclge_promisc_cfg_cmd { 506 u8 flag; 507 u8 vf_id; 508 __le16 rsv0; 509 u8 rsv1[20]; 510 }; 511 512 enum hclge_promisc_type { 513 HCLGE_UNICAST = 1, 514 HCLGE_MULTICAST = 2, 515 HCLGE_BROADCAST = 3, 516 }; 517 518 #define HCLGE_MAC_TX_EN_B 6 519 #define HCLGE_MAC_RX_EN_B 7 520 #define HCLGE_MAC_PAD_TX_B 11 521 #define HCLGE_MAC_PAD_RX_B 12 522 #define HCLGE_MAC_1588_TX_B 13 523 #define HCLGE_MAC_1588_RX_B 14 524 #define HCLGE_MAC_APP_LP_B 15 525 #define HCLGE_MAC_LINE_LP_B 16 526 #define HCLGE_MAC_FCS_TX_B 17 527 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 528 #define HCLGE_MAC_RX_FCS_STRIP_B 19 529 #define HCLGE_MAC_RX_FCS_B 20 530 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 531 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 532 533 struct hclge_config_mac_mode_cmd { 534 __le32 txrx_pad_fcs_loop_en; 535 u8 rsv[20]; 536 }; 537 538 #define HCLGE_CFG_SPEED_S 0 539 #define HCLGE_CFG_SPEED_M GENMASK(5, 0) 540 541 #define HCLGE_CFG_DUPLEX_B 7 542 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) 543 544 struct hclge_config_mac_speed_dup_cmd { 545 u8 speed_dup; 546 547 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 548 u8 mac_change_fec_en; 549 u8 rsv[22]; 550 }; 551 552 #define HCLGE_RING_ID_MASK GENMASK(9, 0) 553 #define HCLGE_TQP_ENABLE_B 0 554 555 #define HCLGE_MAC_CFG_AN_EN_B 0 556 #define HCLGE_MAC_CFG_AN_INT_EN_B 1 557 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 558 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 559 #define HCLGE_MAC_CFG_AN_RST_B 4 560 561 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) 562 563 struct hclge_config_auto_neg_cmd { 564 __le32 cfg_an_cmd_flag; 565 u8 rsv[20]; 566 }; 567 568 struct hclge_sfp_speed_cmd { 569 __le32 sfp_speed; 570 u32 rsv[5]; 571 }; 572 573 #define HCLGE_MAC_UPLINK_PORT 0x100 574 575 struct hclge_config_max_frm_size_cmd { 576 __le16 max_frm_size; 577 u8 min_frm_size; 578 u8 rsv[21]; 579 }; 580 581 enum hclge_mac_vlan_tbl_opcode { 582 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ 583 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ 584 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ 585 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ 586 }; 587 588 #define HCLGE_MAC_VLAN_BIT0_EN_B 0 589 #define HCLGE_MAC_VLAN_BIT1_EN_B 1 590 #define HCLGE_MAC_EPORT_SW_EN_B 12 591 #define HCLGE_MAC_EPORT_TYPE_B 11 592 #define HCLGE_MAC_EPORT_VFID_S 3 593 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) 594 #define HCLGE_MAC_EPORT_PFID_S 0 595 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) 596 struct hclge_mac_vlan_tbl_entry_cmd { 597 u8 flags; 598 u8 resp_code; 599 __le16 vlan_tag; 600 __le32 mac_addr_hi32; 601 __le16 mac_addr_lo16; 602 __le16 rsv1; 603 u8 entry_type; 604 u8 mc_mac_en; 605 __le16 egress_port; 606 __le16 egress_queue; 607 u8 rsv2[6]; 608 }; 609 610 #define HCLGE_UMV_SPC_ALC_B 0 611 struct hclge_umv_spc_alc_cmd { 612 u8 allocate; 613 u8 rsv1[3]; 614 __le32 space_size; 615 u8 rsv2[16]; 616 }; 617 618 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) 619 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) 620 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) 621 #define HCLGE_MAC_ETHERTYPE_LLDP 0x88cc 622 623 struct hclge_mac_mgr_tbl_entry_cmd { 624 u8 flags; 625 u8 resp_code; 626 __le16 vlan_tag; 627 __le32 mac_addr_hi32; 628 __le16 mac_addr_lo16; 629 __le16 rsv1; 630 __le16 ethter_type; 631 __le16 egress_port; 632 __le16 egress_queue; 633 u8 sw_port_id_aware; 634 u8 rsv2; 635 u8 i_port_bitmap; 636 u8 i_port_direction; 637 u8 rsv3[2]; 638 }; 639 640 struct hclge_mac_vlan_add_cmd { 641 __le16 flags; 642 __le16 mac_addr_hi16; 643 __le32 mac_addr_lo32; 644 __le32 mac_addr_msk_hi32; 645 __le16 mac_addr_msk_lo16; 646 __le16 vlan_tag; 647 __le16 ingress_port; 648 __le16 egress_port; 649 u8 rsv[4]; 650 }; 651 652 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0 653 struct hclge_mac_vlan_remove_cmd { 654 __le16 flags; 655 __le16 mac_addr_hi16; 656 __le32 mac_addr_lo32; 657 __le32 mac_addr_msk_hi32; 658 __le16 mac_addr_msk_lo16; 659 __le16 vlan_tag; 660 __le16 ingress_port; 661 __le16 egress_port; 662 u8 rsv[4]; 663 }; 664 665 struct hclge_vlan_filter_ctrl_cmd { 666 u8 vlan_type; 667 u8 vlan_fe; 668 u8 rsv[22]; 669 }; 670 671 struct hclge_vlan_filter_pf_cfg_cmd { 672 u8 vlan_offset; 673 u8 vlan_cfg; 674 u8 rsv[2]; 675 u8 vlan_offset_bitmap[20]; 676 }; 677 678 struct hclge_vlan_filter_vf_cfg_cmd { 679 __le16 vlan_id; 680 u8 resp_code; 681 u8 rsv; 682 u8 vlan_cfg; 683 u8 rsv1[3]; 684 u8 vf_bitmap[16]; 685 }; 686 687 #define HCLGE_ACCEPT_TAG1_B 0 688 #define HCLGE_ACCEPT_UNTAG1_B 1 689 #define HCLGE_PORT_INS_TAG1_EN_B 2 690 #define HCLGE_PORT_INS_TAG2_EN_B 3 691 #define HCLGE_CFG_NIC_ROCE_SEL_B 4 692 #define HCLGE_ACCEPT_TAG2_B 5 693 #define HCLGE_ACCEPT_UNTAG2_B 6 694 695 struct hclge_vport_vtag_tx_cfg_cmd { 696 u8 vport_vlan_cfg; 697 u8 vf_offset; 698 u8 rsv1[2]; 699 __le16 def_vlan_tag1; 700 __le16 def_vlan_tag2; 701 u8 vf_bitmap[8]; 702 u8 rsv2[8]; 703 }; 704 705 #define HCLGE_REM_TAG1_EN_B 0 706 #define HCLGE_REM_TAG2_EN_B 1 707 #define HCLGE_SHOW_TAG1_EN_B 2 708 #define HCLGE_SHOW_TAG2_EN_B 3 709 struct hclge_vport_vtag_rx_cfg_cmd { 710 u8 vport_vlan_cfg; 711 u8 vf_offset; 712 u8 rsv1[6]; 713 u8 vf_bitmap[8]; 714 u8 rsv2[8]; 715 }; 716 717 struct hclge_tx_vlan_type_cfg_cmd { 718 __le16 ot_vlan_type; 719 __le16 in_vlan_type; 720 u8 rsv[20]; 721 }; 722 723 struct hclge_rx_vlan_type_cfg_cmd { 724 __le16 ot_fst_vlan_type; 725 __le16 ot_sec_vlan_type; 726 __le16 in_fst_vlan_type; 727 __le16 in_sec_vlan_type; 728 u8 rsv[16]; 729 }; 730 731 struct hclge_cfg_com_tqp_queue_cmd { 732 __le16 tqp_id; 733 __le16 stream_id; 734 u8 enable; 735 u8 rsv[19]; 736 }; 737 738 struct hclge_cfg_tx_queue_pointer_cmd { 739 __le16 tqp_id; 740 __le16 tx_tail; 741 __le16 tx_head; 742 __le16 fbd_num; 743 __le16 ring_offset; 744 u8 rsv[14]; 745 }; 746 747 #define HCLGE_TSO_MSS_MIN_S 0 748 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) 749 750 #define HCLGE_TSO_MSS_MAX_S 16 751 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) 752 753 struct hclge_cfg_tso_status_cmd { 754 __le16 tso_mss_min; 755 __le16 tso_mss_max; 756 u8 rsv[20]; 757 }; 758 759 #define HCLGE_GRO_EN_B 0 760 struct hclge_cfg_gro_status_cmd { 761 __le16 gro_en; 762 u8 rsv[22]; 763 }; 764 765 #define HCLGE_TSO_MSS_MIN 256 766 #define HCLGE_TSO_MSS_MAX 9668 767 768 #define HCLGE_TQP_RESET_B 0 769 struct hclge_reset_tqp_queue_cmd { 770 __le16 tqp_id; 771 u8 reset_req; 772 u8 ready_to_reset; 773 u8 rsv[20]; 774 }; 775 776 #define HCLGE_CFG_RESET_MAC_B 3 777 #define HCLGE_CFG_RESET_FUNC_B 7 778 struct hclge_reset_cmd { 779 u8 mac_func_reset; 780 u8 fun_reset_vfid; 781 u8 rsv[22]; 782 }; 783 784 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0) 785 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2) 786 #define HCLGE_CMD_SERDES_DONE_B BIT(0) 787 #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1) 788 struct hclge_serdes_lb_cmd { 789 u8 mask; 790 u8 enable; 791 u8 result; 792 u8 rsv[21]; 793 }; 794 795 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ 796 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ 797 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ 798 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ 799 800 #define HCLGE_TYPE_CRQ 0 801 #define HCLGE_TYPE_CSQ 1 802 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 803 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 804 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 805 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 806 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 807 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 808 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c 809 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 810 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 811 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 812 #define HCLGE_NIC_CMQ_EN_B 16 813 #define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B) 814 #define HCLGE_NIC_CMQ_DESC_NUM 1024 815 #define HCLGE_NIC_CMQ_DESC_NUM_S 3 816 817 #define HCLGE_LED_LOCATE_STATE_S 0 818 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) 819 820 struct hclge_set_led_state_cmd { 821 u8 rsv1[3]; 822 u8 locate_led_config; 823 u8 rsv2[20]; 824 }; 825 826 struct hclge_get_fd_mode_cmd { 827 u8 mode; 828 u8 enable; 829 u8 rsv[22]; 830 }; 831 832 struct hclge_get_fd_allocation_cmd { 833 __le32 stage1_entry_num; 834 __le32 stage2_entry_num; 835 __le16 stage1_counter_num; 836 __le16 stage2_counter_num; 837 u8 rsv[12]; 838 }; 839 840 struct hclge_set_fd_key_config_cmd { 841 u8 stage; 842 u8 key_select; 843 u8 inner_sipv6_word_en; 844 u8 inner_dipv6_word_en; 845 u8 outer_sipv6_word_en; 846 u8 outer_dipv6_word_en; 847 u8 rsv1[2]; 848 __le32 tuple_mask; 849 __le32 meta_data_mask; 850 u8 rsv2[8]; 851 }; 852 853 #define HCLGE_FD_EPORT_SW_EN_B 0 854 struct hclge_fd_tcam_config_1_cmd { 855 u8 stage; 856 u8 xy_sel; 857 u8 port_info; 858 u8 rsv1[1]; 859 __le32 index; 860 u8 entry_vld; 861 u8 rsv2[7]; 862 u8 tcam_data[8]; 863 }; 864 865 struct hclge_fd_tcam_config_2_cmd { 866 u8 tcam_data[24]; 867 }; 868 869 struct hclge_fd_tcam_config_3_cmd { 870 u8 tcam_data[20]; 871 u8 rsv[4]; 872 }; 873 874 #define HCLGE_FD_AD_DROP_B 0 875 #define HCLGE_FD_AD_DIRECT_QID_B 1 876 #define HCLGE_FD_AD_QID_S 2 877 #define HCLGE_FD_AD_QID_M GENMASK(12, 2) 878 #define HCLGE_FD_AD_USE_COUNTER_B 12 879 #define HCLGE_FD_AD_COUNTER_NUM_S 13 880 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13) 881 #define HCLGE_FD_AD_NXT_STEP_B 20 882 #define HCLGE_FD_AD_NXT_KEY_S 21 883 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21) 884 #define HCLGE_FD_AD_WR_RULE_ID_B 0 885 #define HCLGE_FD_AD_RULE_ID_S 1 886 #define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1) 887 888 struct hclge_fd_ad_config_cmd { 889 u8 stage; 890 u8 rsv1[3]; 891 __le32 index; 892 __le64 ad_data; 893 u8 rsv2[8]; 894 }; 895 896 int hclge_cmd_init(struct hclge_dev *hdev); 897 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) 898 { 899 writel(value, base + reg); 900 } 901 902 #define hclge_write_dev(a, reg, value) \ 903 hclge_write_reg((a)->io_base, (reg), (value)) 904 #define hclge_read_dev(a, reg) \ 905 hclge_read_reg((a)->io_base, (reg)) 906 907 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) 908 { 909 u8 __iomem *reg_addr = READ_ONCE(base); 910 911 return readl(reg_addr + reg); 912 } 913 914 #define HCLGE_SEND_SYNC(flag) \ 915 ((flag) & HCLGE_CMD_FLAG_NO_INTR) 916 917 struct hclge_hw; 918 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); 919 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, 920 enum hclge_opcode_type opcode, bool is_read); 921 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); 922 923 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, 924 struct hclge_promisc_param *param); 925 926 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, 927 struct hclge_desc *desc); 928 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, 929 struct hclge_desc *desc); 930 931 void hclge_destroy_cmd_queue(struct hclge_hw *hw); 932 int hclge_cmd_queue_init(struct hclge_dev *hdev); 933 #endif 934