1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #ifndef __HNS3_ENET_H 11 #define __HNS3_ENET_H 12 13 #include <linux/if_vlan.h> 14 15 #include "hnae3.h" 16 17 #define HNS3_MOD_VERSION "1.0" 18 19 extern const char hns3_driver_version[]; 20 21 enum hns3_nic_state { 22 HNS3_NIC_STATE_TESTING, 23 HNS3_NIC_STATE_RESETTING, 24 HNS3_NIC_STATE_REINITING, 25 HNS3_NIC_STATE_DOWN, 26 HNS3_NIC_STATE_DISABLED, 27 HNS3_NIC_STATE_REMOVING, 28 HNS3_NIC_STATE_SERVICE_INITED, 29 HNS3_NIC_STATE_SERVICE_SCHED, 30 HNS3_NIC_STATE2_RESET_REQUESTED, 31 HNS3_NIC_STATE_MAX 32 }; 33 34 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000 35 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004 36 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008 37 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C 38 #define HNS3_RING_RX_RING_TAIL_REG 0x00018 39 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C 40 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020 41 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C 42 43 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040 44 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044 45 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048 46 #define HNS3_RING_TX_RING_BD_LEN_REG 0x0004C 47 #define HNS3_RING_TX_RING_TAIL_REG 0x00058 48 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C 49 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060 50 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064 51 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C 52 53 #define HNS3_RING_PREFETCH_EN_REG 0x0007C 54 #define HNS3_RING_CFG_VF_NUM_REG 0x00080 55 #define HNS3_RING_ASID_REG 0x0008C 56 #define HNS3_RING_RX_VM_REG 0x00090 57 #define HNS3_RING_T0_BE_RST 0x00094 58 #define HNS3_RING_COULD_BE_RST 0x00098 59 #define HNS3_RING_WRR_WEIGHT_REG 0x0009c 60 61 #define HNS3_RING_INTMSK_RXWL_REG 0x000A0 62 #define HNS3_RING_INTSTS_RX_RING_REG 0x000A4 63 #define HNS3_RX_RING_INT_STS_REG 0x000A8 64 #define HNS3_RING_INTMSK_TXWL_REG 0x000AC 65 #define HNS3_RING_INTSTS_TX_RING_REG 0x000B0 66 #define HNS3_TX_RING_INT_STS_REG 0x000B4 67 #define HNS3_RING_INTMSK_RX_OVERTIME_REG 0x000B8 68 #define HNS3_RING_INTSTS_RX_OVERTIME_REG 0x000BC 69 #define HNS3_RING_INTMSK_TX_OVERTIME_REG 0x000C4 70 #define HNS3_RING_INTSTS_TX_OVERTIME_REG 0x000C8 71 72 #define HNS3_RING_MB_CTRL_REG 0x00100 73 #define HNS3_RING_MB_DATA_BASE_REG 0x00200 74 75 #define HNS3_TX_REG_OFFSET 0x40 76 77 #define HNS3_RX_HEAD_SIZE 256 78 79 #define HNS3_TX_TIMEOUT (5 * HZ) 80 #define HNS3_RING_NAME_LEN 16 81 #define HNS3_BUFFER_SIZE_2048 2048 82 #define HNS3_RING_MAX_PENDING 32768 83 #define HNS3_RING_MIN_PENDING 8 84 #define HNS3_RING_BD_MULTIPLE 8 85 #define HNS3_MAX_MTU 9728 86 87 #define HNS3_BD_SIZE_512_TYPE 0 88 #define HNS3_BD_SIZE_1024_TYPE 1 89 #define HNS3_BD_SIZE_2048_TYPE 2 90 #define HNS3_BD_SIZE_4096_TYPE 3 91 92 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1 93 #define HNS3_RX_FLAG_L3ID_IPV4 0x0 94 #define HNS3_RX_FLAG_L3ID_IPV6 0x1 95 #define HNS3_RX_FLAG_L4ID_UDP 0x0 96 #define HNS3_RX_FLAG_L4ID_TCP 0x1 97 98 #define HNS3_RXD_DMAC_S 0 99 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S) 100 #define HNS3_RXD_VLAN_S 2 101 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S) 102 #define HNS3_RXD_L3ID_S 4 103 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S) 104 #define HNS3_RXD_L4ID_S 8 105 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S) 106 #define HNS3_RXD_FRAG_B 12 107 #define HNS3_RXD_STRP_TAGP_S 13 108 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S) 109 110 #define HNS3_RXD_L2E_B 16 111 #define HNS3_RXD_L3E_B 17 112 #define HNS3_RXD_L4E_B 18 113 #define HNS3_RXD_TRUNCAT_B 19 114 #define HNS3_RXD_HOI_B 20 115 #define HNS3_RXD_DOI_B 21 116 #define HNS3_RXD_OL3E_B 22 117 #define HNS3_RXD_OL4E_B 23 118 119 #define HNS3_RXD_ODMAC_S 0 120 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S) 121 #define HNS3_RXD_OVLAN_S 2 122 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S) 123 #define HNS3_RXD_OL3ID_S 4 124 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S) 125 #define HNS3_RXD_OL4ID_S 8 126 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S) 127 #define HNS3_RXD_FBHI_S 12 128 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S) 129 #define HNS3_RXD_FBLI_S 14 130 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S) 131 132 #define HNS3_RXD_BDTYPE_S 0 133 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S) 134 #define HNS3_RXD_VLD_B 4 135 #define HNS3_RXD_UDP0_B 5 136 #define HNS3_RXD_EXTEND_B 7 137 #define HNS3_RXD_FE_B 8 138 #define HNS3_RXD_LUM_B 9 139 #define HNS3_RXD_CRCP_B 10 140 #define HNS3_RXD_L3L4P_B 11 141 #define HNS3_RXD_TSIND_S 12 142 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S) 143 #define HNS3_RXD_LKBK_B 15 144 #define HNS3_RXD_HDL_S 16 145 #define HNS3_RXD_HDL_M (0x7ff << HNS3_RXD_HDL_S) 146 #define HNS3_RXD_HSIND_B 31 147 148 #define HNS3_TXD_L3T_S 0 149 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S) 150 #define HNS3_TXD_L4T_S 2 151 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S) 152 #define HNS3_TXD_L3CS_B 4 153 #define HNS3_TXD_L4CS_B 5 154 #define HNS3_TXD_VLAN_B 6 155 #define HNS3_TXD_TSO_B 7 156 157 #define HNS3_TXD_L2LEN_S 8 158 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S) 159 #define HNS3_TXD_L3LEN_S 16 160 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S) 161 #define HNS3_TXD_L4LEN_S 24 162 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S) 163 164 #define HNS3_TXD_OL3T_S 0 165 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S) 166 #define HNS3_TXD_OVLAN_B 2 167 #define HNS3_TXD_MACSEC_B 3 168 #define HNS3_TXD_TUNTYPE_S 4 169 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S) 170 171 #define HNS3_TXD_BDTYPE_S 0 172 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S) 173 #define HNS3_TXD_FE_B 4 174 #define HNS3_TXD_SC_S 5 175 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S) 176 #define HNS3_TXD_EXTEND_B 7 177 #define HNS3_TXD_VLD_B 8 178 #define HNS3_TXD_RI_B 9 179 #define HNS3_TXD_RA_B 10 180 #define HNS3_TXD_TSYN_B 11 181 #define HNS3_TXD_DECTTL_S 12 182 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S) 183 184 #define HNS3_TXD_MSS_S 0 185 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) 186 187 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0) 188 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1) 189 190 #define HNS3_VECTOR_NOT_INITED 0 191 #define HNS3_VECTOR_INITED 1 192 193 #define HNS3_MAX_BD_SIZE 65535 194 #define HNS3_MAX_BD_PER_FRAG 8 195 #define HNS3_MAX_BD_PER_PKT MAX_SKB_FRAGS 196 197 #define HNS3_VECTOR_GL0_OFFSET 0x100 198 #define HNS3_VECTOR_GL1_OFFSET 0x200 199 #define HNS3_VECTOR_GL2_OFFSET 0x300 200 #define HNS3_VECTOR_RL_OFFSET 0x900 201 #define HNS3_VECTOR_RL_EN_B 6 202 203 enum hns3_pkt_l3t_type { 204 HNS3_L3T_NONE, 205 HNS3_L3T_IPV6, 206 HNS3_L3T_IPV4, 207 HNS3_L3T_RESERVED 208 }; 209 210 enum hns3_pkt_l4t_type { 211 HNS3_L4T_UNKNOWN, 212 HNS3_L4T_TCP, 213 HNS3_L4T_UDP, 214 HNS3_L4T_SCTP 215 }; 216 217 enum hns3_pkt_ol3t_type { 218 HNS3_OL3T_NONE, 219 HNS3_OL3T_IPV6, 220 HNS3_OL3T_IPV4_NO_CSUM, 221 HNS3_OL3T_IPV4_CSUM 222 }; 223 224 enum hns3_pkt_tun_type { 225 HNS3_TUN_NONE, 226 HNS3_TUN_MAC_IN_UDP, 227 HNS3_TUN_NVGRE, 228 HNS3_TUN_OTHER 229 }; 230 231 /* hardware spec ring buffer format */ 232 struct __packed hns3_desc { 233 __le64 addr; 234 union { 235 struct { 236 __le16 vlan_tag; 237 __le16 send_size; 238 union { 239 __le32 type_cs_vlan_tso_len; 240 struct { 241 __u8 type_cs_vlan_tso; 242 __u8 l2_len; 243 __u8 l3_len; 244 __u8 l4_len; 245 }; 246 }; 247 __le16 outer_vlan_tag; 248 __le16 tv; 249 250 union { 251 __le32 ol_type_vlan_len_msec; 252 struct { 253 __u8 ol_type_vlan_msec; 254 __u8 ol2_len; 255 __u8 ol3_len; 256 __u8 ol4_len; 257 }; 258 }; 259 260 __le32 paylen; 261 __le16 bdtp_fe_sc_vld_ra_ri; 262 __le16 mss; 263 } tx; 264 265 struct { 266 __le32 l234_info; 267 __le16 pkt_len; 268 __le16 size; 269 270 __le32 rss_hash; 271 __le16 fd_id; 272 __le16 vlan_tag; 273 274 union { 275 __le32 ol_info; 276 struct { 277 __le16 o_dm_vlan_id_fb; 278 __le16 ot_vlan_tag; 279 }; 280 }; 281 282 __le32 bd_base_info; 283 } rx; 284 }; 285 }; 286 287 struct hns3_desc_cb { 288 dma_addr_t dma; /* dma address of this desc */ 289 void *buf; /* cpu addr for a desc */ 290 291 /* priv data for the desc, e.g. skb when use with ip stack*/ 292 void *priv; 293 u16 page_offset; 294 u16 reuse_flag; 295 296 u32 length; /* length of the buffer */ 297 298 /* desc type, used by the ring user to mark the type of the priv data */ 299 u16 type; 300 }; 301 302 enum hns3_pkt_l3type { 303 HNS3_L3_TYPE_IPV4, 304 HNS3_L3_TYPE_IPV6, 305 HNS3_L3_TYPE_ARP, 306 HNS3_L3_TYPE_RARP, 307 HNS3_L3_TYPE_IPV4_OPT, 308 HNS3_L3_TYPE_IPV6_EXT, 309 HNS3_L3_TYPE_LLDP, 310 HNS3_L3_TYPE_BPDU, 311 HNS3_L3_TYPE_MAC_PAUSE, 312 HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/ 313 314 /* reserved for 0xA~0xB*/ 315 316 HNS3_L3_TYPE_CNM = 0xc, 317 318 /* reserved for 0xD~0xE*/ 319 320 HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */ 321 }; 322 323 enum hns3_pkt_l4type { 324 HNS3_L4_TYPE_UDP, 325 HNS3_L4_TYPE_TCP, 326 HNS3_L4_TYPE_GRE, 327 HNS3_L4_TYPE_SCTP, 328 HNS3_L4_TYPE_IGMP, 329 HNS3_L4_TYPE_ICMP, 330 331 /* reserved for 0x6~0xE */ 332 333 HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */ 334 }; 335 336 enum hns3_pkt_ol3type { 337 HNS3_OL3_TYPE_IPV4 = 0, 338 HNS3_OL3_TYPE_IPV6, 339 /* reserved for 0x2~0x3 */ 340 HNS3_OL3_TYPE_IPV4_OPT = 4, 341 HNS3_OL3_TYPE_IPV6_EXT, 342 343 /* reserved for 0x6~0xE*/ 344 345 HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */ 346 }; 347 348 enum hns3_pkt_ol4type { 349 HNS3_OL4_TYPE_NO_TUN, 350 HNS3_OL4_TYPE_MAC_IN_UDP, 351 HNS3_OL4_TYPE_NVGRE, 352 HNS3_OL4_TYPE_UNKNOWN 353 }; 354 355 struct ring_stats { 356 u64 io_err_cnt; 357 u64 sw_err_cnt; 358 u64 seg_pkt_cnt; 359 union { 360 struct { 361 u64 tx_pkts; 362 u64 tx_bytes; 363 u64 tx_err_cnt; 364 u64 restart_queue; 365 u64 tx_busy; 366 }; 367 struct { 368 u64 rx_pkts; 369 u64 rx_bytes; 370 u64 rx_err_cnt; 371 u64 reuse_pg_cnt; 372 u64 err_pkt_len; 373 u64 non_vld_descs; 374 u64 err_bd_num; 375 u64 l2_err; 376 u64 l3l4_csum_err; 377 }; 378 }; 379 }; 380 381 struct hns3_enet_ring { 382 u8 __iomem *io_base; /* base io address for the ring */ 383 struct hns3_desc *desc; /* dma map address space */ 384 struct hns3_desc_cb *desc_cb; 385 struct hns3_enet_ring *next; 386 struct hns3_enet_tqp_vector *tqp_vector; 387 struct hnae3_queue *tqp; 388 char ring_name[HNS3_RING_NAME_LEN]; 389 struct device *dev; /* will be used for DMA mapping of descriptors */ 390 391 /* statistic */ 392 struct ring_stats stats; 393 struct u64_stats_sync syncp; 394 395 dma_addr_t desc_dma_addr; 396 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 397 u16 desc_num; /* total number of desc */ 398 u16 max_desc_num_per_pkt; 399 u16 max_raw_data_sz_per_desc; 400 u16 max_pkt_size; 401 int next_to_use; /* idx of next spare desc */ 402 403 /* idx of lastest sent desc, the ring is empty when equal to 404 * next_to_use 405 */ 406 int next_to_clean; 407 408 u32 flag; /* ring attribute */ 409 int irq_init_flag; 410 411 int numa_node; 412 cpumask_t affinity_mask; 413 }; 414 415 struct hns_queue; 416 417 struct hns3_nic_ring_data { 418 struct hns3_enet_ring *ring; 419 struct napi_struct napi; 420 int queue_index; 421 int (*poll_one)(struct hns3_nic_ring_data *, int, void *); 422 void (*ex_process)(struct hns3_nic_ring_data *, struct sk_buff *); 423 void (*fini_process)(struct hns3_nic_ring_data *); 424 }; 425 426 struct hns3_nic_ops { 427 int (*fill_desc)(struct hns3_enet_ring *ring, void *priv, 428 int size, dma_addr_t dma, int frag_end, 429 enum hns_desc_type type); 430 int (*maybe_stop_tx)(struct sk_buff **out_skb, 431 int *bnum, struct hns3_enet_ring *ring); 432 void (*get_rxd_bnum)(u32 bnum_flag, int *out_bnum); 433 }; 434 435 enum hns3_flow_level_range { 436 HNS3_FLOW_LOW = 0, 437 HNS3_FLOW_MID = 1, 438 HNS3_FLOW_HIGH = 2, 439 HNS3_FLOW_ULTRA = 3, 440 }; 441 442 enum hns3_link_mode_bits { 443 HNS3_LM_FIBRE_BIT = BIT(0), 444 HNS3_LM_AUTONEG_BIT = BIT(1), 445 HNS3_LM_TP_BIT = BIT(2), 446 HNS3_LM_PAUSE_BIT = BIT(3), 447 HNS3_LM_BACKPLANE_BIT = BIT(4), 448 HNS3_LM_10BASET_HALF_BIT = BIT(5), 449 HNS3_LM_10BASET_FULL_BIT = BIT(6), 450 HNS3_LM_100BASET_HALF_BIT = BIT(7), 451 HNS3_LM_100BASET_FULL_BIT = BIT(8), 452 HNS3_LM_1000BASET_FULL_BIT = BIT(9), 453 HNS3_LM_10000BASEKR_FULL_BIT = BIT(10), 454 HNS3_LM_25000BASEKR_FULL_BIT = BIT(11), 455 HNS3_LM_40000BASELR4_FULL_BIT = BIT(12), 456 HNS3_LM_50000BASEKR2_FULL_BIT = BIT(13), 457 HNS3_LM_100000BASEKR4_FULL_BIT = BIT(14), 458 HNS3_LM_COUNT = 15 459 }; 460 461 #define HNS3_INT_GL_MAX 0x1FE0 462 #define HNS3_INT_GL_50K 0x0014 463 #define HNS3_INT_GL_20K 0x0032 464 #define HNS3_INT_GL_18K 0x0036 465 #define HNS3_INT_GL_8K 0x007C 466 467 #define HNS3_INT_RL_MAX 0x00EC 468 #define HNS3_INT_RL_ENABLE_MASK 0x40 469 470 #define HNS3_INT_ADAPT_DOWN_START 100 471 472 struct hns3_enet_coalesce { 473 u16 int_gl; 474 u8 gl_adapt_enable; 475 enum hns3_flow_level_range flow_level; 476 }; 477 478 struct hns3_enet_ring_group { 479 /* array of pointers to rings */ 480 struct hns3_enet_ring *ring; 481 u64 total_bytes; /* total bytes processed this group */ 482 u64 total_packets; /* total packets processed this group */ 483 u16 count; 484 struct hns3_enet_coalesce coal; 485 }; 486 487 struct hns3_enet_tqp_vector { 488 struct hnae3_handle *handle; 489 u8 __iomem *mask_addr; 490 int vector_irq; 491 int irq_init_flag; 492 493 u16 idx; /* index in the TQP vector array per handle. */ 494 495 struct napi_struct napi; 496 497 struct hns3_enet_ring_group rx_group; 498 struct hns3_enet_ring_group tx_group; 499 500 u16 num_tqps; /* total number of tqps in TQP vector */ 501 502 cpumask_t affinity_mask; 503 char name[HNAE3_INT_NAME_LEN]; 504 505 /* when 0 should adjust interrupt coalesce parameter */ 506 u8 int_adapt_down; 507 unsigned long last_jiffies; 508 } ____cacheline_internodealigned_in_smp; 509 510 enum hns3_udp_tnl_type { 511 HNS3_UDP_TNL_VXLAN, 512 HNS3_UDP_TNL_GENEVE, 513 HNS3_UDP_TNL_MAX, 514 }; 515 516 struct hns3_udp_tunnel { 517 u16 dst_port; 518 int used; 519 }; 520 521 struct hns3_nic_priv { 522 struct hnae3_handle *ae_handle; 523 u32 enet_ver; 524 u32 port_id; 525 struct net_device *netdev; 526 struct device *dev; 527 struct hns3_nic_ops ops; 528 529 /** 530 * the cb for nic to manage the ring buffer, the first half of the 531 * array is for tx_ring and vice versa for the second half 532 */ 533 struct hns3_nic_ring_data *ring_data; 534 struct hns3_enet_tqp_vector *tqp_vector; 535 u16 vector_num; 536 537 /* The most recently read link state */ 538 int link; 539 u64 tx_timeout_count; 540 541 unsigned long state; 542 543 struct timer_list service_timer; 544 545 struct work_struct service_task; 546 547 struct notifier_block notifier_block; 548 /* Vxlan/Geneve information */ 549 struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX]; 550 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 551 }; 552 553 union l3_hdr_info { 554 struct iphdr *v4; 555 struct ipv6hdr *v6; 556 unsigned char *hdr; 557 }; 558 559 union l4_hdr_info { 560 struct tcphdr *tcp; 561 struct udphdr *udp; 562 unsigned char *hdr; 563 }; 564 565 /* the distance between [begin, end) in a ring buffer 566 * note: there is a unuse slot between the begin and the end 567 */ 568 static inline int ring_dist(struct hns3_enet_ring *ring, int begin, int end) 569 { 570 return (end - begin + ring->desc_num) % ring->desc_num; 571 } 572 573 static inline int ring_space(struct hns3_enet_ring *ring) 574 { 575 return ring->desc_num - 576 ring_dist(ring, ring->next_to_clean, ring->next_to_use) - 1; 577 } 578 579 static inline int is_ring_empty(struct hns3_enet_ring *ring) 580 { 581 return ring->next_to_use == ring->next_to_clean; 582 } 583 584 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value) 585 { 586 u8 __iomem *reg_addr = READ_ONCE(base); 587 588 writel(value, reg_addr + reg); 589 } 590 591 #define hns3_write_dev(a, reg, value) \ 592 hns3_write_reg((a)->io_base, (reg), (value)) 593 594 #define hnae_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \ 595 (tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG) 596 597 #define ring_to_dev(ring) (&(ring)->tqp->handle->pdev->dev) 598 599 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \ 600 DMA_TO_DEVICE : DMA_FROM_DEVICE) 601 602 #define tx_ring_data(priv, idx) ((priv)->ring_data[idx]) 603 604 #define hnae_buf_size(_ring) ((_ring)->buf_size) 605 #define hnae_page_order(_ring) (get_order(hnae_buf_size(_ring))) 606 #define hnae_page_size(_ring) (PAGE_SIZE << hnae_page_order(_ring)) 607 608 /* iterator for handling rings in ring group */ 609 #define hns3_for_each_ring(pos, head) \ 610 for (pos = (head).ring; pos; pos = pos->next) 611 612 #define hns3_get_handle(ndev) \ 613 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle) 614 615 #define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1) 616 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2) 617 618 #define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2) 619 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4) 620 621 void hns3_ethtool_set_ops(struct net_device *netdev); 622 int hns3_set_channels(struct net_device *netdev, 623 struct ethtool_channels *ch); 624 625 bool hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget); 626 int hns3_init_all_ring(struct hns3_nic_priv *priv); 627 int hns3_uninit_all_ring(struct hns3_nic_priv *priv); 628 int hns3_nic_reset_all_ring(struct hnae3_handle *h); 629 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev); 630 int hns3_clean_rx_ring( 631 struct hns3_enet_ring *ring, int budget, 632 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)); 633 634 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 635 u32 gl_value); 636 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 637 u32 gl_value); 638 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 639 u32 rl_value); 640 641 #ifdef CONFIG_HNS3_DCB 642 void hns3_dcbnl_setup(struct hnae3_handle *handle); 643 #else 644 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {} 645 #endif 646 647 #endif 648