1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HNS3_ENET_H 5 #define __HNS3_ENET_H 6 7 #include <linux/if_vlan.h> 8 9 #include "hnae3.h" 10 11 #define HNS3_MOD_VERSION "1.0" 12 13 extern const char hns3_driver_version[]; 14 15 enum hns3_nic_state { 16 HNS3_NIC_STATE_TESTING, 17 HNS3_NIC_STATE_RESETTING, 18 HNS3_NIC_STATE_INITED, 19 HNS3_NIC_STATE_DOWN, 20 HNS3_NIC_STATE_DISABLED, 21 HNS3_NIC_STATE_REMOVING, 22 HNS3_NIC_STATE_SERVICE_INITED, 23 HNS3_NIC_STATE_SERVICE_SCHED, 24 HNS3_NIC_STATE2_RESET_REQUESTED, 25 HNS3_NIC_STATE_MAX 26 }; 27 28 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000 29 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004 30 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008 31 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C 32 #define HNS3_RING_RX_RING_TAIL_REG 0x00018 33 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C 34 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020 35 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C 36 37 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040 38 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044 39 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048 40 #define HNS3_RING_TX_RING_TC_REG 0x00050 41 #define HNS3_RING_TX_RING_TAIL_REG 0x00058 42 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C 43 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060 44 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064 45 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C 46 47 #define HNS3_RING_PREFETCH_EN_REG 0x0007C 48 #define HNS3_RING_CFG_VF_NUM_REG 0x00080 49 #define HNS3_RING_ASID_REG 0x0008C 50 #define HNS3_RING_EN_REG 0x00090 51 #define HNS3_RING_T0_BE_RST 0x00094 52 #define HNS3_RING_COULD_BE_RST 0x00098 53 #define HNS3_RING_WRR_WEIGHT_REG 0x0009c 54 55 #define HNS3_RING_INTMSK_RXWL_REG 0x000A0 56 #define HNS3_RING_INTSTS_RX_RING_REG 0x000A4 57 #define HNS3_RX_RING_INT_STS_REG 0x000A8 58 #define HNS3_RING_INTMSK_TXWL_REG 0x000AC 59 #define HNS3_RING_INTSTS_TX_RING_REG 0x000B0 60 #define HNS3_TX_RING_INT_STS_REG 0x000B4 61 #define HNS3_RING_INTMSK_RX_OVERTIME_REG 0x000B8 62 #define HNS3_RING_INTSTS_RX_OVERTIME_REG 0x000BC 63 #define HNS3_RING_INTMSK_TX_OVERTIME_REG 0x000C4 64 #define HNS3_RING_INTSTS_TX_OVERTIME_REG 0x000C8 65 66 #define HNS3_RING_MB_CTRL_REG 0x00100 67 #define HNS3_RING_MB_DATA_BASE_REG 0x00200 68 69 #define HNS3_TX_REG_OFFSET 0x40 70 71 #define HNS3_RX_HEAD_SIZE 256 72 73 #define HNS3_TX_TIMEOUT (5 * HZ) 74 #define HNS3_RING_NAME_LEN 16 75 #define HNS3_BUFFER_SIZE_2048 2048 76 #define HNS3_RING_MAX_PENDING 32768 77 #define HNS3_RING_MIN_PENDING 8 78 #define HNS3_RING_BD_MULTIPLE 8 79 #define HNS3_MAX_MTU 9728 80 81 #define HNS3_BD_SIZE_512_TYPE 0 82 #define HNS3_BD_SIZE_1024_TYPE 1 83 #define HNS3_BD_SIZE_2048_TYPE 2 84 #define HNS3_BD_SIZE_4096_TYPE 3 85 86 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1 87 #define HNS3_RX_FLAG_L3ID_IPV4 0x0 88 #define HNS3_RX_FLAG_L3ID_IPV6 0x1 89 #define HNS3_RX_FLAG_L4ID_UDP 0x0 90 #define HNS3_RX_FLAG_L4ID_TCP 0x1 91 92 #define HNS3_RXD_DMAC_S 0 93 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S) 94 #define HNS3_RXD_VLAN_S 2 95 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S) 96 #define HNS3_RXD_L3ID_S 4 97 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S) 98 #define HNS3_RXD_L4ID_S 8 99 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S) 100 #define HNS3_RXD_FRAG_B 12 101 #define HNS3_RXD_STRP_TAGP_S 13 102 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S) 103 104 #define HNS3_RXD_L2E_B 16 105 #define HNS3_RXD_L3E_B 17 106 #define HNS3_RXD_L4E_B 18 107 #define HNS3_RXD_TRUNCAT_B 19 108 #define HNS3_RXD_HOI_B 20 109 #define HNS3_RXD_DOI_B 21 110 #define HNS3_RXD_OL3E_B 22 111 #define HNS3_RXD_OL4E_B 23 112 113 #define HNS3_RXD_ODMAC_S 0 114 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S) 115 #define HNS3_RXD_OVLAN_S 2 116 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S) 117 #define HNS3_RXD_OL3ID_S 4 118 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S) 119 #define HNS3_RXD_OL4ID_S 8 120 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S) 121 #define HNS3_RXD_FBHI_S 12 122 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S) 123 #define HNS3_RXD_FBLI_S 14 124 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S) 125 126 #define HNS3_RXD_BDTYPE_S 0 127 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S) 128 #define HNS3_RXD_VLD_B 4 129 #define HNS3_RXD_UDP0_B 5 130 #define HNS3_RXD_EXTEND_B 7 131 #define HNS3_RXD_FE_B 8 132 #define HNS3_RXD_LUM_B 9 133 #define HNS3_RXD_CRCP_B 10 134 #define HNS3_RXD_L3L4P_B 11 135 #define HNS3_RXD_TSIND_S 12 136 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S) 137 #define HNS3_RXD_LKBK_B 15 138 #define HNS3_RXD_HDL_S 16 139 #define HNS3_RXD_HDL_M (0x7ff << HNS3_RXD_HDL_S) 140 #define HNS3_RXD_HSIND_B 31 141 142 #define HNS3_TXD_L3T_S 0 143 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S) 144 #define HNS3_TXD_L4T_S 2 145 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S) 146 #define HNS3_TXD_L3CS_B 4 147 #define HNS3_TXD_L4CS_B 5 148 #define HNS3_TXD_VLAN_B 6 149 #define HNS3_TXD_TSO_B 7 150 151 #define HNS3_TXD_L2LEN_S 8 152 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S) 153 #define HNS3_TXD_L3LEN_S 16 154 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S) 155 #define HNS3_TXD_L4LEN_S 24 156 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S) 157 158 #define HNS3_TXD_OL3T_S 0 159 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S) 160 #define HNS3_TXD_OVLAN_B 2 161 #define HNS3_TXD_MACSEC_B 3 162 #define HNS3_TXD_TUNTYPE_S 4 163 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S) 164 165 #define HNS3_TXD_BDTYPE_S 0 166 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S) 167 #define HNS3_TXD_FE_B 4 168 #define HNS3_TXD_SC_S 5 169 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S) 170 #define HNS3_TXD_EXTEND_B 7 171 #define HNS3_TXD_VLD_B 8 172 #define HNS3_TXD_RI_B 9 173 #define HNS3_TXD_RA_B 10 174 #define HNS3_TXD_TSYN_B 11 175 #define HNS3_TXD_DECTTL_S 12 176 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S) 177 178 #define HNS3_TXD_MSS_S 0 179 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) 180 181 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0) 182 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1) 183 184 #define HNS3_VECTOR_NOT_INITED 0 185 #define HNS3_VECTOR_INITED 1 186 187 #define HNS3_MAX_BD_SIZE 65535 188 #define HNS3_MAX_BD_PER_FRAG 8 189 #define HNS3_MAX_BD_PER_PKT MAX_SKB_FRAGS 190 191 #define HNS3_VECTOR_GL0_OFFSET 0x100 192 #define HNS3_VECTOR_GL1_OFFSET 0x200 193 #define HNS3_VECTOR_GL2_OFFSET 0x300 194 #define HNS3_VECTOR_RL_OFFSET 0x900 195 #define HNS3_VECTOR_RL_EN_B 6 196 197 #define HNS3_RING_EN_B 0 198 199 enum hns3_pkt_l3t_type { 200 HNS3_L3T_NONE, 201 HNS3_L3T_IPV6, 202 HNS3_L3T_IPV4, 203 HNS3_L3T_RESERVED 204 }; 205 206 enum hns3_pkt_l4t_type { 207 HNS3_L4T_UNKNOWN, 208 HNS3_L4T_TCP, 209 HNS3_L4T_UDP, 210 HNS3_L4T_SCTP 211 }; 212 213 enum hns3_pkt_ol3t_type { 214 HNS3_OL3T_NONE, 215 HNS3_OL3T_IPV6, 216 HNS3_OL3T_IPV4_NO_CSUM, 217 HNS3_OL3T_IPV4_CSUM 218 }; 219 220 enum hns3_pkt_tun_type { 221 HNS3_TUN_NONE, 222 HNS3_TUN_MAC_IN_UDP, 223 HNS3_TUN_NVGRE, 224 HNS3_TUN_OTHER 225 }; 226 227 /* hardware spec ring buffer format */ 228 struct __packed hns3_desc { 229 __le64 addr; 230 union { 231 struct { 232 __le16 vlan_tag; 233 __le16 send_size; 234 union { 235 __le32 type_cs_vlan_tso_len; 236 struct { 237 __u8 type_cs_vlan_tso; 238 __u8 l2_len; 239 __u8 l3_len; 240 __u8 l4_len; 241 }; 242 }; 243 __le16 outer_vlan_tag; 244 __le16 tv; 245 246 union { 247 __le32 ol_type_vlan_len_msec; 248 struct { 249 __u8 ol_type_vlan_msec; 250 __u8 ol2_len; 251 __u8 ol3_len; 252 __u8 ol4_len; 253 }; 254 }; 255 256 __le32 paylen; 257 __le16 bdtp_fe_sc_vld_ra_ri; 258 __le16 mss; 259 } tx; 260 261 struct { 262 __le32 l234_info; 263 __le16 pkt_len; 264 __le16 size; 265 266 __le32 rss_hash; 267 __le16 fd_id; 268 __le16 vlan_tag; 269 270 union { 271 __le32 ol_info; 272 struct { 273 __le16 o_dm_vlan_id_fb; 274 __le16 ot_vlan_tag; 275 }; 276 }; 277 278 __le32 bd_base_info; 279 } rx; 280 }; 281 }; 282 283 struct hns3_desc_cb { 284 dma_addr_t dma; /* dma address of this desc */ 285 void *buf; /* cpu addr for a desc */ 286 287 /* priv data for the desc, e.g. skb when use with ip stack*/ 288 void *priv; 289 u32 page_offset; 290 u32 length; /* length of the buffer */ 291 292 u16 reuse_flag; 293 294 /* desc type, used by the ring user to mark the type of the priv data */ 295 u16 type; 296 }; 297 298 enum hns3_pkt_l3type { 299 HNS3_L3_TYPE_IPV4, 300 HNS3_L3_TYPE_IPV6, 301 HNS3_L3_TYPE_ARP, 302 HNS3_L3_TYPE_RARP, 303 HNS3_L3_TYPE_IPV4_OPT, 304 HNS3_L3_TYPE_IPV6_EXT, 305 HNS3_L3_TYPE_LLDP, 306 HNS3_L3_TYPE_BPDU, 307 HNS3_L3_TYPE_MAC_PAUSE, 308 HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/ 309 310 /* reserved for 0xA~0xB*/ 311 312 HNS3_L3_TYPE_CNM = 0xc, 313 314 /* reserved for 0xD~0xE*/ 315 316 HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */ 317 }; 318 319 enum hns3_pkt_l4type { 320 HNS3_L4_TYPE_UDP, 321 HNS3_L4_TYPE_TCP, 322 HNS3_L4_TYPE_GRE, 323 HNS3_L4_TYPE_SCTP, 324 HNS3_L4_TYPE_IGMP, 325 HNS3_L4_TYPE_ICMP, 326 327 /* reserved for 0x6~0xE */ 328 329 HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */ 330 }; 331 332 enum hns3_pkt_ol3type { 333 HNS3_OL3_TYPE_IPV4 = 0, 334 HNS3_OL3_TYPE_IPV6, 335 /* reserved for 0x2~0x3 */ 336 HNS3_OL3_TYPE_IPV4_OPT = 4, 337 HNS3_OL3_TYPE_IPV6_EXT, 338 339 /* reserved for 0x6~0xE*/ 340 341 HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */ 342 }; 343 344 enum hns3_pkt_ol4type { 345 HNS3_OL4_TYPE_NO_TUN, 346 HNS3_OL4_TYPE_MAC_IN_UDP, 347 HNS3_OL4_TYPE_NVGRE, 348 HNS3_OL4_TYPE_UNKNOWN 349 }; 350 351 struct ring_stats { 352 u64 io_err_cnt; 353 u64 sw_err_cnt; 354 u64 seg_pkt_cnt; 355 union { 356 struct { 357 u64 tx_pkts; 358 u64 tx_bytes; 359 u64 tx_err_cnt; 360 u64 restart_queue; 361 u64 tx_busy; 362 }; 363 struct { 364 u64 rx_pkts; 365 u64 rx_bytes; 366 u64 rx_err_cnt; 367 u64 reuse_pg_cnt; 368 u64 err_pkt_len; 369 u64 non_vld_descs; 370 u64 err_bd_num; 371 u64 l2_err; 372 u64 l3l4_csum_err; 373 }; 374 }; 375 }; 376 377 struct hns3_enet_ring { 378 u8 __iomem *io_base; /* base io address for the ring */ 379 struct hns3_desc *desc; /* dma map address space */ 380 struct hns3_desc_cb *desc_cb; 381 struct hns3_enet_ring *next; 382 struct hns3_enet_tqp_vector *tqp_vector; 383 struct hnae3_queue *tqp; 384 char ring_name[HNS3_RING_NAME_LEN]; 385 struct device *dev; /* will be used for DMA mapping of descriptors */ 386 387 /* statistic */ 388 struct ring_stats stats; 389 struct u64_stats_sync syncp; 390 391 dma_addr_t desc_dma_addr; 392 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 393 u16 desc_num; /* total number of desc */ 394 u16 max_desc_num_per_pkt; 395 u16 max_raw_data_sz_per_desc; 396 u16 max_pkt_size; 397 int next_to_use; /* idx of next spare desc */ 398 399 /* idx of lastest sent desc, the ring is empty when equal to 400 * next_to_use 401 */ 402 int next_to_clean; 403 404 u32 flag; /* ring attribute */ 405 int irq_init_flag; 406 407 int numa_node; 408 cpumask_t affinity_mask; 409 }; 410 411 struct hns_queue; 412 413 struct hns3_nic_ring_data { 414 struct hns3_enet_ring *ring; 415 struct napi_struct napi; 416 int queue_index; 417 int (*poll_one)(struct hns3_nic_ring_data *, int, void *); 418 void (*ex_process)(struct hns3_nic_ring_data *, struct sk_buff *); 419 void (*fini_process)(struct hns3_nic_ring_data *); 420 }; 421 422 struct hns3_nic_ops { 423 int (*fill_desc)(struct hns3_enet_ring *ring, void *priv, 424 int size, int frag_end, enum hns_desc_type type); 425 int (*maybe_stop_tx)(struct sk_buff **out_skb, 426 int *bnum, struct hns3_enet_ring *ring); 427 void (*get_rxd_bnum)(u32 bnum_flag, int *out_bnum); 428 }; 429 430 enum hns3_flow_level_range { 431 HNS3_FLOW_LOW = 0, 432 HNS3_FLOW_MID = 1, 433 HNS3_FLOW_HIGH = 2, 434 HNS3_FLOW_ULTRA = 3, 435 }; 436 437 enum hns3_link_mode_bits { 438 HNS3_LM_FIBRE_BIT = BIT(0), 439 HNS3_LM_AUTONEG_BIT = BIT(1), 440 HNS3_LM_TP_BIT = BIT(2), 441 HNS3_LM_PAUSE_BIT = BIT(3), 442 HNS3_LM_BACKPLANE_BIT = BIT(4), 443 HNS3_LM_10BASET_HALF_BIT = BIT(5), 444 HNS3_LM_10BASET_FULL_BIT = BIT(6), 445 HNS3_LM_100BASET_HALF_BIT = BIT(7), 446 HNS3_LM_100BASET_FULL_BIT = BIT(8), 447 HNS3_LM_1000BASET_FULL_BIT = BIT(9), 448 HNS3_LM_10000BASEKR_FULL_BIT = BIT(10), 449 HNS3_LM_25000BASEKR_FULL_BIT = BIT(11), 450 HNS3_LM_40000BASELR4_FULL_BIT = BIT(12), 451 HNS3_LM_50000BASEKR2_FULL_BIT = BIT(13), 452 HNS3_LM_100000BASEKR4_FULL_BIT = BIT(14), 453 HNS3_LM_COUNT = 15 454 }; 455 456 #define HNS3_INT_GL_MAX 0x1FE0 457 #define HNS3_INT_GL_50K 0x0014 458 #define HNS3_INT_GL_20K 0x0032 459 #define HNS3_INT_GL_18K 0x0036 460 #define HNS3_INT_GL_8K 0x007C 461 462 #define HNS3_INT_RL_MAX 0x00EC 463 #define HNS3_INT_RL_ENABLE_MASK 0x40 464 465 #define HNS3_INT_ADAPT_DOWN_START 100 466 467 struct hns3_enet_coalesce { 468 u16 int_gl; 469 u8 gl_adapt_enable; 470 enum hns3_flow_level_range flow_level; 471 }; 472 473 struct hns3_enet_ring_group { 474 /* array of pointers to rings */ 475 struct hns3_enet_ring *ring; 476 u64 total_bytes; /* total bytes processed this group */ 477 u64 total_packets; /* total packets processed this group */ 478 u16 count; 479 struct hns3_enet_coalesce coal; 480 }; 481 482 struct hns3_enet_tqp_vector { 483 struct hnae3_handle *handle; 484 u8 __iomem *mask_addr; 485 int vector_irq; 486 int irq_init_flag; 487 488 u16 idx; /* index in the TQP vector array per handle. */ 489 490 struct napi_struct napi; 491 492 struct hns3_enet_ring_group rx_group; 493 struct hns3_enet_ring_group tx_group; 494 495 cpumask_t affinity_mask; 496 u16 num_tqps; /* total number of tqps in TQP vector */ 497 struct irq_affinity_notify affinity_notify; 498 499 char name[HNAE3_INT_NAME_LEN]; 500 501 /* when 0 should adjust interrupt coalesce parameter */ 502 u8 int_adapt_down; 503 unsigned long last_jiffies; 504 } ____cacheline_internodealigned_in_smp; 505 506 enum hns3_udp_tnl_type { 507 HNS3_UDP_TNL_VXLAN, 508 HNS3_UDP_TNL_GENEVE, 509 HNS3_UDP_TNL_MAX, 510 }; 511 512 struct hns3_udp_tunnel { 513 u16 dst_port; 514 int used; 515 }; 516 517 struct hns3_nic_priv { 518 struct hnae3_handle *ae_handle; 519 u32 enet_ver; 520 u32 port_id; 521 struct net_device *netdev; 522 struct device *dev; 523 struct hns3_nic_ops ops; 524 525 /** 526 * the cb for nic to manage the ring buffer, the first half of the 527 * array is for tx_ring and vice versa for the second half 528 */ 529 struct hns3_nic_ring_data *ring_data; 530 struct hns3_enet_tqp_vector *tqp_vector; 531 u16 vector_num; 532 533 /* The most recently read link state */ 534 int link; 535 u64 tx_timeout_count; 536 537 unsigned long state; 538 539 struct timer_list service_timer; 540 541 struct work_struct service_task; 542 543 struct notifier_block notifier_block; 544 /* Vxlan/Geneve information */ 545 struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX]; 546 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 547 struct hns3_enet_coalesce tx_coal; 548 struct hns3_enet_coalesce rx_coal; 549 }; 550 551 union l3_hdr_info { 552 struct iphdr *v4; 553 struct ipv6hdr *v6; 554 unsigned char *hdr; 555 }; 556 557 union l4_hdr_info { 558 struct tcphdr *tcp; 559 struct udphdr *udp; 560 unsigned char *hdr; 561 }; 562 563 /* the distance between [begin, end) in a ring buffer 564 * note: there is a unuse slot between the begin and the end 565 */ 566 static inline int ring_dist(struct hns3_enet_ring *ring, int begin, int end) 567 { 568 return (end - begin + ring->desc_num) % ring->desc_num; 569 } 570 571 static inline int ring_space(struct hns3_enet_ring *ring) 572 { 573 return ring->desc_num - 574 ring_dist(ring, ring->next_to_clean, ring->next_to_use) - 1; 575 } 576 577 static inline int is_ring_empty(struct hns3_enet_ring *ring) 578 { 579 return ring->next_to_use == ring->next_to_clean; 580 } 581 582 static inline u32 hns3_read_reg(void __iomem *base, u32 reg) 583 { 584 return readl(base + reg); 585 } 586 587 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value) 588 { 589 u8 __iomem *reg_addr = READ_ONCE(base); 590 591 writel(value, reg_addr + reg); 592 } 593 594 static inline bool hns3_dev_ongoing_func_reset(struct hnae3_ae_dev *ae_dev) 595 { 596 return (ae_dev && (ae_dev->reset_type == HNAE3_FUNC_RESET)); 597 } 598 599 #define hns3_read_dev(a, reg) \ 600 hns3_read_reg((a)->io_base, (reg)) 601 602 static inline bool hns3_nic_resetting(struct net_device *netdev) 603 { 604 struct hns3_nic_priv *priv = netdev_priv(netdev); 605 606 return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 607 } 608 609 #define hns3_write_dev(a, reg, value) \ 610 hns3_write_reg((a)->io_base, (reg), (value)) 611 612 #define hnae3_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \ 613 (tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG) 614 615 #define ring_to_dev(ring) (&(ring)->tqp->handle->pdev->dev) 616 617 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \ 618 DMA_TO_DEVICE : DMA_FROM_DEVICE) 619 620 #define tx_ring_data(priv, idx) ((priv)->ring_data[idx]) 621 622 #define hnae3_buf_size(_ring) ((_ring)->buf_size) 623 #define hnae3_page_order(_ring) (get_order(hnae3_buf_size(_ring))) 624 #define hnae3_page_size(_ring) (PAGE_SIZE << hnae3_page_order(_ring)) 625 626 /* iterator for handling rings in ring group */ 627 #define hns3_for_each_ring(pos, head) \ 628 for (pos = (head).ring; pos; pos = pos->next) 629 630 #define hns3_get_handle(ndev) \ 631 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle) 632 633 #define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1) 634 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2) 635 636 #define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2) 637 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4) 638 639 void hns3_ethtool_set_ops(struct net_device *netdev); 640 int hns3_set_channels(struct net_device *netdev, 641 struct ethtool_channels *ch); 642 643 void hns3_clean_tx_ring(struct hns3_enet_ring *ring); 644 int hns3_init_all_ring(struct hns3_nic_priv *priv); 645 int hns3_uninit_all_ring(struct hns3_nic_priv *priv); 646 int hns3_nic_reset_all_ring(struct hnae3_handle *h); 647 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev); 648 int hns3_clean_rx_ring( 649 struct hns3_enet_ring *ring, int budget, 650 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)); 651 652 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 653 u32 gl_value); 654 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 655 u32 gl_value); 656 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 657 u32 rl_value); 658 659 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable); 660 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags); 661 662 #ifdef CONFIG_HNS3_DCB 663 void hns3_dcbnl_setup(struct hnae3_handle *handle); 664 #else 665 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {} 666 #endif 667 668 #endif 669