1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #ifdef CONFIG_RFS_ACCEL 8 #include <linux/cpu_rmap.h> 9 #endif 10 #include <linux/if_vlan.h> 11 #include <linux/irq.h> 12 #include <linux/ip.h> 13 #include <linux/ipv6.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/aer.h> 17 #include <linux/skbuff.h> 18 #include <linux/sctp.h> 19 #include <net/gre.h> 20 #include <net/ip6_checksum.h> 21 #include <net/pkt_cls.h> 22 #include <net/tcp.h> 23 #include <net/vxlan.h> 24 #include <net/geneve.h> 25 26 #include "hnae3.h" 27 #include "hns3_enet.h" 28 /* All hns3 tracepoints are defined by the include below, which 29 * must be included exactly once across the whole kernel with 30 * CREATE_TRACE_POINTS defined 31 */ 32 #define CREATE_TRACE_POINTS 33 #include "hns3_trace.h" 34 35 #define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift))) 36 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE) 37 38 #define hns3_rl_err(fmt, ...) \ 39 do { \ 40 if (net_ratelimit()) \ 41 netdev_err(fmt, ##__VA_ARGS__); \ 42 } while (0) 43 44 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force); 45 46 static const char hns3_driver_name[] = "hns3"; 47 static const char hns3_driver_string[] = 48 "Hisilicon Ethernet Network Driver for Hip08 Family"; 49 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 50 static struct hnae3_client client; 51 52 static int debug = -1; 53 module_param(debug, int, 0); 54 MODULE_PARM_DESC(debug, " Network interface message level setting"); 55 56 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 57 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) 58 59 #define HNS3_INNER_VLAN_TAG 1 60 #define HNS3_OUTER_VLAN_TAG 2 61 62 #define HNS3_MIN_TX_LEN 33U 63 64 /* hns3_pci_tbl - PCI Device ID Table 65 * 66 * Last entry must be all 0s 67 * 68 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 69 * Class, Class Mask, private data (not used) } 70 */ 71 static const struct pci_device_id hns3_pci_tbl[] = { 72 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 75 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 77 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 79 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 80 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 81 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 83 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 84 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 85 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 86 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 88 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 89 /* required last entry */ 90 {0, } 91 }; 92 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 93 94 static irqreturn_t hns3_irq_handle(int irq, void *vector) 95 { 96 struct hns3_enet_tqp_vector *tqp_vector = vector; 97 98 napi_schedule_irqoff(&tqp_vector->napi); 99 100 return IRQ_HANDLED; 101 } 102 103 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 104 { 105 struct hns3_enet_tqp_vector *tqp_vectors; 106 unsigned int i; 107 108 for (i = 0; i < priv->vector_num; i++) { 109 tqp_vectors = &priv->tqp_vector[i]; 110 111 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 112 continue; 113 114 /* clear the affinity mask */ 115 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 116 117 /* release the irq resource */ 118 free_irq(tqp_vectors->vector_irq, tqp_vectors); 119 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 120 } 121 } 122 123 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 124 { 125 struct hns3_enet_tqp_vector *tqp_vectors; 126 int txrx_int_idx = 0; 127 int rx_int_idx = 0; 128 int tx_int_idx = 0; 129 unsigned int i; 130 int ret; 131 132 for (i = 0; i < priv->vector_num; i++) { 133 tqp_vectors = &priv->tqp_vector[i]; 134 135 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 136 continue; 137 138 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 139 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 140 "%s-%s-%s-%d", hns3_driver_name, 141 pci_name(priv->ae_handle->pdev), 142 "TxRx", txrx_int_idx++); 143 txrx_int_idx++; 144 } else if (tqp_vectors->rx_group.ring) { 145 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 146 "%s-%s-%s-%d", hns3_driver_name, 147 pci_name(priv->ae_handle->pdev), 148 "Rx", rx_int_idx++); 149 } else if (tqp_vectors->tx_group.ring) { 150 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 151 "%s-%s-%s-%d", hns3_driver_name, 152 pci_name(priv->ae_handle->pdev), 153 "Tx", tx_int_idx++); 154 } else { 155 /* Skip this unused q_vector */ 156 continue; 157 } 158 159 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 160 161 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN); 162 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 163 tqp_vectors->name, tqp_vectors); 164 if (ret) { 165 netdev_err(priv->netdev, "request irq(%d) fail\n", 166 tqp_vectors->vector_irq); 167 hns3_nic_uninit_irq(priv); 168 return ret; 169 } 170 171 irq_set_affinity_hint(tqp_vectors->vector_irq, 172 &tqp_vectors->affinity_mask); 173 174 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 175 } 176 177 return 0; 178 } 179 180 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 181 u32 mask_en) 182 { 183 writel(mask_en, tqp_vector->mask_addr); 184 } 185 186 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 187 { 188 napi_enable(&tqp_vector->napi); 189 enable_irq(tqp_vector->vector_irq); 190 191 /* enable vector */ 192 hns3_mask_vector_irq(tqp_vector, 1); 193 } 194 195 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 196 { 197 /* disable vector */ 198 hns3_mask_vector_irq(tqp_vector, 0); 199 200 disable_irq(tqp_vector->vector_irq); 201 napi_disable(&tqp_vector->napi); 202 } 203 204 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 205 u32 rl_value) 206 { 207 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 208 209 /* this defines the configuration for RL (Interrupt Rate Limiter). 210 * Rl defines rate of interrupts i.e. number of interrupts-per-second 211 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 212 */ 213 214 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable && 215 !tqp_vector->rx_group.coal.adapt_enable) 216 /* According to the hardware, the range of rl_reg is 217 * 0-59 and the unit is 4. 218 */ 219 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 220 221 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 222 } 223 224 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 225 u32 gl_value) 226 { 227 u32 new_val; 228 229 if (tqp_vector->rx_group.coal.unit_1us) 230 new_val = gl_value | HNS3_INT_GL_1US; 231 else 232 new_val = hns3_gl_usec_to_reg(gl_value); 233 234 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 235 } 236 237 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 238 u32 gl_value) 239 { 240 u32 new_val; 241 242 if (tqp_vector->tx_group.coal.unit_1us) 243 new_val = gl_value | HNS3_INT_GL_1US; 244 else 245 new_val = hns3_gl_usec_to_reg(gl_value); 246 247 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 248 } 249 250 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector, 251 u32 ql_value) 252 { 253 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET); 254 } 255 256 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector, 257 u32 ql_value) 258 { 259 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET); 260 } 261 262 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector, 263 struct hns3_nic_priv *priv) 264 { 265 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 266 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 267 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 268 269 /* initialize the configuration for interrupt coalescing. 270 * 1. GL (Interrupt Gap Limiter) 271 * 2. RL (Interrupt Rate Limiter) 272 * 3. QL (Interrupt Quantity Limiter) 273 * 274 * Default: enable interrupt coalescing self-adaptive and GL 275 */ 276 tx_coal->adapt_enable = 1; 277 rx_coal->adapt_enable = 1; 278 279 tx_coal->int_gl = HNS3_INT_GL_50K; 280 rx_coal->int_gl = HNS3_INT_GL_50K; 281 282 rx_coal->flow_level = HNS3_FLOW_LOW; 283 tx_coal->flow_level = HNS3_FLOW_LOW; 284 285 /* device version above V3(include V3), GL can configure 1us 286 * unit, so uses 1us unit. 287 */ 288 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) { 289 tx_coal->unit_1us = 1; 290 rx_coal->unit_1us = 1; 291 } 292 293 if (ae_dev->dev_specs.int_ql_max) { 294 tx_coal->ql_enable = 1; 295 rx_coal->ql_enable = 1; 296 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 297 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 298 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 299 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 300 } 301 } 302 303 static void 304 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 305 struct hns3_nic_priv *priv) 306 { 307 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 308 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 309 struct hnae3_handle *h = priv->ae_handle; 310 311 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl); 312 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl); 313 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 314 315 if (tx_coal->ql_enable) 316 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql); 317 318 if (rx_coal->ql_enable) 319 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql); 320 } 321 322 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 323 { 324 struct hnae3_handle *h = hns3_get_handle(netdev); 325 struct hnae3_knic_private_info *kinfo = &h->kinfo; 326 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc; 327 int i, ret; 328 329 if (kinfo->num_tc <= 1) { 330 netdev_reset_tc(netdev); 331 } else { 332 ret = netdev_set_num_tc(netdev, kinfo->num_tc); 333 if (ret) { 334 netdev_err(netdev, 335 "netdev_set_num_tc fail, ret=%d!\n", ret); 336 return ret; 337 } 338 339 for (i = 0; i < HNAE3_MAX_TC; i++) { 340 if (!kinfo->tc_info[i].enable) 341 continue; 342 343 netdev_set_tc_queue(netdev, 344 kinfo->tc_info[i].tc, 345 kinfo->tc_info[i].tqp_count, 346 kinfo->tc_info[i].tqp_offset); 347 } 348 } 349 350 ret = netif_set_real_num_tx_queues(netdev, queue_size); 351 if (ret) { 352 netdev_err(netdev, 353 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret); 354 return ret; 355 } 356 357 ret = netif_set_real_num_rx_queues(netdev, queue_size); 358 if (ret) { 359 netdev_err(netdev, 360 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 361 return ret; 362 } 363 364 return 0; 365 } 366 367 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 368 { 369 u16 alloc_tqps, max_rss_size, rss_size; 370 371 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 372 rss_size = alloc_tqps / h->kinfo.num_tc; 373 374 return min_t(u16, rss_size, max_rss_size); 375 } 376 377 static void hns3_tqp_enable(struct hnae3_queue *tqp) 378 { 379 u32 rcb_reg; 380 381 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 382 rcb_reg |= BIT(HNS3_RING_EN_B); 383 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 384 } 385 386 static void hns3_tqp_disable(struct hnae3_queue *tqp) 387 { 388 u32 rcb_reg; 389 390 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 391 rcb_reg &= ~BIT(HNS3_RING_EN_B); 392 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 393 } 394 395 static void hns3_free_rx_cpu_rmap(struct net_device *netdev) 396 { 397 #ifdef CONFIG_RFS_ACCEL 398 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 399 netdev->rx_cpu_rmap = NULL; 400 #endif 401 } 402 403 static int hns3_set_rx_cpu_rmap(struct net_device *netdev) 404 { 405 #ifdef CONFIG_RFS_ACCEL 406 struct hns3_nic_priv *priv = netdev_priv(netdev); 407 struct hns3_enet_tqp_vector *tqp_vector; 408 int i, ret; 409 410 if (!netdev->rx_cpu_rmap) { 411 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num); 412 if (!netdev->rx_cpu_rmap) 413 return -ENOMEM; 414 } 415 416 for (i = 0; i < priv->vector_num; i++) { 417 tqp_vector = &priv->tqp_vector[i]; 418 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap, 419 tqp_vector->vector_irq); 420 if (ret) { 421 hns3_free_rx_cpu_rmap(netdev); 422 return ret; 423 } 424 } 425 #endif 426 return 0; 427 } 428 429 static int hns3_nic_net_up(struct net_device *netdev) 430 { 431 struct hns3_nic_priv *priv = netdev_priv(netdev); 432 struct hnae3_handle *h = priv->ae_handle; 433 int i, j; 434 int ret; 435 436 ret = hns3_nic_reset_all_ring(h); 437 if (ret) 438 return ret; 439 440 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 441 442 /* enable the vectors */ 443 for (i = 0; i < priv->vector_num; i++) 444 hns3_vector_enable(&priv->tqp_vector[i]); 445 446 /* enable rcb */ 447 for (j = 0; j < h->kinfo.num_tqps; j++) 448 hns3_tqp_enable(h->kinfo.tqp[j]); 449 450 /* start the ae_dev */ 451 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 452 if (ret) { 453 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 454 while (j--) 455 hns3_tqp_disable(h->kinfo.tqp[j]); 456 457 for (j = i - 1; j >= 0; j--) 458 hns3_vector_disable(&priv->tqp_vector[j]); 459 } 460 461 return ret; 462 } 463 464 static void hns3_config_xps(struct hns3_nic_priv *priv) 465 { 466 int i; 467 468 for (i = 0; i < priv->vector_num; i++) { 469 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 470 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 471 472 while (ring) { 473 int ret; 474 475 ret = netif_set_xps_queue(priv->netdev, 476 &tqp_vector->affinity_mask, 477 ring->tqp->tqp_index); 478 if (ret) 479 netdev_warn(priv->netdev, 480 "set xps queue failed: %d", ret); 481 482 ring = ring->next; 483 } 484 } 485 } 486 487 static int hns3_nic_net_open(struct net_device *netdev) 488 { 489 struct hns3_nic_priv *priv = netdev_priv(netdev); 490 struct hnae3_handle *h = hns3_get_handle(netdev); 491 struct hnae3_knic_private_info *kinfo; 492 int i, ret; 493 494 if (hns3_nic_resetting(netdev)) 495 return -EBUSY; 496 497 netif_carrier_off(netdev); 498 499 ret = hns3_nic_set_real_num_queue(netdev); 500 if (ret) 501 return ret; 502 503 ret = hns3_nic_net_up(netdev); 504 if (ret) { 505 netdev_err(netdev, "net up fail, ret=%d!\n", ret); 506 return ret; 507 } 508 509 kinfo = &h->kinfo; 510 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 511 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]); 512 513 if (h->ae_algo->ops->set_timer_task) 514 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 515 516 hns3_config_xps(priv); 517 518 netif_dbg(h, drv, netdev, "net open\n"); 519 520 return 0; 521 } 522 523 static void hns3_reset_tx_queue(struct hnae3_handle *h) 524 { 525 struct net_device *ndev = h->kinfo.netdev; 526 struct hns3_nic_priv *priv = netdev_priv(ndev); 527 struct netdev_queue *dev_queue; 528 u32 i; 529 530 for (i = 0; i < h->kinfo.num_tqps; i++) { 531 dev_queue = netdev_get_tx_queue(ndev, 532 priv->ring[i].queue_index); 533 netdev_tx_reset_queue(dev_queue); 534 } 535 } 536 537 static void hns3_nic_net_down(struct net_device *netdev) 538 { 539 struct hns3_nic_priv *priv = netdev_priv(netdev); 540 struct hnae3_handle *h = hns3_get_handle(netdev); 541 const struct hnae3_ae_ops *ops; 542 int i; 543 544 /* disable vectors */ 545 for (i = 0; i < priv->vector_num; i++) 546 hns3_vector_disable(&priv->tqp_vector[i]); 547 548 /* disable rcb */ 549 for (i = 0; i < h->kinfo.num_tqps; i++) 550 hns3_tqp_disable(h->kinfo.tqp[i]); 551 552 /* stop ae_dev */ 553 ops = priv->ae_handle->ae_algo->ops; 554 if (ops->stop) 555 ops->stop(priv->ae_handle); 556 557 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 558 * during reset process, because driver may not be able 559 * to disable the ring through firmware when downing the netdev. 560 */ 561 if (!hns3_nic_resetting(netdev)) 562 hns3_clear_all_ring(priv->ae_handle, false); 563 564 hns3_reset_tx_queue(priv->ae_handle); 565 } 566 567 static int hns3_nic_net_stop(struct net_device *netdev) 568 { 569 struct hns3_nic_priv *priv = netdev_priv(netdev); 570 struct hnae3_handle *h = hns3_get_handle(netdev); 571 572 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 573 return 0; 574 575 netif_dbg(h, drv, netdev, "net stop\n"); 576 577 if (h->ae_algo->ops->set_timer_task) 578 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 579 580 netif_tx_stop_all_queues(netdev); 581 netif_carrier_off(netdev); 582 583 hns3_nic_net_down(netdev); 584 585 return 0; 586 } 587 588 static int hns3_nic_uc_sync(struct net_device *netdev, 589 const unsigned char *addr) 590 { 591 struct hnae3_handle *h = hns3_get_handle(netdev); 592 593 if (h->ae_algo->ops->add_uc_addr) 594 return h->ae_algo->ops->add_uc_addr(h, addr); 595 596 return 0; 597 } 598 599 static int hns3_nic_uc_unsync(struct net_device *netdev, 600 const unsigned char *addr) 601 { 602 struct hnae3_handle *h = hns3_get_handle(netdev); 603 604 /* need ignore the request of removing device address, because 605 * we store the device address and other addresses of uc list 606 * in the function's mac filter list. 607 */ 608 if (ether_addr_equal(addr, netdev->dev_addr)) 609 return 0; 610 611 if (h->ae_algo->ops->rm_uc_addr) 612 return h->ae_algo->ops->rm_uc_addr(h, addr); 613 614 return 0; 615 } 616 617 static int hns3_nic_mc_sync(struct net_device *netdev, 618 const unsigned char *addr) 619 { 620 struct hnae3_handle *h = hns3_get_handle(netdev); 621 622 if (h->ae_algo->ops->add_mc_addr) 623 return h->ae_algo->ops->add_mc_addr(h, addr); 624 625 return 0; 626 } 627 628 static int hns3_nic_mc_unsync(struct net_device *netdev, 629 const unsigned char *addr) 630 { 631 struct hnae3_handle *h = hns3_get_handle(netdev); 632 633 if (h->ae_algo->ops->rm_mc_addr) 634 return h->ae_algo->ops->rm_mc_addr(h, addr); 635 636 return 0; 637 } 638 639 static u8 hns3_get_netdev_flags(struct net_device *netdev) 640 { 641 u8 flags = 0; 642 643 if (netdev->flags & IFF_PROMISC) { 644 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 645 } else { 646 flags |= HNAE3_VLAN_FLTR; 647 if (netdev->flags & IFF_ALLMULTI) 648 flags |= HNAE3_USER_MPE; 649 } 650 651 return flags; 652 } 653 654 static void hns3_nic_set_rx_mode(struct net_device *netdev) 655 { 656 struct hnae3_handle *h = hns3_get_handle(netdev); 657 u8 new_flags; 658 659 new_flags = hns3_get_netdev_flags(netdev); 660 661 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 662 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync); 663 664 /* User mode Promisc mode enable and vlan filtering is disabled to 665 * let all packets in. 666 */ 667 h->netdev_flags = new_flags; 668 hns3_request_update_promisc_mode(h); 669 } 670 671 void hns3_request_update_promisc_mode(struct hnae3_handle *handle) 672 { 673 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 674 675 if (ops->request_update_promisc_mode) 676 ops->request_update_promisc_mode(handle); 677 } 678 679 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable) 680 { 681 struct hns3_nic_priv *priv = netdev_priv(netdev); 682 struct hnae3_handle *h = priv->ae_handle; 683 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 684 bool last_state; 685 686 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 && 687 h->ae_algo->ops->enable_vlan_filter) { 688 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false; 689 if (enable != last_state) { 690 netdev_info(netdev, 691 "%s vlan filter\n", 692 enable ? "enable" : "disable"); 693 h->ae_algo->ops->enable_vlan_filter(h, enable); 694 } 695 } 696 } 697 698 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen, 699 u16 *mss, u32 *type_cs_vlan_tso) 700 { 701 u32 l4_offset, hdr_len; 702 union l3_hdr_info l3; 703 union l4_hdr_info l4; 704 u32 l4_paylen; 705 int ret; 706 707 if (!skb_is_gso(skb)) 708 return 0; 709 710 ret = skb_cow_head(skb, 0); 711 if (unlikely(ret < 0)) 712 return ret; 713 714 l3.hdr = skb_network_header(skb); 715 l4.hdr = skb_transport_header(skb); 716 717 /* Software should clear the IPv4's checksum field when tso is 718 * needed. 719 */ 720 if (l3.v4->version == 4) 721 l3.v4->check = 0; 722 723 /* tunnel packet */ 724 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 725 SKB_GSO_GRE_CSUM | 726 SKB_GSO_UDP_TUNNEL | 727 SKB_GSO_UDP_TUNNEL_CSUM)) { 728 if ((!(skb_shinfo(skb)->gso_type & 729 SKB_GSO_PARTIAL)) && 730 (skb_shinfo(skb)->gso_type & 731 SKB_GSO_UDP_TUNNEL_CSUM)) { 732 /* Software should clear the udp's checksum 733 * field when tso is needed. 734 */ 735 l4.udp->check = 0; 736 } 737 /* reset l3&l4 pointers from outer to inner headers */ 738 l3.hdr = skb_inner_network_header(skb); 739 l4.hdr = skb_inner_transport_header(skb); 740 741 /* Software should clear the IPv4's checksum field when 742 * tso is needed. 743 */ 744 if (l3.v4->version == 4) 745 l3.v4->check = 0; 746 } 747 748 /* normal or tunnel packet */ 749 l4_offset = l4.hdr - skb->data; 750 751 /* remove payload length from inner pseudo checksum when tso */ 752 l4_paylen = skb->len - l4_offset; 753 754 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 755 hdr_len = sizeof(*l4.udp) + l4_offset; 756 csum_replace_by_diff(&l4.udp->check, 757 (__force __wsum)htonl(l4_paylen)); 758 } else { 759 hdr_len = (l4.tcp->doff << 2) + l4_offset; 760 csum_replace_by_diff(&l4.tcp->check, 761 (__force __wsum)htonl(l4_paylen)); 762 } 763 764 /* find the txbd field values */ 765 *paylen = skb->len - hdr_len; 766 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 767 768 /* get MSS for TSO */ 769 *mss = skb_shinfo(skb)->gso_size; 770 771 trace_hns3_tso(skb); 772 773 return 0; 774 } 775 776 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 777 u8 *il4_proto) 778 { 779 union l3_hdr_info l3; 780 unsigned char *l4_hdr; 781 unsigned char *exthdr; 782 u8 l4_proto_tmp; 783 __be16 frag_off; 784 785 /* find outer header point */ 786 l3.hdr = skb_network_header(skb); 787 l4_hdr = skb_transport_header(skb); 788 789 if (skb->protocol == htons(ETH_P_IPV6)) { 790 exthdr = l3.hdr + sizeof(*l3.v6); 791 l4_proto_tmp = l3.v6->nexthdr; 792 if (l4_hdr != exthdr) 793 ipv6_skip_exthdr(skb, exthdr - skb->data, 794 &l4_proto_tmp, &frag_off); 795 } else if (skb->protocol == htons(ETH_P_IP)) { 796 l4_proto_tmp = l3.v4->protocol; 797 } else { 798 return -EINVAL; 799 } 800 801 *ol4_proto = l4_proto_tmp; 802 803 /* tunnel packet */ 804 if (!skb->encapsulation) { 805 *il4_proto = 0; 806 return 0; 807 } 808 809 /* find inner header point */ 810 l3.hdr = skb_inner_network_header(skb); 811 l4_hdr = skb_inner_transport_header(skb); 812 813 if (l3.v6->version == 6) { 814 exthdr = l3.hdr + sizeof(*l3.v6); 815 l4_proto_tmp = l3.v6->nexthdr; 816 if (l4_hdr != exthdr) 817 ipv6_skip_exthdr(skb, exthdr - skb->data, 818 &l4_proto_tmp, &frag_off); 819 } else if (l3.v4->version == 4) { 820 l4_proto_tmp = l3.v4->protocol; 821 } 822 823 *il4_proto = l4_proto_tmp; 824 825 return 0; 826 } 827 828 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 829 * and it is udp packet, which has a dest port as the IANA assigned. 830 * the hardware is expected to do the checksum offload, but the 831 * hardware will not do the checksum offload when udp dest port is 832 * 4789 or 6081. 833 */ 834 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 835 { 836 union l4_hdr_info l4; 837 838 l4.hdr = skb_transport_header(skb); 839 840 if (!(!skb->encapsulation && 841 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) || 842 l4.udp->dest == htons(GENEVE_UDP_PORT)))) 843 return false; 844 845 skb_checksum_help(skb); 846 847 return true; 848 } 849 850 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 851 u32 *ol_type_vlan_len_msec) 852 { 853 u32 l2_len, l3_len, l4_len; 854 unsigned char *il2_hdr; 855 union l3_hdr_info l3; 856 union l4_hdr_info l4; 857 858 l3.hdr = skb_network_header(skb); 859 l4.hdr = skb_transport_header(skb); 860 861 /* compute OL2 header size, defined in 2 Bytes */ 862 l2_len = l3.hdr - skb->data; 863 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1); 864 865 /* compute OL3 header size, defined in 4 Bytes */ 866 l3_len = l4.hdr - l3.hdr; 867 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2); 868 869 il2_hdr = skb_inner_mac_header(skb); 870 /* compute OL4 header size, defined in 4 Bytes */ 871 l4_len = il2_hdr - l4.hdr; 872 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2); 873 874 /* define outer network header type */ 875 if (skb->protocol == htons(ETH_P_IP)) { 876 if (skb_is_gso(skb)) 877 hns3_set_field(*ol_type_vlan_len_msec, 878 HNS3_TXD_OL3T_S, 879 HNS3_OL3T_IPV4_CSUM); 880 else 881 hns3_set_field(*ol_type_vlan_len_msec, 882 HNS3_TXD_OL3T_S, 883 HNS3_OL3T_IPV4_NO_CSUM); 884 885 } else if (skb->protocol == htons(ETH_P_IPV6)) { 886 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 887 HNS3_OL3T_IPV6); 888 } 889 890 if (ol4_proto == IPPROTO_UDP) 891 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 892 HNS3_TUN_MAC_IN_UDP); 893 else if (ol4_proto == IPPROTO_GRE) 894 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 895 HNS3_TUN_NVGRE); 896 } 897 898 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 899 u8 il4_proto, u32 *type_cs_vlan_tso, 900 u32 *ol_type_vlan_len_msec) 901 { 902 unsigned char *l2_hdr = skb->data; 903 u32 l4_proto = ol4_proto; 904 union l4_hdr_info l4; 905 union l3_hdr_info l3; 906 u32 l2_len, l3_len; 907 908 l4.hdr = skb_transport_header(skb); 909 l3.hdr = skb_network_header(skb); 910 911 /* handle encapsulation skb */ 912 if (skb->encapsulation) { 913 /* If this is a not UDP/GRE encapsulation skb */ 914 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) { 915 /* drop the skb tunnel packet if hardware don't support, 916 * because hardware can't calculate csum when TSO. 917 */ 918 if (skb_is_gso(skb)) 919 return -EDOM; 920 921 /* the stack computes the IP header already, 922 * driver calculate l4 checksum when not TSO. 923 */ 924 skb_checksum_help(skb); 925 return 0; 926 } 927 928 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec); 929 930 /* switch to inner header */ 931 l2_hdr = skb_inner_mac_header(skb); 932 l3.hdr = skb_inner_network_header(skb); 933 l4.hdr = skb_inner_transport_header(skb); 934 l4_proto = il4_proto; 935 } 936 937 if (l3.v4->version == 4) { 938 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 939 HNS3_L3T_IPV4); 940 941 /* the stack computes the IP header already, the only time we 942 * need the hardware to recompute it is in the case of TSO. 943 */ 944 if (skb_is_gso(skb)) 945 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 946 } else if (l3.v6->version == 6) { 947 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 948 HNS3_L3T_IPV6); 949 } 950 951 /* compute inner(/normal) L2 header size, defined in 2 Bytes */ 952 l2_len = l3.hdr - l2_hdr; 953 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 954 955 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 956 l3_len = l4.hdr - l3.hdr; 957 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 958 959 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 960 switch (l4_proto) { 961 case IPPROTO_TCP: 962 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 963 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 964 HNS3_L4T_TCP); 965 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 966 l4.tcp->doff); 967 break; 968 case IPPROTO_UDP: 969 if (hns3_tunnel_csum_bug(skb)) 970 break; 971 972 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 973 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 974 HNS3_L4T_UDP); 975 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 976 (sizeof(struct udphdr) >> 2)); 977 break; 978 case IPPROTO_SCTP: 979 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 980 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 981 HNS3_L4T_SCTP); 982 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 983 (sizeof(struct sctphdr) >> 2)); 984 break; 985 default: 986 /* drop the skb tunnel packet if hardware don't support, 987 * because hardware can't calculate csum when TSO. 988 */ 989 if (skb_is_gso(skb)) 990 return -EDOM; 991 992 /* the stack computes the IP header already, 993 * driver calculate l4 checksum when not TSO. 994 */ 995 skb_checksum_help(skb); 996 return 0; 997 } 998 999 return 0; 1000 } 1001 1002 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring, 1003 struct sk_buff *skb) 1004 { 1005 struct hnae3_handle *handle = tx_ring->tqp->handle; 1006 struct vlan_ethhdr *vhdr; 1007 int rc; 1008 1009 if (!(skb->protocol == htons(ETH_P_8021Q) || 1010 skb_vlan_tag_present(skb))) 1011 return 0; 1012 1013 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN 1014 * header is allowed in skb, otherwise it will cause RAS error. 1015 */ 1016 if (unlikely(skb_vlan_tagged_multi(skb) && 1017 handle->port_base_vlan_state == 1018 HNAE3_PORT_BASE_VLAN_ENABLE)) 1019 return -EINVAL; 1020 1021 if (skb->protocol == htons(ETH_P_8021Q) && 1022 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 1023 /* When HW VLAN acceleration is turned off, and the stack 1024 * sets the protocol to 802.1q, the driver just need to 1025 * set the protocol to the encapsulated ethertype. 1026 */ 1027 skb->protocol = vlan_get_protocol(skb); 1028 return 0; 1029 } 1030 1031 if (skb_vlan_tag_present(skb)) { 1032 /* Based on hw strategy, use out_vtag in two layer tag case, 1033 * and use inner_vtag in one tag case. 1034 */ 1035 if (skb->protocol == htons(ETH_P_8021Q) && 1036 handle->port_base_vlan_state == 1037 HNAE3_PORT_BASE_VLAN_DISABLE) 1038 rc = HNS3_OUTER_VLAN_TAG; 1039 else 1040 rc = HNS3_INNER_VLAN_TAG; 1041 1042 skb->protocol = vlan_get_protocol(skb); 1043 return rc; 1044 } 1045 1046 rc = skb_cow_head(skb, 0); 1047 if (unlikely(rc < 0)) 1048 return rc; 1049 1050 vhdr = (struct vlan_ethhdr *)skb->data; 1051 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT) 1052 & VLAN_PRIO_MASK); 1053 1054 skb->protocol = vlan_get_protocol(skb); 1055 return 0; 1056 } 1057 1058 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring, 1059 struct sk_buff *skb, struct hns3_desc *desc) 1060 { 1061 u32 ol_type_vlan_len_msec = 0; 1062 u32 type_cs_vlan_tso = 0; 1063 u32 paylen = skb->len; 1064 u16 inner_vtag = 0; 1065 u16 out_vtag = 0; 1066 u16 mss = 0; 1067 int ret; 1068 1069 ret = hns3_handle_vtags(ring, skb); 1070 if (unlikely(ret < 0)) { 1071 u64_stats_update_begin(&ring->syncp); 1072 ring->stats.tx_vlan_err++; 1073 u64_stats_update_end(&ring->syncp); 1074 return ret; 1075 } else if (ret == HNS3_INNER_VLAN_TAG) { 1076 inner_vtag = skb_vlan_tag_get(skb); 1077 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1078 VLAN_PRIO_MASK; 1079 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1); 1080 } else if (ret == HNS3_OUTER_VLAN_TAG) { 1081 out_vtag = skb_vlan_tag_get(skb); 1082 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1083 VLAN_PRIO_MASK; 1084 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B, 1085 1); 1086 } 1087 1088 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1089 u8 ol4_proto, il4_proto; 1090 1091 skb_reset_mac_len(skb); 1092 1093 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1094 if (unlikely(ret < 0)) { 1095 u64_stats_update_begin(&ring->syncp); 1096 ring->stats.tx_l4_proto_err++; 1097 u64_stats_update_end(&ring->syncp); 1098 return ret; 1099 } 1100 1101 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto, 1102 &type_cs_vlan_tso, 1103 &ol_type_vlan_len_msec); 1104 if (unlikely(ret < 0)) { 1105 u64_stats_update_begin(&ring->syncp); 1106 ring->stats.tx_l2l3l4_err++; 1107 u64_stats_update_end(&ring->syncp); 1108 return ret; 1109 } 1110 1111 ret = hns3_set_tso(skb, &paylen, &mss, 1112 &type_cs_vlan_tso); 1113 if (unlikely(ret < 0)) { 1114 u64_stats_update_begin(&ring->syncp); 1115 ring->stats.tx_tso_err++; 1116 u64_stats_update_end(&ring->syncp); 1117 return ret; 1118 } 1119 } 1120 1121 /* Set txbd */ 1122 desc->tx.ol_type_vlan_len_msec = 1123 cpu_to_le32(ol_type_vlan_len_msec); 1124 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso); 1125 desc->tx.paylen = cpu_to_le32(paylen); 1126 desc->tx.mss = cpu_to_le16(mss); 1127 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1128 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1129 1130 return 0; 1131 } 1132 1133 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 1134 unsigned int size, enum hns_desc_type type) 1135 { 1136 #define HNS3_LIKELY_BD_NUM 1 1137 1138 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1139 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1140 struct device *dev = ring_to_dev(ring); 1141 skb_frag_t *frag; 1142 unsigned int frag_buf_num; 1143 int k, sizeoflast; 1144 dma_addr_t dma; 1145 1146 if (type == DESC_TYPE_FRAGLIST_SKB || 1147 type == DESC_TYPE_SKB) { 1148 struct sk_buff *skb = (struct sk_buff *)priv; 1149 1150 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1151 } else { 1152 frag = (skb_frag_t *)priv; 1153 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1154 } 1155 1156 if (unlikely(dma_mapping_error(dev, dma))) { 1157 u64_stats_update_begin(&ring->syncp); 1158 ring->stats.sw_err_cnt++; 1159 u64_stats_update_end(&ring->syncp); 1160 return -ENOMEM; 1161 } 1162 1163 desc_cb->priv = priv; 1164 desc_cb->length = size; 1165 desc_cb->dma = dma; 1166 desc_cb->type = type; 1167 1168 if (likely(size <= HNS3_MAX_BD_SIZE)) { 1169 desc->addr = cpu_to_le64(dma); 1170 desc->tx.send_size = cpu_to_le16(size); 1171 desc->tx.bdtp_fe_sc_vld_ra_ri = 1172 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1173 1174 trace_hns3_tx_desc(ring, ring->next_to_use); 1175 ring_ptr_move_fw(ring, next_to_use); 1176 return HNS3_LIKELY_BD_NUM; 1177 } 1178 1179 frag_buf_num = hns3_tx_bd_count(size); 1180 sizeoflast = size % HNS3_MAX_BD_SIZE; 1181 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1182 1183 /* When frag size is bigger than hardware limit, split this frag */ 1184 for (k = 0; k < frag_buf_num; k++) { 1185 /* now, fill the descriptor */ 1186 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1187 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1188 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1189 desc->tx.bdtp_fe_sc_vld_ra_ri = 1190 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1191 1192 trace_hns3_tx_desc(ring, ring->next_to_use); 1193 /* move ring pointer to next */ 1194 ring_ptr_move_fw(ring, next_to_use); 1195 1196 desc = &ring->desc[ring->next_to_use]; 1197 } 1198 1199 return frag_buf_num; 1200 } 1201 1202 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1203 unsigned int bd_num) 1204 { 1205 unsigned int size; 1206 int i; 1207 1208 size = skb_headlen(skb); 1209 while (size > HNS3_MAX_BD_SIZE) { 1210 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1211 size -= HNS3_MAX_BD_SIZE; 1212 1213 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1214 return bd_num; 1215 } 1216 1217 if (size) { 1218 bd_size[bd_num++] = size; 1219 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1220 return bd_num; 1221 } 1222 1223 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1224 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1225 size = skb_frag_size(frag); 1226 if (!size) 1227 continue; 1228 1229 while (size > HNS3_MAX_BD_SIZE) { 1230 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1231 size -= HNS3_MAX_BD_SIZE; 1232 1233 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1234 return bd_num; 1235 } 1236 1237 bd_size[bd_num++] = size; 1238 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1239 return bd_num; 1240 } 1241 1242 return bd_num; 1243 } 1244 1245 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1246 u8 max_non_tso_bd_num) 1247 { 1248 struct sk_buff *frag_skb; 1249 unsigned int bd_num = 0; 1250 1251 /* If the total len is within the max bd limit */ 1252 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !skb_has_frag_list(skb) && 1253 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num)) 1254 return skb_shinfo(skb)->nr_frags + 1U; 1255 1256 /* The below case will always be linearized, return 1257 * HNS3_MAX_BD_NUM_TSO + 1U to make sure it is linearized. 1258 */ 1259 if (unlikely(skb->len > HNS3_MAX_TSO_SIZE || 1260 (!skb_is_gso(skb) && skb->len > 1261 HNS3_MAX_NON_TSO_SIZE(max_non_tso_bd_num)))) 1262 return HNS3_MAX_TSO_BD_NUM + 1U; 1263 1264 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num); 1265 1266 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM) 1267 return bd_num; 1268 1269 skb_walk_frags(skb, frag_skb) { 1270 bd_num = hns3_skb_bd_num(frag_skb, bd_size, bd_num); 1271 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1272 return bd_num; 1273 } 1274 1275 return bd_num; 1276 } 1277 1278 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb) 1279 { 1280 if (!skb->encapsulation) 1281 return skb_transport_offset(skb) + tcp_hdrlen(skb); 1282 1283 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb); 1284 } 1285 1286 /* HW need every continuous max_non_tso_bd_num buffer data to be larger 1287 * than MSS, we simplify it by ensuring skb_headlen + the first continuous 1288 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss, 1289 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger 1290 * than MSS except the last max_non_tso_bd_num - 1 frags. 1291 */ 1292 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size, 1293 unsigned int bd_num, u8 max_non_tso_bd_num) 1294 { 1295 unsigned int tot_len = 0; 1296 int i; 1297 1298 for (i = 0; i < max_non_tso_bd_num - 1U; i++) 1299 tot_len += bd_size[i]; 1300 1301 /* ensure the first max_non_tso_bd_num frags is greater than 1302 * mss + header 1303 */ 1304 if (tot_len + bd_size[max_non_tso_bd_num - 1U] < 1305 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb)) 1306 return true; 1307 1308 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater 1309 * than mss except the last one. 1310 */ 1311 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) { 1312 tot_len -= bd_size[i]; 1313 tot_len += bd_size[i + max_non_tso_bd_num - 1U]; 1314 1315 if (tot_len < skb_shinfo(skb)->gso_size) 1316 return true; 1317 } 1318 1319 return false; 1320 } 1321 1322 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size) 1323 { 1324 int i; 1325 1326 for (i = 0; i < MAX_SKB_FRAGS; i++) 1327 size[i] = skb_frag_size(&shinfo->frags[i]); 1328 } 1329 1330 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring, 1331 struct net_device *netdev, 1332 struct sk_buff *skb) 1333 { 1334 struct hns3_nic_priv *priv = netdev_priv(netdev); 1335 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num; 1336 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U]; 1337 unsigned int bd_num; 1338 1339 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num); 1340 if (unlikely(bd_num > max_non_tso_bd_num)) { 1341 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) && 1342 !hns3_skb_need_linearized(skb, bd_size, bd_num, 1343 max_non_tso_bd_num)) { 1344 trace_hns3_over_max_bd(skb); 1345 goto out; 1346 } 1347 1348 if (__skb_linearize(skb)) 1349 return -ENOMEM; 1350 1351 bd_num = hns3_tx_bd_count(skb->len); 1352 if ((skb_is_gso(skb) && bd_num > HNS3_MAX_TSO_BD_NUM) || 1353 (!skb_is_gso(skb) && 1354 bd_num > max_non_tso_bd_num)) { 1355 trace_hns3_over_max_bd(skb); 1356 return -ENOMEM; 1357 } 1358 1359 u64_stats_update_begin(&ring->syncp); 1360 ring->stats.tx_copy++; 1361 u64_stats_update_end(&ring->syncp); 1362 } 1363 1364 out: 1365 if (likely(ring_space(ring) >= bd_num)) 1366 return bd_num; 1367 1368 netif_stop_subqueue(netdev, ring->queue_index); 1369 smp_mb(); /* Memory barrier before checking ring_space */ 1370 1371 /* Start queue in case hns3_clean_tx_ring has just made room 1372 * available and has not seen the queue stopped state performed 1373 * by netif_stop_subqueue above. 1374 */ 1375 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) && 1376 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 1377 netif_start_subqueue(netdev, ring->queue_index); 1378 return bd_num; 1379 } 1380 1381 return -EBUSY; 1382 } 1383 1384 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1385 { 1386 struct device *dev = ring_to_dev(ring); 1387 unsigned int i; 1388 1389 for (i = 0; i < ring->desc_num; i++) { 1390 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1391 1392 memset(desc, 0, sizeof(*desc)); 1393 1394 /* check if this is where we started */ 1395 if (ring->next_to_use == next_to_use_orig) 1396 break; 1397 1398 /* rollback one */ 1399 ring_ptr_move_bw(ring, next_to_use); 1400 1401 if (!ring->desc_cb[ring->next_to_use].dma) 1402 continue; 1403 1404 /* unmap the descriptor dma address */ 1405 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB || 1406 ring->desc_cb[ring->next_to_use].type == 1407 DESC_TYPE_FRAGLIST_SKB) 1408 dma_unmap_single(dev, 1409 ring->desc_cb[ring->next_to_use].dma, 1410 ring->desc_cb[ring->next_to_use].length, 1411 DMA_TO_DEVICE); 1412 else if (ring->desc_cb[ring->next_to_use].length) 1413 dma_unmap_page(dev, 1414 ring->desc_cb[ring->next_to_use].dma, 1415 ring->desc_cb[ring->next_to_use].length, 1416 DMA_TO_DEVICE); 1417 1418 ring->desc_cb[ring->next_to_use].length = 0; 1419 ring->desc_cb[ring->next_to_use].dma = 0; 1420 ring->desc_cb[ring->next_to_use].type = DESC_TYPE_UNKNOWN; 1421 } 1422 } 1423 1424 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring, 1425 struct sk_buff *skb, enum hns_desc_type type) 1426 { 1427 unsigned int size = skb_headlen(skb); 1428 int i, ret, bd_num = 0; 1429 1430 if (size) { 1431 ret = hns3_fill_desc(ring, skb, size, type); 1432 if (unlikely(ret < 0)) 1433 return ret; 1434 1435 bd_num += ret; 1436 } 1437 1438 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1439 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1440 1441 size = skb_frag_size(frag); 1442 if (!size) 1443 continue; 1444 1445 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE); 1446 if (unlikely(ret < 0)) 1447 return ret; 1448 1449 bd_num += ret; 1450 } 1451 1452 return bd_num; 1453 } 1454 1455 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num, 1456 bool doorbell) 1457 { 1458 ring->pending_buf += num; 1459 1460 if (!doorbell) { 1461 u64_stats_update_begin(&ring->syncp); 1462 ring->stats.tx_more++; 1463 u64_stats_update_end(&ring->syncp); 1464 return; 1465 } 1466 1467 if (!ring->pending_buf) 1468 return; 1469 1470 writel(ring->pending_buf, 1471 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG); 1472 ring->pending_buf = 0; 1473 WRITE_ONCE(ring->last_to_use, ring->next_to_use); 1474 } 1475 1476 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1477 { 1478 struct hns3_nic_priv *priv = netdev_priv(netdev); 1479 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping]; 1480 struct netdev_queue *dev_queue; 1481 int pre_ntu, next_to_use_head; 1482 struct sk_buff *frag_skb; 1483 int bd_num = 0; 1484 bool doorbell; 1485 int ret; 1486 1487 /* Hardware can only handle short frames above 32 bytes */ 1488 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) { 1489 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 1490 return NETDEV_TX_OK; 1491 } 1492 1493 /* Prefetch the data used later */ 1494 prefetch(skb->data); 1495 1496 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb); 1497 if (unlikely(ret <= 0)) { 1498 if (ret == -EBUSY) { 1499 u64_stats_update_begin(&ring->syncp); 1500 ring->stats.tx_busy++; 1501 u64_stats_update_end(&ring->syncp); 1502 hns3_tx_doorbell(ring, 0, true); 1503 return NETDEV_TX_BUSY; 1504 } else if (ret == -ENOMEM) { 1505 u64_stats_update_begin(&ring->syncp); 1506 ring->stats.sw_err_cnt++; 1507 u64_stats_update_end(&ring->syncp); 1508 } 1509 1510 hns3_rl_err(netdev, "xmit error: %d!\n", ret); 1511 goto out_err_tx_ok; 1512 } 1513 1514 next_to_use_head = ring->next_to_use; 1515 1516 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use]); 1517 if (unlikely(ret < 0)) 1518 goto fill_err; 1519 1520 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB); 1521 if (unlikely(ret < 0)) 1522 goto fill_err; 1523 1524 bd_num += ret; 1525 1526 skb_walk_frags(skb, frag_skb) { 1527 ret = hns3_fill_skb_to_desc(ring, frag_skb, 1528 DESC_TYPE_FRAGLIST_SKB); 1529 if (unlikely(ret < 0)) 1530 goto fill_err; 1531 1532 bd_num += ret; 1533 } 1534 1535 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) : 1536 (ring->desc_num - 1); 1537 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |= 1538 cpu_to_le16(BIT(HNS3_TXD_FE_B)); 1539 trace_hns3_tx_desc(ring, pre_ntu); 1540 1541 /* Complete translate all packets */ 1542 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index); 1543 doorbell = __netdev_tx_sent_queue(dev_queue, skb->len, 1544 netdev_xmit_more()); 1545 hns3_tx_doorbell(ring, bd_num, doorbell); 1546 1547 return NETDEV_TX_OK; 1548 1549 fill_err: 1550 hns3_clear_desc(ring, next_to_use_head); 1551 1552 out_err_tx_ok: 1553 dev_kfree_skb_any(skb); 1554 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 1555 return NETDEV_TX_OK; 1556 } 1557 1558 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1559 { 1560 struct hnae3_handle *h = hns3_get_handle(netdev); 1561 struct sockaddr *mac_addr = p; 1562 int ret; 1563 1564 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1565 return -EADDRNOTAVAIL; 1566 1567 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1568 netdev_info(netdev, "already using mac address %pM\n", 1569 mac_addr->sa_data); 1570 return 0; 1571 } 1572 1573 /* For VF device, if there is a perm_addr, then the user will not 1574 * be allowed to change the address. 1575 */ 1576 if (!hns3_is_phys_func(h->pdev) && 1577 !is_zero_ether_addr(netdev->perm_addr)) { 1578 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n", 1579 netdev->perm_addr, mac_addr->sa_data); 1580 return -EPERM; 1581 } 1582 1583 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1584 if (ret) { 1585 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1586 return ret; 1587 } 1588 1589 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1590 1591 return 0; 1592 } 1593 1594 static int hns3_nic_do_ioctl(struct net_device *netdev, 1595 struct ifreq *ifr, int cmd) 1596 { 1597 struct hnae3_handle *h = hns3_get_handle(netdev); 1598 1599 if (!netif_running(netdev)) 1600 return -EINVAL; 1601 1602 if (!h->ae_algo->ops->do_ioctl) 1603 return -EOPNOTSUPP; 1604 1605 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 1606 } 1607 1608 static int hns3_nic_set_features(struct net_device *netdev, 1609 netdev_features_t features) 1610 { 1611 netdev_features_t changed = netdev->features ^ features; 1612 struct hns3_nic_priv *priv = netdev_priv(netdev); 1613 struct hnae3_handle *h = priv->ae_handle; 1614 bool enable; 1615 int ret; 1616 1617 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 1618 enable = !!(features & NETIF_F_GRO_HW); 1619 ret = h->ae_algo->ops->set_gro_en(h, enable); 1620 if (ret) 1621 return ret; 1622 } 1623 1624 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1625 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1626 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 1627 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 1628 if (ret) 1629 return ret; 1630 } 1631 1632 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 1633 enable = !!(features & NETIF_F_NTUPLE); 1634 h->ae_algo->ops->enable_fd(h, enable); 1635 } 1636 1637 netdev->features = features; 1638 return 0; 1639 } 1640 1641 static netdev_features_t hns3_features_check(struct sk_buff *skb, 1642 struct net_device *dev, 1643 netdev_features_t features) 1644 { 1645 #define HNS3_MAX_HDR_LEN 480U 1646 #define HNS3_MAX_L4_HDR_LEN 60U 1647 1648 size_t len; 1649 1650 if (skb->ip_summed != CHECKSUM_PARTIAL) 1651 return features; 1652 1653 if (skb->encapsulation) 1654 len = skb_inner_transport_header(skb) - skb->data; 1655 else 1656 len = skb_transport_header(skb) - skb->data; 1657 1658 /* Assume L4 is 60 byte as TCP is the only protocol with a 1659 * a flexible value, and it's max len is 60 bytes. 1660 */ 1661 len += HNS3_MAX_L4_HDR_LEN; 1662 1663 /* Hardware only supports checksum on the skb with a max header 1664 * len of 480 bytes. 1665 */ 1666 if (len > HNS3_MAX_HDR_LEN) 1667 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 1668 1669 return features; 1670 } 1671 1672 static void hns3_nic_get_stats64(struct net_device *netdev, 1673 struct rtnl_link_stats64 *stats) 1674 { 1675 struct hns3_nic_priv *priv = netdev_priv(netdev); 1676 int queue_num = priv->ae_handle->kinfo.num_tqps; 1677 struct hnae3_handle *handle = priv->ae_handle; 1678 struct hns3_enet_ring *ring; 1679 u64 rx_length_errors = 0; 1680 u64 rx_crc_errors = 0; 1681 u64 rx_multicast = 0; 1682 unsigned int start; 1683 u64 tx_errors = 0; 1684 u64 rx_errors = 0; 1685 unsigned int idx; 1686 u64 tx_bytes = 0; 1687 u64 rx_bytes = 0; 1688 u64 tx_pkts = 0; 1689 u64 rx_pkts = 0; 1690 u64 tx_drop = 0; 1691 u64 rx_drop = 0; 1692 1693 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1694 return; 1695 1696 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1697 1698 for (idx = 0; idx < queue_num; idx++) { 1699 /* fetch the tx stats */ 1700 ring = &priv->ring[idx]; 1701 do { 1702 start = u64_stats_fetch_begin_irq(&ring->syncp); 1703 tx_bytes += ring->stats.tx_bytes; 1704 tx_pkts += ring->stats.tx_pkts; 1705 tx_drop += ring->stats.sw_err_cnt; 1706 tx_drop += ring->stats.tx_vlan_err; 1707 tx_drop += ring->stats.tx_l4_proto_err; 1708 tx_drop += ring->stats.tx_l2l3l4_err; 1709 tx_drop += ring->stats.tx_tso_err; 1710 tx_errors += ring->stats.sw_err_cnt; 1711 tx_errors += ring->stats.tx_vlan_err; 1712 tx_errors += ring->stats.tx_l4_proto_err; 1713 tx_errors += ring->stats.tx_l2l3l4_err; 1714 tx_errors += ring->stats.tx_tso_err; 1715 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1716 1717 /* fetch the rx stats */ 1718 ring = &priv->ring[idx + queue_num]; 1719 do { 1720 start = u64_stats_fetch_begin_irq(&ring->syncp); 1721 rx_bytes += ring->stats.rx_bytes; 1722 rx_pkts += ring->stats.rx_pkts; 1723 rx_drop += ring->stats.l2_err; 1724 rx_errors += ring->stats.l2_err; 1725 rx_errors += ring->stats.l3l4_csum_err; 1726 rx_crc_errors += ring->stats.l2_err; 1727 rx_multicast += ring->stats.rx_multicast; 1728 rx_length_errors += ring->stats.err_pkt_len; 1729 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1730 } 1731 1732 stats->tx_bytes = tx_bytes; 1733 stats->tx_packets = tx_pkts; 1734 stats->rx_bytes = rx_bytes; 1735 stats->rx_packets = rx_pkts; 1736 1737 stats->rx_errors = rx_errors; 1738 stats->multicast = rx_multicast; 1739 stats->rx_length_errors = rx_length_errors; 1740 stats->rx_crc_errors = rx_crc_errors; 1741 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1742 1743 stats->tx_errors = tx_errors; 1744 stats->rx_dropped = rx_drop; 1745 stats->tx_dropped = tx_drop; 1746 stats->collisions = netdev->stats.collisions; 1747 stats->rx_over_errors = netdev->stats.rx_over_errors; 1748 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1749 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1750 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1751 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1752 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1753 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1754 stats->tx_window_errors = netdev->stats.tx_window_errors; 1755 stats->rx_compressed = netdev->stats.rx_compressed; 1756 stats->tx_compressed = netdev->stats.tx_compressed; 1757 } 1758 1759 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1760 { 1761 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1762 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map; 1763 struct hnae3_knic_private_info *kinfo; 1764 u8 tc = mqprio_qopt->qopt.num_tc; 1765 u16 mode = mqprio_qopt->mode; 1766 u8 hw = mqprio_qopt->qopt.hw; 1767 struct hnae3_handle *h; 1768 1769 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1770 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1771 return -EOPNOTSUPP; 1772 1773 if (tc > HNAE3_MAX_TC) 1774 return -EINVAL; 1775 1776 if (!netdev) 1777 return -EINVAL; 1778 1779 h = hns3_get_handle(netdev); 1780 kinfo = &h->kinfo; 1781 1782 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc); 1783 1784 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1785 kinfo->dcb_ops->setup_tc(h, tc ? tc : 1, prio_tc) : -EOPNOTSUPP; 1786 } 1787 1788 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1789 void *type_data) 1790 { 1791 if (type != TC_SETUP_QDISC_MQPRIO) 1792 return -EOPNOTSUPP; 1793 1794 return hns3_setup_tc(dev, type_data); 1795 } 1796 1797 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1798 __be16 proto, u16 vid) 1799 { 1800 struct hnae3_handle *h = hns3_get_handle(netdev); 1801 int ret = -EIO; 1802 1803 if (h->ae_algo->ops->set_vlan_filter) 1804 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1805 1806 return ret; 1807 } 1808 1809 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1810 __be16 proto, u16 vid) 1811 { 1812 struct hnae3_handle *h = hns3_get_handle(netdev); 1813 int ret = -EIO; 1814 1815 if (h->ae_algo->ops->set_vlan_filter) 1816 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1817 1818 return ret; 1819 } 1820 1821 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1822 u8 qos, __be16 vlan_proto) 1823 { 1824 struct hnae3_handle *h = hns3_get_handle(netdev); 1825 int ret = -EIO; 1826 1827 netif_dbg(h, drv, netdev, 1828 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n", 1829 vf, vlan, qos, ntohs(vlan_proto)); 1830 1831 if (h->ae_algo->ops->set_vf_vlan_filter) 1832 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1833 qos, vlan_proto); 1834 1835 return ret; 1836 } 1837 1838 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable) 1839 { 1840 struct hnae3_handle *handle = hns3_get_handle(netdev); 1841 1842 if (hns3_nic_resetting(netdev)) 1843 return -EBUSY; 1844 1845 if (!handle->ae_algo->ops->set_vf_spoofchk) 1846 return -EOPNOTSUPP; 1847 1848 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable); 1849 } 1850 1851 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable) 1852 { 1853 struct hnae3_handle *handle = hns3_get_handle(netdev); 1854 1855 if (!handle->ae_algo->ops->set_vf_trust) 1856 return -EOPNOTSUPP; 1857 1858 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable); 1859 } 1860 1861 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1862 { 1863 struct hnae3_handle *h = hns3_get_handle(netdev); 1864 int ret; 1865 1866 if (hns3_nic_resetting(netdev)) 1867 return -EBUSY; 1868 1869 if (!h->ae_algo->ops->set_mtu) 1870 return -EOPNOTSUPP; 1871 1872 netif_dbg(h, drv, netdev, 1873 "change mtu from %u to %d\n", netdev->mtu, new_mtu); 1874 1875 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 1876 if (ret) 1877 netdev_err(netdev, "failed to change MTU in hardware %d\n", 1878 ret); 1879 else 1880 netdev->mtu = new_mtu; 1881 1882 return ret; 1883 } 1884 1885 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 1886 { 1887 struct hns3_nic_priv *priv = netdev_priv(ndev); 1888 struct hnae3_handle *h = hns3_get_handle(ndev); 1889 struct hns3_enet_ring *tx_ring; 1890 struct napi_struct *napi; 1891 int timeout_queue = 0; 1892 int hw_head, hw_tail; 1893 int fbd_num, fbd_oft; 1894 int ebd_num, ebd_oft; 1895 int bd_num, bd_err; 1896 int ring_en, tc; 1897 int i; 1898 1899 /* Find the stopped queue the same way the stack does */ 1900 for (i = 0; i < ndev->num_tx_queues; i++) { 1901 struct netdev_queue *q; 1902 unsigned long trans_start; 1903 1904 q = netdev_get_tx_queue(ndev, i); 1905 trans_start = q->trans_start; 1906 if (netif_xmit_stopped(q) && 1907 time_after(jiffies, 1908 (trans_start + ndev->watchdog_timeo))) { 1909 timeout_queue = i; 1910 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n", 1911 q->state, 1912 jiffies_to_msecs(jiffies - trans_start)); 1913 break; 1914 } 1915 } 1916 1917 if (i == ndev->num_tx_queues) { 1918 netdev_info(ndev, 1919 "no netdev TX timeout queue found, timeout count: %llu\n", 1920 priv->tx_timeout_count); 1921 return false; 1922 } 1923 1924 priv->tx_timeout_count++; 1925 1926 tx_ring = &priv->ring[timeout_queue]; 1927 napi = &tx_ring->tqp_vector->napi; 1928 1929 netdev_info(ndev, 1930 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n", 1931 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use, 1932 tx_ring->next_to_clean, napi->state); 1933 1934 netdev_info(ndev, 1935 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n", 1936 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes, 1937 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf); 1938 1939 netdev_info(ndev, 1940 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n", 1941 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more, 1942 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy); 1943 1944 /* When mac received many pause frames continuous, it's unable to send 1945 * packets, which may cause tx timeout 1946 */ 1947 if (h->ae_algo->ops->get_mac_stats) { 1948 struct hns3_mac_stats mac_stats; 1949 1950 h->ae_algo->ops->get_mac_stats(h, &mac_stats); 1951 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n", 1952 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt); 1953 } 1954 1955 hw_head = readl_relaxed(tx_ring->tqp->io_base + 1956 HNS3_RING_TX_RING_HEAD_REG); 1957 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 1958 HNS3_RING_TX_RING_TAIL_REG); 1959 fbd_num = readl_relaxed(tx_ring->tqp->io_base + 1960 HNS3_RING_TX_RING_FBDNUM_REG); 1961 fbd_oft = readl_relaxed(tx_ring->tqp->io_base + 1962 HNS3_RING_TX_RING_OFFSET_REG); 1963 ebd_num = readl_relaxed(tx_ring->tqp->io_base + 1964 HNS3_RING_TX_RING_EBDNUM_REG); 1965 ebd_oft = readl_relaxed(tx_ring->tqp->io_base + 1966 HNS3_RING_TX_RING_EBD_OFFSET_REG); 1967 bd_num = readl_relaxed(tx_ring->tqp->io_base + 1968 HNS3_RING_TX_RING_BD_NUM_REG); 1969 bd_err = readl_relaxed(tx_ring->tqp->io_base + 1970 HNS3_RING_TX_RING_BD_ERR_REG); 1971 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG); 1972 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG); 1973 1974 netdev_info(ndev, 1975 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n", 1976 bd_num, hw_head, hw_tail, bd_err, 1977 readl(tx_ring->tqp_vector->mask_addr)); 1978 netdev_info(ndev, 1979 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n", 1980 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft); 1981 1982 return true; 1983 } 1984 1985 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue) 1986 { 1987 struct hns3_nic_priv *priv = netdev_priv(ndev); 1988 struct hnae3_handle *h = priv->ae_handle; 1989 1990 if (!hns3_get_tx_timeo_queue_info(ndev)) 1991 return; 1992 1993 /* request the reset, and let the hclge to determine 1994 * which reset level should be done 1995 */ 1996 if (h->ae_algo->ops->reset_event) 1997 h->ae_algo->ops->reset_event(h->pdev, h); 1998 } 1999 2000 #ifdef CONFIG_RFS_ACCEL 2001 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 2002 u16 rxq_index, u32 flow_id) 2003 { 2004 struct hnae3_handle *h = hns3_get_handle(dev); 2005 struct flow_keys fkeys; 2006 2007 if (!h->ae_algo->ops->add_arfs_entry) 2008 return -EOPNOTSUPP; 2009 2010 if (skb->encapsulation) 2011 return -EPROTONOSUPPORT; 2012 2013 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0)) 2014 return -EPROTONOSUPPORT; 2015 2016 if ((fkeys.basic.n_proto != htons(ETH_P_IP) && 2017 fkeys.basic.n_proto != htons(ETH_P_IPV6)) || 2018 (fkeys.basic.ip_proto != IPPROTO_TCP && 2019 fkeys.basic.ip_proto != IPPROTO_UDP)) 2020 return -EPROTONOSUPPORT; 2021 2022 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys); 2023 } 2024 #endif 2025 2026 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf, 2027 struct ifla_vf_info *ivf) 2028 { 2029 struct hnae3_handle *h = hns3_get_handle(ndev); 2030 2031 if (!h->ae_algo->ops->get_vf_config) 2032 return -EOPNOTSUPP; 2033 2034 return h->ae_algo->ops->get_vf_config(h, vf, ivf); 2035 } 2036 2037 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf, 2038 int link_state) 2039 { 2040 struct hnae3_handle *h = hns3_get_handle(ndev); 2041 2042 if (!h->ae_algo->ops->set_vf_link_state) 2043 return -EOPNOTSUPP; 2044 2045 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state); 2046 } 2047 2048 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf, 2049 int min_tx_rate, int max_tx_rate) 2050 { 2051 struct hnae3_handle *h = hns3_get_handle(ndev); 2052 2053 if (!h->ae_algo->ops->set_vf_rate) 2054 return -EOPNOTSUPP; 2055 2056 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate, 2057 false); 2058 } 2059 2060 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) 2061 { 2062 struct hnae3_handle *h = hns3_get_handle(netdev); 2063 2064 if (!h->ae_algo->ops->set_vf_mac) 2065 return -EOPNOTSUPP; 2066 2067 if (is_multicast_ether_addr(mac)) { 2068 netdev_err(netdev, 2069 "Invalid MAC:%pM specified. Could not set MAC\n", 2070 mac); 2071 return -EINVAL; 2072 } 2073 2074 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac); 2075 } 2076 2077 static const struct net_device_ops hns3_nic_netdev_ops = { 2078 .ndo_open = hns3_nic_net_open, 2079 .ndo_stop = hns3_nic_net_stop, 2080 .ndo_start_xmit = hns3_nic_net_xmit, 2081 .ndo_tx_timeout = hns3_nic_net_timeout, 2082 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 2083 .ndo_do_ioctl = hns3_nic_do_ioctl, 2084 .ndo_change_mtu = hns3_nic_change_mtu, 2085 .ndo_set_features = hns3_nic_set_features, 2086 .ndo_features_check = hns3_features_check, 2087 .ndo_get_stats64 = hns3_nic_get_stats64, 2088 .ndo_setup_tc = hns3_nic_setup_tc, 2089 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 2090 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 2091 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 2092 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 2093 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk, 2094 .ndo_set_vf_trust = hns3_set_vf_trust, 2095 #ifdef CONFIG_RFS_ACCEL 2096 .ndo_rx_flow_steer = hns3_rx_flow_steer, 2097 #endif 2098 .ndo_get_vf_config = hns3_nic_get_vf_config, 2099 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state, 2100 .ndo_set_vf_rate = hns3_nic_set_vf_rate, 2101 .ndo_set_vf_mac = hns3_nic_set_vf_mac, 2102 }; 2103 2104 bool hns3_is_phys_func(struct pci_dev *pdev) 2105 { 2106 u32 dev_id = pdev->device; 2107 2108 switch (dev_id) { 2109 case HNAE3_DEV_ID_GE: 2110 case HNAE3_DEV_ID_25GE: 2111 case HNAE3_DEV_ID_25GE_RDMA: 2112 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 2113 case HNAE3_DEV_ID_50GE_RDMA: 2114 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 2115 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 2116 case HNAE3_DEV_ID_200G_RDMA: 2117 return true; 2118 case HNAE3_DEV_ID_VF: 2119 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF: 2120 return false; 2121 default: 2122 dev_warn(&pdev->dev, "un-recognized pci device-id %u", 2123 dev_id); 2124 } 2125 2126 return false; 2127 } 2128 2129 static void hns3_disable_sriov(struct pci_dev *pdev) 2130 { 2131 /* If our VFs are assigned we cannot shut down SR-IOV 2132 * without causing issues, so just leave the hardware 2133 * available but disabled 2134 */ 2135 if (pci_vfs_assigned(pdev)) { 2136 dev_warn(&pdev->dev, 2137 "disabling driver while VFs are assigned\n"); 2138 return; 2139 } 2140 2141 pci_disable_sriov(pdev); 2142 } 2143 2144 /* hns3_probe - Device initialization routine 2145 * @pdev: PCI device information struct 2146 * @ent: entry in hns3_pci_tbl 2147 * 2148 * hns3_probe initializes a PF identified by a pci_dev structure. 2149 * The OS initialization, configuring of the PF private structure, 2150 * and a hardware reset occur. 2151 * 2152 * Returns 0 on success, negative on failure 2153 */ 2154 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2155 { 2156 struct hnae3_ae_dev *ae_dev; 2157 int ret; 2158 2159 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL); 2160 if (!ae_dev) 2161 return -ENOMEM; 2162 2163 ae_dev->pdev = pdev; 2164 ae_dev->flag = ent->driver_data; 2165 pci_set_drvdata(pdev, ae_dev); 2166 2167 ret = hnae3_register_ae_dev(ae_dev); 2168 if (ret) 2169 pci_set_drvdata(pdev, NULL); 2170 2171 return ret; 2172 } 2173 2174 /* hns3_remove - Device removal routine 2175 * @pdev: PCI device information struct 2176 */ 2177 static void hns3_remove(struct pci_dev *pdev) 2178 { 2179 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2180 2181 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 2182 hns3_disable_sriov(pdev); 2183 2184 hnae3_unregister_ae_dev(ae_dev); 2185 pci_set_drvdata(pdev, NULL); 2186 } 2187 2188 /** 2189 * hns3_pci_sriov_configure 2190 * @pdev: pointer to a pci_dev structure 2191 * @num_vfs: number of VFs to allocate 2192 * 2193 * Enable or change the number of VFs. Called when the user updates the number 2194 * of VFs in sysfs. 2195 **/ 2196 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 2197 { 2198 int ret; 2199 2200 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 2201 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 2202 return -EINVAL; 2203 } 2204 2205 if (num_vfs) { 2206 ret = pci_enable_sriov(pdev, num_vfs); 2207 if (ret) 2208 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 2209 else 2210 return num_vfs; 2211 } else if (!pci_vfs_assigned(pdev)) { 2212 pci_disable_sriov(pdev); 2213 } else { 2214 dev_warn(&pdev->dev, 2215 "Unable to free VFs because some are assigned to VMs.\n"); 2216 } 2217 2218 return 0; 2219 } 2220 2221 static void hns3_shutdown(struct pci_dev *pdev) 2222 { 2223 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2224 2225 hnae3_unregister_ae_dev(ae_dev); 2226 pci_set_drvdata(pdev, NULL); 2227 2228 if (system_state == SYSTEM_POWER_OFF) 2229 pci_set_power_state(pdev, PCI_D3hot); 2230 } 2231 2232 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 2233 pci_channel_state_t state) 2234 { 2235 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2236 pci_ers_result_t ret; 2237 2238 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state); 2239 2240 if (state == pci_channel_io_perm_failure) 2241 return PCI_ERS_RESULT_DISCONNECT; 2242 2243 if (!ae_dev || !ae_dev->ops) { 2244 dev_err(&pdev->dev, 2245 "Can't recover - error happened before device initialized\n"); 2246 return PCI_ERS_RESULT_NONE; 2247 } 2248 2249 if (ae_dev->ops->handle_hw_ras_error) 2250 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 2251 else 2252 return PCI_ERS_RESULT_NONE; 2253 2254 return ret; 2255 } 2256 2257 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 2258 { 2259 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2260 const struct hnae3_ae_ops *ops; 2261 enum hnae3_reset_type reset_type; 2262 struct device *dev = &pdev->dev; 2263 2264 if (!ae_dev || !ae_dev->ops) 2265 return PCI_ERS_RESULT_NONE; 2266 2267 ops = ae_dev->ops; 2268 /* request the reset */ 2269 if (ops->reset_event && ops->get_reset_level && 2270 ops->set_default_reset_request) { 2271 if (ae_dev->hw_err_reset_req) { 2272 reset_type = ops->get_reset_level(ae_dev, 2273 &ae_dev->hw_err_reset_req); 2274 ops->set_default_reset_request(ae_dev, reset_type); 2275 dev_info(dev, "requesting reset due to PCI error\n"); 2276 ops->reset_event(pdev, NULL); 2277 } 2278 2279 return PCI_ERS_RESULT_RECOVERED; 2280 } 2281 2282 return PCI_ERS_RESULT_DISCONNECT; 2283 } 2284 2285 static void hns3_reset_prepare(struct pci_dev *pdev) 2286 { 2287 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2288 2289 dev_info(&pdev->dev, "FLR prepare\n"); 2290 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare) 2291 ae_dev->ops->flr_prepare(ae_dev); 2292 } 2293 2294 static void hns3_reset_done(struct pci_dev *pdev) 2295 { 2296 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2297 2298 dev_info(&pdev->dev, "FLR done\n"); 2299 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done) 2300 ae_dev->ops->flr_done(ae_dev); 2301 } 2302 2303 static const struct pci_error_handlers hns3_err_handler = { 2304 .error_detected = hns3_error_detected, 2305 .slot_reset = hns3_slot_reset, 2306 .reset_prepare = hns3_reset_prepare, 2307 .reset_done = hns3_reset_done, 2308 }; 2309 2310 static struct pci_driver hns3_driver = { 2311 .name = hns3_driver_name, 2312 .id_table = hns3_pci_tbl, 2313 .probe = hns3_probe, 2314 .remove = hns3_remove, 2315 .shutdown = hns3_shutdown, 2316 .sriov_configure = hns3_pci_sriov_configure, 2317 .err_handler = &hns3_err_handler, 2318 }; 2319 2320 /* set default feature to hns3 */ 2321 static void hns3_set_default_feature(struct net_device *netdev) 2322 { 2323 struct hnae3_handle *h = hns3_get_handle(netdev); 2324 struct pci_dev *pdev = h->pdev; 2325 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2326 2327 netdev->priv_flags |= IFF_UNICAST_FLT; 2328 2329 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2330 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2331 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2332 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2333 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2334 NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST; 2335 2336 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 2337 2338 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2339 NETIF_F_HW_VLAN_CTAG_FILTER | 2340 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2341 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2342 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2343 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2344 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2345 NETIF_F_FRAGLIST; 2346 2347 netdev->vlan_features |= 2348 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | 2349 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 2350 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2351 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2352 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2353 NETIF_F_FRAGLIST; 2354 2355 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2356 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2357 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2358 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2359 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2360 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2361 NETIF_F_FRAGLIST; 2362 2363 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2364 netdev->hw_features |= NETIF_F_GRO_HW; 2365 netdev->features |= NETIF_F_GRO_HW; 2366 2367 if (!(h->flags & HNAE3_SUPPORT_VF)) { 2368 netdev->hw_features |= NETIF_F_NTUPLE; 2369 netdev->features |= NETIF_F_NTUPLE; 2370 } 2371 } 2372 2373 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps)) { 2374 netdev->hw_features |= NETIF_F_GSO_UDP_L4; 2375 netdev->features |= NETIF_F_GSO_UDP_L4; 2376 netdev->vlan_features |= NETIF_F_GSO_UDP_L4; 2377 netdev->hw_enc_features |= NETIF_F_GSO_UDP_L4; 2378 } 2379 } 2380 2381 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 2382 struct hns3_desc_cb *cb) 2383 { 2384 unsigned int order = hns3_page_order(ring); 2385 struct page *p; 2386 2387 p = dev_alloc_pages(order); 2388 if (!p) 2389 return -ENOMEM; 2390 2391 cb->priv = p; 2392 cb->page_offset = 0; 2393 cb->reuse_flag = 0; 2394 cb->buf = page_address(p); 2395 cb->length = hns3_page_size(ring); 2396 cb->type = DESC_TYPE_PAGE; 2397 page_ref_add(p, USHRT_MAX - 1); 2398 cb->pagecnt_bias = USHRT_MAX; 2399 2400 return 0; 2401 } 2402 2403 static void hns3_free_buffer(struct hns3_enet_ring *ring, 2404 struct hns3_desc_cb *cb, int budget) 2405 { 2406 if (cb->type == DESC_TYPE_SKB) 2407 napi_consume_skb(cb->priv, budget); 2408 else if (!HNAE3_IS_TX_RING(ring) && cb->pagecnt_bias) 2409 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias); 2410 memset(cb, 0, sizeof(*cb)); 2411 } 2412 2413 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 2414 { 2415 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 2416 cb->length, ring_to_dma_dir(ring)); 2417 2418 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 2419 return -EIO; 2420 2421 return 0; 2422 } 2423 2424 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 2425 struct hns3_desc_cb *cb) 2426 { 2427 if (cb->type == DESC_TYPE_SKB || cb->type == DESC_TYPE_FRAGLIST_SKB) 2428 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 2429 ring_to_dma_dir(ring)); 2430 else if (cb->length) 2431 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 2432 ring_to_dma_dir(ring)); 2433 } 2434 2435 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 2436 { 2437 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2438 ring->desc[i].addr = 0; 2439 } 2440 2441 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i, 2442 int budget) 2443 { 2444 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 2445 2446 if (!ring->desc_cb[i].dma) 2447 return; 2448 2449 hns3_buffer_detach(ring, i); 2450 hns3_free_buffer(ring, cb, budget); 2451 } 2452 2453 static void hns3_free_buffers(struct hns3_enet_ring *ring) 2454 { 2455 int i; 2456 2457 for (i = 0; i < ring->desc_num; i++) 2458 hns3_free_buffer_detach(ring, i, 0); 2459 } 2460 2461 /* free desc along with its attached buffer */ 2462 static void hns3_free_desc(struct hns3_enet_ring *ring) 2463 { 2464 int size = ring->desc_num * sizeof(ring->desc[0]); 2465 2466 hns3_free_buffers(ring); 2467 2468 if (ring->desc) { 2469 dma_free_coherent(ring_to_dev(ring), size, 2470 ring->desc, ring->desc_dma_addr); 2471 ring->desc = NULL; 2472 } 2473 } 2474 2475 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 2476 { 2477 int size = ring->desc_num * sizeof(ring->desc[0]); 2478 2479 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 2480 &ring->desc_dma_addr, GFP_KERNEL); 2481 if (!ring->desc) 2482 return -ENOMEM; 2483 2484 return 0; 2485 } 2486 2487 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring, 2488 struct hns3_desc_cb *cb) 2489 { 2490 int ret; 2491 2492 ret = hns3_alloc_buffer(ring, cb); 2493 if (ret) 2494 goto out; 2495 2496 ret = hns3_map_buffer(ring, cb); 2497 if (ret) 2498 goto out_with_buf; 2499 2500 return 0; 2501 2502 out_with_buf: 2503 hns3_free_buffer(ring, cb, 0); 2504 out: 2505 return ret; 2506 } 2507 2508 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i) 2509 { 2510 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]); 2511 2512 if (ret) 2513 return ret; 2514 2515 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2516 2517 return 0; 2518 } 2519 2520 /* Allocate memory for raw pkg, and map with dma */ 2521 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 2522 { 2523 int i, j, ret; 2524 2525 for (i = 0; i < ring->desc_num; i++) { 2526 ret = hns3_alloc_and_attach_buffer(ring, i); 2527 if (ret) 2528 goto out_buffer_fail; 2529 } 2530 2531 return 0; 2532 2533 out_buffer_fail: 2534 for (j = i - 1; j >= 0; j--) 2535 hns3_free_buffer_detach(ring, j, 0); 2536 return ret; 2537 } 2538 2539 /* detach a in-used buffer and replace with a reserved one */ 2540 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 2541 struct hns3_desc_cb *res_cb) 2542 { 2543 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2544 ring->desc_cb[i] = *res_cb; 2545 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2546 ring->desc[i].rx.bd_base_info = 0; 2547 } 2548 2549 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 2550 { 2551 ring->desc_cb[i].reuse_flag = 0; 2552 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 2553 ring->desc_cb[i].page_offset); 2554 ring->desc[i].rx.bd_base_info = 0; 2555 2556 dma_sync_single_for_device(ring_to_dev(ring), 2557 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset, 2558 hns3_buf_size(ring), 2559 DMA_FROM_DEVICE); 2560 } 2561 2562 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, 2563 int *bytes, int *pkts, int budget) 2564 { 2565 /* pair with ring->last_to_use update in hns3_tx_doorbell(), 2566 * smp_store_release() is not used in hns3_tx_doorbell() because 2567 * the doorbell operation already have the needed barrier operation. 2568 */ 2569 int ltu = smp_load_acquire(&ring->last_to_use); 2570 int ntc = ring->next_to_clean; 2571 struct hns3_desc_cb *desc_cb; 2572 bool reclaimed = false; 2573 struct hns3_desc *desc; 2574 2575 while (ltu != ntc) { 2576 desc = &ring->desc[ntc]; 2577 2578 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) & 2579 BIT(HNS3_TXD_VLD_B)) 2580 break; 2581 2582 desc_cb = &ring->desc_cb[ntc]; 2583 (*pkts) += (desc_cb->type == DESC_TYPE_SKB); 2584 (*bytes) += desc_cb->length; 2585 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */ 2586 hns3_free_buffer_detach(ring, ntc, budget); 2587 2588 if (++ntc == ring->desc_num) 2589 ntc = 0; 2590 2591 /* Issue prefetch for next Tx descriptor */ 2592 prefetch(&ring->desc_cb[ntc]); 2593 reclaimed = true; 2594 } 2595 2596 if (unlikely(!reclaimed)) 2597 return false; 2598 2599 /* This smp_store_release() pairs with smp_load_acquire() in 2600 * ring_space called by hns3_nic_net_xmit. 2601 */ 2602 smp_store_release(&ring->next_to_clean, ntc); 2603 return true; 2604 } 2605 2606 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget) 2607 { 2608 struct net_device *netdev = ring_to_netdev(ring); 2609 struct hns3_nic_priv *priv = netdev_priv(netdev); 2610 struct netdev_queue *dev_queue; 2611 int bytes, pkts; 2612 2613 bytes = 0; 2614 pkts = 0; 2615 2616 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget))) 2617 return; 2618 2619 ring->tqp_vector->tx_group.total_bytes += bytes; 2620 ring->tqp_vector->tx_group.total_packets += pkts; 2621 2622 u64_stats_update_begin(&ring->syncp); 2623 ring->stats.tx_bytes += bytes; 2624 ring->stats.tx_pkts += pkts; 2625 u64_stats_update_end(&ring->syncp); 2626 2627 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 2628 netdev_tx_completed_queue(dev_queue, pkts, bytes); 2629 2630 if (unlikely(netif_carrier_ok(netdev) && 2631 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) { 2632 /* Make sure that anybody stopping the queue after this 2633 * sees the new next_to_clean. 2634 */ 2635 smp_mb(); 2636 if (netif_tx_queue_stopped(dev_queue) && 2637 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 2638 netif_tx_wake_queue(dev_queue); 2639 ring->stats.restart_queue++; 2640 } 2641 } 2642 } 2643 2644 static int hns3_desc_unused(struct hns3_enet_ring *ring) 2645 { 2646 int ntc = ring->next_to_clean; 2647 int ntu = ring->next_to_use; 2648 2649 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 2650 } 2651 2652 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, 2653 int cleand_count) 2654 { 2655 struct hns3_desc_cb *desc_cb; 2656 struct hns3_desc_cb res_cbs; 2657 int i, ret; 2658 2659 for (i = 0; i < cleand_count; i++) { 2660 desc_cb = &ring->desc_cb[ring->next_to_use]; 2661 if (desc_cb->reuse_flag) { 2662 u64_stats_update_begin(&ring->syncp); 2663 ring->stats.reuse_pg_cnt++; 2664 u64_stats_update_end(&ring->syncp); 2665 2666 hns3_reuse_buffer(ring, ring->next_to_use); 2667 } else { 2668 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 2669 if (ret) { 2670 u64_stats_update_begin(&ring->syncp); 2671 ring->stats.sw_err_cnt++; 2672 u64_stats_update_end(&ring->syncp); 2673 2674 hns3_rl_err(ring_to_netdev(ring), 2675 "alloc rx buffer failed: %d\n", 2676 ret); 2677 break; 2678 } 2679 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 2680 2681 u64_stats_update_begin(&ring->syncp); 2682 ring->stats.non_reuse_pg++; 2683 u64_stats_update_end(&ring->syncp); 2684 } 2685 2686 ring_ptr_move_fw(ring, next_to_use); 2687 } 2688 2689 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2690 } 2691 2692 static bool hns3_page_is_reusable(struct page *page) 2693 { 2694 return page_to_nid(page) == numa_mem_id() && 2695 !page_is_pfmemalloc(page); 2696 } 2697 2698 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb) 2699 { 2700 return (page_count(cb->priv) - cb->pagecnt_bias) == 1; 2701 } 2702 2703 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2704 struct hns3_enet_ring *ring, int pull_len, 2705 struct hns3_desc_cb *desc_cb) 2706 { 2707 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 2708 int size = le16_to_cpu(desc->rx.size); 2709 u32 truesize = hns3_buf_size(ring); 2710 2711 desc_cb->pagecnt_bias--; 2712 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2713 size - pull_len, truesize); 2714 2715 /* Avoid re-using remote pages, or the stack is still using the page 2716 * when page_offset rollback to zero, flag default unreuse 2717 */ 2718 if (unlikely(!hns3_page_is_reusable(desc_cb->priv)) || 2719 (!desc_cb->page_offset && !hns3_can_reuse_page(desc_cb))) { 2720 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias); 2721 return; 2722 } 2723 2724 /* Move offset up to the next cache line */ 2725 desc_cb->page_offset += truesize; 2726 2727 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) { 2728 desc_cb->reuse_flag = 1; 2729 } else if (hns3_can_reuse_page(desc_cb)) { 2730 desc_cb->reuse_flag = 1; 2731 desc_cb->page_offset = 0; 2732 } else if (desc_cb->pagecnt_bias) { 2733 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias); 2734 return; 2735 } 2736 2737 if (unlikely(!desc_cb->pagecnt_bias)) { 2738 page_ref_add(desc_cb->priv, USHRT_MAX); 2739 desc_cb->pagecnt_bias = USHRT_MAX; 2740 } 2741 } 2742 2743 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) 2744 { 2745 __be16 type = skb->protocol; 2746 struct tcphdr *th; 2747 int depth = 0; 2748 2749 while (eth_type_vlan(type)) { 2750 struct vlan_hdr *vh; 2751 2752 if ((depth + VLAN_HLEN) > skb_headlen(skb)) 2753 return -EFAULT; 2754 2755 vh = (struct vlan_hdr *)(skb->data + depth); 2756 type = vh->h_vlan_encapsulated_proto; 2757 depth += VLAN_HLEN; 2758 } 2759 2760 skb_set_network_header(skb, depth); 2761 2762 if (type == htons(ETH_P_IP)) { 2763 const struct iphdr *iph = ip_hdr(skb); 2764 2765 depth += sizeof(struct iphdr); 2766 skb_set_transport_header(skb, depth); 2767 th = tcp_hdr(skb); 2768 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr, 2769 iph->daddr, 0); 2770 } else if (type == htons(ETH_P_IPV6)) { 2771 const struct ipv6hdr *iph = ipv6_hdr(skb); 2772 2773 depth += sizeof(struct ipv6hdr); 2774 skb_set_transport_header(skb, depth); 2775 th = tcp_hdr(skb); 2776 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr, 2777 &iph->daddr, 0); 2778 } else { 2779 hns3_rl_err(skb->dev, 2780 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n", 2781 be16_to_cpu(type), depth); 2782 return -EFAULT; 2783 } 2784 2785 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 2786 if (th->cwr) 2787 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 2788 2789 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B)) 2790 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID; 2791 2792 skb->csum_start = (unsigned char *)th - skb->head; 2793 skb->csum_offset = offsetof(struct tcphdr, check); 2794 skb->ip_summed = CHECKSUM_PARTIAL; 2795 2796 trace_hns3_gro(skb); 2797 2798 return 0; 2799 } 2800 2801 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2802 u32 l234info, u32 bd_base_info, u32 ol_info) 2803 { 2804 struct net_device *netdev = ring_to_netdev(ring); 2805 int l3_type, l4_type; 2806 int ol4_type; 2807 2808 skb->ip_summed = CHECKSUM_NONE; 2809 2810 skb_checksum_none_assert(skb); 2811 2812 if (!(netdev->features & NETIF_F_RXCSUM)) 2813 return; 2814 2815 /* check if hardware has done checksum */ 2816 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 2817 return; 2818 2819 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | 2820 BIT(HNS3_RXD_OL3E_B) | 2821 BIT(HNS3_RXD_OL4E_B)))) { 2822 u64_stats_update_begin(&ring->syncp); 2823 ring->stats.l3l4_csum_err++; 2824 u64_stats_update_end(&ring->syncp); 2825 2826 return; 2827 } 2828 2829 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M, 2830 HNS3_RXD_OL4ID_S); 2831 switch (ol4_type) { 2832 case HNS3_OL4_TYPE_MAC_IN_UDP: 2833 case HNS3_OL4_TYPE_NVGRE: 2834 skb->csum_level = 1; 2835 fallthrough; 2836 case HNS3_OL4_TYPE_NO_TUN: 2837 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2838 HNS3_RXD_L3ID_S); 2839 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 2840 HNS3_RXD_L4ID_S); 2841 2842 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 2843 if ((l3_type == HNS3_L3_TYPE_IPV4 || 2844 l3_type == HNS3_L3_TYPE_IPV6) && 2845 (l4_type == HNS3_L4_TYPE_UDP || 2846 l4_type == HNS3_L4_TYPE_TCP || 2847 l4_type == HNS3_L4_TYPE_SCTP)) 2848 skb->ip_summed = CHECKSUM_UNNECESSARY; 2849 break; 2850 default: 2851 break; 2852 } 2853 } 2854 2855 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 2856 { 2857 if (skb_has_frag_list(skb)) 2858 napi_gro_flush(&ring->tqp_vector->napi, false); 2859 2860 napi_gro_receive(&ring->tqp_vector->napi, skb); 2861 } 2862 2863 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 2864 struct hns3_desc *desc, u32 l234info, 2865 u16 *vlan_tag) 2866 { 2867 struct hnae3_handle *handle = ring->tqp->handle; 2868 struct pci_dev *pdev = ring->tqp->handle->pdev; 2869 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2870 2871 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) { 2872 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2873 if (!(*vlan_tag & VLAN_VID_MASK)) 2874 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2875 2876 return (*vlan_tag != 0); 2877 } 2878 2879 #define HNS3_STRP_OUTER_VLAN 0x1 2880 #define HNS3_STRP_INNER_VLAN 0x2 2881 #define HNS3_STRP_BOTH 0x3 2882 2883 /* Hardware always insert VLAN tag into RX descriptor when 2884 * remove the tag from packet, driver needs to determine 2885 * reporting which tag to stack. 2886 */ 2887 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 2888 HNS3_RXD_STRP_TAGP_S)) { 2889 case HNS3_STRP_OUTER_VLAN: 2890 if (handle->port_base_vlan_state != 2891 HNAE3_PORT_BASE_VLAN_DISABLE) 2892 return false; 2893 2894 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2895 return true; 2896 case HNS3_STRP_INNER_VLAN: 2897 if (handle->port_base_vlan_state != 2898 HNAE3_PORT_BASE_VLAN_DISABLE) 2899 return false; 2900 2901 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2902 return true; 2903 case HNS3_STRP_BOTH: 2904 if (handle->port_base_vlan_state == 2905 HNAE3_PORT_BASE_VLAN_DISABLE) 2906 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2907 else 2908 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2909 2910 return true; 2911 default: 2912 return false; 2913 } 2914 } 2915 2916 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring) 2917 { 2918 ring->desc[ring->next_to_clean].rx.bd_base_info &= 2919 cpu_to_le32(~BIT(HNS3_RXD_VLD_B)); 2920 ring->next_to_clean += 1; 2921 2922 if (unlikely(ring->next_to_clean == ring->desc_num)) 2923 ring->next_to_clean = 0; 2924 } 2925 2926 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length, 2927 unsigned char *va) 2928 { 2929 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2930 struct net_device *netdev = ring_to_netdev(ring); 2931 struct sk_buff *skb; 2932 2933 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 2934 skb = ring->skb; 2935 if (unlikely(!skb)) { 2936 hns3_rl_err(netdev, "alloc rx skb fail\n"); 2937 2938 u64_stats_update_begin(&ring->syncp); 2939 ring->stats.sw_err_cnt++; 2940 u64_stats_update_end(&ring->syncp); 2941 2942 return -ENOMEM; 2943 } 2944 2945 trace_hns3_rx_desc(ring); 2946 prefetchw(skb->data); 2947 2948 ring->pending_buf = 1; 2949 ring->frag_num = 0; 2950 ring->tail_skb = NULL; 2951 if (length <= HNS3_RX_HEAD_SIZE) { 2952 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 2953 2954 /* We can reuse buffer as-is, just make sure it is local */ 2955 if (likely(hns3_page_is_reusable(desc_cb->priv))) 2956 desc_cb->reuse_flag = 1; 2957 else /* This page cannot be reused so discard it */ 2958 __page_frag_cache_drain(desc_cb->priv, 2959 desc_cb->pagecnt_bias); 2960 2961 hns3_rx_ring_move_fw(ring); 2962 return 0; 2963 } 2964 u64_stats_update_begin(&ring->syncp); 2965 ring->stats.seg_pkt_cnt++; 2966 u64_stats_update_end(&ring->syncp); 2967 2968 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE); 2969 __skb_put(skb, ring->pull_len); 2970 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 2971 desc_cb); 2972 hns3_rx_ring_move_fw(ring); 2973 2974 return 0; 2975 } 2976 2977 static int hns3_add_frag(struct hns3_enet_ring *ring) 2978 { 2979 struct sk_buff *skb = ring->skb; 2980 struct sk_buff *head_skb = skb; 2981 struct sk_buff *new_skb; 2982 struct hns3_desc_cb *desc_cb; 2983 struct hns3_desc *desc; 2984 u32 bd_base_info; 2985 2986 do { 2987 desc = &ring->desc[ring->next_to_clean]; 2988 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2989 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2990 /* make sure HW write desc complete */ 2991 dma_rmb(); 2992 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 2993 return -ENXIO; 2994 2995 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 2996 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0); 2997 if (unlikely(!new_skb)) { 2998 hns3_rl_err(ring_to_netdev(ring), 2999 "alloc rx fraglist skb fail\n"); 3000 return -ENXIO; 3001 } 3002 ring->frag_num = 0; 3003 3004 if (ring->tail_skb) { 3005 ring->tail_skb->next = new_skb; 3006 ring->tail_skb = new_skb; 3007 } else { 3008 skb_shinfo(skb)->frag_list = new_skb; 3009 ring->tail_skb = new_skb; 3010 } 3011 } 3012 3013 if (ring->tail_skb) { 3014 head_skb->truesize += hns3_buf_size(ring); 3015 head_skb->data_len += le16_to_cpu(desc->rx.size); 3016 head_skb->len += le16_to_cpu(desc->rx.size); 3017 skb = ring->tail_skb; 3018 } 3019 3020 dma_sync_single_for_cpu(ring_to_dev(ring), 3021 desc_cb->dma + desc_cb->page_offset, 3022 hns3_buf_size(ring), 3023 DMA_FROM_DEVICE); 3024 3025 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 3026 trace_hns3_rx_desc(ring); 3027 hns3_rx_ring_move_fw(ring); 3028 ring->pending_buf++; 3029 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B))); 3030 3031 return 0; 3032 } 3033 3034 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring, 3035 struct sk_buff *skb, u32 l234info, 3036 u32 bd_base_info, u32 ol_info) 3037 { 3038 u32 l3_type; 3039 3040 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 3041 HNS3_RXD_GRO_SIZE_M, 3042 HNS3_RXD_GRO_SIZE_S); 3043 /* if there is no HW GRO, do not set gro params */ 3044 if (!skb_shinfo(skb)->gso_size) { 3045 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info); 3046 return 0; 3047 } 3048 3049 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info, 3050 HNS3_RXD_GRO_COUNT_M, 3051 HNS3_RXD_GRO_COUNT_S); 3052 3053 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S); 3054 if (l3_type == HNS3_L3_TYPE_IPV4) 3055 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 3056 else if (l3_type == HNS3_L3_TYPE_IPV6) 3057 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 3058 else 3059 return -EFAULT; 3060 3061 return hns3_gro_complete(skb, l234info); 3062 } 3063 3064 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 3065 struct sk_buff *skb, u32 rss_hash) 3066 { 3067 struct hnae3_handle *handle = ring->tqp->handle; 3068 enum pkt_hash_types rss_type; 3069 3070 if (rss_hash) 3071 rss_type = handle->kinfo.rss_type; 3072 else 3073 rss_type = PKT_HASH_TYPE_NONE; 3074 3075 skb_set_hash(skb, rss_hash, rss_type); 3076 } 3077 3078 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb) 3079 { 3080 struct net_device *netdev = ring_to_netdev(ring); 3081 enum hns3_pkt_l2t_type l2_frame_type; 3082 u32 bd_base_info, l234info, ol_info; 3083 struct hns3_desc *desc; 3084 unsigned int len; 3085 int pre_ntc, ret; 3086 3087 /* bdinfo handled below is only valid on the last BD of the 3088 * current packet, and ring->next_to_clean indicates the first 3089 * descriptor of next packet, so need - 1 below. 3090 */ 3091 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) : 3092 (ring->desc_num - 1); 3093 desc = &ring->desc[pre_ntc]; 3094 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3095 l234info = le32_to_cpu(desc->rx.l234_info); 3096 ol_info = le32_to_cpu(desc->rx.ol_info); 3097 3098 /* Based on hw strategy, the tag offloaded will be stored at 3099 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 3100 * in one layer tag case. 3101 */ 3102 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 3103 u16 vlan_tag; 3104 3105 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 3106 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 3107 vlan_tag); 3108 } 3109 3110 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 3111 BIT(HNS3_RXD_L2E_B))))) { 3112 u64_stats_update_begin(&ring->syncp); 3113 if (l234info & BIT(HNS3_RXD_L2E_B)) 3114 ring->stats.l2_err++; 3115 else 3116 ring->stats.err_pkt_len++; 3117 u64_stats_update_end(&ring->syncp); 3118 3119 return -EFAULT; 3120 } 3121 3122 len = skb->len; 3123 3124 /* Do update ip stack process */ 3125 skb->protocol = eth_type_trans(skb, netdev); 3126 3127 /* This is needed in order to enable forwarding support */ 3128 ret = hns3_set_gro_and_checksum(ring, skb, l234info, 3129 bd_base_info, ol_info); 3130 if (unlikely(ret)) { 3131 u64_stats_update_begin(&ring->syncp); 3132 ring->stats.rx_err_cnt++; 3133 u64_stats_update_end(&ring->syncp); 3134 return ret; 3135 } 3136 3137 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 3138 HNS3_RXD_DMAC_S); 3139 3140 u64_stats_update_begin(&ring->syncp); 3141 ring->stats.rx_pkts++; 3142 ring->stats.rx_bytes += len; 3143 3144 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 3145 ring->stats.rx_multicast++; 3146 3147 u64_stats_update_end(&ring->syncp); 3148 3149 ring->tqp_vector->rx_group.total_bytes += len; 3150 3151 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash)); 3152 return 0; 3153 } 3154 3155 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring) 3156 { 3157 struct sk_buff *skb = ring->skb; 3158 struct hns3_desc_cb *desc_cb; 3159 struct hns3_desc *desc; 3160 unsigned int length; 3161 u32 bd_base_info; 3162 int ret; 3163 3164 desc = &ring->desc[ring->next_to_clean]; 3165 desc_cb = &ring->desc_cb[ring->next_to_clean]; 3166 3167 prefetch(desc); 3168 3169 if (!skb) { 3170 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3171 3172 /* Check valid BD */ 3173 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 3174 return -ENXIO; 3175 3176 dma_rmb(); 3177 length = le16_to_cpu(desc->rx.size); 3178 3179 ring->va = desc_cb->buf + desc_cb->page_offset; 3180 3181 dma_sync_single_for_cpu(ring_to_dev(ring), 3182 desc_cb->dma + desc_cb->page_offset, 3183 hns3_buf_size(ring), 3184 DMA_FROM_DEVICE); 3185 3186 /* Prefetch first cache line of first page. 3187 * Idea is to cache few bytes of the header of the packet. 3188 * Our L1 Cache line size is 64B so need to prefetch twice to make 3189 * it 128B. But in actual we can have greater size of caches with 3190 * 128B Level 1 cache lines. In such a case, single fetch would 3191 * suffice to cache in the relevant part of the header. 3192 */ 3193 net_prefetch(ring->va); 3194 3195 ret = hns3_alloc_skb(ring, length, ring->va); 3196 skb = ring->skb; 3197 3198 if (ret < 0) /* alloc buffer fail */ 3199 return ret; 3200 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */ 3201 ret = hns3_add_frag(ring); 3202 if (ret) 3203 return ret; 3204 } 3205 } else { 3206 ret = hns3_add_frag(ring); 3207 if (ret) 3208 return ret; 3209 } 3210 3211 /* As the head data may be changed when GRO enable, copy 3212 * the head data in after other data rx completed 3213 */ 3214 if (skb->len > HNS3_RX_HEAD_SIZE) 3215 memcpy(skb->data, ring->va, 3216 ALIGN(ring->pull_len, sizeof(long))); 3217 3218 ret = hns3_handle_bdinfo(ring, skb); 3219 if (unlikely(ret)) { 3220 dev_kfree_skb_any(skb); 3221 return ret; 3222 } 3223 3224 skb_record_rx_queue(skb, ring->tqp->tqp_index); 3225 return 0; 3226 } 3227 3228 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget, 3229 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 3230 { 3231 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 3232 int unused_count = hns3_desc_unused(ring); 3233 int recv_pkts = 0; 3234 int err; 3235 3236 unused_count -= ring->pending_buf; 3237 3238 while (recv_pkts < budget) { 3239 /* Reuse or realloc buffers */ 3240 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 3241 hns3_nic_alloc_rx_buffers(ring, unused_count); 3242 unused_count = hns3_desc_unused(ring) - 3243 ring->pending_buf; 3244 } 3245 3246 /* Poll one pkt */ 3247 err = hns3_handle_rx_bd(ring); 3248 /* Do not get FE for the packet or failed to alloc skb */ 3249 if (unlikely(!ring->skb || err == -ENXIO)) { 3250 goto out; 3251 } else if (likely(!err)) { 3252 rx_fn(ring, ring->skb); 3253 recv_pkts++; 3254 } 3255 3256 unused_count += ring->pending_buf; 3257 ring->skb = NULL; 3258 ring->pending_buf = 0; 3259 } 3260 3261 out: 3262 /* Make all data has been write before submit */ 3263 if (unused_count > 0) 3264 hns3_nic_alloc_rx_buffers(ring, unused_count); 3265 3266 return recv_pkts; 3267 } 3268 3269 static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group) 3270 { 3271 #define HNS3_RX_LOW_BYTE_RATE 10000 3272 #define HNS3_RX_MID_BYTE_RATE 20000 3273 #define HNS3_RX_ULTRA_PACKET_RATE 40 3274 3275 enum hns3_flow_level_range new_flow_level; 3276 struct hns3_enet_tqp_vector *tqp_vector; 3277 int packets_per_msecs, bytes_per_msecs; 3278 u32 time_passed_ms; 3279 3280 tqp_vector = ring_group->ring->tqp_vector; 3281 time_passed_ms = 3282 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 3283 if (!time_passed_ms) 3284 return false; 3285 3286 do_div(ring_group->total_packets, time_passed_ms); 3287 packets_per_msecs = ring_group->total_packets; 3288 3289 do_div(ring_group->total_bytes, time_passed_ms); 3290 bytes_per_msecs = ring_group->total_bytes; 3291 3292 new_flow_level = ring_group->coal.flow_level; 3293 3294 /* Simple throttlerate management 3295 * 0-10MB/s lower (50000 ints/s) 3296 * 10-20MB/s middle (20000 ints/s) 3297 * 20-1249MB/s high (18000 ints/s) 3298 * > 40000pps ultra (8000 ints/s) 3299 */ 3300 switch (new_flow_level) { 3301 case HNS3_FLOW_LOW: 3302 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 3303 new_flow_level = HNS3_FLOW_MID; 3304 break; 3305 case HNS3_FLOW_MID: 3306 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 3307 new_flow_level = HNS3_FLOW_HIGH; 3308 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 3309 new_flow_level = HNS3_FLOW_LOW; 3310 break; 3311 case HNS3_FLOW_HIGH: 3312 case HNS3_FLOW_ULTRA: 3313 default: 3314 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 3315 new_flow_level = HNS3_FLOW_MID; 3316 break; 3317 } 3318 3319 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 3320 &tqp_vector->rx_group == ring_group) 3321 new_flow_level = HNS3_FLOW_ULTRA; 3322 3323 ring_group->total_bytes = 0; 3324 ring_group->total_packets = 0; 3325 ring_group->coal.flow_level = new_flow_level; 3326 3327 return true; 3328 } 3329 3330 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 3331 { 3332 struct hns3_enet_tqp_vector *tqp_vector; 3333 u16 new_int_gl; 3334 3335 if (!ring_group->ring) 3336 return false; 3337 3338 tqp_vector = ring_group->ring->tqp_vector; 3339 if (!tqp_vector->last_jiffies) 3340 return false; 3341 3342 if (ring_group->total_packets == 0) { 3343 ring_group->coal.int_gl = HNS3_INT_GL_50K; 3344 ring_group->coal.flow_level = HNS3_FLOW_LOW; 3345 return true; 3346 } 3347 3348 if (!hns3_get_new_flow_lvl(ring_group)) 3349 return false; 3350 3351 new_int_gl = ring_group->coal.int_gl; 3352 switch (ring_group->coal.flow_level) { 3353 case HNS3_FLOW_LOW: 3354 new_int_gl = HNS3_INT_GL_50K; 3355 break; 3356 case HNS3_FLOW_MID: 3357 new_int_gl = HNS3_INT_GL_20K; 3358 break; 3359 case HNS3_FLOW_HIGH: 3360 new_int_gl = HNS3_INT_GL_18K; 3361 break; 3362 case HNS3_FLOW_ULTRA: 3363 new_int_gl = HNS3_INT_GL_8K; 3364 break; 3365 default: 3366 break; 3367 } 3368 3369 if (new_int_gl != ring_group->coal.int_gl) { 3370 ring_group->coal.int_gl = new_int_gl; 3371 return true; 3372 } 3373 return false; 3374 } 3375 3376 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 3377 { 3378 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 3379 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 3380 bool rx_update, tx_update; 3381 3382 /* update param every 1000ms */ 3383 if (time_before(jiffies, 3384 tqp_vector->last_jiffies + msecs_to_jiffies(1000))) 3385 return; 3386 3387 if (rx_group->coal.adapt_enable) { 3388 rx_update = hns3_get_new_int_gl(rx_group); 3389 if (rx_update) 3390 hns3_set_vector_coalesce_rx_gl(tqp_vector, 3391 rx_group->coal.int_gl); 3392 } 3393 3394 if (tx_group->coal.adapt_enable) { 3395 tx_update = hns3_get_new_int_gl(tx_group); 3396 if (tx_update) 3397 hns3_set_vector_coalesce_tx_gl(tqp_vector, 3398 tx_group->coal.int_gl); 3399 } 3400 3401 tqp_vector->last_jiffies = jiffies; 3402 } 3403 3404 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 3405 { 3406 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 3407 struct hns3_enet_ring *ring; 3408 int rx_pkt_total = 0; 3409 3410 struct hns3_enet_tqp_vector *tqp_vector = 3411 container_of(napi, struct hns3_enet_tqp_vector, napi); 3412 bool clean_complete = true; 3413 int rx_budget = budget; 3414 3415 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3416 napi_complete(napi); 3417 return 0; 3418 } 3419 3420 /* Since the actual Tx work is minimal, we can give the Tx a larger 3421 * budget and be more aggressive about cleaning up the Tx descriptors. 3422 */ 3423 hns3_for_each_ring(ring, tqp_vector->tx_group) 3424 hns3_clean_tx_ring(ring, budget); 3425 3426 /* make sure rx ring budget not smaller than 1 */ 3427 if (tqp_vector->num_tqps > 1) 3428 rx_budget = max(budget / tqp_vector->num_tqps, 1); 3429 3430 hns3_for_each_ring(ring, tqp_vector->rx_group) { 3431 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 3432 hns3_rx_skb); 3433 3434 if (rx_cleaned >= rx_budget) 3435 clean_complete = false; 3436 3437 rx_pkt_total += rx_cleaned; 3438 } 3439 3440 tqp_vector->rx_group.total_packets += rx_pkt_total; 3441 3442 if (!clean_complete) 3443 return budget; 3444 3445 if (napi_complete(napi) && 3446 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3447 hns3_update_new_int_gl(tqp_vector); 3448 hns3_mask_vector_irq(tqp_vector, 1); 3449 } 3450 3451 return rx_pkt_total; 3452 } 3453 3454 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3455 struct hnae3_ring_chain_node *head) 3456 { 3457 struct pci_dev *pdev = tqp_vector->handle->pdev; 3458 struct hnae3_ring_chain_node *cur_chain = head; 3459 struct hnae3_ring_chain_node *chain; 3460 struct hns3_enet_ring *tx_ring; 3461 struct hns3_enet_ring *rx_ring; 3462 3463 tx_ring = tqp_vector->tx_group.ring; 3464 if (tx_ring) { 3465 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 3466 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3467 HNAE3_RING_TYPE_TX); 3468 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3469 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 3470 3471 cur_chain->next = NULL; 3472 3473 while (tx_ring->next) { 3474 tx_ring = tx_ring->next; 3475 3476 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 3477 GFP_KERNEL); 3478 if (!chain) 3479 goto err_free_chain; 3480 3481 cur_chain->next = chain; 3482 chain->tqp_index = tx_ring->tqp->tqp_index; 3483 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3484 HNAE3_RING_TYPE_TX); 3485 hnae3_set_field(chain->int_gl_idx, 3486 HNAE3_RING_GL_IDX_M, 3487 HNAE3_RING_GL_IDX_S, 3488 HNAE3_RING_GL_TX); 3489 3490 cur_chain = chain; 3491 } 3492 } 3493 3494 rx_ring = tqp_vector->rx_group.ring; 3495 if (!tx_ring && rx_ring) { 3496 cur_chain->next = NULL; 3497 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 3498 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3499 HNAE3_RING_TYPE_RX); 3500 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3501 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3502 3503 rx_ring = rx_ring->next; 3504 } 3505 3506 while (rx_ring) { 3507 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 3508 if (!chain) 3509 goto err_free_chain; 3510 3511 cur_chain->next = chain; 3512 chain->tqp_index = rx_ring->tqp->tqp_index; 3513 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3514 HNAE3_RING_TYPE_RX); 3515 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3516 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3517 3518 cur_chain = chain; 3519 3520 rx_ring = rx_ring->next; 3521 } 3522 3523 return 0; 3524 3525 err_free_chain: 3526 cur_chain = head->next; 3527 while (cur_chain) { 3528 chain = cur_chain->next; 3529 devm_kfree(&pdev->dev, cur_chain); 3530 cur_chain = chain; 3531 } 3532 head->next = NULL; 3533 3534 return -ENOMEM; 3535 } 3536 3537 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3538 struct hnae3_ring_chain_node *head) 3539 { 3540 struct pci_dev *pdev = tqp_vector->handle->pdev; 3541 struct hnae3_ring_chain_node *chain_tmp, *chain; 3542 3543 chain = head->next; 3544 3545 while (chain) { 3546 chain_tmp = chain->next; 3547 devm_kfree(&pdev->dev, chain); 3548 chain = chain_tmp; 3549 } 3550 } 3551 3552 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 3553 struct hns3_enet_ring *ring) 3554 { 3555 ring->next = group->ring; 3556 group->ring = ring; 3557 3558 group->count++; 3559 } 3560 3561 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 3562 { 3563 struct pci_dev *pdev = priv->ae_handle->pdev; 3564 struct hns3_enet_tqp_vector *tqp_vector; 3565 int num_vectors = priv->vector_num; 3566 int numa_node; 3567 int vector_i; 3568 3569 numa_node = dev_to_node(&pdev->dev); 3570 3571 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 3572 tqp_vector = &priv->tqp_vector[vector_i]; 3573 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 3574 &tqp_vector->affinity_mask); 3575 } 3576 } 3577 3578 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 3579 { 3580 struct hnae3_ring_chain_node vector_ring_chain; 3581 struct hnae3_handle *h = priv->ae_handle; 3582 struct hns3_enet_tqp_vector *tqp_vector; 3583 int ret; 3584 int i; 3585 3586 hns3_nic_set_cpumask(priv); 3587 3588 for (i = 0; i < priv->vector_num; i++) { 3589 tqp_vector = &priv->tqp_vector[i]; 3590 hns3_vector_coalesce_init_hw(tqp_vector, priv); 3591 tqp_vector->num_tqps = 0; 3592 } 3593 3594 for (i = 0; i < h->kinfo.num_tqps; i++) { 3595 u16 vector_i = i % priv->vector_num; 3596 u16 tqp_num = h->kinfo.num_tqps; 3597 3598 tqp_vector = &priv->tqp_vector[vector_i]; 3599 3600 hns3_add_ring_to_group(&tqp_vector->tx_group, 3601 &priv->ring[i]); 3602 3603 hns3_add_ring_to_group(&tqp_vector->rx_group, 3604 &priv->ring[i + tqp_num]); 3605 3606 priv->ring[i].tqp_vector = tqp_vector; 3607 priv->ring[i + tqp_num].tqp_vector = tqp_vector; 3608 tqp_vector->num_tqps++; 3609 } 3610 3611 for (i = 0; i < priv->vector_num; i++) { 3612 tqp_vector = &priv->tqp_vector[i]; 3613 3614 tqp_vector->rx_group.total_bytes = 0; 3615 tqp_vector->rx_group.total_packets = 0; 3616 tqp_vector->tx_group.total_bytes = 0; 3617 tqp_vector->tx_group.total_packets = 0; 3618 tqp_vector->handle = h; 3619 3620 ret = hns3_get_vector_ring_chain(tqp_vector, 3621 &vector_ring_chain); 3622 if (ret) 3623 goto map_ring_fail; 3624 3625 ret = h->ae_algo->ops->map_ring_to_vector(h, 3626 tqp_vector->vector_irq, &vector_ring_chain); 3627 3628 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3629 3630 if (ret) 3631 goto map_ring_fail; 3632 3633 netif_napi_add(priv->netdev, &tqp_vector->napi, 3634 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 3635 } 3636 3637 return 0; 3638 3639 map_ring_fail: 3640 while (i--) 3641 netif_napi_del(&priv->tqp_vector[i].napi); 3642 3643 return ret; 3644 } 3645 3646 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 3647 { 3648 #define HNS3_VECTOR_PF_MAX_NUM 64 3649 3650 struct hnae3_handle *h = priv->ae_handle; 3651 struct hns3_enet_tqp_vector *tqp_vector; 3652 struct hnae3_vector_info *vector; 3653 struct pci_dev *pdev = h->pdev; 3654 u16 tqp_num = h->kinfo.num_tqps; 3655 u16 vector_num; 3656 int ret = 0; 3657 u16 i; 3658 3659 /* RSS size, cpu online and vector_num should be the same */ 3660 /* Should consider 2p/4p later */ 3661 vector_num = min_t(u16, num_online_cpus(), tqp_num); 3662 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM); 3663 3664 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 3665 GFP_KERNEL); 3666 if (!vector) 3667 return -ENOMEM; 3668 3669 /* save the actual available vector number */ 3670 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 3671 3672 priv->vector_num = vector_num; 3673 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 3674 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 3675 GFP_KERNEL); 3676 if (!priv->tqp_vector) { 3677 ret = -ENOMEM; 3678 goto out; 3679 } 3680 3681 for (i = 0; i < priv->vector_num; i++) { 3682 tqp_vector = &priv->tqp_vector[i]; 3683 tqp_vector->idx = i; 3684 tqp_vector->mask_addr = vector[i].io_addr; 3685 tqp_vector->vector_irq = vector[i].vector; 3686 hns3_vector_coalesce_init(tqp_vector, priv); 3687 } 3688 3689 out: 3690 devm_kfree(&pdev->dev, vector); 3691 return ret; 3692 } 3693 3694 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 3695 { 3696 group->ring = NULL; 3697 group->count = 0; 3698 } 3699 3700 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 3701 { 3702 struct hnae3_ring_chain_node vector_ring_chain; 3703 struct hnae3_handle *h = priv->ae_handle; 3704 struct hns3_enet_tqp_vector *tqp_vector; 3705 int i; 3706 3707 for (i = 0; i < priv->vector_num; i++) { 3708 tqp_vector = &priv->tqp_vector[i]; 3709 3710 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 3711 continue; 3712 3713 /* Since the mapping can be overwritten, when fail to get the 3714 * chain between vector and ring, we should go on to deal with 3715 * the remaining options. 3716 */ 3717 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain)) 3718 dev_warn(priv->dev, "failed to get ring chain\n"); 3719 3720 h->ae_algo->ops->unmap_ring_from_vector(h, 3721 tqp_vector->vector_irq, &vector_ring_chain); 3722 3723 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3724 3725 hns3_clear_ring_group(&tqp_vector->rx_group); 3726 hns3_clear_ring_group(&tqp_vector->tx_group); 3727 netif_napi_del(&priv->tqp_vector[i].napi); 3728 } 3729 } 3730 3731 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 3732 { 3733 struct hnae3_handle *h = priv->ae_handle; 3734 struct pci_dev *pdev = h->pdev; 3735 int i, ret; 3736 3737 for (i = 0; i < priv->vector_num; i++) { 3738 struct hns3_enet_tqp_vector *tqp_vector; 3739 3740 tqp_vector = &priv->tqp_vector[i]; 3741 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 3742 if (ret) 3743 return; 3744 } 3745 3746 devm_kfree(&pdev->dev, priv->tqp_vector); 3747 } 3748 3749 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 3750 unsigned int ring_type) 3751 { 3752 int queue_num = priv->ae_handle->kinfo.num_tqps; 3753 struct hns3_enet_ring *ring; 3754 int desc_num; 3755 3756 if (ring_type == HNAE3_RING_TYPE_TX) { 3757 ring = &priv->ring[q->tqp_index]; 3758 desc_num = priv->ae_handle->kinfo.num_tx_desc; 3759 ring->queue_index = q->tqp_index; 3760 } else { 3761 ring = &priv->ring[q->tqp_index + queue_num]; 3762 desc_num = priv->ae_handle->kinfo.num_rx_desc; 3763 ring->queue_index = q->tqp_index; 3764 } 3765 3766 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 3767 3768 ring->tqp = q; 3769 ring->desc = NULL; 3770 ring->desc_cb = NULL; 3771 ring->dev = priv->dev; 3772 ring->desc_dma_addr = 0; 3773 ring->buf_size = q->buf_size; 3774 ring->desc_num = desc_num; 3775 ring->next_to_use = 0; 3776 ring->next_to_clean = 0; 3777 ring->last_to_use = 0; 3778 } 3779 3780 static void hns3_queue_to_ring(struct hnae3_queue *tqp, 3781 struct hns3_nic_priv *priv) 3782 { 3783 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 3784 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 3785 } 3786 3787 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 3788 { 3789 struct hnae3_handle *h = priv->ae_handle; 3790 struct pci_dev *pdev = h->pdev; 3791 int i; 3792 3793 priv->ring = devm_kzalloc(&pdev->dev, 3794 array3_size(h->kinfo.num_tqps, 3795 sizeof(*priv->ring), 2), 3796 GFP_KERNEL); 3797 if (!priv->ring) 3798 return -ENOMEM; 3799 3800 for (i = 0; i < h->kinfo.num_tqps; i++) 3801 hns3_queue_to_ring(h->kinfo.tqp[i], priv); 3802 3803 return 0; 3804 } 3805 3806 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 3807 { 3808 if (!priv->ring) 3809 return; 3810 3811 devm_kfree(priv->dev, priv->ring); 3812 priv->ring = NULL; 3813 } 3814 3815 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 3816 { 3817 int ret; 3818 3819 if (ring->desc_num <= 0 || ring->buf_size <= 0) 3820 return -EINVAL; 3821 3822 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num, 3823 sizeof(ring->desc_cb[0]), GFP_KERNEL); 3824 if (!ring->desc_cb) { 3825 ret = -ENOMEM; 3826 goto out; 3827 } 3828 3829 ret = hns3_alloc_desc(ring); 3830 if (ret) 3831 goto out_with_desc_cb; 3832 3833 if (!HNAE3_IS_TX_RING(ring)) { 3834 ret = hns3_alloc_ring_buffers(ring); 3835 if (ret) 3836 goto out_with_desc; 3837 } 3838 3839 return 0; 3840 3841 out_with_desc: 3842 hns3_free_desc(ring); 3843 out_with_desc_cb: 3844 devm_kfree(ring_to_dev(ring), ring->desc_cb); 3845 ring->desc_cb = NULL; 3846 out: 3847 return ret; 3848 } 3849 3850 void hns3_fini_ring(struct hns3_enet_ring *ring) 3851 { 3852 hns3_free_desc(ring); 3853 devm_kfree(ring_to_dev(ring), ring->desc_cb); 3854 ring->desc_cb = NULL; 3855 ring->next_to_clean = 0; 3856 ring->next_to_use = 0; 3857 ring->last_to_use = 0; 3858 ring->pending_buf = 0; 3859 if (ring->skb) { 3860 dev_kfree_skb_any(ring->skb); 3861 ring->skb = NULL; 3862 } 3863 } 3864 3865 static int hns3_buf_size2type(u32 buf_size) 3866 { 3867 int bd_size_type; 3868 3869 switch (buf_size) { 3870 case 512: 3871 bd_size_type = HNS3_BD_SIZE_512_TYPE; 3872 break; 3873 case 1024: 3874 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 3875 break; 3876 case 2048: 3877 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3878 break; 3879 case 4096: 3880 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 3881 break; 3882 default: 3883 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3884 } 3885 3886 return bd_size_type; 3887 } 3888 3889 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 3890 { 3891 dma_addr_t dma = ring->desc_dma_addr; 3892 struct hnae3_queue *q = ring->tqp; 3893 3894 if (!HNAE3_IS_TX_RING(ring)) { 3895 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma); 3896 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 3897 (u32)((dma >> 31) >> 1)); 3898 3899 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 3900 hns3_buf_size2type(ring->buf_size)); 3901 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 3902 ring->desc_num / 8 - 1); 3903 3904 } else { 3905 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 3906 (u32)dma); 3907 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 3908 (u32)((dma >> 31) >> 1)); 3909 3910 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 3911 ring->desc_num / 8 - 1); 3912 } 3913 } 3914 3915 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 3916 { 3917 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3918 int i; 3919 3920 for (i = 0; i < HNAE3_MAX_TC; i++) { 3921 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i]; 3922 int j; 3923 3924 if (!tc_info->enable) 3925 continue; 3926 3927 for (j = 0; j < tc_info->tqp_count; j++) { 3928 struct hnae3_queue *q; 3929 3930 q = priv->ring[tc_info->tqp_offset + j].tqp; 3931 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, 3932 tc_info->tc); 3933 } 3934 } 3935 } 3936 3937 int hns3_init_all_ring(struct hns3_nic_priv *priv) 3938 { 3939 struct hnae3_handle *h = priv->ae_handle; 3940 int ring_num = h->kinfo.num_tqps * 2; 3941 int i, j; 3942 int ret; 3943 3944 for (i = 0; i < ring_num; i++) { 3945 ret = hns3_alloc_ring_memory(&priv->ring[i]); 3946 if (ret) { 3947 dev_err(priv->dev, 3948 "Alloc ring memory fail! ret=%d\n", ret); 3949 goto out_when_alloc_ring_memory; 3950 } 3951 3952 u64_stats_init(&priv->ring[i].syncp); 3953 } 3954 3955 return 0; 3956 3957 out_when_alloc_ring_memory: 3958 for (j = i - 1; j >= 0; j--) 3959 hns3_fini_ring(&priv->ring[j]); 3960 3961 return -ENOMEM; 3962 } 3963 3964 int hns3_uninit_all_ring(struct hns3_nic_priv *priv) 3965 { 3966 struct hnae3_handle *h = priv->ae_handle; 3967 int i; 3968 3969 for (i = 0; i < h->kinfo.num_tqps; i++) { 3970 hns3_fini_ring(&priv->ring[i]); 3971 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]); 3972 } 3973 return 0; 3974 } 3975 3976 /* Set mac addr if it is configured. or leave it to the AE driver */ 3977 static int hns3_init_mac_addr(struct net_device *netdev) 3978 { 3979 struct hns3_nic_priv *priv = netdev_priv(netdev); 3980 struct hnae3_handle *h = priv->ae_handle; 3981 u8 mac_addr_temp[ETH_ALEN]; 3982 int ret = 0; 3983 3984 if (h->ae_algo->ops->get_mac_addr) 3985 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 3986 3987 /* Check if the MAC address is valid, if not get a random one */ 3988 if (!is_valid_ether_addr(mac_addr_temp)) { 3989 eth_hw_addr_random(netdev); 3990 dev_warn(priv->dev, "using random MAC address %pM\n", 3991 netdev->dev_addr); 3992 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) { 3993 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 3994 ether_addr_copy(netdev->perm_addr, mac_addr_temp); 3995 } else { 3996 return 0; 3997 } 3998 3999 if (h->ae_algo->ops->set_mac_addr) 4000 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 4001 4002 return ret; 4003 } 4004 4005 static int hns3_init_phy(struct net_device *netdev) 4006 { 4007 struct hnae3_handle *h = hns3_get_handle(netdev); 4008 int ret = 0; 4009 4010 if (h->ae_algo->ops->mac_connect_phy) 4011 ret = h->ae_algo->ops->mac_connect_phy(h); 4012 4013 return ret; 4014 } 4015 4016 static void hns3_uninit_phy(struct net_device *netdev) 4017 { 4018 struct hnae3_handle *h = hns3_get_handle(netdev); 4019 4020 if (h->ae_algo->ops->mac_disconnect_phy) 4021 h->ae_algo->ops->mac_disconnect_phy(h); 4022 } 4023 4024 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list) 4025 { 4026 struct hnae3_handle *h = hns3_get_handle(netdev); 4027 4028 if (h->ae_algo->ops->del_all_fd_entries) 4029 h->ae_algo->ops->del_all_fd_entries(h, clear_list); 4030 } 4031 4032 static int hns3_client_start(struct hnae3_handle *handle) 4033 { 4034 if (!handle->ae_algo->ops->client_start) 4035 return 0; 4036 4037 return handle->ae_algo->ops->client_start(handle); 4038 } 4039 4040 static void hns3_client_stop(struct hnae3_handle *handle) 4041 { 4042 if (!handle->ae_algo->ops->client_stop) 4043 return; 4044 4045 handle->ae_algo->ops->client_stop(handle); 4046 } 4047 4048 static void hns3_info_show(struct hns3_nic_priv *priv) 4049 { 4050 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 4051 4052 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr); 4053 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps); 4054 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size); 4055 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size); 4056 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len); 4057 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc); 4058 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc); 4059 dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc); 4060 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu); 4061 } 4062 4063 static int hns3_client_init(struct hnae3_handle *handle) 4064 { 4065 struct pci_dev *pdev = handle->pdev; 4066 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4067 u16 alloc_tqps, max_rss_size; 4068 struct hns3_nic_priv *priv; 4069 struct net_device *netdev; 4070 int ret; 4071 4072 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 4073 &max_rss_size); 4074 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 4075 if (!netdev) 4076 return -ENOMEM; 4077 4078 priv = netdev_priv(netdev); 4079 priv->dev = &pdev->dev; 4080 priv->netdev = netdev; 4081 priv->ae_handle = handle; 4082 priv->tx_timeout_count = 0; 4083 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num; 4084 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 4085 4086 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL); 4087 4088 handle->kinfo.netdev = netdev; 4089 handle->priv = (void *)priv; 4090 4091 hns3_init_mac_addr(netdev); 4092 4093 hns3_set_default_feature(netdev); 4094 4095 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 4096 netdev->priv_flags |= IFF_UNICAST_FLT; 4097 netdev->netdev_ops = &hns3_nic_netdev_ops; 4098 SET_NETDEV_DEV(netdev, &pdev->dev); 4099 hns3_ethtool_set_ops(netdev); 4100 4101 /* Carrier off reporting is important to ethtool even BEFORE open */ 4102 netif_carrier_off(netdev); 4103 4104 ret = hns3_get_ring_config(priv); 4105 if (ret) { 4106 ret = -ENOMEM; 4107 goto out_get_ring_cfg; 4108 } 4109 4110 ret = hns3_nic_alloc_vector_data(priv); 4111 if (ret) { 4112 ret = -ENOMEM; 4113 goto out_alloc_vector_data; 4114 } 4115 4116 ret = hns3_nic_init_vector_data(priv); 4117 if (ret) { 4118 ret = -ENOMEM; 4119 goto out_init_vector_data; 4120 } 4121 4122 ret = hns3_init_all_ring(priv); 4123 if (ret) { 4124 ret = -ENOMEM; 4125 goto out_init_ring; 4126 } 4127 4128 ret = hns3_init_phy(netdev); 4129 if (ret) 4130 goto out_init_phy; 4131 4132 ret = register_netdev(netdev); 4133 if (ret) { 4134 dev_err(priv->dev, "probe register netdev fail!\n"); 4135 goto out_reg_netdev_fail; 4136 } 4137 4138 /* the device can work without cpu rmap, only aRFS needs it */ 4139 ret = hns3_set_rx_cpu_rmap(netdev); 4140 if (ret) 4141 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 4142 4143 ret = hns3_nic_init_irq(priv); 4144 if (ret) { 4145 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 4146 hns3_free_rx_cpu_rmap(netdev); 4147 goto out_init_irq_fail; 4148 } 4149 4150 ret = hns3_client_start(handle); 4151 if (ret) { 4152 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4153 goto out_client_start; 4154 } 4155 4156 hns3_dcbnl_setup(handle); 4157 4158 hns3_dbg_init(handle); 4159 4160 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */ 4161 netdev->max_mtu = HNS3_MAX_MTU; 4162 4163 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4164 4165 if (netif_msg_drv(handle)) 4166 hns3_info_show(priv); 4167 4168 return ret; 4169 4170 out_client_start: 4171 hns3_free_rx_cpu_rmap(netdev); 4172 hns3_nic_uninit_irq(priv); 4173 out_init_irq_fail: 4174 unregister_netdev(netdev); 4175 out_reg_netdev_fail: 4176 hns3_uninit_phy(netdev); 4177 out_init_phy: 4178 hns3_uninit_all_ring(priv); 4179 out_init_ring: 4180 hns3_nic_uninit_vector_data(priv); 4181 out_init_vector_data: 4182 hns3_nic_dealloc_vector_data(priv); 4183 out_alloc_vector_data: 4184 priv->ring = NULL; 4185 out_get_ring_cfg: 4186 priv->ae_handle = NULL; 4187 free_netdev(netdev); 4188 return ret; 4189 } 4190 4191 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 4192 { 4193 struct net_device *netdev = handle->kinfo.netdev; 4194 struct hns3_nic_priv *priv = netdev_priv(netdev); 4195 int ret; 4196 4197 if (netdev->reg_state != NETREG_UNINITIALIZED) 4198 unregister_netdev(netdev); 4199 4200 hns3_client_stop(handle); 4201 4202 hns3_uninit_phy(netdev); 4203 4204 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4205 netdev_warn(netdev, "already uninitialized\n"); 4206 goto out_netdev_free; 4207 } 4208 4209 hns3_free_rx_cpu_rmap(netdev); 4210 4211 hns3_nic_uninit_irq(priv); 4212 4213 hns3_del_all_fd_rules(netdev, true); 4214 4215 hns3_clear_all_ring(handle, true); 4216 4217 hns3_nic_uninit_vector_data(priv); 4218 4219 hns3_nic_dealloc_vector_data(priv); 4220 4221 ret = hns3_uninit_all_ring(priv); 4222 if (ret) 4223 netdev_err(netdev, "uninit ring error\n"); 4224 4225 hns3_put_ring_config(priv); 4226 4227 out_netdev_free: 4228 hns3_dbg_uninit(handle); 4229 free_netdev(netdev); 4230 } 4231 4232 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 4233 { 4234 struct net_device *netdev = handle->kinfo.netdev; 4235 4236 if (!netdev) 4237 return; 4238 4239 if (linkup) { 4240 netif_tx_wake_all_queues(netdev); 4241 netif_carrier_on(netdev); 4242 if (netif_msg_link(handle)) 4243 netdev_info(netdev, "link up\n"); 4244 } else { 4245 netif_carrier_off(netdev); 4246 netif_tx_stop_all_queues(netdev); 4247 if (netif_msg_link(handle)) 4248 netdev_info(netdev, "link down\n"); 4249 } 4250 } 4251 4252 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc) 4253 { 4254 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4255 struct net_device *ndev = kinfo->netdev; 4256 4257 if (tc > HNAE3_MAX_TC) 4258 return -EINVAL; 4259 4260 if (!ndev) 4261 return -ENODEV; 4262 4263 return hns3_nic_set_real_num_queue(ndev); 4264 } 4265 4266 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 4267 { 4268 while (ring->next_to_clean != ring->next_to_use) { 4269 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 4270 hns3_free_buffer_detach(ring, ring->next_to_clean, 0); 4271 ring_ptr_move_fw(ring, next_to_clean); 4272 } 4273 4274 ring->pending_buf = 0; 4275 } 4276 4277 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 4278 { 4279 struct hns3_desc_cb res_cbs; 4280 int ret; 4281 4282 while (ring->next_to_use != ring->next_to_clean) { 4283 /* When a buffer is not reused, it's memory has been 4284 * freed in hns3_handle_rx_bd or will be freed by 4285 * stack, so we need to replace the buffer here. 4286 */ 4287 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4288 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 4289 if (ret) { 4290 u64_stats_update_begin(&ring->syncp); 4291 ring->stats.sw_err_cnt++; 4292 u64_stats_update_end(&ring->syncp); 4293 /* if alloc new buffer fail, exit directly 4294 * and reclear in up flow. 4295 */ 4296 netdev_warn(ring_to_netdev(ring), 4297 "reserve buffer map failed, ret = %d\n", 4298 ret); 4299 return ret; 4300 } 4301 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 4302 } 4303 ring_ptr_move_fw(ring, next_to_use); 4304 } 4305 4306 /* Free the pending skb in rx ring */ 4307 if (ring->skb) { 4308 dev_kfree_skb_any(ring->skb); 4309 ring->skb = NULL; 4310 ring->pending_buf = 0; 4311 } 4312 4313 return 0; 4314 } 4315 4316 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 4317 { 4318 while (ring->next_to_use != ring->next_to_clean) { 4319 /* When a buffer is not reused, it's memory has been 4320 * freed in hns3_handle_rx_bd or will be freed by 4321 * stack, so only need to unmap the buffer here. 4322 */ 4323 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4324 hns3_unmap_buffer(ring, 4325 &ring->desc_cb[ring->next_to_use]); 4326 ring->desc_cb[ring->next_to_use].dma = 0; 4327 } 4328 4329 ring_ptr_move_fw(ring, next_to_use); 4330 } 4331 } 4332 4333 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force) 4334 { 4335 struct net_device *ndev = h->kinfo.netdev; 4336 struct hns3_nic_priv *priv = netdev_priv(ndev); 4337 u32 i; 4338 4339 for (i = 0; i < h->kinfo.num_tqps; i++) { 4340 struct hns3_enet_ring *ring; 4341 4342 ring = &priv->ring[i]; 4343 hns3_clear_tx_ring(ring); 4344 4345 ring = &priv->ring[i + h->kinfo.num_tqps]; 4346 /* Continue to clear other rings even if clearing some 4347 * rings failed. 4348 */ 4349 if (force) 4350 hns3_force_clear_rx_ring(ring); 4351 else 4352 hns3_clear_rx_ring(ring); 4353 } 4354 } 4355 4356 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 4357 { 4358 struct net_device *ndev = h->kinfo.netdev; 4359 struct hns3_nic_priv *priv = netdev_priv(ndev); 4360 struct hns3_enet_ring *rx_ring; 4361 int i, j; 4362 int ret; 4363 4364 for (i = 0; i < h->kinfo.num_tqps; i++) { 4365 ret = h->ae_algo->ops->reset_queue(h, i); 4366 if (ret) 4367 return ret; 4368 4369 hns3_init_ring_hw(&priv->ring[i]); 4370 4371 /* We need to clear tx ring here because self test will 4372 * use the ring and will not run down before up 4373 */ 4374 hns3_clear_tx_ring(&priv->ring[i]); 4375 priv->ring[i].next_to_clean = 0; 4376 priv->ring[i].next_to_use = 0; 4377 priv->ring[i].last_to_use = 0; 4378 4379 rx_ring = &priv->ring[i + h->kinfo.num_tqps]; 4380 hns3_init_ring_hw(rx_ring); 4381 ret = hns3_clear_rx_ring(rx_ring); 4382 if (ret) 4383 return ret; 4384 4385 /* We can not know the hardware head and tail when this 4386 * function is called in reset flow, so we reuse all desc. 4387 */ 4388 for (j = 0; j < rx_ring->desc_num; j++) 4389 hns3_reuse_buffer(rx_ring, j); 4390 4391 rx_ring->next_to_clean = 0; 4392 rx_ring->next_to_use = 0; 4393 } 4394 4395 hns3_init_tx_ring_tc(priv); 4396 4397 return 0; 4398 } 4399 4400 static void hns3_store_coal(struct hns3_nic_priv *priv) 4401 { 4402 /* ethtool only support setting and querying one coal 4403 * configuration for now, so save the vector 0' coal 4404 * configuration here in order to restore it. 4405 */ 4406 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal, 4407 sizeof(struct hns3_enet_coalesce)); 4408 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal, 4409 sizeof(struct hns3_enet_coalesce)); 4410 } 4411 4412 static void hns3_restore_coal(struct hns3_nic_priv *priv) 4413 { 4414 u16 vector_num = priv->vector_num; 4415 int i; 4416 4417 for (i = 0; i < vector_num; i++) { 4418 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal, 4419 sizeof(struct hns3_enet_coalesce)); 4420 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal, 4421 sizeof(struct hns3_enet_coalesce)); 4422 } 4423 } 4424 4425 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 4426 { 4427 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4428 struct net_device *ndev = kinfo->netdev; 4429 struct hns3_nic_priv *priv = netdev_priv(ndev); 4430 4431 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 4432 return 0; 4433 4434 if (!netif_running(ndev)) 4435 return 0; 4436 4437 return hns3_nic_net_stop(ndev); 4438 } 4439 4440 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 4441 { 4442 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4443 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 4444 int ret = 0; 4445 4446 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4447 4448 if (netif_running(kinfo->netdev)) { 4449 ret = hns3_nic_net_open(kinfo->netdev); 4450 if (ret) { 4451 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4452 netdev_err(kinfo->netdev, 4453 "net up fail, ret=%d!\n", ret); 4454 return ret; 4455 } 4456 } 4457 4458 return ret; 4459 } 4460 4461 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 4462 { 4463 struct net_device *netdev = handle->kinfo.netdev; 4464 struct hns3_nic_priv *priv = netdev_priv(netdev); 4465 int ret; 4466 4467 /* Carrier off reporting is important to ethtool even BEFORE open */ 4468 netif_carrier_off(netdev); 4469 4470 ret = hns3_get_ring_config(priv); 4471 if (ret) 4472 return ret; 4473 4474 ret = hns3_nic_alloc_vector_data(priv); 4475 if (ret) 4476 goto err_put_ring; 4477 4478 hns3_restore_coal(priv); 4479 4480 ret = hns3_nic_init_vector_data(priv); 4481 if (ret) 4482 goto err_dealloc_vector; 4483 4484 ret = hns3_init_all_ring(priv); 4485 if (ret) 4486 goto err_uninit_vector; 4487 4488 /* the device can work without cpu rmap, only aRFS needs it */ 4489 ret = hns3_set_rx_cpu_rmap(netdev); 4490 if (ret) 4491 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 4492 4493 ret = hns3_nic_init_irq(priv); 4494 if (ret) { 4495 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 4496 hns3_free_rx_cpu_rmap(netdev); 4497 goto err_init_irq_fail; 4498 } 4499 4500 if (!hns3_is_phys_func(handle->pdev)) 4501 hns3_init_mac_addr(netdev); 4502 4503 ret = hns3_client_start(handle); 4504 if (ret) { 4505 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4506 goto err_client_start_fail; 4507 } 4508 4509 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4510 4511 return ret; 4512 4513 err_client_start_fail: 4514 hns3_free_rx_cpu_rmap(netdev); 4515 hns3_nic_uninit_irq(priv); 4516 err_init_irq_fail: 4517 hns3_uninit_all_ring(priv); 4518 err_uninit_vector: 4519 hns3_nic_uninit_vector_data(priv); 4520 err_dealloc_vector: 4521 hns3_nic_dealloc_vector_data(priv); 4522 err_put_ring: 4523 hns3_put_ring_config(priv); 4524 4525 return ret; 4526 } 4527 4528 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 4529 { 4530 struct net_device *netdev = handle->kinfo.netdev; 4531 struct hns3_nic_priv *priv = netdev_priv(netdev); 4532 int ret; 4533 4534 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4535 netdev_warn(netdev, "already uninitialized\n"); 4536 return 0; 4537 } 4538 4539 hns3_free_rx_cpu_rmap(netdev); 4540 hns3_nic_uninit_irq(priv); 4541 hns3_clear_all_ring(handle, true); 4542 hns3_reset_tx_queue(priv->ae_handle); 4543 4544 hns3_nic_uninit_vector_data(priv); 4545 4546 hns3_store_coal(priv); 4547 4548 hns3_nic_dealloc_vector_data(priv); 4549 4550 ret = hns3_uninit_all_ring(priv); 4551 if (ret) 4552 netdev_err(netdev, "uninit ring error\n"); 4553 4554 hns3_put_ring_config(priv); 4555 4556 return ret; 4557 } 4558 4559 static int hns3_reset_notify(struct hnae3_handle *handle, 4560 enum hnae3_reset_notify_type type) 4561 { 4562 int ret = 0; 4563 4564 switch (type) { 4565 case HNAE3_UP_CLIENT: 4566 ret = hns3_reset_notify_up_enet(handle); 4567 break; 4568 case HNAE3_DOWN_CLIENT: 4569 ret = hns3_reset_notify_down_enet(handle); 4570 break; 4571 case HNAE3_INIT_CLIENT: 4572 ret = hns3_reset_notify_init_enet(handle); 4573 break; 4574 case HNAE3_UNINIT_CLIENT: 4575 ret = hns3_reset_notify_uninit_enet(handle); 4576 break; 4577 default: 4578 break; 4579 } 4580 4581 return ret; 4582 } 4583 4584 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num, 4585 bool rxfh_configured) 4586 { 4587 int ret; 4588 4589 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num, 4590 rxfh_configured); 4591 if (ret) { 4592 dev_err(&handle->pdev->dev, 4593 "Change tqp num(%u) fail.\n", new_tqp_num); 4594 return ret; 4595 } 4596 4597 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT); 4598 if (ret) 4599 return ret; 4600 4601 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT); 4602 if (ret) 4603 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT); 4604 4605 return ret; 4606 } 4607 4608 int hns3_set_channels(struct net_device *netdev, 4609 struct ethtool_channels *ch) 4610 { 4611 struct hnae3_handle *h = hns3_get_handle(netdev); 4612 struct hnae3_knic_private_info *kinfo = &h->kinfo; 4613 bool rxfh_configured = netif_is_rxfh_configured(netdev); 4614 u32 new_tqp_num = ch->combined_count; 4615 u16 org_tqp_num; 4616 int ret; 4617 4618 if (hns3_nic_resetting(netdev)) 4619 return -EBUSY; 4620 4621 if (ch->rx_count || ch->tx_count) 4622 return -EINVAL; 4623 4624 if (new_tqp_num > hns3_get_max_available_channels(h) || 4625 new_tqp_num < 1) { 4626 dev_err(&netdev->dev, 4627 "Change tqps fail, the tqp range is from 1 to %u", 4628 hns3_get_max_available_channels(h)); 4629 return -EINVAL; 4630 } 4631 4632 if (kinfo->rss_size == new_tqp_num) 4633 return 0; 4634 4635 netif_dbg(h, drv, netdev, 4636 "set channels: tqp_num=%u, rxfh=%d\n", 4637 new_tqp_num, rxfh_configured); 4638 4639 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 4640 if (ret) 4641 return ret; 4642 4643 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 4644 if (ret) 4645 return ret; 4646 4647 org_tqp_num = h->kinfo.num_tqps; 4648 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured); 4649 if (ret) { 4650 int ret1; 4651 4652 netdev_warn(netdev, 4653 "Change channels fail, revert to old value\n"); 4654 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured); 4655 if (ret1) { 4656 netdev_err(netdev, 4657 "revert to old channel fail\n"); 4658 return ret1; 4659 } 4660 4661 return ret; 4662 } 4663 4664 return 0; 4665 } 4666 4667 static const struct hns3_hw_error_info hns3_hw_err[] = { 4668 { .type = HNAE3_PPU_POISON_ERROR, 4669 .msg = "PPU poison" }, 4670 { .type = HNAE3_CMDQ_ECC_ERROR, 4671 .msg = "IMP CMDQ error" }, 4672 { .type = HNAE3_IMP_RD_POISON_ERROR, 4673 .msg = "IMP RD poison" }, 4674 { .type = HNAE3_ROCEE_AXI_RESP_ERROR, 4675 .msg = "ROCEE AXI RESP error" }, 4676 }; 4677 4678 static void hns3_process_hw_error(struct hnae3_handle *handle, 4679 enum hnae3_hw_error_type type) 4680 { 4681 int i; 4682 4683 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) { 4684 if (hns3_hw_err[i].type == type) { 4685 dev_err(&handle->pdev->dev, "Detected %s!\n", 4686 hns3_hw_err[i].msg); 4687 break; 4688 } 4689 } 4690 } 4691 4692 static const struct hnae3_client_ops client_ops = { 4693 .init_instance = hns3_client_init, 4694 .uninit_instance = hns3_client_uninit, 4695 .link_status_change = hns3_link_status_change, 4696 .setup_tc = hns3_client_setup_tc, 4697 .reset_notify = hns3_reset_notify, 4698 .process_hw_error = hns3_process_hw_error, 4699 }; 4700 4701 /* hns3_init_module - Driver registration routine 4702 * hns3_init_module is the first routine called when the driver is 4703 * loaded. All it does is register with the PCI subsystem. 4704 */ 4705 static int __init hns3_init_module(void) 4706 { 4707 int ret; 4708 4709 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 4710 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 4711 4712 client.type = HNAE3_CLIENT_KNIC; 4713 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s", 4714 hns3_driver_name); 4715 4716 client.ops = &client_ops; 4717 4718 INIT_LIST_HEAD(&client.node); 4719 4720 hns3_dbg_register_debugfs(hns3_driver_name); 4721 4722 ret = hnae3_register_client(&client); 4723 if (ret) 4724 goto err_reg_client; 4725 4726 ret = pci_register_driver(&hns3_driver); 4727 if (ret) 4728 goto err_reg_driver; 4729 4730 return ret; 4731 4732 err_reg_driver: 4733 hnae3_unregister_client(&client); 4734 err_reg_client: 4735 hns3_dbg_unregister_debugfs(); 4736 return ret; 4737 } 4738 module_init(hns3_init_module); 4739 4740 /* hns3_exit_module - Driver exit cleanup routine 4741 * hns3_exit_module is called just before the driver is removed 4742 * from memory. 4743 */ 4744 static void __exit hns3_exit_module(void) 4745 { 4746 pci_unregister_driver(&hns3_driver); 4747 hnae3_unregister_client(&client); 4748 hns3_dbg_unregister_debugfs(); 4749 } 4750 module_exit(hns3_exit_module); 4751 4752 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 4753 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 4754 MODULE_LICENSE("GPL"); 4755 MODULE_ALIAS("pci:hns-nic"); 4756