1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #include <linux/if_vlan.h> 8 #include <linux/ip.h> 9 #include <linux/ipv6.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/aer.h> 13 #include <linux/skbuff.h> 14 #include <linux/sctp.h> 15 #include <linux/vermagic.h> 16 #include <net/gre.h> 17 #include <net/pkt_cls.h> 18 #include <net/tcp.h> 19 #include <net/vxlan.h> 20 21 #include "hnae3.h" 22 #include "hns3_enet.h" 23 24 static void hns3_clear_all_ring(struct hnae3_handle *h); 25 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h); 26 static void hns3_remove_hw_addr(struct net_device *netdev); 27 28 static const char hns3_driver_name[] = "hns3"; 29 const char hns3_driver_version[] = VERMAGIC_STRING; 30 static const char hns3_driver_string[] = 31 "Hisilicon Ethernet Network Driver for Hip08 Family"; 32 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 33 static struct hnae3_client client; 34 35 /* hns3_pci_tbl - PCI Device ID Table 36 * 37 * Last entry must be all 0s 38 * 39 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 40 * Class, Class Mask, private data (not used) } 41 */ 42 static const struct pci_device_id hns3_pci_tbl[] = { 43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 46 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 48 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 50 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 52 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 54 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 55 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 56 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 57 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 58 /* required last entry */ 59 {0, } 60 }; 61 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 62 63 static irqreturn_t hns3_irq_handle(int irq, void *vector) 64 { 65 struct hns3_enet_tqp_vector *tqp_vector = vector; 66 67 napi_schedule(&tqp_vector->napi); 68 69 return IRQ_HANDLED; 70 } 71 72 /* This callback function is used to set affinity changes to the irq affinity 73 * masks when the irq_set_affinity_notifier function is used. 74 */ 75 static void hns3_nic_irq_affinity_notify(struct irq_affinity_notify *notify, 76 const cpumask_t *mask) 77 { 78 struct hns3_enet_tqp_vector *tqp_vectors = 79 container_of(notify, struct hns3_enet_tqp_vector, 80 affinity_notify); 81 82 tqp_vectors->affinity_mask = *mask; 83 } 84 85 static void hns3_nic_irq_affinity_release(struct kref *ref) 86 { 87 } 88 89 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 90 { 91 struct hns3_enet_tqp_vector *tqp_vectors; 92 unsigned int i; 93 94 for (i = 0; i < priv->vector_num; i++) { 95 tqp_vectors = &priv->tqp_vector[i]; 96 97 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 98 continue; 99 100 /* clear the affinity notifier and affinity mask */ 101 irq_set_affinity_notifier(tqp_vectors->vector_irq, NULL); 102 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 103 104 /* release the irq resource */ 105 free_irq(tqp_vectors->vector_irq, tqp_vectors); 106 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 107 } 108 } 109 110 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 111 { 112 struct hns3_enet_tqp_vector *tqp_vectors; 113 int txrx_int_idx = 0; 114 int rx_int_idx = 0; 115 int tx_int_idx = 0; 116 unsigned int i; 117 int ret; 118 119 for (i = 0; i < priv->vector_num; i++) { 120 tqp_vectors = &priv->tqp_vector[i]; 121 122 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 123 continue; 124 125 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 126 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 127 "%s-%s-%d", priv->netdev->name, "TxRx", 128 txrx_int_idx++); 129 txrx_int_idx++; 130 } else if (tqp_vectors->rx_group.ring) { 131 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 132 "%s-%s-%d", priv->netdev->name, "Rx", 133 rx_int_idx++); 134 } else if (tqp_vectors->tx_group.ring) { 135 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 136 "%s-%s-%d", priv->netdev->name, "Tx", 137 tx_int_idx++); 138 } else { 139 /* Skip this unused q_vector */ 140 continue; 141 } 142 143 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 144 145 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 146 tqp_vectors->name, 147 tqp_vectors); 148 if (ret) { 149 netdev_err(priv->netdev, "request irq(%d) fail\n", 150 tqp_vectors->vector_irq); 151 return ret; 152 } 153 154 tqp_vectors->affinity_notify.notify = 155 hns3_nic_irq_affinity_notify; 156 tqp_vectors->affinity_notify.release = 157 hns3_nic_irq_affinity_release; 158 irq_set_affinity_notifier(tqp_vectors->vector_irq, 159 &tqp_vectors->affinity_notify); 160 irq_set_affinity_hint(tqp_vectors->vector_irq, 161 &tqp_vectors->affinity_mask); 162 163 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 164 } 165 166 return 0; 167 } 168 169 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 170 u32 mask_en) 171 { 172 writel(mask_en, tqp_vector->mask_addr); 173 } 174 175 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 176 { 177 napi_enable(&tqp_vector->napi); 178 179 /* enable vector */ 180 hns3_mask_vector_irq(tqp_vector, 1); 181 } 182 183 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 184 { 185 /* disable vector */ 186 hns3_mask_vector_irq(tqp_vector, 0); 187 188 disable_irq(tqp_vector->vector_irq); 189 napi_disable(&tqp_vector->napi); 190 } 191 192 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 193 u32 rl_value) 194 { 195 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 196 197 /* this defines the configuration for RL (Interrupt Rate Limiter). 198 * Rl defines rate of interrupts i.e. number of interrupts-per-second 199 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 200 */ 201 202 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable && 203 !tqp_vector->rx_group.coal.gl_adapt_enable) 204 /* According to the hardware, the range of rl_reg is 205 * 0-59 and the unit is 4. 206 */ 207 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 208 209 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 210 } 211 212 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 213 u32 gl_value) 214 { 215 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value); 216 217 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 218 } 219 220 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 221 u32 gl_value) 222 { 223 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value); 224 225 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 226 } 227 228 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector, 229 struct hns3_nic_priv *priv) 230 { 231 /* initialize the configuration for interrupt coalescing. 232 * 1. GL (Interrupt Gap Limiter) 233 * 2. RL (Interrupt Rate Limiter) 234 */ 235 236 /* Default: enable interrupt coalescing self-adaptive and GL */ 237 tqp_vector->tx_group.coal.gl_adapt_enable = 1; 238 tqp_vector->rx_group.coal.gl_adapt_enable = 1; 239 240 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K; 241 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K; 242 243 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW; 244 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW; 245 } 246 247 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 248 struct hns3_nic_priv *priv) 249 { 250 struct hnae3_handle *h = priv->ae_handle; 251 252 hns3_set_vector_coalesce_tx_gl(tqp_vector, 253 tqp_vector->tx_group.coal.int_gl); 254 hns3_set_vector_coalesce_rx_gl(tqp_vector, 255 tqp_vector->rx_group.coal.int_gl); 256 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 257 } 258 259 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 260 { 261 struct hnae3_handle *h = hns3_get_handle(netdev); 262 struct hnae3_knic_private_info *kinfo = &h->kinfo; 263 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc; 264 int i, ret; 265 266 if (kinfo->num_tc <= 1) { 267 netdev_reset_tc(netdev); 268 } else { 269 ret = netdev_set_num_tc(netdev, kinfo->num_tc); 270 if (ret) { 271 netdev_err(netdev, 272 "netdev_set_num_tc fail, ret=%d!\n", ret); 273 return ret; 274 } 275 276 for (i = 0; i < HNAE3_MAX_TC; i++) { 277 if (!kinfo->tc_info[i].enable) 278 continue; 279 280 netdev_set_tc_queue(netdev, 281 kinfo->tc_info[i].tc, 282 kinfo->tc_info[i].tqp_count, 283 kinfo->tc_info[i].tqp_offset); 284 } 285 } 286 287 ret = netif_set_real_num_tx_queues(netdev, queue_size); 288 if (ret) { 289 netdev_err(netdev, 290 "netif_set_real_num_tx_queues fail, ret=%d!\n", 291 ret); 292 return ret; 293 } 294 295 ret = netif_set_real_num_rx_queues(netdev, queue_size); 296 if (ret) { 297 netdev_err(netdev, 298 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 299 return ret; 300 } 301 302 return 0; 303 } 304 305 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 306 { 307 u16 alloc_tqps, max_rss_size, rss_size; 308 309 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 310 rss_size = alloc_tqps / h->kinfo.num_tc; 311 312 return min_t(u16, rss_size, max_rss_size); 313 } 314 315 static void hns3_tqp_enable(struct hnae3_queue *tqp) 316 { 317 u32 rcb_reg; 318 319 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 320 rcb_reg |= BIT(HNS3_RING_EN_B); 321 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 322 } 323 324 static void hns3_tqp_disable(struct hnae3_queue *tqp) 325 { 326 u32 rcb_reg; 327 328 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 329 rcb_reg &= ~BIT(HNS3_RING_EN_B); 330 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 331 } 332 333 static int hns3_nic_net_up(struct net_device *netdev) 334 { 335 struct hns3_nic_priv *priv = netdev_priv(netdev); 336 struct hnae3_handle *h = priv->ae_handle; 337 int i, j; 338 int ret; 339 340 ret = hns3_nic_reset_all_ring(h); 341 if (ret) 342 return ret; 343 344 /* get irq resource for all vectors */ 345 ret = hns3_nic_init_irq(priv); 346 if (ret) { 347 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret); 348 return ret; 349 } 350 351 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 352 353 /* enable the vectors */ 354 for (i = 0; i < priv->vector_num; i++) 355 hns3_vector_enable(&priv->tqp_vector[i]); 356 357 /* enable rcb */ 358 for (j = 0; j < h->kinfo.num_tqps; j++) 359 hns3_tqp_enable(h->kinfo.tqp[j]); 360 361 /* start the ae_dev */ 362 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 363 if (ret) 364 goto out_start_err; 365 366 return 0; 367 368 out_start_err: 369 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 370 while (j--) 371 hns3_tqp_disable(h->kinfo.tqp[j]); 372 373 for (j = i - 1; j >= 0; j--) 374 hns3_vector_disable(&priv->tqp_vector[j]); 375 376 hns3_nic_uninit_irq(priv); 377 378 return ret; 379 } 380 381 static int hns3_nic_net_open(struct net_device *netdev) 382 { 383 struct hns3_nic_priv *priv = netdev_priv(netdev); 384 struct hnae3_handle *h = hns3_get_handle(netdev); 385 struct hnae3_knic_private_info *kinfo; 386 int i, ret; 387 388 if (hns3_nic_resetting(netdev)) 389 return -EBUSY; 390 391 netif_carrier_off(netdev); 392 393 ret = hns3_nic_set_real_num_queue(netdev); 394 if (ret) 395 return ret; 396 397 ret = hns3_nic_net_up(netdev); 398 if (ret) { 399 netdev_err(netdev, 400 "hns net up fail, ret=%d!\n", ret); 401 return ret; 402 } 403 404 kinfo = &h->kinfo; 405 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { 406 netdev_set_prio_tc_map(netdev, i, 407 kinfo->prio_tc[i]); 408 } 409 410 if (h->ae_algo->ops->set_timer_task) 411 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 412 413 return 0; 414 } 415 416 static void hns3_nic_net_down(struct net_device *netdev) 417 { 418 struct hns3_nic_priv *priv = netdev_priv(netdev); 419 struct hnae3_handle *h = hns3_get_handle(netdev); 420 const struct hnae3_ae_ops *ops; 421 int i; 422 423 /* disable vectors */ 424 for (i = 0; i < priv->vector_num; i++) 425 hns3_vector_disable(&priv->tqp_vector[i]); 426 427 /* disable rcb */ 428 for (i = 0; i < h->kinfo.num_tqps; i++) 429 hns3_tqp_disable(h->kinfo.tqp[i]); 430 431 /* stop ae_dev */ 432 ops = priv->ae_handle->ae_algo->ops; 433 if (ops->stop) 434 ops->stop(priv->ae_handle); 435 436 /* free irq resources */ 437 hns3_nic_uninit_irq(priv); 438 439 hns3_clear_all_ring(priv->ae_handle); 440 } 441 442 static int hns3_nic_net_stop(struct net_device *netdev) 443 { 444 struct hns3_nic_priv *priv = netdev_priv(netdev); 445 struct hnae3_handle *h = hns3_get_handle(netdev); 446 447 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 448 return 0; 449 450 if (h->ae_algo->ops->set_timer_task) 451 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 452 453 netif_tx_stop_all_queues(netdev); 454 netif_carrier_off(netdev); 455 456 hns3_nic_net_down(netdev); 457 458 return 0; 459 } 460 461 static int hns3_nic_uc_sync(struct net_device *netdev, 462 const unsigned char *addr) 463 { 464 struct hnae3_handle *h = hns3_get_handle(netdev); 465 466 if (h->ae_algo->ops->add_uc_addr) 467 return h->ae_algo->ops->add_uc_addr(h, addr); 468 469 return 0; 470 } 471 472 static int hns3_nic_uc_unsync(struct net_device *netdev, 473 const unsigned char *addr) 474 { 475 struct hnae3_handle *h = hns3_get_handle(netdev); 476 477 if (h->ae_algo->ops->rm_uc_addr) 478 return h->ae_algo->ops->rm_uc_addr(h, addr); 479 480 return 0; 481 } 482 483 static int hns3_nic_mc_sync(struct net_device *netdev, 484 const unsigned char *addr) 485 { 486 struct hnae3_handle *h = hns3_get_handle(netdev); 487 488 if (h->ae_algo->ops->add_mc_addr) 489 return h->ae_algo->ops->add_mc_addr(h, addr); 490 491 return 0; 492 } 493 494 static int hns3_nic_mc_unsync(struct net_device *netdev, 495 const unsigned char *addr) 496 { 497 struct hnae3_handle *h = hns3_get_handle(netdev); 498 499 if (h->ae_algo->ops->rm_mc_addr) 500 return h->ae_algo->ops->rm_mc_addr(h, addr); 501 502 return 0; 503 } 504 505 static u8 hns3_get_netdev_flags(struct net_device *netdev) 506 { 507 u8 flags = 0; 508 509 if (netdev->flags & IFF_PROMISC) { 510 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 511 } else { 512 flags |= HNAE3_VLAN_FLTR; 513 if (netdev->flags & IFF_ALLMULTI) 514 flags |= HNAE3_USER_MPE; 515 } 516 517 return flags; 518 } 519 520 static void hns3_nic_set_rx_mode(struct net_device *netdev) 521 { 522 struct hnae3_handle *h = hns3_get_handle(netdev); 523 u8 new_flags; 524 int ret; 525 526 new_flags = hns3_get_netdev_flags(netdev); 527 528 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 529 if (ret) { 530 netdev_err(netdev, "sync uc address fail\n"); 531 if (ret == -ENOSPC) 532 new_flags |= HNAE3_OVERFLOW_UPE; 533 } 534 535 if (netdev->flags & IFF_MULTICAST) { 536 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync, 537 hns3_nic_mc_unsync); 538 if (ret) { 539 netdev_err(netdev, "sync mc address fail\n"); 540 if (ret == -ENOSPC) 541 new_flags |= HNAE3_OVERFLOW_MPE; 542 } 543 } 544 545 /* User mode Promisc mode enable and vlan filtering is disabled to 546 * let all packets in. MAC-VLAN Table overflow Promisc enabled and 547 * vlan fitering is enabled 548 */ 549 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR); 550 h->netdev_flags = new_flags; 551 hns3_update_promisc_mode(netdev, new_flags); 552 } 553 554 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags) 555 { 556 struct hns3_nic_priv *priv = netdev_priv(netdev); 557 struct hnae3_handle *h = priv->ae_handle; 558 559 if (h->ae_algo->ops->set_promisc_mode) { 560 return h->ae_algo->ops->set_promisc_mode(h, 561 promisc_flags & HNAE3_UPE, 562 promisc_flags & HNAE3_MPE); 563 } 564 565 return 0; 566 } 567 568 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable) 569 { 570 struct hns3_nic_priv *priv = netdev_priv(netdev); 571 struct hnae3_handle *h = priv->ae_handle; 572 bool last_state; 573 574 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) { 575 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false; 576 if (enable != last_state) { 577 netdev_info(netdev, 578 "%s vlan filter\n", 579 enable ? "enable" : "disable"); 580 h->ae_algo->ops->enable_vlan_filter(h, enable); 581 } 582 } 583 } 584 585 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen, 586 u16 *mss, u32 *type_cs_vlan_tso) 587 { 588 u32 l4_offset, hdr_len; 589 union l3_hdr_info l3; 590 union l4_hdr_info l4; 591 u32 l4_paylen; 592 int ret; 593 594 if (!skb_is_gso(skb)) 595 return 0; 596 597 ret = skb_cow_head(skb, 0); 598 if (ret) 599 return ret; 600 601 l3.hdr = skb_network_header(skb); 602 l4.hdr = skb_transport_header(skb); 603 604 /* Software should clear the IPv4's checksum field when tso is 605 * needed. 606 */ 607 if (l3.v4->version == 4) 608 l3.v4->check = 0; 609 610 /* tunnel packet.*/ 611 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 612 SKB_GSO_GRE_CSUM | 613 SKB_GSO_UDP_TUNNEL | 614 SKB_GSO_UDP_TUNNEL_CSUM)) { 615 if ((!(skb_shinfo(skb)->gso_type & 616 SKB_GSO_PARTIAL)) && 617 (skb_shinfo(skb)->gso_type & 618 SKB_GSO_UDP_TUNNEL_CSUM)) { 619 /* Software should clear the udp's checksum 620 * field when tso is needed. 621 */ 622 l4.udp->check = 0; 623 } 624 /* reset l3&l4 pointers from outer to inner headers */ 625 l3.hdr = skb_inner_network_header(skb); 626 l4.hdr = skb_inner_transport_header(skb); 627 628 /* Software should clear the IPv4's checksum field when 629 * tso is needed. 630 */ 631 if (l3.v4->version == 4) 632 l3.v4->check = 0; 633 } 634 635 /* normal or tunnel packet*/ 636 l4_offset = l4.hdr - skb->data; 637 hdr_len = (l4.tcp->doff * 4) + l4_offset; 638 639 /* remove payload length from inner pseudo checksum when tso*/ 640 l4_paylen = skb->len - l4_offset; 641 csum_replace_by_diff(&l4.tcp->check, 642 (__force __wsum)htonl(l4_paylen)); 643 644 /* find the txbd field values */ 645 *paylen = skb->len - hdr_len; 646 hnae3_set_bit(*type_cs_vlan_tso, 647 HNS3_TXD_TSO_B, 1); 648 649 /* get MSS for TSO */ 650 *mss = skb_shinfo(skb)->gso_size; 651 652 return 0; 653 } 654 655 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 656 u8 *il4_proto) 657 { 658 union l3_hdr_info l3; 659 unsigned char *l4_hdr; 660 unsigned char *exthdr; 661 u8 l4_proto_tmp; 662 __be16 frag_off; 663 664 /* find outer header point */ 665 l3.hdr = skb_network_header(skb); 666 l4_hdr = skb_transport_header(skb); 667 668 if (skb->protocol == htons(ETH_P_IPV6)) { 669 exthdr = l3.hdr + sizeof(*l3.v6); 670 l4_proto_tmp = l3.v6->nexthdr; 671 if (l4_hdr != exthdr) 672 ipv6_skip_exthdr(skb, exthdr - skb->data, 673 &l4_proto_tmp, &frag_off); 674 } else if (skb->protocol == htons(ETH_P_IP)) { 675 l4_proto_tmp = l3.v4->protocol; 676 } else { 677 return -EINVAL; 678 } 679 680 *ol4_proto = l4_proto_tmp; 681 682 /* tunnel packet */ 683 if (!skb->encapsulation) { 684 *il4_proto = 0; 685 return 0; 686 } 687 688 /* find inner header point */ 689 l3.hdr = skb_inner_network_header(skb); 690 l4_hdr = skb_inner_transport_header(skb); 691 692 if (l3.v6->version == 6) { 693 exthdr = l3.hdr + sizeof(*l3.v6); 694 l4_proto_tmp = l3.v6->nexthdr; 695 if (l4_hdr != exthdr) 696 ipv6_skip_exthdr(skb, exthdr - skb->data, 697 &l4_proto_tmp, &frag_off); 698 } else if (l3.v4->version == 4) { 699 l4_proto_tmp = l3.v4->protocol; 700 } 701 702 *il4_proto = l4_proto_tmp; 703 704 return 0; 705 } 706 707 static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto, 708 u8 il4_proto, u32 *type_cs_vlan_tso, 709 u32 *ol_type_vlan_len_msec) 710 { 711 union l3_hdr_info l3; 712 union l4_hdr_info l4; 713 unsigned char *l2_hdr; 714 u8 l4_proto = ol4_proto; 715 u32 ol2_len; 716 u32 ol3_len; 717 u32 ol4_len; 718 u32 l2_len; 719 u32 l3_len; 720 721 l3.hdr = skb_network_header(skb); 722 l4.hdr = skb_transport_header(skb); 723 724 /* compute L2 header size for normal packet, defined in 2 Bytes */ 725 l2_len = l3.hdr - skb->data; 726 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M, 727 HNS3_TXD_L2LEN_S, l2_len >> 1); 728 729 /* tunnel packet*/ 730 if (skb->encapsulation) { 731 /* compute OL2 header size, defined in 2 Bytes */ 732 ol2_len = l2_len; 733 hnae3_set_field(*ol_type_vlan_len_msec, 734 HNS3_TXD_L2LEN_M, 735 HNS3_TXD_L2LEN_S, ol2_len >> 1); 736 737 /* compute OL3 header size, defined in 4 Bytes */ 738 ol3_len = l4.hdr - l3.hdr; 739 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M, 740 HNS3_TXD_L3LEN_S, ol3_len >> 2); 741 742 /* MAC in UDP, MAC in GRE (0x6558)*/ 743 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) { 744 /* switch MAC header ptr from outer to inner header.*/ 745 l2_hdr = skb_inner_mac_header(skb); 746 747 /* compute OL4 header size, defined in 4 Bytes. */ 748 ol4_len = l2_hdr - l4.hdr; 749 hnae3_set_field(*ol_type_vlan_len_msec, 750 HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S, 751 ol4_len >> 2); 752 753 /* switch IP header ptr from outer to inner header */ 754 l3.hdr = skb_inner_network_header(skb); 755 756 /* compute inner l2 header size, defined in 2 Bytes. */ 757 l2_len = l3.hdr - l2_hdr; 758 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M, 759 HNS3_TXD_L2LEN_S, l2_len >> 1); 760 } else { 761 /* skb packet types not supported by hardware, 762 * txbd len fild doesn't be filled. 763 */ 764 return; 765 } 766 767 /* switch L4 header pointer from outer to inner */ 768 l4.hdr = skb_inner_transport_header(skb); 769 770 l4_proto = il4_proto; 771 } 772 773 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 774 l3_len = l4.hdr - l3.hdr; 775 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M, 776 HNS3_TXD_L3LEN_S, l3_len >> 2); 777 778 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 779 switch (l4_proto) { 780 case IPPROTO_TCP: 781 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 782 HNS3_TXD_L4LEN_S, l4.tcp->doff); 783 break; 784 case IPPROTO_SCTP: 785 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 786 HNS3_TXD_L4LEN_S, 787 (sizeof(struct sctphdr) >> 2)); 788 break; 789 case IPPROTO_UDP: 790 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 791 HNS3_TXD_L4LEN_S, 792 (sizeof(struct udphdr) >> 2)); 793 break; 794 default: 795 /* skb packet types not supported by hardware, 796 * txbd len fild doesn't be filled. 797 */ 798 return; 799 } 800 } 801 802 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 803 * and it is udp packet, which has a dest port as the IANA assigned. 804 * the hardware is expected to do the checksum offload, but the 805 * hardware will not do the checksum offload when udp dest port is 806 * 4789. 807 */ 808 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 809 { 810 #define IANA_VXLAN_PORT 4789 811 union l4_hdr_info l4; 812 813 l4.hdr = skb_transport_header(skb); 814 815 if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT))) 816 return false; 817 818 skb_checksum_help(skb); 819 820 return true; 821 } 822 823 static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto, 824 u8 il4_proto, u32 *type_cs_vlan_tso, 825 u32 *ol_type_vlan_len_msec) 826 { 827 union l3_hdr_info l3; 828 u32 l4_proto = ol4_proto; 829 830 l3.hdr = skb_network_header(skb); 831 832 /* define OL3 type and tunnel type(OL4).*/ 833 if (skb->encapsulation) { 834 /* define outer network header type.*/ 835 if (skb->protocol == htons(ETH_P_IP)) { 836 if (skb_is_gso(skb)) 837 hnae3_set_field(*ol_type_vlan_len_msec, 838 HNS3_TXD_OL3T_M, 839 HNS3_TXD_OL3T_S, 840 HNS3_OL3T_IPV4_CSUM); 841 else 842 hnae3_set_field(*ol_type_vlan_len_msec, 843 HNS3_TXD_OL3T_M, 844 HNS3_TXD_OL3T_S, 845 HNS3_OL3T_IPV4_NO_CSUM); 846 847 } else if (skb->protocol == htons(ETH_P_IPV6)) { 848 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M, 849 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6); 850 } 851 852 /* define tunnel type(OL4).*/ 853 switch (l4_proto) { 854 case IPPROTO_UDP: 855 hnae3_set_field(*ol_type_vlan_len_msec, 856 HNS3_TXD_TUNTYPE_M, 857 HNS3_TXD_TUNTYPE_S, 858 HNS3_TUN_MAC_IN_UDP); 859 break; 860 case IPPROTO_GRE: 861 hnae3_set_field(*ol_type_vlan_len_msec, 862 HNS3_TXD_TUNTYPE_M, 863 HNS3_TXD_TUNTYPE_S, 864 HNS3_TUN_NVGRE); 865 break; 866 default: 867 /* drop the skb tunnel packet if hardware don't support, 868 * because hardware can't calculate csum when TSO. 869 */ 870 if (skb_is_gso(skb)) 871 return -EDOM; 872 873 /* the stack computes the IP header already, 874 * driver calculate l4 checksum when not TSO. 875 */ 876 skb_checksum_help(skb); 877 return 0; 878 } 879 880 l3.hdr = skb_inner_network_header(skb); 881 l4_proto = il4_proto; 882 } 883 884 if (l3.v4->version == 4) { 885 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M, 886 HNS3_TXD_L3T_S, HNS3_L3T_IPV4); 887 888 /* the stack computes the IP header already, the only time we 889 * need the hardware to recompute it is in the case of TSO. 890 */ 891 if (skb_is_gso(skb)) 892 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 893 } else if (l3.v6->version == 6) { 894 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M, 895 HNS3_TXD_L3T_S, HNS3_L3T_IPV6); 896 } 897 898 switch (l4_proto) { 899 case IPPROTO_TCP: 900 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 901 hnae3_set_field(*type_cs_vlan_tso, 902 HNS3_TXD_L4T_M, 903 HNS3_TXD_L4T_S, 904 HNS3_L4T_TCP); 905 break; 906 case IPPROTO_UDP: 907 if (hns3_tunnel_csum_bug(skb)) 908 break; 909 910 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 911 hnae3_set_field(*type_cs_vlan_tso, 912 HNS3_TXD_L4T_M, 913 HNS3_TXD_L4T_S, 914 HNS3_L4T_UDP); 915 break; 916 case IPPROTO_SCTP: 917 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 918 hnae3_set_field(*type_cs_vlan_tso, 919 HNS3_TXD_L4T_M, 920 HNS3_TXD_L4T_S, 921 HNS3_L4T_SCTP); 922 break; 923 default: 924 /* drop the skb tunnel packet if hardware don't support, 925 * because hardware can't calculate csum when TSO. 926 */ 927 if (skb_is_gso(skb)) 928 return -EDOM; 929 930 /* the stack computes the IP header already, 931 * driver calculate l4 checksum when not TSO. 932 */ 933 skb_checksum_help(skb); 934 return 0; 935 } 936 937 return 0; 938 } 939 940 static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end) 941 { 942 /* Config bd buffer end */ 943 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M, 944 HNS3_TXD_BDTYPE_S, 0); 945 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end); 946 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1); 947 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0); 948 } 949 950 static int hns3_fill_desc_vtags(struct sk_buff *skb, 951 struct hns3_enet_ring *tx_ring, 952 u32 *inner_vlan_flag, 953 u32 *out_vlan_flag, 954 u16 *inner_vtag, 955 u16 *out_vtag) 956 { 957 #define HNS3_TX_VLAN_PRIO_SHIFT 13 958 959 if (skb->protocol == htons(ETH_P_8021Q) && 960 !(tx_ring->tqp->handle->kinfo.netdev->features & 961 NETIF_F_HW_VLAN_CTAG_TX)) { 962 /* When HW VLAN acceleration is turned off, and the stack 963 * sets the protocol to 802.1q, the driver just need to 964 * set the protocol to the encapsulated ethertype. 965 */ 966 skb->protocol = vlan_get_protocol(skb); 967 return 0; 968 } 969 970 if (skb_vlan_tag_present(skb)) { 971 u16 vlan_tag; 972 973 vlan_tag = skb_vlan_tag_get(skb); 974 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT; 975 976 /* Based on hw strategy, use out_vtag in two layer tag case, 977 * and use inner_vtag in one tag case. 978 */ 979 if (skb->protocol == htons(ETH_P_8021Q)) { 980 hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1); 981 *out_vtag = vlan_tag; 982 } else { 983 hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1); 984 *inner_vtag = vlan_tag; 985 } 986 } else if (skb->protocol == htons(ETH_P_8021Q)) { 987 struct vlan_ethhdr *vhdr; 988 int rc; 989 990 rc = skb_cow_head(skb, 0); 991 if (rc < 0) 992 return rc; 993 vhdr = (struct vlan_ethhdr *)skb->data; 994 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7) 995 << HNS3_TX_VLAN_PRIO_SHIFT); 996 } 997 998 skb->protocol = vlan_get_protocol(skb); 999 return 0; 1000 } 1001 1002 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 1003 int size, int frag_end, enum hns_desc_type type) 1004 { 1005 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1006 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1007 struct device *dev = ring_to_dev(ring); 1008 u32 ol_type_vlan_len_msec = 0; 1009 u16 bdtp_fe_sc_vld_ra_ri = 0; 1010 struct skb_frag_struct *frag; 1011 unsigned int frag_buf_num; 1012 u32 type_cs_vlan_tso = 0; 1013 struct sk_buff *skb; 1014 u16 inner_vtag = 0; 1015 u16 out_vtag = 0; 1016 unsigned int k; 1017 int sizeoflast; 1018 u32 paylen = 0; 1019 dma_addr_t dma; 1020 u16 mss = 0; 1021 u8 ol4_proto; 1022 u8 il4_proto; 1023 int ret; 1024 1025 if (type == DESC_TYPE_SKB) { 1026 skb = (struct sk_buff *)priv; 1027 paylen = skb->len; 1028 1029 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso, 1030 &ol_type_vlan_len_msec, 1031 &inner_vtag, &out_vtag); 1032 if (unlikely(ret)) 1033 return ret; 1034 1035 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1036 skb_reset_mac_len(skb); 1037 1038 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1039 if (ret) 1040 return ret; 1041 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto, 1042 &type_cs_vlan_tso, 1043 &ol_type_vlan_len_msec); 1044 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto, 1045 &type_cs_vlan_tso, 1046 &ol_type_vlan_len_msec); 1047 if (ret) 1048 return ret; 1049 1050 ret = hns3_set_tso(skb, &paylen, &mss, 1051 &type_cs_vlan_tso); 1052 if (ret) 1053 return ret; 1054 } 1055 1056 /* Set txbd */ 1057 desc->tx.ol_type_vlan_len_msec = 1058 cpu_to_le32(ol_type_vlan_len_msec); 1059 desc->tx.type_cs_vlan_tso_len = 1060 cpu_to_le32(type_cs_vlan_tso); 1061 desc->tx.paylen = cpu_to_le32(paylen); 1062 desc->tx.mss = cpu_to_le16(mss); 1063 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1064 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1065 1066 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1067 } else { 1068 frag = (struct skb_frag_struct *)priv; 1069 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1070 } 1071 1072 if (dma_mapping_error(ring->dev, dma)) { 1073 ring->stats.sw_err_cnt++; 1074 return -ENOMEM; 1075 } 1076 1077 desc_cb->length = size; 1078 1079 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1080 sizeoflast = size % HNS3_MAX_BD_SIZE; 1081 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1082 1083 /* When frag size is bigger than hardware limit, split this frag */ 1084 for (k = 0; k < frag_buf_num; k++) { 1085 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */ 1086 desc_cb->priv = priv; 1087 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k; 1088 desc_cb->type = (type == DESC_TYPE_SKB && !k) ? 1089 DESC_TYPE_SKB : DESC_TYPE_PAGE; 1090 1091 /* now, fill the descriptor */ 1092 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1093 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1094 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1095 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, 1096 frag_end && (k == frag_buf_num - 1) ? 1097 1 : 0); 1098 desc->tx.bdtp_fe_sc_vld_ra_ri = 1099 cpu_to_le16(bdtp_fe_sc_vld_ra_ri); 1100 1101 /* move ring pointer to next.*/ 1102 ring_ptr_move_fw(ring, next_to_use); 1103 1104 desc_cb = &ring->desc_cb[ring->next_to_use]; 1105 desc = &ring->desc[ring->next_to_use]; 1106 } 1107 1108 return 0; 1109 } 1110 1111 static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum, 1112 struct hns3_enet_ring *ring) 1113 { 1114 struct sk_buff *skb = *out_skb; 1115 struct sk_buff *new_skb = NULL; 1116 struct skb_frag_struct *frag; 1117 int bdnum_for_frag; 1118 int frag_num; 1119 int buf_num; 1120 int size; 1121 int i; 1122 1123 size = skb_headlen(skb); 1124 buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1125 1126 frag_num = skb_shinfo(skb)->nr_frags; 1127 for (i = 0; i < frag_num; i++) { 1128 frag = &skb_shinfo(skb)->frags[i]; 1129 size = skb_frag_size(frag); 1130 bdnum_for_frag = 1131 (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1132 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG) 1133 return -ENOMEM; 1134 1135 buf_num += bdnum_for_frag; 1136 } 1137 1138 if (unlikely(buf_num > HNS3_MAX_BD_PER_FRAG)) { 1139 buf_num = (skb->len + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1140 if (ring_space(ring) < buf_num) 1141 return -EBUSY; 1142 /* manual split the send packet */ 1143 new_skb = skb_copy(skb, GFP_ATOMIC); 1144 if (!new_skb) 1145 return -ENOMEM; 1146 dev_kfree_skb_any(skb); 1147 *out_skb = new_skb; 1148 } 1149 1150 if (unlikely(ring_space(ring) < buf_num)) 1151 return -EBUSY; 1152 1153 *bnum = buf_num; 1154 return 0; 1155 } 1156 1157 static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum, 1158 struct hns3_enet_ring *ring) 1159 { 1160 struct sk_buff *skb = *out_skb; 1161 struct sk_buff *new_skb = NULL; 1162 int buf_num; 1163 1164 /* No. of segments (plus a header) */ 1165 buf_num = skb_shinfo(skb)->nr_frags + 1; 1166 1167 if (unlikely(buf_num > HNS3_MAX_BD_PER_FRAG)) { 1168 buf_num = (skb->len + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1169 if (ring_space(ring) < buf_num) 1170 return -EBUSY; 1171 /* manual split the send packet */ 1172 new_skb = skb_copy(skb, GFP_ATOMIC); 1173 if (!new_skb) 1174 return -ENOMEM; 1175 dev_kfree_skb_any(skb); 1176 *out_skb = new_skb; 1177 } 1178 1179 if (unlikely(ring_space(ring) < buf_num)) 1180 return -EBUSY; 1181 1182 *bnum = buf_num; 1183 1184 return 0; 1185 } 1186 1187 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1188 { 1189 struct device *dev = ring_to_dev(ring); 1190 unsigned int i; 1191 1192 for (i = 0; i < ring->desc_num; i++) { 1193 /* check if this is where we started */ 1194 if (ring->next_to_use == next_to_use_orig) 1195 break; 1196 1197 /* unmap the descriptor dma address */ 1198 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB) 1199 dma_unmap_single(dev, 1200 ring->desc_cb[ring->next_to_use].dma, 1201 ring->desc_cb[ring->next_to_use].length, 1202 DMA_TO_DEVICE); 1203 else if (ring->desc_cb[ring->next_to_use].length) 1204 dma_unmap_page(dev, 1205 ring->desc_cb[ring->next_to_use].dma, 1206 ring->desc_cb[ring->next_to_use].length, 1207 DMA_TO_DEVICE); 1208 1209 ring->desc_cb[ring->next_to_use].length = 0; 1210 1211 /* rollback one */ 1212 ring_ptr_move_bw(ring, next_to_use); 1213 } 1214 } 1215 1216 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1217 { 1218 struct hns3_nic_priv *priv = netdev_priv(netdev); 1219 struct hns3_nic_ring_data *ring_data = 1220 &tx_ring_data(priv, skb->queue_mapping); 1221 struct hns3_enet_ring *ring = ring_data->ring; 1222 struct netdev_queue *dev_queue; 1223 struct skb_frag_struct *frag; 1224 int next_to_use_head; 1225 int next_to_use_frag; 1226 int buf_num; 1227 int seg_num; 1228 int size; 1229 int ret; 1230 int i; 1231 1232 /* Prefetch the data used later */ 1233 prefetch(skb->data); 1234 1235 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) { 1236 case -EBUSY: 1237 u64_stats_update_begin(&ring->syncp); 1238 ring->stats.tx_busy++; 1239 u64_stats_update_end(&ring->syncp); 1240 1241 goto out_net_tx_busy; 1242 case -ENOMEM: 1243 u64_stats_update_begin(&ring->syncp); 1244 ring->stats.sw_err_cnt++; 1245 u64_stats_update_end(&ring->syncp); 1246 netdev_err(netdev, "no memory to xmit!\n"); 1247 1248 goto out_err_tx_ok; 1249 default: 1250 break; 1251 } 1252 1253 /* No. of segments (plus a header) */ 1254 seg_num = skb_shinfo(skb)->nr_frags + 1; 1255 /* Fill the first part */ 1256 size = skb_headlen(skb); 1257 1258 next_to_use_head = ring->next_to_use; 1259 1260 ret = priv->ops.fill_desc(ring, skb, size, seg_num == 1 ? 1 : 0, 1261 DESC_TYPE_SKB); 1262 if (ret) 1263 goto head_fill_err; 1264 1265 next_to_use_frag = ring->next_to_use; 1266 /* Fill the fragments */ 1267 for (i = 1; i < seg_num; i++) { 1268 frag = &skb_shinfo(skb)->frags[i - 1]; 1269 size = skb_frag_size(frag); 1270 1271 ret = priv->ops.fill_desc(ring, frag, size, 1272 seg_num - 1 == i ? 1 : 0, 1273 DESC_TYPE_PAGE); 1274 1275 if (ret) 1276 goto frag_fill_err; 1277 } 1278 1279 /* Complete translate all packets */ 1280 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index); 1281 netdev_tx_sent_queue(dev_queue, skb->len); 1282 1283 wmb(); /* Commit all data before submit */ 1284 1285 hnae3_queue_xmit(ring->tqp, buf_num); 1286 1287 return NETDEV_TX_OK; 1288 1289 frag_fill_err: 1290 hns3_clear_desc(ring, next_to_use_frag); 1291 1292 head_fill_err: 1293 hns3_clear_desc(ring, next_to_use_head); 1294 1295 out_err_tx_ok: 1296 dev_kfree_skb_any(skb); 1297 return NETDEV_TX_OK; 1298 1299 out_net_tx_busy: 1300 netif_stop_subqueue(netdev, ring_data->queue_index); 1301 smp_mb(); /* Commit all data before submit */ 1302 1303 return NETDEV_TX_BUSY; 1304 } 1305 1306 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1307 { 1308 struct hnae3_handle *h = hns3_get_handle(netdev); 1309 struct sockaddr *mac_addr = p; 1310 int ret; 1311 1312 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1313 return -EADDRNOTAVAIL; 1314 1315 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1316 netdev_info(netdev, "already using mac address %pM\n", 1317 mac_addr->sa_data); 1318 return 0; 1319 } 1320 1321 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1322 if (ret) { 1323 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1324 return ret; 1325 } 1326 1327 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1328 1329 return 0; 1330 } 1331 1332 static int hns3_nic_do_ioctl(struct net_device *netdev, 1333 struct ifreq *ifr, int cmd) 1334 { 1335 struct hnae3_handle *h = hns3_get_handle(netdev); 1336 1337 if (!netif_running(netdev)) 1338 return -EINVAL; 1339 1340 if (!h->ae_algo->ops->do_ioctl) 1341 return -EOPNOTSUPP; 1342 1343 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 1344 } 1345 1346 static int hns3_nic_set_features(struct net_device *netdev, 1347 netdev_features_t features) 1348 { 1349 netdev_features_t changed = netdev->features ^ features; 1350 struct hns3_nic_priv *priv = netdev_priv(netdev); 1351 struct hnae3_handle *h = priv->ae_handle; 1352 bool enable; 1353 int ret; 1354 1355 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) { 1356 if (features & (NETIF_F_TSO | NETIF_F_TSO6)) 1357 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 1358 else 1359 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 1360 } 1361 1362 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 1363 enable = !!(features & NETIF_F_GRO_HW); 1364 ret = h->ae_algo->ops->set_gro_en(h, enable); 1365 if (ret) 1366 return ret; 1367 } 1368 1369 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 1370 h->ae_algo->ops->enable_vlan_filter) { 1371 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER); 1372 h->ae_algo->ops->enable_vlan_filter(h, enable); 1373 } 1374 1375 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1376 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1377 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 1378 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 1379 if (ret) 1380 return ret; 1381 } 1382 1383 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 1384 enable = !!(features & NETIF_F_NTUPLE); 1385 h->ae_algo->ops->enable_fd(h, enable); 1386 } 1387 1388 netdev->features = features; 1389 return 0; 1390 } 1391 1392 static void hns3_nic_get_stats64(struct net_device *netdev, 1393 struct rtnl_link_stats64 *stats) 1394 { 1395 struct hns3_nic_priv *priv = netdev_priv(netdev); 1396 int queue_num = priv->ae_handle->kinfo.num_tqps; 1397 struct hnae3_handle *handle = priv->ae_handle; 1398 struct hns3_enet_ring *ring; 1399 u64 rx_length_errors = 0; 1400 u64 rx_crc_errors = 0; 1401 u64 rx_multicast = 0; 1402 unsigned int start; 1403 u64 tx_errors = 0; 1404 u64 rx_errors = 0; 1405 unsigned int idx; 1406 u64 tx_bytes = 0; 1407 u64 rx_bytes = 0; 1408 u64 tx_pkts = 0; 1409 u64 rx_pkts = 0; 1410 u64 tx_drop = 0; 1411 u64 rx_drop = 0; 1412 1413 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1414 return; 1415 1416 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1417 1418 for (idx = 0; idx < queue_num; idx++) { 1419 /* fetch the tx stats */ 1420 ring = priv->ring_data[idx].ring; 1421 do { 1422 start = u64_stats_fetch_begin_irq(&ring->syncp); 1423 tx_bytes += ring->stats.tx_bytes; 1424 tx_pkts += ring->stats.tx_pkts; 1425 tx_drop += ring->stats.sw_err_cnt; 1426 tx_errors += ring->stats.sw_err_cnt; 1427 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1428 1429 /* fetch the rx stats */ 1430 ring = priv->ring_data[idx + queue_num].ring; 1431 do { 1432 start = u64_stats_fetch_begin_irq(&ring->syncp); 1433 rx_bytes += ring->stats.rx_bytes; 1434 rx_pkts += ring->stats.rx_pkts; 1435 rx_drop += ring->stats.non_vld_descs; 1436 rx_drop += ring->stats.l2_err; 1437 rx_errors += ring->stats.non_vld_descs; 1438 rx_errors += ring->stats.l2_err; 1439 rx_crc_errors += ring->stats.l2_err; 1440 rx_crc_errors += ring->stats.l3l4_csum_err; 1441 rx_multicast += ring->stats.rx_multicast; 1442 rx_length_errors += ring->stats.err_pkt_len; 1443 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1444 } 1445 1446 stats->tx_bytes = tx_bytes; 1447 stats->tx_packets = tx_pkts; 1448 stats->rx_bytes = rx_bytes; 1449 stats->rx_packets = rx_pkts; 1450 1451 stats->rx_errors = rx_errors; 1452 stats->multicast = rx_multicast; 1453 stats->rx_length_errors = rx_length_errors; 1454 stats->rx_crc_errors = rx_crc_errors; 1455 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1456 1457 stats->tx_errors = tx_errors; 1458 stats->rx_dropped = rx_drop; 1459 stats->tx_dropped = tx_drop; 1460 stats->collisions = netdev->stats.collisions; 1461 stats->rx_over_errors = netdev->stats.rx_over_errors; 1462 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1463 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1464 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1465 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1466 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1467 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1468 stats->tx_window_errors = netdev->stats.tx_window_errors; 1469 stats->rx_compressed = netdev->stats.rx_compressed; 1470 stats->tx_compressed = netdev->stats.tx_compressed; 1471 } 1472 1473 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1474 { 1475 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1476 struct hnae3_handle *h = hns3_get_handle(netdev); 1477 struct hnae3_knic_private_info *kinfo = &h->kinfo; 1478 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map; 1479 u8 tc = mqprio_qopt->qopt.num_tc; 1480 u16 mode = mqprio_qopt->mode; 1481 u8 hw = mqprio_qopt->qopt.hw; 1482 1483 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1484 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1485 return -EOPNOTSUPP; 1486 1487 if (tc > HNAE3_MAX_TC) 1488 return -EINVAL; 1489 1490 if (!netdev) 1491 return -EINVAL; 1492 1493 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1494 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP; 1495 } 1496 1497 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1498 void *type_data) 1499 { 1500 if (type != TC_SETUP_QDISC_MQPRIO) 1501 return -EOPNOTSUPP; 1502 1503 return hns3_setup_tc(dev, type_data); 1504 } 1505 1506 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1507 __be16 proto, u16 vid) 1508 { 1509 struct hnae3_handle *h = hns3_get_handle(netdev); 1510 struct hns3_nic_priv *priv = netdev_priv(netdev); 1511 int ret = -EIO; 1512 1513 if (h->ae_algo->ops->set_vlan_filter) 1514 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1515 1516 if (!ret) 1517 set_bit(vid, priv->active_vlans); 1518 1519 return ret; 1520 } 1521 1522 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1523 __be16 proto, u16 vid) 1524 { 1525 struct hnae3_handle *h = hns3_get_handle(netdev); 1526 struct hns3_nic_priv *priv = netdev_priv(netdev); 1527 int ret = -EIO; 1528 1529 if (h->ae_algo->ops->set_vlan_filter) 1530 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1531 1532 if (!ret) 1533 clear_bit(vid, priv->active_vlans); 1534 1535 return ret; 1536 } 1537 1538 static int hns3_restore_vlan(struct net_device *netdev) 1539 { 1540 struct hns3_nic_priv *priv = netdev_priv(netdev); 1541 int ret = 0; 1542 u16 vid; 1543 1544 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 1545 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 1546 if (ret) { 1547 netdev_err(netdev, "Restore vlan: %d filter, ret:%d\n", 1548 vid, ret); 1549 return ret; 1550 } 1551 } 1552 1553 return ret; 1554 } 1555 1556 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1557 u8 qos, __be16 vlan_proto) 1558 { 1559 struct hnae3_handle *h = hns3_get_handle(netdev); 1560 int ret = -EIO; 1561 1562 if (h->ae_algo->ops->set_vf_vlan_filter) 1563 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1564 qos, vlan_proto); 1565 1566 return ret; 1567 } 1568 1569 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1570 { 1571 struct hnae3_handle *h = hns3_get_handle(netdev); 1572 int ret; 1573 1574 if (!h->ae_algo->ops->set_mtu) 1575 return -EOPNOTSUPP; 1576 1577 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 1578 if (ret) 1579 netdev_err(netdev, "failed to change MTU in hardware %d\n", 1580 ret); 1581 else 1582 netdev->mtu = new_mtu; 1583 1584 return ret; 1585 } 1586 1587 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 1588 { 1589 struct hns3_nic_priv *priv = netdev_priv(ndev); 1590 struct hns3_enet_ring *tx_ring = NULL; 1591 int timeout_queue = 0; 1592 int hw_head, hw_tail; 1593 int i; 1594 1595 /* Find the stopped queue the same way the stack does */ 1596 for (i = 0; i < ndev->real_num_tx_queues; i++) { 1597 struct netdev_queue *q; 1598 unsigned long trans_start; 1599 1600 q = netdev_get_tx_queue(ndev, i); 1601 trans_start = q->trans_start; 1602 if (netif_xmit_stopped(q) && 1603 time_after(jiffies, 1604 (trans_start + ndev->watchdog_timeo))) { 1605 timeout_queue = i; 1606 break; 1607 } 1608 } 1609 1610 if (i == ndev->num_tx_queues) { 1611 netdev_info(ndev, 1612 "no netdev TX timeout queue found, timeout count: %llu\n", 1613 priv->tx_timeout_count); 1614 return false; 1615 } 1616 1617 tx_ring = priv->ring_data[timeout_queue].ring; 1618 1619 hw_head = readl_relaxed(tx_ring->tqp->io_base + 1620 HNS3_RING_TX_RING_HEAD_REG); 1621 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 1622 HNS3_RING_TX_RING_TAIL_REG); 1623 netdev_info(ndev, 1624 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n", 1625 priv->tx_timeout_count, 1626 timeout_queue, 1627 tx_ring->next_to_use, 1628 tx_ring->next_to_clean, 1629 hw_head, 1630 hw_tail, 1631 readl(tx_ring->tqp_vector->mask_addr)); 1632 1633 return true; 1634 } 1635 1636 static void hns3_nic_net_timeout(struct net_device *ndev) 1637 { 1638 struct hns3_nic_priv *priv = netdev_priv(ndev); 1639 struct hnae3_handle *h = priv->ae_handle; 1640 1641 if (!hns3_get_tx_timeo_queue_info(ndev)) 1642 return; 1643 1644 priv->tx_timeout_count++; 1645 1646 /* request the reset, and let the hclge to determine 1647 * which reset level should be done 1648 */ 1649 if (h->ae_algo->ops->reset_event) 1650 h->ae_algo->ops->reset_event(h->pdev, h); 1651 } 1652 1653 static const struct net_device_ops hns3_nic_netdev_ops = { 1654 .ndo_open = hns3_nic_net_open, 1655 .ndo_stop = hns3_nic_net_stop, 1656 .ndo_start_xmit = hns3_nic_net_xmit, 1657 .ndo_tx_timeout = hns3_nic_net_timeout, 1658 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 1659 .ndo_do_ioctl = hns3_nic_do_ioctl, 1660 .ndo_change_mtu = hns3_nic_change_mtu, 1661 .ndo_set_features = hns3_nic_set_features, 1662 .ndo_get_stats64 = hns3_nic_get_stats64, 1663 .ndo_setup_tc = hns3_nic_setup_tc, 1664 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 1665 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 1666 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 1667 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 1668 }; 1669 1670 static bool hns3_is_phys_func(struct pci_dev *pdev) 1671 { 1672 u32 dev_id = pdev->device; 1673 1674 switch (dev_id) { 1675 case HNAE3_DEV_ID_GE: 1676 case HNAE3_DEV_ID_25GE: 1677 case HNAE3_DEV_ID_25GE_RDMA: 1678 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 1679 case HNAE3_DEV_ID_50GE_RDMA: 1680 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 1681 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 1682 return true; 1683 case HNAE3_DEV_ID_100G_VF: 1684 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF: 1685 return false; 1686 default: 1687 dev_warn(&pdev->dev, "un-recognized pci device-id %d", 1688 dev_id); 1689 } 1690 1691 return false; 1692 } 1693 1694 static void hns3_disable_sriov(struct pci_dev *pdev) 1695 { 1696 /* If our VFs are assigned we cannot shut down SR-IOV 1697 * without causing issues, so just leave the hardware 1698 * available but disabled 1699 */ 1700 if (pci_vfs_assigned(pdev)) { 1701 dev_warn(&pdev->dev, 1702 "disabling driver while VFs are assigned\n"); 1703 return; 1704 } 1705 1706 pci_disable_sriov(pdev); 1707 } 1708 1709 static void hns3_get_dev_capability(struct pci_dev *pdev, 1710 struct hnae3_ae_dev *ae_dev) 1711 { 1712 if (pdev->revision >= 0x21) { 1713 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1); 1714 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1); 1715 } 1716 } 1717 1718 /* hns3_probe - Device initialization routine 1719 * @pdev: PCI device information struct 1720 * @ent: entry in hns3_pci_tbl 1721 * 1722 * hns3_probe initializes a PF identified by a pci_dev structure. 1723 * The OS initialization, configuring of the PF private structure, 1724 * and a hardware reset occur. 1725 * 1726 * Returns 0 on success, negative on failure 1727 */ 1728 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1729 { 1730 struct hnae3_ae_dev *ae_dev; 1731 int ret; 1732 1733 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), 1734 GFP_KERNEL); 1735 if (!ae_dev) { 1736 ret = -ENOMEM; 1737 return ret; 1738 } 1739 1740 ae_dev->pdev = pdev; 1741 ae_dev->flag = ent->driver_data; 1742 ae_dev->dev_type = HNAE3_DEV_KNIC; 1743 ae_dev->reset_type = HNAE3_NONE_RESET; 1744 hns3_get_dev_capability(pdev, ae_dev); 1745 pci_set_drvdata(pdev, ae_dev); 1746 1747 ret = hnae3_register_ae_dev(ae_dev); 1748 if (ret) { 1749 devm_kfree(&pdev->dev, ae_dev); 1750 pci_set_drvdata(pdev, NULL); 1751 } 1752 1753 return ret; 1754 } 1755 1756 /* hns3_remove - Device removal routine 1757 * @pdev: PCI device information struct 1758 */ 1759 static void hns3_remove(struct pci_dev *pdev) 1760 { 1761 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1762 1763 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 1764 hns3_disable_sriov(pdev); 1765 1766 hnae3_unregister_ae_dev(ae_dev); 1767 pci_set_drvdata(pdev, NULL); 1768 } 1769 1770 /** 1771 * hns3_pci_sriov_configure 1772 * @pdev: pointer to a pci_dev structure 1773 * @num_vfs: number of VFs to allocate 1774 * 1775 * Enable or change the number of VFs. Called when the user updates the number 1776 * of VFs in sysfs. 1777 **/ 1778 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 1779 { 1780 int ret; 1781 1782 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 1783 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 1784 return -EINVAL; 1785 } 1786 1787 if (num_vfs) { 1788 ret = pci_enable_sriov(pdev, num_vfs); 1789 if (ret) 1790 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 1791 else 1792 return num_vfs; 1793 } else if (!pci_vfs_assigned(pdev)) { 1794 pci_disable_sriov(pdev); 1795 } else { 1796 dev_warn(&pdev->dev, 1797 "Unable to free VFs because some are assigned to VMs.\n"); 1798 } 1799 1800 return 0; 1801 } 1802 1803 static void hns3_shutdown(struct pci_dev *pdev) 1804 { 1805 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1806 1807 hnae3_unregister_ae_dev(ae_dev); 1808 devm_kfree(&pdev->dev, ae_dev); 1809 pci_set_drvdata(pdev, NULL); 1810 1811 if (system_state == SYSTEM_POWER_OFF) 1812 pci_set_power_state(pdev, PCI_D3hot); 1813 } 1814 1815 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 1816 pci_channel_state_t state) 1817 { 1818 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1819 pci_ers_result_t ret; 1820 1821 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state); 1822 1823 if (state == pci_channel_io_perm_failure) 1824 return PCI_ERS_RESULT_DISCONNECT; 1825 1826 if (!ae_dev) { 1827 dev_err(&pdev->dev, 1828 "Can't recover - error happened during device init\n"); 1829 return PCI_ERS_RESULT_NONE; 1830 } 1831 1832 if (ae_dev->ops->handle_hw_ras_error) 1833 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 1834 else 1835 return PCI_ERS_RESULT_NONE; 1836 1837 return ret; 1838 } 1839 1840 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 1841 { 1842 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1843 struct device *dev = &pdev->dev; 1844 1845 dev_info(dev, "requesting reset due to PCI error\n"); 1846 1847 /* request the reset */ 1848 if (ae_dev->ops->reset_event) { 1849 ae_dev->ops->reset_event(pdev, NULL); 1850 return PCI_ERS_RESULT_RECOVERED; 1851 } 1852 1853 return PCI_ERS_RESULT_DISCONNECT; 1854 } 1855 1856 static void hns3_reset_prepare(struct pci_dev *pdev) 1857 { 1858 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1859 1860 dev_info(&pdev->dev, "hns3 flr prepare\n"); 1861 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare) 1862 ae_dev->ops->flr_prepare(ae_dev); 1863 } 1864 1865 static void hns3_reset_done(struct pci_dev *pdev) 1866 { 1867 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1868 1869 dev_info(&pdev->dev, "hns3 flr done\n"); 1870 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done) 1871 ae_dev->ops->flr_done(ae_dev); 1872 } 1873 1874 static const struct pci_error_handlers hns3_err_handler = { 1875 .error_detected = hns3_error_detected, 1876 .slot_reset = hns3_slot_reset, 1877 .reset_prepare = hns3_reset_prepare, 1878 .reset_done = hns3_reset_done, 1879 }; 1880 1881 static struct pci_driver hns3_driver = { 1882 .name = hns3_driver_name, 1883 .id_table = hns3_pci_tbl, 1884 .probe = hns3_probe, 1885 .remove = hns3_remove, 1886 .shutdown = hns3_shutdown, 1887 .sriov_configure = hns3_pci_sriov_configure, 1888 .err_handler = &hns3_err_handler, 1889 }; 1890 1891 /* set default feature to hns3 */ 1892 static void hns3_set_default_feature(struct net_device *netdev) 1893 { 1894 struct hnae3_handle *h = hns3_get_handle(netdev); 1895 struct pci_dev *pdev = h->pdev; 1896 1897 netdev->priv_flags |= IFF_UNICAST_FLT; 1898 1899 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1900 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1901 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1902 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1903 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1904 1905 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID; 1906 1907 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 1908 1909 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1910 NETIF_F_HW_VLAN_CTAG_FILTER | 1911 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1912 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1913 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1914 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1915 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1916 1917 netdev->vlan_features |= 1918 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | 1919 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 1920 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1921 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1922 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1923 1924 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1925 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1926 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1927 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1928 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1929 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1930 1931 if (pdev->revision >= 0x21) { 1932 netdev->hw_features |= NETIF_F_GRO_HW; 1933 netdev->features |= NETIF_F_GRO_HW; 1934 1935 if (!(h->flags & HNAE3_SUPPORT_VF)) { 1936 netdev->hw_features |= NETIF_F_NTUPLE; 1937 netdev->features |= NETIF_F_NTUPLE; 1938 } 1939 } 1940 } 1941 1942 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 1943 struct hns3_desc_cb *cb) 1944 { 1945 unsigned int order = hnae3_page_order(ring); 1946 struct page *p; 1947 1948 p = dev_alloc_pages(order); 1949 if (!p) 1950 return -ENOMEM; 1951 1952 cb->priv = p; 1953 cb->page_offset = 0; 1954 cb->reuse_flag = 0; 1955 cb->buf = page_address(p); 1956 cb->length = hnae3_page_size(ring); 1957 cb->type = DESC_TYPE_PAGE; 1958 1959 return 0; 1960 } 1961 1962 static void hns3_free_buffer(struct hns3_enet_ring *ring, 1963 struct hns3_desc_cb *cb) 1964 { 1965 if (cb->type == DESC_TYPE_SKB) 1966 dev_kfree_skb_any((struct sk_buff *)cb->priv); 1967 else if (!HNAE3_IS_TX_RING(ring)) 1968 put_page((struct page *)cb->priv); 1969 memset(cb, 0, sizeof(*cb)); 1970 } 1971 1972 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 1973 { 1974 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 1975 cb->length, ring_to_dma_dir(ring)); 1976 1977 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 1978 return -EIO; 1979 1980 return 0; 1981 } 1982 1983 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 1984 struct hns3_desc_cb *cb) 1985 { 1986 if (cb->type == DESC_TYPE_SKB) 1987 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 1988 ring_to_dma_dir(ring)); 1989 else if (cb->length) 1990 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 1991 ring_to_dma_dir(ring)); 1992 } 1993 1994 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 1995 { 1996 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 1997 ring->desc[i].addr = 0; 1998 } 1999 2000 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i) 2001 { 2002 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 2003 2004 if (!ring->desc_cb[i].dma) 2005 return; 2006 2007 hns3_buffer_detach(ring, i); 2008 hns3_free_buffer(ring, cb); 2009 } 2010 2011 static void hns3_free_buffers(struct hns3_enet_ring *ring) 2012 { 2013 int i; 2014 2015 for (i = 0; i < ring->desc_num; i++) 2016 hns3_free_buffer_detach(ring, i); 2017 } 2018 2019 /* free desc along with its attached buffer */ 2020 static void hns3_free_desc(struct hns3_enet_ring *ring) 2021 { 2022 int size = ring->desc_num * sizeof(ring->desc[0]); 2023 2024 hns3_free_buffers(ring); 2025 2026 if (ring->desc) { 2027 dma_free_coherent(ring_to_dev(ring), size, 2028 ring->desc, ring->desc_dma_addr); 2029 ring->desc = NULL; 2030 } 2031 } 2032 2033 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 2034 { 2035 int size = ring->desc_num * sizeof(ring->desc[0]); 2036 2037 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 2038 &ring->desc_dma_addr, GFP_KERNEL); 2039 if (!ring->desc) 2040 return -ENOMEM; 2041 2042 return 0; 2043 } 2044 2045 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring, 2046 struct hns3_desc_cb *cb) 2047 { 2048 int ret; 2049 2050 ret = hns3_alloc_buffer(ring, cb); 2051 if (ret) 2052 goto out; 2053 2054 ret = hns3_map_buffer(ring, cb); 2055 if (ret) 2056 goto out_with_buf; 2057 2058 return 0; 2059 2060 out_with_buf: 2061 hns3_free_buffer(ring, cb); 2062 out: 2063 return ret; 2064 } 2065 2066 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i) 2067 { 2068 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]); 2069 2070 if (ret) 2071 return ret; 2072 2073 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2074 2075 return 0; 2076 } 2077 2078 /* Allocate memory for raw pkg, and map with dma */ 2079 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 2080 { 2081 int i, j, ret; 2082 2083 for (i = 0; i < ring->desc_num; i++) { 2084 ret = hns3_alloc_buffer_attach(ring, i); 2085 if (ret) 2086 goto out_buffer_fail; 2087 } 2088 2089 return 0; 2090 2091 out_buffer_fail: 2092 for (j = i - 1; j >= 0; j--) 2093 hns3_free_buffer_detach(ring, j); 2094 return ret; 2095 } 2096 2097 /* detach a in-used buffer and replace with a reserved one */ 2098 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 2099 struct hns3_desc_cb *res_cb) 2100 { 2101 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2102 ring->desc_cb[i] = *res_cb; 2103 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2104 ring->desc[i].rx.bd_base_info = 0; 2105 } 2106 2107 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 2108 { 2109 ring->desc_cb[i].reuse_flag = 0; 2110 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma 2111 + ring->desc_cb[i].page_offset); 2112 ring->desc[i].rx.bd_base_info = 0; 2113 } 2114 2115 static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes, 2116 int *pkts) 2117 { 2118 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2119 2120 (*pkts) += (desc_cb->type == DESC_TYPE_SKB); 2121 (*bytes) += desc_cb->length; 2122 /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/ 2123 hns3_free_buffer_detach(ring, ring->next_to_clean); 2124 2125 ring_ptr_move_fw(ring, next_to_clean); 2126 } 2127 2128 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h) 2129 { 2130 int u = ring->next_to_use; 2131 int c = ring->next_to_clean; 2132 2133 if (unlikely(h > ring->desc_num)) 2134 return 0; 2135 2136 return u > c ? (h > c && h <= u) : (h > c || h <= u); 2137 } 2138 2139 void hns3_clean_tx_ring(struct hns3_enet_ring *ring) 2140 { 2141 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2142 struct hns3_nic_priv *priv = netdev_priv(netdev); 2143 struct netdev_queue *dev_queue; 2144 int bytes, pkts; 2145 int head; 2146 2147 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG); 2148 rmb(); /* Make sure head is ready before touch any data */ 2149 2150 if (is_ring_empty(ring) || head == ring->next_to_clean) 2151 return; /* no data to poll */ 2152 2153 if (unlikely(!is_valid_clean_head(ring, head))) { 2154 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head, 2155 ring->next_to_use, ring->next_to_clean); 2156 2157 u64_stats_update_begin(&ring->syncp); 2158 ring->stats.io_err_cnt++; 2159 u64_stats_update_end(&ring->syncp); 2160 return; 2161 } 2162 2163 bytes = 0; 2164 pkts = 0; 2165 while (head != ring->next_to_clean) { 2166 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts); 2167 /* Issue prefetch for next Tx descriptor */ 2168 prefetch(&ring->desc_cb[ring->next_to_clean]); 2169 } 2170 2171 ring->tqp_vector->tx_group.total_bytes += bytes; 2172 ring->tqp_vector->tx_group.total_packets += pkts; 2173 2174 u64_stats_update_begin(&ring->syncp); 2175 ring->stats.tx_bytes += bytes; 2176 ring->stats.tx_pkts += pkts; 2177 u64_stats_update_end(&ring->syncp); 2178 2179 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 2180 netdev_tx_completed_queue(dev_queue, pkts, bytes); 2181 2182 if (unlikely(pkts && netif_carrier_ok(netdev) && 2183 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) { 2184 /* Make sure that anybody stopping the queue after this 2185 * sees the new next_to_clean. 2186 */ 2187 smp_mb(); 2188 if (netif_tx_queue_stopped(dev_queue) && 2189 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 2190 netif_tx_wake_queue(dev_queue); 2191 ring->stats.restart_queue++; 2192 } 2193 } 2194 } 2195 2196 static int hns3_desc_unused(struct hns3_enet_ring *ring) 2197 { 2198 int ntc = ring->next_to_clean; 2199 int ntu = ring->next_to_use; 2200 2201 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 2202 } 2203 2204 static void 2205 hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count) 2206 { 2207 struct hns3_desc_cb *desc_cb; 2208 struct hns3_desc_cb res_cbs; 2209 int i, ret; 2210 2211 for (i = 0; i < cleand_count; i++) { 2212 desc_cb = &ring->desc_cb[ring->next_to_use]; 2213 if (desc_cb->reuse_flag) { 2214 u64_stats_update_begin(&ring->syncp); 2215 ring->stats.reuse_pg_cnt++; 2216 u64_stats_update_end(&ring->syncp); 2217 2218 hns3_reuse_buffer(ring, ring->next_to_use); 2219 } else { 2220 ret = hns3_reserve_buffer_map(ring, &res_cbs); 2221 if (ret) { 2222 u64_stats_update_begin(&ring->syncp); 2223 ring->stats.sw_err_cnt++; 2224 u64_stats_update_end(&ring->syncp); 2225 2226 netdev_err(ring->tqp->handle->kinfo.netdev, 2227 "hnae reserve buffer map failed.\n"); 2228 break; 2229 } 2230 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 2231 } 2232 2233 ring_ptr_move_fw(ring, next_to_use); 2234 } 2235 2236 wmb(); /* Make all data has been write before submit */ 2237 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2238 } 2239 2240 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2241 struct hns3_enet_ring *ring, int pull_len, 2242 struct hns3_desc_cb *desc_cb) 2243 { 2244 struct hns3_desc *desc; 2245 u32 truesize; 2246 int size; 2247 int last_offset; 2248 bool twobufs; 2249 2250 twobufs = ((PAGE_SIZE < 8192) && 2251 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048); 2252 2253 desc = &ring->desc[ring->next_to_clean]; 2254 size = le16_to_cpu(desc->rx.size); 2255 2256 truesize = hnae3_buf_size(ring); 2257 2258 if (!twobufs) 2259 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring); 2260 2261 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2262 size - pull_len, truesize); 2263 2264 /* Avoid re-using remote pages,flag default unreuse */ 2265 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id())) 2266 return; 2267 2268 if (twobufs) { 2269 /* If we are only owner of page we can reuse it */ 2270 if (likely(page_count(desc_cb->priv) == 1)) { 2271 /* Flip page offset to other buffer */ 2272 desc_cb->page_offset ^= truesize; 2273 2274 desc_cb->reuse_flag = 1; 2275 /* bump ref count on page before it is given*/ 2276 get_page(desc_cb->priv); 2277 } 2278 return; 2279 } 2280 2281 /* Move offset up to the next cache line */ 2282 desc_cb->page_offset += truesize; 2283 2284 if (desc_cb->page_offset <= last_offset) { 2285 desc_cb->reuse_flag = 1; 2286 /* Bump ref count on page before it is given*/ 2287 get_page(desc_cb->priv); 2288 } 2289 } 2290 2291 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2292 struct hns3_desc *desc) 2293 { 2294 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2295 int l3_type, l4_type; 2296 u32 bd_base_info; 2297 int ol4_type; 2298 u32 l234info; 2299 2300 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2301 l234info = le32_to_cpu(desc->rx.l234_info); 2302 2303 skb->ip_summed = CHECKSUM_NONE; 2304 2305 skb_checksum_none_assert(skb); 2306 2307 if (!(netdev->features & NETIF_F_RXCSUM)) 2308 return; 2309 2310 /* We MUST enable hardware checksum before enabling hardware GRO */ 2311 if (skb_shinfo(skb)->gso_size) { 2312 skb->ip_summed = CHECKSUM_UNNECESSARY; 2313 return; 2314 } 2315 2316 /* check if hardware has done checksum */ 2317 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B)) 2318 return; 2319 2320 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) || 2321 hnae3_get_bit(l234info, HNS3_RXD_L4E_B) || 2322 hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) || 2323 hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) { 2324 u64_stats_update_begin(&ring->syncp); 2325 ring->stats.l3l4_csum_err++; 2326 u64_stats_update_end(&ring->syncp); 2327 2328 return; 2329 } 2330 2331 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2332 HNS3_RXD_L3ID_S); 2333 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 2334 HNS3_RXD_L4ID_S); 2335 2336 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M, 2337 HNS3_RXD_OL4ID_S); 2338 switch (ol4_type) { 2339 case HNS3_OL4_TYPE_MAC_IN_UDP: 2340 case HNS3_OL4_TYPE_NVGRE: 2341 skb->csum_level = 1; 2342 /* fall through */ 2343 case HNS3_OL4_TYPE_NO_TUN: 2344 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 2345 if ((l3_type == HNS3_L3_TYPE_IPV4 || 2346 l3_type == HNS3_L3_TYPE_IPV6) && 2347 (l4_type == HNS3_L4_TYPE_UDP || 2348 l4_type == HNS3_L4_TYPE_TCP || 2349 l4_type == HNS3_L4_TYPE_SCTP)) 2350 skb->ip_summed = CHECKSUM_UNNECESSARY; 2351 break; 2352 default: 2353 break; 2354 } 2355 } 2356 2357 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 2358 { 2359 if (skb_has_frag_list(skb)) 2360 napi_gro_flush(&ring->tqp_vector->napi, false); 2361 2362 napi_gro_receive(&ring->tqp_vector->napi, skb); 2363 } 2364 2365 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 2366 struct hns3_desc *desc, u32 l234info, 2367 u16 *vlan_tag) 2368 { 2369 struct pci_dev *pdev = ring->tqp->handle->pdev; 2370 2371 if (pdev->revision == 0x20) { 2372 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2373 if (!(*vlan_tag & VLAN_VID_MASK)) 2374 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2375 2376 return (*vlan_tag != 0); 2377 } 2378 2379 #define HNS3_STRP_OUTER_VLAN 0x1 2380 #define HNS3_STRP_INNER_VLAN 0x2 2381 2382 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 2383 HNS3_RXD_STRP_TAGP_S)) { 2384 case HNS3_STRP_OUTER_VLAN: 2385 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2386 return true; 2387 case HNS3_STRP_INNER_VLAN: 2388 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2389 return true; 2390 default: 2391 return false; 2392 } 2393 } 2394 2395 static int hns3_alloc_skb(struct hns3_enet_ring *ring, int length, 2396 unsigned char *va) 2397 { 2398 #define HNS3_NEED_ADD_FRAG 1 2399 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2400 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2401 struct sk_buff *skb; 2402 2403 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 2404 skb = ring->skb; 2405 if (unlikely(!skb)) { 2406 netdev_err(netdev, "alloc rx skb fail\n"); 2407 2408 u64_stats_update_begin(&ring->syncp); 2409 ring->stats.sw_err_cnt++; 2410 u64_stats_update_end(&ring->syncp); 2411 2412 return -ENOMEM; 2413 } 2414 2415 prefetchw(skb->data); 2416 2417 ring->pending_buf = 1; 2418 ring->frag_num = 0; 2419 ring->tail_skb = NULL; 2420 if (length <= HNS3_RX_HEAD_SIZE) { 2421 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 2422 2423 /* We can reuse buffer as-is, just make sure it is local */ 2424 if (likely(page_to_nid(desc_cb->priv) == numa_node_id())) 2425 desc_cb->reuse_flag = 1; 2426 else /* This page cannot be reused so discard it */ 2427 put_page(desc_cb->priv); 2428 2429 ring_ptr_move_fw(ring, next_to_clean); 2430 return 0; 2431 } 2432 u64_stats_update_begin(&ring->syncp); 2433 ring->stats.seg_pkt_cnt++; 2434 u64_stats_update_end(&ring->syncp); 2435 2436 ring->pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE); 2437 __skb_put(skb, ring->pull_len); 2438 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 2439 desc_cb); 2440 ring_ptr_move_fw(ring, next_to_clean); 2441 2442 return HNS3_NEED_ADD_FRAG; 2443 } 2444 2445 static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc, 2446 struct sk_buff **out_skb, bool pending) 2447 { 2448 struct sk_buff *skb = *out_skb; 2449 struct sk_buff *head_skb = *out_skb; 2450 struct sk_buff *new_skb; 2451 struct hns3_desc_cb *desc_cb; 2452 struct hns3_desc *pre_desc; 2453 u32 bd_base_info; 2454 int pre_bd; 2455 2456 /* if there is pending bd, the SW param next_to_clean has moved 2457 * to next and the next is NULL 2458 */ 2459 if (pending) { 2460 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) % 2461 ring->desc_num; 2462 pre_desc = &ring->desc[pre_bd]; 2463 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info); 2464 } else { 2465 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2466 } 2467 2468 while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) { 2469 desc = &ring->desc[ring->next_to_clean]; 2470 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2471 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2472 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B)) 2473 return -ENXIO; 2474 2475 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 2476 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 2477 HNS3_RX_HEAD_SIZE); 2478 if (unlikely(!new_skb)) { 2479 netdev_err(ring->tqp->handle->kinfo.netdev, 2480 "alloc rx skb frag fail\n"); 2481 return -ENXIO; 2482 } 2483 ring->frag_num = 0; 2484 2485 if (ring->tail_skb) { 2486 ring->tail_skb->next = new_skb; 2487 ring->tail_skb = new_skb; 2488 } else { 2489 skb_shinfo(skb)->frag_list = new_skb; 2490 ring->tail_skb = new_skb; 2491 } 2492 } 2493 2494 if (ring->tail_skb) { 2495 head_skb->truesize += hnae3_buf_size(ring); 2496 head_skb->data_len += le16_to_cpu(desc->rx.size); 2497 head_skb->len += le16_to_cpu(desc->rx.size); 2498 skb = ring->tail_skb; 2499 } 2500 2501 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 2502 ring_ptr_move_fw(ring, next_to_clean); 2503 ring->pending_buf++; 2504 } 2505 2506 return 0; 2507 } 2508 2509 static void hns3_set_gro_param(struct sk_buff *skb, u32 l234info, 2510 u32 bd_base_info) 2511 { 2512 u16 gro_count; 2513 u32 l3_type; 2514 2515 gro_count = hnae3_get_field(l234info, HNS3_RXD_GRO_COUNT_M, 2516 HNS3_RXD_GRO_COUNT_S); 2517 /* if there is no HW GRO, do not set gro params */ 2518 if (!gro_count) 2519 return; 2520 2521 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count 2522 * to skb_shinfo(skb)->gso_segs 2523 */ 2524 NAPI_GRO_CB(skb)->count = gro_count; 2525 2526 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2527 HNS3_RXD_L3ID_S); 2528 if (l3_type == HNS3_L3_TYPE_IPV4) 2529 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 2530 else if (l3_type == HNS3_L3_TYPE_IPV6) 2531 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 2532 else 2533 return; 2534 2535 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 2536 HNS3_RXD_GRO_SIZE_M, 2537 HNS3_RXD_GRO_SIZE_S); 2538 if (skb_shinfo(skb)->gso_size) 2539 tcp_gro_complete(skb); 2540 } 2541 2542 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 2543 struct sk_buff *skb) 2544 { 2545 struct hnae3_handle *handle = ring->tqp->handle; 2546 enum pkt_hash_types rss_type; 2547 struct hns3_desc *desc; 2548 int last_bd; 2549 2550 /* When driver handle the rss type, ring->next_to_clean indicates the 2551 * first descriptor of next packet, need -1 here. 2552 */ 2553 last_bd = (ring->next_to_clean - 1 + ring->desc_num) % ring->desc_num; 2554 desc = &ring->desc[last_bd]; 2555 2556 if (le32_to_cpu(desc->rx.rss_hash)) 2557 rss_type = handle->kinfo.rss_type; 2558 else 2559 rss_type = PKT_HASH_TYPE_NONE; 2560 2561 skb_set_hash(skb, le32_to_cpu(desc->rx.rss_hash), rss_type); 2562 } 2563 2564 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring, 2565 struct sk_buff **out_skb) 2566 { 2567 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2568 enum hns3_pkt_l2t_type l2_frame_type; 2569 struct sk_buff *skb = ring->skb; 2570 struct hns3_desc_cb *desc_cb; 2571 struct hns3_desc *desc; 2572 u32 bd_base_info; 2573 u32 l234info; 2574 int length; 2575 int ret; 2576 2577 desc = &ring->desc[ring->next_to_clean]; 2578 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2579 2580 prefetch(desc); 2581 2582 length = le16_to_cpu(desc->rx.size); 2583 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2584 2585 /* Check valid BD */ 2586 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) 2587 return -ENXIO; 2588 2589 if (!skb) 2590 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset; 2591 2592 /* Prefetch first cache line of first page 2593 * Idea is to cache few bytes of the header of the packet. Our L1 Cache 2594 * line size is 64B so need to prefetch twice to make it 128B. But in 2595 * actual we can have greater size of caches with 128B Level 1 cache 2596 * lines. In such a case, single fetch would suffice to cache in the 2597 * relevant part of the header. 2598 */ 2599 prefetch(ring->va); 2600 #if L1_CACHE_BYTES < 128 2601 prefetch(ring->va + L1_CACHE_BYTES); 2602 #endif 2603 2604 if (!skb) { 2605 ret = hns3_alloc_skb(ring, length, ring->va); 2606 *out_skb = skb = ring->skb; 2607 2608 if (ret < 0) /* alloc buffer fail */ 2609 return ret; 2610 if (ret > 0) { /* need add frag */ 2611 ret = hns3_add_frag(ring, desc, &skb, false); 2612 if (ret) 2613 return ret; 2614 2615 /* As the head data may be changed when GRO enable, copy 2616 * the head data in after other data rx completed 2617 */ 2618 memcpy(skb->data, ring->va, 2619 ALIGN(ring->pull_len, sizeof(long))); 2620 } 2621 } else { 2622 ret = hns3_add_frag(ring, desc, &skb, true); 2623 if (ret) 2624 return ret; 2625 2626 /* As the head data may be changed when GRO enable, copy 2627 * the head data in after other data rx completed 2628 */ 2629 memcpy(skb->data, ring->va, 2630 ALIGN(ring->pull_len, sizeof(long))); 2631 } 2632 2633 l234info = le32_to_cpu(desc->rx.l234_info); 2634 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2635 2636 /* Based on hw strategy, the tag offloaded will be stored at 2637 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 2638 * in one layer tag case. 2639 */ 2640 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 2641 u16 vlan_tag; 2642 2643 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 2644 __vlan_hwaccel_put_tag(skb, 2645 htons(ETH_P_8021Q), 2646 vlan_tag); 2647 } 2648 2649 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) { 2650 u64_stats_update_begin(&ring->syncp); 2651 ring->stats.non_vld_descs++; 2652 u64_stats_update_end(&ring->syncp); 2653 2654 dev_kfree_skb_any(skb); 2655 return -EINVAL; 2656 } 2657 2658 if (unlikely((!desc->rx.pkt_len) || 2659 hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) { 2660 u64_stats_update_begin(&ring->syncp); 2661 ring->stats.err_pkt_len++; 2662 u64_stats_update_end(&ring->syncp); 2663 2664 dev_kfree_skb_any(skb); 2665 return -EFAULT; 2666 } 2667 2668 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) { 2669 u64_stats_update_begin(&ring->syncp); 2670 ring->stats.l2_err++; 2671 u64_stats_update_end(&ring->syncp); 2672 2673 dev_kfree_skb_any(skb); 2674 return -EFAULT; 2675 } 2676 2677 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 2678 HNS3_RXD_DMAC_S); 2679 u64_stats_update_begin(&ring->syncp); 2680 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 2681 ring->stats.rx_multicast++; 2682 2683 ring->stats.rx_pkts++; 2684 ring->stats.rx_bytes += skb->len; 2685 u64_stats_update_end(&ring->syncp); 2686 2687 ring->tqp_vector->rx_group.total_bytes += skb->len; 2688 2689 /* This is needed in order to enable forwarding support */ 2690 hns3_set_gro_param(skb, l234info, bd_base_info); 2691 2692 hns3_rx_checksum(ring, skb, desc); 2693 *out_skb = skb; 2694 hns3_set_rx_skb_rss_type(ring, skb); 2695 2696 return 0; 2697 } 2698 2699 int hns3_clean_rx_ring( 2700 struct hns3_enet_ring *ring, int budget, 2701 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 2702 { 2703 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 2704 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2705 int recv_pkts, recv_bds, clean_count, err; 2706 int unused_count = hns3_desc_unused(ring) - ring->pending_buf; 2707 struct sk_buff *skb = ring->skb; 2708 int num; 2709 2710 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG); 2711 rmb(); /* Make sure num taken effect before the other data is touched */ 2712 2713 recv_pkts = 0, recv_bds = 0, clean_count = 0; 2714 num -= unused_count; 2715 2716 while (recv_pkts < budget && recv_bds < num) { 2717 /* Reuse or realloc buffers */ 2718 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 2719 hns3_nic_alloc_rx_buffers(ring, 2720 clean_count + unused_count); 2721 clean_count = 0; 2722 unused_count = hns3_desc_unused(ring) - 2723 ring->pending_buf; 2724 } 2725 2726 /* Poll one pkt */ 2727 err = hns3_handle_rx_bd(ring, &skb); 2728 if (unlikely(!skb)) /* This fault cannot be repaired */ 2729 goto out; 2730 2731 if (err == -ENXIO) { /* Do not get FE for the packet */ 2732 goto out; 2733 } else if (unlikely(err)) { /* Do jump the err */ 2734 recv_bds += ring->pending_buf; 2735 clean_count += ring->pending_buf; 2736 ring->skb = NULL; 2737 ring->pending_buf = 0; 2738 continue; 2739 } 2740 2741 /* Do update ip stack process */ 2742 skb->protocol = eth_type_trans(skb, netdev); 2743 rx_fn(ring, skb); 2744 recv_bds += ring->pending_buf; 2745 clean_count += ring->pending_buf; 2746 ring->skb = NULL; 2747 ring->pending_buf = 0; 2748 2749 recv_pkts++; 2750 } 2751 2752 out: 2753 /* Make all data has been write before submit */ 2754 if (clean_count + unused_count > 0) 2755 hns3_nic_alloc_rx_buffers(ring, 2756 clean_count + unused_count); 2757 2758 return recv_pkts; 2759 } 2760 2761 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 2762 { 2763 struct hns3_enet_tqp_vector *tqp_vector = 2764 ring_group->ring->tqp_vector; 2765 enum hns3_flow_level_range new_flow_level; 2766 int packets_per_msecs; 2767 int bytes_per_msecs; 2768 u32 time_passed_ms; 2769 u16 new_int_gl; 2770 2771 if (!tqp_vector->last_jiffies) 2772 return false; 2773 2774 if (ring_group->total_packets == 0) { 2775 ring_group->coal.int_gl = HNS3_INT_GL_50K; 2776 ring_group->coal.flow_level = HNS3_FLOW_LOW; 2777 return true; 2778 } 2779 2780 /* Simple throttlerate management 2781 * 0-10MB/s lower (50000 ints/s) 2782 * 10-20MB/s middle (20000 ints/s) 2783 * 20-1249MB/s high (18000 ints/s) 2784 * > 40000pps ultra (8000 ints/s) 2785 */ 2786 new_flow_level = ring_group->coal.flow_level; 2787 new_int_gl = ring_group->coal.int_gl; 2788 time_passed_ms = 2789 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 2790 2791 if (!time_passed_ms) 2792 return false; 2793 2794 do_div(ring_group->total_packets, time_passed_ms); 2795 packets_per_msecs = ring_group->total_packets; 2796 2797 do_div(ring_group->total_bytes, time_passed_ms); 2798 bytes_per_msecs = ring_group->total_bytes; 2799 2800 #define HNS3_RX_LOW_BYTE_RATE 10000 2801 #define HNS3_RX_MID_BYTE_RATE 20000 2802 2803 switch (new_flow_level) { 2804 case HNS3_FLOW_LOW: 2805 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 2806 new_flow_level = HNS3_FLOW_MID; 2807 break; 2808 case HNS3_FLOW_MID: 2809 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 2810 new_flow_level = HNS3_FLOW_HIGH; 2811 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 2812 new_flow_level = HNS3_FLOW_LOW; 2813 break; 2814 case HNS3_FLOW_HIGH: 2815 case HNS3_FLOW_ULTRA: 2816 default: 2817 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 2818 new_flow_level = HNS3_FLOW_MID; 2819 break; 2820 } 2821 2822 #define HNS3_RX_ULTRA_PACKET_RATE 40 2823 2824 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 2825 &tqp_vector->rx_group == ring_group) 2826 new_flow_level = HNS3_FLOW_ULTRA; 2827 2828 switch (new_flow_level) { 2829 case HNS3_FLOW_LOW: 2830 new_int_gl = HNS3_INT_GL_50K; 2831 break; 2832 case HNS3_FLOW_MID: 2833 new_int_gl = HNS3_INT_GL_20K; 2834 break; 2835 case HNS3_FLOW_HIGH: 2836 new_int_gl = HNS3_INT_GL_18K; 2837 break; 2838 case HNS3_FLOW_ULTRA: 2839 new_int_gl = HNS3_INT_GL_8K; 2840 break; 2841 default: 2842 break; 2843 } 2844 2845 ring_group->total_bytes = 0; 2846 ring_group->total_packets = 0; 2847 ring_group->coal.flow_level = new_flow_level; 2848 if (new_int_gl != ring_group->coal.int_gl) { 2849 ring_group->coal.int_gl = new_int_gl; 2850 return true; 2851 } 2852 return false; 2853 } 2854 2855 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 2856 { 2857 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 2858 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 2859 bool rx_update, tx_update; 2860 2861 /* update param every 1000ms */ 2862 if (time_before(jiffies, 2863 tqp_vector->last_jiffies + msecs_to_jiffies(1000))) 2864 return; 2865 2866 if (rx_group->coal.gl_adapt_enable) { 2867 rx_update = hns3_get_new_int_gl(rx_group); 2868 if (rx_update) 2869 hns3_set_vector_coalesce_rx_gl(tqp_vector, 2870 rx_group->coal.int_gl); 2871 } 2872 2873 if (tx_group->coal.gl_adapt_enable) { 2874 tx_update = hns3_get_new_int_gl(tx_group); 2875 if (tx_update) 2876 hns3_set_vector_coalesce_tx_gl(tqp_vector, 2877 tx_group->coal.int_gl); 2878 } 2879 2880 tqp_vector->last_jiffies = jiffies; 2881 } 2882 2883 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 2884 { 2885 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 2886 struct hns3_enet_ring *ring; 2887 int rx_pkt_total = 0; 2888 2889 struct hns3_enet_tqp_vector *tqp_vector = 2890 container_of(napi, struct hns3_enet_tqp_vector, napi); 2891 bool clean_complete = true; 2892 int rx_budget; 2893 2894 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 2895 napi_complete(napi); 2896 return 0; 2897 } 2898 2899 /* Since the actual Tx work is minimal, we can give the Tx a larger 2900 * budget and be more aggressive about cleaning up the Tx descriptors. 2901 */ 2902 hns3_for_each_ring(ring, tqp_vector->tx_group) 2903 hns3_clean_tx_ring(ring); 2904 2905 /* make sure rx ring budget not smaller than 1 */ 2906 rx_budget = max(budget / tqp_vector->num_tqps, 1); 2907 2908 hns3_for_each_ring(ring, tqp_vector->rx_group) { 2909 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 2910 hns3_rx_skb); 2911 2912 if (rx_cleaned >= rx_budget) 2913 clean_complete = false; 2914 2915 rx_pkt_total += rx_cleaned; 2916 } 2917 2918 tqp_vector->rx_group.total_packets += rx_pkt_total; 2919 2920 if (!clean_complete) 2921 return budget; 2922 2923 if (napi_complete(napi) && 2924 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 2925 hns3_update_new_int_gl(tqp_vector); 2926 hns3_mask_vector_irq(tqp_vector, 1); 2927 } 2928 2929 return rx_pkt_total; 2930 } 2931 2932 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 2933 struct hnae3_ring_chain_node *head) 2934 { 2935 struct pci_dev *pdev = tqp_vector->handle->pdev; 2936 struct hnae3_ring_chain_node *cur_chain = head; 2937 struct hnae3_ring_chain_node *chain; 2938 struct hns3_enet_ring *tx_ring; 2939 struct hns3_enet_ring *rx_ring; 2940 2941 tx_ring = tqp_vector->tx_group.ring; 2942 if (tx_ring) { 2943 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 2944 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 2945 HNAE3_RING_TYPE_TX); 2946 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2947 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 2948 2949 cur_chain->next = NULL; 2950 2951 while (tx_ring->next) { 2952 tx_ring = tx_ring->next; 2953 2954 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 2955 GFP_KERNEL); 2956 if (!chain) 2957 goto err_free_chain; 2958 2959 cur_chain->next = chain; 2960 chain->tqp_index = tx_ring->tqp->tqp_index; 2961 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 2962 HNAE3_RING_TYPE_TX); 2963 hnae3_set_field(chain->int_gl_idx, 2964 HNAE3_RING_GL_IDX_M, 2965 HNAE3_RING_GL_IDX_S, 2966 HNAE3_RING_GL_TX); 2967 2968 cur_chain = chain; 2969 } 2970 } 2971 2972 rx_ring = tqp_vector->rx_group.ring; 2973 if (!tx_ring && rx_ring) { 2974 cur_chain->next = NULL; 2975 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 2976 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 2977 HNAE3_RING_TYPE_RX); 2978 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2979 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 2980 2981 rx_ring = rx_ring->next; 2982 } 2983 2984 while (rx_ring) { 2985 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 2986 if (!chain) 2987 goto err_free_chain; 2988 2989 cur_chain->next = chain; 2990 chain->tqp_index = rx_ring->tqp->tqp_index; 2991 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 2992 HNAE3_RING_TYPE_RX); 2993 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2994 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 2995 2996 cur_chain = chain; 2997 2998 rx_ring = rx_ring->next; 2999 } 3000 3001 return 0; 3002 3003 err_free_chain: 3004 cur_chain = head->next; 3005 while (cur_chain) { 3006 chain = cur_chain->next; 3007 devm_kfree(&pdev->dev, cur_chain); 3008 cur_chain = chain; 3009 } 3010 head->next = NULL; 3011 3012 return -ENOMEM; 3013 } 3014 3015 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3016 struct hnae3_ring_chain_node *head) 3017 { 3018 struct pci_dev *pdev = tqp_vector->handle->pdev; 3019 struct hnae3_ring_chain_node *chain_tmp, *chain; 3020 3021 chain = head->next; 3022 3023 while (chain) { 3024 chain_tmp = chain->next; 3025 devm_kfree(&pdev->dev, chain); 3026 chain = chain_tmp; 3027 } 3028 } 3029 3030 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 3031 struct hns3_enet_ring *ring) 3032 { 3033 ring->next = group->ring; 3034 group->ring = ring; 3035 3036 group->count++; 3037 } 3038 3039 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 3040 { 3041 struct pci_dev *pdev = priv->ae_handle->pdev; 3042 struct hns3_enet_tqp_vector *tqp_vector; 3043 int num_vectors = priv->vector_num; 3044 int numa_node; 3045 int vector_i; 3046 3047 numa_node = dev_to_node(&pdev->dev); 3048 3049 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 3050 tqp_vector = &priv->tqp_vector[vector_i]; 3051 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 3052 &tqp_vector->affinity_mask); 3053 } 3054 } 3055 3056 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 3057 { 3058 struct hnae3_ring_chain_node vector_ring_chain; 3059 struct hnae3_handle *h = priv->ae_handle; 3060 struct hns3_enet_tqp_vector *tqp_vector; 3061 int ret = 0; 3062 int i; 3063 3064 hns3_nic_set_cpumask(priv); 3065 3066 for (i = 0; i < priv->vector_num; i++) { 3067 tqp_vector = &priv->tqp_vector[i]; 3068 hns3_vector_gl_rl_init_hw(tqp_vector, priv); 3069 tqp_vector->num_tqps = 0; 3070 } 3071 3072 for (i = 0; i < h->kinfo.num_tqps; i++) { 3073 u16 vector_i = i % priv->vector_num; 3074 u16 tqp_num = h->kinfo.num_tqps; 3075 3076 tqp_vector = &priv->tqp_vector[vector_i]; 3077 3078 hns3_add_ring_to_group(&tqp_vector->tx_group, 3079 priv->ring_data[i].ring); 3080 3081 hns3_add_ring_to_group(&tqp_vector->rx_group, 3082 priv->ring_data[i + tqp_num].ring); 3083 3084 priv->ring_data[i].ring->tqp_vector = tqp_vector; 3085 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector; 3086 tqp_vector->num_tqps++; 3087 } 3088 3089 for (i = 0; i < priv->vector_num; i++) { 3090 tqp_vector = &priv->tqp_vector[i]; 3091 3092 tqp_vector->rx_group.total_bytes = 0; 3093 tqp_vector->rx_group.total_packets = 0; 3094 tqp_vector->tx_group.total_bytes = 0; 3095 tqp_vector->tx_group.total_packets = 0; 3096 tqp_vector->handle = h; 3097 3098 ret = hns3_get_vector_ring_chain(tqp_vector, 3099 &vector_ring_chain); 3100 if (ret) 3101 goto map_ring_fail; 3102 3103 ret = h->ae_algo->ops->map_ring_to_vector(h, 3104 tqp_vector->vector_irq, &vector_ring_chain); 3105 3106 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3107 3108 if (ret) 3109 goto map_ring_fail; 3110 3111 netif_napi_add(priv->netdev, &tqp_vector->napi, 3112 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 3113 } 3114 3115 return 0; 3116 3117 map_ring_fail: 3118 while (i--) 3119 netif_napi_del(&priv->tqp_vector[i].napi); 3120 3121 return ret; 3122 } 3123 3124 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 3125 { 3126 #define HNS3_VECTOR_PF_MAX_NUM 64 3127 3128 struct hnae3_handle *h = priv->ae_handle; 3129 struct hns3_enet_tqp_vector *tqp_vector; 3130 struct hnae3_vector_info *vector; 3131 struct pci_dev *pdev = h->pdev; 3132 u16 tqp_num = h->kinfo.num_tqps; 3133 u16 vector_num; 3134 int ret = 0; 3135 u16 i; 3136 3137 /* RSS size, cpu online and vector_num should be the same */ 3138 /* Should consider 2p/4p later */ 3139 vector_num = min_t(u16, num_online_cpus(), tqp_num); 3140 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM); 3141 3142 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 3143 GFP_KERNEL); 3144 if (!vector) 3145 return -ENOMEM; 3146 3147 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 3148 3149 priv->vector_num = vector_num; 3150 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 3151 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 3152 GFP_KERNEL); 3153 if (!priv->tqp_vector) { 3154 ret = -ENOMEM; 3155 goto out; 3156 } 3157 3158 for (i = 0; i < priv->vector_num; i++) { 3159 tqp_vector = &priv->tqp_vector[i]; 3160 tqp_vector->idx = i; 3161 tqp_vector->mask_addr = vector[i].io_addr; 3162 tqp_vector->vector_irq = vector[i].vector; 3163 hns3_vector_gl_rl_init(tqp_vector, priv); 3164 } 3165 3166 out: 3167 devm_kfree(&pdev->dev, vector); 3168 return ret; 3169 } 3170 3171 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 3172 { 3173 group->ring = NULL; 3174 group->count = 0; 3175 } 3176 3177 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 3178 { 3179 struct hnae3_ring_chain_node vector_ring_chain; 3180 struct hnae3_handle *h = priv->ae_handle; 3181 struct hns3_enet_tqp_vector *tqp_vector; 3182 int i; 3183 3184 for (i = 0; i < priv->vector_num; i++) { 3185 tqp_vector = &priv->tqp_vector[i]; 3186 3187 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 3188 continue; 3189 3190 hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain); 3191 3192 h->ae_algo->ops->unmap_ring_from_vector(h, 3193 tqp_vector->vector_irq, &vector_ring_chain); 3194 3195 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3196 3197 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) { 3198 irq_set_affinity_notifier(tqp_vector->vector_irq, 3199 NULL); 3200 irq_set_affinity_hint(tqp_vector->vector_irq, NULL); 3201 free_irq(tqp_vector->vector_irq, tqp_vector); 3202 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED; 3203 } 3204 3205 hns3_clear_ring_group(&tqp_vector->rx_group); 3206 hns3_clear_ring_group(&tqp_vector->tx_group); 3207 netif_napi_del(&priv->tqp_vector[i].napi); 3208 } 3209 } 3210 3211 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 3212 { 3213 struct hnae3_handle *h = priv->ae_handle; 3214 struct pci_dev *pdev = h->pdev; 3215 int i, ret; 3216 3217 for (i = 0; i < priv->vector_num; i++) { 3218 struct hns3_enet_tqp_vector *tqp_vector; 3219 3220 tqp_vector = &priv->tqp_vector[i]; 3221 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 3222 if (ret) 3223 return ret; 3224 } 3225 3226 devm_kfree(&pdev->dev, priv->tqp_vector); 3227 return 0; 3228 } 3229 3230 static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 3231 int ring_type) 3232 { 3233 struct hns3_nic_ring_data *ring_data = priv->ring_data; 3234 int queue_num = priv->ae_handle->kinfo.num_tqps; 3235 int desc_num = priv->ae_handle->kinfo.num_desc; 3236 struct pci_dev *pdev = priv->ae_handle->pdev; 3237 struct hns3_enet_ring *ring; 3238 3239 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL); 3240 if (!ring) 3241 return -ENOMEM; 3242 3243 if (ring_type == HNAE3_RING_TYPE_TX) { 3244 ring_data[q->tqp_index].ring = ring; 3245 ring_data[q->tqp_index].queue_index = q->tqp_index; 3246 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET; 3247 } else { 3248 ring_data[q->tqp_index + queue_num].ring = ring; 3249 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index; 3250 ring->io_base = q->io_base; 3251 } 3252 3253 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 3254 3255 ring->tqp = q; 3256 ring->desc = NULL; 3257 ring->desc_cb = NULL; 3258 ring->dev = priv->dev; 3259 ring->desc_dma_addr = 0; 3260 ring->buf_size = q->buf_size; 3261 ring->desc_num = desc_num; 3262 ring->next_to_use = 0; 3263 ring->next_to_clean = 0; 3264 3265 return 0; 3266 } 3267 3268 static int hns3_queue_to_ring(struct hnae3_queue *tqp, 3269 struct hns3_nic_priv *priv) 3270 { 3271 int ret; 3272 3273 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 3274 if (ret) 3275 return ret; 3276 3277 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 3278 if (ret) { 3279 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring); 3280 return ret; 3281 } 3282 3283 return 0; 3284 } 3285 3286 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 3287 { 3288 struct hnae3_handle *h = priv->ae_handle; 3289 struct pci_dev *pdev = h->pdev; 3290 int i, ret; 3291 3292 priv->ring_data = devm_kzalloc(&pdev->dev, 3293 array3_size(h->kinfo.num_tqps, 3294 sizeof(*priv->ring_data), 3295 2), 3296 GFP_KERNEL); 3297 if (!priv->ring_data) 3298 return -ENOMEM; 3299 3300 for (i = 0; i < h->kinfo.num_tqps; i++) { 3301 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv); 3302 if (ret) 3303 goto err; 3304 } 3305 3306 return 0; 3307 err: 3308 while (i--) { 3309 devm_kfree(priv->dev, priv->ring_data[i].ring); 3310 devm_kfree(priv->dev, 3311 priv->ring_data[i + h->kinfo.num_tqps].ring); 3312 } 3313 3314 devm_kfree(&pdev->dev, priv->ring_data); 3315 return ret; 3316 } 3317 3318 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 3319 { 3320 struct hnae3_handle *h = priv->ae_handle; 3321 int i; 3322 3323 for (i = 0; i < h->kinfo.num_tqps; i++) { 3324 devm_kfree(priv->dev, priv->ring_data[i].ring); 3325 devm_kfree(priv->dev, 3326 priv->ring_data[i + h->kinfo.num_tqps].ring); 3327 } 3328 devm_kfree(priv->dev, priv->ring_data); 3329 } 3330 3331 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 3332 { 3333 int ret; 3334 3335 if (ring->desc_num <= 0 || ring->buf_size <= 0) 3336 return -EINVAL; 3337 3338 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]), 3339 GFP_KERNEL); 3340 if (!ring->desc_cb) { 3341 ret = -ENOMEM; 3342 goto out; 3343 } 3344 3345 ret = hns3_alloc_desc(ring); 3346 if (ret) 3347 goto out_with_desc_cb; 3348 3349 if (!HNAE3_IS_TX_RING(ring)) { 3350 ret = hns3_alloc_ring_buffers(ring); 3351 if (ret) 3352 goto out_with_desc; 3353 } 3354 3355 return 0; 3356 3357 out_with_desc: 3358 hns3_free_desc(ring); 3359 out_with_desc_cb: 3360 kfree(ring->desc_cb); 3361 ring->desc_cb = NULL; 3362 out: 3363 return ret; 3364 } 3365 3366 static void hns3_fini_ring(struct hns3_enet_ring *ring) 3367 { 3368 hns3_free_desc(ring); 3369 kfree(ring->desc_cb); 3370 ring->desc_cb = NULL; 3371 ring->next_to_clean = 0; 3372 ring->next_to_use = 0; 3373 ring->pending_buf = 0; 3374 if (ring->skb) { 3375 dev_kfree_skb_any(ring->skb); 3376 ring->skb = NULL; 3377 } 3378 } 3379 3380 static int hns3_buf_size2type(u32 buf_size) 3381 { 3382 int bd_size_type; 3383 3384 switch (buf_size) { 3385 case 512: 3386 bd_size_type = HNS3_BD_SIZE_512_TYPE; 3387 break; 3388 case 1024: 3389 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 3390 break; 3391 case 2048: 3392 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3393 break; 3394 case 4096: 3395 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 3396 break; 3397 default: 3398 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3399 } 3400 3401 return bd_size_type; 3402 } 3403 3404 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 3405 { 3406 dma_addr_t dma = ring->desc_dma_addr; 3407 struct hnae3_queue *q = ring->tqp; 3408 3409 if (!HNAE3_IS_TX_RING(ring)) { 3410 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, 3411 (u32)dma); 3412 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 3413 (u32)((dma >> 31) >> 1)); 3414 3415 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 3416 hns3_buf_size2type(ring->buf_size)); 3417 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 3418 ring->desc_num / 8 - 1); 3419 3420 } else { 3421 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 3422 (u32)dma); 3423 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 3424 (u32)((dma >> 31) >> 1)); 3425 3426 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 3427 ring->desc_num / 8 - 1); 3428 } 3429 } 3430 3431 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 3432 { 3433 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3434 int i; 3435 3436 for (i = 0; i < HNAE3_MAX_TC; i++) { 3437 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i]; 3438 int j; 3439 3440 if (!tc_info->enable) 3441 continue; 3442 3443 for (j = 0; j < tc_info->tqp_count; j++) { 3444 struct hnae3_queue *q; 3445 3446 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp; 3447 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, 3448 tc_info->tc); 3449 } 3450 } 3451 } 3452 3453 int hns3_init_all_ring(struct hns3_nic_priv *priv) 3454 { 3455 struct hnae3_handle *h = priv->ae_handle; 3456 int ring_num = h->kinfo.num_tqps * 2; 3457 int i, j; 3458 int ret; 3459 3460 for (i = 0; i < ring_num; i++) { 3461 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring); 3462 if (ret) { 3463 dev_err(priv->dev, 3464 "Alloc ring memory fail! ret=%d\n", ret); 3465 goto out_when_alloc_ring_memory; 3466 } 3467 3468 u64_stats_init(&priv->ring_data[i].ring->syncp); 3469 } 3470 3471 return 0; 3472 3473 out_when_alloc_ring_memory: 3474 for (j = i - 1; j >= 0; j--) 3475 hns3_fini_ring(priv->ring_data[j].ring); 3476 3477 return -ENOMEM; 3478 } 3479 3480 int hns3_uninit_all_ring(struct hns3_nic_priv *priv) 3481 { 3482 struct hnae3_handle *h = priv->ae_handle; 3483 int i; 3484 3485 for (i = 0; i < h->kinfo.num_tqps; i++) { 3486 hns3_fini_ring(priv->ring_data[i].ring); 3487 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring); 3488 } 3489 return 0; 3490 } 3491 3492 /* Set mac addr if it is configured. or leave it to the AE driver */ 3493 static int hns3_init_mac_addr(struct net_device *netdev, bool init) 3494 { 3495 struct hns3_nic_priv *priv = netdev_priv(netdev); 3496 struct hnae3_handle *h = priv->ae_handle; 3497 u8 mac_addr_temp[ETH_ALEN]; 3498 int ret = 0; 3499 3500 if (h->ae_algo->ops->get_mac_addr && init) { 3501 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 3502 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 3503 } 3504 3505 /* Check if the MAC address is valid, if not get a random one */ 3506 if (!is_valid_ether_addr(netdev->dev_addr)) { 3507 eth_hw_addr_random(netdev); 3508 dev_warn(priv->dev, "using random MAC address %pM\n", 3509 netdev->dev_addr); 3510 } 3511 3512 if (h->ae_algo->ops->set_mac_addr) 3513 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 3514 3515 return ret; 3516 } 3517 3518 static int hns3_init_phy(struct net_device *netdev) 3519 { 3520 struct hnae3_handle *h = hns3_get_handle(netdev); 3521 int ret = 0; 3522 3523 if (h->ae_algo->ops->mac_connect_phy) 3524 ret = h->ae_algo->ops->mac_connect_phy(h); 3525 3526 return ret; 3527 } 3528 3529 static void hns3_uninit_phy(struct net_device *netdev) 3530 { 3531 struct hnae3_handle *h = hns3_get_handle(netdev); 3532 3533 if (h->ae_algo->ops->mac_disconnect_phy) 3534 h->ae_algo->ops->mac_disconnect_phy(h); 3535 } 3536 3537 static int hns3_restore_fd_rules(struct net_device *netdev) 3538 { 3539 struct hnae3_handle *h = hns3_get_handle(netdev); 3540 int ret = 0; 3541 3542 if (h->ae_algo->ops->restore_fd_rules) 3543 ret = h->ae_algo->ops->restore_fd_rules(h); 3544 3545 return ret; 3546 } 3547 3548 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list) 3549 { 3550 struct hnae3_handle *h = hns3_get_handle(netdev); 3551 3552 if (h->ae_algo->ops->del_all_fd_entries) 3553 h->ae_algo->ops->del_all_fd_entries(h, clear_list); 3554 } 3555 3556 static void hns3_nic_set_priv_ops(struct net_device *netdev) 3557 { 3558 struct hns3_nic_priv *priv = netdev_priv(netdev); 3559 3560 priv->ops.fill_desc = hns3_fill_desc; 3561 if ((netdev->features & NETIF_F_TSO) || 3562 (netdev->features & NETIF_F_TSO6)) 3563 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 3564 else 3565 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 3566 } 3567 3568 static int hns3_client_start(struct hnae3_handle *handle) 3569 { 3570 if (!handle->ae_algo->ops->client_start) 3571 return 0; 3572 3573 return handle->ae_algo->ops->client_start(handle); 3574 } 3575 3576 static void hns3_client_stop(struct hnae3_handle *handle) 3577 { 3578 if (!handle->ae_algo->ops->client_stop) 3579 return; 3580 3581 handle->ae_algo->ops->client_stop(handle); 3582 } 3583 3584 static int hns3_client_init(struct hnae3_handle *handle) 3585 { 3586 struct pci_dev *pdev = handle->pdev; 3587 u16 alloc_tqps, max_rss_size; 3588 struct hns3_nic_priv *priv; 3589 struct net_device *netdev; 3590 int ret; 3591 3592 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 3593 &max_rss_size); 3594 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 3595 if (!netdev) 3596 return -ENOMEM; 3597 3598 priv = netdev_priv(netdev); 3599 priv->dev = &pdev->dev; 3600 priv->netdev = netdev; 3601 priv->ae_handle = handle; 3602 priv->tx_timeout_count = 0; 3603 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 3604 3605 handle->kinfo.netdev = netdev; 3606 handle->priv = (void *)priv; 3607 3608 hns3_init_mac_addr(netdev, true); 3609 3610 hns3_set_default_feature(netdev); 3611 3612 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 3613 netdev->priv_flags |= IFF_UNICAST_FLT; 3614 netdev->netdev_ops = &hns3_nic_netdev_ops; 3615 SET_NETDEV_DEV(netdev, &pdev->dev); 3616 hns3_ethtool_set_ops(netdev); 3617 hns3_nic_set_priv_ops(netdev); 3618 3619 /* Carrier off reporting is important to ethtool even BEFORE open */ 3620 netif_carrier_off(netdev); 3621 3622 ret = hns3_get_ring_config(priv); 3623 if (ret) { 3624 ret = -ENOMEM; 3625 goto out_get_ring_cfg; 3626 } 3627 3628 ret = hns3_nic_alloc_vector_data(priv); 3629 if (ret) { 3630 ret = -ENOMEM; 3631 goto out_alloc_vector_data; 3632 } 3633 3634 ret = hns3_nic_init_vector_data(priv); 3635 if (ret) { 3636 ret = -ENOMEM; 3637 goto out_init_vector_data; 3638 } 3639 3640 ret = hns3_init_all_ring(priv); 3641 if (ret) { 3642 ret = -ENOMEM; 3643 goto out_init_ring_data; 3644 } 3645 3646 ret = hns3_init_phy(netdev); 3647 if (ret) 3648 goto out_init_phy; 3649 3650 ret = register_netdev(netdev); 3651 if (ret) { 3652 dev_err(priv->dev, "probe register netdev fail!\n"); 3653 goto out_reg_netdev_fail; 3654 } 3655 3656 ret = hns3_client_start(handle); 3657 if (ret) { 3658 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 3659 goto out_reg_netdev_fail; 3660 } 3661 3662 hns3_dcbnl_setup(handle); 3663 3664 hns3_dbg_init(handle); 3665 3666 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */ 3667 netdev->max_mtu = HNS3_MAX_MTU; 3668 3669 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 3670 3671 return ret; 3672 3673 out_reg_netdev_fail: 3674 hns3_uninit_phy(netdev); 3675 out_init_phy: 3676 hns3_uninit_all_ring(priv); 3677 out_init_ring_data: 3678 hns3_nic_uninit_vector_data(priv); 3679 out_init_vector_data: 3680 hns3_nic_dealloc_vector_data(priv); 3681 out_alloc_vector_data: 3682 priv->ring_data = NULL; 3683 out_get_ring_cfg: 3684 priv->ae_handle = NULL; 3685 free_netdev(netdev); 3686 return ret; 3687 } 3688 3689 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 3690 { 3691 struct net_device *netdev = handle->kinfo.netdev; 3692 struct hns3_nic_priv *priv = netdev_priv(netdev); 3693 int ret; 3694 3695 hns3_client_stop(handle); 3696 3697 hns3_remove_hw_addr(netdev); 3698 3699 if (netdev->reg_state != NETREG_UNINITIALIZED) 3700 unregister_netdev(netdev); 3701 3702 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 3703 netdev_warn(netdev, "already uninitialized\n"); 3704 goto out_netdev_free; 3705 } 3706 3707 hns3_del_all_fd_rules(netdev, true); 3708 3709 hns3_force_clear_all_rx_ring(handle); 3710 3711 hns3_uninit_phy(netdev); 3712 3713 hns3_nic_uninit_vector_data(priv); 3714 3715 ret = hns3_nic_dealloc_vector_data(priv); 3716 if (ret) 3717 netdev_err(netdev, "dealloc vector error\n"); 3718 3719 ret = hns3_uninit_all_ring(priv); 3720 if (ret) 3721 netdev_err(netdev, "uninit ring error\n"); 3722 3723 hns3_put_ring_config(priv); 3724 3725 hns3_dbg_uninit(handle); 3726 3727 priv->ring_data = NULL; 3728 3729 out_netdev_free: 3730 free_netdev(netdev); 3731 } 3732 3733 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 3734 { 3735 struct net_device *netdev = handle->kinfo.netdev; 3736 3737 if (!netdev) 3738 return; 3739 3740 if (linkup) { 3741 netif_carrier_on(netdev); 3742 netif_tx_wake_all_queues(netdev); 3743 netdev_info(netdev, "link up\n"); 3744 } else { 3745 netif_carrier_off(netdev); 3746 netif_tx_stop_all_queues(netdev); 3747 netdev_info(netdev, "link down\n"); 3748 } 3749 } 3750 3751 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc) 3752 { 3753 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3754 struct net_device *ndev = kinfo->netdev; 3755 3756 if (tc > HNAE3_MAX_TC) 3757 return -EINVAL; 3758 3759 if (!ndev) 3760 return -ENODEV; 3761 3762 return hns3_nic_set_real_num_queue(ndev); 3763 } 3764 3765 static int hns3_recover_hw_addr(struct net_device *ndev) 3766 { 3767 struct netdev_hw_addr_list *list; 3768 struct netdev_hw_addr *ha, *tmp; 3769 int ret = 0; 3770 3771 /* go through and sync uc_addr entries to the device */ 3772 list = &ndev->uc; 3773 list_for_each_entry_safe(ha, tmp, &list->list, list) { 3774 ret = hns3_nic_uc_sync(ndev, ha->addr); 3775 if (ret) 3776 return ret; 3777 } 3778 3779 /* go through and sync mc_addr entries to the device */ 3780 list = &ndev->mc; 3781 list_for_each_entry_safe(ha, tmp, &list->list, list) { 3782 ret = hns3_nic_mc_sync(ndev, ha->addr); 3783 if (ret) 3784 return ret; 3785 } 3786 3787 return ret; 3788 } 3789 3790 static void hns3_remove_hw_addr(struct net_device *netdev) 3791 { 3792 struct netdev_hw_addr_list *list; 3793 struct netdev_hw_addr *ha, *tmp; 3794 3795 hns3_nic_uc_unsync(netdev, netdev->dev_addr); 3796 3797 /* go through and unsync uc_addr entries to the device */ 3798 list = &netdev->uc; 3799 list_for_each_entry_safe(ha, tmp, &list->list, list) 3800 hns3_nic_uc_unsync(netdev, ha->addr); 3801 3802 /* go through and unsync mc_addr entries to the device */ 3803 list = &netdev->mc; 3804 list_for_each_entry_safe(ha, tmp, &list->list, list) 3805 if (ha->refcount > 1) 3806 hns3_nic_mc_unsync(netdev, ha->addr); 3807 } 3808 3809 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 3810 { 3811 while (ring->next_to_clean != ring->next_to_use) { 3812 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 3813 hns3_free_buffer_detach(ring, ring->next_to_clean); 3814 ring_ptr_move_fw(ring, next_to_clean); 3815 } 3816 } 3817 3818 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 3819 { 3820 struct hns3_desc_cb res_cbs; 3821 int ret; 3822 3823 while (ring->next_to_use != ring->next_to_clean) { 3824 /* When a buffer is not reused, it's memory has been 3825 * freed in hns3_handle_rx_bd or will be freed by 3826 * stack, so we need to replace the buffer here. 3827 */ 3828 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3829 ret = hns3_reserve_buffer_map(ring, &res_cbs); 3830 if (ret) { 3831 u64_stats_update_begin(&ring->syncp); 3832 ring->stats.sw_err_cnt++; 3833 u64_stats_update_end(&ring->syncp); 3834 /* if alloc new buffer fail, exit directly 3835 * and reclear in up flow. 3836 */ 3837 netdev_warn(ring->tqp->handle->kinfo.netdev, 3838 "reserve buffer map failed, ret = %d\n", 3839 ret); 3840 return ret; 3841 } 3842 hns3_replace_buffer(ring, ring->next_to_use, 3843 &res_cbs); 3844 } 3845 ring_ptr_move_fw(ring, next_to_use); 3846 } 3847 3848 return 0; 3849 } 3850 3851 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 3852 { 3853 while (ring->next_to_use != ring->next_to_clean) { 3854 /* When a buffer is not reused, it's memory has been 3855 * freed in hns3_handle_rx_bd or will be freed by 3856 * stack, so only need to unmap the buffer here. 3857 */ 3858 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3859 hns3_unmap_buffer(ring, 3860 &ring->desc_cb[ring->next_to_use]); 3861 ring->desc_cb[ring->next_to_use].dma = 0; 3862 } 3863 3864 ring_ptr_move_fw(ring, next_to_use); 3865 } 3866 } 3867 3868 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h) 3869 { 3870 struct net_device *ndev = h->kinfo.netdev; 3871 struct hns3_nic_priv *priv = netdev_priv(ndev); 3872 struct hns3_enet_ring *ring; 3873 u32 i; 3874 3875 for (i = 0; i < h->kinfo.num_tqps; i++) { 3876 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3877 hns3_force_clear_rx_ring(ring); 3878 } 3879 } 3880 3881 static void hns3_clear_all_ring(struct hnae3_handle *h) 3882 { 3883 struct net_device *ndev = h->kinfo.netdev; 3884 struct hns3_nic_priv *priv = netdev_priv(ndev); 3885 u32 i; 3886 3887 for (i = 0; i < h->kinfo.num_tqps; i++) { 3888 struct netdev_queue *dev_queue; 3889 struct hns3_enet_ring *ring; 3890 3891 ring = priv->ring_data[i].ring; 3892 hns3_clear_tx_ring(ring); 3893 dev_queue = netdev_get_tx_queue(ndev, 3894 priv->ring_data[i].queue_index); 3895 netdev_tx_reset_queue(dev_queue); 3896 3897 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3898 /* Continue to clear other rings even if clearing some 3899 * rings failed. 3900 */ 3901 hns3_clear_rx_ring(ring); 3902 } 3903 } 3904 3905 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 3906 { 3907 struct net_device *ndev = h->kinfo.netdev; 3908 struct hns3_nic_priv *priv = netdev_priv(ndev); 3909 struct hns3_enet_ring *rx_ring; 3910 int i, j; 3911 int ret; 3912 3913 for (i = 0; i < h->kinfo.num_tqps; i++) { 3914 ret = h->ae_algo->ops->reset_queue(h, i); 3915 if (ret) 3916 return ret; 3917 3918 hns3_init_ring_hw(priv->ring_data[i].ring); 3919 3920 /* We need to clear tx ring here because self test will 3921 * use the ring and will not run down before up 3922 */ 3923 hns3_clear_tx_ring(priv->ring_data[i].ring); 3924 priv->ring_data[i].ring->next_to_clean = 0; 3925 priv->ring_data[i].ring->next_to_use = 0; 3926 3927 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3928 hns3_init_ring_hw(rx_ring); 3929 ret = hns3_clear_rx_ring(rx_ring); 3930 if (ret) 3931 return ret; 3932 3933 /* We can not know the hardware head and tail when this 3934 * function is called in reset flow, so we reuse all desc. 3935 */ 3936 for (j = 0; j < rx_ring->desc_num; j++) 3937 hns3_reuse_buffer(rx_ring, j); 3938 3939 rx_ring->next_to_clean = 0; 3940 rx_ring->next_to_use = 0; 3941 } 3942 3943 hns3_init_tx_ring_tc(priv); 3944 3945 return 0; 3946 } 3947 3948 static void hns3_store_coal(struct hns3_nic_priv *priv) 3949 { 3950 /* ethtool only support setting and querying one coal 3951 * configuation for now, so save the vector 0' coal 3952 * configuation here in order to restore it. 3953 */ 3954 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal, 3955 sizeof(struct hns3_enet_coalesce)); 3956 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal, 3957 sizeof(struct hns3_enet_coalesce)); 3958 } 3959 3960 static void hns3_restore_coal(struct hns3_nic_priv *priv) 3961 { 3962 u16 vector_num = priv->vector_num; 3963 int i; 3964 3965 for (i = 0; i < vector_num; i++) { 3966 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal, 3967 sizeof(struct hns3_enet_coalesce)); 3968 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal, 3969 sizeof(struct hns3_enet_coalesce)); 3970 } 3971 } 3972 3973 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 3974 { 3975 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 3976 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3977 struct net_device *ndev = kinfo->netdev; 3978 struct hns3_nic_priv *priv = netdev_priv(ndev); 3979 3980 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 3981 return 0; 3982 3983 /* it is cumbersome for hardware to pick-and-choose entries for deletion 3984 * from table space. Hence, for function reset software intervention is 3985 * required to delete the entries 3986 */ 3987 if (hns3_dev_ongoing_func_reset(ae_dev)) { 3988 hns3_remove_hw_addr(ndev); 3989 hns3_del_all_fd_rules(ndev, false); 3990 } 3991 3992 if (!netif_running(ndev)) 3993 return 0; 3994 3995 return hns3_nic_net_stop(ndev); 3996 } 3997 3998 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 3999 { 4000 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4001 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 4002 int ret = 0; 4003 4004 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4005 4006 if (netif_running(kinfo->netdev)) { 4007 ret = hns3_nic_net_open(kinfo->netdev); 4008 if (ret) { 4009 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4010 netdev_err(kinfo->netdev, 4011 "hns net up fail, ret=%d!\n", ret); 4012 return ret; 4013 } 4014 } 4015 4016 return ret; 4017 } 4018 4019 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 4020 { 4021 struct net_device *netdev = handle->kinfo.netdev; 4022 struct hns3_nic_priv *priv = netdev_priv(netdev); 4023 int ret; 4024 4025 /* Carrier off reporting is important to ethtool even BEFORE open */ 4026 netif_carrier_off(netdev); 4027 4028 ret = hns3_get_ring_config(priv); 4029 if (ret) 4030 return ret; 4031 4032 ret = hns3_nic_alloc_vector_data(priv); 4033 if (ret) 4034 goto err_put_ring; 4035 4036 hns3_restore_coal(priv); 4037 4038 ret = hns3_nic_init_vector_data(priv); 4039 if (ret) 4040 goto err_dealloc_vector; 4041 4042 ret = hns3_init_all_ring(priv); 4043 if (ret) 4044 goto err_uninit_vector; 4045 4046 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4047 4048 return ret; 4049 4050 err_uninit_vector: 4051 hns3_nic_uninit_vector_data(priv); 4052 priv->ring_data = NULL; 4053 err_dealloc_vector: 4054 hns3_nic_dealloc_vector_data(priv); 4055 err_put_ring: 4056 hns3_put_ring_config(priv); 4057 priv->ring_data = NULL; 4058 4059 return ret; 4060 } 4061 4062 static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle) 4063 { 4064 struct net_device *netdev = handle->kinfo.netdev; 4065 bool vlan_filter_enable; 4066 int ret; 4067 4068 ret = hns3_init_mac_addr(netdev, false); 4069 if (ret) 4070 return ret; 4071 4072 ret = hns3_recover_hw_addr(netdev); 4073 if (ret) 4074 return ret; 4075 4076 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags); 4077 if (ret) 4078 return ret; 4079 4080 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true; 4081 hns3_enable_vlan_filter(netdev, vlan_filter_enable); 4082 4083 /* Hardware table is only clear when pf resets */ 4084 if (!(handle->flags & HNAE3_SUPPORT_VF)) { 4085 ret = hns3_restore_vlan(netdev); 4086 if (ret) 4087 return ret; 4088 } 4089 4090 return hns3_restore_fd_rules(netdev); 4091 } 4092 4093 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 4094 { 4095 struct net_device *netdev = handle->kinfo.netdev; 4096 struct hns3_nic_priv *priv = netdev_priv(netdev); 4097 int ret; 4098 4099 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4100 netdev_warn(netdev, "already uninitialized\n"); 4101 return 0; 4102 } 4103 4104 hns3_force_clear_all_rx_ring(handle); 4105 4106 hns3_nic_uninit_vector_data(priv); 4107 4108 hns3_store_coal(priv); 4109 4110 ret = hns3_nic_dealloc_vector_data(priv); 4111 if (ret) 4112 netdev_err(netdev, "dealloc vector error\n"); 4113 4114 ret = hns3_uninit_all_ring(priv); 4115 if (ret) 4116 netdev_err(netdev, "uninit ring error\n"); 4117 4118 hns3_put_ring_config(priv); 4119 priv->ring_data = NULL; 4120 4121 clear_bit(HNS3_NIC_STATE_INITED, &priv->state); 4122 4123 return ret; 4124 } 4125 4126 static int hns3_reset_notify(struct hnae3_handle *handle, 4127 enum hnae3_reset_notify_type type) 4128 { 4129 int ret = 0; 4130 4131 switch (type) { 4132 case HNAE3_UP_CLIENT: 4133 ret = hns3_reset_notify_up_enet(handle); 4134 break; 4135 case HNAE3_DOWN_CLIENT: 4136 ret = hns3_reset_notify_down_enet(handle); 4137 break; 4138 case HNAE3_INIT_CLIENT: 4139 ret = hns3_reset_notify_init_enet(handle); 4140 break; 4141 case HNAE3_UNINIT_CLIENT: 4142 ret = hns3_reset_notify_uninit_enet(handle); 4143 break; 4144 case HNAE3_RESTORE_CLIENT: 4145 ret = hns3_reset_notify_restore_enet(handle); 4146 break; 4147 default: 4148 break; 4149 } 4150 4151 return ret; 4152 } 4153 4154 int hns3_set_channels(struct net_device *netdev, 4155 struct ethtool_channels *ch) 4156 { 4157 struct hnae3_handle *h = hns3_get_handle(netdev); 4158 struct hnae3_knic_private_info *kinfo = &h->kinfo; 4159 bool rxfh_configured = netif_is_rxfh_configured(netdev); 4160 u32 new_tqp_num = ch->combined_count; 4161 u16 org_tqp_num; 4162 int ret; 4163 4164 if (ch->rx_count || ch->tx_count) 4165 return -EINVAL; 4166 4167 if (new_tqp_num > hns3_get_max_available_channels(h) || 4168 new_tqp_num < 1) { 4169 dev_err(&netdev->dev, 4170 "Change tqps fail, the tqp range is from 1 to %d", 4171 hns3_get_max_available_channels(h)); 4172 return -EINVAL; 4173 } 4174 4175 if (kinfo->rss_size == new_tqp_num) 4176 return 0; 4177 4178 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 4179 if (ret) 4180 return ret; 4181 4182 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 4183 if (ret) 4184 return ret; 4185 4186 org_tqp_num = h->kinfo.num_tqps; 4187 ret = h->ae_algo->ops->set_channels(h, new_tqp_num, rxfh_configured); 4188 if (ret) { 4189 ret = h->ae_algo->ops->set_channels(h, org_tqp_num, 4190 rxfh_configured); 4191 if (ret) { 4192 /* If revert to old tqp failed, fatal error occurred */ 4193 dev_err(&netdev->dev, 4194 "Revert to old tqp num fail, ret=%d", ret); 4195 return ret; 4196 } 4197 dev_info(&netdev->dev, 4198 "Change tqp num fail, Revert to old tqp num"); 4199 } 4200 ret = hns3_reset_notify(h, HNAE3_INIT_CLIENT); 4201 if (ret) 4202 return ret; 4203 4204 return hns3_reset_notify(h, HNAE3_UP_CLIENT); 4205 } 4206 4207 static const struct hnae3_client_ops client_ops = { 4208 .init_instance = hns3_client_init, 4209 .uninit_instance = hns3_client_uninit, 4210 .link_status_change = hns3_link_status_change, 4211 .setup_tc = hns3_client_setup_tc, 4212 .reset_notify = hns3_reset_notify, 4213 }; 4214 4215 /* hns3_init_module - Driver registration routine 4216 * hns3_init_module is the first routine called when the driver is 4217 * loaded. All it does is register with the PCI subsystem. 4218 */ 4219 static int __init hns3_init_module(void) 4220 { 4221 int ret; 4222 4223 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 4224 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 4225 4226 client.type = HNAE3_CLIENT_KNIC; 4227 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s", 4228 hns3_driver_name); 4229 4230 client.ops = &client_ops; 4231 4232 INIT_LIST_HEAD(&client.node); 4233 4234 hns3_dbg_register_debugfs(hns3_driver_name); 4235 4236 ret = hnae3_register_client(&client); 4237 if (ret) 4238 goto err_reg_client; 4239 4240 ret = pci_register_driver(&hns3_driver); 4241 if (ret) 4242 goto err_reg_driver; 4243 4244 return ret; 4245 4246 err_reg_driver: 4247 hnae3_unregister_client(&client); 4248 err_reg_client: 4249 hns3_dbg_unregister_debugfs(); 4250 return ret; 4251 } 4252 module_init(hns3_init_module); 4253 4254 /* hns3_exit_module - Driver exit cleanup routine 4255 * hns3_exit_module is called just before the driver is removed 4256 * from memory. 4257 */ 4258 static void __exit hns3_exit_module(void) 4259 { 4260 pci_unregister_driver(&hns3_driver); 4261 hnae3_unregister_client(&client); 4262 hns3_dbg_unregister_debugfs(); 4263 } 4264 module_exit(hns3_exit_module); 4265 4266 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 4267 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 4268 MODULE_LICENSE("GPL"); 4269 MODULE_ALIAS("pci:hns-nic"); 4270 MODULE_VERSION(HNS3_MOD_VERSION); 4271