1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #ifdef CONFIG_RFS_ACCEL 8 #include <linux/cpu_rmap.h> 9 #endif 10 #include <linux/if_vlan.h> 11 #include <linux/irq.h> 12 #include <linux/ip.h> 13 #include <linux/ipv6.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/aer.h> 17 #include <linux/skbuff.h> 18 #include <linux/sctp.h> 19 #include <net/gre.h> 20 #include <net/ip6_checksum.h> 21 #include <net/pkt_cls.h> 22 #include <net/tcp.h> 23 #include <net/vxlan.h> 24 #include <net/geneve.h> 25 26 #include "hnae3.h" 27 #include "hns3_enet.h" 28 /* All hns3 tracepoints are defined by the include below, which 29 * must be included exactly once across the whole kernel with 30 * CREATE_TRACE_POINTS defined 31 */ 32 #define CREATE_TRACE_POINTS 33 #include "hns3_trace.h" 34 35 #define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift)) 36 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE) 37 38 #define hns3_rl_err(fmt, ...) \ 39 do { \ 40 if (net_ratelimit()) \ 41 netdev_err(fmt, ##__VA_ARGS__); \ 42 } while (0) 43 44 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force); 45 46 static const char hns3_driver_name[] = "hns3"; 47 static const char hns3_driver_string[] = 48 "Hisilicon Ethernet Network Driver for Hip08 Family"; 49 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 50 static struct hnae3_client client; 51 52 static int debug = -1; 53 module_param(debug, int, 0); 54 MODULE_PARM_DESC(debug, " Network interface message level setting"); 55 56 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 57 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) 58 59 #define HNS3_INNER_VLAN_TAG 1 60 #define HNS3_OUTER_VLAN_TAG 2 61 62 #define HNS3_MIN_TX_LEN 33U 63 64 /* hns3_pci_tbl - PCI Device ID Table 65 * 66 * Last entry must be all 0s 67 * 68 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 69 * Class, Class Mask, private data (not used) } 70 */ 71 static const struct pci_device_id hns3_pci_tbl[] = { 72 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 75 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 77 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 79 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 80 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 81 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 83 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 84 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 85 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 86 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 88 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 89 /* required last entry */ 90 {0, } 91 }; 92 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 93 94 static irqreturn_t hns3_irq_handle(int irq, void *vector) 95 { 96 struct hns3_enet_tqp_vector *tqp_vector = vector; 97 98 napi_schedule_irqoff(&tqp_vector->napi); 99 100 return IRQ_HANDLED; 101 } 102 103 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 104 { 105 struct hns3_enet_tqp_vector *tqp_vectors; 106 unsigned int i; 107 108 for (i = 0; i < priv->vector_num; i++) { 109 tqp_vectors = &priv->tqp_vector[i]; 110 111 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 112 continue; 113 114 /* clear the affinity mask */ 115 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 116 117 /* release the irq resource */ 118 free_irq(tqp_vectors->vector_irq, tqp_vectors); 119 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 120 } 121 } 122 123 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 124 { 125 struct hns3_enet_tqp_vector *tqp_vectors; 126 int txrx_int_idx = 0; 127 int rx_int_idx = 0; 128 int tx_int_idx = 0; 129 unsigned int i; 130 int ret; 131 132 for (i = 0; i < priv->vector_num; i++) { 133 tqp_vectors = &priv->tqp_vector[i]; 134 135 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 136 continue; 137 138 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 139 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 140 "%s-%s-%s-%d", hns3_driver_name, 141 pci_name(priv->ae_handle->pdev), 142 "TxRx", txrx_int_idx++); 143 txrx_int_idx++; 144 } else if (tqp_vectors->rx_group.ring) { 145 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 146 "%s-%s-%s-%d", hns3_driver_name, 147 pci_name(priv->ae_handle->pdev), 148 "Rx", rx_int_idx++); 149 } else if (tqp_vectors->tx_group.ring) { 150 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 151 "%s-%s-%s-%d", hns3_driver_name, 152 pci_name(priv->ae_handle->pdev), 153 "Tx", tx_int_idx++); 154 } else { 155 /* Skip this unused q_vector */ 156 continue; 157 } 158 159 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 160 161 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN); 162 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 163 tqp_vectors->name, tqp_vectors); 164 if (ret) { 165 netdev_err(priv->netdev, "request irq(%d) fail\n", 166 tqp_vectors->vector_irq); 167 hns3_nic_uninit_irq(priv); 168 return ret; 169 } 170 171 irq_set_affinity_hint(tqp_vectors->vector_irq, 172 &tqp_vectors->affinity_mask); 173 174 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 175 } 176 177 return 0; 178 } 179 180 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 181 u32 mask_en) 182 { 183 writel(mask_en, tqp_vector->mask_addr); 184 } 185 186 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 187 { 188 napi_enable(&tqp_vector->napi); 189 enable_irq(tqp_vector->vector_irq); 190 191 /* enable vector */ 192 hns3_mask_vector_irq(tqp_vector, 1); 193 } 194 195 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 196 { 197 /* disable vector */ 198 hns3_mask_vector_irq(tqp_vector, 0); 199 200 disable_irq(tqp_vector->vector_irq); 201 napi_disable(&tqp_vector->napi); 202 } 203 204 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 205 u32 rl_value) 206 { 207 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 208 209 /* this defines the configuration for RL (Interrupt Rate Limiter). 210 * Rl defines rate of interrupts i.e. number of interrupts-per-second 211 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 212 */ 213 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable && 214 !tqp_vector->rx_group.coal.adapt_enable) 215 /* According to the hardware, the range of rl_reg is 216 * 0-59 and the unit is 4. 217 */ 218 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 219 220 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 221 } 222 223 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 224 u32 gl_value) 225 { 226 u32 new_val; 227 228 if (tqp_vector->rx_group.coal.unit_1us) 229 new_val = gl_value | HNS3_INT_GL_1US; 230 else 231 new_val = hns3_gl_usec_to_reg(gl_value); 232 233 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 234 } 235 236 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 237 u32 gl_value) 238 { 239 u32 new_val; 240 241 if (tqp_vector->tx_group.coal.unit_1us) 242 new_val = gl_value | HNS3_INT_GL_1US; 243 else 244 new_val = hns3_gl_usec_to_reg(gl_value); 245 246 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 247 } 248 249 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector, 250 u32 ql_value) 251 { 252 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET); 253 } 254 255 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector, 256 u32 ql_value) 257 { 258 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET); 259 } 260 261 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector, 262 struct hns3_nic_priv *priv) 263 { 264 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 265 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 266 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 267 268 /* initialize the configuration for interrupt coalescing. 269 * 1. GL (Interrupt Gap Limiter) 270 * 2. RL (Interrupt Rate Limiter) 271 * 3. QL (Interrupt Quantity Limiter) 272 * 273 * Default: enable interrupt coalescing self-adaptive and GL 274 */ 275 tx_coal->adapt_enable = 1; 276 rx_coal->adapt_enable = 1; 277 278 tx_coal->int_gl = HNS3_INT_GL_50K; 279 rx_coal->int_gl = HNS3_INT_GL_50K; 280 281 rx_coal->flow_level = HNS3_FLOW_LOW; 282 tx_coal->flow_level = HNS3_FLOW_LOW; 283 284 /* device version above V3(include V3), GL can configure 1us 285 * unit, so uses 1us unit. 286 */ 287 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) { 288 tx_coal->unit_1us = 1; 289 rx_coal->unit_1us = 1; 290 } 291 292 if (ae_dev->dev_specs.int_ql_max) { 293 tx_coal->ql_enable = 1; 294 rx_coal->ql_enable = 1; 295 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 296 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 297 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 298 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 299 } 300 } 301 302 static void 303 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 304 struct hns3_nic_priv *priv) 305 { 306 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 307 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 308 struct hnae3_handle *h = priv->ae_handle; 309 310 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl); 311 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl); 312 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 313 314 if (tx_coal->ql_enable) 315 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql); 316 317 if (rx_coal->ql_enable) 318 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql); 319 } 320 321 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 322 { 323 struct hnae3_handle *h = hns3_get_handle(netdev); 324 struct hnae3_knic_private_info *kinfo = &h->kinfo; 325 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 326 unsigned int queue_size = kinfo->num_tqps; 327 int i, ret; 328 329 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) { 330 netdev_reset_tc(netdev); 331 } else { 332 ret = netdev_set_num_tc(netdev, tc_info->num_tc); 333 if (ret) { 334 netdev_err(netdev, 335 "netdev_set_num_tc fail, ret=%d!\n", ret); 336 return ret; 337 } 338 339 for (i = 0; i < HNAE3_MAX_TC; i++) { 340 if (!test_bit(i, &tc_info->tc_en)) 341 continue; 342 343 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i], 344 tc_info->tqp_offset[i]); 345 } 346 } 347 348 ret = netif_set_real_num_tx_queues(netdev, queue_size); 349 if (ret) { 350 netdev_err(netdev, 351 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret); 352 return ret; 353 } 354 355 ret = netif_set_real_num_rx_queues(netdev, queue_size); 356 if (ret) { 357 netdev_err(netdev, 358 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 359 return ret; 360 } 361 362 return 0; 363 } 364 365 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 366 { 367 u16 alloc_tqps, max_rss_size, rss_size; 368 369 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 370 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc; 371 372 return min_t(u16, rss_size, max_rss_size); 373 } 374 375 static void hns3_tqp_enable(struct hnae3_queue *tqp) 376 { 377 u32 rcb_reg; 378 379 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 380 rcb_reg |= BIT(HNS3_RING_EN_B); 381 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 382 } 383 384 static void hns3_tqp_disable(struct hnae3_queue *tqp) 385 { 386 u32 rcb_reg; 387 388 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 389 rcb_reg &= ~BIT(HNS3_RING_EN_B); 390 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 391 } 392 393 static void hns3_free_rx_cpu_rmap(struct net_device *netdev) 394 { 395 #ifdef CONFIG_RFS_ACCEL 396 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 397 netdev->rx_cpu_rmap = NULL; 398 #endif 399 } 400 401 static int hns3_set_rx_cpu_rmap(struct net_device *netdev) 402 { 403 #ifdef CONFIG_RFS_ACCEL 404 struct hns3_nic_priv *priv = netdev_priv(netdev); 405 struct hns3_enet_tqp_vector *tqp_vector; 406 int i, ret; 407 408 if (!netdev->rx_cpu_rmap) { 409 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num); 410 if (!netdev->rx_cpu_rmap) 411 return -ENOMEM; 412 } 413 414 for (i = 0; i < priv->vector_num; i++) { 415 tqp_vector = &priv->tqp_vector[i]; 416 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap, 417 tqp_vector->vector_irq); 418 if (ret) { 419 hns3_free_rx_cpu_rmap(netdev); 420 return ret; 421 } 422 } 423 #endif 424 return 0; 425 } 426 427 static int hns3_nic_net_up(struct net_device *netdev) 428 { 429 struct hns3_nic_priv *priv = netdev_priv(netdev); 430 struct hnae3_handle *h = priv->ae_handle; 431 int i, j; 432 int ret; 433 434 ret = hns3_nic_reset_all_ring(h); 435 if (ret) 436 return ret; 437 438 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 439 440 /* enable the vectors */ 441 for (i = 0; i < priv->vector_num; i++) 442 hns3_vector_enable(&priv->tqp_vector[i]); 443 444 /* enable rcb */ 445 for (j = 0; j < h->kinfo.num_tqps; j++) 446 hns3_tqp_enable(h->kinfo.tqp[j]); 447 448 /* start the ae_dev */ 449 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 450 if (ret) { 451 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 452 while (j--) 453 hns3_tqp_disable(h->kinfo.tqp[j]); 454 455 for (j = i - 1; j >= 0; j--) 456 hns3_vector_disable(&priv->tqp_vector[j]); 457 } 458 459 return ret; 460 } 461 462 static void hns3_config_xps(struct hns3_nic_priv *priv) 463 { 464 int i; 465 466 for (i = 0; i < priv->vector_num; i++) { 467 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 468 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 469 470 while (ring) { 471 int ret; 472 473 ret = netif_set_xps_queue(priv->netdev, 474 &tqp_vector->affinity_mask, 475 ring->tqp->tqp_index); 476 if (ret) 477 netdev_warn(priv->netdev, 478 "set xps queue failed: %d", ret); 479 480 ring = ring->next; 481 } 482 } 483 } 484 485 static int hns3_nic_net_open(struct net_device *netdev) 486 { 487 struct hns3_nic_priv *priv = netdev_priv(netdev); 488 struct hnae3_handle *h = hns3_get_handle(netdev); 489 struct hnae3_knic_private_info *kinfo; 490 int i, ret; 491 492 if (hns3_nic_resetting(netdev)) 493 return -EBUSY; 494 495 netif_carrier_off(netdev); 496 497 ret = hns3_nic_set_real_num_queue(netdev); 498 if (ret) 499 return ret; 500 501 ret = hns3_nic_net_up(netdev); 502 if (ret) { 503 netdev_err(netdev, "net up fail, ret=%d!\n", ret); 504 return ret; 505 } 506 507 kinfo = &h->kinfo; 508 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 509 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]); 510 511 if (h->ae_algo->ops->set_timer_task) 512 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 513 514 hns3_config_xps(priv); 515 516 netif_dbg(h, drv, netdev, "net open\n"); 517 518 return 0; 519 } 520 521 static void hns3_reset_tx_queue(struct hnae3_handle *h) 522 { 523 struct net_device *ndev = h->kinfo.netdev; 524 struct hns3_nic_priv *priv = netdev_priv(ndev); 525 struct netdev_queue *dev_queue; 526 u32 i; 527 528 for (i = 0; i < h->kinfo.num_tqps; i++) { 529 dev_queue = netdev_get_tx_queue(ndev, 530 priv->ring[i].queue_index); 531 netdev_tx_reset_queue(dev_queue); 532 } 533 } 534 535 static void hns3_nic_net_down(struct net_device *netdev) 536 { 537 struct hns3_nic_priv *priv = netdev_priv(netdev); 538 struct hnae3_handle *h = hns3_get_handle(netdev); 539 const struct hnae3_ae_ops *ops; 540 int i; 541 542 /* disable vectors */ 543 for (i = 0; i < priv->vector_num; i++) 544 hns3_vector_disable(&priv->tqp_vector[i]); 545 546 /* disable rcb */ 547 for (i = 0; i < h->kinfo.num_tqps; i++) 548 hns3_tqp_disable(h->kinfo.tqp[i]); 549 550 /* stop ae_dev */ 551 ops = priv->ae_handle->ae_algo->ops; 552 if (ops->stop) 553 ops->stop(priv->ae_handle); 554 555 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 556 * during reset process, because driver may not be able 557 * to disable the ring through firmware when downing the netdev. 558 */ 559 if (!hns3_nic_resetting(netdev)) 560 hns3_clear_all_ring(priv->ae_handle, false); 561 562 hns3_reset_tx_queue(priv->ae_handle); 563 } 564 565 static int hns3_nic_net_stop(struct net_device *netdev) 566 { 567 struct hns3_nic_priv *priv = netdev_priv(netdev); 568 struct hnae3_handle *h = hns3_get_handle(netdev); 569 570 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 571 return 0; 572 573 netif_dbg(h, drv, netdev, "net stop\n"); 574 575 if (h->ae_algo->ops->set_timer_task) 576 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 577 578 netif_tx_stop_all_queues(netdev); 579 netif_carrier_off(netdev); 580 581 hns3_nic_net_down(netdev); 582 583 return 0; 584 } 585 586 static int hns3_nic_uc_sync(struct net_device *netdev, 587 const unsigned char *addr) 588 { 589 struct hnae3_handle *h = hns3_get_handle(netdev); 590 591 if (h->ae_algo->ops->add_uc_addr) 592 return h->ae_algo->ops->add_uc_addr(h, addr); 593 594 return 0; 595 } 596 597 static int hns3_nic_uc_unsync(struct net_device *netdev, 598 const unsigned char *addr) 599 { 600 struct hnae3_handle *h = hns3_get_handle(netdev); 601 602 /* need ignore the request of removing device address, because 603 * we store the device address and other addresses of uc list 604 * in the function's mac filter list. 605 */ 606 if (ether_addr_equal(addr, netdev->dev_addr)) 607 return 0; 608 609 if (h->ae_algo->ops->rm_uc_addr) 610 return h->ae_algo->ops->rm_uc_addr(h, addr); 611 612 return 0; 613 } 614 615 static int hns3_nic_mc_sync(struct net_device *netdev, 616 const unsigned char *addr) 617 { 618 struct hnae3_handle *h = hns3_get_handle(netdev); 619 620 if (h->ae_algo->ops->add_mc_addr) 621 return h->ae_algo->ops->add_mc_addr(h, addr); 622 623 return 0; 624 } 625 626 static int hns3_nic_mc_unsync(struct net_device *netdev, 627 const unsigned char *addr) 628 { 629 struct hnae3_handle *h = hns3_get_handle(netdev); 630 631 if (h->ae_algo->ops->rm_mc_addr) 632 return h->ae_algo->ops->rm_mc_addr(h, addr); 633 634 return 0; 635 } 636 637 static u8 hns3_get_netdev_flags(struct net_device *netdev) 638 { 639 u8 flags = 0; 640 641 if (netdev->flags & IFF_PROMISC) { 642 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 643 } else { 644 flags |= HNAE3_VLAN_FLTR; 645 if (netdev->flags & IFF_ALLMULTI) 646 flags |= HNAE3_USER_MPE; 647 } 648 649 return flags; 650 } 651 652 static void hns3_nic_set_rx_mode(struct net_device *netdev) 653 { 654 struct hnae3_handle *h = hns3_get_handle(netdev); 655 u8 new_flags; 656 657 new_flags = hns3_get_netdev_flags(netdev); 658 659 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 660 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync); 661 662 /* User mode Promisc mode enable and vlan filtering is disabled to 663 * let all packets in. 664 */ 665 h->netdev_flags = new_flags; 666 hns3_request_update_promisc_mode(h); 667 } 668 669 void hns3_request_update_promisc_mode(struct hnae3_handle *handle) 670 { 671 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 672 673 if (ops->request_update_promisc_mode) 674 ops->request_update_promisc_mode(handle); 675 } 676 677 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable) 678 { 679 struct hns3_nic_priv *priv = netdev_priv(netdev); 680 struct hnae3_handle *h = priv->ae_handle; 681 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 682 bool last_state; 683 684 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 && 685 h->ae_algo->ops->enable_vlan_filter) { 686 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false; 687 if (enable != last_state) { 688 netdev_info(netdev, 689 "%s vlan filter\n", 690 enable ? "enable" : "disable"); 691 h->ae_algo->ops->enable_vlan_filter(h, enable); 692 } 693 } 694 } 695 696 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs, 697 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes) 698 { 699 u32 l4_offset, hdr_len; 700 union l3_hdr_info l3; 701 union l4_hdr_info l4; 702 u32 l4_paylen; 703 int ret; 704 705 if (!skb_is_gso(skb)) 706 return 0; 707 708 ret = skb_cow_head(skb, 0); 709 if (unlikely(ret < 0)) 710 return ret; 711 712 l3.hdr = skb_network_header(skb); 713 l4.hdr = skb_transport_header(skb); 714 715 /* Software should clear the IPv4's checksum field when tso is 716 * needed. 717 */ 718 if (l3.v4->version == 4) 719 l3.v4->check = 0; 720 721 /* tunnel packet */ 722 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 723 SKB_GSO_GRE_CSUM | 724 SKB_GSO_UDP_TUNNEL | 725 SKB_GSO_UDP_TUNNEL_CSUM)) { 726 /* reset l3&l4 pointers from outer to inner headers */ 727 l3.hdr = skb_inner_network_header(skb); 728 l4.hdr = skb_inner_transport_header(skb); 729 730 /* Software should clear the IPv4's checksum field when 731 * tso is needed. 732 */ 733 if (l3.v4->version == 4) 734 l3.v4->check = 0; 735 } 736 737 /* normal or tunnel packet */ 738 l4_offset = l4.hdr - skb->data; 739 740 /* remove payload length from inner pseudo checksum when tso */ 741 l4_paylen = skb->len - l4_offset; 742 743 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 744 hdr_len = sizeof(*l4.udp) + l4_offset; 745 csum_replace_by_diff(&l4.udp->check, 746 (__force __wsum)htonl(l4_paylen)); 747 } else { 748 hdr_len = (l4.tcp->doff << 2) + l4_offset; 749 csum_replace_by_diff(&l4.tcp->check, 750 (__force __wsum)htonl(l4_paylen)); 751 } 752 753 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len; 754 755 /* find the txbd field values */ 756 *paylen_fdop_ol4cs = skb->len - hdr_len; 757 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 758 759 /* offload outer UDP header checksum */ 760 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM) 761 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1); 762 763 /* get MSS for TSO */ 764 *mss = skb_shinfo(skb)->gso_size; 765 766 trace_hns3_tso(skb); 767 768 return 0; 769 } 770 771 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 772 u8 *il4_proto) 773 { 774 union l3_hdr_info l3; 775 unsigned char *l4_hdr; 776 unsigned char *exthdr; 777 u8 l4_proto_tmp; 778 __be16 frag_off; 779 780 /* find outer header point */ 781 l3.hdr = skb_network_header(skb); 782 l4_hdr = skb_transport_header(skb); 783 784 if (skb->protocol == htons(ETH_P_IPV6)) { 785 exthdr = l3.hdr + sizeof(*l3.v6); 786 l4_proto_tmp = l3.v6->nexthdr; 787 if (l4_hdr != exthdr) 788 ipv6_skip_exthdr(skb, exthdr - skb->data, 789 &l4_proto_tmp, &frag_off); 790 } else if (skb->protocol == htons(ETH_P_IP)) { 791 l4_proto_tmp = l3.v4->protocol; 792 } else { 793 return -EINVAL; 794 } 795 796 *ol4_proto = l4_proto_tmp; 797 798 /* tunnel packet */ 799 if (!skb->encapsulation) { 800 *il4_proto = 0; 801 return 0; 802 } 803 804 /* find inner header point */ 805 l3.hdr = skb_inner_network_header(skb); 806 l4_hdr = skb_inner_transport_header(skb); 807 808 if (l3.v6->version == 6) { 809 exthdr = l3.hdr + sizeof(*l3.v6); 810 l4_proto_tmp = l3.v6->nexthdr; 811 if (l4_hdr != exthdr) 812 ipv6_skip_exthdr(skb, exthdr - skb->data, 813 &l4_proto_tmp, &frag_off); 814 } else if (l3.v4->version == 4) { 815 l4_proto_tmp = l3.v4->protocol; 816 } 817 818 *il4_proto = l4_proto_tmp; 819 820 return 0; 821 } 822 823 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 824 * and it is udp packet, which has a dest port as the IANA assigned. 825 * the hardware is expected to do the checksum offload, but the 826 * hardware will not do the checksum offload when udp dest port is 827 * 4789 or 6081. 828 */ 829 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 830 { 831 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 832 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 833 union l4_hdr_info l4; 834 835 /* device version above V3(include V3), the hardware can 836 * do this checksum offload. 837 */ 838 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 839 return false; 840 841 l4.hdr = skb_transport_header(skb); 842 843 if (!(!skb->encapsulation && 844 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) || 845 l4.udp->dest == htons(GENEVE_UDP_PORT)))) 846 return false; 847 848 skb_checksum_help(skb); 849 850 return true; 851 } 852 853 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 854 u32 *ol_type_vlan_len_msec) 855 { 856 u32 l2_len, l3_len, l4_len; 857 unsigned char *il2_hdr; 858 union l3_hdr_info l3; 859 union l4_hdr_info l4; 860 861 l3.hdr = skb_network_header(skb); 862 l4.hdr = skb_transport_header(skb); 863 864 /* compute OL2 header size, defined in 2 Bytes */ 865 l2_len = l3.hdr - skb->data; 866 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1); 867 868 /* compute OL3 header size, defined in 4 Bytes */ 869 l3_len = l4.hdr - l3.hdr; 870 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2); 871 872 il2_hdr = skb_inner_mac_header(skb); 873 /* compute OL4 header size, defined in 4 Bytes */ 874 l4_len = il2_hdr - l4.hdr; 875 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2); 876 877 /* define outer network header type */ 878 if (skb->protocol == htons(ETH_P_IP)) { 879 if (skb_is_gso(skb)) 880 hns3_set_field(*ol_type_vlan_len_msec, 881 HNS3_TXD_OL3T_S, 882 HNS3_OL3T_IPV4_CSUM); 883 else 884 hns3_set_field(*ol_type_vlan_len_msec, 885 HNS3_TXD_OL3T_S, 886 HNS3_OL3T_IPV4_NO_CSUM); 887 } else if (skb->protocol == htons(ETH_P_IPV6)) { 888 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 889 HNS3_OL3T_IPV6); 890 } 891 892 if (ol4_proto == IPPROTO_UDP) 893 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 894 HNS3_TUN_MAC_IN_UDP); 895 else if (ol4_proto == IPPROTO_GRE) 896 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 897 HNS3_TUN_NVGRE); 898 } 899 900 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 901 u8 il4_proto, u32 *type_cs_vlan_tso, 902 u32 *ol_type_vlan_len_msec) 903 { 904 unsigned char *l2_hdr = skb->data; 905 u32 l4_proto = ol4_proto; 906 union l4_hdr_info l4; 907 union l3_hdr_info l3; 908 u32 l2_len, l3_len; 909 910 l4.hdr = skb_transport_header(skb); 911 l3.hdr = skb_network_header(skb); 912 913 /* handle encapsulation skb */ 914 if (skb->encapsulation) { 915 /* If this is a not UDP/GRE encapsulation skb */ 916 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) { 917 /* drop the skb tunnel packet if hardware don't support, 918 * because hardware can't calculate csum when TSO. 919 */ 920 if (skb_is_gso(skb)) 921 return -EDOM; 922 923 /* the stack computes the IP header already, 924 * driver calculate l4 checksum when not TSO. 925 */ 926 skb_checksum_help(skb); 927 return 0; 928 } 929 930 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec); 931 932 /* switch to inner header */ 933 l2_hdr = skb_inner_mac_header(skb); 934 l3.hdr = skb_inner_network_header(skb); 935 l4.hdr = skb_inner_transport_header(skb); 936 l4_proto = il4_proto; 937 } 938 939 if (l3.v4->version == 4) { 940 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 941 HNS3_L3T_IPV4); 942 943 /* the stack computes the IP header already, the only time we 944 * need the hardware to recompute it is in the case of TSO. 945 */ 946 if (skb_is_gso(skb)) 947 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 948 } else if (l3.v6->version == 6) { 949 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 950 HNS3_L3T_IPV6); 951 } 952 953 /* compute inner(/normal) L2 header size, defined in 2 Bytes */ 954 l2_len = l3.hdr - l2_hdr; 955 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 956 957 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 958 l3_len = l4.hdr - l3.hdr; 959 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 960 961 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 962 switch (l4_proto) { 963 case IPPROTO_TCP: 964 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 965 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 966 HNS3_L4T_TCP); 967 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 968 l4.tcp->doff); 969 break; 970 case IPPROTO_UDP: 971 if (hns3_tunnel_csum_bug(skb)) 972 break; 973 974 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 975 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 976 HNS3_L4T_UDP); 977 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 978 (sizeof(struct udphdr) >> 2)); 979 break; 980 case IPPROTO_SCTP: 981 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 982 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 983 HNS3_L4T_SCTP); 984 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 985 (sizeof(struct sctphdr) >> 2)); 986 break; 987 default: 988 /* drop the skb tunnel packet if hardware don't support, 989 * because hardware can't calculate csum when TSO. 990 */ 991 if (skb_is_gso(skb)) 992 return -EDOM; 993 994 /* the stack computes the IP header already, 995 * driver calculate l4 checksum when not TSO. 996 */ 997 skb_checksum_help(skb); 998 return 0; 999 } 1000 1001 return 0; 1002 } 1003 1004 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring, 1005 struct sk_buff *skb) 1006 { 1007 struct hnae3_handle *handle = tx_ring->tqp->handle; 1008 struct hnae3_ae_dev *ae_dev; 1009 struct vlan_ethhdr *vhdr; 1010 int rc; 1011 1012 if (!(skb->protocol == htons(ETH_P_8021Q) || 1013 skb_vlan_tag_present(skb))) 1014 return 0; 1015 1016 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert 1017 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it 1018 * will cause RAS error. 1019 */ 1020 ae_dev = pci_get_drvdata(handle->pdev); 1021 if (unlikely(skb_vlan_tagged_multi(skb) && 1022 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 && 1023 handle->port_base_vlan_state == 1024 HNAE3_PORT_BASE_VLAN_ENABLE)) 1025 return -EINVAL; 1026 1027 if (skb->protocol == htons(ETH_P_8021Q) && 1028 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 1029 /* When HW VLAN acceleration is turned off, and the stack 1030 * sets the protocol to 802.1q, the driver just need to 1031 * set the protocol to the encapsulated ethertype. 1032 */ 1033 skb->protocol = vlan_get_protocol(skb); 1034 return 0; 1035 } 1036 1037 if (skb_vlan_tag_present(skb)) { 1038 /* Based on hw strategy, use out_vtag in two layer tag case, 1039 * and use inner_vtag in one tag case. 1040 */ 1041 if (skb->protocol == htons(ETH_P_8021Q) && 1042 handle->port_base_vlan_state == 1043 HNAE3_PORT_BASE_VLAN_DISABLE) 1044 rc = HNS3_OUTER_VLAN_TAG; 1045 else 1046 rc = HNS3_INNER_VLAN_TAG; 1047 1048 skb->protocol = vlan_get_protocol(skb); 1049 return rc; 1050 } 1051 1052 rc = skb_cow_head(skb, 0); 1053 if (unlikely(rc < 0)) 1054 return rc; 1055 1056 vhdr = (struct vlan_ethhdr *)skb->data; 1057 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT) 1058 & VLAN_PRIO_MASK); 1059 1060 skb->protocol = vlan_get_protocol(skb); 1061 return 0; 1062 } 1063 1064 /* check if the hardware is capable of checksum offloading */ 1065 static bool hns3_check_hw_tx_csum(struct sk_buff *skb) 1066 { 1067 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 1068 1069 /* Kindly note, due to backward compatibility of the TX descriptor, 1070 * HW checksum of the non-IP packets and GSO packets is handled at 1071 * different place in the following code 1072 */ 1073 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) || 1074 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state)) 1075 return false; 1076 1077 return true; 1078 } 1079 1080 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring, 1081 struct sk_buff *skb, struct hns3_desc *desc, 1082 struct hns3_desc_cb *desc_cb) 1083 { 1084 u32 ol_type_vlan_len_msec = 0; 1085 u32 paylen_ol4cs = skb->len; 1086 u32 type_cs_vlan_tso = 0; 1087 u16 mss_hw_csum = 0; 1088 u16 inner_vtag = 0; 1089 u16 out_vtag = 0; 1090 int ret; 1091 1092 ret = hns3_handle_vtags(ring, skb); 1093 if (unlikely(ret < 0)) { 1094 u64_stats_update_begin(&ring->syncp); 1095 ring->stats.tx_vlan_err++; 1096 u64_stats_update_end(&ring->syncp); 1097 return ret; 1098 } else if (ret == HNS3_INNER_VLAN_TAG) { 1099 inner_vtag = skb_vlan_tag_get(skb); 1100 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1101 VLAN_PRIO_MASK; 1102 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1); 1103 } else if (ret == HNS3_OUTER_VLAN_TAG) { 1104 out_vtag = skb_vlan_tag_get(skb); 1105 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1106 VLAN_PRIO_MASK; 1107 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B, 1108 1); 1109 } 1110 1111 desc_cb->send_bytes = skb->len; 1112 1113 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1114 u8 ol4_proto, il4_proto; 1115 1116 if (hns3_check_hw_tx_csum(skb)) { 1117 /* set checksum start and offset, defined in 2 Bytes */ 1118 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_CSUM_START_S, 1119 skb_checksum_start_offset(skb) >> 1); 1120 hns3_set_field(ol_type_vlan_len_msec, 1121 HNS3_TXD_CSUM_OFFSET_S, 1122 skb->csum_offset >> 1); 1123 mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B); 1124 goto out_hw_tx_csum; 1125 } 1126 1127 skb_reset_mac_len(skb); 1128 1129 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1130 if (unlikely(ret < 0)) { 1131 u64_stats_update_begin(&ring->syncp); 1132 ring->stats.tx_l4_proto_err++; 1133 u64_stats_update_end(&ring->syncp); 1134 return ret; 1135 } 1136 1137 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto, 1138 &type_cs_vlan_tso, 1139 &ol_type_vlan_len_msec); 1140 if (unlikely(ret < 0)) { 1141 u64_stats_update_begin(&ring->syncp); 1142 ring->stats.tx_l2l3l4_err++; 1143 u64_stats_update_end(&ring->syncp); 1144 return ret; 1145 } 1146 1147 ret = hns3_set_tso(skb, &paylen_ol4cs, &mss_hw_csum, 1148 &type_cs_vlan_tso, &desc_cb->send_bytes); 1149 if (unlikely(ret < 0)) { 1150 u64_stats_update_begin(&ring->syncp); 1151 ring->stats.tx_tso_err++; 1152 u64_stats_update_end(&ring->syncp); 1153 return ret; 1154 } 1155 } 1156 1157 out_hw_tx_csum: 1158 /* Set txbd */ 1159 desc->tx.ol_type_vlan_len_msec = 1160 cpu_to_le32(ol_type_vlan_len_msec); 1161 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso); 1162 desc->tx.paylen_ol4cs = cpu_to_le32(paylen_ol4cs); 1163 desc->tx.mss_hw_csum = cpu_to_le16(mss_hw_csum); 1164 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1165 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1166 1167 return 0; 1168 } 1169 1170 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 1171 unsigned int size, enum hns_desc_type type) 1172 { 1173 #define HNS3_LIKELY_BD_NUM 1 1174 1175 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1176 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1177 struct device *dev = ring_to_dev(ring); 1178 skb_frag_t *frag; 1179 unsigned int frag_buf_num; 1180 int k, sizeoflast; 1181 dma_addr_t dma; 1182 1183 if (type == DESC_TYPE_FRAGLIST_SKB || 1184 type == DESC_TYPE_SKB) { 1185 struct sk_buff *skb = (struct sk_buff *)priv; 1186 1187 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1188 } else { 1189 frag = (skb_frag_t *)priv; 1190 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1191 } 1192 1193 if (unlikely(dma_mapping_error(dev, dma))) { 1194 u64_stats_update_begin(&ring->syncp); 1195 ring->stats.sw_err_cnt++; 1196 u64_stats_update_end(&ring->syncp); 1197 return -ENOMEM; 1198 } 1199 1200 desc_cb->priv = priv; 1201 desc_cb->length = size; 1202 desc_cb->dma = dma; 1203 desc_cb->type = type; 1204 1205 if (likely(size <= HNS3_MAX_BD_SIZE)) { 1206 desc->addr = cpu_to_le64(dma); 1207 desc->tx.send_size = cpu_to_le16(size); 1208 desc->tx.bdtp_fe_sc_vld_ra_ri = 1209 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1210 1211 trace_hns3_tx_desc(ring, ring->next_to_use); 1212 ring_ptr_move_fw(ring, next_to_use); 1213 return HNS3_LIKELY_BD_NUM; 1214 } 1215 1216 frag_buf_num = hns3_tx_bd_count(size); 1217 sizeoflast = size % HNS3_MAX_BD_SIZE; 1218 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1219 1220 /* When frag size is bigger than hardware limit, split this frag */ 1221 for (k = 0; k < frag_buf_num; k++) { 1222 /* now, fill the descriptor */ 1223 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1224 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1225 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1226 desc->tx.bdtp_fe_sc_vld_ra_ri = 1227 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1228 1229 trace_hns3_tx_desc(ring, ring->next_to_use); 1230 /* move ring pointer to next */ 1231 ring_ptr_move_fw(ring, next_to_use); 1232 1233 desc = &ring->desc[ring->next_to_use]; 1234 } 1235 1236 return frag_buf_num; 1237 } 1238 1239 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1240 unsigned int bd_num) 1241 { 1242 unsigned int size; 1243 int i; 1244 1245 size = skb_headlen(skb); 1246 while (size > HNS3_MAX_BD_SIZE) { 1247 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1248 size -= HNS3_MAX_BD_SIZE; 1249 1250 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1251 return bd_num; 1252 } 1253 1254 if (size) { 1255 bd_size[bd_num++] = size; 1256 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1257 return bd_num; 1258 } 1259 1260 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1261 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1262 size = skb_frag_size(frag); 1263 if (!size) 1264 continue; 1265 1266 while (size > HNS3_MAX_BD_SIZE) { 1267 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1268 size -= HNS3_MAX_BD_SIZE; 1269 1270 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1271 return bd_num; 1272 } 1273 1274 bd_size[bd_num++] = size; 1275 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1276 return bd_num; 1277 } 1278 1279 return bd_num; 1280 } 1281 1282 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1283 u8 max_non_tso_bd_num, unsigned int bd_num, 1284 unsigned int recursion_level) 1285 { 1286 #define HNS3_MAX_RECURSION_LEVEL 24 1287 1288 struct sk_buff *frag_skb; 1289 1290 /* If the total len is within the max bd limit */ 1291 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level && 1292 !skb_has_frag_list(skb) && 1293 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num)) 1294 return skb_shinfo(skb)->nr_frags + 1U; 1295 1296 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL)) 1297 return UINT_MAX; 1298 1299 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num); 1300 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM) 1301 return bd_num; 1302 1303 skb_walk_frags(skb, frag_skb) { 1304 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num, 1305 bd_num, recursion_level + 1); 1306 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1307 return bd_num; 1308 } 1309 1310 return bd_num; 1311 } 1312 1313 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb) 1314 { 1315 if (!skb->encapsulation) 1316 return skb_transport_offset(skb) + tcp_hdrlen(skb); 1317 1318 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb); 1319 } 1320 1321 /* HW need every continuous max_non_tso_bd_num buffer data to be larger 1322 * than MSS, we simplify it by ensuring skb_headlen + the first continuous 1323 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss, 1324 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger 1325 * than MSS except the last max_non_tso_bd_num - 1 frags. 1326 */ 1327 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size, 1328 unsigned int bd_num, u8 max_non_tso_bd_num) 1329 { 1330 unsigned int tot_len = 0; 1331 int i; 1332 1333 for (i = 0; i < max_non_tso_bd_num - 1U; i++) 1334 tot_len += bd_size[i]; 1335 1336 /* ensure the first max_non_tso_bd_num frags is greater than 1337 * mss + header 1338 */ 1339 if (tot_len + bd_size[max_non_tso_bd_num - 1U] < 1340 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb)) 1341 return true; 1342 1343 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater 1344 * than mss except the last one. 1345 */ 1346 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) { 1347 tot_len -= bd_size[i]; 1348 tot_len += bd_size[i + max_non_tso_bd_num - 1U]; 1349 1350 if (tot_len < skb_shinfo(skb)->gso_size) 1351 return true; 1352 } 1353 1354 return false; 1355 } 1356 1357 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size) 1358 { 1359 int i; 1360 1361 for (i = 0; i < MAX_SKB_FRAGS; i++) 1362 size[i] = skb_frag_size(&shinfo->frags[i]); 1363 } 1364 1365 static int hns3_skb_linearize(struct hns3_enet_ring *ring, 1366 struct sk_buff *skb, 1367 u8 max_non_tso_bd_num, 1368 unsigned int bd_num) 1369 { 1370 /* 'bd_num == UINT_MAX' means the skb' fraglist has a 1371 * recursion level of over HNS3_MAX_RECURSION_LEVEL. 1372 */ 1373 if (bd_num == UINT_MAX) { 1374 u64_stats_update_begin(&ring->syncp); 1375 ring->stats.over_max_recursion++; 1376 u64_stats_update_end(&ring->syncp); 1377 return -ENOMEM; 1378 } 1379 1380 /* The skb->len has exceeded the hw limitation, linearization 1381 * will not help. 1382 */ 1383 if (skb->len > HNS3_MAX_TSO_SIZE || 1384 (!skb_is_gso(skb) && skb->len > 1385 HNS3_MAX_NON_TSO_SIZE(max_non_tso_bd_num))) { 1386 u64_stats_update_begin(&ring->syncp); 1387 ring->stats.hw_limitation++; 1388 u64_stats_update_end(&ring->syncp); 1389 return -ENOMEM; 1390 } 1391 1392 if (__skb_linearize(skb)) { 1393 u64_stats_update_begin(&ring->syncp); 1394 ring->stats.sw_err_cnt++; 1395 u64_stats_update_end(&ring->syncp); 1396 return -ENOMEM; 1397 } 1398 1399 return 0; 1400 } 1401 1402 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring, 1403 struct net_device *netdev, 1404 struct sk_buff *skb) 1405 { 1406 struct hns3_nic_priv *priv = netdev_priv(netdev); 1407 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num; 1408 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U]; 1409 unsigned int bd_num; 1410 1411 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0); 1412 if (unlikely(bd_num > max_non_tso_bd_num)) { 1413 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) && 1414 !hns3_skb_need_linearized(skb, bd_size, bd_num, 1415 max_non_tso_bd_num)) { 1416 trace_hns3_over_max_bd(skb); 1417 goto out; 1418 } 1419 1420 if (hns3_skb_linearize(ring, skb, max_non_tso_bd_num, 1421 bd_num)) 1422 return -ENOMEM; 1423 1424 bd_num = hns3_tx_bd_count(skb->len); 1425 1426 u64_stats_update_begin(&ring->syncp); 1427 ring->stats.tx_copy++; 1428 u64_stats_update_end(&ring->syncp); 1429 } 1430 1431 out: 1432 if (likely(ring_space(ring) >= bd_num)) 1433 return bd_num; 1434 1435 netif_stop_subqueue(netdev, ring->queue_index); 1436 smp_mb(); /* Memory barrier before checking ring_space */ 1437 1438 /* Start queue in case hns3_clean_tx_ring has just made room 1439 * available and has not seen the queue stopped state performed 1440 * by netif_stop_subqueue above. 1441 */ 1442 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) && 1443 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 1444 netif_start_subqueue(netdev, ring->queue_index); 1445 return bd_num; 1446 } 1447 1448 u64_stats_update_begin(&ring->syncp); 1449 ring->stats.tx_busy++; 1450 u64_stats_update_end(&ring->syncp); 1451 1452 return -EBUSY; 1453 } 1454 1455 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1456 { 1457 struct device *dev = ring_to_dev(ring); 1458 unsigned int i; 1459 1460 for (i = 0; i < ring->desc_num; i++) { 1461 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1462 1463 memset(desc, 0, sizeof(*desc)); 1464 1465 /* check if this is where we started */ 1466 if (ring->next_to_use == next_to_use_orig) 1467 break; 1468 1469 /* rollback one */ 1470 ring_ptr_move_bw(ring, next_to_use); 1471 1472 if (!ring->desc_cb[ring->next_to_use].dma) 1473 continue; 1474 1475 /* unmap the descriptor dma address */ 1476 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB || 1477 ring->desc_cb[ring->next_to_use].type == 1478 DESC_TYPE_FRAGLIST_SKB) 1479 dma_unmap_single(dev, 1480 ring->desc_cb[ring->next_to_use].dma, 1481 ring->desc_cb[ring->next_to_use].length, 1482 DMA_TO_DEVICE); 1483 else if (ring->desc_cb[ring->next_to_use].length) 1484 dma_unmap_page(dev, 1485 ring->desc_cb[ring->next_to_use].dma, 1486 ring->desc_cb[ring->next_to_use].length, 1487 DMA_TO_DEVICE); 1488 1489 ring->desc_cb[ring->next_to_use].length = 0; 1490 ring->desc_cb[ring->next_to_use].dma = 0; 1491 ring->desc_cb[ring->next_to_use].type = DESC_TYPE_UNKNOWN; 1492 } 1493 } 1494 1495 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring, 1496 struct sk_buff *skb, enum hns_desc_type type) 1497 { 1498 unsigned int size = skb_headlen(skb); 1499 struct sk_buff *frag_skb; 1500 int i, ret, bd_num = 0; 1501 1502 if (size) { 1503 ret = hns3_fill_desc(ring, skb, size, type); 1504 if (unlikely(ret < 0)) 1505 return ret; 1506 1507 bd_num += ret; 1508 } 1509 1510 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1511 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1512 1513 size = skb_frag_size(frag); 1514 if (!size) 1515 continue; 1516 1517 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE); 1518 if (unlikely(ret < 0)) 1519 return ret; 1520 1521 bd_num += ret; 1522 } 1523 1524 skb_walk_frags(skb, frag_skb) { 1525 ret = hns3_fill_skb_to_desc(ring, frag_skb, 1526 DESC_TYPE_FRAGLIST_SKB); 1527 if (unlikely(ret < 0)) 1528 return ret; 1529 1530 bd_num += ret; 1531 } 1532 1533 return bd_num; 1534 } 1535 1536 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num, 1537 bool doorbell) 1538 { 1539 ring->pending_buf += num; 1540 1541 if (!doorbell) { 1542 u64_stats_update_begin(&ring->syncp); 1543 ring->stats.tx_more++; 1544 u64_stats_update_end(&ring->syncp); 1545 return; 1546 } 1547 1548 if (!ring->pending_buf) 1549 return; 1550 1551 writel(ring->pending_buf, 1552 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG); 1553 ring->pending_buf = 0; 1554 WRITE_ONCE(ring->last_to_use, ring->next_to_use); 1555 } 1556 1557 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1558 { 1559 struct hns3_nic_priv *priv = netdev_priv(netdev); 1560 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping]; 1561 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1562 struct netdev_queue *dev_queue; 1563 int pre_ntu, next_to_use_head; 1564 bool doorbell; 1565 int ret; 1566 1567 /* Hardware can only handle short frames above 32 bytes */ 1568 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) { 1569 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 1570 1571 u64_stats_update_begin(&ring->syncp); 1572 ring->stats.sw_err_cnt++; 1573 u64_stats_update_end(&ring->syncp); 1574 1575 return NETDEV_TX_OK; 1576 } 1577 1578 /* Prefetch the data used later */ 1579 prefetch(skb->data); 1580 1581 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb); 1582 if (unlikely(ret <= 0)) { 1583 if (ret == -EBUSY) { 1584 hns3_tx_doorbell(ring, 0, true); 1585 return NETDEV_TX_BUSY; 1586 } 1587 1588 hns3_rl_err(netdev, "xmit error: %d!\n", ret); 1589 goto out_err_tx_ok; 1590 } 1591 1592 next_to_use_head = ring->next_to_use; 1593 1594 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use], 1595 desc_cb); 1596 if (unlikely(ret < 0)) 1597 goto fill_err; 1598 1599 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is 1600 * zero, which is unlikely, and 'ret > 0' means how many tx desc 1601 * need to be notified to the hw. 1602 */ 1603 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB); 1604 if (unlikely(ret <= 0)) 1605 goto fill_err; 1606 1607 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) : 1608 (ring->desc_num - 1); 1609 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |= 1610 cpu_to_le16(BIT(HNS3_TXD_FE_B)); 1611 trace_hns3_tx_desc(ring, pre_ntu); 1612 1613 /* Complete translate all packets */ 1614 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index); 1615 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes, 1616 netdev_xmit_more()); 1617 hns3_tx_doorbell(ring, ret, doorbell); 1618 1619 return NETDEV_TX_OK; 1620 1621 fill_err: 1622 hns3_clear_desc(ring, next_to_use_head); 1623 1624 out_err_tx_ok: 1625 dev_kfree_skb_any(skb); 1626 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 1627 return NETDEV_TX_OK; 1628 } 1629 1630 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1631 { 1632 struct hnae3_handle *h = hns3_get_handle(netdev); 1633 struct sockaddr *mac_addr = p; 1634 int ret; 1635 1636 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1637 return -EADDRNOTAVAIL; 1638 1639 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1640 netdev_info(netdev, "already using mac address %pM\n", 1641 mac_addr->sa_data); 1642 return 0; 1643 } 1644 1645 /* For VF device, if there is a perm_addr, then the user will not 1646 * be allowed to change the address. 1647 */ 1648 if (!hns3_is_phys_func(h->pdev) && 1649 !is_zero_ether_addr(netdev->perm_addr)) { 1650 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n", 1651 netdev->perm_addr, mac_addr->sa_data); 1652 return -EPERM; 1653 } 1654 1655 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1656 if (ret) { 1657 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1658 return ret; 1659 } 1660 1661 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1662 1663 return 0; 1664 } 1665 1666 static int hns3_nic_do_ioctl(struct net_device *netdev, 1667 struct ifreq *ifr, int cmd) 1668 { 1669 struct hnae3_handle *h = hns3_get_handle(netdev); 1670 1671 if (!netif_running(netdev)) 1672 return -EINVAL; 1673 1674 if (!h->ae_algo->ops->do_ioctl) 1675 return -EOPNOTSUPP; 1676 1677 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 1678 } 1679 1680 static int hns3_nic_set_features(struct net_device *netdev, 1681 netdev_features_t features) 1682 { 1683 netdev_features_t changed = netdev->features ^ features; 1684 struct hns3_nic_priv *priv = netdev_priv(netdev); 1685 struct hnae3_handle *h = priv->ae_handle; 1686 bool enable; 1687 int ret; 1688 1689 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 1690 enable = !!(features & NETIF_F_GRO_HW); 1691 ret = h->ae_algo->ops->set_gro_en(h, enable); 1692 if (ret) 1693 return ret; 1694 } 1695 1696 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1697 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1698 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 1699 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 1700 if (ret) 1701 return ret; 1702 } 1703 1704 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 1705 enable = !!(features & NETIF_F_NTUPLE); 1706 h->ae_algo->ops->enable_fd(h, enable); 1707 } 1708 1709 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) && 1710 h->ae_algo->ops->cls_flower_active(h)) { 1711 netdev_err(netdev, 1712 "there are offloaded TC filters active, cannot disable HW TC offload"); 1713 return -EINVAL; 1714 } 1715 1716 netdev->features = features; 1717 return 0; 1718 } 1719 1720 static netdev_features_t hns3_features_check(struct sk_buff *skb, 1721 struct net_device *dev, 1722 netdev_features_t features) 1723 { 1724 #define HNS3_MAX_HDR_LEN 480U 1725 #define HNS3_MAX_L4_HDR_LEN 60U 1726 1727 size_t len; 1728 1729 if (skb->ip_summed != CHECKSUM_PARTIAL) 1730 return features; 1731 1732 if (skb->encapsulation) 1733 len = skb_inner_transport_header(skb) - skb->data; 1734 else 1735 len = skb_transport_header(skb) - skb->data; 1736 1737 /* Assume L4 is 60 byte as TCP is the only protocol with a 1738 * a flexible value, and it's max len is 60 bytes. 1739 */ 1740 len += HNS3_MAX_L4_HDR_LEN; 1741 1742 /* Hardware only supports checksum on the skb with a max header 1743 * len of 480 bytes. 1744 */ 1745 if (len > HNS3_MAX_HDR_LEN) 1746 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 1747 1748 return features; 1749 } 1750 1751 static void hns3_nic_get_stats64(struct net_device *netdev, 1752 struct rtnl_link_stats64 *stats) 1753 { 1754 struct hns3_nic_priv *priv = netdev_priv(netdev); 1755 int queue_num = priv->ae_handle->kinfo.num_tqps; 1756 struct hnae3_handle *handle = priv->ae_handle; 1757 struct hns3_enet_ring *ring; 1758 u64 rx_length_errors = 0; 1759 u64 rx_crc_errors = 0; 1760 u64 rx_multicast = 0; 1761 unsigned int start; 1762 u64 tx_errors = 0; 1763 u64 rx_errors = 0; 1764 unsigned int idx; 1765 u64 tx_bytes = 0; 1766 u64 rx_bytes = 0; 1767 u64 tx_pkts = 0; 1768 u64 rx_pkts = 0; 1769 u64 tx_drop = 0; 1770 u64 rx_drop = 0; 1771 1772 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1773 return; 1774 1775 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1776 1777 for (idx = 0; idx < queue_num; idx++) { 1778 /* fetch the tx stats */ 1779 ring = &priv->ring[idx]; 1780 do { 1781 start = u64_stats_fetch_begin_irq(&ring->syncp); 1782 tx_bytes += ring->stats.tx_bytes; 1783 tx_pkts += ring->stats.tx_pkts; 1784 tx_drop += ring->stats.sw_err_cnt; 1785 tx_drop += ring->stats.tx_vlan_err; 1786 tx_drop += ring->stats.tx_l4_proto_err; 1787 tx_drop += ring->stats.tx_l2l3l4_err; 1788 tx_drop += ring->stats.tx_tso_err; 1789 tx_drop += ring->stats.over_max_recursion; 1790 tx_drop += ring->stats.hw_limitation; 1791 tx_errors += ring->stats.sw_err_cnt; 1792 tx_errors += ring->stats.tx_vlan_err; 1793 tx_errors += ring->stats.tx_l4_proto_err; 1794 tx_errors += ring->stats.tx_l2l3l4_err; 1795 tx_errors += ring->stats.tx_tso_err; 1796 tx_errors += ring->stats.over_max_recursion; 1797 tx_errors += ring->stats.hw_limitation; 1798 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1799 1800 /* fetch the rx stats */ 1801 ring = &priv->ring[idx + queue_num]; 1802 do { 1803 start = u64_stats_fetch_begin_irq(&ring->syncp); 1804 rx_bytes += ring->stats.rx_bytes; 1805 rx_pkts += ring->stats.rx_pkts; 1806 rx_drop += ring->stats.l2_err; 1807 rx_errors += ring->stats.l2_err; 1808 rx_errors += ring->stats.l3l4_csum_err; 1809 rx_crc_errors += ring->stats.l2_err; 1810 rx_multicast += ring->stats.rx_multicast; 1811 rx_length_errors += ring->stats.err_pkt_len; 1812 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1813 } 1814 1815 stats->tx_bytes = tx_bytes; 1816 stats->tx_packets = tx_pkts; 1817 stats->rx_bytes = rx_bytes; 1818 stats->rx_packets = rx_pkts; 1819 1820 stats->rx_errors = rx_errors; 1821 stats->multicast = rx_multicast; 1822 stats->rx_length_errors = rx_length_errors; 1823 stats->rx_crc_errors = rx_crc_errors; 1824 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1825 1826 stats->tx_errors = tx_errors; 1827 stats->rx_dropped = rx_drop; 1828 stats->tx_dropped = tx_drop; 1829 stats->collisions = netdev->stats.collisions; 1830 stats->rx_over_errors = netdev->stats.rx_over_errors; 1831 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1832 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1833 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1834 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1835 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1836 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1837 stats->tx_window_errors = netdev->stats.tx_window_errors; 1838 stats->rx_compressed = netdev->stats.rx_compressed; 1839 stats->tx_compressed = netdev->stats.tx_compressed; 1840 } 1841 1842 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1843 { 1844 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1845 struct hnae3_knic_private_info *kinfo; 1846 u8 tc = mqprio_qopt->qopt.num_tc; 1847 u16 mode = mqprio_qopt->mode; 1848 u8 hw = mqprio_qopt->qopt.hw; 1849 struct hnae3_handle *h; 1850 1851 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1852 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1853 return -EOPNOTSUPP; 1854 1855 if (tc > HNAE3_MAX_TC) 1856 return -EINVAL; 1857 1858 if (!netdev) 1859 return -EINVAL; 1860 1861 h = hns3_get_handle(netdev); 1862 kinfo = &h->kinfo; 1863 1864 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc); 1865 1866 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1867 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP; 1868 } 1869 1870 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv, 1871 struct flow_cls_offload *flow) 1872 { 1873 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid); 1874 struct hnae3_handle *h = hns3_get_handle(priv->netdev); 1875 1876 switch (flow->command) { 1877 case FLOW_CLS_REPLACE: 1878 if (h->ae_algo->ops->add_cls_flower) 1879 return h->ae_algo->ops->add_cls_flower(h, flow, tc); 1880 break; 1881 case FLOW_CLS_DESTROY: 1882 if (h->ae_algo->ops->del_cls_flower) 1883 return h->ae_algo->ops->del_cls_flower(h, flow); 1884 break; 1885 default: 1886 break; 1887 } 1888 1889 return -EOPNOTSUPP; 1890 } 1891 1892 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 1893 void *cb_priv) 1894 { 1895 struct hns3_nic_priv *priv = cb_priv; 1896 1897 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data)) 1898 return -EOPNOTSUPP; 1899 1900 switch (type) { 1901 case TC_SETUP_CLSFLOWER: 1902 return hns3_setup_tc_cls_flower(priv, type_data); 1903 default: 1904 return -EOPNOTSUPP; 1905 } 1906 } 1907 1908 static LIST_HEAD(hns3_block_cb_list); 1909 1910 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1911 void *type_data) 1912 { 1913 struct hns3_nic_priv *priv = netdev_priv(dev); 1914 int ret; 1915 1916 switch (type) { 1917 case TC_SETUP_QDISC_MQPRIO: 1918 ret = hns3_setup_tc(dev, type_data); 1919 break; 1920 case TC_SETUP_BLOCK: 1921 ret = flow_block_cb_setup_simple(type_data, 1922 &hns3_block_cb_list, 1923 hns3_setup_tc_block_cb, 1924 priv, priv, true); 1925 break; 1926 default: 1927 return -EOPNOTSUPP; 1928 } 1929 1930 return ret; 1931 } 1932 1933 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1934 __be16 proto, u16 vid) 1935 { 1936 struct hnae3_handle *h = hns3_get_handle(netdev); 1937 int ret = -EIO; 1938 1939 if (h->ae_algo->ops->set_vlan_filter) 1940 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1941 1942 return ret; 1943 } 1944 1945 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1946 __be16 proto, u16 vid) 1947 { 1948 struct hnae3_handle *h = hns3_get_handle(netdev); 1949 int ret = -EIO; 1950 1951 if (h->ae_algo->ops->set_vlan_filter) 1952 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1953 1954 return ret; 1955 } 1956 1957 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1958 u8 qos, __be16 vlan_proto) 1959 { 1960 struct hnae3_handle *h = hns3_get_handle(netdev); 1961 int ret = -EIO; 1962 1963 netif_dbg(h, drv, netdev, 1964 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n", 1965 vf, vlan, qos, ntohs(vlan_proto)); 1966 1967 if (h->ae_algo->ops->set_vf_vlan_filter) 1968 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1969 qos, vlan_proto); 1970 1971 return ret; 1972 } 1973 1974 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable) 1975 { 1976 struct hnae3_handle *handle = hns3_get_handle(netdev); 1977 1978 if (hns3_nic_resetting(netdev)) 1979 return -EBUSY; 1980 1981 if (!handle->ae_algo->ops->set_vf_spoofchk) 1982 return -EOPNOTSUPP; 1983 1984 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable); 1985 } 1986 1987 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable) 1988 { 1989 struct hnae3_handle *handle = hns3_get_handle(netdev); 1990 1991 if (!handle->ae_algo->ops->set_vf_trust) 1992 return -EOPNOTSUPP; 1993 1994 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable); 1995 } 1996 1997 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1998 { 1999 struct hnae3_handle *h = hns3_get_handle(netdev); 2000 int ret; 2001 2002 if (hns3_nic_resetting(netdev)) 2003 return -EBUSY; 2004 2005 if (!h->ae_algo->ops->set_mtu) 2006 return -EOPNOTSUPP; 2007 2008 netif_dbg(h, drv, netdev, 2009 "change mtu from %u to %d\n", netdev->mtu, new_mtu); 2010 2011 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 2012 if (ret) 2013 netdev_err(netdev, "failed to change MTU in hardware %d\n", 2014 ret); 2015 else 2016 netdev->mtu = new_mtu; 2017 2018 return ret; 2019 } 2020 2021 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 2022 { 2023 struct hns3_nic_priv *priv = netdev_priv(ndev); 2024 struct hnae3_handle *h = hns3_get_handle(ndev); 2025 struct hns3_enet_ring *tx_ring; 2026 struct napi_struct *napi; 2027 int timeout_queue = 0; 2028 int hw_head, hw_tail; 2029 int fbd_num, fbd_oft; 2030 int ebd_num, ebd_oft; 2031 int bd_num, bd_err; 2032 int ring_en, tc; 2033 int i; 2034 2035 /* Find the stopped queue the same way the stack does */ 2036 for (i = 0; i < ndev->num_tx_queues; i++) { 2037 struct netdev_queue *q; 2038 unsigned long trans_start; 2039 2040 q = netdev_get_tx_queue(ndev, i); 2041 trans_start = q->trans_start; 2042 if (netif_xmit_stopped(q) && 2043 time_after(jiffies, 2044 (trans_start + ndev->watchdog_timeo))) { 2045 timeout_queue = i; 2046 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n", 2047 q->state, 2048 jiffies_to_msecs(jiffies - trans_start)); 2049 break; 2050 } 2051 } 2052 2053 if (i == ndev->num_tx_queues) { 2054 netdev_info(ndev, 2055 "no netdev TX timeout queue found, timeout count: %llu\n", 2056 priv->tx_timeout_count); 2057 return false; 2058 } 2059 2060 priv->tx_timeout_count++; 2061 2062 tx_ring = &priv->ring[timeout_queue]; 2063 napi = &tx_ring->tqp_vector->napi; 2064 2065 netdev_info(ndev, 2066 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n", 2067 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use, 2068 tx_ring->next_to_clean, napi->state); 2069 2070 netdev_info(ndev, 2071 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n", 2072 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes, 2073 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf); 2074 2075 netdev_info(ndev, 2076 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n", 2077 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more, 2078 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy); 2079 2080 /* When mac received many pause frames continuous, it's unable to send 2081 * packets, which may cause tx timeout 2082 */ 2083 if (h->ae_algo->ops->get_mac_stats) { 2084 struct hns3_mac_stats mac_stats; 2085 2086 h->ae_algo->ops->get_mac_stats(h, &mac_stats); 2087 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n", 2088 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt); 2089 } 2090 2091 hw_head = readl_relaxed(tx_ring->tqp->io_base + 2092 HNS3_RING_TX_RING_HEAD_REG); 2093 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 2094 HNS3_RING_TX_RING_TAIL_REG); 2095 fbd_num = readl_relaxed(tx_ring->tqp->io_base + 2096 HNS3_RING_TX_RING_FBDNUM_REG); 2097 fbd_oft = readl_relaxed(tx_ring->tqp->io_base + 2098 HNS3_RING_TX_RING_OFFSET_REG); 2099 ebd_num = readl_relaxed(tx_ring->tqp->io_base + 2100 HNS3_RING_TX_RING_EBDNUM_REG); 2101 ebd_oft = readl_relaxed(tx_ring->tqp->io_base + 2102 HNS3_RING_TX_RING_EBD_OFFSET_REG); 2103 bd_num = readl_relaxed(tx_ring->tqp->io_base + 2104 HNS3_RING_TX_RING_BD_NUM_REG); 2105 bd_err = readl_relaxed(tx_ring->tqp->io_base + 2106 HNS3_RING_TX_RING_BD_ERR_REG); 2107 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG); 2108 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG); 2109 2110 netdev_info(ndev, 2111 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n", 2112 bd_num, hw_head, hw_tail, bd_err, 2113 readl(tx_ring->tqp_vector->mask_addr)); 2114 netdev_info(ndev, 2115 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n", 2116 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft); 2117 2118 return true; 2119 } 2120 2121 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue) 2122 { 2123 struct hns3_nic_priv *priv = netdev_priv(ndev); 2124 struct hnae3_handle *h = priv->ae_handle; 2125 2126 if (!hns3_get_tx_timeo_queue_info(ndev)) 2127 return; 2128 2129 /* request the reset, and let the hclge to determine 2130 * which reset level should be done 2131 */ 2132 if (h->ae_algo->ops->reset_event) 2133 h->ae_algo->ops->reset_event(h->pdev, h); 2134 } 2135 2136 #ifdef CONFIG_RFS_ACCEL 2137 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 2138 u16 rxq_index, u32 flow_id) 2139 { 2140 struct hnae3_handle *h = hns3_get_handle(dev); 2141 struct flow_keys fkeys; 2142 2143 if (!h->ae_algo->ops->add_arfs_entry) 2144 return -EOPNOTSUPP; 2145 2146 if (skb->encapsulation) 2147 return -EPROTONOSUPPORT; 2148 2149 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0)) 2150 return -EPROTONOSUPPORT; 2151 2152 if ((fkeys.basic.n_proto != htons(ETH_P_IP) && 2153 fkeys.basic.n_proto != htons(ETH_P_IPV6)) || 2154 (fkeys.basic.ip_proto != IPPROTO_TCP && 2155 fkeys.basic.ip_proto != IPPROTO_UDP)) 2156 return -EPROTONOSUPPORT; 2157 2158 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys); 2159 } 2160 #endif 2161 2162 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf, 2163 struct ifla_vf_info *ivf) 2164 { 2165 struct hnae3_handle *h = hns3_get_handle(ndev); 2166 2167 if (!h->ae_algo->ops->get_vf_config) 2168 return -EOPNOTSUPP; 2169 2170 return h->ae_algo->ops->get_vf_config(h, vf, ivf); 2171 } 2172 2173 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf, 2174 int link_state) 2175 { 2176 struct hnae3_handle *h = hns3_get_handle(ndev); 2177 2178 if (!h->ae_algo->ops->set_vf_link_state) 2179 return -EOPNOTSUPP; 2180 2181 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state); 2182 } 2183 2184 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf, 2185 int min_tx_rate, int max_tx_rate) 2186 { 2187 struct hnae3_handle *h = hns3_get_handle(ndev); 2188 2189 if (!h->ae_algo->ops->set_vf_rate) 2190 return -EOPNOTSUPP; 2191 2192 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate, 2193 false); 2194 } 2195 2196 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) 2197 { 2198 struct hnae3_handle *h = hns3_get_handle(netdev); 2199 2200 if (!h->ae_algo->ops->set_vf_mac) 2201 return -EOPNOTSUPP; 2202 2203 if (is_multicast_ether_addr(mac)) { 2204 netdev_err(netdev, 2205 "Invalid MAC:%pM specified. Could not set MAC\n", 2206 mac); 2207 return -EINVAL; 2208 } 2209 2210 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac); 2211 } 2212 2213 static const struct net_device_ops hns3_nic_netdev_ops = { 2214 .ndo_open = hns3_nic_net_open, 2215 .ndo_stop = hns3_nic_net_stop, 2216 .ndo_start_xmit = hns3_nic_net_xmit, 2217 .ndo_tx_timeout = hns3_nic_net_timeout, 2218 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 2219 .ndo_do_ioctl = hns3_nic_do_ioctl, 2220 .ndo_change_mtu = hns3_nic_change_mtu, 2221 .ndo_set_features = hns3_nic_set_features, 2222 .ndo_features_check = hns3_features_check, 2223 .ndo_get_stats64 = hns3_nic_get_stats64, 2224 .ndo_setup_tc = hns3_nic_setup_tc, 2225 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 2226 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 2227 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 2228 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 2229 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk, 2230 .ndo_set_vf_trust = hns3_set_vf_trust, 2231 #ifdef CONFIG_RFS_ACCEL 2232 .ndo_rx_flow_steer = hns3_rx_flow_steer, 2233 #endif 2234 .ndo_get_vf_config = hns3_nic_get_vf_config, 2235 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state, 2236 .ndo_set_vf_rate = hns3_nic_set_vf_rate, 2237 .ndo_set_vf_mac = hns3_nic_set_vf_mac, 2238 }; 2239 2240 bool hns3_is_phys_func(struct pci_dev *pdev) 2241 { 2242 u32 dev_id = pdev->device; 2243 2244 switch (dev_id) { 2245 case HNAE3_DEV_ID_GE: 2246 case HNAE3_DEV_ID_25GE: 2247 case HNAE3_DEV_ID_25GE_RDMA: 2248 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 2249 case HNAE3_DEV_ID_50GE_RDMA: 2250 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 2251 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 2252 case HNAE3_DEV_ID_200G_RDMA: 2253 return true; 2254 case HNAE3_DEV_ID_VF: 2255 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF: 2256 return false; 2257 default: 2258 dev_warn(&pdev->dev, "un-recognized pci device-id %u", 2259 dev_id); 2260 } 2261 2262 return false; 2263 } 2264 2265 static void hns3_disable_sriov(struct pci_dev *pdev) 2266 { 2267 /* If our VFs are assigned we cannot shut down SR-IOV 2268 * without causing issues, so just leave the hardware 2269 * available but disabled 2270 */ 2271 if (pci_vfs_assigned(pdev)) { 2272 dev_warn(&pdev->dev, 2273 "disabling driver while VFs are assigned\n"); 2274 return; 2275 } 2276 2277 pci_disable_sriov(pdev); 2278 } 2279 2280 /* hns3_probe - Device initialization routine 2281 * @pdev: PCI device information struct 2282 * @ent: entry in hns3_pci_tbl 2283 * 2284 * hns3_probe initializes a PF identified by a pci_dev structure. 2285 * The OS initialization, configuring of the PF private structure, 2286 * and a hardware reset occur. 2287 * 2288 * Returns 0 on success, negative on failure 2289 */ 2290 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2291 { 2292 struct hnae3_ae_dev *ae_dev; 2293 int ret; 2294 2295 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL); 2296 if (!ae_dev) 2297 return -ENOMEM; 2298 2299 ae_dev->pdev = pdev; 2300 ae_dev->flag = ent->driver_data; 2301 pci_set_drvdata(pdev, ae_dev); 2302 2303 ret = hnae3_register_ae_dev(ae_dev); 2304 if (ret) 2305 pci_set_drvdata(pdev, NULL); 2306 2307 return ret; 2308 } 2309 2310 /* hns3_remove - Device removal routine 2311 * @pdev: PCI device information struct 2312 */ 2313 static void hns3_remove(struct pci_dev *pdev) 2314 { 2315 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2316 2317 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 2318 hns3_disable_sriov(pdev); 2319 2320 hnae3_unregister_ae_dev(ae_dev); 2321 pci_set_drvdata(pdev, NULL); 2322 } 2323 2324 /** 2325 * hns3_pci_sriov_configure 2326 * @pdev: pointer to a pci_dev structure 2327 * @num_vfs: number of VFs to allocate 2328 * 2329 * Enable or change the number of VFs. Called when the user updates the number 2330 * of VFs in sysfs. 2331 **/ 2332 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 2333 { 2334 int ret; 2335 2336 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 2337 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 2338 return -EINVAL; 2339 } 2340 2341 if (num_vfs) { 2342 ret = pci_enable_sriov(pdev, num_vfs); 2343 if (ret) 2344 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 2345 else 2346 return num_vfs; 2347 } else if (!pci_vfs_assigned(pdev)) { 2348 pci_disable_sriov(pdev); 2349 } else { 2350 dev_warn(&pdev->dev, 2351 "Unable to free VFs because some are assigned to VMs.\n"); 2352 } 2353 2354 return 0; 2355 } 2356 2357 static void hns3_shutdown(struct pci_dev *pdev) 2358 { 2359 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2360 2361 hnae3_unregister_ae_dev(ae_dev); 2362 pci_set_drvdata(pdev, NULL); 2363 2364 if (system_state == SYSTEM_POWER_OFF) 2365 pci_set_power_state(pdev, PCI_D3hot); 2366 } 2367 2368 static int __maybe_unused hns3_suspend(struct device *dev) 2369 { 2370 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev); 2371 2372 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) { 2373 dev_info(dev, "Begin to suspend.\n"); 2374 if (ae_dev->ops && ae_dev->ops->reset_prepare) 2375 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET); 2376 } 2377 2378 return 0; 2379 } 2380 2381 static int __maybe_unused hns3_resume(struct device *dev) 2382 { 2383 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev); 2384 2385 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) { 2386 dev_info(dev, "Begin to resume.\n"); 2387 if (ae_dev->ops && ae_dev->ops->reset_done) 2388 ae_dev->ops->reset_done(ae_dev); 2389 } 2390 2391 return 0; 2392 } 2393 2394 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 2395 pci_channel_state_t state) 2396 { 2397 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2398 pci_ers_result_t ret; 2399 2400 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state); 2401 2402 if (state == pci_channel_io_perm_failure) 2403 return PCI_ERS_RESULT_DISCONNECT; 2404 2405 if (!ae_dev || !ae_dev->ops) { 2406 dev_err(&pdev->dev, 2407 "Can't recover - error happened before device initialized\n"); 2408 return PCI_ERS_RESULT_NONE; 2409 } 2410 2411 if (ae_dev->ops->handle_hw_ras_error) 2412 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 2413 else 2414 return PCI_ERS_RESULT_NONE; 2415 2416 return ret; 2417 } 2418 2419 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 2420 { 2421 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2422 const struct hnae3_ae_ops *ops; 2423 enum hnae3_reset_type reset_type; 2424 struct device *dev = &pdev->dev; 2425 2426 if (!ae_dev || !ae_dev->ops) 2427 return PCI_ERS_RESULT_NONE; 2428 2429 ops = ae_dev->ops; 2430 /* request the reset */ 2431 if (ops->reset_event && ops->get_reset_level && 2432 ops->set_default_reset_request) { 2433 if (ae_dev->hw_err_reset_req) { 2434 reset_type = ops->get_reset_level(ae_dev, 2435 &ae_dev->hw_err_reset_req); 2436 ops->set_default_reset_request(ae_dev, reset_type); 2437 dev_info(dev, "requesting reset due to PCI error\n"); 2438 ops->reset_event(pdev, NULL); 2439 } 2440 2441 return PCI_ERS_RESULT_RECOVERED; 2442 } 2443 2444 return PCI_ERS_RESULT_DISCONNECT; 2445 } 2446 2447 static void hns3_reset_prepare(struct pci_dev *pdev) 2448 { 2449 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2450 2451 dev_info(&pdev->dev, "FLR prepare\n"); 2452 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare) 2453 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET); 2454 } 2455 2456 static void hns3_reset_done(struct pci_dev *pdev) 2457 { 2458 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2459 2460 dev_info(&pdev->dev, "FLR done\n"); 2461 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done) 2462 ae_dev->ops->reset_done(ae_dev); 2463 } 2464 2465 static const struct pci_error_handlers hns3_err_handler = { 2466 .error_detected = hns3_error_detected, 2467 .slot_reset = hns3_slot_reset, 2468 .reset_prepare = hns3_reset_prepare, 2469 .reset_done = hns3_reset_done, 2470 }; 2471 2472 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume); 2473 2474 static struct pci_driver hns3_driver = { 2475 .name = hns3_driver_name, 2476 .id_table = hns3_pci_tbl, 2477 .probe = hns3_probe, 2478 .remove = hns3_remove, 2479 .shutdown = hns3_shutdown, 2480 .driver.pm = &hns3_pm_ops, 2481 .sriov_configure = hns3_pci_sriov_configure, 2482 .err_handler = &hns3_err_handler, 2483 }; 2484 2485 /* set default feature to hns3 */ 2486 static void hns3_set_default_feature(struct net_device *netdev) 2487 { 2488 struct hnae3_handle *h = hns3_get_handle(netdev); 2489 struct pci_dev *pdev = h->pdev; 2490 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2491 2492 netdev->priv_flags |= IFF_UNICAST_FLT; 2493 2494 netdev->hw_enc_features |= NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2495 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2496 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2497 NETIF_F_SCTP_CRC | NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST; 2498 2499 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 2500 2501 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 2502 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2503 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2504 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2505 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2506 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 2507 2508 netdev->vlan_features |= NETIF_F_RXCSUM | 2509 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 2510 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2511 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2512 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 2513 2514 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 2515 NETIF_F_HW_VLAN_CTAG_RX | 2516 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2517 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2518 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2519 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 2520 2521 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2522 netdev->hw_features |= NETIF_F_GRO_HW; 2523 netdev->features |= NETIF_F_GRO_HW; 2524 2525 if (!(h->flags & HNAE3_SUPPORT_VF)) { 2526 netdev->hw_features |= NETIF_F_NTUPLE; 2527 netdev->features |= NETIF_F_NTUPLE; 2528 } 2529 } 2530 2531 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps)) { 2532 netdev->hw_features |= NETIF_F_GSO_UDP_L4; 2533 netdev->features |= NETIF_F_GSO_UDP_L4; 2534 netdev->vlan_features |= NETIF_F_GSO_UDP_L4; 2535 netdev->hw_enc_features |= NETIF_F_GSO_UDP_L4; 2536 } 2537 2538 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) { 2539 netdev->hw_features |= NETIF_F_HW_CSUM; 2540 netdev->features |= NETIF_F_HW_CSUM; 2541 netdev->vlan_features |= NETIF_F_HW_CSUM; 2542 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 2543 } else { 2544 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2545 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2546 netdev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2547 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2548 } 2549 2550 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps)) { 2551 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 2552 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 2553 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 2554 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 2555 } 2556 2557 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) { 2558 netdev->hw_features |= NETIF_F_HW_TC; 2559 netdev->features |= NETIF_F_HW_TC; 2560 } 2561 } 2562 2563 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 2564 struct hns3_desc_cb *cb) 2565 { 2566 unsigned int order = hns3_page_order(ring); 2567 struct page *p; 2568 2569 p = dev_alloc_pages(order); 2570 if (!p) 2571 return -ENOMEM; 2572 2573 cb->priv = p; 2574 cb->page_offset = 0; 2575 cb->reuse_flag = 0; 2576 cb->buf = page_address(p); 2577 cb->length = hns3_page_size(ring); 2578 cb->type = DESC_TYPE_PAGE; 2579 page_ref_add(p, USHRT_MAX - 1); 2580 cb->pagecnt_bias = USHRT_MAX; 2581 2582 return 0; 2583 } 2584 2585 static void hns3_free_buffer(struct hns3_enet_ring *ring, 2586 struct hns3_desc_cb *cb, int budget) 2587 { 2588 if (cb->type == DESC_TYPE_SKB) 2589 napi_consume_skb(cb->priv, budget); 2590 else if (!HNAE3_IS_TX_RING(ring) && cb->pagecnt_bias) 2591 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias); 2592 memset(cb, 0, sizeof(*cb)); 2593 } 2594 2595 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 2596 { 2597 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 2598 cb->length, ring_to_dma_dir(ring)); 2599 2600 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 2601 return -EIO; 2602 2603 return 0; 2604 } 2605 2606 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 2607 struct hns3_desc_cb *cb) 2608 { 2609 if (cb->type == DESC_TYPE_SKB || cb->type == DESC_TYPE_FRAGLIST_SKB) 2610 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 2611 ring_to_dma_dir(ring)); 2612 else if (cb->length) 2613 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 2614 ring_to_dma_dir(ring)); 2615 } 2616 2617 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 2618 { 2619 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2620 ring->desc[i].addr = 0; 2621 } 2622 2623 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i, 2624 int budget) 2625 { 2626 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 2627 2628 if (!ring->desc_cb[i].dma) 2629 return; 2630 2631 hns3_buffer_detach(ring, i); 2632 hns3_free_buffer(ring, cb, budget); 2633 } 2634 2635 static void hns3_free_buffers(struct hns3_enet_ring *ring) 2636 { 2637 int i; 2638 2639 for (i = 0; i < ring->desc_num; i++) 2640 hns3_free_buffer_detach(ring, i, 0); 2641 } 2642 2643 /* free desc along with its attached buffer */ 2644 static void hns3_free_desc(struct hns3_enet_ring *ring) 2645 { 2646 int size = ring->desc_num * sizeof(ring->desc[0]); 2647 2648 hns3_free_buffers(ring); 2649 2650 if (ring->desc) { 2651 dma_free_coherent(ring_to_dev(ring), size, 2652 ring->desc, ring->desc_dma_addr); 2653 ring->desc = NULL; 2654 } 2655 } 2656 2657 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 2658 { 2659 int size = ring->desc_num * sizeof(ring->desc[0]); 2660 2661 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 2662 &ring->desc_dma_addr, GFP_KERNEL); 2663 if (!ring->desc) 2664 return -ENOMEM; 2665 2666 return 0; 2667 } 2668 2669 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring, 2670 struct hns3_desc_cb *cb) 2671 { 2672 int ret; 2673 2674 ret = hns3_alloc_buffer(ring, cb); 2675 if (ret) 2676 goto out; 2677 2678 ret = hns3_map_buffer(ring, cb); 2679 if (ret) 2680 goto out_with_buf; 2681 2682 return 0; 2683 2684 out_with_buf: 2685 hns3_free_buffer(ring, cb, 0); 2686 out: 2687 return ret; 2688 } 2689 2690 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i) 2691 { 2692 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]); 2693 2694 if (ret) 2695 return ret; 2696 2697 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2698 2699 return 0; 2700 } 2701 2702 /* Allocate memory for raw pkg, and map with dma */ 2703 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 2704 { 2705 int i, j, ret; 2706 2707 for (i = 0; i < ring->desc_num; i++) { 2708 ret = hns3_alloc_and_attach_buffer(ring, i); 2709 if (ret) 2710 goto out_buffer_fail; 2711 } 2712 2713 return 0; 2714 2715 out_buffer_fail: 2716 for (j = i - 1; j >= 0; j--) 2717 hns3_free_buffer_detach(ring, j, 0); 2718 return ret; 2719 } 2720 2721 /* detach a in-used buffer and replace with a reserved one */ 2722 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 2723 struct hns3_desc_cb *res_cb) 2724 { 2725 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2726 ring->desc_cb[i] = *res_cb; 2727 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2728 ring->desc[i].rx.bd_base_info = 0; 2729 } 2730 2731 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 2732 { 2733 ring->desc_cb[i].reuse_flag = 0; 2734 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 2735 ring->desc_cb[i].page_offset); 2736 ring->desc[i].rx.bd_base_info = 0; 2737 2738 dma_sync_single_for_device(ring_to_dev(ring), 2739 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset, 2740 hns3_buf_size(ring), 2741 DMA_FROM_DEVICE); 2742 } 2743 2744 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, 2745 int *bytes, int *pkts, int budget) 2746 { 2747 /* pair with ring->last_to_use update in hns3_tx_doorbell(), 2748 * smp_store_release() is not used in hns3_tx_doorbell() because 2749 * the doorbell operation already have the needed barrier operation. 2750 */ 2751 int ltu = smp_load_acquire(&ring->last_to_use); 2752 int ntc = ring->next_to_clean; 2753 struct hns3_desc_cb *desc_cb; 2754 bool reclaimed = false; 2755 struct hns3_desc *desc; 2756 2757 while (ltu != ntc) { 2758 desc = &ring->desc[ntc]; 2759 2760 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) & 2761 BIT(HNS3_TXD_VLD_B)) 2762 break; 2763 2764 desc_cb = &ring->desc_cb[ntc]; 2765 2766 if (desc_cb->type == DESC_TYPE_SKB) { 2767 (*pkts)++; 2768 (*bytes) += desc_cb->send_bytes; 2769 } 2770 2771 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */ 2772 hns3_free_buffer_detach(ring, ntc, budget); 2773 2774 if (++ntc == ring->desc_num) 2775 ntc = 0; 2776 2777 /* Issue prefetch for next Tx descriptor */ 2778 prefetch(&ring->desc_cb[ntc]); 2779 reclaimed = true; 2780 } 2781 2782 if (unlikely(!reclaimed)) 2783 return false; 2784 2785 /* This smp_store_release() pairs with smp_load_acquire() in 2786 * ring_space called by hns3_nic_net_xmit. 2787 */ 2788 smp_store_release(&ring->next_to_clean, ntc); 2789 return true; 2790 } 2791 2792 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget) 2793 { 2794 struct net_device *netdev = ring_to_netdev(ring); 2795 struct hns3_nic_priv *priv = netdev_priv(netdev); 2796 struct netdev_queue *dev_queue; 2797 int bytes, pkts; 2798 2799 bytes = 0; 2800 pkts = 0; 2801 2802 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget))) 2803 return; 2804 2805 ring->tqp_vector->tx_group.total_bytes += bytes; 2806 ring->tqp_vector->tx_group.total_packets += pkts; 2807 2808 u64_stats_update_begin(&ring->syncp); 2809 ring->stats.tx_bytes += bytes; 2810 ring->stats.tx_pkts += pkts; 2811 u64_stats_update_end(&ring->syncp); 2812 2813 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 2814 netdev_tx_completed_queue(dev_queue, pkts, bytes); 2815 2816 if (unlikely(netif_carrier_ok(netdev) && 2817 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) { 2818 /* Make sure that anybody stopping the queue after this 2819 * sees the new next_to_clean. 2820 */ 2821 smp_mb(); 2822 if (netif_tx_queue_stopped(dev_queue) && 2823 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 2824 netif_tx_wake_queue(dev_queue); 2825 ring->stats.restart_queue++; 2826 } 2827 } 2828 } 2829 2830 static int hns3_desc_unused(struct hns3_enet_ring *ring) 2831 { 2832 int ntc = ring->next_to_clean; 2833 int ntu = ring->next_to_use; 2834 2835 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 2836 } 2837 2838 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, 2839 int cleand_count) 2840 { 2841 struct hns3_desc_cb *desc_cb; 2842 struct hns3_desc_cb res_cbs; 2843 int i, ret; 2844 2845 for (i = 0; i < cleand_count; i++) { 2846 desc_cb = &ring->desc_cb[ring->next_to_use]; 2847 if (desc_cb->reuse_flag) { 2848 u64_stats_update_begin(&ring->syncp); 2849 ring->stats.reuse_pg_cnt++; 2850 u64_stats_update_end(&ring->syncp); 2851 2852 hns3_reuse_buffer(ring, ring->next_to_use); 2853 } else { 2854 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 2855 if (ret) { 2856 u64_stats_update_begin(&ring->syncp); 2857 ring->stats.sw_err_cnt++; 2858 u64_stats_update_end(&ring->syncp); 2859 2860 hns3_rl_err(ring_to_netdev(ring), 2861 "alloc rx buffer failed: %d\n", 2862 ret); 2863 break; 2864 } 2865 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 2866 2867 u64_stats_update_begin(&ring->syncp); 2868 ring->stats.non_reuse_pg++; 2869 u64_stats_update_end(&ring->syncp); 2870 } 2871 2872 ring_ptr_move_fw(ring, next_to_use); 2873 } 2874 2875 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2876 } 2877 2878 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb) 2879 { 2880 return (page_count(cb->priv) - cb->pagecnt_bias) == 1; 2881 } 2882 2883 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2884 struct hns3_enet_ring *ring, int pull_len, 2885 struct hns3_desc_cb *desc_cb) 2886 { 2887 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 2888 int size = le16_to_cpu(desc->rx.size); 2889 u32 truesize = hns3_buf_size(ring); 2890 2891 desc_cb->pagecnt_bias--; 2892 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2893 size - pull_len, truesize); 2894 2895 /* Avoid re-using remote and pfmemalloc pages, or the stack is still 2896 * using the page when page_offset rollback to zero, flag default 2897 * unreuse 2898 */ 2899 if (!dev_page_is_reusable(desc_cb->priv) || 2900 (!desc_cb->page_offset && !hns3_can_reuse_page(desc_cb))) { 2901 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias); 2902 return; 2903 } 2904 2905 /* Move offset up to the next cache line */ 2906 desc_cb->page_offset += truesize; 2907 2908 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) { 2909 desc_cb->reuse_flag = 1; 2910 } else if (hns3_can_reuse_page(desc_cb)) { 2911 desc_cb->reuse_flag = 1; 2912 desc_cb->page_offset = 0; 2913 } else if (desc_cb->pagecnt_bias) { 2914 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias); 2915 return; 2916 } 2917 2918 if (unlikely(!desc_cb->pagecnt_bias)) { 2919 page_ref_add(desc_cb->priv, USHRT_MAX); 2920 desc_cb->pagecnt_bias = USHRT_MAX; 2921 } 2922 } 2923 2924 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) 2925 { 2926 __be16 type = skb->protocol; 2927 struct tcphdr *th; 2928 int depth = 0; 2929 2930 while (eth_type_vlan(type)) { 2931 struct vlan_hdr *vh; 2932 2933 if ((depth + VLAN_HLEN) > skb_headlen(skb)) 2934 return -EFAULT; 2935 2936 vh = (struct vlan_hdr *)(skb->data + depth); 2937 type = vh->h_vlan_encapsulated_proto; 2938 depth += VLAN_HLEN; 2939 } 2940 2941 skb_set_network_header(skb, depth); 2942 2943 if (type == htons(ETH_P_IP)) { 2944 const struct iphdr *iph = ip_hdr(skb); 2945 2946 depth += sizeof(struct iphdr); 2947 skb_set_transport_header(skb, depth); 2948 th = tcp_hdr(skb); 2949 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr, 2950 iph->daddr, 0); 2951 } else if (type == htons(ETH_P_IPV6)) { 2952 const struct ipv6hdr *iph = ipv6_hdr(skb); 2953 2954 depth += sizeof(struct ipv6hdr); 2955 skb_set_transport_header(skb, depth); 2956 th = tcp_hdr(skb); 2957 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr, 2958 &iph->daddr, 0); 2959 } else { 2960 hns3_rl_err(skb->dev, 2961 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n", 2962 be16_to_cpu(type), depth); 2963 return -EFAULT; 2964 } 2965 2966 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 2967 if (th->cwr) 2968 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 2969 2970 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B)) 2971 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID; 2972 2973 skb->csum_start = (unsigned char *)th - skb->head; 2974 skb->csum_offset = offsetof(struct tcphdr, check); 2975 skb->ip_summed = CHECKSUM_PARTIAL; 2976 2977 trace_hns3_gro(skb); 2978 2979 return 0; 2980 } 2981 2982 static void hns3_checksum_complete(struct hns3_enet_ring *ring, 2983 struct sk_buff *skb, u32 l234info) 2984 { 2985 u32 lo, hi; 2986 2987 u64_stats_update_begin(&ring->syncp); 2988 ring->stats.csum_complete++; 2989 u64_stats_update_end(&ring->syncp); 2990 skb->ip_summed = CHECKSUM_COMPLETE; 2991 lo = hnae3_get_field(l234info, HNS3_RXD_L2_CSUM_L_M, 2992 HNS3_RXD_L2_CSUM_L_S); 2993 hi = hnae3_get_field(l234info, HNS3_RXD_L2_CSUM_H_M, 2994 HNS3_RXD_L2_CSUM_H_S); 2995 skb->csum = csum_unfold((__force __sum16)(lo | hi << 8)); 2996 } 2997 2998 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2999 u32 l234info, u32 bd_base_info, u32 ol_info) 3000 { 3001 struct net_device *netdev = ring_to_netdev(ring); 3002 int l3_type, l4_type; 3003 int ol4_type; 3004 3005 skb->ip_summed = CHECKSUM_NONE; 3006 3007 skb_checksum_none_assert(skb); 3008 3009 if (!(netdev->features & NETIF_F_RXCSUM)) 3010 return; 3011 3012 if (l234info & BIT(HNS3_RXD_L2_CSUM_B)) { 3013 hns3_checksum_complete(ring, skb, l234info); 3014 return; 3015 } 3016 3017 /* check if hardware has done checksum */ 3018 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 3019 return; 3020 3021 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | 3022 BIT(HNS3_RXD_OL3E_B) | 3023 BIT(HNS3_RXD_OL4E_B)))) { 3024 u64_stats_update_begin(&ring->syncp); 3025 ring->stats.l3l4_csum_err++; 3026 u64_stats_update_end(&ring->syncp); 3027 3028 return; 3029 } 3030 3031 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M, 3032 HNS3_RXD_OL4ID_S); 3033 switch (ol4_type) { 3034 case HNS3_OL4_TYPE_MAC_IN_UDP: 3035 case HNS3_OL4_TYPE_NVGRE: 3036 skb->csum_level = 1; 3037 fallthrough; 3038 case HNS3_OL4_TYPE_NO_TUN: 3039 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 3040 HNS3_RXD_L3ID_S); 3041 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 3042 HNS3_RXD_L4ID_S); 3043 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 3044 if ((l3_type == HNS3_L3_TYPE_IPV4 || 3045 l3_type == HNS3_L3_TYPE_IPV6) && 3046 (l4_type == HNS3_L4_TYPE_UDP || 3047 l4_type == HNS3_L4_TYPE_TCP || 3048 l4_type == HNS3_L4_TYPE_SCTP)) 3049 skb->ip_summed = CHECKSUM_UNNECESSARY; 3050 break; 3051 default: 3052 break; 3053 } 3054 } 3055 3056 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 3057 { 3058 if (skb_has_frag_list(skb)) 3059 napi_gro_flush(&ring->tqp_vector->napi, false); 3060 3061 napi_gro_receive(&ring->tqp_vector->napi, skb); 3062 } 3063 3064 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 3065 struct hns3_desc *desc, u32 l234info, 3066 u16 *vlan_tag) 3067 { 3068 struct hnae3_handle *handle = ring->tqp->handle; 3069 struct pci_dev *pdev = ring->tqp->handle->pdev; 3070 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3071 3072 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) { 3073 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3074 if (!(*vlan_tag & VLAN_VID_MASK)) 3075 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3076 3077 return (*vlan_tag != 0); 3078 } 3079 3080 #define HNS3_STRP_OUTER_VLAN 0x1 3081 #define HNS3_STRP_INNER_VLAN 0x2 3082 #define HNS3_STRP_BOTH 0x3 3083 3084 /* Hardware always insert VLAN tag into RX descriptor when 3085 * remove the tag from packet, driver needs to determine 3086 * reporting which tag to stack. 3087 */ 3088 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 3089 HNS3_RXD_STRP_TAGP_S)) { 3090 case HNS3_STRP_OUTER_VLAN: 3091 if (handle->port_base_vlan_state != 3092 HNAE3_PORT_BASE_VLAN_DISABLE) 3093 return false; 3094 3095 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3096 return true; 3097 case HNS3_STRP_INNER_VLAN: 3098 if (handle->port_base_vlan_state != 3099 HNAE3_PORT_BASE_VLAN_DISABLE) 3100 return false; 3101 3102 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3103 return true; 3104 case HNS3_STRP_BOTH: 3105 if (handle->port_base_vlan_state == 3106 HNAE3_PORT_BASE_VLAN_DISABLE) 3107 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3108 else 3109 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3110 3111 return true; 3112 default: 3113 return false; 3114 } 3115 } 3116 3117 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring) 3118 { 3119 ring->desc[ring->next_to_clean].rx.bd_base_info &= 3120 cpu_to_le32(~BIT(HNS3_RXD_VLD_B)); 3121 ring->next_to_clean += 1; 3122 3123 if (unlikely(ring->next_to_clean == ring->desc_num)) 3124 ring->next_to_clean = 0; 3125 } 3126 3127 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length, 3128 unsigned char *va) 3129 { 3130 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 3131 struct net_device *netdev = ring_to_netdev(ring); 3132 struct sk_buff *skb; 3133 3134 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 3135 skb = ring->skb; 3136 if (unlikely(!skb)) { 3137 hns3_rl_err(netdev, "alloc rx skb fail\n"); 3138 3139 u64_stats_update_begin(&ring->syncp); 3140 ring->stats.sw_err_cnt++; 3141 u64_stats_update_end(&ring->syncp); 3142 3143 return -ENOMEM; 3144 } 3145 3146 trace_hns3_rx_desc(ring); 3147 prefetchw(skb->data); 3148 3149 ring->pending_buf = 1; 3150 ring->frag_num = 0; 3151 ring->tail_skb = NULL; 3152 if (length <= HNS3_RX_HEAD_SIZE) { 3153 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 3154 3155 /* We can reuse buffer as-is, just make sure it is reusable */ 3156 if (dev_page_is_reusable(desc_cb->priv)) 3157 desc_cb->reuse_flag = 1; 3158 else /* This page cannot be reused so discard it */ 3159 __page_frag_cache_drain(desc_cb->priv, 3160 desc_cb->pagecnt_bias); 3161 3162 hns3_rx_ring_move_fw(ring); 3163 return 0; 3164 } 3165 u64_stats_update_begin(&ring->syncp); 3166 ring->stats.seg_pkt_cnt++; 3167 u64_stats_update_end(&ring->syncp); 3168 3169 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE); 3170 __skb_put(skb, ring->pull_len); 3171 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 3172 desc_cb); 3173 hns3_rx_ring_move_fw(ring); 3174 3175 return 0; 3176 } 3177 3178 static int hns3_add_frag(struct hns3_enet_ring *ring) 3179 { 3180 struct sk_buff *skb = ring->skb; 3181 struct sk_buff *head_skb = skb; 3182 struct sk_buff *new_skb; 3183 struct hns3_desc_cb *desc_cb; 3184 struct hns3_desc *desc; 3185 u32 bd_base_info; 3186 3187 do { 3188 desc = &ring->desc[ring->next_to_clean]; 3189 desc_cb = &ring->desc_cb[ring->next_to_clean]; 3190 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3191 /* make sure HW write desc complete */ 3192 dma_rmb(); 3193 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 3194 return -ENXIO; 3195 3196 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 3197 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0); 3198 if (unlikely(!new_skb)) { 3199 hns3_rl_err(ring_to_netdev(ring), 3200 "alloc rx fraglist skb fail\n"); 3201 return -ENXIO; 3202 } 3203 ring->frag_num = 0; 3204 3205 if (ring->tail_skb) { 3206 ring->tail_skb->next = new_skb; 3207 ring->tail_skb = new_skb; 3208 } else { 3209 skb_shinfo(skb)->frag_list = new_skb; 3210 ring->tail_skb = new_skb; 3211 } 3212 } 3213 3214 if (ring->tail_skb) { 3215 head_skb->truesize += hns3_buf_size(ring); 3216 head_skb->data_len += le16_to_cpu(desc->rx.size); 3217 head_skb->len += le16_to_cpu(desc->rx.size); 3218 skb = ring->tail_skb; 3219 } 3220 3221 dma_sync_single_for_cpu(ring_to_dev(ring), 3222 desc_cb->dma + desc_cb->page_offset, 3223 hns3_buf_size(ring), 3224 DMA_FROM_DEVICE); 3225 3226 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 3227 trace_hns3_rx_desc(ring); 3228 hns3_rx_ring_move_fw(ring); 3229 ring->pending_buf++; 3230 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B))); 3231 3232 return 0; 3233 } 3234 3235 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring, 3236 struct sk_buff *skb, u32 l234info, 3237 u32 bd_base_info, u32 ol_info) 3238 { 3239 u32 l3_type; 3240 3241 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 3242 HNS3_RXD_GRO_SIZE_M, 3243 HNS3_RXD_GRO_SIZE_S); 3244 /* if there is no HW GRO, do not set gro params */ 3245 if (!skb_shinfo(skb)->gso_size) { 3246 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info); 3247 return 0; 3248 } 3249 3250 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info, 3251 HNS3_RXD_GRO_COUNT_M, 3252 HNS3_RXD_GRO_COUNT_S); 3253 3254 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S); 3255 if (l3_type == HNS3_L3_TYPE_IPV4) 3256 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 3257 else if (l3_type == HNS3_L3_TYPE_IPV6) 3258 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 3259 else 3260 return -EFAULT; 3261 3262 return hns3_gro_complete(skb, l234info); 3263 } 3264 3265 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 3266 struct sk_buff *skb, u32 rss_hash) 3267 { 3268 struct hnae3_handle *handle = ring->tqp->handle; 3269 enum pkt_hash_types rss_type; 3270 3271 if (rss_hash) 3272 rss_type = handle->kinfo.rss_type; 3273 else 3274 rss_type = PKT_HASH_TYPE_NONE; 3275 3276 skb_set_hash(skb, rss_hash, rss_type); 3277 } 3278 3279 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb) 3280 { 3281 struct net_device *netdev = ring_to_netdev(ring); 3282 enum hns3_pkt_l2t_type l2_frame_type; 3283 u32 bd_base_info, l234info, ol_info; 3284 struct hns3_desc *desc; 3285 unsigned int len; 3286 int pre_ntc, ret; 3287 3288 /* bdinfo handled below is only valid on the last BD of the 3289 * current packet, and ring->next_to_clean indicates the first 3290 * descriptor of next packet, so need - 1 below. 3291 */ 3292 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) : 3293 (ring->desc_num - 1); 3294 desc = &ring->desc[pre_ntc]; 3295 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3296 l234info = le32_to_cpu(desc->rx.l234_info); 3297 ol_info = le32_to_cpu(desc->rx.ol_info); 3298 3299 /* Based on hw strategy, the tag offloaded will be stored at 3300 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 3301 * in one layer tag case. 3302 */ 3303 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 3304 u16 vlan_tag; 3305 3306 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 3307 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 3308 vlan_tag); 3309 } 3310 3311 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 3312 BIT(HNS3_RXD_L2E_B))))) { 3313 u64_stats_update_begin(&ring->syncp); 3314 if (l234info & BIT(HNS3_RXD_L2E_B)) 3315 ring->stats.l2_err++; 3316 else 3317 ring->stats.err_pkt_len++; 3318 u64_stats_update_end(&ring->syncp); 3319 3320 return -EFAULT; 3321 } 3322 3323 len = skb->len; 3324 3325 /* Do update ip stack process */ 3326 skb->protocol = eth_type_trans(skb, netdev); 3327 3328 /* This is needed in order to enable forwarding support */ 3329 ret = hns3_set_gro_and_checksum(ring, skb, l234info, 3330 bd_base_info, ol_info); 3331 if (unlikely(ret)) { 3332 u64_stats_update_begin(&ring->syncp); 3333 ring->stats.rx_err_cnt++; 3334 u64_stats_update_end(&ring->syncp); 3335 return ret; 3336 } 3337 3338 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 3339 HNS3_RXD_DMAC_S); 3340 3341 u64_stats_update_begin(&ring->syncp); 3342 ring->stats.rx_pkts++; 3343 ring->stats.rx_bytes += len; 3344 3345 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 3346 ring->stats.rx_multicast++; 3347 3348 u64_stats_update_end(&ring->syncp); 3349 3350 ring->tqp_vector->rx_group.total_bytes += len; 3351 3352 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash)); 3353 return 0; 3354 } 3355 3356 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring) 3357 { 3358 struct sk_buff *skb = ring->skb; 3359 struct hns3_desc_cb *desc_cb; 3360 struct hns3_desc *desc; 3361 unsigned int length; 3362 u32 bd_base_info; 3363 int ret; 3364 3365 desc = &ring->desc[ring->next_to_clean]; 3366 desc_cb = &ring->desc_cb[ring->next_to_clean]; 3367 3368 prefetch(desc); 3369 3370 if (!skb) { 3371 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3372 /* Check valid BD */ 3373 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 3374 return -ENXIO; 3375 3376 dma_rmb(); 3377 length = le16_to_cpu(desc->rx.size); 3378 3379 ring->va = desc_cb->buf + desc_cb->page_offset; 3380 3381 dma_sync_single_for_cpu(ring_to_dev(ring), 3382 desc_cb->dma + desc_cb->page_offset, 3383 hns3_buf_size(ring), 3384 DMA_FROM_DEVICE); 3385 3386 /* Prefetch first cache line of first page. 3387 * Idea is to cache few bytes of the header of the packet. 3388 * Our L1 Cache line size is 64B so need to prefetch twice to make 3389 * it 128B. But in actual we can have greater size of caches with 3390 * 128B Level 1 cache lines. In such a case, single fetch would 3391 * suffice to cache in the relevant part of the header. 3392 */ 3393 net_prefetch(ring->va); 3394 3395 ret = hns3_alloc_skb(ring, length, ring->va); 3396 skb = ring->skb; 3397 3398 if (ret < 0) /* alloc buffer fail */ 3399 return ret; 3400 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */ 3401 ret = hns3_add_frag(ring); 3402 if (ret) 3403 return ret; 3404 } 3405 } else { 3406 ret = hns3_add_frag(ring); 3407 if (ret) 3408 return ret; 3409 } 3410 3411 /* As the head data may be changed when GRO enable, copy 3412 * the head data in after other data rx completed 3413 */ 3414 if (skb->len > HNS3_RX_HEAD_SIZE) 3415 memcpy(skb->data, ring->va, 3416 ALIGN(ring->pull_len, sizeof(long))); 3417 3418 ret = hns3_handle_bdinfo(ring, skb); 3419 if (unlikely(ret)) { 3420 dev_kfree_skb_any(skb); 3421 return ret; 3422 } 3423 3424 skb_record_rx_queue(skb, ring->tqp->tqp_index); 3425 return 0; 3426 } 3427 3428 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget, 3429 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 3430 { 3431 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 3432 int unused_count = hns3_desc_unused(ring); 3433 int recv_pkts = 0; 3434 int err; 3435 3436 unused_count -= ring->pending_buf; 3437 3438 while (recv_pkts < budget) { 3439 /* Reuse or realloc buffers */ 3440 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 3441 hns3_nic_alloc_rx_buffers(ring, unused_count); 3442 unused_count = hns3_desc_unused(ring) - 3443 ring->pending_buf; 3444 } 3445 3446 /* Poll one pkt */ 3447 err = hns3_handle_rx_bd(ring); 3448 /* Do not get FE for the packet or failed to alloc skb */ 3449 if (unlikely(!ring->skb || err == -ENXIO)) { 3450 goto out; 3451 } else if (likely(!err)) { 3452 rx_fn(ring, ring->skb); 3453 recv_pkts++; 3454 } 3455 3456 unused_count += ring->pending_buf; 3457 ring->skb = NULL; 3458 ring->pending_buf = 0; 3459 } 3460 3461 out: 3462 /* Make all data has been write before submit */ 3463 if (unused_count > 0) 3464 hns3_nic_alloc_rx_buffers(ring, unused_count); 3465 3466 return recv_pkts; 3467 } 3468 3469 static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group) 3470 { 3471 #define HNS3_RX_LOW_BYTE_RATE 10000 3472 #define HNS3_RX_MID_BYTE_RATE 20000 3473 #define HNS3_RX_ULTRA_PACKET_RATE 40 3474 3475 enum hns3_flow_level_range new_flow_level; 3476 struct hns3_enet_tqp_vector *tqp_vector; 3477 int packets_per_msecs, bytes_per_msecs; 3478 u32 time_passed_ms; 3479 3480 tqp_vector = ring_group->ring->tqp_vector; 3481 time_passed_ms = 3482 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 3483 if (!time_passed_ms) 3484 return false; 3485 3486 do_div(ring_group->total_packets, time_passed_ms); 3487 packets_per_msecs = ring_group->total_packets; 3488 3489 do_div(ring_group->total_bytes, time_passed_ms); 3490 bytes_per_msecs = ring_group->total_bytes; 3491 3492 new_flow_level = ring_group->coal.flow_level; 3493 3494 /* Simple throttlerate management 3495 * 0-10MB/s lower (50000 ints/s) 3496 * 10-20MB/s middle (20000 ints/s) 3497 * 20-1249MB/s high (18000 ints/s) 3498 * > 40000pps ultra (8000 ints/s) 3499 */ 3500 switch (new_flow_level) { 3501 case HNS3_FLOW_LOW: 3502 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 3503 new_flow_level = HNS3_FLOW_MID; 3504 break; 3505 case HNS3_FLOW_MID: 3506 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 3507 new_flow_level = HNS3_FLOW_HIGH; 3508 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 3509 new_flow_level = HNS3_FLOW_LOW; 3510 break; 3511 case HNS3_FLOW_HIGH: 3512 case HNS3_FLOW_ULTRA: 3513 default: 3514 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 3515 new_flow_level = HNS3_FLOW_MID; 3516 break; 3517 } 3518 3519 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 3520 &tqp_vector->rx_group == ring_group) 3521 new_flow_level = HNS3_FLOW_ULTRA; 3522 3523 ring_group->total_bytes = 0; 3524 ring_group->total_packets = 0; 3525 ring_group->coal.flow_level = new_flow_level; 3526 3527 return true; 3528 } 3529 3530 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 3531 { 3532 struct hns3_enet_tqp_vector *tqp_vector; 3533 u16 new_int_gl; 3534 3535 if (!ring_group->ring) 3536 return false; 3537 3538 tqp_vector = ring_group->ring->tqp_vector; 3539 if (!tqp_vector->last_jiffies) 3540 return false; 3541 3542 if (ring_group->total_packets == 0) { 3543 ring_group->coal.int_gl = HNS3_INT_GL_50K; 3544 ring_group->coal.flow_level = HNS3_FLOW_LOW; 3545 return true; 3546 } 3547 3548 if (!hns3_get_new_flow_lvl(ring_group)) 3549 return false; 3550 3551 new_int_gl = ring_group->coal.int_gl; 3552 switch (ring_group->coal.flow_level) { 3553 case HNS3_FLOW_LOW: 3554 new_int_gl = HNS3_INT_GL_50K; 3555 break; 3556 case HNS3_FLOW_MID: 3557 new_int_gl = HNS3_INT_GL_20K; 3558 break; 3559 case HNS3_FLOW_HIGH: 3560 new_int_gl = HNS3_INT_GL_18K; 3561 break; 3562 case HNS3_FLOW_ULTRA: 3563 new_int_gl = HNS3_INT_GL_8K; 3564 break; 3565 default: 3566 break; 3567 } 3568 3569 if (new_int_gl != ring_group->coal.int_gl) { 3570 ring_group->coal.int_gl = new_int_gl; 3571 return true; 3572 } 3573 return false; 3574 } 3575 3576 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 3577 { 3578 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 3579 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 3580 bool rx_update, tx_update; 3581 3582 /* update param every 1000ms */ 3583 if (time_before(jiffies, 3584 tqp_vector->last_jiffies + msecs_to_jiffies(1000))) 3585 return; 3586 3587 if (rx_group->coal.adapt_enable) { 3588 rx_update = hns3_get_new_int_gl(rx_group); 3589 if (rx_update) 3590 hns3_set_vector_coalesce_rx_gl(tqp_vector, 3591 rx_group->coal.int_gl); 3592 } 3593 3594 if (tx_group->coal.adapt_enable) { 3595 tx_update = hns3_get_new_int_gl(tx_group); 3596 if (tx_update) 3597 hns3_set_vector_coalesce_tx_gl(tqp_vector, 3598 tx_group->coal.int_gl); 3599 } 3600 3601 tqp_vector->last_jiffies = jiffies; 3602 } 3603 3604 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 3605 { 3606 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 3607 struct hns3_enet_ring *ring; 3608 int rx_pkt_total = 0; 3609 3610 struct hns3_enet_tqp_vector *tqp_vector = 3611 container_of(napi, struct hns3_enet_tqp_vector, napi); 3612 bool clean_complete = true; 3613 int rx_budget = budget; 3614 3615 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3616 napi_complete(napi); 3617 return 0; 3618 } 3619 3620 /* Since the actual Tx work is minimal, we can give the Tx a larger 3621 * budget and be more aggressive about cleaning up the Tx descriptors. 3622 */ 3623 hns3_for_each_ring(ring, tqp_vector->tx_group) 3624 hns3_clean_tx_ring(ring, budget); 3625 3626 /* make sure rx ring budget not smaller than 1 */ 3627 if (tqp_vector->num_tqps > 1) 3628 rx_budget = max(budget / tqp_vector->num_tqps, 1); 3629 3630 hns3_for_each_ring(ring, tqp_vector->rx_group) { 3631 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 3632 hns3_rx_skb); 3633 if (rx_cleaned >= rx_budget) 3634 clean_complete = false; 3635 3636 rx_pkt_total += rx_cleaned; 3637 } 3638 3639 tqp_vector->rx_group.total_packets += rx_pkt_total; 3640 3641 if (!clean_complete) 3642 return budget; 3643 3644 if (napi_complete(napi) && 3645 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3646 hns3_update_new_int_gl(tqp_vector); 3647 hns3_mask_vector_irq(tqp_vector, 1); 3648 } 3649 3650 return rx_pkt_total; 3651 } 3652 3653 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3654 struct hnae3_ring_chain_node *head) 3655 { 3656 struct pci_dev *pdev = tqp_vector->handle->pdev; 3657 struct hnae3_ring_chain_node *cur_chain = head; 3658 struct hnae3_ring_chain_node *chain; 3659 struct hns3_enet_ring *tx_ring; 3660 struct hns3_enet_ring *rx_ring; 3661 3662 tx_ring = tqp_vector->tx_group.ring; 3663 if (tx_ring) { 3664 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 3665 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3666 HNAE3_RING_TYPE_TX); 3667 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3668 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 3669 3670 cur_chain->next = NULL; 3671 3672 while (tx_ring->next) { 3673 tx_ring = tx_ring->next; 3674 3675 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 3676 GFP_KERNEL); 3677 if (!chain) 3678 goto err_free_chain; 3679 3680 cur_chain->next = chain; 3681 chain->tqp_index = tx_ring->tqp->tqp_index; 3682 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3683 HNAE3_RING_TYPE_TX); 3684 hnae3_set_field(chain->int_gl_idx, 3685 HNAE3_RING_GL_IDX_M, 3686 HNAE3_RING_GL_IDX_S, 3687 HNAE3_RING_GL_TX); 3688 3689 cur_chain = chain; 3690 } 3691 } 3692 3693 rx_ring = tqp_vector->rx_group.ring; 3694 if (!tx_ring && rx_ring) { 3695 cur_chain->next = NULL; 3696 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 3697 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3698 HNAE3_RING_TYPE_RX); 3699 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3700 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3701 3702 rx_ring = rx_ring->next; 3703 } 3704 3705 while (rx_ring) { 3706 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 3707 if (!chain) 3708 goto err_free_chain; 3709 3710 cur_chain->next = chain; 3711 chain->tqp_index = rx_ring->tqp->tqp_index; 3712 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3713 HNAE3_RING_TYPE_RX); 3714 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3715 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3716 3717 cur_chain = chain; 3718 3719 rx_ring = rx_ring->next; 3720 } 3721 3722 return 0; 3723 3724 err_free_chain: 3725 cur_chain = head->next; 3726 while (cur_chain) { 3727 chain = cur_chain->next; 3728 devm_kfree(&pdev->dev, cur_chain); 3729 cur_chain = chain; 3730 } 3731 head->next = NULL; 3732 3733 return -ENOMEM; 3734 } 3735 3736 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3737 struct hnae3_ring_chain_node *head) 3738 { 3739 struct pci_dev *pdev = tqp_vector->handle->pdev; 3740 struct hnae3_ring_chain_node *chain_tmp, *chain; 3741 3742 chain = head->next; 3743 3744 while (chain) { 3745 chain_tmp = chain->next; 3746 devm_kfree(&pdev->dev, chain); 3747 chain = chain_tmp; 3748 } 3749 } 3750 3751 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 3752 struct hns3_enet_ring *ring) 3753 { 3754 ring->next = group->ring; 3755 group->ring = ring; 3756 3757 group->count++; 3758 } 3759 3760 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 3761 { 3762 struct pci_dev *pdev = priv->ae_handle->pdev; 3763 struct hns3_enet_tqp_vector *tqp_vector; 3764 int num_vectors = priv->vector_num; 3765 int numa_node; 3766 int vector_i; 3767 3768 numa_node = dev_to_node(&pdev->dev); 3769 3770 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 3771 tqp_vector = &priv->tqp_vector[vector_i]; 3772 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 3773 &tqp_vector->affinity_mask); 3774 } 3775 } 3776 3777 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 3778 { 3779 struct hnae3_handle *h = priv->ae_handle; 3780 struct hns3_enet_tqp_vector *tqp_vector; 3781 int ret; 3782 int i; 3783 3784 hns3_nic_set_cpumask(priv); 3785 3786 for (i = 0; i < priv->vector_num; i++) { 3787 tqp_vector = &priv->tqp_vector[i]; 3788 hns3_vector_coalesce_init_hw(tqp_vector, priv); 3789 tqp_vector->num_tqps = 0; 3790 } 3791 3792 for (i = 0; i < h->kinfo.num_tqps; i++) { 3793 u16 vector_i = i % priv->vector_num; 3794 u16 tqp_num = h->kinfo.num_tqps; 3795 3796 tqp_vector = &priv->tqp_vector[vector_i]; 3797 3798 hns3_add_ring_to_group(&tqp_vector->tx_group, 3799 &priv->ring[i]); 3800 3801 hns3_add_ring_to_group(&tqp_vector->rx_group, 3802 &priv->ring[i + tqp_num]); 3803 3804 priv->ring[i].tqp_vector = tqp_vector; 3805 priv->ring[i + tqp_num].tqp_vector = tqp_vector; 3806 tqp_vector->num_tqps++; 3807 } 3808 3809 for (i = 0; i < priv->vector_num; i++) { 3810 struct hnae3_ring_chain_node vector_ring_chain; 3811 3812 tqp_vector = &priv->tqp_vector[i]; 3813 3814 tqp_vector->rx_group.total_bytes = 0; 3815 tqp_vector->rx_group.total_packets = 0; 3816 tqp_vector->tx_group.total_bytes = 0; 3817 tqp_vector->tx_group.total_packets = 0; 3818 tqp_vector->handle = h; 3819 3820 ret = hns3_get_vector_ring_chain(tqp_vector, 3821 &vector_ring_chain); 3822 if (ret) 3823 goto map_ring_fail; 3824 3825 ret = h->ae_algo->ops->map_ring_to_vector(h, 3826 tqp_vector->vector_irq, &vector_ring_chain); 3827 3828 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3829 3830 if (ret) 3831 goto map_ring_fail; 3832 3833 netif_napi_add(priv->netdev, &tqp_vector->napi, 3834 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 3835 } 3836 3837 return 0; 3838 3839 map_ring_fail: 3840 while (i--) 3841 netif_napi_del(&priv->tqp_vector[i].napi); 3842 3843 return ret; 3844 } 3845 3846 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 3847 { 3848 struct hnae3_handle *h = priv->ae_handle; 3849 struct hns3_enet_tqp_vector *tqp_vector; 3850 struct hnae3_vector_info *vector; 3851 struct pci_dev *pdev = h->pdev; 3852 u16 tqp_num = h->kinfo.num_tqps; 3853 u16 vector_num; 3854 int ret = 0; 3855 u16 i; 3856 3857 /* RSS size, cpu online and vector_num should be the same */ 3858 /* Should consider 2p/4p later */ 3859 vector_num = min_t(u16, num_online_cpus(), tqp_num); 3860 3861 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 3862 GFP_KERNEL); 3863 if (!vector) 3864 return -ENOMEM; 3865 3866 /* save the actual available vector number */ 3867 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 3868 3869 priv->vector_num = vector_num; 3870 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 3871 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 3872 GFP_KERNEL); 3873 if (!priv->tqp_vector) { 3874 ret = -ENOMEM; 3875 goto out; 3876 } 3877 3878 for (i = 0; i < priv->vector_num; i++) { 3879 tqp_vector = &priv->tqp_vector[i]; 3880 tqp_vector->idx = i; 3881 tqp_vector->mask_addr = vector[i].io_addr; 3882 tqp_vector->vector_irq = vector[i].vector; 3883 hns3_vector_coalesce_init(tqp_vector, priv); 3884 } 3885 3886 out: 3887 devm_kfree(&pdev->dev, vector); 3888 return ret; 3889 } 3890 3891 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 3892 { 3893 group->ring = NULL; 3894 group->count = 0; 3895 } 3896 3897 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 3898 { 3899 struct hnae3_ring_chain_node vector_ring_chain; 3900 struct hnae3_handle *h = priv->ae_handle; 3901 struct hns3_enet_tqp_vector *tqp_vector; 3902 int i; 3903 3904 for (i = 0; i < priv->vector_num; i++) { 3905 tqp_vector = &priv->tqp_vector[i]; 3906 3907 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 3908 continue; 3909 3910 /* Since the mapping can be overwritten, when fail to get the 3911 * chain between vector and ring, we should go on to deal with 3912 * the remaining options. 3913 */ 3914 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain)) 3915 dev_warn(priv->dev, "failed to get ring chain\n"); 3916 3917 h->ae_algo->ops->unmap_ring_from_vector(h, 3918 tqp_vector->vector_irq, &vector_ring_chain); 3919 3920 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3921 3922 hns3_clear_ring_group(&tqp_vector->rx_group); 3923 hns3_clear_ring_group(&tqp_vector->tx_group); 3924 netif_napi_del(&priv->tqp_vector[i].napi); 3925 } 3926 } 3927 3928 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 3929 { 3930 struct hnae3_handle *h = priv->ae_handle; 3931 struct pci_dev *pdev = h->pdev; 3932 int i, ret; 3933 3934 for (i = 0; i < priv->vector_num; i++) { 3935 struct hns3_enet_tqp_vector *tqp_vector; 3936 3937 tqp_vector = &priv->tqp_vector[i]; 3938 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 3939 if (ret) 3940 return; 3941 } 3942 3943 devm_kfree(&pdev->dev, priv->tqp_vector); 3944 } 3945 3946 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 3947 unsigned int ring_type) 3948 { 3949 int queue_num = priv->ae_handle->kinfo.num_tqps; 3950 struct hns3_enet_ring *ring; 3951 int desc_num; 3952 3953 if (ring_type == HNAE3_RING_TYPE_TX) { 3954 ring = &priv->ring[q->tqp_index]; 3955 desc_num = priv->ae_handle->kinfo.num_tx_desc; 3956 ring->queue_index = q->tqp_index; 3957 } else { 3958 ring = &priv->ring[q->tqp_index + queue_num]; 3959 desc_num = priv->ae_handle->kinfo.num_rx_desc; 3960 ring->queue_index = q->tqp_index; 3961 } 3962 3963 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 3964 3965 ring->tqp = q; 3966 ring->desc = NULL; 3967 ring->desc_cb = NULL; 3968 ring->dev = priv->dev; 3969 ring->desc_dma_addr = 0; 3970 ring->buf_size = q->buf_size; 3971 ring->desc_num = desc_num; 3972 ring->next_to_use = 0; 3973 ring->next_to_clean = 0; 3974 ring->last_to_use = 0; 3975 } 3976 3977 static void hns3_queue_to_ring(struct hnae3_queue *tqp, 3978 struct hns3_nic_priv *priv) 3979 { 3980 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 3981 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 3982 } 3983 3984 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 3985 { 3986 struct hnae3_handle *h = priv->ae_handle; 3987 struct pci_dev *pdev = h->pdev; 3988 int i; 3989 3990 priv->ring = devm_kzalloc(&pdev->dev, 3991 array3_size(h->kinfo.num_tqps, 3992 sizeof(*priv->ring), 2), 3993 GFP_KERNEL); 3994 if (!priv->ring) 3995 return -ENOMEM; 3996 3997 for (i = 0; i < h->kinfo.num_tqps; i++) 3998 hns3_queue_to_ring(h->kinfo.tqp[i], priv); 3999 4000 return 0; 4001 } 4002 4003 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 4004 { 4005 if (!priv->ring) 4006 return; 4007 4008 devm_kfree(priv->dev, priv->ring); 4009 priv->ring = NULL; 4010 } 4011 4012 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 4013 { 4014 int ret; 4015 4016 if (ring->desc_num <= 0 || ring->buf_size <= 0) 4017 return -EINVAL; 4018 4019 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num, 4020 sizeof(ring->desc_cb[0]), GFP_KERNEL); 4021 if (!ring->desc_cb) { 4022 ret = -ENOMEM; 4023 goto out; 4024 } 4025 4026 ret = hns3_alloc_desc(ring); 4027 if (ret) 4028 goto out_with_desc_cb; 4029 4030 if (!HNAE3_IS_TX_RING(ring)) { 4031 ret = hns3_alloc_ring_buffers(ring); 4032 if (ret) 4033 goto out_with_desc; 4034 } 4035 4036 return 0; 4037 4038 out_with_desc: 4039 hns3_free_desc(ring); 4040 out_with_desc_cb: 4041 devm_kfree(ring_to_dev(ring), ring->desc_cb); 4042 ring->desc_cb = NULL; 4043 out: 4044 return ret; 4045 } 4046 4047 void hns3_fini_ring(struct hns3_enet_ring *ring) 4048 { 4049 hns3_free_desc(ring); 4050 devm_kfree(ring_to_dev(ring), ring->desc_cb); 4051 ring->desc_cb = NULL; 4052 ring->next_to_clean = 0; 4053 ring->next_to_use = 0; 4054 ring->last_to_use = 0; 4055 ring->pending_buf = 0; 4056 if (ring->skb) { 4057 dev_kfree_skb_any(ring->skb); 4058 ring->skb = NULL; 4059 } 4060 } 4061 4062 static int hns3_buf_size2type(u32 buf_size) 4063 { 4064 int bd_size_type; 4065 4066 switch (buf_size) { 4067 case 512: 4068 bd_size_type = HNS3_BD_SIZE_512_TYPE; 4069 break; 4070 case 1024: 4071 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 4072 break; 4073 case 2048: 4074 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 4075 break; 4076 case 4096: 4077 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 4078 break; 4079 default: 4080 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 4081 } 4082 4083 return bd_size_type; 4084 } 4085 4086 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 4087 { 4088 dma_addr_t dma = ring->desc_dma_addr; 4089 struct hnae3_queue *q = ring->tqp; 4090 4091 if (!HNAE3_IS_TX_RING(ring)) { 4092 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma); 4093 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 4094 (u32)((dma >> 31) >> 1)); 4095 4096 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 4097 hns3_buf_size2type(ring->buf_size)); 4098 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 4099 ring->desc_num / 8 - 1); 4100 } else { 4101 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 4102 (u32)dma); 4103 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 4104 (u32)((dma >> 31) >> 1)); 4105 4106 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 4107 ring->desc_num / 8 - 1); 4108 } 4109 } 4110 4111 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 4112 { 4113 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 4114 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 4115 int i; 4116 4117 for (i = 0; i < HNAE3_MAX_TC; i++) { 4118 int j; 4119 4120 if (!test_bit(i, &tc_info->tc_en)) 4121 continue; 4122 4123 for (j = 0; j < tc_info->tqp_count[i]; j++) { 4124 struct hnae3_queue *q; 4125 4126 q = priv->ring[tc_info->tqp_offset[i] + j].tqp; 4127 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i); 4128 } 4129 } 4130 } 4131 4132 int hns3_init_all_ring(struct hns3_nic_priv *priv) 4133 { 4134 struct hnae3_handle *h = priv->ae_handle; 4135 int ring_num = h->kinfo.num_tqps * 2; 4136 int i, j; 4137 int ret; 4138 4139 for (i = 0; i < ring_num; i++) { 4140 ret = hns3_alloc_ring_memory(&priv->ring[i]); 4141 if (ret) { 4142 dev_err(priv->dev, 4143 "Alloc ring memory fail! ret=%d\n", ret); 4144 goto out_when_alloc_ring_memory; 4145 } 4146 4147 u64_stats_init(&priv->ring[i].syncp); 4148 } 4149 4150 return 0; 4151 4152 out_when_alloc_ring_memory: 4153 for (j = i - 1; j >= 0; j--) 4154 hns3_fini_ring(&priv->ring[j]); 4155 4156 return -ENOMEM; 4157 } 4158 4159 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv) 4160 { 4161 struct hnae3_handle *h = priv->ae_handle; 4162 int i; 4163 4164 for (i = 0; i < h->kinfo.num_tqps; i++) { 4165 hns3_fini_ring(&priv->ring[i]); 4166 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]); 4167 } 4168 } 4169 4170 /* Set mac addr if it is configured. or leave it to the AE driver */ 4171 static int hns3_init_mac_addr(struct net_device *netdev) 4172 { 4173 struct hns3_nic_priv *priv = netdev_priv(netdev); 4174 struct hnae3_handle *h = priv->ae_handle; 4175 u8 mac_addr_temp[ETH_ALEN]; 4176 int ret = 0; 4177 4178 if (h->ae_algo->ops->get_mac_addr) 4179 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 4180 4181 /* Check if the MAC address is valid, if not get a random one */ 4182 if (!is_valid_ether_addr(mac_addr_temp)) { 4183 eth_hw_addr_random(netdev); 4184 dev_warn(priv->dev, "using random MAC address %pM\n", 4185 netdev->dev_addr); 4186 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) { 4187 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 4188 ether_addr_copy(netdev->perm_addr, mac_addr_temp); 4189 } else { 4190 return 0; 4191 } 4192 4193 if (h->ae_algo->ops->set_mac_addr) 4194 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 4195 4196 return ret; 4197 } 4198 4199 static int hns3_init_phy(struct net_device *netdev) 4200 { 4201 struct hnae3_handle *h = hns3_get_handle(netdev); 4202 int ret = 0; 4203 4204 if (h->ae_algo->ops->mac_connect_phy) 4205 ret = h->ae_algo->ops->mac_connect_phy(h); 4206 4207 return ret; 4208 } 4209 4210 static void hns3_uninit_phy(struct net_device *netdev) 4211 { 4212 struct hnae3_handle *h = hns3_get_handle(netdev); 4213 4214 if (h->ae_algo->ops->mac_disconnect_phy) 4215 h->ae_algo->ops->mac_disconnect_phy(h); 4216 } 4217 4218 static int hns3_client_start(struct hnae3_handle *handle) 4219 { 4220 if (!handle->ae_algo->ops->client_start) 4221 return 0; 4222 4223 return handle->ae_algo->ops->client_start(handle); 4224 } 4225 4226 static void hns3_client_stop(struct hnae3_handle *handle) 4227 { 4228 if (!handle->ae_algo->ops->client_stop) 4229 return; 4230 4231 handle->ae_algo->ops->client_stop(handle); 4232 } 4233 4234 static void hns3_info_show(struct hns3_nic_priv *priv) 4235 { 4236 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 4237 4238 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr); 4239 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps); 4240 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size); 4241 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size); 4242 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len); 4243 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc); 4244 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc); 4245 dev_info(priv->dev, "Total number of enabled TCs: %u\n", 4246 kinfo->tc_info.num_tc); 4247 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu); 4248 } 4249 4250 static int hns3_client_init(struct hnae3_handle *handle) 4251 { 4252 struct pci_dev *pdev = handle->pdev; 4253 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4254 u16 alloc_tqps, max_rss_size; 4255 struct hns3_nic_priv *priv; 4256 struct net_device *netdev; 4257 int ret; 4258 4259 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 4260 &max_rss_size); 4261 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 4262 if (!netdev) 4263 return -ENOMEM; 4264 4265 priv = netdev_priv(netdev); 4266 priv->dev = &pdev->dev; 4267 priv->netdev = netdev; 4268 priv->ae_handle = handle; 4269 priv->tx_timeout_count = 0; 4270 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num; 4271 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 4272 4273 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL); 4274 4275 handle->kinfo.netdev = netdev; 4276 handle->priv = (void *)priv; 4277 4278 hns3_init_mac_addr(netdev); 4279 4280 hns3_set_default_feature(netdev); 4281 4282 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 4283 netdev->priv_flags |= IFF_UNICAST_FLT; 4284 netdev->netdev_ops = &hns3_nic_netdev_ops; 4285 SET_NETDEV_DEV(netdev, &pdev->dev); 4286 hns3_ethtool_set_ops(netdev); 4287 4288 /* Carrier off reporting is important to ethtool even BEFORE open */ 4289 netif_carrier_off(netdev); 4290 4291 ret = hns3_get_ring_config(priv); 4292 if (ret) { 4293 ret = -ENOMEM; 4294 goto out_get_ring_cfg; 4295 } 4296 4297 ret = hns3_nic_alloc_vector_data(priv); 4298 if (ret) { 4299 ret = -ENOMEM; 4300 goto out_alloc_vector_data; 4301 } 4302 4303 ret = hns3_nic_init_vector_data(priv); 4304 if (ret) { 4305 ret = -ENOMEM; 4306 goto out_init_vector_data; 4307 } 4308 4309 ret = hns3_init_all_ring(priv); 4310 if (ret) { 4311 ret = -ENOMEM; 4312 goto out_init_ring; 4313 } 4314 4315 ret = hns3_init_phy(netdev); 4316 if (ret) 4317 goto out_init_phy; 4318 4319 ret = register_netdev(netdev); 4320 if (ret) { 4321 dev_err(priv->dev, "probe register netdev fail!\n"); 4322 goto out_reg_netdev_fail; 4323 } 4324 4325 /* the device can work without cpu rmap, only aRFS needs it */ 4326 ret = hns3_set_rx_cpu_rmap(netdev); 4327 if (ret) 4328 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 4329 4330 ret = hns3_nic_init_irq(priv); 4331 if (ret) { 4332 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 4333 hns3_free_rx_cpu_rmap(netdev); 4334 goto out_init_irq_fail; 4335 } 4336 4337 ret = hns3_client_start(handle); 4338 if (ret) { 4339 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4340 goto out_client_start; 4341 } 4342 4343 hns3_dcbnl_setup(handle); 4344 4345 hns3_dbg_init(handle); 4346 4347 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size); 4348 4349 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) 4350 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state); 4351 4352 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4353 4354 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 4355 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags); 4356 4357 if (netif_msg_drv(handle)) 4358 hns3_info_show(priv); 4359 4360 return ret; 4361 4362 out_client_start: 4363 hns3_free_rx_cpu_rmap(netdev); 4364 hns3_nic_uninit_irq(priv); 4365 out_init_irq_fail: 4366 unregister_netdev(netdev); 4367 out_reg_netdev_fail: 4368 hns3_uninit_phy(netdev); 4369 out_init_phy: 4370 hns3_uninit_all_ring(priv); 4371 out_init_ring: 4372 hns3_nic_uninit_vector_data(priv); 4373 out_init_vector_data: 4374 hns3_nic_dealloc_vector_data(priv); 4375 out_alloc_vector_data: 4376 priv->ring = NULL; 4377 out_get_ring_cfg: 4378 priv->ae_handle = NULL; 4379 free_netdev(netdev); 4380 return ret; 4381 } 4382 4383 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 4384 { 4385 struct net_device *netdev = handle->kinfo.netdev; 4386 struct hns3_nic_priv *priv = netdev_priv(netdev); 4387 4388 if (netdev->reg_state != NETREG_UNINITIALIZED) 4389 unregister_netdev(netdev); 4390 4391 hns3_client_stop(handle); 4392 4393 hns3_uninit_phy(netdev); 4394 4395 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4396 netdev_warn(netdev, "already uninitialized\n"); 4397 goto out_netdev_free; 4398 } 4399 4400 hns3_free_rx_cpu_rmap(netdev); 4401 4402 hns3_nic_uninit_irq(priv); 4403 4404 hns3_clear_all_ring(handle, true); 4405 4406 hns3_nic_uninit_vector_data(priv); 4407 4408 hns3_nic_dealloc_vector_data(priv); 4409 4410 hns3_uninit_all_ring(priv); 4411 4412 hns3_put_ring_config(priv); 4413 4414 out_netdev_free: 4415 hns3_dbg_uninit(handle); 4416 free_netdev(netdev); 4417 } 4418 4419 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 4420 { 4421 struct net_device *netdev = handle->kinfo.netdev; 4422 4423 if (!netdev) 4424 return; 4425 4426 if (linkup) { 4427 netif_tx_wake_all_queues(netdev); 4428 netif_carrier_on(netdev); 4429 if (netif_msg_link(handle)) 4430 netdev_info(netdev, "link up\n"); 4431 } else { 4432 netif_carrier_off(netdev); 4433 netif_tx_stop_all_queues(netdev); 4434 if (netif_msg_link(handle)) 4435 netdev_info(netdev, "link down\n"); 4436 } 4437 } 4438 4439 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 4440 { 4441 while (ring->next_to_clean != ring->next_to_use) { 4442 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 4443 hns3_free_buffer_detach(ring, ring->next_to_clean, 0); 4444 ring_ptr_move_fw(ring, next_to_clean); 4445 } 4446 4447 ring->pending_buf = 0; 4448 } 4449 4450 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 4451 { 4452 struct hns3_desc_cb res_cbs; 4453 int ret; 4454 4455 while (ring->next_to_use != ring->next_to_clean) { 4456 /* When a buffer is not reused, it's memory has been 4457 * freed in hns3_handle_rx_bd or will be freed by 4458 * stack, so we need to replace the buffer here. 4459 */ 4460 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4461 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 4462 if (ret) { 4463 u64_stats_update_begin(&ring->syncp); 4464 ring->stats.sw_err_cnt++; 4465 u64_stats_update_end(&ring->syncp); 4466 /* if alloc new buffer fail, exit directly 4467 * and reclear in up flow. 4468 */ 4469 netdev_warn(ring_to_netdev(ring), 4470 "reserve buffer map failed, ret = %d\n", 4471 ret); 4472 return ret; 4473 } 4474 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 4475 } 4476 ring_ptr_move_fw(ring, next_to_use); 4477 } 4478 4479 /* Free the pending skb in rx ring */ 4480 if (ring->skb) { 4481 dev_kfree_skb_any(ring->skb); 4482 ring->skb = NULL; 4483 ring->pending_buf = 0; 4484 } 4485 4486 return 0; 4487 } 4488 4489 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 4490 { 4491 while (ring->next_to_use != ring->next_to_clean) { 4492 /* When a buffer is not reused, it's memory has been 4493 * freed in hns3_handle_rx_bd or will be freed by 4494 * stack, so only need to unmap the buffer here. 4495 */ 4496 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4497 hns3_unmap_buffer(ring, 4498 &ring->desc_cb[ring->next_to_use]); 4499 ring->desc_cb[ring->next_to_use].dma = 0; 4500 } 4501 4502 ring_ptr_move_fw(ring, next_to_use); 4503 } 4504 } 4505 4506 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force) 4507 { 4508 struct net_device *ndev = h->kinfo.netdev; 4509 struct hns3_nic_priv *priv = netdev_priv(ndev); 4510 u32 i; 4511 4512 for (i = 0; i < h->kinfo.num_tqps; i++) { 4513 struct hns3_enet_ring *ring; 4514 4515 ring = &priv->ring[i]; 4516 hns3_clear_tx_ring(ring); 4517 4518 ring = &priv->ring[i + h->kinfo.num_tqps]; 4519 /* Continue to clear other rings even if clearing some 4520 * rings failed. 4521 */ 4522 if (force) 4523 hns3_force_clear_rx_ring(ring); 4524 else 4525 hns3_clear_rx_ring(ring); 4526 } 4527 } 4528 4529 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 4530 { 4531 struct net_device *ndev = h->kinfo.netdev; 4532 struct hns3_nic_priv *priv = netdev_priv(ndev); 4533 struct hns3_enet_ring *rx_ring; 4534 int i, j; 4535 int ret; 4536 4537 ret = h->ae_algo->ops->reset_queue(h); 4538 if (ret) 4539 return ret; 4540 4541 for (i = 0; i < h->kinfo.num_tqps; i++) { 4542 hns3_init_ring_hw(&priv->ring[i]); 4543 4544 /* We need to clear tx ring here because self test will 4545 * use the ring and will not run down before up 4546 */ 4547 hns3_clear_tx_ring(&priv->ring[i]); 4548 priv->ring[i].next_to_clean = 0; 4549 priv->ring[i].next_to_use = 0; 4550 priv->ring[i].last_to_use = 0; 4551 4552 rx_ring = &priv->ring[i + h->kinfo.num_tqps]; 4553 hns3_init_ring_hw(rx_ring); 4554 ret = hns3_clear_rx_ring(rx_ring); 4555 if (ret) 4556 return ret; 4557 4558 /* We can not know the hardware head and tail when this 4559 * function is called in reset flow, so we reuse all desc. 4560 */ 4561 for (j = 0; j < rx_ring->desc_num; j++) 4562 hns3_reuse_buffer(rx_ring, j); 4563 4564 rx_ring->next_to_clean = 0; 4565 rx_ring->next_to_use = 0; 4566 } 4567 4568 hns3_init_tx_ring_tc(priv); 4569 4570 return 0; 4571 } 4572 4573 static void hns3_store_coal(struct hns3_nic_priv *priv) 4574 { 4575 /* ethtool only support setting and querying one coal 4576 * configuration for now, so save the vector 0' coal 4577 * configuration here in order to restore it. 4578 */ 4579 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal, 4580 sizeof(struct hns3_enet_coalesce)); 4581 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal, 4582 sizeof(struct hns3_enet_coalesce)); 4583 } 4584 4585 static void hns3_restore_coal(struct hns3_nic_priv *priv) 4586 { 4587 u16 vector_num = priv->vector_num; 4588 int i; 4589 4590 for (i = 0; i < vector_num; i++) { 4591 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal, 4592 sizeof(struct hns3_enet_coalesce)); 4593 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal, 4594 sizeof(struct hns3_enet_coalesce)); 4595 } 4596 } 4597 4598 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 4599 { 4600 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4601 struct net_device *ndev = kinfo->netdev; 4602 struct hns3_nic_priv *priv = netdev_priv(ndev); 4603 4604 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 4605 return 0; 4606 4607 if (!netif_running(ndev)) 4608 return 0; 4609 4610 return hns3_nic_net_stop(ndev); 4611 } 4612 4613 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 4614 { 4615 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4616 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 4617 int ret = 0; 4618 4619 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4620 4621 if (netif_running(kinfo->netdev)) { 4622 ret = hns3_nic_net_open(kinfo->netdev); 4623 if (ret) { 4624 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4625 netdev_err(kinfo->netdev, 4626 "net up fail, ret=%d!\n", ret); 4627 return ret; 4628 } 4629 } 4630 4631 return ret; 4632 } 4633 4634 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 4635 { 4636 struct net_device *netdev = handle->kinfo.netdev; 4637 struct hns3_nic_priv *priv = netdev_priv(netdev); 4638 int ret; 4639 4640 /* Carrier off reporting is important to ethtool even BEFORE open */ 4641 netif_carrier_off(netdev); 4642 4643 ret = hns3_get_ring_config(priv); 4644 if (ret) 4645 return ret; 4646 4647 ret = hns3_nic_alloc_vector_data(priv); 4648 if (ret) 4649 goto err_put_ring; 4650 4651 hns3_restore_coal(priv); 4652 4653 ret = hns3_nic_init_vector_data(priv); 4654 if (ret) 4655 goto err_dealloc_vector; 4656 4657 ret = hns3_init_all_ring(priv); 4658 if (ret) 4659 goto err_uninit_vector; 4660 4661 /* the device can work without cpu rmap, only aRFS needs it */ 4662 ret = hns3_set_rx_cpu_rmap(netdev); 4663 if (ret) 4664 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 4665 4666 ret = hns3_nic_init_irq(priv); 4667 if (ret) { 4668 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 4669 hns3_free_rx_cpu_rmap(netdev); 4670 goto err_init_irq_fail; 4671 } 4672 4673 if (!hns3_is_phys_func(handle->pdev)) 4674 hns3_init_mac_addr(netdev); 4675 4676 ret = hns3_client_start(handle); 4677 if (ret) { 4678 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4679 goto err_client_start_fail; 4680 } 4681 4682 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4683 4684 return ret; 4685 4686 err_client_start_fail: 4687 hns3_free_rx_cpu_rmap(netdev); 4688 hns3_nic_uninit_irq(priv); 4689 err_init_irq_fail: 4690 hns3_uninit_all_ring(priv); 4691 err_uninit_vector: 4692 hns3_nic_uninit_vector_data(priv); 4693 err_dealloc_vector: 4694 hns3_nic_dealloc_vector_data(priv); 4695 err_put_ring: 4696 hns3_put_ring_config(priv); 4697 4698 return ret; 4699 } 4700 4701 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 4702 { 4703 struct net_device *netdev = handle->kinfo.netdev; 4704 struct hns3_nic_priv *priv = netdev_priv(netdev); 4705 4706 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4707 netdev_warn(netdev, "already uninitialized\n"); 4708 return 0; 4709 } 4710 4711 hns3_free_rx_cpu_rmap(netdev); 4712 hns3_nic_uninit_irq(priv); 4713 hns3_clear_all_ring(handle, true); 4714 hns3_reset_tx_queue(priv->ae_handle); 4715 4716 hns3_nic_uninit_vector_data(priv); 4717 4718 hns3_store_coal(priv); 4719 4720 hns3_nic_dealloc_vector_data(priv); 4721 4722 hns3_uninit_all_ring(priv); 4723 4724 hns3_put_ring_config(priv); 4725 4726 return 0; 4727 } 4728 4729 static int hns3_reset_notify(struct hnae3_handle *handle, 4730 enum hnae3_reset_notify_type type) 4731 { 4732 int ret = 0; 4733 4734 switch (type) { 4735 case HNAE3_UP_CLIENT: 4736 ret = hns3_reset_notify_up_enet(handle); 4737 break; 4738 case HNAE3_DOWN_CLIENT: 4739 ret = hns3_reset_notify_down_enet(handle); 4740 break; 4741 case HNAE3_INIT_CLIENT: 4742 ret = hns3_reset_notify_init_enet(handle); 4743 break; 4744 case HNAE3_UNINIT_CLIENT: 4745 ret = hns3_reset_notify_uninit_enet(handle); 4746 break; 4747 default: 4748 break; 4749 } 4750 4751 return ret; 4752 } 4753 4754 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num, 4755 bool rxfh_configured) 4756 { 4757 int ret; 4758 4759 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num, 4760 rxfh_configured); 4761 if (ret) { 4762 dev_err(&handle->pdev->dev, 4763 "Change tqp num(%u) fail.\n", new_tqp_num); 4764 return ret; 4765 } 4766 4767 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT); 4768 if (ret) 4769 return ret; 4770 4771 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT); 4772 if (ret) 4773 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT); 4774 4775 return ret; 4776 } 4777 4778 int hns3_set_channels(struct net_device *netdev, 4779 struct ethtool_channels *ch) 4780 { 4781 struct hnae3_handle *h = hns3_get_handle(netdev); 4782 struct hnae3_knic_private_info *kinfo = &h->kinfo; 4783 bool rxfh_configured = netif_is_rxfh_configured(netdev); 4784 u32 new_tqp_num = ch->combined_count; 4785 u16 org_tqp_num; 4786 int ret; 4787 4788 if (hns3_nic_resetting(netdev)) 4789 return -EBUSY; 4790 4791 if (ch->rx_count || ch->tx_count) 4792 return -EINVAL; 4793 4794 if (kinfo->tc_info.mqprio_active) { 4795 dev_err(&netdev->dev, 4796 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n"); 4797 return -EINVAL; 4798 } 4799 4800 if (new_tqp_num > hns3_get_max_available_channels(h) || 4801 new_tqp_num < 1) { 4802 dev_err(&netdev->dev, 4803 "Change tqps fail, the tqp range is from 1 to %u", 4804 hns3_get_max_available_channels(h)); 4805 return -EINVAL; 4806 } 4807 4808 if (kinfo->rss_size == new_tqp_num) 4809 return 0; 4810 4811 netif_dbg(h, drv, netdev, 4812 "set channels: tqp_num=%u, rxfh=%d\n", 4813 new_tqp_num, rxfh_configured); 4814 4815 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 4816 if (ret) 4817 return ret; 4818 4819 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 4820 if (ret) 4821 return ret; 4822 4823 org_tqp_num = h->kinfo.num_tqps; 4824 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured); 4825 if (ret) { 4826 int ret1; 4827 4828 netdev_warn(netdev, 4829 "Change channels fail, revert to old value\n"); 4830 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured); 4831 if (ret1) { 4832 netdev_err(netdev, 4833 "revert to old channel fail\n"); 4834 return ret1; 4835 } 4836 4837 return ret; 4838 } 4839 4840 return 0; 4841 } 4842 4843 static const struct hns3_hw_error_info hns3_hw_err[] = { 4844 { .type = HNAE3_PPU_POISON_ERROR, 4845 .msg = "PPU poison" }, 4846 { .type = HNAE3_CMDQ_ECC_ERROR, 4847 .msg = "IMP CMDQ error" }, 4848 { .type = HNAE3_IMP_RD_POISON_ERROR, 4849 .msg = "IMP RD poison" }, 4850 { .type = HNAE3_ROCEE_AXI_RESP_ERROR, 4851 .msg = "ROCEE AXI RESP error" }, 4852 }; 4853 4854 static void hns3_process_hw_error(struct hnae3_handle *handle, 4855 enum hnae3_hw_error_type type) 4856 { 4857 int i; 4858 4859 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) { 4860 if (hns3_hw_err[i].type == type) { 4861 dev_err(&handle->pdev->dev, "Detected %s!\n", 4862 hns3_hw_err[i].msg); 4863 break; 4864 } 4865 } 4866 } 4867 4868 static const struct hnae3_client_ops client_ops = { 4869 .init_instance = hns3_client_init, 4870 .uninit_instance = hns3_client_uninit, 4871 .link_status_change = hns3_link_status_change, 4872 .reset_notify = hns3_reset_notify, 4873 .process_hw_error = hns3_process_hw_error, 4874 }; 4875 4876 /* hns3_init_module - Driver registration routine 4877 * hns3_init_module is the first routine called when the driver is 4878 * loaded. All it does is register with the PCI subsystem. 4879 */ 4880 static int __init hns3_init_module(void) 4881 { 4882 int ret; 4883 4884 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 4885 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 4886 4887 client.type = HNAE3_CLIENT_KNIC; 4888 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s", 4889 hns3_driver_name); 4890 4891 client.ops = &client_ops; 4892 4893 INIT_LIST_HEAD(&client.node); 4894 4895 hns3_dbg_register_debugfs(hns3_driver_name); 4896 4897 ret = hnae3_register_client(&client); 4898 if (ret) 4899 goto err_reg_client; 4900 4901 ret = pci_register_driver(&hns3_driver); 4902 if (ret) 4903 goto err_reg_driver; 4904 4905 return ret; 4906 4907 err_reg_driver: 4908 hnae3_unregister_client(&client); 4909 err_reg_client: 4910 hns3_dbg_unregister_debugfs(); 4911 return ret; 4912 } 4913 module_init(hns3_init_module); 4914 4915 /* hns3_exit_module - Driver exit cleanup routine 4916 * hns3_exit_module is called just before the driver is removed 4917 * from memory. 4918 */ 4919 static void __exit hns3_exit_module(void) 4920 { 4921 pci_unregister_driver(&hns3_driver); 4922 hnae3_unregister_client(&client); 4923 hns3_dbg_unregister_debugfs(); 4924 } 4925 module_exit(hns3_exit_module); 4926 4927 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 4928 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 4929 MODULE_LICENSE("GPL"); 4930 MODULE_ALIAS("pci:hns-nic"); 4931