1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #ifdef CONFIG_RFS_ACCEL 8 #include <linux/cpu_rmap.h> 9 #endif 10 #include <linux/if_vlan.h> 11 #include <linux/irq.h> 12 #include <linux/ip.h> 13 #include <linux/ipv6.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/aer.h> 17 #include <linux/skbuff.h> 18 #include <linux/sctp.h> 19 #include <net/gre.h> 20 #include <net/ip6_checksum.h> 21 #include <net/pkt_cls.h> 22 #include <net/tcp.h> 23 #include <net/vxlan.h> 24 #include <net/geneve.h> 25 26 #include "hnae3.h" 27 #include "hns3_enet.h" 28 /* All hns3 tracepoints are defined by the include below, which 29 * must be included exactly once across the whole kernel with 30 * CREATE_TRACE_POINTS defined 31 */ 32 #define CREATE_TRACE_POINTS 33 #include "hns3_trace.h" 34 35 #define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift))) 36 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE) 37 38 #define hns3_rl_err(fmt, ...) \ 39 do { \ 40 if (net_ratelimit()) \ 41 netdev_err(fmt, ##__VA_ARGS__); \ 42 } while (0) 43 44 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force); 45 46 static const char hns3_driver_name[] = "hns3"; 47 static const char hns3_driver_string[] = 48 "Hisilicon Ethernet Network Driver for Hip08 Family"; 49 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 50 static struct hnae3_client client; 51 52 static int debug = -1; 53 module_param(debug, int, 0); 54 MODULE_PARM_DESC(debug, " Network interface message level setting"); 55 56 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 57 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) 58 59 #define HNS3_INNER_VLAN_TAG 1 60 #define HNS3_OUTER_VLAN_TAG 2 61 62 #define HNS3_MIN_TX_LEN 33U 63 64 /* hns3_pci_tbl - PCI Device ID Table 65 * 66 * Last entry must be all 0s 67 * 68 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 69 * Class, Class Mask, private data (not used) } 70 */ 71 static const struct pci_device_id hns3_pci_tbl[] = { 72 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 75 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 77 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 79 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 80 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 81 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 83 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 84 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 85 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 86 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 88 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 89 /* required last entry */ 90 {0, } 91 }; 92 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 93 94 static irqreturn_t hns3_irq_handle(int irq, void *vector) 95 { 96 struct hns3_enet_tqp_vector *tqp_vector = vector; 97 98 napi_schedule_irqoff(&tqp_vector->napi); 99 100 return IRQ_HANDLED; 101 } 102 103 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 104 { 105 struct hns3_enet_tqp_vector *tqp_vectors; 106 unsigned int i; 107 108 for (i = 0; i < priv->vector_num; i++) { 109 tqp_vectors = &priv->tqp_vector[i]; 110 111 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 112 continue; 113 114 /* clear the affinity mask */ 115 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 116 117 /* release the irq resource */ 118 free_irq(tqp_vectors->vector_irq, tqp_vectors); 119 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 120 } 121 } 122 123 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 124 { 125 struct hns3_enet_tqp_vector *tqp_vectors; 126 int txrx_int_idx = 0; 127 int rx_int_idx = 0; 128 int tx_int_idx = 0; 129 unsigned int i; 130 int ret; 131 132 for (i = 0; i < priv->vector_num; i++) { 133 tqp_vectors = &priv->tqp_vector[i]; 134 135 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 136 continue; 137 138 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 139 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 140 "%s-%s-%s-%d", hns3_driver_name, 141 pci_name(priv->ae_handle->pdev), 142 "TxRx", txrx_int_idx++); 143 txrx_int_idx++; 144 } else if (tqp_vectors->rx_group.ring) { 145 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 146 "%s-%s-%s-%d", hns3_driver_name, 147 pci_name(priv->ae_handle->pdev), 148 "Rx", rx_int_idx++); 149 } else if (tqp_vectors->tx_group.ring) { 150 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 151 "%s-%s-%s-%d", hns3_driver_name, 152 pci_name(priv->ae_handle->pdev), 153 "Tx", tx_int_idx++); 154 } else { 155 /* Skip this unused q_vector */ 156 continue; 157 } 158 159 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 160 161 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN); 162 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 163 tqp_vectors->name, tqp_vectors); 164 if (ret) { 165 netdev_err(priv->netdev, "request irq(%d) fail\n", 166 tqp_vectors->vector_irq); 167 hns3_nic_uninit_irq(priv); 168 return ret; 169 } 170 171 irq_set_affinity_hint(tqp_vectors->vector_irq, 172 &tqp_vectors->affinity_mask); 173 174 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 175 } 176 177 return 0; 178 } 179 180 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 181 u32 mask_en) 182 { 183 writel(mask_en, tqp_vector->mask_addr); 184 } 185 186 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 187 { 188 napi_enable(&tqp_vector->napi); 189 enable_irq(tqp_vector->vector_irq); 190 191 /* enable vector */ 192 hns3_mask_vector_irq(tqp_vector, 1); 193 } 194 195 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 196 { 197 /* disable vector */ 198 hns3_mask_vector_irq(tqp_vector, 0); 199 200 disable_irq(tqp_vector->vector_irq); 201 napi_disable(&tqp_vector->napi); 202 } 203 204 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 205 u32 rl_value) 206 { 207 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 208 209 /* this defines the configuration for RL (Interrupt Rate Limiter). 210 * Rl defines rate of interrupts i.e. number of interrupts-per-second 211 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 212 */ 213 214 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable && 215 !tqp_vector->rx_group.coal.adapt_enable) 216 /* According to the hardware, the range of rl_reg is 217 * 0-59 and the unit is 4. 218 */ 219 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 220 221 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 222 } 223 224 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 225 u32 gl_value) 226 { 227 u32 new_val; 228 229 if (tqp_vector->rx_group.coal.unit_1us) 230 new_val = gl_value | HNS3_INT_GL_1US; 231 else 232 new_val = hns3_gl_usec_to_reg(gl_value); 233 234 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 235 } 236 237 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 238 u32 gl_value) 239 { 240 u32 new_val; 241 242 if (tqp_vector->tx_group.coal.unit_1us) 243 new_val = gl_value | HNS3_INT_GL_1US; 244 else 245 new_val = hns3_gl_usec_to_reg(gl_value); 246 247 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 248 } 249 250 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector, 251 u32 ql_value) 252 { 253 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET); 254 } 255 256 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector, 257 u32 ql_value) 258 { 259 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET); 260 } 261 262 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector, 263 struct hns3_nic_priv *priv) 264 { 265 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 266 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 267 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 268 269 /* initialize the configuration for interrupt coalescing. 270 * 1. GL (Interrupt Gap Limiter) 271 * 2. RL (Interrupt Rate Limiter) 272 * 3. QL (Interrupt Quantity Limiter) 273 * 274 * Default: enable interrupt coalescing self-adaptive and GL 275 */ 276 tx_coal->adapt_enable = 1; 277 rx_coal->adapt_enable = 1; 278 279 tx_coal->int_gl = HNS3_INT_GL_50K; 280 rx_coal->int_gl = HNS3_INT_GL_50K; 281 282 rx_coal->flow_level = HNS3_FLOW_LOW; 283 tx_coal->flow_level = HNS3_FLOW_LOW; 284 285 /* device version above V3(include V3), GL can configure 1us 286 * unit, so uses 1us unit. 287 */ 288 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) { 289 tx_coal->unit_1us = 1; 290 rx_coal->unit_1us = 1; 291 } 292 293 if (ae_dev->dev_specs.int_ql_max) { 294 tx_coal->ql_enable = 1; 295 rx_coal->ql_enable = 1; 296 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 297 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 298 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 299 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 300 } 301 } 302 303 static void 304 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 305 struct hns3_nic_priv *priv) 306 { 307 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 308 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 309 struct hnae3_handle *h = priv->ae_handle; 310 311 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl); 312 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl); 313 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 314 315 if (tx_coal->ql_enable) 316 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql); 317 318 if (rx_coal->ql_enable) 319 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql); 320 } 321 322 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 323 { 324 struct hnae3_handle *h = hns3_get_handle(netdev); 325 struct hnae3_knic_private_info *kinfo = &h->kinfo; 326 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc; 327 int i, ret; 328 329 if (kinfo->num_tc <= 1) { 330 netdev_reset_tc(netdev); 331 } else { 332 ret = netdev_set_num_tc(netdev, kinfo->num_tc); 333 if (ret) { 334 netdev_err(netdev, 335 "netdev_set_num_tc fail, ret=%d!\n", ret); 336 return ret; 337 } 338 339 for (i = 0; i < HNAE3_MAX_TC; i++) { 340 if (!kinfo->tc_info[i].enable) 341 continue; 342 343 netdev_set_tc_queue(netdev, 344 kinfo->tc_info[i].tc, 345 kinfo->tc_info[i].tqp_count, 346 kinfo->tc_info[i].tqp_offset); 347 } 348 } 349 350 ret = netif_set_real_num_tx_queues(netdev, queue_size); 351 if (ret) { 352 netdev_err(netdev, 353 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret); 354 return ret; 355 } 356 357 ret = netif_set_real_num_rx_queues(netdev, queue_size); 358 if (ret) { 359 netdev_err(netdev, 360 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 361 return ret; 362 } 363 364 return 0; 365 } 366 367 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 368 { 369 u16 alloc_tqps, max_rss_size, rss_size; 370 371 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 372 rss_size = alloc_tqps / h->kinfo.num_tc; 373 374 return min_t(u16, rss_size, max_rss_size); 375 } 376 377 static void hns3_tqp_enable(struct hnae3_queue *tqp) 378 { 379 u32 rcb_reg; 380 381 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 382 rcb_reg |= BIT(HNS3_RING_EN_B); 383 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 384 } 385 386 static void hns3_tqp_disable(struct hnae3_queue *tqp) 387 { 388 u32 rcb_reg; 389 390 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 391 rcb_reg &= ~BIT(HNS3_RING_EN_B); 392 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 393 } 394 395 static void hns3_free_rx_cpu_rmap(struct net_device *netdev) 396 { 397 #ifdef CONFIG_RFS_ACCEL 398 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 399 netdev->rx_cpu_rmap = NULL; 400 #endif 401 } 402 403 static int hns3_set_rx_cpu_rmap(struct net_device *netdev) 404 { 405 #ifdef CONFIG_RFS_ACCEL 406 struct hns3_nic_priv *priv = netdev_priv(netdev); 407 struct hns3_enet_tqp_vector *tqp_vector; 408 int i, ret; 409 410 if (!netdev->rx_cpu_rmap) { 411 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num); 412 if (!netdev->rx_cpu_rmap) 413 return -ENOMEM; 414 } 415 416 for (i = 0; i < priv->vector_num; i++) { 417 tqp_vector = &priv->tqp_vector[i]; 418 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap, 419 tqp_vector->vector_irq); 420 if (ret) { 421 hns3_free_rx_cpu_rmap(netdev); 422 return ret; 423 } 424 } 425 #endif 426 return 0; 427 } 428 429 static int hns3_nic_net_up(struct net_device *netdev) 430 { 431 struct hns3_nic_priv *priv = netdev_priv(netdev); 432 struct hnae3_handle *h = priv->ae_handle; 433 int i, j; 434 int ret; 435 436 ret = hns3_nic_reset_all_ring(h); 437 if (ret) 438 return ret; 439 440 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 441 442 /* enable the vectors */ 443 for (i = 0; i < priv->vector_num; i++) 444 hns3_vector_enable(&priv->tqp_vector[i]); 445 446 /* enable rcb */ 447 for (j = 0; j < h->kinfo.num_tqps; j++) 448 hns3_tqp_enable(h->kinfo.tqp[j]); 449 450 /* start the ae_dev */ 451 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 452 if (ret) { 453 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 454 while (j--) 455 hns3_tqp_disable(h->kinfo.tqp[j]); 456 457 for (j = i - 1; j >= 0; j--) 458 hns3_vector_disable(&priv->tqp_vector[j]); 459 } 460 461 return ret; 462 } 463 464 static void hns3_config_xps(struct hns3_nic_priv *priv) 465 { 466 int i; 467 468 for (i = 0; i < priv->vector_num; i++) { 469 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 470 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 471 472 while (ring) { 473 int ret; 474 475 ret = netif_set_xps_queue(priv->netdev, 476 &tqp_vector->affinity_mask, 477 ring->tqp->tqp_index); 478 if (ret) 479 netdev_warn(priv->netdev, 480 "set xps queue failed: %d", ret); 481 482 ring = ring->next; 483 } 484 } 485 } 486 487 static int hns3_nic_net_open(struct net_device *netdev) 488 { 489 struct hns3_nic_priv *priv = netdev_priv(netdev); 490 struct hnae3_handle *h = hns3_get_handle(netdev); 491 struct hnae3_knic_private_info *kinfo; 492 int i, ret; 493 494 if (hns3_nic_resetting(netdev)) 495 return -EBUSY; 496 497 netif_carrier_off(netdev); 498 499 ret = hns3_nic_set_real_num_queue(netdev); 500 if (ret) 501 return ret; 502 503 ret = hns3_nic_net_up(netdev); 504 if (ret) { 505 netdev_err(netdev, "net up fail, ret=%d!\n", ret); 506 return ret; 507 } 508 509 kinfo = &h->kinfo; 510 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 511 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]); 512 513 if (h->ae_algo->ops->set_timer_task) 514 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 515 516 hns3_config_xps(priv); 517 518 netif_dbg(h, drv, netdev, "net open\n"); 519 520 return 0; 521 } 522 523 static void hns3_reset_tx_queue(struct hnae3_handle *h) 524 { 525 struct net_device *ndev = h->kinfo.netdev; 526 struct hns3_nic_priv *priv = netdev_priv(ndev); 527 struct netdev_queue *dev_queue; 528 u32 i; 529 530 for (i = 0; i < h->kinfo.num_tqps; i++) { 531 dev_queue = netdev_get_tx_queue(ndev, 532 priv->ring[i].queue_index); 533 netdev_tx_reset_queue(dev_queue); 534 } 535 } 536 537 static void hns3_nic_net_down(struct net_device *netdev) 538 { 539 struct hns3_nic_priv *priv = netdev_priv(netdev); 540 struct hnae3_handle *h = hns3_get_handle(netdev); 541 const struct hnae3_ae_ops *ops; 542 int i; 543 544 /* disable vectors */ 545 for (i = 0; i < priv->vector_num; i++) 546 hns3_vector_disable(&priv->tqp_vector[i]); 547 548 /* disable rcb */ 549 for (i = 0; i < h->kinfo.num_tqps; i++) 550 hns3_tqp_disable(h->kinfo.tqp[i]); 551 552 /* stop ae_dev */ 553 ops = priv->ae_handle->ae_algo->ops; 554 if (ops->stop) 555 ops->stop(priv->ae_handle); 556 557 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 558 * during reset process, because driver may not be able 559 * to disable the ring through firmware when downing the netdev. 560 */ 561 if (!hns3_nic_resetting(netdev)) 562 hns3_clear_all_ring(priv->ae_handle, false); 563 564 hns3_reset_tx_queue(priv->ae_handle); 565 } 566 567 static int hns3_nic_net_stop(struct net_device *netdev) 568 { 569 struct hns3_nic_priv *priv = netdev_priv(netdev); 570 struct hnae3_handle *h = hns3_get_handle(netdev); 571 572 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 573 return 0; 574 575 netif_dbg(h, drv, netdev, "net stop\n"); 576 577 if (h->ae_algo->ops->set_timer_task) 578 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 579 580 netif_tx_stop_all_queues(netdev); 581 netif_carrier_off(netdev); 582 583 hns3_nic_net_down(netdev); 584 585 return 0; 586 } 587 588 static int hns3_nic_uc_sync(struct net_device *netdev, 589 const unsigned char *addr) 590 { 591 struct hnae3_handle *h = hns3_get_handle(netdev); 592 593 if (h->ae_algo->ops->add_uc_addr) 594 return h->ae_algo->ops->add_uc_addr(h, addr); 595 596 return 0; 597 } 598 599 static int hns3_nic_uc_unsync(struct net_device *netdev, 600 const unsigned char *addr) 601 { 602 struct hnae3_handle *h = hns3_get_handle(netdev); 603 604 /* need ignore the request of removing device address, because 605 * we store the device address and other addresses of uc list 606 * in the function's mac filter list. 607 */ 608 if (ether_addr_equal(addr, netdev->dev_addr)) 609 return 0; 610 611 if (h->ae_algo->ops->rm_uc_addr) 612 return h->ae_algo->ops->rm_uc_addr(h, addr); 613 614 return 0; 615 } 616 617 static int hns3_nic_mc_sync(struct net_device *netdev, 618 const unsigned char *addr) 619 { 620 struct hnae3_handle *h = hns3_get_handle(netdev); 621 622 if (h->ae_algo->ops->add_mc_addr) 623 return h->ae_algo->ops->add_mc_addr(h, addr); 624 625 return 0; 626 } 627 628 static int hns3_nic_mc_unsync(struct net_device *netdev, 629 const unsigned char *addr) 630 { 631 struct hnae3_handle *h = hns3_get_handle(netdev); 632 633 if (h->ae_algo->ops->rm_mc_addr) 634 return h->ae_algo->ops->rm_mc_addr(h, addr); 635 636 return 0; 637 } 638 639 static u8 hns3_get_netdev_flags(struct net_device *netdev) 640 { 641 u8 flags = 0; 642 643 if (netdev->flags & IFF_PROMISC) { 644 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 645 } else { 646 flags |= HNAE3_VLAN_FLTR; 647 if (netdev->flags & IFF_ALLMULTI) 648 flags |= HNAE3_USER_MPE; 649 } 650 651 return flags; 652 } 653 654 static void hns3_nic_set_rx_mode(struct net_device *netdev) 655 { 656 struct hnae3_handle *h = hns3_get_handle(netdev); 657 u8 new_flags; 658 659 new_flags = hns3_get_netdev_flags(netdev); 660 661 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 662 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync); 663 664 /* User mode Promisc mode enable and vlan filtering is disabled to 665 * let all packets in. 666 */ 667 h->netdev_flags = new_flags; 668 hns3_request_update_promisc_mode(h); 669 } 670 671 void hns3_request_update_promisc_mode(struct hnae3_handle *handle) 672 { 673 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 674 675 if (ops->request_update_promisc_mode) 676 ops->request_update_promisc_mode(handle); 677 } 678 679 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable) 680 { 681 struct hns3_nic_priv *priv = netdev_priv(netdev); 682 struct hnae3_handle *h = priv->ae_handle; 683 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 684 bool last_state; 685 686 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 && 687 h->ae_algo->ops->enable_vlan_filter) { 688 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false; 689 if (enable != last_state) { 690 netdev_info(netdev, 691 "%s vlan filter\n", 692 enable ? "enable" : "disable"); 693 h->ae_algo->ops->enable_vlan_filter(h, enable); 694 } 695 } 696 } 697 698 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs, 699 u16 *mss, u32 *type_cs_vlan_tso) 700 { 701 u32 l4_offset, hdr_len; 702 union l3_hdr_info l3; 703 union l4_hdr_info l4; 704 u32 l4_paylen; 705 int ret; 706 707 if (!skb_is_gso(skb)) 708 return 0; 709 710 ret = skb_cow_head(skb, 0); 711 if (unlikely(ret < 0)) 712 return ret; 713 714 l3.hdr = skb_network_header(skb); 715 l4.hdr = skb_transport_header(skb); 716 717 /* Software should clear the IPv4's checksum field when tso is 718 * needed. 719 */ 720 if (l3.v4->version == 4) 721 l3.v4->check = 0; 722 723 /* tunnel packet */ 724 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 725 SKB_GSO_GRE_CSUM | 726 SKB_GSO_UDP_TUNNEL | 727 SKB_GSO_UDP_TUNNEL_CSUM)) { 728 /* reset l3&l4 pointers from outer to inner headers */ 729 l3.hdr = skb_inner_network_header(skb); 730 l4.hdr = skb_inner_transport_header(skb); 731 732 /* Software should clear the IPv4's checksum field when 733 * tso is needed. 734 */ 735 if (l3.v4->version == 4) 736 l3.v4->check = 0; 737 } 738 739 /* normal or tunnel packet */ 740 l4_offset = l4.hdr - skb->data; 741 742 /* remove payload length from inner pseudo checksum when tso */ 743 l4_paylen = skb->len - l4_offset; 744 745 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 746 hdr_len = sizeof(*l4.udp) + l4_offset; 747 csum_replace_by_diff(&l4.udp->check, 748 (__force __wsum)htonl(l4_paylen)); 749 } else { 750 hdr_len = (l4.tcp->doff << 2) + l4_offset; 751 csum_replace_by_diff(&l4.tcp->check, 752 (__force __wsum)htonl(l4_paylen)); 753 } 754 755 /* find the txbd field values */ 756 *paylen_fdop_ol4cs = skb->len - hdr_len; 757 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 758 759 /* offload outer UDP header checksum */ 760 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM) 761 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1); 762 763 /* get MSS for TSO */ 764 *mss = skb_shinfo(skb)->gso_size; 765 766 trace_hns3_tso(skb); 767 768 return 0; 769 } 770 771 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 772 u8 *il4_proto) 773 { 774 union l3_hdr_info l3; 775 unsigned char *l4_hdr; 776 unsigned char *exthdr; 777 u8 l4_proto_tmp; 778 __be16 frag_off; 779 780 /* find outer header point */ 781 l3.hdr = skb_network_header(skb); 782 l4_hdr = skb_transport_header(skb); 783 784 if (skb->protocol == htons(ETH_P_IPV6)) { 785 exthdr = l3.hdr + sizeof(*l3.v6); 786 l4_proto_tmp = l3.v6->nexthdr; 787 if (l4_hdr != exthdr) 788 ipv6_skip_exthdr(skb, exthdr - skb->data, 789 &l4_proto_tmp, &frag_off); 790 } else if (skb->protocol == htons(ETH_P_IP)) { 791 l4_proto_tmp = l3.v4->protocol; 792 } else { 793 return -EINVAL; 794 } 795 796 *ol4_proto = l4_proto_tmp; 797 798 /* tunnel packet */ 799 if (!skb->encapsulation) { 800 *il4_proto = 0; 801 return 0; 802 } 803 804 /* find inner header point */ 805 l3.hdr = skb_inner_network_header(skb); 806 l4_hdr = skb_inner_transport_header(skb); 807 808 if (l3.v6->version == 6) { 809 exthdr = l3.hdr + sizeof(*l3.v6); 810 l4_proto_tmp = l3.v6->nexthdr; 811 if (l4_hdr != exthdr) 812 ipv6_skip_exthdr(skb, exthdr - skb->data, 813 &l4_proto_tmp, &frag_off); 814 } else if (l3.v4->version == 4) { 815 l4_proto_tmp = l3.v4->protocol; 816 } 817 818 *il4_proto = l4_proto_tmp; 819 820 return 0; 821 } 822 823 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 824 * and it is udp packet, which has a dest port as the IANA assigned. 825 * the hardware is expected to do the checksum offload, but the 826 * hardware will not do the checksum offload when udp dest port is 827 * 4789 or 6081. 828 */ 829 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 830 { 831 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 832 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 833 union l4_hdr_info l4; 834 835 /* device version above V3(include V3), the hardware can 836 * do this checksum offload. 837 */ 838 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 839 return false; 840 841 l4.hdr = skb_transport_header(skb); 842 843 if (!(!skb->encapsulation && 844 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) || 845 l4.udp->dest == htons(GENEVE_UDP_PORT)))) 846 return false; 847 848 skb_checksum_help(skb); 849 850 return true; 851 } 852 853 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 854 u32 *ol_type_vlan_len_msec) 855 { 856 u32 l2_len, l3_len, l4_len; 857 unsigned char *il2_hdr; 858 union l3_hdr_info l3; 859 union l4_hdr_info l4; 860 861 l3.hdr = skb_network_header(skb); 862 l4.hdr = skb_transport_header(skb); 863 864 /* compute OL2 header size, defined in 2 Bytes */ 865 l2_len = l3.hdr - skb->data; 866 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1); 867 868 /* compute OL3 header size, defined in 4 Bytes */ 869 l3_len = l4.hdr - l3.hdr; 870 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2); 871 872 il2_hdr = skb_inner_mac_header(skb); 873 /* compute OL4 header size, defined in 4 Bytes */ 874 l4_len = il2_hdr - l4.hdr; 875 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2); 876 877 /* define outer network header type */ 878 if (skb->protocol == htons(ETH_P_IP)) { 879 if (skb_is_gso(skb)) 880 hns3_set_field(*ol_type_vlan_len_msec, 881 HNS3_TXD_OL3T_S, 882 HNS3_OL3T_IPV4_CSUM); 883 else 884 hns3_set_field(*ol_type_vlan_len_msec, 885 HNS3_TXD_OL3T_S, 886 HNS3_OL3T_IPV4_NO_CSUM); 887 888 } else if (skb->protocol == htons(ETH_P_IPV6)) { 889 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 890 HNS3_OL3T_IPV6); 891 } 892 893 if (ol4_proto == IPPROTO_UDP) 894 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 895 HNS3_TUN_MAC_IN_UDP); 896 else if (ol4_proto == IPPROTO_GRE) 897 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 898 HNS3_TUN_NVGRE); 899 } 900 901 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 902 u8 il4_proto, u32 *type_cs_vlan_tso, 903 u32 *ol_type_vlan_len_msec) 904 { 905 unsigned char *l2_hdr = skb->data; 906 u32 l4_proto = ol4_proto; 907 union l4_hdr_info l4; 908 union l3_hdr_info l3; 909 u32 l2_len, l3_len; 910 911 l4.hdr = skb_transport_header(skb); 912 l3.hdr = skb_network_header(skb); 913 914 /* handle encapsulation skb */ 915 if (skb->encapsulation) { 916 /* If this is a not UDP/GRE encapsulation skb */ 917 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) { 918 /* drop the skb tunnel packet if hardware don't support, 919 * because hardware can't calculate csum when TSO. 920 */ 921 if (skb_is_gso(skb)) 922 return -EDOM; 923 924 /* the stack computes the IP header already, 925 * driver calculate l4 checksum when not TSO. 926 */ 927 skb_checksum_help(skb); 928 return 0; 929 } 930 931 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec); 932 933 /* switch to inner header */ 934 l2_hdr = skb_inner_mac_header(skb); 935 l3.hdr = skb_inner_network_header(skb); 936 l4.hdr = skb_inner_transport_header(skb); 937 l4_proto = il4_proto; 938 } 939 940 if (l3.v4->version == 4) { 941 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 942 HNS3_L3T_IPV4); 943 944 /* the stack computes the IP header already, the only time we 945 * need the hardware to recompute it is in the case of TSO. 946 */ 947 if (skb_is_gso(skb)) 948 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 949 } else if (l3.v6->version == 6) { 950 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 951 HNS3_L3T_IPV6); 952 } 953 954 /* compute inner(/normal) L2 header size, defined in 2 Bytes */ 955 l2_len = l3.hdr - l2_hdr; 956 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 957 958 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 959 l3_len = l4.hdr - l3.hdr; 960 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 961 962 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 963 switch (l4_proto) { 964 case IPPROTO_TCP: 965 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 966 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 967 HNS3_L4T_TCP); 968 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 969 l4.tcp->doff); 970 break; 971 case IPPROTO_UDP: 972 if (hns3_tunnel_csum_bug(skb)) 973 break; 974 975 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 976 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 977 HNS3_L4T_UDP); 978 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 979 (sizeof(struct udphdr) >> 2)); 980 break; 981 case IPPROTO_SCTP: 982 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 983 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 984 HNS3_L4T_SCTP); 985 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 986 (sizeof(struct sctphdr) >> 2)); 987 break; 988 default: 989 /* drop the skb tunnel packet if hardware don't support, 990 * because hardware can't calculate csum when TSO. 991 */ 992 if (skb_is_gso(skb)) 993 return -EDOM; 994 995 /* the stack computes the IP header already, 996 * driver calculate l4 checksum when not TSO. 997 */ 998 skb_checksum_help(skb); 999 return 0; 1000 } 1001 1002 return 0; 1003 } 1004 1005 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring, 1006 struct sk_buff *skb) 1007 { 1008 struct hnae3_handle *handle = tx_ring->tqp->handle; 1009 struct vlan_ethhdr *vhdr; 1010 int rc; 1011 1012 if (!(skb->protocol == htons(ETH_P_8021Q) || 1013 skb_vlan_tag_present(skb))) 1014 return 0; 1015 1016 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN 1017 * header is allowed in skb, otherwise it will cause RAS error. 1018 */ 1019 if (unlikely(skb_vlan_tagged_multi(skb) && 1020 handle->port_base_vlan_state == 1021 HNAE3_PORT_BASE_VLAN_ENABLE)) 1022 return -EINVAL; 1023 1024 if (skb->protocol == htons(ETH_P_8021Q) && 1025 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 1026 /* When HW VLAN acceleration is turned off, and the stack 1027 * sets the protocol to 802.1q, the driver just need to 1028 * set the protocol to the encapsulated ethertype. 1029 */ 1030 skb->protocol = vlan_get_protocol(skb); 1031 return 0; 1032 } 1033 1034 if (skb_vlan_tag_present(skb)) { 1035 /* Based on hw strategy, use out_vtag in two layer tag case, 1036 * and use inner_vtag in one tag case. 1037 */ 1038 if (skb->protocol == htons(ETH_P_8021Q) && 1039 handle->port_base_vlan_state == 1040 HNAE3_PORT_BASE_VLAN_DISABLE) 1041 rc = HNS3_OUTER_VLAN_TAG; 1042 else 1043 rc = HNS3_INNER_VLAN_TAG; 1044 1045 skb->protocol = vlan_get_protocol(skb); 1046 return rc; 1047 } 1048 1049 rc = skb_cow_head(skb, 0); 1050 if (unlikely(rc < 0)) 1051 return rc; 1052 1053 vhdr = (struct vlan_ethhdr *)skb->data; 1054 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT) 1055 & VLAN_PRIO_MASK); 1056 1057 skb->protocol = vlan_get_protocol(skb); 1058 return 0; 1059 } 1060 1061 /* check if the hardware is capable of checksum offloading */ 1062 static bool hns3_check_hw_tx_csum(struct sk_buff *skb) 1063 { 1064 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 1065 1066 /* Kindly note, due to backward compatibility of the TX descriptor, 1067 * HW checksum of the non-IP packets and GSO packets is handled at 1068 * different place in the following code 1069 */ 1070 if (skb->csum_not_inet || skb_is_gso(skb) || 1071 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state)) 1072 return false; 1073 1074 return true; 1075 } 1076 1077 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring, 1078 struct sk_buff *skb, struct hns3_desc *desc) 1079 { 1080 u32 ol_type_vlan_len_msec = 0; 1081 u32 paylen_ol4cs = skb->len; 1082 u32 type_cs_vlan_tso = 0; 1083 u16 mss_hw_csum = 0; 1084 u16 inner_vtag = 0; 1085 u16 out_vtag = 0; 1086 int ret; 1087 1088 ret = hns3_handle_vtags(ring, skb); 1089 if (unlikely(ret < 0)) { 1090 u64_stats_update_begin(&ring->syncp); 1091 ring->stats.tx_vlan_err++; 1092 u64_stats_update_end(&ring->syncp); 1093 return ret; 1094 } else if (ret == HNS3_INNER_VLAN_TAG) { 1095 inner_vtag = skb_vlan_tag_get(skb); 1096 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1097 VLAN_PRIO_MASK; 1098 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1); 1099 } else if (ret == HNS3_OUTER_VLAN_TAG) { 1100 out_vtag = skb_vlan_tag_get(skb); 1101 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1102 VLAN_PRIO_MASK; 1103 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B, 1104 1); 1105 } 1106 1107 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1108 u8 ol4_proto, il4_proto; 1109 1110 if (hns3_check_hw_tx_csum(skb)) { 1111 /* set checksum start and offset, defined in 2 Bytes */ 1112 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_CSUM_START_S, 1113 skb_checksum_start_offset(skb) >> 1); 1114 hns3_set_field(ol_type_vlan_len_msec, 1115 HNS3_TXD_CSUM_OFFSET_S, 1116 skb->csum_offset >> 1); 1117 mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B); 1118 goto out_hw_tx_csum; 1119 } 1120 1121 skb_reset_mac_len(skb); 1122 1123 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1124 if (unlikely(ret < 0)) { 1125 u64_stats_update_begin(&ring->syncp); 1126 ring->stats.tx_l4_proto_err++; 1127 u64_stats_update_end(&ring->syncp); 1128 return ret; 1129 } 1130 1131 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto, 1132 &type_cs_vlan_tso, 1133 &ol_type_vlan_len_msec); 1134 if (unlikely(ret < 0)) { 1135 u64_stats_update_begin(&ring->syncp); 1136 ring->stats.tx_l2l3l4_err++; 1137 u64_stats_update_end(&ring->syncp); 1138 return ret; 1139 } 1140 1141 ret = hns3_set_tso(skb, &paylen_ol4cs, &mss_hw_csum, 1142 &type_cs_vlan_tso); 1143 if (unlikely(ret < 0)) { 1144 u64_stats_update_begin(&ring->syncp); 1145 ring->stats.tx_tso_err++; 1146 u64_stats_update_end(&ring->syncp); 1147 return ret; 1148 } 1149 } 1150 1151 out_hw_tx_csum: 1152 /* Set txbd */ 1153 desc->tx.ol_type_vlan_len_msec = 1154 cpu_to_le32(ol_type_vlan_len_msec); 1155 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso); 1156 desc->tx.paylen_ol4cs = cpu_to_le32(paylen_ol4cs); 1157 desc->tx.mss_hw_csum = cpu_to_le16(mss_hw_csum); 1158 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1159 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1160 1161 return 0; 1162 } 1163 1164 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 1165 unsigned int size, enum hns_desc_type type) 1166 { 1167 #define HNS3_LIKELY_BD_NUM 1 1168 1169 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1170 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1171 struct device *dev = ring_to_dev(ring); 1172 skb_frag_t *frag; 1173 unsigned int frag_buf_num; 1174 int k, sizeoflast; 1175 dma_addr_t dma; 1176 1177 if (type == DESC_TYPE_FRAGLIST_SKB || 1178 type == DESC_TYPE_SKB) { 1179 struct sk_buff *skb = (struct sk_buff *)priv; 1180 1181 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1182 } else { 1183 frag = (skb_frag_t *)priv; 1184 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1185 } 1186 1187 if (unlikely(dma_mapping_error(dev, dma))) { 1188 u64_stats_update_begin(&ring->syncp); 1189 ring->stats.sw_err_cnt++; 1190 u64_stats_update_end(&ring->syncp); 1191 return -ENOMEM; 1192 } 1193 1194 desc_cb->priv = priv; 1195 desc_cb->length = size; 1196 desc_cb->dma = dma; 1197 desc_cb->type = type; 1198 1199 if (likely(size <= HNS3_MAX_BD_SIZE)) { 1200 desc->addr = cpu_to_le64(dma); 1201 desc->tx.send_size = cpu_to_le16(size); 1202 desc->tx.bdtp_fe_sc_vld_ra_ri = 1203 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1204 1205 trace_hns3_tx_desc(ring, ring->next_to_use); 1206 ring_ptr_move_fw(ring, next_to_use); 1207 return HNS3_LIKELY_BD_NUM; 1208 } 1209 1210 frag_buf_num = hns3_tx_bd_count(size); 1211 sizeoflast = size % HNS3_MAX_BD_SIZE; 1212 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1213 1214 /* When frag size is bigger than hardware limit, split this frag */ 1215 for (k = 0; k < frag_buf_num; k++) { 1216 /* now, fill the descriptor */ 1217 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1218 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1219 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1220 desc->tx.bdtp_fe_sc_vld_ra_ri = 1221 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1222 1223 trace_hns3_tx_desc(ring, ring->next_to_use); 1224 /* move ring pointer to next */ 1225 ring_ptr_move_fw(ring, next_to_use); 1226 1227 desc = &ring->desc[ring->next_to_use]; 1228 } 1229 1230 return frag_buf_num; 1231 } 1232 1233 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1234 unsigned int bd_num) 1235 { 1236 unsigned int size; 1237 int i; 1238 1239 size = skb_headlen(skb); 1240 while (size > HNS3_MAX_BD_SIZE) { 1241 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1242 size -= HNS3_MAX_BD_SIZE; 1243 1244 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1245 return bd_num; 1246 } 1247 1248 if (size) { 1249 bd_size[bd_num++] = size; 1250 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1251 return bd_num; 1252 } 1253 1254 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1255 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1256 size = skb_frag_size(frag); 1257 if (!size) 1258 continue; 1259 1260 while (size > HNS3_MAX_BD_SIZE) { 1261 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1262 size -= HNS3_MAX_BD_SIZE; 1263 1264 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1265 return bd_num; 1266 } 1267 1268 bd_size[bd_num++] = size; 1269 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1270 return bd_num; 1271 } 1272 1273 return bd_num; 1274 } 1275 1276 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1277 u8 max_non_tso_bd_num) 1278 { 1279 struct sk_buff *frag_skb; 1280 unsigned int bd_num = 0; 1281 1282 /* If the total len is within the max bd limit */ 1283 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !skb_has_frag_list(skb) && 1284 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num)) 1285 return skb_shinfo(skb)->nr_frags + 1U; 1286 1287 /* The below case will always be linearized, return 1288 * HNS3_MAX_BD_NUM_TSO + 1U to make sure it is linearized. 1289 */ 1290 if (unlikely(skb->len > HNS3_MAX_TSO_SIZE || 1291 (!skb_is_gso(skb) && skb->len > 1292 HNS3_MAX_NON_TSO_SIZE(max_non_tso_bd_num)))) 1293 return HNS3_MAX_TSO_BD_NUM + 1U; 1294 1295 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num); 1296 1297 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM) 1298 return bd_num; 1299 1300 skb_walk_frags(skb, frag_skb) { 1301 bd_num = hns3_skb_bd_num(frag_skb, bd_size, bd_num); 1302 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1303 return bd_num; 1304 } 1305 1306 return bd_num; 1307 } 1308 1309 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb) 1310 { 1311 if (!skb->encapsulation) 1312 return skb_transport_offset(skb) + tcp_hdrlen(skb); 1313 1314 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb); 1315 } 1316 1317 /* HW need every continuous max_non_tso_bd_num buffer data to be larger 1318 * than MSS, we simplify it by ensuring skb_headlen + the first continuous 1319 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss, 1320 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger 1321 * than MSS except the last max_non_tso_bd_num - 1 frags. 1322 */ 1323 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size, 1324 unsigned int bd_num, u8 max_non_tso_bd_num) 1325 { 1326 unsigned int tot_len = 0; 1327 int i; 1328 1329 for (i = 0; i < max_non_tso_bd_num - 1U; i++) 1330 tot_len += bd_size[i]; 1331 1332 /* ensure the first max_non_tso_bd_num frags is greater than 1333 * mss + header 1334 */ 1335 if (tot_len + bd_size[max_non_tso_bd_num - 1U] < 1336 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb)) 1337 return true; 1338 1339 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater 1340 * than mss except the last one. 1341 */ 1342 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) { 1343 tot_len -= bd_size[i]; 1344 tot_len += bd_size[i + max_non_tso_bd_num - 1U]; 1345 1346 if (tot_len < skb_shinfo(skb)->gso_size) 1347 return true; 1348 } 1349 1350 return false; 1351 } 1352 1353 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size) 1354 { 1355 int i; 1356 1357 for (i = 0; i < MAX_SKB_FRAGS; i++) 1358 size[i] = skb_frag_size(&shinfo->frags[i]); 1359 } 1360 1361 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring, 1362 struct net_device *netdev, 1363 struct sk_buff *skb) 1364 { 1365 struct hns3_nic_priv *priv = netdev_priv(netdev); 1366 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num; 1367 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U]; 1368 unsigned int bd_num; 1369 1370 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num); 1371 if (unlikely(bd_num > max_non_tso_bd_num)) { 1372 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) && 1373 !hns3_skb_need_linearized(skb, bd_size, bd_num, 1374 max_non_tso_bd_num)) { 1375 trace_hns3_over_max_bd(skb); 1376 goto out; 1377 } 1378 1379 if (__skb_linearize(skb)) 1380 return -ENOMEM; 1381 1382 bd_num = hns3_tx_bd_count(skb->len); 1383 if ((skb_is_gso(skb) && bd_num > HNS3_MAX_TSO_BD_NUM) || 1384 (!skb_is_gso(skb) && 1385 bd_num > max_non_tso_bd_num)) { 1386 trace_hns3_over_max_bd(skb); 1387 return -ENOMEM; 1388 } 1389 1390 u64_stats_update_begin(&ring->syncp); 1391 ring->stats.tx_copy++; 1392 u64_stats_update_end(&ring->syncp); 1393 } 1394 1395 out: 1396 if (likely(ring_space(ring) >= bd_num)) 1397 return bd_num; 1398 1399 netif_stop_subqueue(netdev, ring->queue_index); 1400 smp_mb(); /* Memory barrier before checking ring_space */ 1401 1402 /* Start queue in case hns3_clean_tx_ring has just made room 1403 * available and has not seen the queue stopped state performed 1404 * by netif_stop_subqueue above. 1405 */ 1406 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) && 1407 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 1408 netif_start_subqueue(netdev, ring->queue_index); 1409 return bd_num; 1410 } 1411 1412 return -EBUSY; 1413 } 1414 1415 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1416 { 1417 struct device *dev = ring_to_dev(ring); 1418 unsigned int i; 1419 1420 for (i = 0; i < ring->desc_num; i++) { 1421 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1422 1423 memset(desc, 0, sizeof(*desc)); 1424 1425 /* check if this is where we started */ 1426 if (ring->next_to_use == next_to_use_orig) 1427 break; 1428 1429 /* rollback one */ 1430 ring_ptr_move_bw(ring, next_to_use); 1431 1432 if (!ring->desc_cb[ring->next_to_use].dma) 1433 continue; 1434 1435 /* unmap the descriptor dma address */ 1436 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB || 1437 ring->desc_cb[ring->next_to_use].type == 1438 DESC_TYPE_FRAGLIST_SKB) 1439 dma_unmap_single(dev, 1440 ring->desc_cb[ring->next_to_use].dma, 1441 ring->desc_cb[ring->next_to_use].length, 1442 DMA_TO_DEVICE); 1443 else if (ring->desc_cb[ring->next_to_use].length) 1444 dma_unmap_page(dev, 1445 ring->desc_cb[ring->next_to_use].dma, 1446 ring->desc_cb[ring->next_to_use].length, 1447 DMA_TO_DEVICE); 1448 1449 ring->desc_cb[ring->next_to_use].length = 0; 1450 ring->desc_cb[ring->next_to_use].dma = 0; 1451 ring->desc_cb[ring->next_to_use].type = DESC_TYPE_UNKNOWN; 1452 } 1453 } 1454 1455 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring, 1456 struct sk_buff *skb, enum hns_desc_type type) 1457 { 1458 unsigned int size = skb_headlen(skb); 1459 int i, ret, bd_num = 0; 1460 1461 if (size) { 1462 ret = hns3_fill_desc(ring, skb, size, type); 1463 if (unlikely(ret < 0)) 1464 return ret; 1465 1466 bd_num += ret; 1467 } 1468 1469 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1470 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1471 1472 size = skb_frag_size(frag); 1473 if (!size) 1474 continue; 1475 1476 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE); 1477 if (unlikely(ret < 0)) 1478 return ret; 1479 1480 bd_num += ret; 1481 } 1482 1483 return bd_num; 1484 } 1485 1486 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num, 1487 bool doorbell) 1488 { 1489 ring->pending_buf += num; 1490 1491 if (!doorbell) { 1492 u64_stats_update_begin(&ring->syncp); 1493 ring->stats.tx_more++; 1494 u64_stats_update_end(&ring->syncp); 1495 return; 1496 } 1497 1498 if (!ring->pending_buf) 1499 return; 1500 1501 writel(ring->pending_buf, 1502 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG); 1503 ring->pending_buf = 0; 1504 WRITE_ONCE(ring->last_to_use, ring->next_to_use); 1505 } 1506 1507 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1508 { 1509 struct hns3_nic_priv *priv = netdev_priv(netdev); 1510 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping]; 1511 struct netdev_queue *dev_queue; 1512 int pre_ntu, next_to_use_head; 1513 struct sk_buff *frag_skb; 1514 int bd_num = 0; 1515 bool doorbell; 1516 int ret; 1517 1518 /* Hardware can only handle short frames above 32 bytes */ 1519 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) { 1520 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 1521 return NETDEV_TX_OK; 1522 } 1523 1524 /* Prefetch the data used later */ 1525 prefetch(skb->data); 1526 1527 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb); 1528 if (unlikely(ret <= 0)) { 1529 if (ret == -EBUSY) { 1530 u64_stats_update_begin(&ring->syncp); 1531 ring->stats.tx_busy++; 1532 u64_stats_update_end(&ring->syncp); 1533 hns3_tx_doorbell(ring, 0, true); 1534 return NETDEV_TX_BUSY; 1535 } else if (ret == -ENOMEM) { 1536 u64_stats_update_begin(&ring->syncp); 1537 ring->stats.sw_err_cnt++; 1538 u64_stats_update_end(&ring->syncp); 1539 } 1540 1541 hns3_rl_err(netdev, "xmit error: %d!\n", ret); 1542 goto out_err_tx_ok; 1543 } 1544 1545 next_to_use_head = ring->next_to_use; 1546 1547 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use]); 1548 if (unlikely(ret < 0)) 1549 goto fill_err; 1550 1551 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB); 1552 if (unlikely(ret < 0)) 1553 goto fill_err; 1554 1555 bd_num += ret; 1556 1557 skb_walk_frags(skb, frag_skb) { 1558 ret = hns3_fill_skb_to_desc(ring, frag_skb, 1559 DESC_TYPE_FRAGLIST_SKB); 1560 if (unlikely(ret < 0)) 1561 goto fill_err; 1562 1563 bd_num += ret; 1564 } 1565 1566 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) : 1567 (ring->desc_num - 1); 1568 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |= 1569 cpu_to_le16(BIT(HNS3_TXD_FE_B)); 1570 trace_hns3_tx_desc(ring, pre_ntu); 1571 1572 /* Complete translate all packets */ 1573 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index); 1574 doorbell = __netdev_tx_sent_queue(dev_queue, skb->len, 1575 netdev_xmit_more()); 1576 hns3_tx_doorbell(ring, bd_num, doorbell); 1577 1578 return NETDEV_TX_OK; 1579 1580 fill_err: 1581 hns3_clear_desc(ring, next_to_use_head); 1582 1583 out_err_tx_ok: 1584 dev_kfree_skb_any(skb); 1585 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 1586 return NETDEV_TX_OK; 1587 } 1588 1589 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1590 { 1591 struct hnae3_handle *h = hns3_get_handle(netdev); 1592 struct sockaddr *mac_addr = p; 1593 int ret; 1594 1595 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1596 return -EADDRNOTAVAIL; 1597 1598 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1599 netdev_info(netdev, "already using mac address %pM\n", 1600 mac_addr->sa_data); 1601 return 0; 1602 } 1603 1604 /* For VF device, if there is a perm_addr, then the user will not 1605 * be allowed to change the address. 1606 */ 1607 if (!hns3_is_phys_func(h->pdev) && 1608 !is_zero_ether_addr(netdev->perm_addr)) { 1609 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n", 1610 netdev->perm_addr, mac_addr->sa_data); 1611 return -EPERM; 1612 } 1613 1614 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1615 if (ret) { 1616 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1617 return ret; 1618 } 1619 1620 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1621 1622 return 0; 1623 } 1624 1625 static int hns3_nic_do_ioctl(struct net_device *netdev, 1626 struct ifreq *ifr, int cmd) 1627 { 1628 struct hnae3_handle *h = hns3_get_handle(netdev); 1629 1630 if (!netif_running(netdev)) 1631 return -EINVAL; 1632 1633 if (!h->ae_algo->ops->do_ioctl) 1634 return -EOPNOTSUPP; 1635 1636 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 1637 } 1638 1639 static int hns3_nic_set_features(struct net_device *netdev, 1640 netdev_features_t features) 1641 { 1642 netdev_features_t changed = netdev->features ^ features; 1643 struct hns3_nic_priv *priv = netdev_priv(netdev); 1644 struct hnae3_handle *h = priv->ae_handle; 1645 bool enable; 1646 int ret; 1647 1648 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 1649 enable = !!(features & NETIF_F_GRO_HW); 1650 ret = h->ae_algo->ops->set_gro_en(h, enable); 1651 if (ret) 1652 return ret; 1653 } 1654 1655 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1656 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1657 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 1658 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 1659 if (ret) 1660 return ret; 1661 } 1662 1663 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 1664 enable = !!(features & NETIF_F_NTUPLE); 1665 h->ae_algo->ops->enable_fd(h, enable); 1666 } 1667 1668 netdev->features = features; 1669 return 0; 1670 } 1671 1672 static netdev_features_t hns3_features_check(struct sk_buff *skb, 1673 struct net_device *dev, 1674 netdev_features_t features) 1675 { 1676 #define HNS3_MAX_HDR_LEN 480U 1677 #define HNS3_MAX_L4_HDR_LEN 60U 1678 1679 size_t len; 1680 1681 if (skb->ip_summed != CHECKSUM_PARTIAL) 1682 return features; 1683 1684 if (skb->encapsulation) 1685 len = skb_inner_transport_header(skb) - skb->data; 1686 else 1687 len = skb_transport_header(skb) - skb->data; 1688 1689 /* Assume L4 is 60 byte as TCP is the only protocol with a 1690 * a flexible value, and it's max len is 60 bytes. 1691 */ 1692 len += HNS3_MAX_L4_HDR_LEN; 1693 1694 /* Hardware only supports checksum on the skb with a max header 1695 * len of 480 bytes. 1696 */ 1697 if (len > HNS3_MAX_HDR_LEN) 1698 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 1699 1700 return features; 1701 } 1702 1703 static void hns3_nic_get_stats64(struct net_device *netdev, 1704 struct rtnl_link_stats64 *stats) 1705 { 1706 struct hns3_nic_priv *priv = netdev_priv(netdev); 1707 int queue_num = priv->ae_handle->kinfo.num_tqps; 1708 struct hnae3_handle *handle = priv->ae_handle; 1709 struct hns3_enet_ring *ring; 1710 u64 rx_length_errors = 0; 1711 u64 rx_crc_errors = 0; 1712 u64 rx_multicast = 0; 1713 unsigned int start; 1714 u64 tx_errors = 0; 1715 u64 rx_errors = 0; 1716 unsigned int idx; 1717 u64 tx_bytes = 0; 1718 u64 rx_bytes = 0; 1719 u64 tx_pkts = 0; 1720 u64 rx_pkts = 0; 1721 u64 tx_drop = 0; 1722 u64 rx_drop = 0; 1723 1724 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1725 return; 1726 1727 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1728 1729 for (idx = 0; idx < queue_num; idx++) { 1730 /* fetch the tx stats */ 1731 ring = &priv->ring[idx]; 1732 do { 1733 start = u64_stats_fetch_begin_irq(&ring->syncp); 1734 tx_bytes += ring->stats.tx_bytes; 1735 tx_pkts += ring->stats.tx_pkts; 1736 tx_drop += ring->stats.sw_err_cnt; 1737 tx_drop += ring->stats.tx_vlan_err; 1738 tx_drop += ring->stats.tx_l4_proto_err; 1739 tx_drop += ring->stats.tx_l2l3l4_err; 1740 tx_drop += ring->stats.tx_tso_err; 1741 tx_errors += ring->stats.sw_err_cnt; 1742 tx_errors += ring->stats.tx_vlan_err; 1743 tx_errors += ring->stats.tx_l4_proto_err; 1744 tx_errors += ring->stats.tx_l2l3l4_err; 1745 tx_errors += ring->stats.tx_tso_err; 1746 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1747 1748 /* fetch the rx stats */ 1749 ring = &priv->ring[idx + queue_num]; 1750 do { 1751 start = u64_stats_fetch_begin_irq(&ring->syncp); 1752 rx_bytes += ring->stats.rx_bytes; 1753 rx_pkts += ring->stats.rx_pkts; 1754 rx_drop += ring->stats.l2_err; 1755 rx_errors += ring->stats.l2_err; 1756 rx_errors += ring->stats.l3l4_csum_err; 1757 rx_crc_errors += ring->stats.l2_err; 1758 rx_multicast += ring->stats.rx_multicast; 1759 rx_length_errors += ring->stats.err_pkt_len; 1760 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1761 } 1762 1763 stats->tx_bytes = tx_bytes; 1764 stats->tx_packets = tx_pkts; 1765 stats->rx_bytes = rx_bytes; 1766 stats->rx_packets = rx_pkts; 1767 1768 stats->rx_errors = rx_errors; 1769 stats->multicast = rx_multicast; 1770 stats->rx_length_errors = rx_length_errors; 1771 stats->rx_crc_errors = rx_crc_errors; 1772 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1773 1774 stats->tx_errors = tx_errors; 1775 stats->rx_dropped = rx_drop; 1776 stats->tx_dropped = tx_drop; 1777 stats->collisions = netdev->stats.collisions; 1778 stats->rx_over_errors = netdev->stats.rx_over_errors; 1779 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1780 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1781 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1782 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1783 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1784 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1785 stats->tx_window_errors = netdev->stats.tx_window_errors; 1786 stats->rx_compressed = netdev->stats.rx_compressed; 1787 stats->tx_compressed = netdev->stats.tx_compressed; 1788 } 1789 1790 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1791 { 1792 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1793 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map; 1794 struct hnae3_knic_private_info *kinfo; 1795 u8 tc = mqprio_qopt->qopt.num_tc; 1796 u16 mode = mqprio_qopt->mode; 1797 u8 hw = mqprio_qopt->qopt.hw; 1798 struct hnae3_handle *h; 1799 1800 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1801 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1802 return -EOPNOTSUPP; 1803 1804 if (tc > HNAE3_MAX_TC) 1805 return -EINVAL; 1806 1807 if (!netdev) 1808 return -EINVAL; 1809 1810 h = hns3_get_handle(netdev); 1811 kinfo = &h->kinfo; 1812 1813 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc); 1814 1815 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1816 kinfo->dcb_ops->setup_tc(h, tc ? tc : 1, prio_tc) : -EOPNOTSUPP; 1817 } 1818 1819 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1820 void *type_data) 1821 { 1822 if (type != TC_SETUP_QDISC_MQPRIO) 1823 return -EOPNOTSUPP; 1824 1825 return hns3_setup_tc(dev, type_data); 1826 } 1827 1828 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1829 __be16 proto, u16 vid) 1830 { 1831 struct hnae3_handle *h = hns3_get_handle(netdev); 1832 int ret = -EIO; 1833 1834 if (h->ae_algo->ops->set_vlan_filter) 1835 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1836 1837 return ret; 1838 } 1839 1840 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1841 __be16 proto, u16 vid) 1842 { 1843 struct hnae3_handle *h = hns3_get_handle(netdev); 1844 int ret = -EIO; 1845 1846 if (h->ae_algo->ops->set_vlan_filter) 1847 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1848 1849 return ret; 1850 } 1851 1852 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1853 u8 qos, __be16 vlan_proto) 1854 { 1855 struct hnae3_handle *h = hns3_get_handle(netdev); 1856 int ret = -EIO; 1857 1858 netif_dbg(h, drv, netdev, 1859 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n", 1860 vf, vlan, qos, ntohs(vlan_proto)); 1861 1862 if (h->ae_algo->ops->set_vf_vlan_filter) 1863 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1864 qos, vlan_proto); 1865 1866 return ret; 1867 } 1868 1869 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable) 1870 { 1871 struct hnae3_handle *handle = hns3_get_handle(netdev); 1872 1873 if (hns3_nic_resetting(netdev)) 1874 return -EBUSY; 1875 1876 if (!handle->ae_algo->ops->set_vf_spoofchk) 1877 return -EOPNOTSUPP; 1878 1879 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable); 1880 } 1881 1882 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable) 1883 { 1884 struct hnae3_handle *handle = hns3_get_handle(netdev); 1885 1886 if (!handle->ae_algo->ops->set_vf_trust) 1887 return -EOPNOTSUPP; 1888 1889 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable); 1890 } 1891 1892 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1893 { 1894 struct hnae3_handle *h = hns3_get_handle(netdev); 1895 int ret; 1896 1897 if (hns3_nic_resetting(netdev)) 1898 return -EBUSY; 1899 1900 if (!h->ae_algo->ops->set_mtu) 1901 return -EOPNOTSUPP; 1902 1903 netif_dbg(h, drv, netdev, 1904 "change mtu from %u to %d\n", netdev->mtu, new_mtu); 1905 1906 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 1907 if (ret) 1908 netdev_err(netdev, "failed to change MTU in hardware %d\n", 1909 ret); 1910 else 1911 netdev->mtu = new_mtu; 1912 1913 return ret; 1914 } 1915 1916 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 1917 { 1918 struct hns3_nic_priv *priv = netdev_priv(ndev); 1919 struct hnae3_handle *h = hns3_get_handle(ndev); 1920 struct hns3_enet_ring *tx_ring; 1921 struct napi_struct *napi; 1922 int timeout_queue = 0; 1923 int hw_head, hw_tail; 1924 int fbd_num, fbd_oft; 1925 int ebd_num, ebd_oft; 1926 int bd_num, bd_err; 1927 int ring_en, tc; 1928 int i; 1929 1930 /* Find the stopped queue the same way the stack does */ 1931 for (i = 0; i < ndev->num_tx_queues; i++) { 1932 struct netdev_queue *q; 1933 unsigned long trans_start; 1934 1935 q = netdev_get_tx_queue(ndev, i); 1936 trans_start = q->trans_start; 1937 if (netif_xmit_stopped(q) && 1938 time_after(jiffies, 1939 (trans_start + ndev->watchdog_timeo))) { 1940 timeout_queue = i; 1941 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n", 1942 q->state, 1943 jiffies_to_msecs(jiffies - trans_start)); 1944 break; 1945 } 1946 } 1947 1948 if (i == ndev->num_tx_queues) { 1949 netdev_info(ndev, 1950 "no netdev TX timeout queue found, timeout count: %llu\n", 1951 priv->tx_timeout_count); 1952 return false; 1953 } 1954 1955 priv->tx_timeout_count++; 1956 1957 tx_ring = &priv->ring[timeout_queue]; 1958 napi = &tx_ring->tqp_vector->napi; 1959 1960 netdev_info(ndev, 1961 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n", 1962 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use, 1963 tx_ring->next_to_clean, napi->state); 1964 1965 netdev_info(ndev, 1966 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n", 1967 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes, 1968 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf); 1969 1970 netdev_info(ndev, 1971 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n", 1972 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more, 1973 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy); 1974 1975 /* When mac received many pause frames continuous, it's unable to send 1976 * packets, which may cause tx timeout 1977 */ 1978 if (h->ae_algo->ops->get_mac_stats) { 1979 struct hns3_mac_stats mac_stats; 1980 1981 h->ae_algo->ops->get_mac_stats(h, &mac_stats); 1982 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n", 1983 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt); 1984 } 1985 1986 hw_head = readl_relaxed(tx_ring->tqp->io_base + 1987 HNS3_RING_TX_RING_HEAD_REG); 1988 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 1989 HNS3_RING_TX_RING_TAIL_REG); 1990 fbd_num = readl_relaxed(tx_ring->tqp->io_base + 1991 HNS3_RING_TX_RING_FBDNUM_REG); 1992 fbd_oft = readl_relaxed(tx_ring->tqp->io_base + 1993 HNS3_RING_TX_RING_OFFSET_REG); 1994 ebd_num = readl_relaxed(tx_ring->tqp->io_base + 1995 HNS3_RING_TX_RING_EBDNUM_REG); 1996 ebd_oft = readl_relaxed(tx_ring->tqp->io_base + 1997 HNS3_RING_TX_RING_EBD_OFFSET_REG); 1998 bd_num = readl_relaxed(tx_ring->tqp->io_base + 1999 HNS3_RING_TX_RING_BD_NUM_REG); 2000 bd_err = readl_relaxed(tx_ring->tqp->io_base + 2001 HNS3_RING_TX_RING_BD_ERR_REG); 2002 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG); 2003 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG); 2004 2005 netdev_info(ndev, 2006 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n", 2007 bd_num, hw_head, hw_tail, bd_err, 2008 readl(tx_ring->tqp_vector->mask_addr)); 2009 netdev_info(ndev, 2010 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n", 2011 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft); 2012 2013 return true; 2014 } 2015 2016 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue) 2017 { 2018 struct hns3_nic_priv *priv = netdev_priv(ndev); 2019 struct hnae3_handle *h = priv->ae_handle; 2020 2021 if (!hns3_get_tx_timeo_queue_info(ndev)) 2022 return; 2023 2024 /* request the reset, and let the hclge to determine 2025 * which reset level should be done 2026 */ 2027 if (h->ae_algo->ops->reset_event) 2028 h->ae_algo->ops->reset_event(h->pdev, h); 2029 } 2030 2031 #ifdef CONFIG_RFS_ACCEL 2032 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 2033 u16 rxq_index, u32 flow_id) 2034 { 2035 struct hnae3_handle *h = hns3_get_handle(dev); 2036 struct flow_keys fkeys; 2037 2038 if (!h->ae_algo->ops->add_arfs_entry) 2039 return -EOPNOTSUPP; 2040 2041 if (skb->encapsulation) 2042 return -EPROTONOSUPPORT; 2043 2044 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0)) 2045 return -EPROTONOSUPPORT; 2046 2047 if ((fkeys.basic.n_proto != htons(ETH_P_IP) && 2048 fkeys.basic.n_proto != htons(ETH_P_IPV6)) || 2049 (fkeys.basic.ip_proto != IPPROTO_TCP && 2050 fkeys.basic.ip_proto != IPPROTO_UDP)) 2051 return -EPROTONOSUPPORT; 2052 2053 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys); 2054 } 2055 #endif 2056 2057 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf, 2058 struct ifla_vf_info *ivf) 2059 { 2060 struct hnae3_handle *h = hns3_get_handle(ndev); 2061 2062 if (!h->ae_algo->ops->get_vf_config) 2063 return -EOPNOTSUPP; 2064 2065 return h->ae_algo->ops->get_vf_config(h, vf, ivf); 2066 } 2067 2068 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf, 2069 int link_state) 2070 { 2071 struct hnae3_handle *h = hns3_get_handle(ndev); 2072 2073 if (!h->ae_algo->ops->set_vf_link_state) 2074 return -EOPNOTSUPP; 2075 2076 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state); 2077 } 2078 2079 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf, 2080 int min_tx_rate, int max_tx_rate) 2081 { 2082 struct hnae3_handle *h = hns3_get_handle(ndev); 2083 2084 if (!h->ae_algo->ops->set_vf_rate) 2085 return -EOPNOTSUPP; 2086 2087 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate, 2088 false); 2089 } 2090 2091 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) 2092 { 2093 struct hnae3_handle *h = hns3_get_handle(netdev); 2094 2095 if (!h->ae_algo->ops->set_vf_mac) 2096 return -EOPNOTSUPP; 2097 2098 if (is_multicast_ether_addr(mac)) { 2099 netdev_err(netdev, 2100 "Invalid MAC:%pM specified. Could not set MAC\n", 2101 mac); 2102 return -EINVAL; 2103 } 2104 2105 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac); 2106 } 2107 2108 static const struct net_device_ops hns3_nic_netdev_ops = { 2109 .ndo_open = hns3_nic_net_open, 2110 .ndo_stop = hns3_nic_net_stop, 2111 .ndo_start_xmit = hns3_nic_net_xmit, 2112 .ndo_tx_timeout = hns3_nic_net_timeout, 2113 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 2114 .ndo_do_ioctl = hns3_nic_do_ioctl, 2115 .ndo_change_mtu = hns3_nic_change_mtu, 2116 .ndo_set_features = hns3_nic_set_features, 2117 .ndo_features_check = hns3_features_check, 2118 .ndo_get_stats64 = hns3_nic_get_stats64, 2119 .ndo_setup_tc = hns3_nic_setup_tc, 2120 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 2121 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 2122 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 2123 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 2124 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk, 2125 .ndo_set_vf_trust = hns3_set_vf_trust, 2126 #ifdef CONFIG_RFS_ACCEL 2127 .ndo_rx_flow_steer = hns3_rx_flow_steer, 2128 #endif 2129 .ndo_get_vf_config = hns3_nic_get_vf_config, 2130 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state, 2131 .ndo_set_vf_rate = hns3_nic_set_vf_rate, 2132 .ndo_set_vf_mac = hns3_nic_set_vf_mac, 2133 }; 2134 2135 bool hns3_is_phys_func(struct pci_dev *pdev) 2136 { 2137 u32 dev_id = pdev->device; 2138 2139 switch (dev_id) { 2140 case HNAE3_DEV_ID_GE: 2141 case HNAE3_DEV_ID_25GE: 2142 case HNAE3_DEV_ID_25GE_RDMA: 2143 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 2144 case HNAE3_DEV_ID_50GE_RDMA: 2145 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 2146 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 2147 case HNAE3_DEV_ID_200G_RDMA: 2148 return true; 2149 case HNAE3_DEV_ID_VF: 2150 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF: 2151 return false; 2152 default: 2153 dev_warn(&pdev->dev, "un-recognized pci device-id %u", 2154 dev_id); 2155 } 2156 2157 return false; 2158 } 2159 2160 static void hns3_disable_sriov(struct pci_dev *pdev) 2161 { 2162 /* If our VFs are assigned we cannot shut down SR-IOV 2163 * without causing issues, so just leave the hardware 2164 * available but disabled 2165 */ 2166 if (pci_vfs_assigned(pdev)) { 2167 dev_warn(&pdev->dev, 2168 "disabling driver while VFs are assigned\n"); 2169 return; 2170 } 2171 2172 pci_disable_sriov(pdev); 2173 } 2174 2175 /* hns3_probe - Device initialization routine 2176 * @pdev: PCI device information struct 2177 * @ent: entry in hns3_pci_tbl 2178 * 2179 * hns3_probe initializes a PF identified by a pci_dev structure. 2180 * The OS initialization, configuring of the PF private structure, 2181 * and a hardware reset occur. 2182 * 2183 * Returns 0 on success, negative on failure 2184 */ 2185 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2186 { 2187 struct hnae3_ae_dev *ae_dev; 2188 int ret; 2189 2190 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL); 2191 if (!ae_dev) 2192 return -ENOMEM; 2193 2194 ae_dev->pdev = pdev; 2195 ae_dev->flag = ent->driver_data; 2196 pci_set_drvdata(pdev, ae_dev); 2197 2198 ret = hnae3_register_ae_dev(ae_dev); 2199 if (ret) 2200 pci_set_drvdata(pdev, NULL); 2201 2202 return ret; 2203 } 2204 2205 /* hns3_remove - Device removal routine 2206 * @pdev: PCI device information struct 2207 */ 2208 static void hns3_remove(struct pci_dev *pdev) 2209 { 2210 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2211 2212 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 2213 hns3_disable_sriov(pdev); 2214 2215 hnae3_unregister_ae_dev(ae_dev); 2216 pci_set_drvdata(pdev, NULL); 2217 } 2218 2219 /** 2220 * hns3_pci_sriov_configure 2221 * @pdev: pointer to a pci_dev structure 2222 * @num_vfs: number of VFs to allocate 2223 * 2224 * Enable or change the number of VFs. Called when the user updates the number 2225 * of VFs in sysfs. 2226 **/ 2227 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 2228 { 2229 int ret; 2230 2231 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 2232 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 2233 return -EINVAL; 2234 } 2235 2236 if (num_vfs) { 2237 ret = pci_enable_sriov(pdev, num_vfs); 2238 if (ret) 2239 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 2240 else 2241 return num_vfs; 2242 } else if (!pci_vfs_assigned(pdev)) { 2243 pci_disable_sriov(pdev); 2244 } else { 2245 dev_warn(&pdev->dev, 2246 "Unable to free VFs because some are assigned to VMs.\n"); 2247 } 2248 2249 return 0; 2250 } 2251 2252 static void hns3_shutdown(struct pci_dev *pdev) 2253 { 2254 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2255 2256 hnae3_unregister_ae_dev(ae_dev); 2257 pci_set_drvdata(pdev, NULL); 2258 2259 if (system_state == SYSTEM_POWER_OFF) 2260 pci_set_power_state(pdev, PCI_D3hot); 2261 } 2262 2263 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 2264 pci_channel_state_t state) 2265 { 2266 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2267 pci_ers_result_t ret; 2268 2269 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state); 2270 2271 if (state == pci_channel_io_perm_failure) 2272 return PCI_ERS_RESULT_DISCONNECT; 2273 2274 if (!ae_dev || !ae_dev->ops) { 2275 dev_err(&pdev->dev, 2276 "Can't recover - error happened before device initialized\n"); 2277 return PCI_ERS_RESULT_NONE; 2278 } 2279 2280 if (ae_dev->ops->handle_hw_ras_error) 2281 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 2282 else 2283 return PCI_ERS_RESULT_NONE; 2284 2285 return ret; 2286 } 2287 2288 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 2289 { 2290 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2291 const struct hnae3_ae_ops *ops; 2292 enum hnae3_reset_type reset_type; 2293 struct device *dev = &pdev->dev; 2294 2295 if (!ae_dev || !ae_dev->ops) 2296 return PCI_ERS_RESULT_NONE; 2297 2298 ops = ae_dev->ops; 2299 /* request the reset */ 2300 if (ops->reset_event && ops->get_reset_level && 2301 ops->set_default_reset_request) { 2302 if (ae_dev->hw_err_reset_req) { 2303 reset_type = ops->get_reset_level(ae_dev, 2304 &ae_dev->hw_err_reset_req); 2305 ops->set_default_reset_request(ae_dev, reset_type); 2306 dev_info(dev, "requesting reset due to PCI error\n"); 2307 ops->reset_event(pdev, NULL); 2308 } 2309 2310 return PCI_ERS_RESULT_RECOVERED; 2311 } 2312 2313 return PCI_ERS_RESULT_DISCONNECT; 2314 } 2315 2316 static void hns3_reset_prepare(struct pci_dev *pdev) 2317 { 2318 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2319 2320 dev_info(&pdev->dev, "FLR prepare\n"); 2321 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare) 2322 ae_dev->ops->flr_prepare(ae_dev); 2323 } 2324 2325 static void hns3_reset_done(struct pci_dev *pdev) 2326 { 2327 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2328 2329 dev_info(&pdev->dev, "FLR done\n"); 2330 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done) 2331 ae_dev->ops->flr_done(ae_dev); 2332 } 2333 2334 static const struct pci_error_handlers hns3_err_handler = { 2335 .error_detected = hns3_error_detected, 2336 .slot_reset = hns3_slot_reset, 2337 .reset_prepare = hns3_reset_prepare, 2338 .reset_done = hns3_reset_done, 2339 }; 2340 2341 static struct pci_driver hns3_driver = { 2342 .name = hns3_driver_name, 2343 .id_table = hns3_pci_tbl, 2344 .probe = hns3_probe, 2345 .remove = hns3_remove, 2346 .shutdown = hns3_shutdown, 2347 .sriov_configure = hns3_pci_sriov_configure, 2348 .err_handler = &hns3_err_handler, 2349 }; 2350 2351 /* set default feature to hns3 */ 2352 static void hns3_set_default_feature(struct net_device *netdev) 2353 { 2354 struct hnae3_handle *h = hns3_get_handle(netdev); 2355 struct pci_dev *pdev = h->pdev; 2356 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2357 2358 netdev->priv_flags |= IFF_UNICAST_FLT; 2359 2360 netdev->hw_enc_features |= NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2361 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2362 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2363 NETIF_F_SCTP_CRC | NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST; 2364 2365 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 2366 2367 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 2368 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2369 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2370 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2371 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2372 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 2373 2374 netdev->vlan_features |= NETIF_F_RXCSUM | 2375 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 2376 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2377 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2378 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 2379 2380 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 2381 NETIF_F_HW_VLAN_CTAG_RX | 2382 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2383 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2384 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2385 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 2386 2387 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2388 netdev->hw_features |= NETIF_F_GRO_HW; 2389 netdev->features |= NETIF_F_GRO_HW; 2390 2391 if (!(h->flags & HNAE3_SUPPORT_VF)) { 2392 netdev->hw_features |= NETIF_F_NTUPLE; 2393 netdev->features |= NETIF_F_NTUPLE; 2394 } 2395 } 2396 2397 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps)) { 2398 netdev->hw_features |= NETIF_F_GSO_UDP_L4; 2399 netdev->features |= NETIF_F_GSO_UDP_L4; 2400 netdev->vlan_features |= NETIF_F_GSO_UDP_L4; 2401 netdev->hw_enc_features |= NETIF_F_GSO_UDP_L4; 2402 } 2403 2404 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) { 2405 netdev->hw_features |= NETIF_F_HW_CSUM; 2406 netdev->features |= NETIF_F_HW_CSUM; 2407 netdev->vlan_features |= NETIF_F_HW_CSUM; 2408 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 2409 } else { 2410 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2411 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2412 netdev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2413 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2414 } 2415 2416 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps)) { 2417 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 2418 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 2419 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 2420 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 2421 } 2422 } 2423 2424 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 2425 struct hns3_desc_cb *cb) 2426 { 2427 unsigned int order = hns3_page_order(ring); 2428 struct page *p; 2429 2430 p = dev_alloc_pages(order); 2431 if (!p) 2432 return -ENOMEM; 2433 2434 cb->priv = p; 2435 cb->page_offset = 0; 2436 cb->reuse_flag = 0; 2437 cb->buf = page_address(p); 2438 cb->length = hns3_page_size(ring); 2439 cb->type = DESC_TYPE_PAGE; 2440 page_ref_add(p, USHRT_MAX - 1); 2441 cb->pagecnt_bias = USHRT_MAX; 2442 2443 return 0; 2444 } 2445 2446 static void hns3_free_buffer(struct hns3_enet_ring *ring, 2447 struct hns3_desc_cb *cb, int budget) 2448 { 2449 if (cb->type == DESC_TYPE_SKB) 2450 napi_consume_skb(cb->priv, budget); 2451 else if (!HNAE3_IS_TX_RING(ring) && cb->pagecnt_bias) 2452 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias); 2453 memset(cb, 0, sizeof(*cb)); 2454 } 2455 2456 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 2457 { 2458 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 2459 cb->length, ring_to_dma_dir(ring)); 2460 2461 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 2462 return -EIO; 2463 2464 return 0; 2465 } 2466 2467 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 2468 struct hns3_desc_cb *cb) 2469 { 2470 if (cb->type == DESC_TYPE_SKB || cb->type == DESC_TYPE_FRAGLIST_SKB) 2471 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 2472 ring_to_dma_dir(ring)); 2473 else if (cb->length) 2474 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 2475 ring_to_dma_dir(ring)); 2476 } 2477 2478 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 2479 { 2480 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2481 ring->desc[i].addr = 0; 2482 } 2483 2484 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i, 2485 int budget) 2486 { 2487 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 2488 2489 if (!ring->desc_cb[i].dma) 2490 return; 2491 2492 hns3_buffer_detach(ring, i); 2493 hns3_free_buffer(ring, cb, budget); 2494 } 2495 2496 static void hns3_free_buffers(struct hns3_enet_ring *ring) 2497 { 2498 int i; 2499 2500 for (i = 0; i < ring->desc_num; i++) 2501 hns3_free_buffer_detach(ring, i, 0); 2502 } 2503 2504 /* free desc along with its attached buffer */ 2505 static void hns3_free_desc(struct hns3_enet_ring *ring) 2506 { 2507 int size = ring->desc_num * sizeof(ring->desc[0]); 2508 2509 hns3_free_buffers(ring); 2510 2511 if (ring->desc) { 2512 dma_free_coherent(ring_to_dev(ring), size, 2513 ring->desc, ring->desc_dma_addr); 2514 ring->desc = NULL; 2515 } 2516 } 2517 2518 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 2519 { 2520 int size = ring->desc_num * sizeof(ring->desc[0]); 2521 2522 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 2523 &ring->desc_dma_addr, GFP_KERNEL); 2524 if (!ring->desc) 2525 return -ENOMEM; 2526 2527 return 0; 2528 } 2529 2530 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring, 2531 struct hns3_desc_cb *cb) 2532 { 2533 int ret; 2534 2535 ret = hns3_alloc_buffer(ring, cb); 2536 if (ret) 2537 goto out; 2538 2539 ret = hns3_map_buffer(ring, cb); 2540 if (ret) 2541 goto out_with_buf; 2542 2543 return 0; 2544 2545 out_with_buf: 2546 hns3_free_buffer(ring, cb, 0); 2547 out: 2548 return ret; 2549 } 2550 2551 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i) 2552 { 2553 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]); 2554 2555 if (ret) 2556 return ret; 2557 2558 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2559 2560 return 0; 2561 } 2562 2563 /* Allocate memory for raw pkg, and map with dma */ 2564 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 2565 { 2566 int i, j, ret; 2567 2568 for (i = 0; i < ring->desc_num; i++) { 2569 ret = hns3_alloc_and_attach_buffer(ring, i); 2570 if (ret) 2571 goto out_buffer_fail; 2572 } 2573 2574 return 0; 2575 2576 out_buffer_fail: 2577 for (j = i - 1; j >= 0; j--) 2578 hns3_free_buffer_detach(ring, j, 0); 2579 return ret; 2580 } 2581 2582 /* detach a in-used buffer and replace with a reserved one */ 2583 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 2584 struct hns3_desc_cb *res_cb) 2585 { 2586 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2587 ring->desc_cb[i] = *res_cb; 2588 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2589 ring->desc[i].rx.bd_base_info = 0; 2590 } 2591 2592 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 2593 { 2594 ring->desc_cb[i].reuse_flag = 0; 2595 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 2596 ring->desc_cb[i].page_offset); 2597 ring->desc[i].rx.bd_base_info = 0; 2598 2599 dma_sync_single_for_device(ring_to_dev(ring), 2600 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset, 2601 hns3_buf_size(ring), 2602 DMA_FROM_DEVICE); 2603 } 2604 2605 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, 2606 int *bytes, int *pkts, int budget) 2607 { 2608 /* pair with ring->last_to_use update in hns3_tx_doorbell(), 2609 * smp_store_release() is not used in hns3_tx_doorbell() because 2610 * the doorbell operation already have the needed barrier operation. 2611 */ 2612 int ltu = smp_load_acquire(&ring->last_to_use); 2613 int ntc = ring->next_to_clean; 2614 struct hns3_desc_cb *desc_cb; 2615 bool reclaimed = false; 2616 struct hns3_desc *desc; 2617 2618 while (ltu != ntc) { 2619 desc = &ring->desc[ntc]; 2620 2621 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) & 2622 BIT(HNS3_TXD_VLD_B)) 2623 break; 2624 2625 desc_cb = &ring->desc_cb[ntc]; 2626 (*pkts) += (desc_cb->type == DESC_TYPE_SKB); 2627 (*bytes) += desc_cb->length; 2628 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */ 2629 hns3_free_buffer_detach(ring, ntc, budget); 2630 2631 if (++ntc == ring->desc_num) 2632 ntc = 0; 2633 2634 /* Issue prefetch for next Tx descriptor */ 2635 prefetch(&ring->desc_cb[ntc]); 2636 reclaimed = true; 2637 } 2638 2639 if (unlikely(!reclaimed)) 2640 return false; 2641 2642 /* This smp_store_release() pairs with smp_load_acquire() in 2643 * ring_space called by hns3_nic_net_xmit. 2644 */ 2645 smp_store_release(&ring->next_to_clean, ntc); 2646 return true; 2647 } 2648 2649 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget) 2650 { 2651 struct net_device *netdev = ring_to_netdev(ring); 2652 struct hns3_nic_priv *priv = netdev_priv(netdev); 2653 struct netdev_queue *dev_queue; 2654 int bytes, pkts; 2655 2656 bytes = 0; 2657 pkts = 0; 2658 2659 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget))) 2660 return; 2661 2662 ring->tqp_vector->tx_group.total_bytes += bytes; 2663 ring->tqp_vector->tx_group.total_packets += pkts; 2664 2665 u64_stats_update_begin(&ring->syncp); 2666 ring->stats.tx_bytes += bytes; 2667 ring->stats.tx_pkts += pkts; 2668 u64_stats_update_end(&ring->syncp); 2669 2670 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 2671 netdev_tx_completed_queue(dev_queue, pkts, bytes); 2672 2673 if (unlikely(netif_carrier_ok(netdev) && 2674 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) { 2675 /* Make sure that anybody stopping the queue after this 2676 * sees the new next_to_clean. 2677 */ 2678 smp_mb(); 2679 if (netif_tx_queue_stopped(dev_queue) && 2680 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 2681 netif_tx_wake_queue(dev_queue); 2682 ring->stats.restart_queue++; 2683 } 2684 } 2685 } 2686 2687 static int hns3_desc_unused(struct hns3_enet_ring *ring) 2688 { 2689 int ntc = ring->next_to_clean; 2690 int ntu = ring->next_to_use; 2691 2692 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 2693 } 2694 2695 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, 2696 int cleand_count) 2697 { 2698 struct hns3_desc_cb *desc_cb; 2699 struct hns3_desc_cb res_cbs; 2700 int i, ret; 2701 2702 for (i = 0; i < cleand_count; i++) { 2703 desc_cb = &ring->desc_cb[ring->next_to_use]; 2704 if (desc_cb->reuse_flag) { 2705 u64_stats_update_begin(&ring->syncp); 2706 ring->stats.reuse_pg_cnt++; 2707 u64_stats_update_end(&ring->syncp); 2708 2709 hns3_reuse_buffer(ring, ring->next_to_use); 2710 } else { 2711 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 2712 if (ret) { 2713 u64_stats_update_begin(&ring->syncp); 2714 ring->stats.sw_err_cnt++; 2715 u64_stats_update_end(&ring->syncp); 2716 2717 hns3_rl_err(ring_to_netdev(ring), 2718 "alloc rx buffer failed: %d\n", 2719 ret); 2720 break; 2721 } 2722 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 2723 2724 u64_stats_update_begin(&ring->syncp); 2725 ring->stats.non_reuse_pg++; 2726 u64_stats_update_end(&ring->syncp); 2727 } 2728 2729 ring_ptr_move_fw(ring, next_to_use); 2730 } 2731 2732 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2733 } 2734 2735 static bool hns3_page_is_reusable(struct page *page) 2736 { 2737 return page_to_nid(page) == numa_mem_id() && 2738 !page_is_pfmemalloc(page); 2739 } 2740 2741 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb) 2742 { 2743 return (page_count(cb->priv) - cb->pagecnt_bias) == 1; 2744 } 2745 2746 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2747 struct hns3_enet_ring *ring, int pull_len, 2748 struct hns3_desc_cb *desc_cb) 2749 { 2750 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 2751 int size = le16_to_cpu(desc->rx.size); 2752 u32 truesize = hns3_buf_size(ring); 2753 2754 desc_cb->pagecnt_bias--; 2755 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2756 size - pull_len, truesize); 2757 2758 /* Avoid re-using remote pages, or the stack is still using the page 2759 * when page_offset rollback to zero, flag default unreuse 2760 */ 2761 if (unlikely(!hns3_page_is_reusable(desc_cb->priv)) || 2762 (!desc_cb->page_offset && !hns3_can_reuse_page(desc_cb))) { 2763 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias); 2764 return; 2765 } 2766 2767 /* Move offset up to the next cache line */ 2768 desc_cb->page_offset += truesize; 2769 2770 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) { 2771 desc_cb->reuse_flag = 1; 2772 } else if (hns3_can_reuse_page(desc_cb)) { 2773 desc_cb->reuse_flag = 1; 2774 desc_cb->page_offset = 0; 2775 } else if (desc_cb->pagecnt_bias) { 2776 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias); 2777 return; 2778 } 2779 2780 if (unlikely(!desc_cb->pagecnt_bias)) { 2781 page_ref_add(desc_cb->priv, USHRT_MAX); 2782 desc_cb->pagecnt_bias = USHRT_MAX; 2783 } 2784 } 2785 2786 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) 2787 { 2788 __be16 type = skb->protocol; 2789 struct tcphdr *th; 2790 int depth = 0; 2791 2792 while (eth_type_vlan(type)) { 2793 struct vlan_hdr *vh; 2794 2795 if ((depth + VLAN_HLEN) > skb_headlen(skb)) 2796 return -EFAULT; 2797 2798 vh = (struct vlan_hdr *)(skb->data + depth); 2799 type = vh->h_vlan_encapsulated_proto; 2800 depth += VLAN_HLEN; 2801 } 2802 2803 skb_set_network_header(skb, depth); 2804 2805 if (type == htons(ETH_P_IP)) { 2806 const struct iphdr *iph = ip_hdr(skb); 2807 2808 depth += sizeof(struct iphdr); 2809 skb_set_transport_header(skb, depth); 2810 th = tcp_hdr(skb); 2811 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr, 2812 iph->daddr, 0); 2813 } else if (type == htons(ETH_P_IPV6)) { 2814 const struct ipv6hdr *iph = ipv6_hdr(skb); 2815 2816 depth += sizeof(struct ipv6hdr); 2817 skb_set_transport_header(skb, depth); 2818 th = tcp_hdr(skb); 2819 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr, 2820 &iph->daddr, 0); 2821 } else { 2822 hns3_rl_err(skb->dev, 2823 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n", 2824 be16_to_cpu(type), depth); 2825 return -EFAULT; 2826 } 2827 2828 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 2829 if (th->cwr) 2830 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 2831 2832 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B)) 2833 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID; 2834 2835 skb->csum_start = (unsigned char *)th - skb->head; 2836 skb->csum_offset = offsetof(struct tcphdr, check); 2837 skb->ip_summed = CHECKSUM_PARTIAL; 2838 2839 trace_hns3_gro(skb); 2840 2841 return 0; 2842 } 2843 2844 static void hns3_checksum_complete(struct hns3_enet_ring *ring, 2845 struct sk_buff *skb, u32 l234info) 2846 { 2847 u32 lo, hi; 2848 2849 u64_stats_update_begin(&ring->syncp); 2850 ring->stats.csum_complete++; 2851 u64_stats_update_end(&ring->syncp); 2852 skb->ip_summed = CHECKSUM_COMPLETE; 2853 lo = hnae3_get_field(l234info, HNS3_RXD_L2_CSUM_L_M, 2854 HNS3_RXD_L2_CSUM_L_S); 2855 hi = hnae3_get_field(l234info, HNS3_RXD_L2_CSUM_H_M, 2856 HNS3_RXD_L2_CSUM_H_S); 2857 skb->csum = csum_unfold((__force __sum16)(lo | hi << 8)); 2858 } 2859 2860 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2861 u32 l234info, u32 bd_base_info, u32 ol_info) 2862 { 2863 struct net_device *netdev = ring_to_netdev(ring); 2864 int l3_type, l4_type; 2865 int ol4_type; 2866 2867 skb->ip_summed = CHECKSUM_NONE; 2868 2869 skb_checksum_none_assert(skb); 2870 2871 if (!(netdev->features & NETIF_F_RXCSUM)) 2872 return; 2873 2874 if (l234info & BIT(HNS3_RXD_L2_CSUM_B)) { 2875 hns3_checksum_complete(ring, skb, l234info); 2876 return; 2877 } 2878 2879 /* check if hardware has done checksum */ 2880 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 2881 return; 2882 2883 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | 2884 BIT(HNS3_RXD_OL3E_B) | 2885 BIT(HNS3_RXD_OL4E_B)))) { 2886 u64_stats_update_begin(&ring->syncp); 2887 ring->stats.l3l4_csum_err++; 2888 u64_stats_update_end(&ring->syncp); 2889 2890 return; 2891 } 2892 2893 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M, 2894 HNS3_RXD_OL4ID_S); 2895 switch (ol4_type) { 2896 case HNS3_OL4_TYPE_MAC_IN_UDP: 2897 case HNS3_OL4_TYPE_NVGRE: 2898 skb->csum_level = 1; 2899 fallthrough; 2900 case HNS3_OL4_TYPE_NO_TUN: 2901 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2902 HNS3_RXD_L3ID_S); 2903 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 2904 HNS3_RXD_L4ID_S); 2905 2906 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 2907 if ((l3_type == HNS3_L3_TYPE_IPV4 || 2908 l3_type == HNS3_L3_TYPE_IPV6) && 2909 (l4_type == HNS3_L4_TYPE_UDP || 2910 l4_type == HNS3_L4_TYPE_TCP || 2911 l4_type == HNS3_L4_TYPE_SCTP)) 2912 skb->ip_summed = CHECKSUM_UNNECESSARY; 2913 break; 2914 default: 2915 break; 2916 } 2917 } 2918 2919 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 2920 { 2921 if (skb_has_frag_list(skb)) 2922 napi_gro_flush(&ring->tqp_vector->napi, false); 2923 2924 napi_gro_receive(&ring->tqp_vector->napi, skb); 2925 } 2926 2927 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 2928 struct hns3_desc *desc, u32 l234info, 2929 u16 *vlan_tag) 2930 { 2931 struct hnae3_handle *handle = ring->tqp->handle; 2932 struct pci_dev *pdev = ring->tqp->handle->pdev; 2933 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2934 2935 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) { 2936 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2937 if (!(*vlan_tag & VLAN_VID_MASK)) 2938 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2939 2940 return (*vlan_tag != 0); 2941 } 2942 2943 #define HNS3_STRP_OUTER_VLAN 0x1 2944 #define HNS3_STRP_INNER_VLAN 0x2 2945 #define HNS3_STRP_BOTH 0x3 2946 2947 /* Hardware always insert VLAN tag into RX descriptor when 2948 * remove the tag from packet, driver needs to determine 2949 * reporting which tag to stack. 2950 */ 2951 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 2952 HNS3_RXD_STRP_TAGP_S)) { 2953 case HNS3_STRP_OUTER_VLAN: 2954 if (handle->port_base_vlan_state != 2955 HNAE3_PORT_BASE_VLAN_DISABLE) 2956 return false; 2957 2958 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2959 return true; 2960 case HNS3_STRP_INNER_VLAN: 2961 if (handle->port_base_vlan_state != 2962 HNAE3_PORT_BASE_VLAN_DISABLE) 2963 return false; 2964 2965 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2966 return true; 2967 case HNS3_STRP_BOTH: 2968 if (handle->port_base_vlan_state == 2969 HNAE3_PORT_BASE_VLAN_DISABLE) 2970 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2971 else 2972 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2973 2974 return true; 2975 default: 2976 return false; 2977 } 2978 } 2979 2980 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring) 2981 { 2982 ring->desc[ring->next_to_clean].rx.bd_base_info &= 2983 cpu_to_le32(~BIT(HNS3_RXD_VLD_B)); 2984 ring->next_to_clean += 1; 2985 2986 if (unlikely(ring->next_to_clean == ring->desc_num)) 2987 ring->next_to_clean = 0; 2988 } 2989 2990 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length, 2991 unsigned char *va) 2992 { 2993 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2994 struct net_device *netdev = ring_to_netdev(ring); 2995 struct sk_buff *skb; 2996 2997 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 2998 skb = ring->skb; 2999 if (unlikely(!skb)) { 3000 hns3_rl_err(netdev, "alloc rx skb fail\n"); 3001 3002 u64_stats_update_begin(&ring->syncp); 3003 ring->stats.sw_err_cnt++; 3004 u64_stats_update_end(&ring->syncp); 3005 3006 return -ENOMEM; 3007 } 3008 3009 trace_hns3_rx_desc(ring); 3010 prefetchw(skb->data); 3011 3012 ring->pending_buf = 1; 3013 ring->frag_num = 0; 3014 ring->tail_skb = NULL; 3015 if (length <= HNS3_RX_HEAD_SIZE) { 3016 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 3017 3018 /* We can reuse buffer as-is, just make sure it is local */ 3019 if (likely(hns3_page_is_reusable(desc_cb->priv))) 3020 desc_cb->reuse_flag = 1; 3021 else /* This page cannot be reused so discard it */ 3022 __page_frag_cache_drain(desc_cb->priv, 3023 desc_cb->pagecnt_bias); 3024 3025 hns3_rx_ring_move_fw(ring); 3026 return 0; 3027 } 3028 u64_stats_update_begin(&ring->syncp); 3029 ring->stats.seg_pkt_cnt++; 3030 u64_stats_update_end(&ring->syncp); 3031 3032 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE); 3033 __skb_put(skb, ring->pull_len); 3034 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 3035 desc_cb); 3036 hns3_rx_ring_move_fw(ring); 3037 3038 return 0; 3039 } 3040 3041 static int hns3_add_frag(struct hns3_enet_ring *ring) 3042 { 3043 struct sk_buff *skb = ring->skb; 3044 struct sk_buff *head_skb = skb; 3045 struct sk_buff *new_skb; 3046 struct hns3_desc_cb *desc_cb; 3047 struct hns3_desc *desc; 3048 u32 bd_base_info; 3049 3050 do { 3051 desc = &ring->desc[ring->next_to_clean]; 3052 desc_cb = &ring->desc_cb[ring->next_to_clean]; 3053 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3054 /* make sure HW write desc complete */ 3055 dma_rmb(); 3056 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 3057 return -ENXIO; 3058 3059 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 3060 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0); 3061 if (unlikely(!new_skb)) { 3062 hns3_rl_err(ring_to_netdev(ring), 3063 "alloc rx fraglist skb fail\n"); 3064 return -ENXIO; 3065 } 3066 ring->frag_num = 0; 3067 3068 if (ring->tail_skb) { 3069 ring->tail_skb->next = new_skb; 3070 ring->tail_skb = new_skb; 3071 } else { 3072 skb_shinfo(skb)->frag_list = new_skb; 3073 ring->tail_skb = new_skb; 3074 } 3075 } 3076 3077 if (ring->tail_skb) { 3078 head_skb->truesize += hns3_buf_size(ring); 3079 head_skb->data_len += le16_to_cpu(desc->rx.size); 3080 head_skb->len += le16_to_cpu(desc->rx.size); 3081 skb = ring->tail_skb; 3082 } 3083 3084 dma_sync_single_for_cpu(ring_to_dev(ring), 3085 desc_cb->dma + desc_cb->page_offset, 3086 hns3_buf_size(ring), 3087 DMA_FROM_DEVICE); 3088 3089 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 3090 trace_hns3_rx_desc(ring); 3091 hns3_rx_ring_move_fw(ring); 3092 ring->pending_buf++; 3093 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B))); 3094 3095 return 0; 3096 } 3097 3098 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring, 3099 struct sk_buff *skb, u32 l234info, 3100 u32 bd_base_info, u32 ol_info) 3101 { 3102 u32 l3_type; 3103 3104 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 3105 HNS3_RXD_GRO_SIZE_M, 3106 HNS3_RXD_GRO_SIZE_S); 3107 /* if there is no HW GRO, do not set gro params */ 3108 if (!skb_shinfo(skb)->gso_size) { 3109 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info); 3110 return 0; 3111 } 3112 3113 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info, 3114 HNS3_RXD_GRO_COUNT_M, 3115 HNS3_RXD_GRO_COUNT_S); 3116 3117 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S); 3118 if (l3_type == HNS3_L3_TYPE_IPV4) 3119 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 3120 else if (l3_type == HNS3_L3_TYPE_IPV6) 3121 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 3122 else 3123 return -EFAULT; 3124 3125 return hns3_gro_complete(skb, l234info); 3126 } 3127 3128 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 3129 struct sk_buff *skb, u32 rss_hash) 3130 { 3131 struct hnae3_handle *handle = ring->tqp->handle; 3132 enum pkt_hash_types rss_type; 3133 3134 if (rss_hash) 3135 rss_type = handle->kinfo.rss_type; 3136 else 3137 rss_type = PKT_HASH_TYPE_NONE; 3138 3139 skb_set_hash(skb, rss_hash, rss_type); 3140 } 3141 3142 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb) 3143 { 3144 struct net_device *netdev = ring_to_netdev(ring); 3145 enum hns3_pkt_l2t_type l2_frame_type; 3146 u32 bd_base_info, l234info, ol_info; 3147 struct hns3_desc *desc; 3148 unsigned int len; 3149 int pre_ntc, ret; 3150 3151 /* bdinfo handled below is only valid on the last BD of the 3152 * current packet, and ring->next_to_clean indicates the first 3153 * descriptor of next packet, so need - 1 below. 3154 */ 3155 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) : 3156 (ring->desc_num - 1); 3157 desc = &ring->desc[pre_ntc]; 3158 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3159 l234info = le32_to_cpu(desc->rx.l234_info); 3160 ol_info = le32_to_cpu(desc->rx.ol_info); 3161 3162 /* Based on hw strategy, the tag offloaded will be stored at 3163 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 3164 * in one layer tag case. 3165 */ 3166 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 3167 u16 vlan_tag; 3168 3169 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 3170 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 3171 vlan_tag); 3172 } 3173 3174 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 3175 BIT(HNS3_RXD_L2E_B))))) { 3176 u64_stats_update_begin(&ring->syncp); 3177 if (l234info & BIT(HNS3_RXD_L2E_B)) 3178 ring->stats.l2_err++; 3179 else 3180 ring->stats.err_pkt_len++; 3181 u64_stats_update_end(&ring->syncp); 3182 3183 return -EFAULT; 3184 } 3185 3186 len = skb->len; 3187 3188 /* Do update ip stack process */ 3189 skb->protocol = eth_type_trans(skb, netdev); 3190 3191 /* This is needed in order to enable forwarding support */ 3192 ret = hns3_set_gro_and_checksum(ring, skb, l234info, 3193 bd_base_info, ol_info); 3194 if (unlikely(ret)) { 3195 u64_stats_update_begin(&ring->syncp); 3196 ring->stats.rx_err_cnt++; 3197 u64_stats_update_end(&ring->syncp); 3198 return ret; 3199 } 3200 3201 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 3202 HNS3_RXD_DMAC_S); 3203 3204 u64_stats_update_begin(&ring->syncp); 3205 ring->stats.rx_pkts++; 3206 ring->stats.rx_bytes += len; 3207 3208 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 3209 ring->stats.rx_multicast++; 3210 3211 u64_stats_update_end(&ring->syncp); 3212 3213 ring->tqp_vector->rx_group.total_bytes += len; 3214 3215 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash)); 3216 return 0; 3217 } 3218 3219 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring) 3220 { 3221 struct sk_buff *skb = ring->skb; 3222 struct hns3_desc_cb *desc_cb; 3223 struct hns3_desc *desc; 3224 unsigned int length; 3225 u32 bd_base_info; 3226 int ret; 3227 3228 desc = &ring->desc[ring->next_to_clean]; 3229 desc_cb = &ring->desc_cb[ring->next_to_clean]; 3230 3231 prefetch(desc); 3232 3233 if (!skb) { 3234 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3235 3236 /* Check valid BD */ 3237 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 3238 return -ENXIO; 3239 3240 dma_rmb(); 3241 length = le16_to_cpu(desc->rx.size); 3242 3243 ring->va = desc_cb->buf + desc_cb->page_offset; 3244 3245 dma_sync_single_for_cpu(ring_to_dev(ring), 3246 desc_cb->dma + desc_cb->page_offset, 3247 hns3_buf_size(ring), 3248 DMA_FROM_DEVICE); 3249 3250 /* Prefetch first cache line of first page. 3251 * Idea is to cache few bytes of the header of the packet. 3252 * Our L1 Cache line size is 64B so need to prefetch twice to make 3253 * it 128B. But in actual we can have greater size of caches with 3254 * 128B Level 1 cache lines. In such a case, single fetch would 3255 * suffice to cache in the relevant part of the header. 3256 */ 3257 net_prefetch(ring->va); 3258 3259 ret = hns3_alloc_skb(ring, length, ring->va); 3260 skb = ring->skb; 3261 3262 if (ret < 0) /* alloc buffer fail */ 3263 return ret; 3264 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */ 3265 ret = hns3_add_frag(ring); 3266 if (ret) 3267 return ret; 3268 } 3269 } else { 3270 ret = hns3_add_frag(ring); 3271 if (ret) 3272 return ret; 3273 } 3274 3275 /* As the head data may be changed when GRO enable, copy 3276 * the head data in after other data rx completed 3277 */ 3278 if (skb->len > HNS3_RX_HEAD_SIZE) 3279 memcpy(skb->data, ring->va, 3280 ALIGN(ring->pull_len, sizeof(long))); 3281 3282 ret = hns3_handle_bdinfo(ring, skb); 3283 if (unlikely(ret)) { 3284 dev_kfree_skb_any(skb); 3285 return ret; 3286 } 3287 3288 skb_record_rx_queue(skb, ring->tqp->tqp_index); 3289 return 0; 3290 } 3291 3292 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget, 3293 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 3294 { 3295 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 3296 int unused_count = hns3_desc_unused(ring); 3297 int recv_pkts = 0; 3298 int err; 3299 3300 unused_count -= ring->pending_buf; 3301 3302 while (recv_pkts < budget) { 3303 /* Reuse or realloc buffers */ 3304 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 3305 hns3_nic_alloc_rx_buffers(ring, unused_count); 3306 unused_count = hns3_desc_unused(ring) - 3307 ring->pending_buf; 3308 } 3309 3310 /* Poll one pkt */ 3311 err = hns3_handle_rx_bd(ring); 3312 /* Do not get FE for the packet or failed to alloc skb */ 3313 if (unlikely(!ring->skb || err == -ENXIO)) { 3314 goto out; 3315 } else if (likely(!err)) { 3316 rx_fn(ring, ring->skb); 3317 recv_pkts++; 3318 } 3319 3320 unused_count += ring->pending_buf; 3321 ring->skb = NULL; 3322 ring->pending_buf = 0; 3323 } 3324 3325 out: 3326 /* Make all data has been write before submit */ 3327 if (unused_count > 0) 3328 hns3_nic_alloc_rx_buffers(ring, unused_count); 3329 3330 return recv_pkts; 3331 } 3332 3333 static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group) 3334 { 3335 #define HNS3_RX_LOW_BYTE_RATE 10000 3336 #define HNS3_RX_MID_BYTE_RATE 20000 3337 #define HNS3_RX_ULTRA_PACKET_RATE 40 3338 3339 enum hns3_flow_level_range new_flow_level; 3340 struct hns3_enet_tqp_vector *tqp_vector; 3341 int packets_per_msecs, bytes_per_msecs; 3342 u32 time_passed_ms; 3343 3344 tqp_vector = ring_group->ring->tqp_vector; 3345 time_passed_ms = 3346 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 3347 if (!time_passed_ms) 3348 return false; 3349 3350 do_div(ring_group->total_packets, time_passed_ms); 3351 packets_per_msecs = ring_group->total_packets; 3352 3353 do_div(ring_group->total_bytes, time_passed_ms); 3354 bytes_per_msecs = ring_group->total_bytes; 3355 3356 new_flow_level = ring_group->coal.flow_level; 3357 3358 /* Simple throttlerate management 3359 * 0-10MB/s lower (50000 ints/s) 3360 * 10-20MB/s middle (20000 ints/s) 3361 * 20-1249MB/s high (18000 ints/s) 3362 * > 40000pps ultra (8000 ints/s) 3363 */ 3364 switch (new_flow_level) { 3365 case HNS3_FLOW_LOW: 3366 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 3367 new_flow_level = HNS3_FLOW_MID; 3368 break; 3369 case HNS3_FLOW_MID: 3370 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 3371 new_flow_level = HNS3_FLOW_HIGH; 3372 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 3373 new_flow_level = HNS3_FLOW_LOW; 3374 break; 3375 case HNS3_FLOW_HIGH: 3376 case HNS3_FLOW_ULTRA: 3377 default: 3378 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 3379 new_flow_level = HNS3_FLOW_MID; 3380 break; 3381 } 3382 3383 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 3384 &tqp_vector->rx_group == ring_group) 3385 new_flow_level = HNS3_FLOW_ULTRA; 3386 3387 ring_group->total_bytes = 0; 3388 ring_group->total_packets = 0; 3389 ring_group->coal.flow_level = new_flow_level; 3390 3391 return true; 3392 } 3393 3394 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 3395 { 3396 struct hns3_enet_tqp_vector *tqp_vector; 3397 u16 new_int_gl; 3398 3399 if (!ring_group->ring) 3400 return false; 3401 3402 tqp_vector = ring_group->ring->tqp_vector; 3403 if (!tqp_vector->last_jiffies) 3404 return false; 3405 3406 if (ring_group->total_packets == 0) { 3407 ring_group->coal.int_gl = HNS3_INT_GL_50K; 3408 ring_group->coal.flow_level = HNS3_FLOW_LOW; 3409 return true; 3410 } 3411 3412 if (!hns3_get_new_flow_lvl(ring_group)) 3413 return false; 3414 3415 new_int_gl = ring_group->coal.int_gl; 3416 switch (ring_group->coal.flow_level) { 3417 case HNS3_FLOW_LOW: 3418 new_int_gl = HNS3_INT_GL_50K; 3419 break; 3420 case HNS3_FLOW_MID: 3421 new_int_gl = HNS3_INT_GL_20K; 3422 break; 3423 case HNS3_FLOW_HIGH: 3424 new_int_gl = HNS3_INT_GL_18K; 3425 break; 3426 case HNS3_FLOW_ULTRA: 3427 new_int_gl = HNS3_INT_GL_8K; 3428 break; 3429 default: 3430 break; 3431 } 3432 3433 if (new_int_gl != ring_group->coal.int_gl) { 3434 ring_group->coal.int_gl = new_int_gl; 3435 return true; 3436 } 3437 return false; 3438 } 3439 3440 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 3441 { 3442 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 3443 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 3444 bool rx_update, tx_update; 3445 3446 /* update param every 1000ms */ 3447 if (time_before(jiffies, 3448 tqp_vector->last_jiffies + msecs_to_jiffies(1000))) 3449 return; 3450 3451 if (rx_group->coal.adapt_enable) { 3452 rx_update = hns3_get_new_int_gl(rx_group); 3453 if (rx_update) 3454 hns3_set_vector_coalesce_rx_gl(tqp_vector, 3455 rx_group->coal.int_gl); 3456 } 3457 3458 if (tx_group->coal.adapt_enable) { 3459 tx_update = hns3_get_new_int_gl(tx_group); 3460 if (tx_update) 3461 hns3_set_vector_coalesce_tx_gl(tqp_vector, 3462 tx_group->coal.int_gl); 3463 } 3464 3465 tqp_vector->last_jiffies = jiffies; 3466 } 3467 3468 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 3469 { 3470 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 3471 struct hns3_enet_ring *ring; 3472 int rx_pkt_total = 0; 3473 3474 struct hns3_enet_tqp_vector *tqp_vector = 3475 container_of(napi, struct hns3_enet_tqp_vector, napi); 3476 bool clean_complete = true; 3477 int rx_budget = budget; 3478 3479 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3480 napi_complete(napi); 3481 return 0; 3482 } 3483 3484 /* Since the actual Tx work is minimal, we can give the Tx a larger 3485 * budget and be more aggressive about cleaning up the Tx descriptors. 3486 */ 3487 hns3_for_each_ring(ring, tqp_vector->tx_group) 3488 hns3_clean_tx_ring(ring, budget); 3489 3490 /* make sure rx ring budget not smaller than 1 */ 3491 if (tqp_vector->num_tqps > 1) 3492 rx_budget = max(budget / tqp_vector->num_tqps, 1); 3493 3494 hns3_for_each_ring(ring, tqp_vector->rx_group) { 3495 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 3496 hns3_rx_skb); 3497 3498 if (rx_cleaned >= rx_budget) 3499 clean_complete = false; 3500 3501 rx_pkt_total += rx_cleaned; 3502 } 3503 3504 tqp_vector->rx_group.total_packets += rx_pkt_total; 3505 3506 if (!clean_complete) 3507 return budget; 3508 3509 if (napi_complete(napi) && 3510 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3511 hns3_update_new_int_gl(tqp_vector); 3512 hns3_mask_vector_irq(tqp_vector, 1); 3513 } 3514 3515 return rx_pkt_total; 3516 } 3517 3518 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3519 struct hnae3_ring_chain_node *head) 3520 { 3521 struct pci_dev *pdev = tqp_vector->handle->pdev; 3522 struct hnae3_ring_chain_node *cur_chain = head; 3523 struct hnae3_ring_chain_node *chain; 3524 struct hns3_enet_ring *tx_ring; 3525 struct hns3_enet_ring *rx_ring; 3526 3527 tx_ring = tqp_vector->tx_group.ring; 3528 if (tx_ring) { 3529 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 3530 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3531 HNAE3_RING_TYPE_TX); 3532 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3533 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 3534 3535 cur_chain->next = NULL; 3536 3537 while (tx_ring->next) { 3538 tx_ring = tx_ring->next; 3539 3540 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 3541 GFP_KERNEL); 3542 if (!chain) 3543 goto err_free_chain; 3544 3545 cur_chain->next = chain; 3546 chain->tqp_index = tx_ring->tqp->tqp_index; 3547 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3548 HNAE3_RING_TYPE_TX); 3549 hnae3_set_field(chain->int_gl_idx, 3550 HNAE3_RING_GL_IDX_M, 3551 HNAE3_RING_GL_IDX_S, 3552 HNAE3_RING_GL_TX); 3553 3554 cur_chain = chain; 3555 } 3556 } 3557 3558 rx_ring = tqp_vector->rx_group.ring; 3559 if (!tx_ring && rx_ring) { 3560 cur_chain->next = NULL; 3561 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 3562 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3563 HNAE3_RING_TYPE_RX); 3564 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3565 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3566 3567 rx_ring = rx_ring->next; 3568 } 3569 3570 while (rx_ring) { 3571 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 3572 if (!chain) 3573 goto err_free_chain; 3574 3575 cur_chain->next = chain; 3576 chain->tqp_index = rx_ring->tqp->tqp_index; 3577 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3578 HNAE3_RING_TYPE_RX); 3579 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3580 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3581 3582 cur_chain = chain; 3583 3584 rx_ring = rx_ring->next; 3585 } 3586 3587 return 0; 3588 3589 err_free_chain: 3590 cur_chain = head->next; 3591 while (cur_chain) { 3592 chain = cur_chain->next; 3593 devm_kfree(&pdev->dev, cur_chain); 3594 cur_chain = chain; 3595 } 3596 head->next = NULL; 3597 3598 return -ENOMEM; 3599 } 3600 3601 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3602 struct hnae3_ring_chain_node *head) 3603 { 3604 struct pci_dev *pdev = tqp_vector->handle->pdev; 3605 struct hnae3_ring_chain_node *chain_tmp, *chain; 3606 3607 chain = head->next; 3608 3609 while (chain) { 3610 chain_tmp = chain->next; 3611 devm_kfree(&pdev->dev, chain); 3612 chain = chain_tmp; 3613 } 3614 } 3615 3616 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 3617 struct hns3_enet_ring *ring) 3618 { 3619 ring->next = group->ring; 3620 group->ring = ring; 3621 3622 group->count++; 3623 } 3624 3625 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 3626 { 3627 struct pci_dev *pdev = priv->ae_handle->pdev; 3628 struct hns3_enet_tqp_vector *tqp_vector; 3629 int num_vectors = priv->vector_num; 3630 int numa_node; 3631 int vector_i; 3632 3633 numa_node = dev_to_node(&pdev->dev); 3634 3635 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 3636 tqp_vector = &priv->tqp_vector[vector_i]; 3637 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 3638 &tqp_vector->affinity_mask); 3639 } 3640 } 3641 3642 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 3643 { 3644 struct hnae3_ring_chain_node vector_ring_chain; 3645 struct hnae3_handle *h = priv->ae_handle; 3646 struct hns3_enet_tqp_vector *tqp_vector; 3647 int ret; 3648 int i; 3649 3650 hns3_nic_set_cpumask(priv); 3651 3652 for (i = 0; i < priv->vector_num; i++) { 3653 tqp_vector = &priv->tqp_vector[i]; 3654 hns3_vector_coalesce_init_hw(tqp_vector, priv); 3655 tqp_vector->num_tqps = 0; 3656 } 3657 3658 for (i = 0; i < h->kinfo.num_tqps; i++) { 3659 u16 vector_i = i % priv->vector_num; 3660 u16 tqp_num = h->kinfo.num_tqps; 3661 3662 tqp_vector = &priv->tqp_vector[vector_i]; 3663 3664 hns3_add_ring_to_group(&tqp_vector->tx_group, 3665 &priv->ring[i]); 3666 3667 hns3_add_ring_to_group(&tqp_vector->rx_group, 3668 &priv->ring[i + tqp_num]); 3669 3670 priv->ring[i].tqp_vector = tqp_vector; 3671 priv->ring[i + tqp_num].tqp_vector = tqp_vector; 3672 tqp_vector->num_tqps++; 3673 } 3674 3675 for (i = 0; i < priv->vector_num; i++) { 3676 tqp_vector = &priv->tqp_vector[i]; 3677 3678 tqp_vector->rx_group.total_bytes = 0; 3679 tqp_vector->rx_group.total_packets = 0; 3680 tqp_vector->tx_group.total_bytes = 0; 3681 tqp_vector->tx_group.total_packets = 0; 3682 tqp_vector->handle = h; 3683 3684 ret = hns3_get_vector_ring_chain(tqp_vector, 3685 &vector_ring_chain); 3686 if (ret) 3687 goto map_ring_fail; 3688 3689 ret = h->ae_algo->ops->map_ring_to_vector(h, 3690 tqp_vector->vector_irq, &vector_ring_chain); 3691 3692 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3693 3694 if (ret) 3695 goto map_ring_fail; 3696 3697 netif_napi_add(priv->netdev, &tqp_vector->napi, 3698 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 3699 } 3700 3701 return 0; 3702 3703 map_ring_fail: 3704 while (i--) 3705 netif_napi_del(&priv->tqp_vector[i].napi); 3706 3707 return ret; 3708 } 3709 3710 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 3711 { 3712 struct hnae3_handle *h = priv->ae_handle; 3713 struct hns3_enet_tqp_vector *tqp_vector; 3714 struct hnae3_vector_info *vector; 3715 struct pci_dev *pdev = h->pdev; 3716 u16 tqp_num = h->kinfo.num_tqps; 3717 u16 vector_num; 3718 int ret = 0; 3719 u16 i; 3720 3721 /* RSS size, cpu online and vector_num should be the same */ 3722 /* Should consider 2p/4p later */ 3723 vector_num = min_t(u16, num_online_cpus(), tqp_num); 3724 3725 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 3726 GFP_KERNEL); 3727 if (!vector) 3728 return -ENOMEM; 3729 3730 /* save the actual available vector number */ 3731 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 3732 3733 priv->vector_num = vector_num; 3734 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 3735 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 3736 GFP_KERNEL); 3737 if (!priv->tqp_vector) { 3738 ret = -ENOMEM; 3739 goto out; 3740 } 3741 3742 for (i = 0; i < priv->vector_num; i++) { 3743 tqp_vector = &priv->tqp_vector[i]; 3744 tqp_vector->idx = i; 3745 tqp_vector->mask_addr = vector[i].io_addr; 3746 tqp_vector->vector_irq = vector[i].vector; 3747 hns3_vector_coalesce_init(tqp_vector, priv); 3748 } 3749 3750 out: 3751 devm_kfree(&pdev->dev, vector); 3752 return ret; 3753 } 3754 3755 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 3756 { 3757 group->ring = NULL; 3758 group->count = 0; 3759 } 3760 3761 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 3762 { 3763 struct hnae3_ring_chain_node vector_ring_chain; 3764 struct hnae3_handle *h = priv->ae_handle; 3765 struct hns3_enet_tqp_vector *tqp_vector; 3766 int i; 3767 3768 for (i = 0; i < priv->vector_num; i++) { 3769 tqp_vector = &priv->tqp_vector[i]; 3770 3771 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 3772 continue; 3773 3774 /* Since the mapping can be overwritten, when fail to get the 3775 * chain between vector and ring, we should go on to deal with 3776 * the remaining options. 3777 */ 3778 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain)) 3779 dev_warn(priv->dev, "failed to get ring chain\n"); 3780 3781 h->ae_algo->ops->unmap_ring_from_vector(h, 3782 tqp_vector->vector_irq, &vector_ring_chain); 3783 3784 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3785 3786 hns3_clear_ring_group(&tqp_vector->rx_group); 3787 hns3_clear_ring_group(&tqp_vector->tx_group); 3788 netif_napi_del(&priv->tqp_vector[i].napi); 3789 } 3790 } 3791 3792 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 3793 { 3794 struct hnae3_handle *h = priv->ae_handle; 3795 struct pci_dev *pdev = h->pdev; 3796 int i, ret; 3797 3798 for (i = 0; i < priv->vector_num; i++) { 3799 struct hns3_enet_tqp_vector *tqp_vector; 3800 3801 tqp_vector = &priv->tqp_vector[i]; 3802 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 3803 if (ret) 3804 return; 3805 } 3806 3807 devm_kfree(&pdev->dev, priv->tqp_vector); 3808 } 3809 3810 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 3811 unsigned int ring_type) 3812 { 3813 int queue_num = priv->ae_handle->kinfo.num_tqps; 3814 struct hns3_enet_ring *ring; 3815 int desc_num; 3816 3817 if (ring_type == HNAE3_RING_TYPE_TX) { 3818 ring = &priv->ring[q->tqp_index]; 3819 desc_num = priv->ae_handle->kinfo.num_tx_desc; 3820 ring->queue_index = q->tqp_index; 3821 } else { 3822 ring = &priv->ring[q->tqp_index + queue_num]; 3823 desc_num = priv->ae_handle->kinfo.num_rx_desc; 3824 ring->queue_index = q->tqp_index; 3825 } 3826 3827 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 3828 3829 ring->tqp = q; 3830 ring->desc = NULL; 3831 ring->desc_cb = NULL; 3832 ring->dev = priv->dev; 3833 ring->desc_dma_addr = 0; 3834 ring->buf_size = q->buf_size; 3835 ring->desc_num = desc_num; 3836 ring->next_to_use = 0; 3837 ring->next_to_clean = 0; 3838 ring->last_to_use = 0; 3839 } 3840 3841 static void hns3_queue_to_ring(struct hnae3_queue *tqp, 3842 struct hns3_nic_priv *priv) 3843 { 3844 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 3845 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 3846 } 3847 3848 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 3849 { 3850 struct hnae3_handle *h = priv->ae_handle; 3851 struct pci_dev *pdev = h->pdev; 3852 int i; 3853 3854 priv->ring = devm_kzalloc(&pdev->dev, 3855 array3_size(h->kinfo.num_tqps, 3856 sizeof(*priv->ring), 2), 3857 GFP_KERNEL); 3858 if (!priv->ring) 3859 return -ENOMEM; 3860 3861 for (i = 0; i < h->kinfo.num_tqps; i++) 3862 hns3_queue_to_ring(h->kinfo.tqp[i], priv); 3863 3864 return 0; 3865 } 3866 3867 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 3868 { 3869 if (!priv->ring) 3870 return; 3871 3872 devm_kfree(priv->dev, priv->ring); 3873 priv->ring = NULL; 3874 } 3875 3876 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 3877 { 3878 int ret; 3879 3880 if (ring->desc_num <= 0 || ring->buf_size <= 0) 3881 return -EINVAL; 3882 3883 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num, 3884 sizeof(ring->desc_cb[0]), GFP_KERNEL); 3885 if (!ring->desc_cb) { 3886 ret = -ENOMEM; 3887 goto out; 3888 } 3889 3890 ret = hns3_alloc_desc(ring); 3891 if (ret) 3892 goto out_with_desc_cb; 3893 3894 if (!HNAE3_IS_TX_RING(ring)) { 3895 ret = hns3_alloc_ring_buffers(ring); 3896 if (ret) 3897 goto out_with_desc; 3898 } 3899 3900 return 0; 3901 3902 out_with_desc: 3903 hns3_free_desc(ring); 3904 out_with_desc_cb: 3905 devm_kfree(ring_to_dev(ring), ring->desc_cb); 3906 ring->desc_cb = NULL; 3907 out: 3908 return ret; 3909 } 3910 3911 void hns3_fini_ring(struct hns3_enet_ring *ring) 3912 { 3913 hns3_free_desc(ring); 3914 devm_kfree(ring_to_dev(ring), ring->desc_cb); 3915 ring->desc_cb = NULL; 3916 ring->next_to_clean = 0; 3917 ring->next_to_use = 0; 3918 ring->last_to_use = 0; 3919 ring->pending_buf = 0; 3920 if (ring->skb) { 3921 dev_kfree_skb_any(ring->skb); 3922 ring->skb = NULL; 3923 } 3924 } 3925 3926 static int hns3_buf_size2type(u32 buf_size) 3927 { 3928 int bd_size_type; 3929 3930 switch (buf_size) { 3931 case 512: 3932 bd_size_type = HNS3_BD_SIZE_512_TYPE; 3933 break; 3934 case 1024: 3935 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 3936 break; 3937 case 2048: 3938 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3939 break; 3940 case 4096: 3941 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 3942 break; 3943 default: 3944 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3945 } 3946 3947 return bd_size_type; 3948 } 3949 3950 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 3951 { 3952 dma_addr_t dma = ring->desc_dma_addr; 3953 struct hnae3_queue *q = ring->tqp; 3954 3955 if (!HNAE3_IS_TX_RING(ring)) { 3956 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma); 3957 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 3958 (u32)((dma >> 31) >> 1)); 3959 3960 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 3961 hns3_buf_size2type(ring->buf_size)); 3962 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 3963 ring->desc_num / 8 - 1); 3964 3965 } else { 3966 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 3967 (u32)dma); 3968 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 3969 (u32)((dma >> 31) >> 1)); 3970 3971 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 3972 ring->desc_num / 8 - 1); 3973 } 3974 } 3975 3976 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 3977 { 3978 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3979 int i; 3980 3981 for (i = 0; i < HNAE3_MAX_TC; i++) { 3982 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i]; 3983 int j; 3984 3985 if (!tc_info->enable) 3986 continue; 3987 3988 for (j = 0; j < tc_info->tqp_count; j++) { 3989 struct hnae3_queue *q; 3990 3991 q = priv->ring[tc_info->tqp_offset + j].tqp; 3992 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, 3993 tc_info->tc); 3994 } 3995 } 3996 } 3997 3998 int hns3_init_all_ring(struct hns3_nic_priv *priv) 3999 { 4000 struct hnae3_handle *h = priv->ae_handle; 4001 int ring_num = h->kinfo.num_tqps * 2; 4002 int i, j; 4003 int ret; 4004 4005 for (i = 0; i < ring_num; i++) { 4006 ret = hns3_alloc_ring_memory(&priv->ring[i]); 4007 if (ret) { 4008 dev_err(priv->dev, 4009 "Alloc ring memory fail! ret=%d\n", ret); 4010 goto out_when_alloc_ring_memory; 4011 } 4012 4013 u64_stats_init(&priv->ring[i].syncp); 4014 } 4015 4016 return 0; 4017 4018 out_when_alloc_ring_memory: 4019 for (j = i - 1; j >= 0; j--) 4020 hns3_fini_ring(&priv->ring[j]); 4021 4022 return -ENOMEM; 4023 } 4024 4025 int hns3_uninit_all_ring(struct hns3_nic_priv *priv) 4026 { 4027 struct hnae3_handle *h = priv->ae_handle; 4028 int i; 4029 4030 for (i = 0; i < h->kinfo.num_tqps; i++) { 4031 hns3_fini_ring(&priv->ring[i]); 4032 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]); 4033 } 4034 return 0; 4035 } 4036 4037 /* Set mac addr if it is configured. or leave it to the AE driver */ 4038 static int hns3_init_mac_addr(struct net_device *netdev) 4039 { 4040 struct hns3_nic_priv *priv = netdev_priv(netdev); 4041 struct hnae3_handle *h = priv->ae_handle; 4042 u8 mac_addr_temp[ETH_ALEN]; 4043 int ret = 0; 4044 4045 if (h->ae_algo->ops->get_mac_addr) 4046 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 4047 4048 /* Check if the MAC address is valid, if not get a random one */ 4049 if (!is_valid_ether_addr(mac_addr_temp)) { 4050 eth_hw_addr_random(netdev); 4051 dev_warn(priv->dev, "using random MAC address %pM\n", 4052 netdev->dev_addr); 4053 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) { 4054 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 4055 ether_addr_copy(netdev->perm_addr, mac_addr_temp); 4056 } else { 4057 return 0; 4058 } 4059 4060 if (h->ae_algo->ops->set_mac_addr) 4061 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 4062 4063 return ret; 4064 } 4065 4066 static int hns3_init_phy(struct net_device *netdev) 4067 { 4068 struct hnae3_handle *h = hns3_get_handle(netdev); 4069 int ret = 0; 4070 4071 if (h->ae_algo->ops->mac_connect_phy) 4072 ret = h->ae_algo->ops->mac_connect_phy(h); 4073 4074 return ret; 4075 } 4076 4077 static void hns3_uninit_phy(struct net_device *netdev) 4078 { 4079 struct hnae3_handle *h = hns3_get_handle(netdev); 4080 4081 if (h->ae_algo->ops->mac_disconnect_phy) 4082 h->ae_algo->ops->mac_disconnect_phy(h); 4083 } 4084 4085 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list) 4086 { 4087 struct hnae3_handle *h = hns3_get_handle(netdev); 4088 4089 if (h->ae_algo->ops->del_all_fd_entries) 4090 h->ae_algo->ops->del_all_fd_entries(h, clear_list); 4091 } 4092 4093 static int hns3_client_start(struct hnae3_handle *handle) 4094 { 4095 if (!handle->ae_algo->ops->client_start) 4096 return 0; 4097 4098 return handle->ae_algo->ops->client_start(handle); 4099 } 4100 4101 static void hns3_client_stop(struct hnae3_handle *handle) 4102 { 4103 if (!handle->ae_algo->ops->client_stop) 4104 return; 4105 4106 handle->ae_algo->ops->client_stop(handle); 4107 } 4108 4109 static void hns3_info_show(struct hns3_nic_priv *priv) 4110 { 4111 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 4112 4113 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr); 4114 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps); 4115 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size); 4116 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size); 4117 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len); 4118 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc); 4119 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc); 4120 dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc); 4121 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu); 4122 } 4123 4124 static int hns3_client_init(struct hnae3_handle *handle) 4125 { 4126 struct pci_dev *pdev = handle->pdev; 4127 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4128 u16 alloc_tqps, max_rss_size; 4129 struct hns3_nic_priv *priv; 4130 struct net_device *netdev; 4131 int ret; 4132 4133 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 4134 &max_rss_size); 4135 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 4136 if (!netdev) 4137 return -ENOMEM; 4138 4139 priv = netdev_priv(netdev); 4140 priv->dev = &pdev->dev; 4141 priv->netdev = netdev; 4142 priv->ae_handle = handle; 4143 priv->tx_timeout_count = 0; 4144 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num; 4145 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 4146 4147 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL); 4148 4149 handle->kinfo.netdev = netdev; 4150 handle->priv = (void *)priv; 4151 4152 hns3_init_mac_addr(netdev); 4153 4154 hns3_set_default_feature(netdev); 4155 4156 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 4157 netdev->priv_flags |= IFF_UNICAST_FLT; 4158 netdev->netdev_ops = &hns3_nic_netdev_ops; 4159 SET_NETDEV_DEV(netdev, &pdev->dev); 4160 hns3_ethtool_set_ops(netdev); 4161 4162 /* Carrier off reporting is important to ethtool even BEFORE open */ 4163 netif_carrier_off(netdev); 4164 4165 ret = hns3_get_ring_config(priv); 4166 if (ret) { 4167 ret = -ENOMEM; 4168 goto out_get_ring_cfg; 4169 } 4170 4171 ret = hns3_nic_alloc_vector_data(priv); 4172 if (ret) { 4173 ret = -ENOMEM; 4174 goto out_alloc_vector_data; 4175 } 4176 4177 ret = hns3_nic_init_vector_data(priv); 4178 if (ret) { 4179 ret = -ENOMEM; 4180 goto out_init_vector_data; 4181 } 4182 4183 ret = hns3_init_all_ring(priv); 4184 if (ret) { 4185 ret = -ENOMEM; 4186 goto out_init_ring; 4187 } 4188 4189 ret = hns3_init_phy(netdev); 4190 if (ret) 4191 goto out_init_phy; 4192 4193 ret = register_netdev(netdev); 4194 if (ret) { 4195 dev_err(priv->dev, "probe register netdev fail!\n"); 4196 goto out_reg_netdev_fail; 4197 } 4198 4199 /* the device can work without cpu rmap, only aRFS needs it */ 4200 ret = hns3_set_rx_cpu_rmap(netdev); 4201 if (ret) 4202 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 4203 4204 ret = hns3_nic_init_irq(priv); 4205 if (ret) { 4206 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 4207 hns3_free_rx_cpu_rmap(netdev); 4208 goto out_init_irq_fail; 4209 } 4210 4211 ret = hns3_client_start(handle); 4212 if (ret) { 4213 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4214 goto out_client_start; 4215 } 4216 4217 hns3_dcbnl_setup(handle); 4218 4219 hns3_dbg_init(handle); 4220 4221 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */ 4222 netdev->max_mtu = HNS3_MAX_MTU; 4223 4224 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) 4225 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state); 4226 4227 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4228 4229 if (netif_msg_drv(handle)) 4230 hns3_info_show(priv); 4231 4232 return ret; 4233 4234 out_client_start: 4235 hns3_free_rx_cpu_rmap(netdev); 4236 hns3_nic_uninit_irq(priv); 4237 out_init_irq_fail: 4238 unregister_netdev(netdev); 4239 out_reg_netdev_fail: 4240 hns3_uninit_phy(netdev); 4241 out_init_phy: 4242 hns3_uninit_all_ring(priv); 4243 out_init_ring: 4244 hns3_nic_uninit_vector_data(priv); 4245 out_init_vector_data: 4246 hns3_nic_dealloc_vector_data(priv); 4247 out_alloc_vector_data: 4248 priv->ring = NULL; 4249 out_get_ring_cfg: 4250 priv->ae_handle = NULL; 4251 free_netdev(netdev); 4252 return ret; 4253 } 4254 4255 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 4256 { 4257 struct net_device *netdev = handle->kinfo.netdev; 4258 struct hns3_nic_priv *priv = netdev_priv(netdev); 4259 int ret; 4260 4261 if (netdev->reg_state != NETREG_UNINITIALIZED) 4262 unregister_netdev(netdev); 4263 4264 hns3_client_stop(handle); 4265 4266 hns3_uninit_phy(netdev); 4267 4268 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4269 netdev_warn(netdev, "already uninitialized\n"); 4270 goto out_netdev_free; 4271 } 4272 4273 hns3_free_rx_cpu_rmap(netdev); 4274 4275 hns3_nic_uninit_irq(priv); 4276 4277 hns3_del_all_fd_rules(netdev, true); 4278 4279 hns3_clear_all_ring(handle, true); 4280 4281 hns3_nic_uninit_vector_data(priv); 4282 4283 hns3_nic_dealloc_vector_data(priv); 4284 4285 ret = hns3_uninit_all_ring(priv); 4286 if (ret) 4287 netdev_err(netdev, "uninit ring error\n"); 4288 4289 hns3_put_ring_config(priv); 4290 4291 out_netdev_free: 4292 hns3_dbg_uninit(handle); 4293 free_netdev(netdev); 4294 } 4295 4296 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 4297 { 4298 struct net_device *netdev = handle->kinfo.netdev; 4299 4300 if (!netdev) 4301 return; 4302 4303 if (linkup) { 4304 netif_tx_wake_all_queues(netdev); 4305 netif_carrier_on(netdev); 4306 if (netif_msg_link(handle)) 4307 netdev_info(netdev, "link up\n"); 4308 } else { 4309 netif_carrier_off(netdev); 4310 netif_tx_stop_all_queues(netdev); 4311 if (netif_msg_link(handle)) 4312 netdev_info(netdev, "link down\n"); 4313 } 4314 } 4315 4316 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc) 4317 { 4318 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4319 struct net_device *ndev = kinfo->netdev; 4320 4321 if (tc > HNAE3_MAX_TC) 4322 return -EINVAL; 4323 4324 if (!ndev) 4325 return -ENODEV; 4326 4327 return hns3_nic_set_real_num_queue(ndev); 4328 } 4329 4330 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 4331 { 4332 while (ring->next_to_clean != ring->next_to_use) { 4333 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 4334 hns3_free_buffer_detach(ring, ring->next_to_clean, 0); 4335 ring_ptr_move_fw(ring, next_to_clean); 4336 } 4337 4338 ring->pending_buf = 0; 4339 } 4340 4341 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 4342 { 4343 struct hns3_desc_cb res_cbs; 4344 int ret; 4345 4346 while (ring->next_to_use != ring->next_to_clean) { 4347 /* When a buffer is not reused, it's memory has been 4348 * freed in hns3_handle_rx_bd or will be freed by 4349 * stack, so we need to replace the buffer here. 4350 */ 4351 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4352 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 4353 if (ret) { 4354 u64_stats_update_begin(&ring->syncp); 4355 ring->stats.sw_err_cnt++; 4356 u64_stats_update_end(&ring->syncp); 4357 /* if alloc new buffer fail, exit directly 4358 * and reclear in up flow. 4359 */ 4360 netdev_warn(ring_to_netdev(ring), 4361 "reserve buffer map failed, ret = %d\n", 4362 ret); 4363 return ret; 4364 } 4365 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 4366 } 4367 ring_ptr_move_fw(ring, next_to_use); 4368 } 4369 4370 /* Free the pending skb in rx ring */ 4371 if (ring->skb) { 4372 dev_kfree_skb_any(ring->skb); 4373 ring->skb = NULL; 4374 ring->pending_buf = 0; 4375 } 4376 4377 return 0; 4378 } 4379 4380 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 4381 { 4382 while (ring->next_to_use != ring->next_to_clean) { 4383 /* When a buffer is not reused, it's memory has been 4384 * freed in hns3_handle_rx_bd or will be freed by 4385 * stack, so only need to unmap the buffer here. 4386 */ 4387 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4388 hns3_unmap_buffer(ring, 4389 &ring->desc_cb[ring->next_to_use]); 4390 ring->desc_cb[ring->next_to_use].dma = 0; 4391 } 4392 4393 ring_ptr_move_fw(ring, next_to_use); 4394 } 4395 } 4396 4397 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force) 4398 { 4399 struct net_device *ndev = h->kinfo.netdev; 4400 struct hns3_nic_priv *priv = netdev_priv(ndev); 4401 u32 i; 4402 4403 for (i = 0; i < h->kinfo.num_tqps; i++) { 4404 struct hns3_enet_ring *ring; 4405 4406 ring = &priv->ring[i]; 4407 hns3_clear_tx_ring(ring); 4408 4409 ring = &priv->ring[i + h->kinfo.num_tqps]; 4410 /* Continue to clear other rings even if clearing some 4411 * rings failed. 4412 */ 4413 if (force) 4414 hns3_force_clear_rx_ring(ring); 4415 else 4416 hns3_clear_rx_ring(ring); 4417 } 4418 } 4419 4420 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 4421 { 4422 struct net_device *ndev = h->kinfo.netdev; 4423 struct hns3_nic_priv *priv = netdev_priv(ndev); 4424 struct hns3_enet_ring *rx_ring; 4425 int i, j; 4426 int ret; 4427 4428 for (i = 0; i < h->kinfo.num_tqps; i++) { 4429 ret = h->ae_algo->ops->reset_queue(h, i); 4430 if (ret) 4431 return ret; 4432 4433 hns3_init_ring_hw(&priv->ring[i]); 4434 4435 /* We need to clear tx ring here because self test will 4436 * use the ring and will not run down before up 4437 */ 4438 hns3_clear_tx_ring(&priv->ring[i]); 4439 priv->ring[i].next_to_clean = 0; 4440 priv->ring[i].next_to_use = 0; 4441 priv->ring[i].last_to_use = 0; 4442 4443 rx_ring = &priv->ring[i + h->kinfo.num_tqps]; 4444 hns3_init_ring_hw(rx_ring); 4445 ret = hns3_clear_rx_ring(rx_ring); 4446 if (ret) 4447 return ret; 4448 4449 /* We can not know the hardware head and tail when this 4450 * function is called in reset flow, so we reuse all desc. 4451 */ 4452 for (j = 0; j < rx_ring->desc_num; j++) 4453 hns3_reuse_buffer(rx_ring, j); 4454 4455 rx_ring->next_to_clean = 0; 4456 rx_ring->next_to_use = 0; 4457 } 4458 4459 hns3_init_tx_ring_tc(priv); 4460 4461 return 0; 4462 } 4463 4464 static void hns3_store_coal(struct hns3_nic_priv *priv) 4465 { 4466 /* ethtool only support setting and querying one coal 4467 * configuration for now, so save the vector 0' coal 4468 * configuration here in order to restore it. 4469 */ 4470 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal, 4471 sizeof(struct hns3_enet_coalesce)); 4472 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal, 4473 sizeof(struct hns3_enet_coalesce)); 4474 } 4475 4476 static void hns3_restore_coal(struct hns3_nic_priv *priv) 4477 { 4478 u16 vector_num = priv->vector_num; 4479 int i; 4480 4481 for (i = 0; i < vector_num; i++) { 4482 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal, 4483 sizeof(struct hns3_enet_coalesce)); 4484 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal, 4485 sizeof(struct hns3_enet_coalesce)); 4486 } 4487 } 4488 4489 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 4490 { 4491 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4492 struct net_device *ndev = kinfo->netdev; 4493 struct hns3_nic_priv *priv = netdev_priv(ndev); 4494 4495 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 4496 return 0; 4497 4498 if (!netif_running(ndev)) 4499 return 0; 4500 4501 return hns3_nic_net_stop(ndev); 4502 } 4503 4504 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 4505 { 4506 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4507 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 4508 int ret = 0; 4509 4510 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4511 4512 if (netif_running(kinfo->netdev)) { 4513 ret = hns3_nic_net_open(kinfo->netdev); 4514 if (ret) { 4515 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4516 netdev_err(kinfo->netdev, 4517 "net up fail, ret=%d!\n", ret); 4518 return ret; 4519 } 4520 } 4521 4522 return ret; 4523 } 4524 4525 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 4526 { 4527 struct net_device *netdev = handle->kinfo.netdev; 4528 struct hns3_nic_priv *priv = netdev_priv(netdev); 4529 int ret; 4530 4531 /* Carrier off reporting is important to ethtool even BEFORE open */ 4532 netif_carrier_off(netdev); 4533 4534 ret = hns3_get_ring_config(priv); 4535 if (ret) 4536 return ret; 4537 4538 ret = hns3_nic_alloc_vector_data(priv); 4539 if (ret) 4540 goto err_put_ring; 4541 4542 hns3_restore_coal(priv); 4543 4544 ret = hns3_nic_init_vector_data(priv); 4545 if (ret) 4546 goto err_dealloc_vector; 4547 4548 ret = hns3_init_all_ring(priv); 4549 if (ret) 4550 goto err_uninit_vector; 4551 4552 /* the device can work without cpu rmap, only aRFS needs it */ 4553 ret = hns3_set_rx_cpu_rmap(netdev); 4554 if (ret) 4555 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 4556 4557 ret = hns3_nic_init_irq(priv); 4558 if (ret) { 4559 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 4560 hns3_free_rx_cpu_rmap(netdev); 4561 goto err_init_irq_fail; 4562 } 4563 4564 if (!hns3_is_phys_func(handle->pdev)) 4565 hns3_init_mac_addr(netdev); 4566 4567 ret = hns3_client_start(handle); 4568 if (ret) { 4569 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4570 goto err_client_start_fail; 4571 } 4572 4573 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4574 4575 return ret; 4576 4577 err_client_start_fail: 4578 hns3_free_rx_cpu_rmap(netdev); 4579 hns3_nic_uninit_irq(priv); 4580 err_init_irq_fail: 4581 hns3_uninit_all_ring(priv); 4582 err_uninit_vector: 4583 hns3_nic_uninit_vector_data(priv); 4584 err_dealloc_vector: 4585 hns3_nic_dealloc_vector_data(priv); 4586 err_put_ring: 4587 hns3_put_ring_config(priv); 4588 4589 return ret; 4590 } 4591 4592 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 4593 { 4594 struct net_device *netdev = handle->kinfo.netdev; 4595 struct hns3_nic_priv *priv = netdev_priv(netdev); 4596 int ret; 4597 4598 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4599 netdev_warn(netdev, "already uninitialized\n"); 4600 return 0; 4601 } 4602 4603 hns3_free_rx_cpu_rmap(netdev); 4604 hns3_nic_uninit_irq(priv); 4605 hns3_clear_all_ring(handle, true); 4606 hns3_reset_tx_queue(priv->ae_handle); 4607 4608 hns3_nic_uninit_vector_data(priv); 4609 4610 hns3_store_coal(priv); 4611 4612 hns3_nic_dealloc_vector_data(priv); 4613 4614 ret = hns3_uninit_all_ring(priv); 4615 if (ret) 4616 netdev_err(netdev, "uninit ring error\n"); 4617 4618 hns3_put_ring_config(priv); 4619 4620 return ret; 4621 } 4622 4623 static int hns3_reset_notify(struct hnae3_handle *handle, 4624 enum hnae3_reset_notify_type type) 4625 { 4626 int ret = 0; 4627 4628 switch (type) { 4629 case HNAE3_UP_CLIENT: 4630 ret = hns3_reset_notify_up_enet(handle); 4631 break; 4632 case HNAE3_DOWN_CLIENT: 4633 ret = hns3_reset_notify_down_enet(handle); 4634 break; 4635 case HNAE3_INIT_CLIENT: 4636 ret = hns3_reset_notify_init_enet(handle); 4637 break; 4638 case HNAE3_UNINIT_CLIENT: 4639 ret = hns3_reset_notify_uninit_enet(handle); 4640 break; 4641 default: 4642 break; 4643 } 4644 4645 return ret; 4646 } 4647 4648 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num, 4649 bool rxfh_configured) 4650 { 4651 int ret; 4652 4653 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num, 4654 rxfh_configured); 4655 if (ret) { 4656 dev_err(&handle->pdev->dev, 4657 "Change tqp num(%u) fail.\n", new_tqp_num); 4658 return ret; 4659 } 4660 4661 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT); 4662 if (ret) 4663 return ret; 4664 4665 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT); 4666 if (ret) 4667 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT); 4668 4669 return ret; 4670 } 4671 4672 int hns3_set_channels(struct net_device *netdev, 4673 struct ethtool_channels *ch) 4674 { 4675 struct hnae3_handle *h = hns3_get_handle(netdev); 4676 struct hnae3_knic_private_info *kinfo = &h->kinfo; 4677 bool rxfh_configured = netif_is_rxfh_configured(netdev); 4678 u32 new_tqp_num = ch->combined_count; 4679 u16 org_tqp_num; 4680 int ret; 4681 4682 if (hns3_nic_resetting(netdev)) 4683 return -EBUSY; 4684 4685 if (ch->rx_count || ch->tx_count) 4686 return -EINVAL; 4687 4688 if (new_tqp_num > hns3_get_max_available_channels(h) || 4689 new_tqp_num < 1) { 4690 dev_err(&netdev->dev, 4691 "Change tqps fail, the tqp range is from 1 to %u", 4692 hns3_get_max_available_channels(h)); 4693 return -EINVAL; 4694 } 4695 4696 if (kinfo->rss_size == new_tqp_num) 4697 return 0; 4698 4699 netif_dbg(h, drv, netdev, 4700 "set channels: tqp_num=%u, rxfh=%d\n", 4701 new_tqp_num, rxfh_configured); 4702 4703 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 4704 if (ret) 4705 return ret; 4706 4707 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 4708 if (ret) 4709 return ret; 4710 4711 org_tqp_num = h->kinfo.num_tqps; 4712 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured); 4713 if (ret) { 4714 int ret1; 4715 4716 netdev_warn(netdev, 4717 "Change channels fail, revert to old value\n"); 4718 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured); 4719 if (ret1) { 4720 netdev_err(netdev, 4721 "revert to old channel fail\n"); 4722 return ret1; 4723 } 4724 4725 return ret; 4726 } 4727 4728 return 0; 4729 } 4730 4731 static const struct hns3_hw_error_info hns3_hw_err[] = { 4732 { .type = HNAE3_PPU_POISON_ERROR, 4733 .msg = "PPU poison" }, 4734 { .type = HNAE3_CMDQ_ECC_ERROR, 4735 .msg = "IMP CMDQ error" }, 4736 { .type = HNAE3_IMP_RD_POISON_ERROR, 4737 .msg = "IMP RD poison" }, 4738 { .type = HNAE3_ROCEE_AXI_RESP_ERROR, 4739 .msg = "ROCEE AXI RESP error" }, 4740 }; 4741 4742 static void hns3_process_hw_error(struct hnae3_handle *handle, 4743 enum hnae3_hw_error_type type) 4744 { 4745 int i; 4746 4747 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) { 4748 if (hns3_hw_err[i].type == type) { 4749 dev_err(&handle->pdev->dev, "Detected %s!\n", 4750 hns3_hw_err[i].msg); 4751 break; 4752 } 4753 } 4754 } 4755 4756 static const struct hnae3_client_ops client_ops = { 4757 .init_instance = hns3_client_init, 4758 .uninit_instance = hns3_client_uninit, 4759 .link_status_change = hns3_link_status_change, 4760 .setup_tc = hns3_client_setup_tc, 4761 .reset_notify = hns3_reset_notify, 4762 .process_hw_error = hns3_process_hw_error, 4763 }; 4764 4765 /* hns3_init_module - Driver registration routine 4766 * hns3_init_module is the first routine called when the driver is 4767 * loaded. All it does is register with the PCI subsystem. 4768 */ 4769 static int __init hns3_init_module(void) 4770 { 4771 int ret; 4772 4773 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 4774 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 4775 4776 client.type = HNAE3_CLIENT_KNIC; 4777 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s", 4778 hns3_driver_name); 4779 4780 client.ops = &client_ops; 4781 4782 INIT_LIST_HEAD(&client.node); 4783 4784 hns3_dbg_register_debugfs(hns3_driver_name); 4785 4786 ret = hnae3_register_client(&client); 4787 if (ret) 4788 goto err_reg_client; 4789 4790 ret = pci_register_driver(&hns3_driver); 4791 if (ret) 4792 goto err_reg_driver; 4793 4794 return ret; 4795 4796 err_reg_driver: 4797 hnae3_unregister_client(&client); 4798 err_reg_client: 4799 hns3_dbg_unregister_debugfs(); 4800 return ret; 4801 } 4802 module_init(hns3_init_module); 4803 4804 /* hns3_exit_module - Driver exit cleanup routine 4805 * hns3_exit_module is called just before the driver is removed 4806 * from memory. 4807 */ 4808 static void __exit hns3_exit_module(void) 4809 { 4810 pci_unregister_driver(&hns3_driver); 4811 hnae3_unregister_client(&client); 4812 hns3_dbg_unregister_debugfs(); 4813 } 4814 module_exit(hns3_exit_module); 4815 4816 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 4817 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 4818 MODULE_LICENSE("GPL"); 4819 MODULE_ALIAS("pci:hns-nic"); 4820