1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #ifdef CONFIG_RFS_ACCEL 8 #include <linux/cpu_rmap.h> 9 #endif 10 #include <linux/if_vlan.h> 11 #include <linux/irq.h> 12 #include <linux/ip.h> 13 #include <linux/ipv6.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/skbuff.h> 17 #include <linux/sctp.h> 18 #include <net/gre.h> 19 #include <net/gro.h> 20 #include <net/ip6_checksum.h> 21 #include <net/page_pool/helpers.h> 22 #include <net/pkt_cls.h> 23 #include <net/pkt_sched.h> 24 #include <net/tcp.h> 25 #include <net/vxlan.h> 26 #include <net/geneve.h> 27 28 #include "hnae3.h" 29 #include "hns3_enet.h" 30 /* All hns3 tracepoints are defined by the include below, which 31 * must be included exactly once across the whole kernel with 32 * CREATE_TRACE_POINTS defined 33 */ 34 #define CREATE_TRACE_POINTS 35 #include "hns3_trace.h" 36 37 #define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift)) 38 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE) 39 40 #define hns3_rl_err(fmt, ...) \ 41 do { \ 42 if (net_ratelimit()) \ 43 netdev_err(fmt, ##__VA_ARGS__); \ 44 } while (0) 45 46 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force); 47 48 static const char hns3_driver_name[] = "hns3"; 49 static const char hns3_driver_string[] = 50 "Hisilicon Ethernet Network Driver for Hip08 Family"; 51 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 52 static struct hnae3_client client; 53 54 static int debug = -1; 55 module_param(debug, int, 0); 56 MODULE_PARM_DESC(debug, " Network interface message level setting"); 57 58 static unsigned int tx_sgl = 1; 59 module_param(tx_sgl, uint, 0600); 60 MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping"); 61 62 static bool page_pool_enabled = true; 63 module_param(page_pool_enabled, bool, 0400); 64 65 #define HNS3_SGL_SIZE(nfrag) (sizeof(struct scatterlist) * (nfrag) + \ 66 sizeof(struct sg_table)) 67 #define HNS3_MAX_SGL_SIZE ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \ 68 dma_get_cache_alignment()) 69 70 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 71 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) 72 73 #define HNS3_INNER_VLAN_TAG 1 74 #define HNS3_OUTER_VLAN_TAG 2 75 76 #define HNS3_MIN_TX_LEN 33U 77 #define HNS3_MIN_TUN_PKT_LEN 65U 78 79 /* hns3_pci_tbl - PCI Device ID Table 80 * 81 * Last entry must be all 0s 82 * 83 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 84 * Class, Class Mask, private data (not used) } 85 */ 86 static const struct pci_device_id hns3_pci_tbl[] = { 87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 88 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 89 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 90 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 91 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 92 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 93 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 94 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 95 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 96 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 97 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 98 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 99 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 100 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 101 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 102 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 103 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 104 /* required last entry */ 105 {0,} 106 }; 107 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 108 109 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t, h) \ 110 { ptype, \ 111 l, \ 112 CHECKSUM_##s, \ 113 HNS3_L3_TYPE_##t, \ 114 1, \ 115 h} 116 117 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \ 118 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0, \ 119 PKT_HASH_TYPE_NONE } 120 121 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = { 122 HNS3_RX_PTYPE_UNUSED_ENTRY(0), 123 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP, PKT_HASH_TYPE_NONE), 124 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP, PKT_HASH_TYPE_NONE), 125 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP, PKT_HASH_TYPE_NONE), 126 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 127 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 128 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 129 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM, PKT_HASH_TYPE_NONE), 130 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 131 HNS3_RX_PTYPE_UNUSED_ENTRY(9), 132 HNS3_RX_PTYPE_UNUSED_ENTRY(10), 133 HNS3_RX_PTYPE_UNUSED_ENTRY(11), 134 HNS3_RX_PTYPE_UNUSED_ENTRY(12), 135 HNS3_RX_PTYPE_UNUSED_ENTRY(13), 136 HNS3_RX_PTYPE_UNUSED_ENTRY(14), 137 HNS3_RX_PTYPE_UNUSED_ENTRY(15), 138 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 139 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE), 140 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE), 141 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 142 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 143 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4, PKT_HASH_TYPE_NONE), 144 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 145 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4, PKT_HASH_TYPE_L3), 146 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4, PKT_HASH_TYPE_L3), 147 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 148 HNS3_RX_PTYPE_UNUSED_ENTRY(26), 149 HNS3_RX_PTYPE_UNUSED_ENTRY(27), 150 HNS3_RX_PTYPE_UNUSED_ENTRY(28), 151 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 152 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 153 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 154 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 155 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 156 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 157 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 158 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 159 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 160 HNS3_RX_PTYPE_UNUSED_ENTRY(38), 161 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 162 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 163 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 164 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 165 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 166 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 167 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 168 HNS3_RX_PTYPE_UNUSED_ENTRY(46), 169 HNS3_RX_PTYPE_UNUSED_ENTRY(47), 170 HNS3_RX_PTYPE_UNUSED_ENTRY(48), 171 HNS3_RX_PTYPE_UNUSED_ENTRY(49), 172 HNS3_RX_PTYPE_UNUSED_ENTRY(50), 173 HNS3_RX_PTYPE_UNUSED_ENTRY(51), 174 HNS3_RX_PTYPE_UNUSED_ENTRY(52), 175 HNS3_RX_PTYPE_UNUSED_ENTRY(53), 176 HNS3_RX_PTYPE_UNUSED_ENTRY(54), 177 HNS3_RX_PTYPE_UNUSED_ENTRY(55), 178 HNS3_RX_PTYPE_UNUSED_ENTRY(56), 179 HNS3_RX_PTYPE_UNUSED_ENTRY(57), 180 HNS3_RX_PTYPE_UNUSED_ENTRY(58), 181 HNS3_RX_PTYPE_UNUSED_ENTRY(59), 182 HNS3_RX_PTYPE_UNUSED_ENTRY(60), 183 HNS3_RX_PTYPE_UNUSED_ENTRY(61), 184 HNS3_RX_PTYPE_UNUSED_ENTRY(62), 185 HNS3_RX_PTYPE_UNUSED_ENTRY(63), 186 HNS3_RX_PTYPE_UNUSED_ENTRY(64), 187 HNS3_RX_PTYPE_UNUSED_ENTRY(65), 188 HNS3_RX_PTYPE_UNUSED_ENTRY(66), 189 HNS3_RX_PTYPE_UNUSED_ENTRY(67), 190 HNS3_RX_PTYPE_UNUSED_ENTRY(68), 191 HNS3_RX_PTYPE_UNUSED_ENTRY(69), 192 HNS3_RX_PTYPE_UNUSED_ENTRY(70), 193 HNS3_RX_PTYPE_UNUSED_ENTRY(71), 194 HNS3_RX_PTYPE_UNUSED_ENTRY(72), 195 HNS3_RX_PTYPE_UNUSED_ENTRY(73), 196 HNS3_RX_PTYPE_UNUSED_ENTRY(74), 197 HNS3_RX_PTYPE_UNUSED_ENTRY(75), 198 HNS3_RX_PTYPE_UNUSED_ENTRY(76), 199 HNS3_RX_PTYPE_UNUSED_ENTRY(77), 200 HNS3_RX_PTYPE_UNUSED_ENTRY(78), 201 HNS3_RX_PTYPE_UNUSED_ENTRY(79), 202 HNS3_RX_PTYPE_UNUSED_ENTRY(80), 203 HNS3_RX_PTYPE_UNUSED_ENTRY(81), 204 HNS3_RX_PTYPE_UNUSED_ENTRY(82), 205 HNS3_RX_PTYPE_UNUSED_ENTRY(83), 206 HNS3_RX_PTYPE_UNUSED_ENTRY(84), 207 HNS3_RX_PTYPE_UNUSED_ENTRY(85), 208 HNS3_RX_PTYPE_UNUSED_ENTRY(86), 209 HNS3_RX_PTYPE_UNUSED_ENTRY(87), 210 HNS3_RX_PTYPE_UNUSED_ENTRY(88), 211 HNS3_RX_PTYPE_UNUSED_ENTRY(89), 212 HNS3_RX_PTYPE_UNUSED_ENTRY(90), 213 HNS3_RX_PTYPE_UNUSED_ENTRY(91), 214 HNS3_RX_PTYPE_UNUSED_ENTRY(92), 215 HNS3_RX_PTYPE_UNUSED_ENTRY(93), 216 HNS3_RX_PTYPE_UNUSED_ENTRY(94), 217 HNS3_RX_PTYPE_UNUSED_ENTRY(95), 218 HNS3_RX_PTYPE_UNUSED_ENTRY(96), 219 HNS3_RX_PTYPE_UNUSED_ENTRY(97), 220 HNS3_RX_PTYPE_UNUSED_ENTRY(98), 221 HNS3_RX_PTYPE_UNUSED_ENTRY(99), 222 HNS3_RX_PTYPE_UNUSED_ENTRY(100), 223 HNS3_RX_PTYPE_UNUSED_ENTRY(101), 224 HNS3_RX_PTYPE_UNUSED_ENTRY(102), 225 HNS3_RX_PTYPE_UNUSED_ENTRY(103), 226 HNS3_RX_PTYPE_UNUSED_ENTRY(104), 227 HNS3_RX_PTYPE_UNUSED_ENTRY(105), 228 HNS3_RX_PTYPE_UNUSED_ENTRY(106), 229 HNS3_RX_PTYPE_UNUSED_ENTRY(107), 230 HNS3_RX_PTYPE_UNUSED_ENTRY(108), 231 HNS3_RX_PTYPE_UNUSED_ENTRY(109), 232 HNS3_RX_PTYPE_UNUSED_ENTRY(110), 233 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 234 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 235 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 236 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 237 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6, PKT_HASH_TYPE_L3), 238 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 239 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6, PKT_HASH_TYPE_L3), 240 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6, PKT_HASH_TYPE_L3), 241 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 242 HNS3_RX_PTYPE_UNUSED_ENTRY(120), 243 HNS3_RX_PTYPE_UNUSED_ENTRY(121), 244 HNS3_RX_PTYPE_UNUSED_ENTRY(122), 245 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 246 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 247 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 248 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 249 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 250 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 251 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 252 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 253 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 254 HNS3_RX_PTYPE_UNUSED_ENTRY(132), 255 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 256 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 257 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 258 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 259 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 260 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 261 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 262 HNS3_RX_PTYPE_UNUSED_ENTRY(140), 263 HNS3_RX_PTYPE_UNUSED_ENTRY(141), 264 HNS3_RX_PTYPE_UNUSED_ENTRY(142), 265 HNS3_RX_PTYPE_UNUSED_ENTRY(143), 266 HNS3_RX_PTYPE_UNUSED_ENTRY(144), 267 HNS3_RX_PTYPE_UNUSED_ENTRY(145), 268 HNS3_RX_PTYPE_UNUSED_ENTRY(146), 269 HNS3_RX_PTYPE_UNUSED_ENTRY(147), 270 HNS3_RX_PTYPE_UNUSED_ENTRY(148), 271 HNS3_RX_PTYPE_UNUSED_ENTRY(149), 272 HNS3_RX_PTYPE_UNUSED_ENTRY(150), 273 HNS3_RX_PTYPE_UNUSED_ENTRY(151), 274 HNS3_RX_PTYPE_UNUSED_ENTRY(152), 275 HNS3_RX_PTYPE_UNUSED_ENTRY(153), 276 HNS3_RX_PTYPE_UNUSED_ENTRY(154), 277 HNS3_RX_PTYPE_UNUSED_ENTRY(155), 278 HNS3_RX_PTYPE_UNUSED_ENTRY(156), 279 HNS3_RX_PTYPE_UNUSED_ENTRY(157), 280 HNS3_RX_PTYPE_UNUSED_ENTRY(158), 281 HNS3_RX_PTYPE_UNUSED_ENTRY(159), 282 HNS3_RX_PTYPE_UNUSED_ENTRY(160), 283 HNS3_RX_PTYPE_UNUSED_ENTRY(161), 284 HNS3_RX_PTYPE_UNUSED_ENTRY(162), 285 HNS3_RX_PTYPE_UNUSED_ENTRY(163), 286 HNS3_RX_PTYPE_UNUSED_ENTRY(164), 287 HNS3_RX_PTYPE_UNUSED_ENTRY(165), 288 HNS3_RX_PTYPE_UNUSED_ENTRY(166), 289 HNS3_RX_PTYPE_UNUSED_ENTRY(167), 290 HNS3_RX_PTYPE_UNUSED_ENTRY(168), 291 HNS3_RX_PTYPE_UNUSED_ENTRY(169), 292 HNS3_RX_PTYPE_UNUSED_ENTRY(170), 293 HNS3_RX_PTYPE_UNUSED_ENTRY(171), 294 HNS3_RX_PTYPE_UNUSED_ENTRY(172), 295 HNS3_RX_PTYPE_UNUSED_ENTRY(173), 296 HNS3_RX_PTYPE_UNUSED_ENTRY(174), 297 HNS3_RX_PTYPE_UNUSED_ENTRY(175), 298 HNS3_RX_PTYPE_UNUSED_ENTRY(176), 299 HNS3_RX_PTYPE_UNUSED_ENTRY(177), 300 HNS3_RX_PTYPE_UNUSED_ENTRY(178), 301 HNS3_RX_PTYPE_UNUSED_ENTRY(179), 302 HNS3_RX_PTYPE_UNUSED_ENTRY(180), 303 HNS3_RX_PTYPE_UNUSED_ENTRY(181), 304 HNS3_RX_PTYPE_UNUSED_ENTRY(182), 305 HNS3_RX_PTYPE_UNUSED_ENTRY(183), 306 HNS3_RX_PTYPE_UNUSED_ENTRY(184), 307 HNS3_RX_PTYPE_UNUSED_ENTRY(185), 308 HNS3_RX_PTYPE_UNUSED_ENTRY(186), 309 HNS3_RX_PTYPE_UNUSED_ENTRY(187), 310 HNS3_RX_PTYPE_UNUSED_ENTRY(188), 311 HNS3_RX_PTYPE_UNUSED_ENTRY(189), 312 HNS3_RX_PTYPE_UNUSED_ENTRY(190), 313 HNS3_RX_PTYPE_UNUSED_ENTRY(191), 314 HNS3_RX_PTYPE_UNUSED_ENTRY(192), 315 HNS3_RX_PTYPE_UNUSED_ENTRY(193), 316 HNS3_RX_PTYPE_UNUSED_ENTRY(194), 317 HNS3_RX_PTYPE_UNUSED_ENTRY(195), 318 HNS3_RX_PTYPE_UNUSED_ENTRY(196), 319 HNS3_RX_PTYPE_UNUSED_ENTRY(197), 320 HNS3_RX_PTYPE_UNUSED_ENTRY(198), 321 HNS3_RX_PTYPE_UNUSED_ENTRY(199), 322 HNS3_RX_PTYPE_UNUSED_ENTRY(200), 323 HNS3_RX_PTYPE_UNUSED_ENTRY(201), 324 HNS3_RX_PTYPE_UNUSED_ENTRY(202), 325 HNS3_RX_PTYPE_UNUSED_ENTRY(203), 326 HNS3_RX_PTYPE_UNUSED_ENTRY(204), 327 HNS3_RX_PTYPE_UNUSED_ENTRY(205), 328 HNS3_RX_PTYPE_UNUSED_ENTRY(206), 329 HNS3_RX_PTYPE_UNUSED_ENTRY(207), 330 HNS3_RX_PTYPE_UNUSED_ENTRY(208), 331 HNS3_RX_PTYPE_UNUSED_ENTRY(209), 332 HNS3_RX_PTYPE_UNUSED_ENTRY(210), 333 HNS3_RX_PTYPE_UNUSED_ENTRY(211), 334 HNS3_RX_PTYPE_UNUSED_ENTRY(212), 335 HNS3_RX_PTYPE_UNUSED_ENTRY(213), 336 HNS3_RX_PTYPE_UNUSED_ENTRY(214), 337 HNS3_RX_PTYPE_UNUSED_ENTRY(215), 338 HNS3_RX_PTYPE_UNUSED_ENTRY(216), 339 HNS3_RX_PTYPE_UNUSED_ENTRY(217), 340 HNS3_RX_PTYPE_UNUSED_ENTRY(218), 341 HNS3_RX_PTYPE_UNUSED_ENTRY(219), 342 HNS3_RX_PTYPE_UNUSED_ENTRY(220), 343 HNS3_RX_PTYPE_UNUSED_ENTRY(221), 344 HNS3_RX_PTYPE_UNUSED_ENTRY(222), 345 HNS3_RX_PTYPE_UNUSED_ENTRY(223), 346 HNS3_RX_PTYPE_UNUSED_ENTRY(224), 347 HNS3_RX_PTYPE_UNUSED_ENTRY(225), 348 HNS3_RX_PTYPE_UNUSED_ENTRY(226), 349 HNS3_RX_PTYPE_UNUSED_ENTRY(227), 350 HNS3_RX_PTYPE_UNUSED_ENTRY(228), 351 HNS3_RX_PTYPE_UNUSED_ENTRY(229), 352 HNS3_RX_PTYPE_UNUSED_ENTRY(230), 353 HNS3_RX_PTYPE_UNUSED_ENTRY(231), 354 HNS3_RX_PTYPE_UNUSED_ENTRY(232), 355 HNS3_RX_PTYPE_UNUSED_ENTRY(233), 356 HNS3_RX_PTYPE_UNUSED_ENTRY(234), 357 HNS3_RX_PTYPE_UNUSED_ENTRY(235), 358 HNS3_RX_PTYPE_UNUSED_ENTRY(236), 359 HNS3_RX_PTYPE_UNUSED_ENTRY(237), 360 HNS3_RX_PTYPE_UNUSED_ENTRY(238), 361 HNS3_RX_PTYPE_UNUSED_ENTRY(239), 362 HNS3_RX_PTYPE_UNUSED_ENTRY(240), 363 HNS3_RX_PTYPE_UNUSED_ENTRY(241), 364 HNS3_RX_PTYPE_UNUSED_ENTRY(242), 365 HNS3_RX_PTYPE_UNUSED_ENTRY(243), 366 HNS3_RX_PTYPE_UNUSED_ENTRY(244), 367 HNS3_RX_PTYPE_UNUSED_ENTRY(245), 368 HNS3_RX_PTYPE_UNUSED_ENTRY(246), 369 HNS3_RX_PTYPE_UNUSED_ENTRY(247), 370 HNS3_RX_PTYPE_UNUSED_ENTRY(248), 371 HNS3_RX_PTYPE_UNUSED_ENTRY(249), 372 HNS3_RX_PTYPE_UNUSED_ENTRY(250), 373 HNS3_RX_PTYPE_UNUSED_ENTRY(251), 374 HNS3_RX_PTYPE_UNUSED_ENTRY(252), 375 HNS3_RX_PTYPE_UNUSED_ENTRY(253), 376 HNS3_RX_PTYPE_UNUSED_ENTRY(254), 377 HNS3_RX_PTYPE_UNUSED_ENTRY(255), 378 }; 379 380 #define HNS3_INVALID_PTYPE \ 381 ARRAY_SIZE(hns3_rx_ptype_tbl) 382 383 static irqreturn_t hns3_irq_handle(int irq, void *vector) 384 { 385 struct hns3_enet_tqp_vector *tqp_vector = vector; 386 387 napi_schedule_irqoff(&tqp_vector->napi); 388 tqp_vector->event_cnt++; 389 390 return IRQ_HANDLED; 391 } 392 393 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 394 { 395 struct hns3_enet_tqp_vector *tqp_vectors; 396 unsigned int i; 397 398 for (i = 0; i < priv->vector_num; i++) { 399 tqp_vectors = &priv->tqp_vector[i]; 400 401 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 402 continue; 403 404 /* clear the affinity mask */ 405 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 406 407 /* release the irq resource */ 408 free_irq(tqp_vectors->vector_irq, tqp_vectors); 409 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 410 } 411 } 412 413 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 414 { 415 struct hns3_enet_tqp_vector *tqp_vectors; 416 int txrx_int_idx = 0; 417 int rx_int_idx = 0; 418 int tx_int_idx = 0; 419 unsigned int i; 420 int ret; 421 422 for (i = 0; i < priv->vector_num; i++) { 423 tqp_vectors = &priv->tqp_vector[i]; 424 425 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 426 continue; 427 428 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 429 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 430 "%s-%s-%s-%d", hns3_driver_name, 431 pci_name(priv->ae_handle->pdev), 432 "TxRx", txrx_int_idx++); 433 txrx_int_idx++; 434 } else if (tqp_vectors->rx_group.ring) { 435 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 436 "%s-%s-%s-%d", hns3_driver_name, 437 pci_name(priv->ae_handle->pdev), 438 "Rx", rx_int_idx++); 439 } else if (tqp_vectors->tx_group.ring) { 440 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 441 "%s-%s-%s-%d", hns3_driver_name, 442 pci_name(priv->ae_handle->pdev), 443 "Tx", tx_int_idx++); 444 } else { 445 /* Skip this unused q_vector */ 446 continue; 447 } 448 449 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 450 451 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN); 452 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 453 tqp_vectors->name, tqp_vectors); 454 if (ret) { 455 netdev_err(priv->netdev, "request irq(%d) fail\n", 456 tqp_vectors->vector_irq); 457 hns3_nic_uninit_irq(priv); 458 return ret; 459 } 460 461 irq_set_affinity_hint(tqp_vectors->vector_irq, 462 &tqp_vectors->affinity_mask); 463 464 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 465 } 466 467 return 0; 468 } 469 470 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 471 u32 mask_en) 472 { 473 writel(mask_en, tqp_vector->mask_addr); 474 } 475 476 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 477 { 478 napi_enable(&tqp_vector->napi); 479 enable_irq(tqp_vector->vector_irq); 480 481 /* enable vector */ 482 hns3_mask_vector_irq(tqp_vector, 1); 483 } 484 485 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 486 { 487 /* disable vector */ 488 hns3_mask_vector_irq(tqp_vector, 0); 489 490 disable_irq(tqp_vector->vector_irq); 491 napi_disable(&tqp_vector->napi); 492 cancel_work_sync(&tqp_vector->rx_group.dim.work); 493 cancel_work_sync(&tqp_vector->tx_group.dim.work); 494 } 495 496 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 497 u32 rl_value) 498 { 499 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 500 501 /* this defines the configuration for RL (Interrupt Rate Limiter). 502 * Rl defines rate of interrupts i.e. number of interrupts-per-second 503 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 504 */ 505 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable && 506 !tqp_vector->rx_group.coal.adapt_enable) 507 /* According to the hardware, the range of rl_reg is 508 * 0-59 and the unit is 4. 509 */ 510 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 511 512 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 513 } 514 515 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 516 u32 gl_value) 517 { 518 u32 new_val; 519 520 if (tqp_vector->rx_group.coal.unit_1us) 521 new_val = gl_value | HNS3_INT_GL_1US; 522 else 523 new_val = hns3_gl_usec_to_reg(gl_value); 524 525 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 526 } 527 528 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 529 u32 gl_value) 530 { 531 u32 new_val; 532 533 if (tqp_vector->tx_group.coal.unit_1us) 534 new_val = gl_value | HNS3_INT_GL_1US; 535 else 536 new_val = hns3_gl_usec_to_reg(gl_value); 537 538 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 539 } 540 541 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector, 542 u32 ql_value) 543 { 544 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET); 545 } 546 547 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector, 548 u32 ql_value) 549 { 550 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET); 551 } 552 553 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector, 554 struct hns3_nic_priv *priv) 555 { 556 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 557 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 558 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 559 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal; 560 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal; 561 562 tx_coal->adapt_enable = ptx_coal->adapt_enable; 563 rx_coal->adapt_enable = prx_coal->adapt_enable; 564 565 tx_coal->int_gl = ptx_coal->int_gl; 566 rx_coal->int_gl = prx_coal->int_gl; 567 568 rx_coal->flow_level = prx_coal->flow_level; 569 tx_coal->flow_level = ptx_coal->flow_level; 570 571 /* device version above V3(include V3), GL can configure 1us 572 * unit, so uses 1us unit. 573 */ 574 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) { 575 tx_coal->unit_1us = 1; 576 rx_coal->unit_1us = 1; 577 } 578 579 if (ae_dev->dev_specs.int_ql_max) { 580 tx_coal->ql_enable = 1; 581 rx_coal->ql_enable = 1; 582 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 583 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 584 tx_coal->int_ql = ptx_coal->int_ql; 585 rx_coal->int_ql = prx_coal->int_ql; 586 } 587 } 588 589 static void 590 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 591 struct hns3_nic_priv *priv) 592 { 593 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 594 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 595 struct hnae3_handle *h = priv->ae_handle; 596 597 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl); 598 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl); 599 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 600 601 if (tx_coal->ql_enable) 602 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql); 603 604 if (rx_coal->ql_enable) 605 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql); 606 } 607 608 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 609 { 610 struct hnae3_handle *h = hns3_get_handle(netdev); 611 struct hnae3_knic_private_info *kinfo = &h->kinfo; 612 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 613 unsigned int queue_size = kinfo->num_tqps; 614 int i, ret; 615 616 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) { 617 netdev_reset_tc(netdev); 618 } else { 619 ret = netdev_set_num_tc(netdev, tc_info->num_tc); 620 if (ret) { 621 netdev_err(netdev, 622 "netdev_set_num_tc fail, ret=%d!\n", ret); 623 return ret; 624 } 625 626 for (i = 0; i < tc_info->num_tc; i++) 627 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i], 628 tc_info->tqp_offset[i]); 629 } 630 631 ret = netif_set_real_num_tx_queues(netdev, queue_size); 632 if (ret) { 633 netdev_err(netdev, 634 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret); 635 return ret; 636 } 637 638 ret = netif_set_real_num_rx_queues(netdev, queue_size); 639 if (ret) { 640 netdev_err(netdev, 641 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 642 return ret; 643 } 644 645 return 0; 646 } 647 648 u16 hns3_get_max_available_channels(struct hnae3_handle *h) 649 { 650 u16 alloc_tqps, max_rss_size, rss_size; 651 652 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 653 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc; 654 655 return min_t(u16, rss_size, max_rss_size); 656 } 657 658 static void hns3_tqp_enable(struct hnae3_queue *tqp) 659 { 660 u32 rcb_reg; 661 662 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 663 rcb_reg |= BIT(HNS3_RING_EN_B); 664 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 665 } 666 667 static void hns3_tqp_disable(struct hnae3_queue *tqp) 668 { 669 u32 rcb_reg; 670 671 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 672 rcb_reg &= ~BIT(HNS3_RING_EN_B); 673 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 674 } 675 676 static void hns3_free_rx_cpu_rmap(struct net_device *netdev) 677 { 678 #ifdef CONFIG_RFS_ACCEL 679 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 680 netdev->rx_cpu_rmap = NULL; 681 #endif 682 } 683 684 static int hns3_set_rx_cpu_rmap(struct net_device *netdev) 685 { 686 #ifdef CONFIG_RFS_ACCEL 687 struct hns3_nic_priv *priv = netdev_priv(netdev); 688 struct hns3_enet_tqp_vector *tqp_vector; 689 int i, ret; 690 691 if (!netdev->rx_cpu_rmap) { 692 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num); 693 if (!netdev->rx_cpu_rmap) 694 return -ENOMEM; 695 } 696 697 for (i = 0; i < priv->vector_num; i++) { 698 tqp_vector = &priv->tqp_vector[i]; 699 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap, 700 tqp_vector->vector_irq); 701 if (ret) { 702 hns3_free_rx_cpu_rmap(netdev); 703 return ret; 704 } 705 } 706 #endif 707 return 0; 708 } 709 710 static int hns3_nic_net_up(struct net_device *netdev) 711 { 712 struct hns3_nic_priv *priv = netdev_priv(netdev); 713 struct hnae3_handle *h = priv->ae_handle; 714 int i, j; 715 int ret; 716 717 ret = hns3_nic_reset_all_ring(h); 718 if (ret) 719 return ret; 720 721 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 722 723 /* enable the vectors */ 724 for (i = 0; i < priv->vector_num; i++) 725 hns3_vector_enable(&priv->tqp_vector[i]); 726 727 /* enable rcb */ 728 for (j = 0; j < h->kinfo.num_tqps; j++) 729 hns3_tqp_enable(h->kinfo.tqp[j]); 730 731 /* start the ae_dev */ 732 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 733 if (ret) { 734 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 735 while (j--) 736 hns3_tqp_disable(h->kinfo.tqp[j]); 737 738 for (j = i - 1; j >= 0; j--) 739 hns3_vector_disable(&priv->tqp_vector[j]); 740 } 741 742 return ret; 743 } 744 745 static void hns3_config_xps(struct hns3_nic_priv *priv) 746 { 747 int i; 748 749 for (i = 0; i < priv->vector_num; i++) { 750 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 751 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 752 753 while (ring) { 754 int ret; 755 756 ret = netif_set_xps_queue(priv->netdev, 757 &tqp_vector->affinity_mask, 758 ring->tqp->tqp_index); 759 if (ret) 760 netdev_warn(priv->netdev, 761 "set xps queue failed: %d", ret); 762 763 ring = ring->next; 764 } 765 } 766 } 767 768 static int hns3_nic_net_open(struct net_device *netdev) 769 { 770 struct hns3_nic_priv *priv = netdev_priv(netdev); 771 struct hnae3_handle *h = hns3_get_handle(netdev); 772 struct hnae3_knic_private_info *kinfo; 773 int i, ret; 774 775 if (hns3_nic_resetting(netdev)) 776 return -EBUSY; 777 778 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 779 netdev_warn(netdev, "net open repeatedly!\n"); 780 return 0; 781 } 782 783 netif_carrier_off(netdev); 784 785 ret = hns3_nic_set_real_num_queue(netdev); 786 if (ret) 787 return ret; 788 789 ret = hns3_nic_net_up(netdev); 790 if (ret) { 791 netdev_err(netdev, "net up fail, ret=%d!\n", ret); 792 return ret; 793 } 794 795 kinfo = &h->kinfo; 796 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 797 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]); 798 799 if (h->ae_algo->ops->set_timer_task) 800 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 801 802 hns3_config_xps(priv); 803 804 netif_dbg(h, drv, netdev, "net open\n"); 805 806 return 0; 807 } 808 809 static void hns3_reset_tx_queue(struct hnae3_handle *h) 810 { 811 struct net_device *ndev = h->kinfo.netdev; 812 struct hns3_nic_priv *priv = netdev_priv(ndev); 813 struct netdev_queue *dev_queue; 814 u32 i; 815 816 for (i = 0; i < h->kinfo.num_tqps; i++) { 817 dev_queue = netdev_get_tx_queue(ndev, 818 priv->ring[i].queue_index); 819 netdev_tx_reset_queue(dev_queue); 820 } 821 } 822 823 static void hns3_nic_net_down(struct net_device *netdev) 824 { 825 struct hns3_nic_priv *priv = netdev_priv(netdev); 826 struct hnae3_handle *h = hns3_get_handle(netdev); 827 const struct hnae3_ae_ops *ops; 828 int i; 829 830 /* disable vectors */ 831 for (i = 0; i < priv->vector_num; i++) 832 hns3_vector_disable(&priv->tqp_vector[i]); 833 834 /* disable rcb */ 835 for (i = 0; i < h->kinfo.num_tqps; i++) 836 hns3_tqp_disable(h->kinfo.tqp[i]); 837 838 /* stop ae_dev */ 839 ops = priv->ae_handle->ae_algo->ops; 840 if (ops->stop) 841 ops->stop(priv->ae_handle); 842 843 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 844 * during reset process, because driver may not be able 845 * to disable the ring through firmware when downing the netdev. 846 */ 847 if (!hns3_nic_resetting(netdev)) 848 hns3_clear_all_ring(priv->ae_handle, false); 849 850 hns3_reset_tx_queue(priv->ae_handle); 851 } 852 853 static int hns3_nic_net_stop(struct net_device *netdev) 854 { 855 struct hns3_nic_priv *priv = netdev_priv(netdev); 856 struct hnae3_handle *h = hns3_get_handle(netdev); 857 858 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 859 return 0; 860 861 netif_dbg(h, drv, netdev, "net stop\n"); 862 863 if (h->ae_algo->ops->set_timer_task) 864 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 865 866 netif_carrier_off(netdev); 867 netif_tx_disable(netdev); 868 869 hns3_nic_net_down(netdev); 870 871 return 0; 872 } 873 874 static int hns3_nic_uc_sync(struct net_device *netdev, 875 const unsigned char *addr) 876 { 877 struct hnae3_handle *h = hns3_get_handle(netdev); 878 879 if (h->ae_algo->ops->add_uc_addr) 880 return h->ae_algo->ops->add_uc_addr(h, addr); 881 882 return 0; 883 } 884 885 static int hns3_nic_uc_unsync(struct net_device *netdev, 886 const unsigned char *addr) 887 { 888 struct hnae3_handle *h = hns3_get_handle(netdev); 889 890 /* need ignore the request of removing device address, because 891 * we store the device address and other addresses of uc list 892 * in the function's mac filter list. 893 */ 894 if (ether_addr_equal(addr, netdev->dev_addr)) 895 return 0; 896 897 if (h->ae_algo->ops->rm_uc_addr) 898 return h->ae_algo->ops->rm_uc_addr(h, addr); 899 900 return 0; 901 } 902 903 static int hns3_nic_mc_sync(struct net_device *netdev, 904 const unsigned char *addr) 905 { 906 struct hnae3_handle *h = hns3_get_handle(netdev); 907 908 if (h->ae_algo->ops->add_mc_addr) 909 return h->ae_algo->ops->add_mc_addr(h, addr); 910 911 return 0; 912 } 913 914 static int hns3_nic_mc_unsync(struct net_device *netdev, 915 const unsigned char *addr) 916 { 917 struct hnae3_handle *h = hns3_get_handle(netdev); 918 919 if (h->ae_algo->ops->rm_mc_addr) 920 return h->ae_algo->ops->rm_mc_addr(h, addr); 921 922 return 0; 923 } 924 925 static u8 hns3_get_netdev_flags(struct net_device *netdev) 926 { 927 u8 flags = 0; 928 929 if (netdev->flags & IFF_PROMISC) 930 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 931 else if (netdev->flags & IFF_ALLMULTI) 932 flags = HNAE3_USER_MPE; 933 934 return flags; 935 } 936 937 static void hns3_nic_set_rx_mode(struct net_device *netdev) 938 { 939 struct hnae3_handle *h = hns3_get_handle(netdev); 940 u8 new_flags; 941 942 new_flags = hns3_get_netdev_flags(netdev); 943 944 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 945 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync); 946 947 /* User mode Promisc mode enable and vlan filtering is disabled to 948 * let all packets in. 949 */ 950 h->netdev_flags = new_flags; 951 hns3_request_update_promisc_mode(h); 952 } 953 954 void hns3_request_update_promisc_mode(struct hnae3_handle *handle) 955 { 956 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 957 958 if (ops->request_update_promisc_mode) 959 ops->request_update_promisc_mode(handle); 960 } 961 962 static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring) 963 { 964 struct hns3_tx_spare *tx_spare = ring->tx_spare; 965 u32 ntc, ntu; 966 967 /* This smp_load_acquire() pairs with smp_store_release() in 968 * hns3_tx_spare_update() called in tx desc cleaning process. 969 */ 970 ntc = smp_load_acquire(&tx_spare->last_to_clean); 971 ntu = tx_spare->next_to_use; 972 973 if (ntc > ntu) 974 return ntc - ntu - 1; 975 976 /* The free tx buffer is divided into two part, so pick the 977 * larger one. 978 */ 979 return max(ntc, tx_spare->len - ntu) - 1; 980 } 981 982 static void hns3_tx_spare_update(struct hns3_enet_ring *ring) 983 { 984 struct hns3_tx_spare *tx_spare = ring->tx_spare; 985 986 if (!tx_spare || 987 tx_spare->last_to_clean == tx_spare->next_to_clean) 988 return; 989 990 /* This smp_store_release() pairs with smp_load_acquire() in 991 * hns3_tx_spare_space() called in xmit process. 992 */ 993 smp_store_release(&tx_spare->last_to_clean, 994 tx_spare->next_to_clean); 995 } 996 997 static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring, 998 struct sk_buff *skb, 999 u32 space) 1000 { 1001 u32 len = skb->len <= ring->tx_copybreak ? skb->len : 1002 skb_headlen(skb); 1003 1004 if (len > ring->tx_copybreak) 1005 return false; 1006 1007 if (ALIGN(len, dma_get_cache_alignment()) > space) { 1008 hns3_ring_stats_update(ring, tx_spare_full); 1009 return false; 1010 } 1011 1012 return true; 1013 } 1014 1015 static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring, 1016 struct sk_buff *skb, 1017 u32 space) 1018 { 1019 if (skb->len <= ring->tx_copybreak || !tx_sgl || 1020 (!skb_has_frag_list(skb) && 1021 skb_shinfo(skb)->nr_frags < tx_sgl)) 1022 return false; 1023 1024 if (space < HNS3_MAX_SGL_SIZE) { 1025 hns3_ring_stats_update(ring, tx_spare_full); 1026 return false; 1027 } 1028 1029 return true; 1030 } 1031 1032 static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring) 1033 { 1034 u32 alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size; 1035 struct hns3_tx_spare *tx_spare; 1036 struct page *page; 1037 dma_addr_t dma; 1038 int order; 1039 1040 if (!alloc_size) 1041 return; 1042 1043 order = get_order(alloc_size); 1044 if (order > MAX_PAGE_ORDER) { 1045 if (net_ratelimit()) 1046 dev_warn(ring_to_dev(ring), "failed to allocate tx spare buffer, exceed to max order\n"); 1047 return; 1048 } 1049 1050 tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare), 1051 GFP_KERNEL); 1052 if (!tx_spare) { 1053 /* The driver still work without the tx spare buffer */ 1054 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n"); 1055 goto devm_kzalloc_error; 1056 } 1057 1058 page = alloc_pages_node(dev_to_node(ring_to_dev(ring)), 1059 GFP_KERNEL, order); 1060 if (!page) { 1061 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n"); 1062 goto alloc_pages_error; 1063 } 1064 1065 dma = dma_map_page(ring_to_dev(ring), page, 0, 1066 PAGE_SIZE << order, DMA_TO_DEVICE); 1067 if (dma_mapping_error(ring_to_dev(ring), dma)) { 1068 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n"); 1069 goto dma_mapping_error; 1070 } 1071 1072 tx_spare->dma = dma; 1073 tx_spare->buf = page_address(page); 1074 tx_spare->len = PAGE_SIZE << order; 1075 ring->tx_spare = tx_spare; 1076 return; 1077 1078 dma_mapping_error: 1079 put_page(page); 1080 alloc_pages_error: 1081 devm_kfree(ring_to_dev(ring), tx_spare); 1082 devm_kzalloc_error: 1083 ring->tqp->handle->kinfo.tx_spare_buf_size = 0; 1084 } 1085 1086 /* Use hns3_tx_spare_space() to make sure there is enough buffer 1087 * before calling below function to allocate tx buffer. 1088 */ 1089 static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring, 1090 unsigned int size, dma_addr_t *dma, 1091 u32 *cb_len) 1092 { 1093 struct hns3_tx_spare *tx_spare = ring->tx_spare; 1094 u32 ntu = tx_spare->next_to_use; 1095 1096 size = ALIGN(size, dma_get_cache_alignment()); 1097 *cb_len = size; 1098 1099 /* Tx spare buffer wraps back here because the end of 1100 * freed tx buffer is not enough. 1101 */ 1102 if (ntu + size > tx_spare->len) { 1103 *cb_len += (tx_spare->len - ntu); 1104 ntu = 0; 1105 } 1106 1107 tx_spare->next_to_use = ntu + size; 1108 if (tx_spare->next_to_use == tx_spare->len) 1109 tx_spare->next_to_use = 0; 1110 1111 *dma = tx_spare->dma + ntu; 1112 1113 return tx_spare->buf + ntu; 1114 } 1115 1116 static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len) 1117 { 1118 struct hns3_tx_spare *tx_spare = ring->tx_spare; 1119 1120 if (len > tx_spare->next_to_use) { 1121 len -= tx_spare->next_to_use; 1122 tx_spare->next_to_use = tx_spare->len - len; 1123 } else { 1124 tx_spare->next_to_use -= len; 1125 } 1126 } 1127 1128 static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring, 1129 struct hns3_desc_cb *cb) 1130 { 1131 struct hns3_tx_spare *tx_spare = ring->tx_spare; 1132 u32 ntc = tx_spare->next_to_clean; 1133 u32 len = cb->length; 1134 1135 tx_spare->next_to_clean += len; 1136 1137 if (tx_spare->next_to_clean >= tx_spare->len) { 1138 tx_spare->next_to_clean -= tx_spare->len; 1139 1140 if (tx_spare->next_to_clean) { 1141 ntc = 0; 1142 len = tx_spare->next_to_clean; 1143 } 1144 } 1145 1146 /* This tx spare buffer is only really reclaimed after calling 1147 * hns3_tx_spare_update(), so it is still safe to use the info in 1148 * the tx buffer to do the dma sync or sg unmapping after 1149 * tx_spare->next_to_clean is moved forword. 1150 */ 1151 if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) { 1152 dma_addr_t dma = tx_spare->dma + ntc; 1153 1154 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len, 1155 DMA_TO_DEVICE); 1156 } else { 1157 struct sg_table *sgt = tx_spare->buf + ntc; 1158 1159 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents, 1160 DMA_TO_DEVICE); 1161 } 1162 } 1163 1164 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs, 1165 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes) 1166 { 1167 u32 l4_offset, hdr_len; 1168 union l3_hdr_info l3; 1169 union l4_hdr_info l4; 1170 u32 l4_paylen; 1171 int ret; 1172 1173 if (!skb_is_gso(skb)) 1174 return 0; 1175 1176 ret = skb_cow_head(skb, 0); 1177 if (unlikely(ret < 0)) 1178 return ret; 1179 1180 l3.hdr = skb_network_header(skb); 1181 l4.hdr = skb_transport_header(skb); 1182 1183 /* Software should clear the IPv4's checksum field when tso is 1184 * needed. 1185 */ 1186 if (l3.v4->version == 4) 1187 l3.v4->check = 0; 1188 1189 /* tunnel packet */ 1190 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 1191 SKB_GSO_GRE_CSUM | 1192 SKB_GSO_UDP_TUNNEL | 1193 SKB_GSO_UDP_TUNNEL_CSUM)) { 1194 /* reset l3&l4 pointers from outer to inner headers */ 1195 l3.hdr = skb_inner_network_header(skb); 1196 l4.hdr = skb_inner_transport_header(skb); 1197 1198 /* Software should clear the IPv4's checksum field when 1199 * tso is needed. 1200 */ 1201 if (l3.v4->version == 4) 1202 l3.v4->check = 0; 1203 } 1204 1205 /* normal or tunnel packet */ 1206 l4_offset = l4.hdr - skb->data; 1207 1208 /* remove payload length from inner pseudo checksum when tso */ 1209 l4_paylen = skb->len - l4_offset; 1210 1211 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 1212 hdr_len = sizeof(*l4.udp) + l4_offset; 1213 csum_replace_by_diff(&l4.udp->check, 1214 (__force __wsum)htonl(l4_paylen)); 1215 } else { 1216 hdr_len = (l4.tcp->doff << 2) + l4_offset; 1217 csum_replace_by_diff(&l4.tcp->check, 1218 (__force __wsum)htonl(l4_paylen)); 1219 } 1220 1221 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len; 1222 1223 /* find the txbd field values */ 1224 *paylen_fdop_ol4cs = skb->len - hdr_len; 1225 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 1226 1227 /* offload outer UDP header checksum */ 1228 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM) 1229 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1); 1230 1231 /* get MSS for TSO */ 1232 *mss = skb_shinfo(skb)->gso_size; 1233 1234 trace_hns3_tso(skb); 1235 1236 return 0; 1237 } 1238 1239 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 1240 u8 *il4_proto) 1241 { 1242 union l3_hdr_info l3; 1243 unsigned char *l4_hdr; 1244 unsigned char *exthdr; 1245 u8 l4_proto_tmp; 1246 __be16 frag_off; 1247 1248 /* find outer header point */ 1249 l3.hdr = skb_network_header(skb); 1250 l4_hdr = skb_transport_header(skb); 1251 1252 if (skb->protocol == htons(ETH_P_IPV6)) { 1253 exthdr = l3.hdr + sizeof(*l3.v6); 1254 l4_proto_tmp = l3.v6->nexthdr; 1255 if (l4_hdr != exthdr) 1256 ipv6_skip_exthdr(skb, exthdr - skb->data, 1257 &l4_proto_tmp, &frag_off); 1258 } else if (skb->protocol == htons(ETH_P_IP)) { 1259 l4_proto_tmp = l3.v4->protocol; 1260 } else { 1261 return -EINVAL; 1262 } 1263 1264 *ol4_proto = l4_proto_tmp; 1265 1266 /* tunnel packet */ 1267 if (!skb->encapsulation) { 1268 *il4_proto = 0; 1269 return 0; 1270 } 1271 1272 /* find inner header point */ 1273 l3.hdr = skb_inner_network_header(skb); 1274 l4_hdr = skb_inner_transport_header(skb); 1275 1276 if (l3.v6->version == 6) { 1277 exthdr = l3.hdr + sizeof(*l3.v6); 1278 l4_proto_tmp = l3.v6->nexthdr; 1279 if (l4_hdr != exthdr) 1280 ipv6_skip_exthdr(skb, exthdr - skb->data, 1281 &l4_proto_tmp, &frag_off); 1282 } else if (l3.v4->version == 4) { 1283 l4_proto_tmp = l3.v4->protocol; 1284 } 1285 1286 *il4_proto = l4_proto_tmp; 1287 1288 return 0; 1289 } 1290 1291 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 1292 * and it is udp packet, which has a dest port as the IANA assigned. 1293 * the hardware is expected to do the checksum offload, but the 1294 * hardware will not do the checksum offload when udp dest port is 1295 * 4789, 4790 or 6081. 1296 */ 1297 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 1298 { 1299 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 1300 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 1301 union l4_hdr_info l4; 1302 1303 /* device version above V3(include V3), the hardware can 1304 * do this checksum offload. 1305 */ 1306 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 1307 return false; 1308 1309 l4.hdr = skb_transport_header(skb); 1310 1311 if (!(!skb->encapsulation && 1312 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) || 1313 l4.udp->dest == htons(GENEVE_UDP_PORT) || 1314 l4.udp->dest == htons(IANA_VXLAN_GPE_UDP_PORT)))) 1315 return false; 1316 1317 return true; 1318 } 1319 1320 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 1321 u32 *ol_type_vlan_len_msec) 1322 { 1323 u32 l2_len, l3_len, l4_len; 1324 unsigned char *il2_hdr; 1325 union l3_hdr_info l3; 1326 union l4_hdr_info l4; 1327 1328 l3.hdr = skb_network_header(skb); 1329 l4.hdr = skb_transport_header(skb); 1330 1331 /* compute OL2 header size, defined in 2 Bytes */ 1332 l2_len = l3.hdr - skb->data; 1333 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1); 1334 1335 /* compute OL3 header size, defined in 4 Bytes */ 1336 l3_len = l4.hdr - l3.hdr; 1337 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2); 1338 1339 il2_hdr = skb_inner_mac_header(skb); 1340 /* compute OL4 header size, defined in 4 Bytes */ 1341 l4_len = il2_hdr - l4.hdr; 1342 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2); 1343 1344 /* define outer network header type */ 1345 if (skb->protocol == htons(ETH_P_IP)) { 1346 if (skb_is_gso(skb)) 1347 hns3_set_field(*ol_type_vlan_len_msec, 1348 HNS3_TXD_OL3T_S, 1349 HNS3_OL3T_IPV4_CSUM); 1350 else 1351 hns3_set_field(*ol_type_vlan_len_msec, 1352 HNS3_TXD_OL3T_S, 1353 HNS3_OL3T_IPV4_NO_CSUM); 1354 } else if (skb->protocol == htons(ETH_P_IPV6)) { 1355 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 1356 HNS3_OL3T_IPV6); 1357 } 1358 1359 if (ol4_proto == IPPROTO_UDP) 1360 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 1361 HNS3_TUN_MAC_IN_UDP); 1362 else if (ol4_proto == IPPROTO_GRE) 1363 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 1364 HNS3_TUN_NVGRE); 1365 } 1366 1367 static void hns3_set_l3_type(struct sk_buff *skb, union l3_hdr_info l3, 1368 u32 *type_cs_vlan_tso) 1369 { 1370 if (l3.v4->version == 4) { 1371 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 1372 HNS3_L3T_IPV4); 1373 1374 /* the stack computes the IP header already, the only time we 1375 * need the hardware to recompute it is in the case of TSO. 1376 */ 1377 if (skb_is_gso(skb)) 1378 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 1379 } else if (l3.v6->version == 6) { 1380 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 1381 HNS3_L3T_IPV6); 1382 } 1383 } 1384 1385 static int hns3_set_l4_csum_length(struct sk_buff *skb, union l4_hdr_info l4, 1386 u32 l4_proto, u32 *type_cs_vlan_tso) 1387 { 1388 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 1389 switch (l4_proto) { 1390 case IPPROTO_TCP: 1391 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1392 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1393 HNS3_L4T_TCP); 1394 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1395 l4.tcp->doff); 1396 break; 1397 case IPPROTO_UDP: 1398 if (hns3_tunnel_csum_bug(skb)) { 1399 int ret = skb_put_padto(skb, HNS3_MIN_TUN_PKT_LEN); 1400 1401 return ret ? ret : skb_checksum_help(skb); 1402 } 1403 1404 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1405 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1406 HNS3_L4T_UDP); 1407 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1408 (sizeof(struct udphdr) >> 2)); 1409 break; 1410 case IPPROTO_SCTP: 1411 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1412 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1413 HNS3_L4T_SCTP); 1414 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1415 (sizeof(struct sctphdr) >> 2)); 1416 break; 1417 default: 1418 /* drop the skb tunnel packet if hardware don't support, 1419 * because hardware can't calculate csum when TSO. 1420 */ 1421 if (skb_is_gso(skb)) 1422 return -EDOM; 1423 1424 /* the stack computes the IP header already, 1425 * driver calculate l4 checksum when not TSO. 1426 */ 1427 return skb_checksum_help(skb); 1428 } 1429 1430 return 0; 1431 } 1432 1433 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 1434 u8 il4_proto, u32 *type_cs_vlan_tso, 1435 u32 *ol_type_vlan_len_msec) 1436 { 1437 unsigned char *l2_hdr = skb->data; 1438 u32 l4_proto = ol4_proto; 1439 union l4_hdr_info l4; 1440 union l3_hdr_info l3; 1441 u32 l2_len, l3_len; 1442 1443 l4.hdr = skb_transport_header(skb); 1444 l3.hdr = skb_network_header(skb); 1445 1446 /* handle encapsulation skb */ 1447 if (skb->encapsulation) { 1448 /* If this is a not UDP/GRE encapsulation skb */ 1449 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) { 1450 /* drop the skb tunnel packet if hardware don't support, 1451 * because hardware can't calculate csum when TSO. 1452 */ 1453 if (skb_is_gso(skb)) 1454 return -EDOM; 1455 1456 /* the stack computes the IP header already, 1457 * driver calculate l4 checksum when not TSO. 1458 */ 1459 return skb_checksum_help(skb); 1460 } 1461 1462 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec); 1463 1464 /* switch to inner header */ 1465 l2_hdr = skb_inner_mac_header(skb); 1466 l3.hdr = skb_inner_network_header(skb); 1467 l4.hdr = skb_inner_transport_header(skb); 1468 l4_proto = il4_proto; 1469 } 1470 1471 hns3_set_l3_type(skb, l3, type_cs_vlan_tso); 1472 1473 /* compute inner(/normal) L2 header size, defined in 2 Bytes */ 1474 l2_len = l3.hdr - l2_hdr; 1475 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 1476 1477 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 1478 l3_len = l4.hdr - l3.hdr; 1479 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 1480 1481 return hns3_set_l4_csum_length(skb, l4, l4_proto, type_cs_vlan_tso); 1482 } 1483 1484 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring, 1485 struct sk_buff *skb) 1486 { 1487 struct hnae3_handle *handle = tx_ring->tqp->handle; 1488 struct hnae3_ae_dev *ae_dev; 1489 struct vlan_ethhdr *vhdr; 1490 int rc; 1491 1492 if (!(skb->protocol == htons(ETH_P_8021Q) || 1493 skb_vlan_tag_present(skb))) 1494 return 0; 1495 1496 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert 1497 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it 1498 * will cause RAS error. 1499 */ 1500 ae_dev = pci_get_drvdata(handle->pdev); 1501 if (unlikely(skb_vlan_tagged_multi(skb) && 1502 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 && 1503 handle->port_base_vlan_state == 1504 HNAE3_PORT_BASE_VLAN_ENABLE)) 1505 return -EINVAL; 1506 1507 if (skb->protocol == htons(ETH_P_8021Q) && 1508 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 1509 /* When HW VLAN acceleration is turned off, and the stack 1510 * sets the protocol to 802.1q, the driver just need to 1511 * set the protocol to the encapsulated ethertype. 1512 */ 1513 skb->protocol = vlan_get_protocol(skb); 1514 return 0; 1515 } 1516 1517 if (skb_vlan_tag_present(skb)) { 1518 /* Based on hw strategy, use out_vtag in two layer tag case, 1519 * and use inner_vtag in one tag case. 1520 */ 1521 if (skb->protocol == htons(ETH_P_8021Q) && 1522 handle->port_base_vlan_state == 1523 HNAE3_PORT_BASE_VLAN_DISABLE) 1524 rc = HNS3_OUTER_VLAN_TAG; 1525 else 1526 rc = HNS3_INNER_VLAN_TAG; 1527 1528 skb->protocol = vlan_get_protocol(skb); 1529 return rc; 1530 } 1531 1532 rc = skb_cow_head(skb, 0); 1533 if (unlikely(rc < 0)) 1534 return rc; 1535 1536 vhdr = skb_vlan_eth_hdr(skb); 1537 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT) 1538 & VLAN_PRIO_MASK); 1539 1540 skb->protocol = vlan_get_protocol(skb); 1541 return 0; 1542 } 1543 1544 /* check if the hardware is capable of checksum offloading */ 1545 static bool hns3_check_hw_tx_csum(struct sk_buff *skb) 1546 { 1547 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 1548 1549 /* Kindly note, due to backward compatibility of the TX descriptor, 1550 * HW checksum of the non-IP packets and GSO packets is handled at 1551 * different place in the following code 1552 */ 1553 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) || 1554 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state)) 1555 return false; 1556 1557 return true; 1558 } 1559 1560 struct hns3_desc_param { 1561 u32 paylen_ol4cs; 1562 u32 ol_type_vlan_len_msec; 1563 u32 type_cs_vlan_tso; 1564 u16 mss_hw_csum; 1565 u16 inner_vtag; 1566 u16 out_vtag; 1567 }; 1568 1569 static void hns3_init_desc_data(struct sk_buff *skb, struct hns3_desc_param *pa) 1570 { 1571 pa->paylen_ol4cs = skb->len; 1572 pa->ol_type_vlan_len_msec = 0; 1573 pa->type_cs_vlan_tso = 0; 1574 pa->mss_hw_csum = 0; 1575 pa->inner_vtag = 0; 1576 pa->out_vtag = 0; 1577 } 1578 1579 static int hns3_handle_vlan_info(struct hns3_enet_ring *ring, 1580 struct sk_buff *skb, 1581 struct hns3_desc_param *param) 1582 { 1583 int ret; 1584 1585 ret = hns3_handle_vtags(ring, skb); 1586 if (unlikely(ret < 0)) { 1587 hns3_ring_stats_update(ring, tx_vlan_err); 1588 return ret; 1589 } else if (ret == HNS3_INNER_VLAN_TAG) { 1590 param->inner_vtag = skb_vlan_tag_get(skb); 1591 param->inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1592 VLAN_PRIO_MASK; 1593 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1); 1594 } else if (ret == HNS3_OUTER_VLAN_TAG) { 1595 param->out_vtag = skb_vlan_tag_get(skb); 1596 param->out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1597 VLAN_PRIO_MASK; 1598 hns3_set_field(param->ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B, 1599 1); 1600 } 1601 return 0; 1602 } 1603 1604 static int hns3_handle_csum_partial(struct hns3_enet_ring *ring, 1605 struct sk_buff *skb, 1606 struct hns3_desc_cb *desc_cb, 1607 struct hns3_desc_param *param) 1608 { 1609 u8 ol4_proto, il4_proto; 1610 int ret; 1611 1612 if (hns3_check_hw_tx_csum(skb)) { 1613 /* set checksum start and offset, defined in 2 Bytes */ 1614 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_CSUM_START_S, 1615 skb_checksum_start_offset(skb) >> 1); 1616 hns3_set_field(param->ol_type_vlan_len_msec, 1617 HNS3_TXD_CSUM_OFFSET_S, 1618 skb->csum_offset >> 1); 1619 param->mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B); 1620 return 0; 1621 } 1622 1623 skb_reset_mac_len(skb); 1624 1625 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1626 if (unlikely(ret < 0)) { 1627 hns3_ring_stats_update(ring, tx_l4_proto_err); 1628 return ret; 1629 } 1630 1631 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto, 1632 ¶m->type_cs_vlan_tso, 1633 ¶m->ol_type_vlan_len_msec); 1634 if (unlikely(ret < 0)) { 1635 hns3_ring_stats_update(ring, tx_l2l3l4_err); 1636 return ret; 1637 } 1638 1639 ret = hns3_set_tso(skb, ¶m->paylen_ol4cs, ¶m->mss_hw_csum, 1640 ¶m->type_cs_vlan_tso, &desc_cb->send_bytes); 1641 if (unlikely(ret < 0)) { 1642 hns3_ring_stats_update(ring, tx_tso_err); 1643 return ret; 1644 } 1645 return 0; 1646 } 1647 1648 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring, 1649 struct sk_buff *skb, struct hns3_desc *desc, 1650 struct hns3_desc_cb *desc_cb) 1651 { 1652 struct hns3_desc_param param; 1653 int ret; 1654 1655 hns3_init_desc_data(skb, ¶m); 1656 ret = hns3_handle_vlan_info(ring, skb, ¶m); 1657 if (unlikely(ret < 0)) 1658 return ret; 1659 1660 desc_cb->send_bytes = skb->len; 1661 1662 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1663 ret = hns3_handle_csum_partial(ring, skb, desc_cb, ¶m); 1664 if (ret) 1665 return ret; 1666 } 1667 1668 /* Set txbd */ 1669 desc->tx.ol_type_vlan_len_msec = 1670 cpu_to_le32(param.ol_type_vlan_len_msec); 1671 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(param.type_cs_vlan_tso); 1672 desc->tx.paylen_ol4cs = cpu_to_le32(param.paylen_ol4cs); 1673 desc->tx.mss_hw_csum = cpu_to_le16(param.mss_hw_csum); 1674 desc->tx.vlan_tag = cpu_to_le16(param.inner_vtag); 1675 desc->tx.outer_vlan_tag = cpu_to_le16(param.out_vtag); 1676 1677 return 0; 1678 } 1679 1680 static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma, 1681 unsigned int size) 1682 { 1683 #define HNS3_LIKELY_BD_NUM 1 1684 1685 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1686 unsigned int frag_buf_num; 1687 int k, sizeoflast; 1688 1689 if (likely(size <= HNS3_MAX_BD_SIZE)) { 1690 desc->addr = cpu_to_le64(dma); 1691 desc->tx.send_size = cpu_to_le16(size); 1692 desc->tx.bdtp_fe_sc_vld_ra_ri = 1693 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1694 1695 trace_hns3_tx_desc(ring, ring->next_to_use); 1696 ring_ptr_move_fw(ring, next_to_use); 1697 return HNS3_LIKELY_BD_NUM; 1698 } 1699 1700 frag_buf_num = hns3_tx_bd_count(size); 1701 sizeoflast = size % HNS3_MAX_BD_SIZE; 1702 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1703 1704 /* When frag size is bigger than hardware limit, split this frag */ 1705 for (k = 0; k < frag_buf_num; k++) { 1706 /* now, fill the descriptor */ 1707 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1708 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1709 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1710 desc->tx.bdtp_fe_sc_vld_ra_ri = 1711 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1712 1713 trace_hns3_tx_desc(ring, ring->next_to_use); 1714 /* move ring pointer to next */ 1715 ring_ptr_move_fw(ring, next_to_use); 1716 1717 desc = &ring->desc[ring->next_to_use]; 1718 } 1719 1720 return frag_buf_num; 1721 } 1722 1723 static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv, 1724 unsigned int type) 1725 { 1726 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1727 struct device *dev = ring_to_dev(ring); 1728 unsigned int size; 1729 dma_addr_t dma; 1730 1731 if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) { 1732 struct sk_buff *skb = (struct sk_buff *)priv; 1733 1734 size = skb_headlen(skb); 1735 if (!size) 1736 return 0; 1737 1738 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1739 } else if (type & DESC_TYPE_BOUNCE_HEAD) { 1740 /* Head data has been filled in hns3_handle_tx_bounce(), 1741 * just return 0 here. 1742 */ 1743 return 0; 1744 } else { 1745 skb_frag_t *frag = (skb_frag_t *)priv; 1746 1747 size = skb_frag_size(frag); 1748 if (!size) 1749 return 0; 1750 1751 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1752 } 1753 1754 if (unlikely(dma_mapping_error(dev, dma))) { 1755 hns3_ring_stats_update(ring, sw_err_cnt); 1756 return -ENOMEM; 1757 } 1758 1759 desc_cb->priv = priv; 1760 desc_cb->length = size; 1761 desc_cb->dma = dma; 1762 desc_cb->type = type; 1763 1764 return hns3_fill_desc(ring, dma, size); 1765 } 1766 1767 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1768 unsigned int bd_num) 1769 { 1770 unsigned int size; 1771 int i; 1772 1773 size = skb_headlen(skb); 1774 while (size > HNS3_MAX_BD_SIZE) { 1775 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1776 size -= HNS3_MAX_BD_SIZE; 1777 1778 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1779 return bd_num; 1780 } 1781 1782 if (size) { 1783 bd_size[bd_num++] = size; 1784 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1785 return bd_num; 1786 } 1787 1788 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1789 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1790 size = skb_frag_size(frag); 1791 if (!size) 1792 continue; 1793 1794 while (size > HNS3_MAX_BD_SIZE) { 1795 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1796 size -= HNS3_MAX_BD_SIZE; 1797 1798 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1799 return bd_num; 1800 } 1801 1802 bd_size[bd_num++] = size; 1803 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1804 return bd_num; 1805 } 1806 1807 return bd_num; 1808 } 1809 1810 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1811 u8 max_non_tso_bd_num, unsigned int bd_num, 1812 unsigned int recursion_level) 1813 { 1814 #define HNS3_MAX_RECURSION_LEVEL 24 1815 1816 struct sk_buff *frag_skb; 1817 1818 /* If the total len is within the max bd limit */ 1819 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level && 1820 !skb_has_frag_list(skb) && 1821 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num)) 1822 return skb_shinfo(skb)->nr_frags + 1U; 1823 1824 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL)) 1825 return UINT_MAX; 1826 1827 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num); 1828 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM) 1829 return bd_num; 1830 1831 skb_walk_frags(skb, frag_skb) { 1832 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num, 1833 bd_num, recursion_level + 1); 1834 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1835 return bd_num; 1836 } 1837 1838 return bd_num; 1839 } 1840 1841 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb) 1842 { 1843 if (!skb->encapsulation) 1844 return skb_tcp_all_headers(skb); 1845 1846 return skb_inner_tcp_all_headers(skb); 1847 } 1848 1849 /* HW need every continuous max_non_tso_bd_num buffer data to be larger 1850 * than MSS, we simplify it by ensuring skb_headlen + the first continuous 1851 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss, 1852 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger 1853 * than MSS except the last max_non_tso_bd_num - 1 frags. 1854 */ 1855 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size, 1856 unsigned int bd_num, u8 max_non_tso_bd_num) 1857 { 1858 unsigned int tot_len = 0; 1859 int i; 1860 1861 for (i = 0; i < max_non_tso_bd_num - 1U; i++) 1862 tot_len += bd_size[i]; 1863 1864 /* ensure the first max_non_tso_bd_num frags is greater than 1865 * mss + header 1866 */ 1867 if (tot_len + bd_size[max_non_tso_bd_num - 1U] < 1868 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb)) 1869 return true; 1870 1871 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater 1872 * than mss except the last one. 1873 */ 1874 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) { 1875 tot_len -= bd_size[i]; 1876 tot_len += bd_size[i + max_non_tso_bd_num - 1U]; 1877 1878 if (tot_len < skb_shinfo(skb)->gso_size) 1879 return true; 1880 } 1881 1882 return false; 1883 } 1884 1885 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size) 1886 { 1887 int i; 1888 1889 for (i = 0; i < MAX_SKB_FRAGS; i++) 1890 size[i] = skb_frag_size(&shinfo->frags[i]); 1891 } 1892 1893 static int hns3_skb_linearize(struct hns3_enet_ring *ring, 1894 struct sk_buff *skb, 1895 unsigned int bd_num) 1896 { 1897 /* 'bd_num == UINT_MAX' means the skb' fraglist has a 1898 * recursion level of over HNS3_MAX_RECURSION_LEVEL. 1899 */ 1900 if (bd_num == UINT_MAX) { 1901 hns3_ring_stats_update(ring, over_max_recursion); 1902 return -ENOMEM; 1903 } 1904 1905 /* The skb->len has exceeded the hw limitation, linearization 1906 * will not help. 1907 */ 1908 if (skb->len > HNS3_MAX_TSO_SIZE || 1909 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)) { 1910 hns3_ring_stats_update(ring, hw_limitation); 1911 return -ENOMEM; 1912 } 1913 1914 if (__skb_linearize(skb)) { 1915 hns3_ring_stats_update(ring, sw_err_cnt); 1916 return -ENOMEM; 1917 } 1918 1919 return 0; 1920 } 1921 1922 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring, 1923 struct net_device *netdev, 1924 struct sk_buff *skb) 1925 { 1926 struct hns3_nic_priv *priv = netdev_priv(netdev); 1927 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num; 1928 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U]; 1929 unsigned int bd_num; 1930 1931 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0); 1932 if (unlikely(bd_num > max_non_tso_bd_num)) { 1933 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) && 1934 !hns3_skb_need_linearized(skb, bd_size, bd_num, 1935 max_non_tso_bd_num)) { 1936 trace_hns3_over_max_bd(skb); 1937 goto out; 1938 } 1939 1940 if (hns3_skb_linearize(ring, skb, bd_num)) 1941 return -ENOMEM; 1942 1943 bd_num = hns3_tx_bd_count(skb->len); 1944 1945 hns3_ring_stats_update(ring, tx_copy); 1946 } 1947 1948 out: 1949 if (likely(ring_space(ring) >= bd_num)) 1950 return bd_num; 1951 1952 netif_stop_subqueue(netdev, ring->queue_index); 1953 smp_mb(); /* Memory barrier before checking ring_space */ 1954 1955 /* Start queue in case hns3_clean_tx_ring has just made room 1956 * available and has not seen the queue stopped state performed 1957 * by netif_stop_subqueue above. 1958 */ 1959 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) && 1960 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 1961 netif_start_subqueue(netdev, ring->queue_index); 1962 return bd_num; 1963 } 1964 1965 hns3_ring_stats_update(ring, tx_busy); 1966 1967 return -EBUSY; 1968 } 1969 1970 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1971 { 1972 struct device *dev = ring_to_dev(ring); 1973 unsigned int i; 1974 1975 for (i = 0; i < ring->desc_num; i++) { 1976 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1977 struct hns3_desc_cb *desc_cb; 1978 1979 memset(desc, 0, sizeof(*desc)); 1980 1981 /* check if this is where we started */ 1982 if (ring->next_to_use == next_to_use_orig) 1983 break; 1984 1985 /* rollback one */ 1986 ring_ptr_move_bw(ring, next_to_use); 1987 1988 desc_cb = &ring->desc_cb[ring->next_to_use]; 1989 1990 if (!desc_cb->dma) 1991 continue; 1992 1993 /* unmap the descriptor dma address */ 1994 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB)) 1995 dma_unmap_single(dev, desc_cb->dma, desc_cb->length, 1996 DMA_TO_DEVICE); 1997 else if (desc_cb->type & 1998 (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) 1999 hns3_tx_spare_rollback(ring, desc_cb->length); 2000 else if (desc_cb->length) 2001 dma_unmap_page(dev, desc_cb->dma, desc_cb->length, 2002 DMA_TO_DEVICE); 2003 2004 desc_cb->length = 0; 2005 desc_cb->dma = 0; 2006 desc_cb->type = DESC_TYPE_UNKNOWN; 2007 } 2008 } 2009 2010 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring, 2011 struct sk_buff *skb, unsigned int type) 2012 { 2013 struct sk_buff *frag_skb; 2014 int i, ret, bd_num = 0; 2015 2016 ret = hns3_map_and_fill_desc(ring, skb, type); 2017 if (unlikely(ret < 0)) 2018 return ret; 2019 2020 bd_num += ret; 2021 2022 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2023 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2024 2025 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE); 2026 if (unlikely(ret < 0)) 2027 return ret; 2028 2029 bd_num += ret; 2030 } 2031 2032 skb_walk_frags(skb, frag_skb) { 2033 ret = hns3_fill_skb_to_desc(ring, frag_skb, 2034 DESC_TYPE_FRAGLIST_SKB); 2035 if (unlikely(ret < 0)) 2036 return ret; 2037 2038 bd_num += ret; 2039 } 2040 2041 return bd_num; 2042 } 2043 2044 static void hns3_tx_push_bd(struct hns3_enet_ring *ring, int num) 2045 { 2046 #define HNS3_BYTES_PER_64BIT 8 2047 2048 struct hns3_desc desc[HNS3_MAX_PUSH_BD_NUM] = {}; 2049 int offset = 0; 2050 2051 /* make sure everything is visible to device before 2052 * excuting tx push or updating doorbell 2053 */ 2054 dma_wmb(); 2055 2056 do { 2057 int idx = (ring->next_to_use - num + ring->desc_num) % 2058 ring->desc_num; 2059 2060 u64_stats_update_begin(&ring->syncp); 2061 ring->stats.tx_push++; 2062 u64_stats_update_end(&ring->syncp); 2063 memcpy(&desc[offset], &ring->desc[idx], 2064 sizeof(struct hns3_desc)); 2065 offset++; 2066 } while (--num); 2067 2068 __iowrite64_copy(ring->tqp->mem_base, desc, 2069 (sizeof(struct hns3_desc) * HNS3_MAX_PUSH_BD_NUM) / 2070 HNS3_BYTES_PER_64BIT); 2071 } 2072 2073 static void hns3_tx_mem_doorbell(struct hns3_enet_ring *ring) 2074 { 2075 #define HNS3_MEM_DOORBELL_OFFSET 64 2076 2077 __le64 bd_num = cpu_to_le64((u64)ring->pending_buf); 2078 2079 /* make sure everything is visible to device before 2080 * excuting tx push or updating doorbell 2081 */ 2082 dma_wmb(); 2083 2084 __iowrite64_copy(ring->tqp->mem_base + HNS3_MEM_DOORBELL_OFFSET, 2085 &bd_num, 1); 2086 u64_stats_update_begin(&ring->syncp); 2087 ring->stats.tx_mem_doorbell += ring->pending_buf; 2088 u64_stats_update_end(&ring->syncp); 2089 } 2090 2091 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num, 2092 bool doorbell) 2093 { 2094 struct net_device *netdev = ring_to_netdev(ring); 2095 struct hns3_nic_priv *priv = netdev_priv(netdev); 2096 2097 /* when tx push is enabled, the packet whose number of BD below 2098 * HNS3_MAX_PUSH_BD_NUM can be pushed directly. 2099 */ 2100 if (test_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state) && num && 2101 !ring->pending_buf && num <= HNS3_MAX_PUSH_BD_NUM && doorbell) { 2102 /* This smp_store_release() pairs with smp_load_aquire() in 2103 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit 2104 * is updated. 2105 */ 2106 smp_store_release(&ring->last_to_use, ring->next_to_use); 2107 hns3_tx_push_bd(ring, num); 2108 return; 2109 } 2110 2111 ring->pending_buf += num; 2112 2113 if (!doorbell) { 2114 hns3_ring_stats_update(ring, tx_more); 2115 return; 2116 } 2117 2118 /* This smp_store_release() pairs with smp_load_aquire() in 2119 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit is updated. 2120 */ 2121 smp_store_release(&ring->last_to_use, ring->next_to_use); 2122 2123 if (ring->tqp->mem_base) 2124 hns3_tx_mem_doorbell(ring); 2125 else 2126 writel(ring->pending_buf, 2127 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG); 2128 2129 ring->pending_buf = 0; 2130 } 2131 2132 static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb, 2133 struct hns3_desc *desc) 2134 { 2135 struct hnae3_handle *h = hns3_get_handle(netdev); 2136 2137 if (!(h->ae_algo->ops->set_tx_hwts_info && 2138 h->ae_algo->ops->set_tx_hwts_info(h, skb))) 2139 return; 2140 2141 desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B)); 2142 } 2143 2144 static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring, 2145 struct sk_buff *skb) 2146 { 2147 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 2148 unsigned int type = DESC_TYPE_BOUNCE_HEAD; 2149 unsigned int size = skb_headlen(skb); 2150 dma_addr_t dma; 2151 int bd_num = 0; 2152 u32 cb_len; 2153 void *buf; 2154 int ret; 2155 2156 if (skb->len <= ring->tx_copybreak) { 2157 size = skb->len; 2158 type = DESC_TYPE_BOUNCE_ALL; 2159 } 2160 2161 /* hns3_can_use_tx_bounce() is called to ensure the below 2162 * function can always return the tx buffer. 2163 */ 2164 buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len); 2165 2166 ret = skb_copy_bits(skb, 0, buf, size); 2167 if (unlikely(ret < 0)) { 2168 hns3_tx_spare_rollback(ring, cb_len); 2169 hns3_ring_stats_update(ring, copy_bits_err); 2170 return ret; 2171 } 2172 2173 desc_cb->priv = skb; 2174 desc_cb->length = cb_len; 2175 desc_cb->dma = dma; 2176 desc_cb->type = type; 2177 2178 bd_num += hns3_fill_desc(ring, dma, size); 2179 2180 if (type == DESC_TYPE_BOUNCE_HEAD) { 2181 ret = hns3_fill_skb_to_desc(ring, skb, 2182 DESC_TYPE_BOUNCE_HEAD); 2183 if (unlikely(ret < 0)) 2184 return ret; 2185 2186 bd_num += ret; 2187 } 2188 2189 dma_sync_single_for_device(ring_to_dev(ring), dma, size, 2190 DMA_TO_DEVICE); 2191 2192 hns3_ring_stats_update(ring, tx_bounce); 2193 2194 return bd_num; 2195 } 2196 2197 static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring, 2198 struct sk_buff *skb) 2199 { 2200 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 2201 u32 nfrag = skb_shinfo(skb)->nr_frags + 1; 2202 struct sg_table *sgt; 2203 int i, bd_num = 0; 2204 dma_addr_t dma; 2205 u32 cb_len; 2206 int nents; 2207 2208 if (skb_has_frag_list(skb)) 2209 nfrag = HNS3_MAX_TSO_BD_NUM; 2210 2211 /* hns3_can_use_tx_sgl() is called to ensure the below 2212 * function can always return the tx buffer. 2213 */ 2214 sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag), 2215 &dma, &cb_len); 2216 2217 /* scatterlist follows by the sg table */ 2218 sgt->sgl = (struct scatterlist *)(sgt + 1); 2219 sg_init_table(sgt->sgl, nfrag); 2220 nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len); 2221 if (unlikely(nents < 0)) { 2222 hns3_tx_spare_rollback(ring, cb_len); 2223 hns3_ring_stats_update(ring, skb2sgl_err); 2224 return -ENOMEM; 2225 } 2226 2227 sgt->orig_nents = nents; 2228 sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents, 2229 DMA_TO_DEVICE); 2230 if (unlikely(!sgt->nents)) { 2231 hns3_tx_spare_rollback(ring, cb_len); 2232 hns3_ring_stats_update(ring, map_sg_err); 2233 return -ENOMEM; 2234 } 2235 2236 desc_cb->priv = skb; 2237 desc_cb->length = cb_len; 2238 desc_cb->dma = dma; 2239 desc_cb->type = DESC_TYPE_SGL_SKB; 2240 2241 for (i = 0; i < sgt->nents; i++) 2242 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i), 2243 sg_dma_len(sgt->sgl + i)); 2244 hns3_ring_stats_update(ring, tx_sgl); 2245 2246 return bd_num; 2247 } 2248 2249 static int hns3_handle_desc_filling(struct hns3_enet_ring *ring, 2250 struct sk_buff *skb) 2251 { 2252 u32 space; 2253 2254 if (!ring->tx_spare) 2255 goto out; 2256 2257 space = hns3_tx_spare_space(ring); 2258 2259 if (hns3_can_use_tx_sgl(ring, skb, space)) 2260 return hns3_handle_tx_sgl(ring, skb); 2261 2262 if (hns3_can_use_tx_bounce(ring, skb, space)) 2263 return hns3_handle_tx_bounce(ring, skb); 2264 2265 out: 2266 return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB); 2267 } 2268 2269 static int hns3_handle_skb_desc(struct hns3_enet_ring *ring, 2270 struct sk_buff *skb, 2271 struct hns3_desc_cb *desc_cb, 2272 int next_to_use_head) 2273 { 2274 int ret; 2275 2276 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use], 2277 desc_cb); 2278 if (unlikely(ret < 0)) 2279 goto fill_err; 2280 2281 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is 2282 * zero, which is unlikely, and 'ret > 0' means how many tx desc 2283 * need to be notified to the hw. 2284 */ 2285 ret = hns3_handle_desc_filling(ring, skb); 2286 if (likely(ret > 0)) 2287 return ret; 2288 2289 fill_err: 2290 hns3_clear_desc(ring, next_to_use_head); 2291 return ret; 2292 } 2293 2294 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 2295 { 2296 struct hns3_nic_priv *priv = netdev_priv(netdev); 2297 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping]; 2298 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 2299 struct netdev_queue *dev_queue; 2300 int pre_ntu, ret; 2301 bool doorbell; 2302 2303 /* Hardware can only handle short frames above 32 bytes */ 2304 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) { 2305 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 2306 2307 hns3_ring_stats_update(ring, sw_err_cnt); 2308 2309 return NETDEV_TX_OK; 2310 } 2311 2312 /* Prefetch the data used later */ 2313 prefetch(skb->data); 2314 2315 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb); 2316 if (unlikely(ret <= 0)) { 2317 if (ret == -EBUSY) { 2318 hns3_tx_doorbell(ring, 0, true); 2319 return NETDEV_TX_BUSY; 2320 } 2321 2322 hns3_rl_err(netdev, "xmit error: %d!\n", ret); 2323 goto out_err_tx_ok; 2324 } 2325 2326 ret = hns3_handle_skb_desc(ring, skb, desc_cb, ring->next_to_use); 2327 if (unlikely(ret <= 0)) 2328 goto out_err_tx_ok; 2329 2330 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) : 2331 (ring->desc_num - 1); 2332 2333 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 2334 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]); 2335 2336 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |= 2337 cpu_to_le16(BIT(HNS3_TXD_FE_B)); 2338 trace_hns3_tx_desc(ring, pre_ntu); 2339 2340 skb_tx_timestamp(skb); 2341 2342 /* Complete translate all packets */ 2343 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index); 2344 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes, 2345 netdev_xmit_more()); 2346 hns3_tx_doorbell(ring, ret, doorbell); 2347 2348 return NETDEV_TX_OK; 2349 2350 out_err_tx_ok: 2351 dev_kfree_skb_any(skb); 2352 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 2353 return NETDEV_TX_OK; 2354 } 2355 2356 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 2357 { 2358 char format_mac_addr_perm[HNAE3_FORMAT_MAC_ADDR_LEN]; 2359 char format_mac_addr_sa[HNAE3_FORMAT_MAC_ADDR_LEN]; 2360 struct hnae3_handle *h = hns3_get_handle(netdev); 2361 struct sockaddr *mac_addr = p; 2362 int ret; 2363 2364 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 2365 return -EADDRNOTAVAIL; 2366 2367 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 2368 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data); 2369 netdev_info(netdev, "already using mac address %s\n", 2370 format_mac_addr_sa); 2371 return 0; 2372 } 2373 2374 /* For VF device, if there is a perm_addr, then the user will not 2375 * be allowed to change the address. 2376 */ 2377 if (!hns3_is_phys_func(h->pdev) && 2378 !is_zero_ether_addr(netdev->perm_addr)) { 2379 hnae3_format_mac_addr(format_mac_addr_perm, netdev->perm_addr); 2380 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data); 2381 netdev_err(netdev, "has permanent MAC %s, user MAC %s not allow\n", 2382 format_mac_addr_perm, format_mac_addr_sa); 2383 return -EPERM; 2384 } 2385 2386 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 2387 if (ret) { 2388 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 2389 return ret; 2390 } 2391 2392 eth_hw_addr_set(netdev, mac_addr->sa_data); 2393 2394 return 0; 2395 } 2396 2397 static int hns3_nic_do_ioctl(struct net_device *netdev, 2398 struct ifreq *ifr, int cmd) 2399 { 2400 struct hnae3_handle *h = hns3_get_handle(netdev); 2401 2402 if (!netif_running(netdev)) 2403 return -EINVAL; 2404 2405 if (!h->ae_algo->ops->do_ioctl) 2406 return -EOPNOTSUPP; 2407 2408 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 2409 } 2410 2411 static int hns3_nic_set_features(struct net_device *netdev, 2412 netdev_features_t features) 2413 { 2414 netdev_features_t changed = netdev->features ^ features; 2415 struct hns3_nic_priv *priv = netdev_priv(netdev); 2416 struct hnae3_handle *h = priv->ae_handle; 2417 bool enable; 2418 int ret; 2419 2420 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 2421 enable = !!(features & NETIF_F_GRO_HW); 2422 ret = h->ae_algo->ops->set_gro_en(h, enable); 2423 if (ret) 2424 return ret; 2425 } 2426 2427 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 2428 h->ae_algo->ops->enable_hw_strip_rxvtag) { 2429 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 2430 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 2431 if (ret) 2432 return ret; 2433 } 2434 2435 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 2436 enable = !!(features & NETIF_F_NTUPLE); 2437 h->ae_algo->ops->enable_fd(h, enable); 2438 } 2439 2440 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) && 2441 h->ae_algo->ops->cls_flower_active(h)) { 2442 netdev_err(netdev, 2443 "there are offloaded TC filters active, cannot disable HW TC offload"); 2444 return -EINVAL; 2445 } 2446 2447 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 2448 h->ae_algo->ops->enable_vlan_filter) { 2449 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER); 2450 ret = h->ae_algo->ops->enable_vlan_filter(h, enable); 2451 if (ret) 2452 return ret; 2453 } 2454 2455 return 0; 2456 } 2457 2458 static netdev_features_t hns3_features_check(struct sk_buff *skb, 2459 struct net_device *dev, 2460 netdev_features_t features) 2461 { 2462 #define HNS3_MAX_HDR_LEN 480U 2463 #define HNS3_MAX_L4_HDR_LEN 60U 2464 2465 size_t len; 2466 2467 if (skb->ip_summed != CHECKSUM_PARTIAL) 2468 return features; 2469 2470 if (skb->encapsulation) 2471 len = skb_inner_transport_offset(skb); 2472 else 2473 len = skb_transport_offset(skb); 2474 2475 /* Assume L4 is 60 byte as TCP is the only protocol with a 2476 * a flexible value, and it's max len is 60 bytes. 2477 */ 2478 len += HNS3_MAX_L4_HDR_LEN; 2479 2480 /* Hardware only supports checksum on the skb with a max header 2481 * len of 480 bytes. 2482 */ 2483 if (len > HNS3_MAX_HDR_LEN) 2484 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2485 2486 return features; 2487 } 2488 2489 static void hns3_fetch_stats(struct rtnl_link_stats64 *stats, 2490 struct hns3_enet_ring *ring, bool is_tx) 2491 { 2492 unsigned int start; 2493 2494 do { 2495 start = u64_stats_fetch_begin(&ring->syncp); 2496 if (is_tx) { 2497 stats->tx_bytes += ring->stats.tx_bytes; 2498 stats->tx_packets += ring->stats.tx_pkts; 2499 stats->tx_dropped += ring->stats.sw_err_cnt; 2500 stats->tx_dropped += ring->stats.tx_vlan_err; 2501 stats->tx_dropped += ring->stats.tx_l4_proto_err; 2502 stats->tx_dropped += ring->stats.tx_l2l3l4_err; 2503 stats->tx_dropped += ring->stats.tx_tso_err; 2504 stats->tx_dropped += ring->stats.over_max_recursion; 2505 stats->tx_dropped += ring->stats.hw_limitation; 2506 stats->tx_dropped += ring->stats.copy_bits_err; 2507 stats->tx_dropped += ring->stats.skb2sgl_err; 2508 stats->tx_dropped += ring->stats.map_sg_err; 2509 stats->tx_errors += ring->stats.sw_err_cnt; 2510 stats->tx_errors += ring->stats.tx_vlan_err; 2511 stats->tx_errors += ring->stats.tx_l4_proto_err; 2512 stats->tx_errors += ring->stats.tx_l2l3l4_err; 2513 stats->tx_errors += ring->stats.tx_tso_err; 2514 stats->tx_errors += ring->stats.over_max_recursion; 2515 stats->tx_errors += ring->stats.hw_limitation; 2516 stats->tx_errors += ring->stats.copy_bits_err; 2517 stats->tx_errors += ring->stats.skb2sgl_err; 2518 stats->tx_errors += ring->stats.map_sg_err; 2519 } else { 2520 stats->rx_bytes += ring->stats.rx_bytes; 2521 stats->rx_packets += ring->stats.rx_pkts; 2522 stats->rx_dropped += ring->stats.l2_err; 2523 stats->rx_errors += ring->stats.l2_err; 2524 stats->rx_errors += ring->stats.l3l4_csum_err; 2525 stats->rx_crc_errors += ring->stats.l2_err; 2526 stats->multicast += ring->stats.rx_multicast; 2527 stats->rx_length_errors += ring->stats.err_pkt_len; 2528 } 2529 } while (u64_stats_fetch_retry(&ring->syncp, start)); 2530 } 2531 2532 static void hns3_nic_get_stats64(struct net_device *netdev, 2533 struct rtnl_link_stats64 *stats) 2534 { 2535 struct hns3_nic_priv *priv = netdev_priv(netdev); 2536 int queue_num = priv->ae_handle->kinfo.num_tqps; 2537 struct hnae3_handle *handle = priv->ae_handle; 2538 struct rtnl_link_stats64 ring_total_stats; 2539 struct hns3_enet_ring *ring; 2540 unsigned int idx; 2541 2542 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 2543 return; 2544 2545 handle->ae_algo->ops->update_stats(handle); 2546 2547 memset(&ring_total_stats, 0, sizeof(ring_total_stats)); 2548 for (idx = 0; idx < queue_num; idx++) { 2549 /* fetch the tx stats */ 2550 ring = &priv->ring[idx]; 2551 hns3_fetch_stats(&ring_total_stats, ring, true); 2552 2553 /* fetch the rx stats */ 2554 ring = &priv->ring[idx + queue_num]; 2555 hns3_fetch_stats(&ring_total_stats, ring, false); 2556 } 2557 2558 stats->tx_bytes = ring_total_stats.tx_bytes; 2559 stats->tx_packets = ring_total_stats.tx_packets; 2560 stats->rx_bytes = ring_total_stats.rx_bytes; 2561 stats->rx_packets = ring_total_stats.rx_packets; 2562 2563 stats->rx_errors = ring_total_stats.rx_errors; 2564 stats->multicast = ring_total_stats.multicast; 2565 stats->rx_length_errors = ring_total_stats.rx_length_errors; 2566 stats->rx_crc_errors = ring_total_stats.rx_crc_errors; 2567 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 2568 2569 stats->tx_errors = ring_total_stats.tx_errors; 2570 stats->rx_dropped = ring_total_stats.rx_dropped; 2571 stats->tx_dropped = ring_total_stats.tx_dropped; 2572 stats->collisions = netdev->stats.collisions; 2573 stats->rx_over_errors = netdev->stats.rx_over_errors; 2574 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 2575 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 2576 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 2577 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 2578 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 2579 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 2580 stats->tx_window_errors = netdev->stats.tx_window_errors; 2581 stats->rx_compressed = netdev->stats.rx_compressed; 2582 stats->tx_compressed = netdev->stats.tx_compressed; 2583 } 2584 2585 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 2586 { 2587 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 2588 struct hnae3_knic_private_info *kinfo; 2589 u8 tc = mqprio_qopt->qopt.num_tc; 2590 u16 mode = mqprio_qopt->mode; 2591 u8 hw = mqprio_qopt->qopt.hw; 2592 struct hnae3_handle *h; 2593 2594 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 2595 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 2596 return -EOPNOTSUPP; 2597 2598 if (tc > HNAE3_MAX_TC) 2599 return -EINVAL; 2600 2601 if (!netdev) 2602 return -EINVAL; 2603 2604 h = hns3_get_handle(netdev); 2605 kinfo = &h->kinfo; 2606 2607 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc); 2608 2609 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 2610 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP; 2611 } 2612 2613 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv, 2614 struct flow_cls_offload *flow) 2615 { 2616 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid); 2617 struct hnae3_handle *h = hns3_get_handle(priv->netdev); 2618 2619 switch (flow->command) { 2620 case FLOW_CLS_REPLACE: 2621 if (h->ae_algo->ops->add_cls_flower) 2622 return h->ae_algo->ops->add_cls_flower(h, flow, tc); 2623 break; 2624 case FLOW_CLS_DESTROY: 2625 if (h->ae_algo->ops->del_cls_flower) 2626 return h->ae_algo->ops->del_cls_flower(h, flow); 2627 break; 2628 default: 2629 break; 2630 } 2631 2632 return -EOPNOTSUPP; 2633 } 2634 2635 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2636 void *cb_priv) 2637 { 2638 struct hns3_nic_priv *priv = cb_priv; 2639 2640 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data)) 2641 return -EOPNOTSUPP; 2642 2643 switch (type) { 2644 case TC_SETUP_CLSFLOWER: 2645 return hns3_setup_tc_cls_flower(priv, type_data); 2646 default: 2647 return -EOPNOTSUPP; 2648 } 2649 } 2650 2651 static LIST_HEAD(hns3_block_cb_list); 2652 2653 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 2654 void *type_data) 2655 { 2656 struct hns3_nic_priv *priv = netdev_priv(dev); 2657 int ret; 2658 2659 switch (type) { 2660 case TC_SETUP_QDISC_MQPRIO: 2661 ret = hns3_setup_tc(dev, type_data); 2662 break; 2663 case TC_SETUP_BLOCK: 2664 ret = flow_block_cb_setup_simple(type_data, 2665 &hns3_block_cb_list, 2666 hns3_setup_tc_block_cb, 2667 priv, priv, true); 2668 break; 2669 default: 2670 return -EOPNOTSUPP; 2671 } 2672 2673 return ret; 2674 } 2675 2676 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 2677 __be16 proto, u16 vid) 2678 { 2679 struct hnae3_handle *h = hns3_get_handle(netdev); 2680 int ret = -EIO; 2681 2682 if (h->ae_algo->ops->set_vlan_filter) 2683 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 2684 2685 return ret; 2686 } 2687 2688 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 2689 __be16 proto, u16 vid) 2690 { 2691 struct hnae3_handle *h = hns3_get_handle(netdev); 2692 int ret = -EIO; 2693 2694 if (h->ae_algo->ops->set_vlan_filter) 2695 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 2696 2697 return ret; 2698 } 2699 2700 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2701 u8 qos, __be16 vlan_proto) 2702 { 2703 struct hnae3_handle *h = hns3_get_handle(netdev); 2704 int ret = -EIO; 2705 2706 netif_dbg(h, drv, netdev, 2707 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n", 2708 vf, vlan, qos, ntohs(vlan_proto)); 2709 2710 if (h->ae_algo->ops->set_vf_vlan_filter) 2711 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 2712 qos, vlan_proto); 2713 2714 return ret; 2715 } 2716 2717 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable) 2718 { 2719 struct hnae3_handle *handle = hns3_get_handle(netdev); 2720 2721 if (hns3_nic_resetting(netdev)) 2722 return -EBUSY; 2723 2724 if (!handle->ae_algo->ops->set_vf_spoofchk) 2725 return -EOPNOTSUPP; 2726 2727 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable); 2728 } 2729 2730 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable) 2731 { 2732 struct hnae3_handle *handle = hns3_get_handle(netdev); 2733 2734 if (!handle->ae_algo->ops->set_vf_trust) 2735 return -EOPNOTSUPP; 2736 2737 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable); 2738 } 2739 2740 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 2741 { 2742 struct hnae3_handle *h = hns3_get_handle(netdev); 2743 int ret; 2744 2745 if (hns3_nic_resetting(netdev)) 2746 return -EBUSY; 2747 2748 if (!h->ae_algo->ops->set_mtu) 2749 return -EOPNOTSUPP; 2750 2751 netif_dbg(h, drv, netdev, 2752 "change mtu from %u to %d\n", netdev->mtu, new_mtu); 2753 2754 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 2755 if (ret) 2756 netdev_err(netdev, "failed to change MTU in hardware %d\n", 2757 ret); 2758 else 2759 WRITE_ONCE(netdev->mtu, new_mtu); 2760 2761 return ret; 2762 } 2763 2764 static int hns3_get_timeout_queue(struct net_device *ndev) 2765 { 2766 int i; 2767 2768 /* Find the stopped queue the same way the stack does */ 2769 for (i = 0; i < ndev->num_tx_queues; i++) { 2770 struct netdev_queue *q; 2771 unsigned long trans_start; 2772 2773 q = netdev_get_tx_queue(ndev, i); 2774 trans_start = READ_ONCE(q->trans_start); 2775 if (netif_xmit_stopped(q) && 2776 time_after(jiffies, 2777 (trans_start + ndev->watchdog_timeo))) { 2778 #ifdef CONFIG_BQL 2779 struct dql *dql = &q->dql; 2780 2781 netdev_info(ndev, "DQL info last_cnt: %u, queued: %u, adj_limit: %u, completed: %u\n", 2782 dql->last_obj_cnt, dql->num_queued, 2783 dql->adj_limit, dql->num_completed); 2784 #endif 2785 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n", 2786 q->state, 2787 jiffies_to_msecs(jiffies - trans_start)); 2788 break; 2789 } 2790 } 2791 2792 return i; 2793 } 2794 2795 static void hns3_dump_queue_stats(struct net_device *ndev, 2796 struct hns3_enet_ring *tx_ring, 2797 int timeout_queue) 2798 { 2799 struct napi_struct *napi = &tx_ring->tqp_vector->napi; 2800 struct hns3_nic_priv *priv = netdev_priv(ndev); 2801 2802 netdev_info(ndev, 2803 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n", 2804 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use, 2805 tx_ring->next_to_clean, napi->state); 2806 2807 netdev_info(ndev, 2808 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n", 2809 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes, 2810 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf); 2811 2812 netdev_info(ndev, 2813 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n", 2814 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more, 2815 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy); 2816 2817 netdev_info(ndev, "tx_push: %llu, tx_mem_doorbell: %llu\n", 2818 tx_ring->stats.tx_push, tx_ring->stats.tx_mem_doorbell); 2819 } 2820 2821 static void hns3_dump_queue_reg(struct net_device *ndev, 2822 struct hns3_enet_ring *tx_ring) 2823 { 2824 netdev_info(ndev, 2825 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n", 2826 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_NUM_REG), 2827 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_HEAD_REG), 2828 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TAIL_REG), 2829 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_ERR_REG), 2830 readl(tx_ring->tqp_vector->mask_addr)); 2831 netdev_info(ndev, 2832 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n", 2833 hns3_tqp_read_reg(tx_ring, HNS3_RING_EN_REG), 2834 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TC_REG), 2835 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_FBDNUM_REG), 2836 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_OFFSET_REG), 2837 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_EBDNUM_REG), 2838 hns3_tqp_read_reg(tx_ring, 2839 HNS3_RING_TX_RING_EBD_OFFSET_REG)); 2840 } 2841 2842 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 2843 { 2844 struct hns3_nic_priv *priv = netdev_priv(ndev); 2845 struct hnae3_handle *h = hns3_get_handle(ndev); 2846 struct hns3_enet_ring *tx_ring; 2847 int timeout_queue; 2848 2849 timeout_queue = hns3_get_timeout_queue(ndev); 2850 if (timeout_queue >= ndev->num_tx_queues) { 2851 netdev_info(ndev, 2852 "no netdev TX timeout queue found, timeout count: %llu\n", 2853 priv->tx_timeout_count); 2854 return false; 2855 } 2856 2857 priv->tx_timeout_count++; 2858 2859 tx_ring = &priv->ring[timeout_queue]; 2860 hns3_dump_queue_stats(ndev, tx_ring, timeout_queue); 2861 2862 /* When mac received many pause frames continuous, it's unable to send 2863 * packets, which may cause tx timeout 2864 */ 2865 if (h->ae_algo->ops->get_mac_stats) { 2866 struct hns3_mac_stats mac_stats; 2867 2868 h->ae_algo->ops->get_mac_stats(h, &mac_stats); 2869 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n", 2870 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt); 2871 } 2872 2873 hns3_dump_queue_reg(ndev, tx_ring); 2874 2875 return true; 2876 } 2877 2878 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue) 2879 { 2880 struct hns3_nic_priv *priv = netdev_priv(ndev); 2881 struct hnae3_handle *h = priv->ae_handle; 2882 2883 if (!hns3_get_tx_timeo_queue_info(ndev)) 2884 return; 2885 2886 /* request the reset, and let the hclge to determine 2887 * which reset level should be done 2888 */ 2889 if (h->ae_algo->ops->reset_event) 2890 h->ae_algo->ops->reset_event(h->pdev, h); 2891 } 2892 2893 #ifdef CONFIG_RFS_ACCEL 2894 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 2895 u16 rxq_index, u32 flow_id) 2896 { 2897 struct hnae3_handle *h = hns3_get_handle(dev); 2898 struct flow_keys fkeys; 2899 2900 if (!h->ae_algo->ops->add_arfs_entry) 2901 return -EOPNOTSUPP; 2902 2903 if (skb->encapsulation) 2904 return -EPROTONOSUPPORT; 2905 2906 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0)) 2907 return -EPROTONOSUPPORT; 2908 2909 if ((fkeys.basic.n_proto != htons(ETH_P_IP) && 2910 fkeys.basic.n_proto != htons(ETH_P_IPV6)) || 2911 (fkeys.basic.ip_proto != IPPROTO_TCP && 2912 fkeys.basic.ip_proto != IPPROTO_UDP)) 2913 return -EPROTONOSUPPORT; 2914 2915 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys); 2916 } 2917 #endif 2918 2919 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf, 2920 struct ifla_vf_info *ivf) 2921 { 2922 struct hnae3_handle *h = hns3_get_handle(ndev); 2923 2924 if (!h->ae_algo->ops->get_vf_config) 2925 return -EOPNOTSUPP; 2926 2927 return h->ae_algo->ops->get_vf_config(h, vf, ivf); 2928 } 2929 2930 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf, 2931 int link_state) 2932 { 2933 struct hnae3_handle *h = hns3_get_handle(ndev); 2934 2935 if (!h->ae_algo->ops->set_vf_link_state) 2936 return -EOPNOTSUPP; 2937 2938 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state); 2939 } 2940 2941 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf, 2942 int min_tx_rate, int max_tx_rate) 2943 { 2944 struct hnae3_handle *h = hns3_get_handle(ndev); 2945 2946 if (!h->ae_algo->ops->set_vf_rate) 2947 return -EOPNOTSUPP; 2948 2949 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate, 2950 false); 2951 } 2952 2953 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) 2954 { 2955 struct hnae3_handle *h = hns3_get_handle(netdev); 2956 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 2957 2958 if (!h->ae_algo->ops->set_vf_mac) 2959 return -EOPNOTSUPP; 2960 2961 if (is_multicast_ether_addr(mac)) { 2962 hnae3_format_mac_addr(format_mac_addr, mac); 2963 netdev_err(netdev, 2964 "Invalid MAC:%s specified. Could not set MAC\n", 2965 format_mac_addr); 2966 return -EINVAL; 2967 } 2968 2969 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac); 2970 } 2971 2972 #define HNS3_INVALID_DSCP 0xff 2973 #define HNS3_DSCP_SHIFT 2 2974 2975 static u8 hns3_get_skb_dscp(struct sk_buff *skb) 2976 { 2977 __be16 protocol = skb->protocol; 2978 u8 dscp = HNS3_INVALID_DSCP; 2979 2980 if (protocol == htons(ETH_P_8021Q)) 2981 protocol = vlan_get_protocol(skb); 2982 2983 if (protocol == htons(ETH_P_IP)) 2984 dscp = ipv4_get_dsfield(ip_hdr(skb)) >> HNS3_DSCP_SHIFT; 2985 else if (protocol == htons(ETH_P_IPV6)) 2986 dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> HNS3_DSCP_SHIFT; 2987 2988 return dscp; 2989 } 2990 2991 static u16 hns3_nic_select_queue(struct net_device *netdev, 2992 struct sk_buff *skb, 2993 struct net_device *sb_dev) 2994 { 2995 struct hnae3_handle *h = hns3_get_handle(netdev); 2996 u8 dscp; 2997 2998 if (h->kinfo.tc_map_mode != HNAE3_TC_MAP_MODE_DSCP || 2999 !h->ae_algo->ops->get_dscp_prio) 3000 goto out; 3001 3002 dscp = hns3_get_skb_dscp(skb); 3003 if (unlikely(dscp >= HNAE3_MAX_DSCP)) 3004 goto out; 3005 3006 skb->priority = h->kinfo.dscp_prio[dscp]; 3007 if (skb->priority == HNAE3_PRIO_ID_INVALID) 3008 skb->priority = 0; 3009 3010 out: 3011 return netdev_pick_tx(netdev, skb, sb_dev); 3012 } 3013 3014 static const struct net_device_ops hns3_nic_netdev_ops = { 3015 .ndo_open = hns3_nic_net_open, 3016 .ndo_stop = hns3_nic_net_stop, 3017 .ndo_start_xmit = hns3_nic_net_xmit, 3018 .ndo_tx_timeout = hns3_nic_net_timeout, 3019 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 3020 .ndo_eth_ioctl = hns3_nic_do_ioctl, 3021 .ndo_change_mtu = hns3_nic_change_mtu, 3022 .ndo_set_features = hns3_nic_set_features, 3023 .ndo_features_check = hns3_features_check, 3024 .ndo_get_stats64 = hns3_nic_get_stats64, 3025 .ndo_setup_tc = hns3_nic_setup_tc, 3026 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 3027 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 3028 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 3029 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 3030 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk, 3031 .ndo_set_vf_trust = hns3_set_vf_trust, 3032 #ifdef CONFIG_RFS_ACCEL 3033 .ndo_rx_flow_steer = hns3_rx_flow_steer, 3034 #endif 3035 .ndo_get_vf_config = hns3_nic_get_vf_config, 3036 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state, 3037 .ndo_set_vf_rate = hns3_nic_set_vf_rate, 3038 .ndo_set_vf_mac = hns3_nic_set_vf_mac, 3039 .ndo_select_queue = hns3_nic_select_queue, 3040 }; 3041 3042 bool hns3_is_phys_func(struct pci_dev *pdev) 3043 { 3044 u32 dev_id = pdev->device; 3045 3046 switch (dev_id) { 3047 case HNAE3_DEV_ID_GE: 3048 case HNAE3_DEV_ID_25GE: 3049 case HNAE3_DEV_ID_25GE_RDMA: 3050 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 3051 case HNAE3_DEV_ID_50GE_RDMA: 3052 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 3053 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 3054 case HNAE3_DEV_ID_200G_RDMA: 3055 return true; 3056 case HNAE3_DEV_ID_VF: 3057 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF: 3058 return false; 3059 default: 3060 dev_warn(&pdev->dev, "un-recognized pci device-id %u", 3061 dev_id); 3062 } 3063 3064 return false; 3065 } 3066 3067 static void hns3_disable_sriov(struct pci_dev *pdev) 3068 { 3069 /* If our VFs are assigned we cannot shut down SR-IOV 3070 * without causing issues, so just leave the hardware 3071 * available but disabled 3072 */ 3073 if (pci_vfs_assigned(pdev)) { 3074 dev_warn(&pdev->dev, 3075 "disabling driver while VFs are assigned\n"); 3076 return; 3077 } 3078 3079 pci_disable_sriov(pdev); 3080 } 3081 3082 /* hns3_probe - Device initialization routine 3083 * @pdev: PCI device information struct 3084 * @ent: entry in hns3_pci_tbl 3085 * 3086 * hns3_probe initializes a PF identified by a pci_dev structure. 3087 * The OS initialization, configuring of the PF private structure, 3088 * and a hardware reset occur. 3089 * 3090 * Returns 0 on success, negative on failure 3091 */ 3092 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3093 { 3094 struct hnae3_ae_dev *ae_dev; 3095 int ret; 3096 3097 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL); 3098 if (!ae_dev) 3099 return -ENOMEM; 3100 3101 ae_dev->pdev = pdev; 3102 ae_dev->flag = ent->driver_data; 3103 pci_set_drvdata(pdev, ae_dev); 3104 3105 ret = hnae3_register_ae_dev(ae_dev); 3106 if (ret) 3107 pci_set_drvdata(pdev, NULL); 3108 3109 return ret; 3110 } 3111 3112 /** 3113 * hns3_clean_vf_config 3114 * @pdev: pointer to a pci_dev structure 3115 * @num_vfs: number of VFs allocated 3116 * 3117 * Clean residual vf config after disable sriov 3118 **/ 3119 static void hns3_clean_vf_config(struct pci_dev *pdev, int num_vfs) 3120 { 3121 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3122 3123 if (ae_dev->ops->clean_vf_config) 3124 ae_dev->ops->clean_vf_config(ae_dev, num_vfs); 3125 } 3126 3127 /* hns3_remove - Device removal routine 3128 * @pdev: PCI device information struct 3129 */ 3130 static void hns3_remove(struct pci_dev *pdev) 3131 { 3132 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3133 3134 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 3135 hns3_disable_sriov(pdev); 3136 3137 hnae3_unregister_ae_dev(ae_dev); 3138 pci_set_drvdata(pdev, NULL); 3139 } 3140 3141 /** 3142 * hns3_pci_sriov_configure 3143 * @pdev: pointer to a pci_dev structure 3144 * @num_vfs: number of VFs to allocate 3145 * 3146 * Enable or change the number of VFs. Called when the user updates the number 3147 * of VFs in sysfs. 3148 **/ 3149 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 3150 { 3151 int ret; 3152 3153 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 3154 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 3155 return -EINVAL; 3156 } 3157 3158 if (num_vfs) { 3159 ret = pci_enable_sriov(pdev, num_vfs); 3160 if (ret) 3161 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 3162 else 3163 return num_vfs; 3164 } else if (!pci_vfs_assigned(pdev)) { 3165 int num_vfs_pre = pci_num_vf(pdev); 3166 3167 pci_disable_sriov(pdev); 3168 hns3_clean_vf_config(pdev, num_vfs_pre); 3169 } else { 3170 dev_warn(&pdev->dev, 3171 "Unable to free VFs because some are assigned to VMs.\n"); 3172 } 3173 3174 return 0; 3175 } 3176 3177 static void hns3_shutdown(struct pci_dev *pdev) 3178 { 3179 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3180 3181 hnae3_unregister_ae_dev(ae_dev); 3182 pci_set_drvdata(pdev, NULL); 3183 3184 if (system_state == SYSTEM_POWER_OFF) 3185 pci_set_power_state(pdev, PCI_D3hot); 3186 } 3187 3188 static int __maybe_unused hns3_suspend(struct device *dev) 3189 { 3190 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev); 3191 3192 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) { 3193 dev_info(dev, "Begin to suspend.\n"); 3194 if (ae_dev->ops && ae_dev->ops->reset_prepare) 3195 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET); 3196 } 3197 3198 return 0; 3199 } 3200 3201 static int __maybe_unused hns3_resume(struct device *dev) 3202 { 3203 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev); 3204 3205 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) { 3206 dev_info(dev, "Begin to resume.\n"); 3207 if (ae_dev->ops && ae_dev->ops->reset_done) 3208 ae_dev->ops->reset_done(ae_dev); 3209 } 3210 3211 return 0; 3212 } 3213 3214 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 3215 pci_channel_state_t state) 3216 { 3217 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3218 pci_ers_result_t ret; 3219 3220 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state); 3221 3222 if (state == pci_channel_io_perm_failure) 3223 return PCI_ERS_RESULT_DISCONNECT; 3224 3225 if (!ae_dev || !ae_dev->ops) { 3226 dev_err(&pdev->dev, 3227 "Can't recover - error happened before device initialized\n"); 3228 return PCI_ERS_RESULT_NONE; 3229 } 3230 3231 if (ae_dev->ops->handle_hw_ras_error) 3232 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 3233 else 3234 return PCI_ERS_RESULT_NONE; 3235 3236 return ret; 3237 } 3238 3239 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 3240 { 3241 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3242 const struct hnae3_ae_ops *ops; 3243 enum hnae3_reset_type reset_type; 3244 struct device *dev = &pdev->dev; 3245 3246 if (!ae_dev || !ae_dev->ops) 3247 return PCI_ERS_RESULT_NONE; 3248 3249 ops = ae_dev->ops; 3250 /* request the reset */ 3251 if (ops->reset_event && ops->get_reset_level && 3252 ops->set_default_reset_request) { 3253 if (ae_dev->hw_err_reset_req) { 3254 reset_type = ops->get_reset_level(ae_dev, 3255 &ae_dev->hw_err_reset_req); 3256 ops->set_default_reset_request(ae_dev, reset_type); 3257 dev_info(dev, "requesting reset due to PCI error\n"); 3258 ops->reset_event(pdev, NULL); 3259 } 3260 3261 return PCI_ERS_RESULT_RECOVERED; 3262 } 3263 3264 return PCI_ERS_RESULT_DISCONNECT; 3265 } 3266 3267 static void hns3_reset_prepare(struct pci_dev *pdev) 3268 { 3269 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3270 3271 dev_info(&pdev->dev, "FLR prepare\n"); 3272 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare) 3273 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET); 3274 } 3275 3276 static void hns3_reset_done(struct pci_dev *pdev) 3277 { 3278 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3279 3280 dev_info(&pdev->dev, "FLR done\n"); 3281 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done) 3282 ae_dev->ops->reset_done(ae_dev); 3283 } 3284 3285 static const struct pci_error_handlers hns3_err_handler = { 3286 .error_detected = hns3_error_detected, 3287 .slot_reset = hns3_slot_reset, 3288 .reset_prepare = hns3_reset_prepare, 3289 .reset_done = hns3_reset_done, 3290 }; 3291 3292 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume); 3293 3294 static struct pci_driver hns3_driver = { 3295 .name = hns3_driver_name, 3296 .id_table = hns3_pci_tbl, 3297 .probe = hns3_probe, 3298 .remove = hns3_remove, 3299 .shutdown = hns3_shutdown, 3300 .driver.pm = &hns3_pm_ops, 3301 .sriov_configure = hns3_pci_sriov_configure, 3302 .err_handler = &hns3_err_handler, 3303 }; 3304 3305 /* set default feature to hns3 */ 3306 static void hns3_set_default_feature(struct net_device *netdev) 3307 { 3308 struct hnae3_handle *h = hns3_get_handle(netdev); 3309 struct pci_dev *pdev = h->pdev; 3310 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3311 3312 netdev->priv_flags |= IFF_UNICAST_FLT; 3313 3314 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3315 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 3316 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 3317 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 3318 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 3319 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 3320 3321 if (hnae3_ae_dev_gro_supported(ae_dev)) 3322 netdev->features |= NETIF_F_GRO_HW; 3323 3324 if (hnae3_ae_dev_fd_supported(ae_dev)) 3325 netdev->features |= NETIF_F_NTUPLE; 3326 3327 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps)) 3328 netdev->features |= NETIF_F_GSO_UDP_L4; 3329 3330 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) 3331 netdev->features |= NETIF_F_HW_CSUM; 3332 else 3333 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 3334 3335 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps)) 3336 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 3337 3338 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) 3339 netdev->features |= NETIF_F_HW_TC; 3340 3341 netdev->hw_features |= netdev->features; 3342 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 3343 netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 3344 3345 netdev->vlan_features |= netdev->features & 3346 ~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX | 3347 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE | 3348 NETIF_F_HW_TC); 3349 3350 netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID; 3351 3352 /* The device_version V3 hardware can't offload the checksum for IP in 3353 * GRE packets, but can do it for NvGRE. So default to disable the 3354 * checksum and GSO offload for GRE. 3355 */ 3356 if (ae_dev->dev_version > HNAE3_DEVICE_VERSION_V2) { 3357 netdev->features &= ~NETIF_F_GSO_GRE; 3358 netdev->features &= ~NETIF_F_GSO_GRE_CSUM; 3359 } 3360 } 3361 3362 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 3363 struct hns3_desc_cb *cb) 3364 { 3365 unsigned int order = hns3_page_order(ring); 3366 struct page *p; 3367 3368 if (ring->page_pool) { 3369 p = page_pool_dev_alloc_frag(ring->page_pool, 3370 &cb->page_offset, 3371 hns3_buf_size(ring)); 3372 if (unlikely(!p)) 3373 return -ENOMEM; 3374 3375 cb->priv = p; 3376 cb->buf = page_address(p); 3377 cb->dma = page_pool_get_dma_addr(p); 3378 cb->type = DESC_TYPE_PP_FRAG; 3379 cb->reuse_flag = 0; 3380 return 0; 3381 } 3382 3383 p = dev_alloc_pages(order); 3384 if (!p) 3385 return -ENOMEM; 3386 3387 cb->priv = p; 3388 cb->page_offset = 0; 3389 cb->reuse_flag = 0; 3390 cb->buf = page_address(p); 3391 cb->length = hns3_page_size(ring); 3392 cb->type = DESC_TYPE_PAGE; 3393 page_ref_add(p, USHRT_MAX - 1); 3394 cb->pagecnt_bias = USHRT_MAX; 3395 3396 return 0; 3397 } 3398 3399 static void hns3_free_buffer(struct hns3_enet_ring *ring, 3400 struct hns3_desc_cb *cb, int budget) 3401 { 3402 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD | 3403 DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB)) 3404 napi_consume_skb(cb->priv, budget); 3405 else if (!HNAE3_IS_TX_RING(ring)) { 3406 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias) 3407 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias); 3408 else if (cb->type & DESC_TYPE_PP_FRAG) 3409 page_pool_put_full_page(ring->page_pool, cb->priv, 3410 false); 3411 } 3412 memset(cb, 0, sizeof(*cb)); 3413 } 3414 3415 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 3416 { 3417 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 3418 cb->length, ring_to_dma_dir(ring)); 3419 3420 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 3421 return -EIO; 3422 3423 return 0; 3424 } 3425 3426 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 3427 struct hns3_desc_cb *cb) 3428 { 3429 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB)) 3430 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 3431 ring_to_dma_dir(ring)); 3432 else if ((cb->type & DESC_TYPE_PAGE) && cb->length) 3433 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 3434 ring_to_dma_dir(ring)); 3435 else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD | 3436 DESC_TYPE_SGL_SKB)) 3437 hns3_tx_spare_reclaim_cb(ring, cb); 3438 } 3439 3440 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 3441 { 3442 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 3443 ring->desc[i].addr = 0; 3444 ring->desc_cb[i].refill = 0; 3445 } 3446 3447 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i, 3448 int budget) 3449 { 3450 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 3451 3452 if (!ring->desc_cb[i].dma) 3453 return; 3454 3455 hns3_buffer_detach(ring, i); 3456 hns3_free_buffer(ring, cb, budget); 3457 } 3458 3459 static void hns3_free_buffers(struct hns3_enet_ring *ring) 3460 { 3461 int i; 3462 3463 for (i = 0; i < ring->desc_num; i++) 3464 hns3_free_buffer_detach(ring, i, 0); 3465 } 3466 3467 /* free desc along with its attached buffer */ 3468 static void hns3_free_desc(struct hns3_enet_ring *ring) 3469 { 3470 int size = ring->desc_num * sizeof(ring->desc[0]); 3471 3472 hns3_free_buffers(ring); 3473 3474 if (ring->desc) { 3475 dma_free_coherent(ring_to_dev(ring), size, 3476 ring->desc, ring->desc_dma_addr); 3477 ring->desc = NULL; 3478 } 3479 } 3480 3481 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 3482 { 3483 int size = ring->desc_num * sizeof(ring->desc[0]); 3484 3485 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 3486 &ring->desc_dma_addr, GFP_KERNEL); 3487 if (!ring->desc) 3488 return -ENOMEM; 3489 3490 return 0; 3491 } 3492 3493 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring, 3494 struct hns3_desc_cb *cb) 3495 { 3496 int ret; 3497 3498 ret = hns3_alloc_buffer(ring, cb); 3499 if (ret || ring->page_pool) 3500 goto out; 3501 3502 ret = hns3_map_buffer(ring, cb); 3503 if (ret) 3504 goto out_with_buf; 3505 3506 return 0; 3507 3508 out_with_buf: 3509 hns3_free_buffer(ring, cb, 0); 3510 out: 3511 return ret; 3512 } 3513 3514 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i) 3515 { 3516 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]); 3517 3518 if (ret) 3519 return ret; 3520 3521 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 3522 ring->desc_cb[i].page_offset); 3523 ring->desc_cb[i].refill = 1; 3524 3525 return 0; 3526 } 3527 3528 /* Allocate memory for raw pkg, and map with dma */ 3529 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 3530 { 3531 int i, j, ret; 3532 3533 for (i = 0; i < ring->desc_num; i++) { 3534 ret = hns3_alloc_and_attach_buffer(ring, i); 3535 if (ret) 3536 goto out_buffer_fail; 3537 3538 if (!(i % HNS3_RESCHED_BD_NUM)) 3539 cond_resched(); 3540 } 3541 3542 return 0; 3543 3544 out_buffer_fail: 3545 for (j = i - 1; j >= 0; j--) 3546 hns3_free_buffer_detach(ring, j, 0); 3547 return ret; 3548 } 3549 3550 /* detach a in-used buffer and replace with a reserved one */ 3551 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 3552 struct hns3_desc_cb *res_cb) 3553 { 3554 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 3555 ring->desc_cb[i] = *res_cb; 3556 ring->desc_cb[i].refill = 1; 3557 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 3558 ring->desc_cb[i].page_offset); 3559 ring->desc[i].rx.bd_base_info = 0; 3560 } 3561 3562 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 3563 { 3564 ring->desc_cb[i].reuse_flag = 0; 3565 ring->desc_cb[i].refill = 1; 3566 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 3567 ring->desc_cb[i].page_offset); 3568 ring->desc[i].rx.bd_base_info = 0; 3569 3570 dma_sync_single_for_device(ring_to_dev(ring), 3571 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset, 3572 hns3_buf_size(ring), 3573 DMA_FROM_DEVICE); 3574 } 3575 3576 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, 3577 int *bytes, int *pkts, int budget) 3578 { 3579 /* This smp_load_acquire() pairs with smp_store_release() in 3580 * hns3_tx_doorbell(). 3581 */ 3582 int ltu = smp_load_acquire(&ring->last_to_use); 3583 int ntc = ring->next_to_clean; 3584 struct hns3_desc_cb *desc_cb; 3585 bool reclaimed = false; 3586 struct hns3_desc *desc; 3587 3588 while (ltu != ntc) { 3589 desc = &ring->desc[ntc]; 3590 3591 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) & 3592 BIT(HNS3_TXD_VLD_B)) 3593 break; 3594 3595 desc_cb = &ring->desc_cb[ntc]; 3596 3597 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL | 3598 DESC_TYPE_BOUNCE_HEAD | 3599 DESC_TYPE_SGL_SKB)) { 3600 (*pkts)++; 3601 (*bytes) += desc_cb->send_bytes; 3602 } 3603 3604 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */ 3605 hns3_free_buffer_detach(ring, ntc, budget); 3606 3607 if (++ntc == ring->desc_num) 3608 ntc = 0; 3609 3610 /* Issue prefetch for next Tx descriptor */ 3611 prefetch(&ring->desc_cb[ntc]); 3612 reclaimed = true; 3613 } 3614 3615 if (unlikely(!reclaimed)) 3616 return false; 3617 3618 /* This smp_store_release() pairs with smp_load_acquire() in 3619 * ring_space called by hns3_nic_net_xmit. 3620 */ 3621 smp_store_release(&ring->next_to_clean, ntc); 3622 3623 hns3_tx_spare_update(ring); 3624 3625 return true; 3626 } 3627 3628 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget) 3629 { 3630 struct net_device *netdev = ring_to_netdev(ring); 3631 struct hns3_nic_priv *priv = netdev_priv(netdev); 3632 struct netdev_queue *dev_queue; 3633 int bytes, pkts; 3634 3635 bytes = 0; 3636 pkts = 0; 3637 3638 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget))) 3639 return; 3640 3641 ring->tqp_vector->tx_group.total_bytes += bytes; 3642 ring->tqp_vector->tx_group.total_packets += pkts; 3643 3644 u64_stats_update_begin(&ring->syncp); 3645 ring->stats.tx_bytes += bytes; 3646 ring->stats.tx_pkts += pkts; 3647 u64_stats_update_end(&ring->syncp); 3648 3649 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 3650 netdev_tx_completed_queue(dev_queue, pkts, bytes); 3651 3652 if (unlikely(netif_carrier_ok(netdev) && 3653 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) { 3654 /* Make sure that anybody stopping the queue after this 3655 * sees the new next_to_clean. 3656 */ 3657 smp_mb(); 3658 if (netif_tx_queue_stopped(dev_queue) && 3659 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 3660 netif_tx_wake_queue(dev_queue); 3661 ring->stats.restart_queue++; 3662 } 3663 } 3664 } 3665 3666 static int hns3_desc_unused(struct hns3_enet_ring *ring) 3667 { 3668 int ntc = ring->next_to_clean; 3669 int ntu = ring->next_to_use; 3670 3671 if (unlikely(ntc == ntu && !ring->desc_cb[ntc].refill)) 3672 return ring->desc_num; 3673 3674 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 3675 } 3676 3677 /* Return true if there is any allocation failure */ 3678 static bool hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, 3679 int cleand_count) 3680 { 3681 struct hns3_desc_cb *desc_cb; 3682 struct hns3_desc_cb res_cbs; 3683 int i, ret; 3684 3685 for (i = 0; i < cleand_count; i++) { 3686 desc_cb = &ring->desc_cb[ring->next_to_use]; 3687 if (desc_cb->reuse_flag) { 3688 hns3_ring_stats_update(ring, reuse_pg_cnt); 3689 3690 hns3_reuse_buffer(ring, ring->next_to_use); 3691 } else { 3692 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 3693 if (ret) { 3694 hns3_ring_stats_update(ring, sw_err_cnt); 3695 3696 hns3_rl_err(ring_to_netdev(ring), 3697 "alloc rx buffer failed: %d\n", 3698 ret); 3699 3700 writel(i, ring->tqp->io_base + 3701 HNS3_RING_RX_RING_HEAD_REG); 3702 return true; 3703 } 3704 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 3705 3706 hns3_ring_stats_update(ring, non_reuse_pg); 3707 } 3708 3709 ring_ptr_move_fw(ring, next_to_use); 3710 } 3711 3712 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 3713 return false; 3714 } 3715 3716 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb) 3717 { 3718 return page_count(cb->priv) == cb->pagecnt_bias; 3719 } 3720 3721 static int hns3_handle_rx_copybreak(struct sk_buff *skb, int i, 3722 struct hns3_enet_ring *ring, 3723 int pull_len, 3724 struct hns3_desc_cb *desc_cb) 3725 { 3726 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 3727 u32 frag_offset = desc_cb->page_offset + pull_len; 3728 int size = le16_to_cpu(desc->rx.size); 3729 u32 frag_size = size - pull_len; 3730 void *frag = napi_alloc_frag(frag_size); 3731 3732 if (unlikely(!frag)) { 3733 hns3_ring_stats_update(ring, frag_alloc_err); 3734 3735 hns3_rl_err(ring_to_netdev(ring), 3736 "failed to allocate rx frag\n"); 3737 return -ENOMEM; 3738 } 3739 3740 desc_cb->reuse_flag = 1; 3741 memcpy(frag, desc_cb->buf + frag_offset, frag_size); 3742 skb_add_rx_frag(skb, i, virt_to_page(frag), 3743 offset_in_page(frag), frag_size, frag_size); 3744 3745 hns3_ring_stats_update(ring, frag_alloc); 3746 return 0; 3747 } 3748 3749 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 3750 struct hns3_enet_ring *ring, int pull_len, 3751 struct hns3_desc_cb *desc_cb) 3752 { 3753 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 3754 u32 frag_offset = desc_cb->page_offset + pull_len; 3755 int size = le16_to_cpu(desc->rx.size); 3756 u32 truesize = hns3_buf_size(ring); 3757 u32 frag_size = size - pull_len; 3758 int ret = 0; 3759 bool reused; 3760 3761 if (ring->page_pool) { 3762 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset, 3763 frag_size, truesize); 3764 return; 3765 } 3766 3767 /* Avoid re-using remote or pfmem page */ 3768 if (unlikely(!dev_page_is_reusable(desc_cb->priv))) 3769 goto out; 3770 3771 reused = hns3_can_reuse_page(desc_cb); 3772 3773 /* Rx page can be reused when: 3774 * 1. Rx page is only owned by the driver when page_offset 3775 * is zero, which means 0 @ truesize will be used by 3776 * stack after skb_add_rx_frag() is called, and the rest 3777 * of rx page can be reused by driver. 3778 * Or 3779 * 2. Rx page is only owned by the driver when page_offset 3780 * is non-zero, which means page_offset @ truesize will 3781 * be used by stack after skb_add_rx_frag() is called, 3782 * and 0 @ truesize can be reused by driver. 3783 */ 3784 if ((!desc_cb->page_offset && reused) || 3785 ((desc_cb->page_offset + truesize + truesize) <= 3786 hns3_page_size(ring) && desc_cb->page_offset)) { 3787 desc_cb->page_offset += truesize; 3788 desc_cb->reuse_flag = 1; 3789 } else if (desc_cb->page_offset && reused) { 3790 desc_cb->page_offset = 0; 3791 desc_cb->reuse_flag = 1; 3792 } else if (frag_size <= ring->rx_copybreak) { 3793 ret = hns3_handle_rx_copybreak(skb, i, ring, pull_len, desc_cb); 3794 if (!ret) 3795 return; 3796 } 3797 3798 out: 3799 desc_cb->pagecnt_bias--; 3800 3801 if (unlikely(!desc_cb->pagecnt_bias)) { 3802 page_ref_add(desc_cb->priv, USHRT_MAX); 3803 desc_cb->pagecnt_bias = USHRT_MAX; 3804 } 3805 3806 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset, 3807 frag_size, truesize); 3808 3809 if (unlikely(!desc_cb->reuse_flag)) 3810 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias); 3811 } 3812 3813 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) 3814 { 3815 __be16 type = skb->protocol; 3816 struct tcphdr *th; 3817 int depth = 0; 3818 3819 while (eth_type_vlan(type)) { 3820 struct vlan_hdr *vh; 3821 3822 if ((depth + VLAN_HLEN) > skb_headlen(skb)) 3823 return -EFAULT; 3824 3825 vh = (struct vlan_hdr *)(skb->data + depth); 3826 type = vh->h_vlan_encapsulated_proto; 3827 depth += VLAN_HLEN; 3828 } 3829 3830 skb_set_network_header(skb, depth); 3831 3832 if (type == htons(ETH_P_IP)) { 3833 const struct iphdr *iph = ip_hdr(skb); 3834 3835 depth += sizeof(struct iphdr); 3836 skb_set_transport_header(skb, depth); 3837 th = tcp_hdr(skb); 3838 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr, 3839 iph->daddr, 0); 3840 } else if (type == htons(ETH_P_IPV6)) { 3841 const struct ipv6hdr *iph = ipv6_hdr(skb); 3842 3843 depth += sizeof(struct ipv6hdr); 3844 skb_set_transport_header(skb, depth); 3845 th = tcp_hdr(skb); 3846 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr, 3847 &iph->daddr, 0); 3848 } else { 3849 hns3_rl_err(skb->dev, 3850 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n", 3851 be16_to_cpu(type), depth); 3852 return -EFAULT; 3853 } 3854 3855 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 3856 if (th->cwr) 3857 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 3858 3859 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B)) 3860 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID; 3861 3862 skb->csum_start = (unsigned char *)th - skb->head; 3863 skb->csum_offset = offsetof(struct tcphdr, check); 3864 skb->ip_summed = CHECKSUM_PARTIAL; 3865 3866 trace_hns3_gro(skb); 3867 3868 return 0; 3869 } 3870 3871 static void hns3_checksum_complete(struct hns3_enet_ring *ring, 3872 struct sk_buff *skb, u32 ptype, u16 csum) 3873 { 3874 if (ptype == HNS3_INVALID_PTYPE || 3875 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE) 3876 return; 3877 3878 hns3_ring_stats_update(ring, csum_complete); 3879 skb->ip_summed = CHECKSUM_COMPLETE; 3880 skb->csum = csum_unfold((__force __sum16)csum); 3881 } 3882 3883 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info, 3884 u32 ol_info, u32 ptype) 3885 { 3886 int l3_type, l4_type; 3887 int ol4_type; 3888 3889 if (ptype != HNS3_INVALID_PTYPE) { 3890 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level; 3891 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed; 3892 3893 return; 3894 } 3895 3896 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M, 3897 HNS3_RXD_OL4ID_S); 3898 switch (ol4_type) { 3899 case HNS3_OL4_TYPE_MAC_IN_UDP: 3900 case HNS3_OL4_TYPE_NVGRE: 3901 skb->csum_level = 1; 3902 fallthrough; 3903 case HNS3_OL4_TYPE_NO_TUN: 3904 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 3905 HNS3_RXD_L3ID_S); 3906 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 3907 HNS3_RXD_L4ID_S); 3908 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 3909 if ((l3_type == HNS3_L3_TYPE_IPV4 || 3910 l3_type == HNS3_L3_TYPE_IPV6) && 3911 (l4_type == HNS3_L4_TYPE_UDP || 3912 l4_type == HNS3_L4_TYPE_TCP || 3913 l4_type == HNS3_L4_TYPE_SCTP)) 3914 skb->ip_summed = CHECKSUM_UNNECESSARY; 3915 break; 3916 default: 3917 break; 3918 } 3919 } 3920 3921 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 3922 u32 l234info, u32 bd_base_info, u32 ol_info, 3923 u16 csum) 3924 { 3925 struct net_device *netdev = ring_to_netdev(ring); 3926 struct hns3_nic_priv *priv = netdev_priv(netdev); 3927 u32 ptype = HNS3_INVALID_PTYPE; 3928 3929 skb->ip_summed = CHECKSUM_NONE; 3930 3931 skb_checksum_none_assert(skb); 3932 3933 if (!(netdev->features & NETIF_F_RXCSUM)) 3934 return; 3935 3936 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) 3937 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, 3938 HNS3_RXD_PTYPE_S); 3939 3940 hns3_checksum_complete(ring, skb, ptype, csum); 3941 3942 /* check if hardware has done checksum */ 3943 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 3944 return; 3945 3946 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | 3947 BIT(HNS3_RXD_OL3E_B) | 3948 BIT(HNS3_RXD_OL4E_B)))) { 3949 skb->ip_summed = CHECKSUM_NONE; 3950 hns3_ring_stats_update(ring, l3l4_csum_err); 3951 3952 return; 3953 } 3954 3955 hns3_rx_handle_csum(skb, l234info, ol_info, ptype); 3956 } 3957 3958 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 3959 { 3960 if (skb_has_frag_list(skb)) 3961 napi_gro_flush(&ring->tqp_vector->napi, false); 3962 3963 napi_gro_receive(&ring->tqp_vector->napi, skb); 3964 } 3965 3966 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 3967 struct hns3_desc *desc, u32 l234info, 3968 u16 *vlan_tag) 3969 { 3970 struct hnae3_handle *handle = ring->tqp->handle; 3971 struct pci_dev *pdev = ring->tqp->handle->pdev; 3972 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3973 3974 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) { 3975 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3976 if (!(*vlan_tag & VLAN_VID_MASK)) 3977 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3978 3979 return (*vlan_tag != 0); 3980 } 3981 3982 #define HNS3_STRP_OUTER_VLAN 0x1 3983 #define HNS3_STRP_INNER_VLAN 0x2 3984 #define HNS3_STRP_BOTH 0x3 3985 3986 /* Hardware always insert VLAN tag into RX descriptor when 3987 * remove the tag from packet, driver needs to determine 3988 * reporting which tag to stack. 3989 */ 3990 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 3991 HNS3_RXD_STRP_TAGP_S)) { 3992 case HNS3_STRP_OUTER_VLAN: 3993 if (handle->port_base_vlan_state != 3994 HNAE3_PORT_BASE_VLAN_DISABLE) 3995 return false; 3996 3997 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3998 return true; 3999 case HNS3_STRP_INNER_VLAN: 4000 if (handle->port_base_vlan_state != 4001 HNAE3_PORT_BASE_VLAN_DISABLE) 4002 return false; 4003 4004 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 4005 return true; 4006 case HNS3_STRP_BOTH: 4007 if (handle->port_base_vlan_state == 4008 HNAE3_PORT_BASE_VLAN_DISABLE) 4009 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 4010 else 4011 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 4012 4013 return true; 4014 default: 4015 return false; 4016 } 4017 } 4018 4019 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring) 4020 { 4021 ring->desc[ring->next_to_clean].rx.bd_base_info &= 4022 cpu_to_le32(~BIT(HNS3_RXD_VLD_B)); 4023 ring->desc_cb[ring->next_to_clean].refill = 0; 4024 ring->next_to_clean += 1; 4025 4026 if (unlikely(ring->next_to_clean == ring->desc_num)) 4027 ring->next_to_clean = 0; 4028 } 4029 4030 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length, 4031 unsigned char *va) 4032 { 4033 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 4034 struct net_device *netdev = ring_to_netdev(ring); 4035 struct sk_buff *skb; 4036 4037 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 4038 skb = ring->skb; 4039 if (unlikely(!skb)) { 4040 hns3_rl_err(netdev, "alloc rx skb fail\n"); 4041 hns3_ring_stats_update(ring, sw_err_cnt); 4042 4043 return -ENOMEM; 4044 } 4045 4046 trace_hns3_rx_desc(ring); 4047 prefetchw(skb->data); 4048 4049 ring->pending_buf = 1; 4050 ring->frag_num = 0; 4051 ring->tail_skb = NULL; 4052 if (length <= HNS3_RX_HEAD_SIZE) { 4053 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 4054 4055 /* We can reuse buffer as-is, just make sure it is reusable */ 4056 if (dev_page_is_reusable(desc_cb->priv)) 4057 desc_cb->reuse_flag = 1; 4058 else if (desc_cb->type & DESC_TYPE_PP_FRAG) 4059 page_pool_put_full_page(ring->page_pool, desc_cb->priv, 4060 false); 4061 else /* This page cannot be reused so discard it */ 4062 __page_frag_cache_drain(desc_cb->priv, 4063 desc_cb->pagecnt_bias); 4064 4065 hns3_rx_ring_move_fw(ring); 4066 return 0; 4067 } 4068 4069 if (ring->page_pool) 4070 skb_mark_for_recycle(skb); 4071 4072 hns3_ring_stats_update(ring, seg_pkt_cnt); 4073 4074 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE); 4075 __skb_put(skb, ring->pull_len); 4076 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 4077 desc_cb); 4078 hns3_rx_ring_move_fw(ring); 4079 4080 return 0; 4081 } 4082 4083 static int hns3_add_frag(struct hns3_enet_ring *ring) 4084 { 4085 struct sk_buff *skb = ring->skb; 4086 struct sk_buff *head_skb = skb; 4087 struct sk_buff *new_skb; 4088 struct hns3_desc_cb *desc_cb; 4089 struct hns3_desc *desc; 4090 u32 bd_base_info; 4091 4092 do { 4093 desc = &ring->desc[ring->next_to_clean]; 4094 desc_cb = &ring->desc_cb[ring->next_to_clean]; 4095 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 4096 /* make sure HW write desc complete */ 4097 dma_rmb(); 4098 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 4099 return -ENXIO; 4100 4101 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 4102 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0); 4103 if (unlikely(!new_skb)) { 4104 hns3_rl_err(ring_to_netdev(ring), 4105 "alloc rx fraglist skb fail\n"); 4106 return -ENXIO; 4107 } 4108 4109 if (ring->page_pool) 4110 skb_mark_for_recycle(new_skb); 4111 4112 ring->frag_num = 0; 4113 4114 if (ring->tail_skb) { 4115 ring->tail_skb->next = new_skb; 4116 ring->tail_skb = new_skb; 4117 } else { 4118 skb_shinfo(skb)->frag_list = new_skb; 4119 ring->tail_skb = new_skb; 4120 } 4121 } 4122 4123 if (ring->tail_skb) { 4124 head_skb->truesize += hns3_buf_size(ring); 4125 head_skb->data_len += le16_to_cpu(desc->rx.size); 4126 head_skb->len += le16_to_cpu(desc->rx.size); 4127 skb = ring->tail_skb; 4128 } 4129 4130 dma_sync_single_for_cpu(ring_to_dev(ring), 4131 desc_cb->dma + desc_cb->page_offset, 4132 hns3_buf_size(ring), 4133 DMA_FROM_DEVICE); 4134 4135 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 4136 trace_hns3_rx_desc(ring); 4137 hns3_rx_ring_move_fw(ring); 4138 ring->pending_buf++; 4139 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B))); 4140 4141 return 0; 4142 } 4143 4144 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring, 4145 struct sk_buff *skb, u32 l234info, 4146 u32 bd_base_info, u32 ol_info, u16 csum) 4147 { 4148 struct net_device *netdev = ring_to_netdev(ring); 4149 struct hns3_nic_priv *priv = netdev_priv(netdev); 4150 u32 l3_type; 4151 4152 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 4153 HNS3_RXD_GRO_SIZE_M, 4154 HNS3_RXD_GRO_SIZE_S); 4155 /* if there is no HW GRO, do not set gro params */ 4156 if (!skb_shinfo(skb)->gso_size) { 4157 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info, 4158 csum); 4159 return 0; 4160 } 4161 4162 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info, 4163 HNS3_RXD_GRO_COUNT_M, 4164 HNS3_RXD_GRO_COUNT_S); 4165 4166 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) { 4167 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, 4168 HNS3_RXD_PTYPE_S); 4169 4170 l3_type = hns3_rx_ptype_tbl[ptype].l3_type; 4171 } else { 4172 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 4173 HNS3_RXD_L3ID_S); 4174 } 4175 4176 if (l3_type == HNS3_L3_TYPE_IPV4) 4177 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 4178 else if (l3_type == HNS3_L3_TYPE_IPV6) 4179 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 4180 else 4181 return -EFAULT; 4182 4183 return hns3_gro_complete(skb, l234info); 4184 } 4185 4186 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 4187 struct sk_buff *skb, u32 rss_hash, 4188 u32 l234info, u32 ol_info) 4189 { 4190 enum pkt_hash_types rss_type = PKT_HASH_TYPE_NONE; 4191 struct net_device *netdev = ring_to_netdev(ring); 4192 struct hns3_nic_priv *priv = netdev_priv(netdev); 4193 4194 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) { 4195 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, 4196 HNS3_RXD_PTYPE_S); 4197 4198 rss_type = hns3_rx_ptype_tbl[ptype].hash_type; 4199 } else { 4200 int l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 4201 HNS3_RXD_L3ID_S); 4202 int l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 4203 HNS3_RXD_L4ID_S); 4204 4205 if (l3_type == HNS3_L3_TYPE_IPV4 || 4206 l3_type == HNS3_L3_TYPE_IPV6) { 4207 if (l4_type == HNS3_L4_TYPE_UDP || 4208 l4_type == HNS3_L4_TYPE_TCP || 4209 l4_type == HNS3_L4_TYPE_SCTP) 4210 rss_type = PKT_HASH_TYPE_L4; 4211 else if (l4_type == HNS3_L4_TYPE_IGMP || 4212 l4_type == HNS3_L4_TYPE_ICMP) 4213 rss_type = PKT_HASH_TYPE_L3; 4214 } 4215 } 4216 4217 skb_set_hash(skb, rss_hash, rss_type); 4218 } 4219 4220 static void hns3_handle_rx_ts_info(struct net_device *netdev, 4221 struct hns3_desc *desc, struct sk_buff *skb, 4222 u32 bd_base_info) 4223 { 4224 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) { 4225 struct hnae3_handle *h = hns3_get_handle(netdev); 4226 u32 nsec = le32_to_cpu(desc->ts_nsec); 4227 u32 sec = le32_to_cpu(desc->ts_sec); 4228 4229 if (h->ae_algo->ops->get_rx_hwts) 4230 h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec); 4231 } 4232 } 4233 4234 static void hns3_handle_rx_vlan_tag(struct hns3_enet_ring *ring, 4235 struct hns3_desc *desc, struct sk_buff *skb, 4236 u32 l234info) 4237 { 4238 struct net_device *netdev = ring_to_netdev(ring); 4239 4240 /* Based on hw strategy, the tag offloaded will be stored at 4241 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 4242 * in one layer tag case. 4243 */ 4244 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 4245 u16 vlan_tag; 4246 4247 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 4248 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 4249 vlan_tag); 4250 } 4251 } 4252 4253 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb) 4254 { 4255 struct net_device *netdev = ring_to_netdev(ring); 4256 enum hns3_pkt_l2t_type l2_frame_type; 4257 u32 bd_base_info, l234info, ol_info; 4258 struct hns3_desc *desc; 4259 unsigned int len; 4260 int pre_ntc, ret; 4261 u16 csum; 4262 4263 /* bdinfo handled below is only valid on the last BD of the 4264 * current packet, and ring->next_to_clean indicates the first 4265 * descriptor of next packet, so need - 1 below. 4266 */ 4267 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) : 4268 (ring->desc_num - 1); 4269 desc = &ring->desc[pre_ntc]; 4270 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 4271 l234info = le32_to_cpu(desc->rx.l234_info); 4272 ol_info = le32_to_cpu(desc->rx.ol_info); 4273 csum = le16_to_cpu(desc->csum); 4274 4275 hns3_handle_rx_ts_info(netdev, desc, skb, bd_base_info); 4276 4277 hns3_handle_rx_vlan_tag(ring, desc, skb, l234info); 4278 4279 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 4280 BIT(HNS3_RXD_L2E_B))))) { 4281 u64_stats_update_begin(&ring->syncp); 4282 if (l234info & BIT(HNS3_RXD_L2E_B)) 4283 ring->stats.l2_err++; 4284 else 4285 ring->stats.err_pkt_len++; 4286 u64_stats_update_end(&ring->syncp); 4287 4288 return -EFAULT; 4289 } 4290 4291 len = skb->len; 4292 4293 /* Do update ip stack process */ 4294 skb->protocol = eth_type_trans(skb, netdev); 4295 4296 /* This is needed in order to enable forwarding support */ 4297 ret = hns3_set_gro_and_checksum(ring, skb, l234info, 4298 bd_base_info, ol_info, csum); 4299 if (unlikely(ret)) { 4300 hns3_ring_stats_update(ring, rx_err_cnt); 4301 return ret; 4302 } 4303 4304 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 4305 HNS3_RXD_DMAC_S); 4306 4307 u64_stats_update_begin(&ring->syncp); 4308 ring->stats.rx_pkts++; 4309 ring->stats.rx_bytes += len; 4310 4311 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 4312 ring->stats.rx_multicast++; 4313 4314 u64_stats_update_end(&ring->syncp); 4315 4316 ring->tqp_vector->rx_group.total_bytes += len; 4317 4318 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash), 4319 l234info, ol_info); 4320 return 0; 4321 } 4322 4323 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring) 4324 { 4325 struct sk_buff *skb = ring->skb; 4326 struct hns3_desc_cb *desc_cb; 4327 struct hns3_desc *desc; 4328 unsigned int length; 4329 u32 bd_base_info; 4330 int ret; 4331 4332 desc = &ring->desc[ring->next_to_clean]; 4333 desc_cb = &ring->desc_cb[ring->next_to_clean]; 4334 4335 prefetch(desc); 4336 4337 if (!skb) { 4338 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 4339 /* Check valid BD */ 4340 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 4341 return -ENXIO; 4342 4343 dma_rmb(); 4344 length = le16_to_cpu(desc->rx.size); 4345 4346 ring->va = desc_cb->buf + desc_cb->page_offset; 4347 4348 dma_sync_single_for_cpu(ring_to_dev(ring), 4349 desc_cb->dma + desc_cb->page_offset, 4350 hns3_buf_size(ring), 4351 DMA_FROM_DEVICE); 4352 4353 /* Prefetch first cache line of first page. 4354 * Idea is to cache few bytes of the header of the packet. 4355 * Our L1 Cache line size is 64B so need to prefetch twice to make 4356 * it 128B. But in actual we can have greater size of caches with 4357 * 128B Level 1 cache lines. In such a case, single fetch would 4358 * suffice to cache in the relevant part of the header. 4359 */ 4360 net_prefetch(ring->va); 4361 4362 ret = hns3_alloc_skb(ring, length, ring->va); 4363 skb = ring->skb; 4364 4365 if (ret < 0) /* alloc buffer fail */ 4366 return ret; 4367 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */ 4368 ret = hns3_add_frag(ring); 4369 if (ret) 4370 return ret; 4371 } 4372 } else { 4373 ret = hns3_add_frag(ring); 4374 if (ret) 4375 return ret; 4376 } 4377 4378 /* As the head data may be changed when GRO enable, copy 4379 * the head data in after other data rx completed 4380 */ 4381 if (skb->len > HNS3_RX_HEAD_SIZE) 4382 memcpy(skb->data, ring->va, 4383 ALIGN(ring->pull_len, sizeof(long))); 4384 4385 ret = hns3_handle_bdinfo(ring, skb); 4386 if (unlikely(ret)) { 4387 dev_kfree_skb_any(skb); 4388 return ret; 4389 } 4390 4391 skb_record_rx_queue(skb, ring->tqp->tqp_index); 4392 return 0; 4393 } 4394 4395 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget, 4396 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 4397 { 4398 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 4399 int unused_count = hns3_desc_unused(ring); 4400 bool failure = false; 4401 int recv_pkts = 0; 4402 int err; 4403 4404 unused_count -= ring->pending_buf; 4405 4406 while (recv_pkts < budget) { 4407 /* Reuse or realloc buffers */ 4408 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 4409 failure = failure || 4410 hns3_nic_alloc_rx_buffers(ring, unused_count); 4411 unused_count = 0; 4412 } 4413 4414 /* Poll one pkt */ 4415 err = hns3_handle_rx_bd(ring); 4416 /* Do not get FE for the packet or failed to alloc skb */ 4417 if (unlikely(!ring->skb || err == -ENXIO)) { 4418 goto out; 4419 } else if (likely(!err)) { 4420 rx_fn(ring, ring->skb); 4421 recv_pkts++; 4422 } 4423 4424 unused_count += ring->pending_buf; 4425 ring->skb = NULL; 4426 ring->pending_buf = 0; 4427 } 4428 4429 out: 4430 /* sync head pointer before exiting, since hardware will calculate 4431 * FBD number with head pointer 4432 */ 4433 if (unused_count > 0) 4434 failure = failure || 4435 hns3_nic_alloc_rx_buffers(ring, unused_count); 4436 4437 return failure ? budget : recv_pkts; 4438 } 4439 4440 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector) 4441 { 4442 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 4443 struct dim_sample sample = {}; 4444 4445 if (!rx_group->coal.adapt_enable) 4446 return; 4447 4448 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets, 4449 rx_group->total_bytes, &sample); 4450 net_dim(&rx_group->dim, &sample); 4451 } 4452 4453 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector) 4454 { 4455 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 4456 struct dim_sample sample = {}; 4457 4458 if (!tx_group->coal.adapt_enable) 4459 return; 4460 4461 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets, 4462 tx_group->total_bytes, &sample); 4463 net_dim(&tx_group->dim, &sample); 4464 } 4465 4466 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 4467 { 4468 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 4469 struct hns3_enet_ring *ring; 4470 int rx_pkt_total = 0; 4471 4472 struct hns3_enet_tqp_vector *tqp_vector = 4473 container_of(napi, struct hns3_enet_tqp_vector, napi); 4474 bool clean_complete = true; 4475 int rx_budget = budget; 4476 4477 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 4478 napi_complete(napi); 4479 return 0; 4480 } 4481 4482 /* Since the actual Tx work is minimal, we can give the Tx a larger 4483 * budget and be more aggressive about cleaning up the Tx descriptors. 4484 */ 4485 hns3_for_each_ring(ring, tqp_vector->tx_group) 4486 hns3_clean_tx_ring(ring, budget); 4487 4488 /* make sure rx ring budget not smaller than 1 */ 4489 if (tqp_vector->num_tqps > 1) 4490 rx_budget = max(budget / tqp_vector->num_tqps, 1); 4491 4492 hns3_for_each_ring(ring, tqp_vector->rx_group) { 4493 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 4494 hns3_rx_skb); 4495 if (rx_cleaned >= rx_budget) 4496 clean_complete = false; 4497 4498 rx_pkt_total += rx_cleaned; 4499 } 4500 4501 tqp_vector->rx_group.total_packets += rx_pkt_total; 4502 4503 if (!clean_complete) 4504 return budget; 4505 4506 if (napi_complete(napi) && 4507 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 4508 hns3_update_rx_int_coalesce(tqp_vector); 4509 hns3_update_tx_int_coalesce(tqp_vector); 4510 4511 hns3_mask_vector_irq(tqp_vector, 1); 4512 } 4513 4514 return rx_pkt_total; 4515 } 4516 4517 static int hns3_create_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 4518 struct hnae3_ring_chain_node **head, 4519 bool is_tx) 4520 { 4521 u32 bit_value = is_tx ? HNAE3_RING_TYPE_TX : HNAE3_RING_TYPE_RX; 4522 u32 field_value = is_tx ? HNAE3_RING_GL_TX : HNAE3_RING_GL_RX; 4523 struct hnae3_ring_chain_node *cur_chain = *head; 4524 struct pci_dev *pdev = tqp_vector->handle->pdev; 4525 struct hnae3_ring_chain_node *chain; 4526 struct hns3_enet_ring *ring; 4527 4528 ring = is_tx ? tqp_vector->tx_group.ring : tqp_vector->rx_group.ring; 4529 4530 if (cur_chain) { 4531 while (cur_chain->next) 4532 cur_chain = cur_chain->next; 4533 } 4534 4535 while (ring) { 4536 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 4537 if (!chain) 4538 return -ENOMEM; 4539 if (cur_chain) 4540 cur_chain->next = chain; 4541 else 4542 *head = chain; 4543 chain->tqp_index = ring->tqp->tqp_index; 4544 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 4545 bit_value); 4546 hnae3_set_field(chain->int_gl_idx, 4547 HNAE3_RING_GL_IDX_M, 4548 HNAE3_RING_GL_IDX_S, field_value); 4549 4550 cur_chain = chain; 4551 4552 ring = ring->next; 4553 } 4554 4555 return 0; 4556 } 4557 4558 static struct hnae3_ring_chain_node * 4559 hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector) 4560 { 4561 struct pci_dev *pdev = tqp_vector->handle->pdev; 4562 struct hnae3_ring_chain_node *cur_chain = NULL; 4563 struct hnae3_ring_chain_node *chain; 4564 4565 if (hns3_create_ring_chain(tqp_vector, &cur_chain, true)) 4566 goto err_free_chain; 4567 4568 if (hns3_create_ring_chain(tqp_vector, &cur_chain, false)) 4569 goto err_free_chain; 4570 4571 return cur_chain; 4572 4573 err_free_chain: 4574 while (cur_chain) { 4575 chain = cur_chain->next; 4576 devm_kfree(&pdev->dev, cur_chain); 4577 cur_chain = chain; 4578 } 4579 4580 return NULL; 4581 } 4582 4583 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 4584 struct hnae3_ring_chain_node *head) 4585 { 4586 struct pci_dev *pdev = tqp_vector->handle->pdev; 4587 struct hnae3_ring_chain_node *chain_tmp, *chain; 4588 4589 chain = head; 4590 4591 while (chain) { 4592 chain_tmp = chain->next; 4593 devm_kfree(&pdev->dev, chain); 4594 chain = chain_tmp; 4595 } 4596 } 4597 4598 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 4599 struct hns3_enet_ring *ring) 4600 { 4601 ring->next = group->ring; 4602 group->ring = ring; 4603 4604 group->count++; 4605 } 4606 4607 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 4608 { 4609 struct pci_dev *pdev = priv->ae_handle->pdev; 4610 struct hns3_enet_tqp_vector *tqp_vector; 4611 int num_vectors = priv->vector_num; 4612 int numa_node; 4613 int vector_i; 4614 4615 numa_node = dev_to_node(&pdev->dev); 4616 4617 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 4618 tqp_vector = &priv->tqp_vector[vector_i]; 4619 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 4620 &tqp_vector->affinity_mask); 4621 } 4622 } 4623 4624 static void hns3_rx_dim_work(struct work_struct *work) 4625 { 4626 struct dim *dim = container_of(work, struct dim, work); 4627 struct hns3_enet_ring_group *group = container_of(dim, 4628 struct hns3_enet_ring_group, dim); 4629 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector; 4630 struct dim_cq_moder cur_moder = 4631 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 4632 4633 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec); 4634 tqp_vector->rx_group.coal.int_gl = cur_moder.usec; 4635 4636 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) { 4637 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts); 4638 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts; 4639 } 4640 4641 dim->state = DIM_START_MEASURE; 4642 } 4643 4644 static void hns3_tx_dim_work(struct work_struct *work) 4645 { 4646 struct dim *dim = container_of(work, struct dim, work); 4647 struct hns3_enet_ring_group *group = container_of(dim, 4648 struct hns3_enet_ring_group, dim); 4649 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector; 4650 struct dim_cq_moder cur_moder = 4651 net_dim_get_tx_moderation(dim->mode, dim->profile_ix); 4652 4653 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec); 4654 tqp_vector->tx_group.coal.int_gl = cur_moder.usec; 4655 4656 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) { 4657 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts); 4658 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts; 4659 } 4660 4661 dim->state = DIM_START_MEASURE; 4662 } 4663 4664 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector) 4665 { 4666 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work); 4667 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work); 4668 } 4669 4670 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 4671 { 4672 struct hnae3_handle *h = priv->ae_handle; 4673 struct hns3_enet_tqp_vector *tqp_vector; 4674 int ret; 4675 int i; 4676 4677 hns3_nic_set_cpumask(priv); 4678 4679 for (i = 0; i < priv->vector_num; i++) { 4680 tqp_vector = &priv->tqp_vector[i]; 4681 hns3_vector_coalesce_init_hw(tqp_vector, priv); 4682 tqp_vector->num_tqps = 0; 4683 hns3_nic_init_dim(tqp_vector); 4684 } 4685 4686 for (i = 0; i < h->kinfo.num_tqps; i++) { 4687 u16 vector_i = i % priv->vector_num; 4688 u16 tqp_num = h->kinfo.num_tqps; 4689 4690 tqp_vector = &priv->tqp_vector[vector_i]; 4691 4692 hns3_add_ring_to_group(&tqp_vector->tx_group, 4693 &priv->ring[i]); 4694 4695 hns3_add_ring_to_group(&tqp_vector->rx_group, 4696 &priv->ring[i + tqp_num]); 4697 4698 priv->ring[i].tqp_vector = tqp_vector; 4699 priv->ring[i + tqp_num].tqp_vector = tqp_vector; 4700 tqp_vector->num_tqps++; 4701 } 4702 4703 for (i = 0; i < priv->vector_num; i++) { 4704 struct hnae3_ring_chain_node *vector_ring_chain; 4705 4706 tqp_vector = &priv->tqp_vector[i]; 4707 4708 tqp_vector->rx_group.total_bytes = 0; 4709 tqp_vector->rx_group.total_packets = 0; 4710 tqp_vector->tx_group.total_bytes = 0; 4711 tqp_vector->tx_group.total_packets = 0; 4712 tqp_vector->handle = h; 4713 4714 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector); 4715 if (!vector_ring_chain) { 4716 ret = -ENOMEM; 4717 goto map_ring_fail; 4718 } 4719 4720 ret = h->ae_algo->ops->map_ring_to_vector(h, 4721 tqp_vector->vector_irq, vector_ring_chain); 4722 4723 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain); 4724 4725 if (ret) 4726 goto map_ring_fail; 4727 4728 netif_napi_add(priv->netdev, &tqp_vector->napi, 4729 hns3_nic_common_poll); 4730 } 4731 4732 return 0; 4733 4734 map_ring_fail: 4735 while (i--) 4736 netif_napi_del(&priv->tqp_vector[i].napi); 4737 4738 return ret; 4739 } 4740 4741 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv) 4742 { 4743 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 4744 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal; 4745 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal; 4746 4747 /* initialize the configuration for interrupt coalescing. 4748 * 1. GL (Interrupt Gap Limiter) 4749 * 2. RL (Interrupt Rate Limiter) 4750 * 3. QL (Interrupt Quantity Limiter) 4751 * 4752 * Default: enable interrupt coalescing self-adaptive and GL 4753 */ 4754 tx_coal->adapt_enable = 1; 4755 rx_coal->adapt_enable = 1; 4756 4757 tx_coal->int_gl = HNS3_INT_GL_50K; 4758 rx_coal->int_gl = HNS3_INT_GL_50K; 4759 4760 rx_coal->flow_level = HNS3_FLOW_LOW; 4761 tx_coal->flow_level = HNS3_FLOW_LOW; 4762 4763 if (ae_dev->dev_specs.int_ql_max) { 4764 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 4765 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 4766 } 4767 } 4768 4769 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 4770 { 4771 struct hnae3_handle *h = priv->ae_handle; 4772 struct hns3_enet_tqp_vector *tqp_vector; 4773 struct hnae3_vector_info *vector; 4774 struct pci_dev *pdev = h->pdev; 4775 u16 tqp_num = h->kinfo.num_tqps; 4776 u16 vector_num; 4777 int ret = 0; 4778 u16 i; 4779 4780 /* RSS size, cpu online and vector_num should be the same */ 4781 /* Should consider 2p/4p later */ 4782 vector_num = min_t(u16, num_online_cpus(), tqp_num); 4783 4784 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 4785 GFP_KERNEL); 4786 if (!vector) 4787 return -ENOMEM; 4788 4789 /* save the actual available vector number */ 4790 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 4791 4792 priv->vector_num = vector_num; 4793 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 4794 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 4795 GFP_KERNEL); 4796 if (!priv->tqp_vector) { 4797 ret = -ENOMEM; 4798 goto out; 4799 } 4800 4801 for (i = 0; i < priv->vector_num; i++) { 4802 tqp_vector = &priv->tqp_vector[i]; 4803 tqp_vector->idx = i; 4804 tqp_vector->mask_addr = vector[i].io_addr; 4805 tqp_vector->vector_irq = vector[i].vector; 4806 hns3_vector_coalesce_init(tqp_vector, priv); 4807 } 4808 4809 out: 4810 devm_kfree(&pdev->dev, vector); 4811 return ret; 4812 } 4813 4814 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 4815 { 4816 group->ring = NULL; 4817 group->count = 0; 4818 } 4819 4820 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 4821 { 4822 struct hnae3_ring_chain_node *vector_ring_chain; 4823 struct hnae3_handle *h = priv->ae_handle; 4824 struct hns3_enet_tqp_vector *tqp_vector; 4825 int i; 4826 4827 for (i = 0; i < priv->vector_num; i++) { 4828 tqp_vector = &priv->tqp_vector[i]; 4829 4830 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 4831 continue; 4832 4833 /* Since the mapping can be overwritten, when fail to get the 4834 * chain between vector and ring, we should go on to deal with 4835 * the remaining options. 4836 */ 4837 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector); 4838 if (!vector_ring_chain) 4839 dev_warn(priv->dev, "failed to get ring chain\n"); 4840 4841 h->ae_algo->ops->unmap_ring_from_vector(h, 4842 tqp_vector->vector_irq, vector_ring_chain); 4843 4844 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain); 4845 4846 hns3_clear_ring_group(&tqp_vector->rx_group); 4847 hns3_clear_ring_group(&tqp_vector->tx_group); 4848 netif_napi_del(&priv->tqp_vector[i].napi); 4849 } 4850 } 4851 4852 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 4853 { 4854 struct hnae3_handle *h = priv->ae_handle; 4855 struct pci_dev *pdev = h->pdev; 4856 int i, ret; 4857 4858 for (i = 0; i < priv->vector_num; i++) { 4859 struct hns3_enet_tqp_vector *tqp_vector; 4860 4861 tqp_vector = &priv->tqp_vector[i]; 4862 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 4863 if (ret) 4864 return; 4865 } 4866 4867 devm_kfree(&pdev->dev, priv->tqp_vector); 4868 } 4869 4870 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 4871 unsigned int ring_type) 4872 { 4873 int queue_num = priv->ae_handle->kinfo.num_tqps; 4874 struct hns3_enet_ring *ring; 4875 int desc_num; 4876 4877 if (ring_type == HNAE3_RING_TYPE_TX) { 4878 ring = &priv->ring[q->tqp_index]; 4879 desc_num = priv->ae_handle->kinfo.num_tx_desc; 4880 ring->queue_index = q->tqp_index; 4881 ring->tx_copybreak = priv->tx_copybreak; 4882 ring->last_to_use = 0; 4883 } else { 4884 ring = &priv->ring[q->tqp_index + queue_num]; 4885 desc_num = priv->ae_handle->kinfo.num_rx_desc; 4886 ring->queue_index = q->tqp_index; 4887 ring->rx_copybreak = priv->rx_copybreak; 4888 } 4889 4890 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 4891 4892 ring->tqp = q; 4893 ring->desc = NULL; 4894 ring->desc_cb = NULL; 4895 ring->dev = priv->dev; 4896 ring->desc_dma_addr = 0; 4897 ring->buf_size = q->buf_size; 4898 ring->desc_num = desc_num; 4899 ring->next_to_use = 0; 4900 ring->next_to_clean = 0; 4901 } 4902 4903 static void hns3_queue_to_ring(struct hnae3_queue *tqp, 4904 struct hns3_nic_priv *priv) 4905 { 4906 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 4907 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 4908 } 4909 4910 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 4911 { 4912 struct hnae3_handle *h = priv->ae_handle; 4913 struct pci_dev *pdev = h->pdev; 4914 int i; 4915 4916 priv->ring = devm_kzalloc(&pdev->dev, 4917 array3_size(h->kinfo.num_tqps, 4918 sizeof(*priv->ring), 2), 4919 GFP_KERNEL); 4920 if (!priv->ring) 4921 return -ENOMEM; 4922 4923 for (i = 0; i < h->kinfo.num_tqps; i++) 4924 hns3_queue_to_ring(h->kinfo.tqp[i], priv); 4925 4926 return 0; 4927 } 4928 4929 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 4930 { 4931 if (!priv->ring) 4932 return; 4933 4934 devm_kfree(priv->dev, priv->ring); 4935 priv->ring = NULL; 4936 } 4937 4938 static void hns3_alloc_page_pool(struct hns3_enet_ring *ring) 4939 { 4940 struct page_pool_params pp_params = { 4941 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 4942 .order = hns3_page_order(ring), 4943 .pool_size = ring->desc_num * hns3_buf_size(ring) / 4944 (PAGE_SIZE << hns3_page_order(ring)), 4945 .nid = dev_to_node(ring_to_dev(ring)), 4946 .dev = ring_to_dev(ring), 4947 .dma_dir = DMA_FROM_DEVICE, 4948 .offset = 0, 4949 .max_len = PAGE_SIZE << hns3_page_order(ring), 4950 }; 4951 4952 ring->page_pool = page_pool_create(&pp_params); 4953 if (IS_ERR(ring->page_pool)) { 4954 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n", 4955 PTR_ERR(ring->page_pool)); 4956 ring->page_pool = NULL; 4957 } 4958 } 4959 4960 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 4961 { 4962 int ret; 4963 4964 if (ring->desc_num <= 0 || ring->buf_size <= 0) 4965 return -EINVAL; 4966 4967 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num, 4968 sizeof(ring->desc_cb[0]), GFP_KERNEL); 4969 if (!ring->desc_cb) { 4970 ret = -ENOMEM; 4971 goto out; 4972 } 4973 4974 ret = hns3_alloc_desc(ring); 4975 if (ret) 4976 goto out_with_desc_cb; 4977 4978 if (!HNAE3_IS_TX_RING(ring)) { 4979 if (page_pool_enabled) 4980 hns3_alloc_page_pool(ring); 4981 4982 ret = hns3_alloc_ring_buffers(ring); 4983 if (ret) 4984 goto out_with_desc; 4985 } else { 4986 hns3_init_tx_spare_buffer(ring); 4987 } 4988 4989 return 0; 4990 4991 out_with_desc: 4992 hns3_free_desc(ring); 4993 out_with_desc_cb: 4994 devm_kfree(ring_to_dev(ring), ring->desc_cb); 4995 ring->desc_cb = NULL; 4996 out: 4997 return ret; 4998 } 4999 5000 void hns3_fini_ring(struct hns3_enet_ring *ring) 5001 { 5002 hns3_free_desc(ring); 5003 devm_kfree(ring_to_dev(ring), ring->desc_cb); 5004 ring->desc_cb = NULL; 5005 ring->next_to_clean = 0; 5006 ring->next_to_use = 0; 5007 ring->last_to_use = 0; 5008 ring->pending_buf = 0; 5009 if (!HNAE3_IS_TX_RING(ring) && ring->skb) { 5010 dev_kfree_skb_any(ring->skb); 5011 ring->skb = NULL; 5012 } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) { 5013 struct hns3_tx_spare *tx_spare = ring->tx_spare; 5014 5015 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len, 5016 DMA_TO_DEVICE); 5017 free_pages((unsigned long)tx_spare->buf, 5018 get_order(tx_spare->len)); 5019 devm_kfree(ring_to_dev(ring), tx_spare); 5020 ring->tx_spare = NULL; 5021 } 5022 5023 if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) { 5024 page_pool_destroy(ring->page_pool); 5025 ring->page_pool = NULL; 5026 } 5027 } 5028 5029 static int hns3_buf_size2type(u32 buf_size) 5030 { 5031 int bd_size_type; 5032 5033 switch (buf_size) { 5034 case 512: 5035 bd_size_type = HNS3_BD_SIZE_512_TYPE; 5036 break; 5037 case 1024: 5038 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 5039 break; 5040 case 2048: 5041 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 5042 break; 5043 case 4096: 5044 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 5045 break; 5046 default: 5047 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 5048 } 5049 5050 return bd_size_type; 5051 } 5052 5053 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 5054 { 5055 dma_addr_t dma = ring->desc_dma_addr; 5056 struct hnae3_queue *q = ring->tqp; 5057 5058 if (!HNAE3_IS_TX_RING(ring)) { 5059 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma); 5060 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 5061 (u32)((dma >> 31) >> 1)); 5062 5063 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 5064 hns3_buf_size2type(ring->buf_size)); 5065 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 5066 ring->desc_num / 8 - 1); 5067 } else { 5068 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 5069 (u32)dma); 5070 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 5071 (u32)((dma >> 31) >> 1)); 5072 5073 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 5074 ring->desc_num / 8 - 1); 5075 } 5076 } 5077 5078 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 5079 { 5080 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 5081 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 5082 int i; 5083 5084 for (i = 0; i < tc_info->num_tc; i++) { 5085 int j; 5086 5087 for (j = 0; j < tc_info->tqp_count[i]; j++) { 5088 struct hnae3_queue *q; 5089 5090 q = priv->ring[tc_info->tqp_offset[i] + j].tqp; 5091 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i); 5092 } 5093 } 5094 } 5095 5096 int hns3_init_all_ring(struct hns3_nic_priv *priv) 5097 { 5098 struct hnae3_handle *h = priv->ae_handle; 5099 int ring_num = h->kinfo.num_tqps * 2; 5100 int i, j; 5101 int ret; 5102 5103 for (i = 0; i < ring_num; i++) { 5104 ret = hns3_alloc_ring_memory(&priv->ring[i]); 5105 if (ret) { 5106 dev_err(priv->dev, 5107 "Alloc ring memory fail! ret=%d\n", ret); 5108 goto out_when_alloc_ring_memory; 5109 } 5110 5111 u64_stats_init(&priv->ring[i].syncp); 5112 cond_resched(); 5113 } 5114 5115 return 0; 5116 5117 out_when_alloc_ring_memory: 5118 for (j = i - 1; j >= 0; j--) 5119 hns3_fini_ring(&priv->ring[j]); 5120 5121 return -ENOMEM; 5122 } 5123 5124 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv) 5125 { 5126 struct hnae3_handle *h = priv->ae_handle; 5127 int i; 5128 5129 for (i = 0; i < h->kinfo.num_tqps; i++) { 5130 hns3_fini_ring(&priv->ring[i]); 5131 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]); 5132 } 5133 } 5134 5135 /* Set mac addr if it is configured. or leave it to the AE driver */ 5136 static int hns3_init_mac_addr(struct net_device *netdev) 5137 { 5138 struct hns3_nic_priv *priv = netdev_priv(netdev); 5139 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 5140 struct hnae3_handle *h = priv->ae_handle; 5141 u8 mac_addr_temp[ETH_ALEN] = {0}; 5142 int ret = 0; 5143 5144 if (h->ae_algo->ops->get_mac_addr) 5145 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 5146 5147 /* Check if the MAC address is valid, if not get a random one */ 5148 if (!is_valid_ether_addr(mac_addr_temp)) { 5149 eth_hw_addr_random(netdev); 5150 hnae3_format_mac_addr(format_mac_addr, netdev->dev_addr); 5151 dev_warn(priv->dev, "using random MAC address %s\n", 5152 format_mac_addr); 5153 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) { 5154 eth_hw_addr_set(netdev, mac_addr_temp); 5155 ether_addr_copy(netdev->perm_addr, mac_addr_temp); 5156 } else { 5157 return 0; 5158 } 5159 5160 if (h->ae_algo->ops->set_mac_addr) 5161 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 5162 5163 return ret; 5164 } 5165 5166 static int hns3_init_phy(struct net_device *netdev) 5167 { 5168 struct hnae3_handle *h = hns3_get_handle(netdev); 5169 int ret = 0; 5170 5171 if (h->ae_algo->ops->mac_connect_phy) 5172 ret = h->ae_algo->ops->mac_connect_phy(h); 5173 5174 return ret; 5175 } 5176 5177 static void hns3_uninit_phy(struct net_device *netdev) 5178 { 5179 struct hnae3_handle *h = hns3_get_handle(netdev); 5180 5181 if (h->ae_algo->ops->mac_disconnect_phy) 5182 h->ae_algo->ops->mac_disconnect_phy(h); 5183 } 5184 5185 static int hns3_client_start(struct hnae3_handle *handle) 5186 { 5187 if (!handle->ae_algo->ops->client_start) 5188 return 0; 5189 5190 return handle->ae_algo->ops->client_start(handle); 5191 } 5192 5193 static void hns3_client_stop(struct hnae3_handle *handle) 5194 { 5195 if (!handle->ae_algo->ops->client_stop) 5196 return; 5197 5198 handle->ae_algo->ops->client_stop(handle); 5199 } 5200 5201 static void hns3_info_show(struct hns3_nic_priv *priv) 5202 { 5203 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 5204 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 5205 5206 hnae3_format_mac_addr(format_mac_addr, priv->netdev->dev_addr); 5207 dev_info(priv->dev, "MAC address: %s\n", format_mac_addr); 5208 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps); 5209 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size); 5210 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size); 5211 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len); 5212 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc); 5213 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc); 5214 dev_info(priv->dev, "Total number of enabled TCs: %u\n", 5215 kinfo->tc_info.num_tc); 5216 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu); 5217 } 5218 5219 static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv, 5220 enum dim_cq_period_mode mode, bool is_tx) 5221 { 5222 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 5223 struct hnae3_handle *handle = priv->ae_handle; 5224 int i; 5225 5226 if (is_tx) { 5227 priv->tx_cqe_mode = mode; 5228 5229 for (i = 0; i < priv->vector_num; i++) 5230 priv->tqp_vector[i].tx_group.dim.mode = mode; 5231 } else { 5232 priv->rx_cqe_mode = mode; 5233 5234 for (i = 0; i < priv->vector_num; i++) 5235 priv->tqp_vector[i].rx_group.dim.mode = mode; 5236 } 5237 5238 if (hnae3_ae_dev_cq_supported(ae_dev)) { 5239 u32 new_mode; 5240 u64 reg; 5241 5242 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ? 5243 HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE; 5244 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG; 5245 5246 writel(new_mode, handle->kinfo.io_base + reg); 5247 } 5248 } 5249 5250 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv, 5251 enum dim_cq_period_mode tx_mode, 5252 enum dim_cq_period_mode rx_mode) 5253 { 5254 hns3_set_cq_period_mode(priv, tx_mode, true); 5255 hns3_set_cq_period_mode(priv, rx_mode, false); 5256 } 5257 5258 static void hns3_state_init(struct hnae3_handle *handle) 5259 { 5260 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 5261 struct net_device *netdev = handle->kinfo.netdev; 5262 struct hns3_nic_priv *priv = netdev_priv(netdev); 5263 5264 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 5265 5266 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 5267 set_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state); 5268 5269 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5270 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags); 5271 5272 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) 5273 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state); 5274 5275 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev)) 5276 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state); 5277 } 5278 5279 static void hns3_state_uninit(struct hnae3_handle *handle) 5280 { 5281 struct hns3_nic_priv *priv = handle->priv; 5282 5283 clear_bit(HNS3_NIC_STATE_INITED, &priv->state); 5284 } 5285 5286 static int hns3_client_init(struct hnae3_handle *handle) 5287 { 5288 struct pci_dev *pdev = handle->pdev; 5289 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 5290 u16 alloc_tqps, max_rss_size; 5291 struct hns3_nic_priv *priv; 5292 struct net_device *netdev; 5293 int ret; 5294 5295 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 5296 &max_rss_size); 5297 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 5298 if (!netdev) 5299 return -ENOMEM; 5300 5301 priv = netdev_priv(netdev); 5302 priv->dev = &pdev->dev; 5303 priv->netdev = netdev; 5304 priv->ae_handle = handle; 5305 priv->tx_timeout_count = 0; 5306 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num; 5307 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 5308 5309 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL); 5310 5311 handle->kinfo.netdev = netdev; 5312 handle->priv = (void *)priv; 5313 5314 hns3_init_mac_addr(netdev); 5315 5316 hns3_set_default_feature(netdev); 5317 5318 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 5319 netdev->priv_flags |= IFF_UNICAST_FLT; 5320 netdev->netdev_ops = &hns3_nic_netdev_ops; 5321 SET_NETDEV_DEV(netdev, &pdev->dev); 5322 hns3_ethtool_set_ops(netdev); 5323 5324 /* Carrier off reporting is important to ethtool even BEFORE open */ 5325 netif_carrier_off(netdev); 5326 5327 ret = hns3_get_ring_config(priv); 5328 if (ret) { 5329 ret = -ENOMEM; 5330 goto out_get_ring_cfg; 5331 } 5332 5333 hns3_nic_init_coal_cfg(priv); 5334 5335 ret = hns3_nic_alloc_vector_data(priv); 5336 if (ret) { 5337 ret = -ENOMEM; 5338 goto out_alloc_vector_data; 5339 } 5340 5341 ret = hns3_nic_init_vector_data(priv); 5342 if (ret) { 5343 ret = -ENOMEM; 5344 goto out_init_vector_data; 5345 } 5346 5347 ret = hns3_init_all_ring(priv); 5348 if (ret) { 5349 ret = -ENOMEM; 5350 goto out_init_ring; 5351 } 5352 5353 hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE, 5354 DIM_CQ_PERIOD_MODE_START_FROM_EQE); 5355 5356 ret = hns3_init_phy(netdev); 5357 if (ret) 5358 goto out_init_phy; 5359 5360 /* the device can work without cpu rmap, only aRFS needs it */ 5361 ret = hns3_set_rx_cpu_rmap(netdev); 5362 if (ret) 5363 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 5364 5365 ret = hns3_nic_init_irq(priv); 5366 if (ret) { 5367 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 5368 hns3_free_rx_cpu_rmap(netdev); 5369 goto out_init_irq_fail; 5370 } 5371 5372 ret = hns3_client_start(handle); 5373 if (ret) { 5374 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 5375 goto out_client_start; 5376 } 5377 5378 hns3_dcbnl_setup(handle); 5379 5380 ret = hns3_dbg_init(handle); 5381 if (ret) { 5382 dev_err(priv->dev, "failed to init debugfs, ret = %d\n", 5383 ret); 5384 goto out_client_start; 5385 } 5386 5387 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size); 5388 5389 hns3_state_init(handle); 5390 5391 ret = register_netdev(netdev); 5392 if (ret) { 5393 dev_err(priv->dev, "probe register netdev fail!\n"); 5394 goto out_reg_netdev_fail; 5395 } 5396 5397 if (netif_msg_drv(handle)) 5398 hns3_info_show(priv); 5399 5400 return ret; 5401 5402 out_reg_netdev_fail: 5403 hns3_state_uninit(handle); 5404 hns3_dbg_uninit(handle); 5405 hns3_client_stop(handle); 5406 out_client_start: 5407 hns3_free_rx_cpu_rmap(netdev); 5408 hns3_nic_uninit_irq(priv); 5409 out_init_irq_fail: 5410 hns3_uninit_phy(netdev); 5411 out_init_phy: 5412 hns3_uninit_all_ring(priv); 5413 out_init_ring: 5414 hns3_nic_uninit_vector_data(priv); 5415 out_init_vector_data: 5416 hns3_nic_dealloc_vector_data(priv); 5417 out_alloc_vector_data: 5418 priv->ring = NULL; 5419 out_get_ring_cfg: 5420 priv->ae_handle = NULL; 5421 free_netdev(netdev); 5422 return ret; 5423 } 5424 5425 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 5426 { 5427 struct net_device *netdev = handle->kinfo.netdev; 5428 struct hns3_nic_priv *priv = netdev_priv(netdev); 5429 5430 if (netdev->reg_state != NETREG_UNINITIALIZED) 5431 unregister_netdev(netdev); 5432 5433 hns3_client_stop(handle); 5434 5435 hns3_uninit_phy(netdev); 5436 5437 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 5438 netdev_warn(netdev, "already uninitialized\n"); 5439 goto out_netdev_free; 5440 } 5441 5442 hns3_free_rx_cpu_rmap(netdev); 5443 5444 hns3_nic_uninit_irq(priv); 5445 5446 hns3_clear_all_ring(handle, true); 5447 5448 hns3_nic_uninit_vector_data(priv); 5449 5450 hns3_nic_dealloc_vector_data(priv); 5451 5452 hns3_uninit_all_ring(priv); 5453 5454 hns3_put_ring_config(priv); 5455 5456 out_netdev_free: 5457 hns3_dbg_uninit(handle); 5458 free_netdev(netdev); 5459 } 5460 5461 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 5462 { 5463 struct net_device *netdev = handle->kinfo.netdev; 5464 5465 if (!netdev) 5466 return; 5467 5468 if (linkup) { 5469 netif_tx_wake_all_queues(netdev); 5470 netif_carrier_on(netdev); 5471 if (netif_msg_link(handle)) 5472 netdev_info(netdev, "link up\n"); 5473 } else { 5474 netif_carrier_off(netdev); 5475 netif_tx_stop_all_queues(netdev); 5476 if (netif_msg_link(handle)) 5477 netdev_info(netdev, "link down\n"); 5478 } 5479 } 5480 5481 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 5482 { 5483 while (ring->next_to_clean != ring->next_to_use) { 5484 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 5485 hns3_free_buffer_detach(ring, ring->next_to_clean, 0); 5486 ring_ptr_move_fw(ring, next_to_clean); 5487 } 5488 5489 ring->pending_buf = 0; 5490 } 5491 5492 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 5493 { 5494 struct hns3_desc_cb res_cbs; 5495 int ret; 5496 5497 while (ring->next_to_use != ring->next_to_clean) { 5498 /* When a buffer is not reused, it's memory has been 5499 * freed in hns3_handle_rx_bd or will be freed by 5500 * stack, so we need to replace the buffer here. 5501 */ 5502 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 5503 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 5504 if (ret) { 5505 hns3_ring_stats_update(ring, sw_err_cnt); 5506 /* if alloc new buffer fail, exit directly 5507 * and reclear in up flow. 5508 */ 5509 netdev_warn(ring_to_netdev(ring), 5510 "reserve buffer map failed, ret = %d\n", 5511 ret); 5512 return ret; 5513 } 5514 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 5515 } 5516 ring_ptr_move_fw(ring, next_to_use); 5517 } 5518 5519 /* Free the pending skb in rx ring */ 5520 if (ring->skb) { 5521 dev_kfree_skb_any(ring->skb); 5522 ring->skb = NULL; 5523 ring->pending_buf = 0; 5524 } 5525 5526 return 0; 5527 } 5528 5529 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 5530 { 5531 while (ring->next_to_use != ring->next_to_clean) { 5532 /* When a buffer is not reused, it's memory has been 5533 * freed in hns3_handle_rx_bd or will be freed by 5534 * stack, so only need to unmap the buffer here. 5535 */ 5536 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 5537 hns3_unmap_buffer(ring, 5538 &ring->desc_cb[ring->next_to_use]); 5539 ring->desc_cb[ring->next_to_use].dma = 0; 5540 } 5541 5542 ring_ptr_move_fw(ring, next_to_use); 5543 } 5544 } 5545 5546 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force) 5547 { 5548 struct net_device *ndev = h->kinfo.netdev; 5549 struct hns3_nic_priv *priv = netdev_priv(ndev); 5550 u32 i; 5551 5552 for (i = 0; i < h->kinfo.num_tqps; i++) { 5553 struct hns3_enet_ring *ring; 5554 5555 ring = &priv->ring[i]; 5556 hns3_clear_tx_ring(ring); 5557 5558 ring = &priv->ring[i + h->kinfo.num_tqps]; 5559 /* Continue to clear other rings even if clearing some 5560 * rings failed. 5561 */ 5562 if (force) 5563 hns3_force_clear_rx_ring(ring); 5564 else 5565 hns3_clear_rx_ring(ring); 5566 } 5567 } 5568 5569 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 5570 { 5571 struct net_device *ndev = h->kinfo.netdev; 5572 struct hns3_nic_priv *priv = netdev_priv(ndev); 5573 struct hns3_enet_ring *rx_ring; 5574 int i, j; 5575 int ret; 5576 5577 ret = h->ae_algo->ops->reset_queue(h); 5578 if (ret) 5579 return ret; 5580 5581 for (i = 0; i < h->kinfo.num_tqps; i++) { 5582 hns3_init_ring_hw(&priv->ring[i]); 5583 5584 /* We need to clear tx ring here because self test will 5585 * use the ring and will not run down before up 5586 */ 5587 hns3_clear_tx_ring(&priv->ring[i]); 5588 priv->ring[i].next_to_clean = 0; 5589 priv->ring[i].next_to_use = 0; 5590 priv->ring[i].last_to_use = 0; 5591 5592 rx_ring = &priv->ring[i + h->kinfo.num_tqps]; 5593 hns3_init_ring_hw(rx_ring); 5594 ret = hns3_clear_rx_ring(rx_ring); 5595 if (ret) 5596 return ret; 5597 5598 /* We can not know the hardware head and tail when this 5599 * function is called in reset flow, so we reuse all desc. 5600 */ 5601 for (j = 0; j < rx_ring->desc_num; j++) 5602 hns3_reuse_buffer(rx_ring, j); 5603 5604 rx_ring->next_to_clean = 0; 5605 rx_ring->next_to_use = 0; 5606 } 5607 5608 hns3_init_tx_ring_tc(priv); 5609 5610 return 0; 5611 } 5612 5613 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 5614 { 5615 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 5616 struct net_device *ndev = kinfo->netdev; 5617 struct hns3_nic_priv *priv = netdev_priv(ndev); 5618 5619 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 5620 return 0; 5621 5622 if (!netif_running(ndev)) 5623 return 0; 5624 5625 return hns3_nic_net_stop(ndev); 5626 } 5627 5628 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 5629 { 5630 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 5631 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 5632 int ret = 0; 5633 5634 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 5635 netdev_err(kinfo->netdev, "device is not initialized yet\n"); 5636 return -EFAULT; 5637 } 5638 5639 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 5640 5641 if (netif_running(kinfo->netdev)) { 5642 ret = hns3_nic_net_open(kinfo->netdev); 5643 if (ret) { 5644 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 5645 netdev_err(kinfo->netdev, 5646 "net up fail, ret=%d!\n", ret); 5647 return ret; 5648 } 5649 } 5650 5651 return ret; 5652 } 5653 5654 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 5655 { 5656 struct net_device *netdev = handle->kinfo.netdev; 5657 struct hns3_nic_priv *priv = netdev_priv(netdev); 5658 int ret; 5659 5660 /* Carrier off reporting is important to ethtool even BEFORE open */ 5661 netif_carrier_off(netdev); 5662 5663 ret = hns3_get_ring_config(priv); 5664 if (ret) 5665 return ret; 5666 5667 ret = hns3_nic_alloc_vector_data(priv); 5668 if (ret) 5669 goto err_put_ring; 5670 5671 ret = hns3_nic_init_vector_data(priv); 5672 if (ret) 5673 goto err_dealloc_vector; 5674 5675 ret = hns3_init_all_ring(priv); 5676 if (ret) 5677 goto err_uninit_vector; 5678 5679 hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode); 5680 5681 /* the device can work without cpu rmap, only aRFS needs it */ 5682 ret = hns3_set_rx_cpu_rmap(netdev); 5683 if (ret) 5684 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 5685 5686 ret = hns3_nic_init_irq(priv); 5687 if (ret) { 5688 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 5689 hns3_free_rx_cpu_rmap(netdev); 5690 goto err_init_irq_fail; 5691 } 5692 5693 if (!hns3_is_phys_func(handle->pdev)) 5694 hns3_init_mac_addr(netdev); 5695 5696 ret = hns3_client_start(handle); 5697 if (ret) { 5698 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 5699 goto err_client_start_fail; 5700 } 5701 5702 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 5703 5704 return ret; 5705 5706 err_client_start_fail: 5707 hns3_free_rx_cpu_rmap(netdev); 5708 hns3_nic_uninit_irq(priv); 5709 err_init_irq_fail: 5710 hns3_uninit_all_ring(priv); 5711 err_uninit_vector: 5712 hns3_nic_uninit_vector_data(priv); 5713 err_dealloc_vector: 5714 hns3_nic_dealloc_vector_data(priv); 5715 err_put_ring: 5716 hns3_put_ring_config(priv); 5717 5718 return ret; 5719 } 5720 5721 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 5722 { 5723 struct net_device *netdev = handle->kinfo.netdev; 5724 struct hns3_nic_priv *priv = netdev_priv(netdev); 5725 5726 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 5727 hns3_nic_net_stop(netdev); 5728 5729 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 5730 netdev_warn(netdev, "already uninitialized\n"); 5731 return 0; 5732 } 5733 5734 hns3_free_rx_cpu_rmap(netdev); 5735 hns3_nic_uninit_irq(priv); 5736 hns3_clear_all_ring(handle, true); 5737 hns3_reset_tx_queue(priv->ae_handle); 5738 5739 hns3_nic_uninit_vector_data(priv); 5740 5741 hns3_nic_dealloc_vector_data(priv); 5742 5743 hns3_uninit_all_ring(priv); 5744 5745 hns3_put_ring_config(priv); 5746 5747 return 0; 5748 } 5749 5750 int hns3_reset_notify(struct hnae3_handle *handle, 5751 enum hnae3_reset_notify_type type) 5752 { 5753 int ret = 0; 5754 5755 switch (type) { 5756 case HNAE3_UP_CLIENT: 5757 ret = hns3_reset_notify_up_enet(handle); 5758 break; 5759 case HNAE3_DOWN_CLIENT: 5760 ret = hns3_reset_notify_down_enet(handle); 5761 break; 5762 case HNAE3_INIT_CLIENT: 5763 ret = hns3_reset_notify_init_enet(handle); 5764 break; 5765 case HNAE3_UNINIT_CLIENT: 5766 ret = hns3_reset_notify_uninit_enet(handle); 5767 break; 5768 default: 5769 break; 5770 } 5771 5772 return ret; 5773 } 5774 5775 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num, 5776 bool rxfh_configured) 5777 { 5778 int ret; 5779 5780 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num, 5781 rxfh_configured); 5782 if (ret) { 5783 dev_err(&handle->pdev->dev, 5784 "Change tqp num(%u) fail.\n", new_tqp_num); 5785 return ret; 5786 } 5787 5788 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT); 5789 if (ret) 5790 return ret; 5791 5792 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT); 5793 if (ret) 5794 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT); 5795 5796 return ret; 5797 } 5798 5799 int hns3_set_channels(struct net_device *netdev, 5800 struct ethtool_channels *ch) 5801 { 5802 struct hnae3_handle *h = hns3_get_handle(netdev); 5803 struct hnae3_knic_private_info *kinfo = &h->kinfo; 5804 bool rxfh_configured = netif_is_rxfh_configured(netdev); 5805 u32 new_tqp_num = ch->combined_count; 5806 u16 org_tqp_num; 5807 int ret; 5808 5809 if (hns3_nic_resetting(netdev)) 5810 return -EBUSY; 5811 5812 if (ch->rx_count || ch->tx_count) 5813 return -EINVAL; 5814 5815 if (kinfo->tc_info.mqprio_active) { 5816 dev_err(&netdev->dev, 5817 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n"); 5818 return -EINVAL; 5819 } 5820 5821 if (new_tqp_num > hns3_get_max_available_channels(h) || 5822 new_tqp_num < 1) { 5823 dev_err(&netdev->dev, 5824 "Change tqps fail, the tqp range is from 1 to %u", 5825 hns3_get_max_available_channels(h)); 5826 return -EINVAL; 5827 } 5828 5829 if (kinfo->rss_size == new_tqp_num) 5830 return 0; 5831 5832 netif_dbg(h, drv, netdev, 5833 "set channels: tqp_num=%u, rxfh=%d\n", 5834 new_tqp_num, rxfh_configured); 5835 5836 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 5837 if (ret) 5838 return ret; 5839 5840 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 5841 if (ret) 5842 return ret; 5843 5844 org_tqp_num = h->kinfo.num_tqps; 5845 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured); 5846 if (ret) { 5847 int ret1; 5848 5849 netdev_warn(netdev, 5850 "Change channels fail, revert to old value\n"); 5851 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured); 5852 if (ret1) { 5853 netdev_err(netdev, 5854 "revert to old channel fail\n"); 5855 return ret1; 5856 } 5857 5858 return ret; 5859 } 5860 5861 return 0; 5862 } 5863 5864 void hns3_external_lb_prepare(struct net_device *ndev, bool if_running) 5865 { 5866 struct hns3_nic_priv *priv = netdev_priv(ndev); 5867 struct hnae3_handle *h = priv->ae_handle; 5868 int i; 5869 5870 if (!if_running) 5871 return; 5872 5873 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 5874 return; 5875 5876 netif_carrier_off(ndev); 5877 netif_tx_disable(ndev); 5878 5879 for (i = 0; i < priv->vector_num; i++) 5880 hns3_vector_disable(&priv->tqp_vector[i]); 5881 5882 for (i = 0; i < h->kinfo.num_tqps; i++) 5883 hns3_tqp_disable(h->kinfo.tqp[i]); 5884 5885 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 5886 * during reset process, because driver may not be able 5887 * to disable the ring through firmware when downing the netdev. 5888 */ 5889 if (!hns3_nic_resetting(ndev)) 5890 hns3_nic_reset_all_ring(priv->ae_handle); 5891 5892 hns3_reset_tx_queue(priv->ae_handle); 5893 } 5894 5895 void hns3_external_lb_restore(struct net_device *ndev, bool if_running) 5896 { 5897 struct hns3_nic_priv *priv = netdev_priv(ndev); 5898 struct hnae3_handle *h = priv->ae_handle; 5899 int i; 5900 5901 if (!if_running) 5902 return; 5903 5904 if (hns3_nic_resetting(ndev)) 5905 return; 5906 5907 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 5908 return; 5909 5910 if (hns3_nic_reset_all_ring(priv->ae_handle)) 5911 return; 5912 5913 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 5914 5915 for (i = 0; i < priv->vector_num; i++) 5916 hns3_vector_enable(&priv->tqp_vector[i]); 5917 5918 for (i = 0; i < h->kinfo.num_tqps; i++) 5919 hns3_tqp_enable(h->kinfo.tqp[i]); 5920 5921 netif_tx_wake_all_queues(ndev); 5922 5923 if (h->ae_algo->ops->get_status(h)) 5924 netif_carrier_on(ndev); 5925 } 5926 5927 static const struct hns3_hw_error_info hns3_hw_err[] = { 5928 { .type = HNAE3_PPU_POISON_ERROR, 5929 .msg = "PPU poison" }, 5930 { .type = HNAE3_CMDQ_ECC_ERROR, 5931 .msg = "IMP CMDQ error" }, 5932 { .type = HNAE3_IMP_RD_POISON_ERROR, 5933 .msg = "IMP RD poison" }, 5934 { .type = HNAE3_ROCEE_AXI_RESP_ERROR, 5935 .msg = "ROCEE AXI RESP error" }, 5936 }; 5937 5938 static void hns3_process_hw_error(struct hnae3_handle *handle, 5939 enum hnae3_hw_error_type type) 5940 { 5941 int i; 5942 5943 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) { 5944 if (hns3_hw_err[i].type == type) { 5945 dev_err(&handle->pdev->dev, "Detected %s!\n", 5946 hns3_hw_err[i].msg); 5947 break; 5948 } 5949 } 5950 } 5951 5952 static const struct hnae3_client_ops client_ops = { 5953 .init_instance = hns3_client_init, 5954 .uninit_instance = hns3_client_uninit, 5955 .link_status_change = hns3_link_status_change, 5956 .reset_notify = hns3_reset_notify, 5957 .process_hw_error = hns3_process_hw_error, 5958 }; 5959 5960 /* hns3_init_module - Driver registration routine 5961 * hns3_init_module is the first routine called when the driver is 5962 * loaded. All it does is register with the PCI subsystem. 5963 */ 5964 static int __init hns3_init_module(void) 5965 { 5966 int ret; 5967 5968 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 5969 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 5970 5971 client.type = HNAE3_CLIENT_KNIC; 5972 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s", 5973 hns3_driver_name); 5974 5975 client.ops = &client_ops; 5976 5977 INIT_LIST_HEAD(&client.node); 5978 5979 hns3_dbg_register_debugfs(hns3_driver_name); 5980 5981 ret = hnae3_register_client(&client); 5982 if (ret) 5983 goto err_reg_client; 5984 5985 ret = pci_register_driver(&hns3_driver); 5986 if (ret) 5987 goto err_reg_driver; 5988 5989 return ret; 5990 5991 err_reg_driver: 5992 hnae3_unregister_client(&client); 5993 err_reg_client: 5994 hns3_dbg_unregister_debugfs(); 5995 return ret; 5996 } 5997 module_init(hns3_init_module); 5998 5999 /* hns3_exit_module - Driver exit cleanup routine 6000 * hns3_exit_module is called just before the driver is removed 6001 * from memory. 6002 */ 6003 static void __exit hns3_exit_module(void) 6004 { 6005 pci_unregister_driver(&hns3_driver); 6006 hnae3_unregister_client(&client); 6007 hns3_dbg_unregister_debugfs(); 6008 } 6009 module_exit(hns3_exit_module); 6010 6011 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 6012 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 6013 MODULE_LICENSE("GPL"); 6014 MODULE_ALIAS("pci:hns-nic"); 6015