1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #ifdef CONFIG_RFS_ACCEL 8 #include <linux/cpu_rmap.h> 9 #endif 10 #include <linux/if_vlan.h> 11 #include <linux/ip.h> 12 #include <linux/ipv6.h> 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/aer.h> 16 #include <linux/skbuff.h> 17 #include <linux/sctp.h> 18 #include <linux/vermagic.h> 19 #include <net/gre.h> 20 #include <net/ip6_checksum.h> 21 #include <net/pkt_cls.h> 22 #include <net/tcp.h> 23 #include <net/vxlan.h> 24 25 #include "hnae3.h" 26 #include "hns3_enet.h" 27 28 #define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift))) 29 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE) 30 31 static void hns3_clear_all_ring(struct hnae3_handle *h); 32 static void hns3_force_clear_all_ring(struct hnae3_handle *h); 33 static void hns3_remove_hw_addr(struct net_device *netdev); 34 35 static const char hns3_driver_name[] = "hns3"; 36 const char hns3_driver_version[] = VERMAGIC_STRING; 37 static const char hns3_driver_string[] = 38 "Hisilicon Ethernet Network Driver for Hip08 Family"; 39 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 40 static struct hnae3_client client; 41 42 static int debug = -1; 43 module_param(debug, int, 0); 44 MODULE_PARM_DESC(debug, " Network interface message level setting"); 45 46 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 47 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) 48 49 /* hns3_pci_tbl - PCI Device ID Table 50 * 51 * Last entry must be all 0s 52 * 53 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 54 * Class, Class Mask, private data (not used) } 55 */ 56 static const struct pci_device_id hns3_pci_tbl[] = { 57 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 58 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 59 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 60 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 61 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 62 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 63 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 64 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 65 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 66 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 67 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 68 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 69 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 70 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 71 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 72 /* required last entry */ 73 {0, } 74 }; 75 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 76 77 static irqreturn_t hns3_irq_handle(int irq, void *vector) 78 { 79 struct hns3_enet_tqp_vector *tqp_vector = vector; 80 81 napi_schedule_irqoff(&tqp_vector->napi); 82 83 return IRQ_HANDLED; 84 } 85 86 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 87 { 88 struct hns3_enet_tqp_vector *tqp_vectors; 89 unsigned int i; 90 91 for (i = 0; i < priv->vector_num; i++) { 92 tqp_vectors = &priv->tqp_vector[i]; 93 94 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 95 continue; 96 97 /* clear the affinity mask */ 98 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 99 100 /* release the irq resource */ 101 free_irq(tqp_vectors->vector_irq, tqp_vectors); 102 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 103 } 104 } 105 106 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 107 { 108 struct hns3_enet_tqp_vector *tqp_vectors; 109 int txrx_int_idx = 0; 110 int rx_int_idx = 0; 111 int tx_int_idx = 0; 112 unsigned int i; 113 int ret; 114 115 for (i = 0; i < priv->vector_num; i++) { 116 tqp_vectors = &priv->tqp_vector[i]; 117 118 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 119 continue; 120 121 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 122 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 123 "%s-%s-%d", priv->netdev->name, "TxRx", 124 txrx_int_idx++); 125 txrx_int_idx++; 126 } else if (tqp_vectors->rx_group.ring) { 127 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 128 "%s-%s-%d", priv->netdev->name, "Rx", 129 rx_int_idx++); 130 } else if (tqp_vectors->tx_group.ring) { 131 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 132 "%s-%s-%d", priv->netdev->name, "Tx", 133 tx_int_idx++); 134 } else { 135 /* Skip this unused q_vector */ 136 continue; 137 } 138 139 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 140 141 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 142 tqp_vectors->name, tqp_vectors); 143 if (ret) { 144 netdev_err(priv->netdev, "request irq(%d) fail\n", 145 tqp_vectors->vector_irq); 146 hns3_nic_uninit_irq(priv); 147 return ret; 148 } 149 150 irq_set_affinity_hint(tqp_vectors->vector_irq, 151 &tqp_vectors->affinity_mask); 152 153 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 154 } 155 156 return 0; 157 } 158 159 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 160 u32 mask_en) 161 { 162 writel(mask_en, tqp_vector->mask_addr); 163 } 164 165 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 166 { 167 napi_enable(&tqp_vector->napi); 168 169 /* enable vector */ 170 hns3_mask_vector_irq(tqp_vector, 1); 171 } 172 173 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 174 { 175 /* disable vector */ 176 hns3_mask_vector_irq(tqp_vector, 0); 177 178 disable_irq(tqp_vector->vector_irq); 179 napi_disable(&tqp_vector->napi); 180 } 181 182 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 183 u32 rl_value) 184 { 185 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 186 187 /* this defines the configuration for RL (Interrupt Rate Limiter). 188 * Rl defines rate of interrupts i.e. number of interrupts-per-second 189 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 190 */ 191 192 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable && 193 !tqp_vector->rx_group.coal.gl_adapt_enable) 194 /* According to the hardware, the range of rl_reg is 195 * 0-59 and the unit is 4. 196 */ 197 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 198 199 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 200 } 201 202 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 203 u32 gl_value) 204 { 205 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value); 206 207 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 208 } 209 210 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 211 u32 gl_value) 212 { 213 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value); 214 215 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 216 } 217 218 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector, 219 struct hns3_nic_priv *priv) 220 { 221 /* initialize the configuration for interrupt coalescing. 222 * 1. GL (Interrupt Gap Limiter) 223 * 2. RL (Interrupt Rate Limiter) 224 */ 225 226 /* Default: enable interrupt coalescing self-adaptive and GL */ 227 tqp_vector->tx_group.coal.gl_adapt_enable = 1; 228 tqp_vector->rx_group.coal.gl_adapt_enable = 1; 229 230 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K; 231 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K; 232 233 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW; 234 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW; 235 } 236 237 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 238 struct hns3_nic_priv *priv) 239 { 240 struct hnae3_handle *h = priv->ae_handle; 241 242 hns3_set_vector_coalesce_tx_gl(tqp_vector, 243 tqp_vector->tx_group.coal.int_gl); 244 hns3_set_vector_coalesce_rx_gl(tqp_vector, 245 tqp_vector->rx_group.coal.int_gl); 246 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 247 } 248 249 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 250 { 251 struct hnae3_handle *h = hns3_get_handle(netdev); 252 struct hnae3_knic_private_info *kinfo = &h->kinfo; 253 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc; 254 int i, ret; 255 256 if (kinfo->num_tc <= 1) { 257 netdev_reset_tc(netdev); 258 } else { 259 ret = netdev_set_num_tc(netdev, kinfo->num_tc); 260 if (ret) { 261 netdev_err(netdev, 262 "netdev_set_num_tc fail, ret=%d!\n", ret); 263 return ret; 264 } 265 266 for (i = 0; i < HNAE3_MAX_TC; i++) { 267 if (!kinfo->tc_info[i].enable) 268 continue; 269 270 netdev_set_tc_queue(netdev, 271 kinfo->tc_info[i].tc, 272 kinfo->tc_info[i].tqp_count, 273 kinfo->tc_info[i].tqp_offset); 274 } 275 } 276 277 ret = netif_set_real_num_tx_queues(netdev, queue_size); 278 if (ret) { 279 netdev_err(netdev, 280 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret); 281 return ret; 282 } 283 284 ret = netif_set_real_num_rx_queues(netdev, queue_size); 285 if (ret) { 286 netdev_err(netdev, 287 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 288 return ret; 289 } 290 291 return 0; 292 } 293 294 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 295 { 296 u16 alloc_tqps, max_rss_size, rss_size; 297 298 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 299 rss_size = alloc_tqps / h->kinfo.num_tc; 300 301 return min_t(u16, rss_size, max_rss_size); 302 } 303 304 static void hns3_tqp_enable(struct hnae3_queue *tqp) 305 { 306 u32 rcb_reg; 307 308 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 309 rcb_reg |= BIT(HNS3_RING_EN_B); 310 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 311 } 312 313 static void hns3_tqp_disable(struct hnae3_queue *tqp) 314 { 315 u32 rcb_reg; 316 317 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 318 rcb_reg &= ~BIT(HNS3_RING_EN_B); 319 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 320 } 321 322 static void hns3_free_rx_cpu_rmap(struct net_device *netdev) 323 { 324 #ifdef CONFIG_RFS_ACCEL 325 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 326 netdev->rx_cpu_rmap = NULL; 327 #endif 328 } 329 330 static int hns3_set_rx_cpu_rmap(struct net_device *netdev) 331 { 332 #ifdef CONFIG_RFS_ACCEL 333 struct hns3_nic_priv *priv = netdev_priv(netdev); 334 struct hns3_enet_tqp_vector *tqp_vector; 335 int i, ret; 336 337 if (!netdev->rx_cpu_rmap) { 338 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num); 339 if (!netdev->rx_cpu_rmap) 340 return -ENOMEM; 341 } 342 343 for (i = 0; i < priv->vector_num; i++) { 344 tqp_vector = &priv->tqp_vector[i]; 345 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap, 346 tqp_vector->vector_irq); 347 if (ret) { 348 hns3_free_rx_cpu_rmap(netdev); 349 return ret; 350 } 351 } 352 #endif 353 return 0; 354 } 355 356 static int hns3_nic_net_up(struct net_device *netdev) 357 { 358 struct hns3_nic_priv *priv = netdev_priv(netdev); 359 struct hnae3_handle *h = priv->ae_handle; 360 int i, j; 361 int ret; 362 363 ret = hns3_nic_reset_all_ring(h); 364 if (ret) 365 return ret; 366 367 /* the device can work without cpu rmap, only aRFS needs it */ 368 ret = hns3_set_rx_cpu_rmap(netdev); 369 if (ret) 370 netdev_warn(netdev, "set rx cpu rmap fail, ret=%d!\n", ret); 371 372 /* get irq resource for all vectors */ 373 ret = hns3_nic_init_irq(priv); 374 if (ret) { 375 netdev_err(netdev, "init irq failed! ret=%d\n", ret); 376 goto free_rmap; 377 } 378 379 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 380 381 /* enable the vectors */ 382 for (i = 0; i < priv->vector_num; i++) 383 hns3_vector_enable(&priv->tqp_vector[i]); 384 385 /* enable rcb */ 386 for (j = 0; j < h->kinfo.num_tqps; j++) 387 hns3_tqp_enable(h->kinfo.tqp[j]); 388 389 /* start the ae_dev */ 390 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 391 if (ret) 392 goto out_start_err; 393 394 return 0; 395 396 out_start_err: 397 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 398 while (j--) 399 hns3_tqp_disable(h->kinfo.tqp[j]); 400 401 for (j = i - 1; j >= 0; j--) 402 hns3_vector_disable(&priv->tqp_vector[j]); 403 404 hns3_nic_uninit_irq(priv); 405 free_rmap: 406 hns3_free_rx_cpu_rmap(netdev); 407 return ret; 408 } 409 410 static void hns3_config_xps(struct hns3_nic_priv *priv) 411 { 412 int i; 413 414 for (i = 0; i < priv->vector_num; i++) { 415 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 416 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 417 418 while (ring) { 419 int ret; 420 421 ret = netif_set_xps_queue(priv->netdev, 422 &tqp_vector->affinity_mask, 423 ring->tqp->tqp_index); 424 if (ret) 425 netdev_warn(priv->netdev, 426 "set xps queue failed: %d", ret); 427 428 ring = ring->next; 429 } 430 } 431 } 432 433 static int hns3_nic_net_open(struct net_device *netdev) 434 { 435 struct hns3_nic_priv *priv = netdev_priv(netdev); 436 struct hnae3_handle *h = hns3_get_handle(netdev); 437 struct hnae3_knic_private_info *kinfo; 438 int i, ret; 439 440 if (hns3_nic_resetting(netdev)) 441 return -EBUSY; 442 443 netif_carrier_off(netdev); 444 445 ret = hns3_nic_set_real_num_queue(netdev); 446 if (ret) 447 return ret; 448 449 ret = hns3_nic_net_up(netdev); 450 if (ret) { 451 netdev_err(netdev, "net up fail, ret=%d!\n", ret); 452 return ret; 453 } 454 455 kinfo = &h->kinfo; 456 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 457 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]); 458 459 if (h->ae_algo->ops->set_timer_task) 460 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 461 462 hns3_config_xps(priv); 463 return 0; 464 } 465 466 static void hns3_nic_net_down(struct net_device *netdev) 467 { 468 struct hns3_nic_priv *priv = netdev_priv(netdev); 469 struct hnae3_handle *h = hns3_get_handle(netdev); 470 const struct hnae3_ae_ops *ops; 471 int i; 472 473 /* disable vectors */ 474 for (i = 0; i < priv->vector_num; i++) 475 hns3_vector_disable(&priv->tqp_vector[i]); 476 477 /* disable rcb */ 478 for (i = 0; i < h->kinfo.num_tqps; i++) 479 hns3_tqp_disable(h->kinfo.tqp[i]); 480 481 /* stop ae_dev */ 482 ops = priv->ae_handle->ae_algo->ops; 483 if (ops->stop) 484 ops->stop(priv->ae_handle); 485 486 hns3_free_rx_cpu_rmap(netdev); 487 488 /* free irq resources */ 489 hns3_nic_uninit_irq(priv); 490 491 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 492 * during reset process, because driver may not be able 493 * to disable the ring through firmware when downing the netdev. 494 */ 495 if (!hns3_nic_resetting(netdev)) 496 hns3_clear_all_ring(priv->ae_handle); 497 } 498 499 static int hns3_nic_net_stop(struct net_device *netdev) 500 { 501 struct hns3_nic_priv *priv = netdev_priv(netdev); 502 struct hnae3_handle *h = hns3_get_handle(netdev); 503 504 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 505 return 0; 506 507 if (h->ae_algo->ops->set_timer_task) 508 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 509 510 netif_tx_stop_all_queues(netdev); 511 netif_carrier_off(netdev); 512 513 hns3_nic_net_down(netdev); 514 515 return 0; 516 } 517 518 static int hns3_nic_uc_sync(struct net_device *netdev, 519 const unsigned char *addr) 520 { 521 struct hnae3_handle *h = hns3_get_handle(netdev); 522 523 if (h->ae_algo->ops->add_uc_addr) 524 return h->ae_algo->ops->add_uc_addr(h, addr); 525 526 return 0; 527 } 528 529 static int hns3_nic_uc_unsync(struct net_device *netdev, 530 const unsigned char *addr) 531 { 532 struct hnae3_handle *h = hns3_get_handle(netdev); 533 534 if (h->ae_algo->ops->rm_uc_addr) 535 return h->ae_algo->ops->rm_uc_addr(h, addr); 536 537 return 0; 538 } 539 540 static int hns3_nic_mc_sync(struct net_device *netdev, 541 const unsigned char *addr) 542 { 543 struct hnae3_handle *h = hns3_get_handle(netdev); 544 545 if (h->ae_algo->ops->add_mc_addr) 546 return h->ae_algo->ops->add_mc_addr(h, addr); 547 548 return 0; 549 } 550 551 static int hns3_nic_mc_unsync(struct net_device *netdev, 552 const unsigned char *addr) 553 { 554 struct hnae3_handle *h = hns3_get_handle(netdev); 555 556 if (h->ae_algo->ops->rm_mc_addr) 557 return h->ae_algo->ops->rm_mc_addr(h, addr); 558 559 return 0; 560 } 561 562 static u8 hns3_get_netdev_flags(struct net_device *netdev) 563 { 564 u8 flags = 0; 565 566 if (netdev->flags & IFF_PROMISC) { 567 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 568 } else { 569 flags |= HNAE3_VLAN_FLTR; 570 if (netdev->flags & IFF_ALLMULTI) 571 flags |= HNAE3_USER_MPE; 572 } 573 574 return flags; 575 } 576 577 static void hns3_nic_set_rx_mode(struct net_device *netdev) 578 { 579 struct hnae3_handle *h = hns3_get_handle(netdev); 580 u8 new_flags; 581 int ret; 582 583 new_flags = hns3_get_netdev_flags(netdev); 584 585 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 586 if (ret) { 587 netdev_err(netdev, "sync uc address fail\n"); 588 if (ret == -ENOSPC) 589 new_flags |= HNAE3_OVERFLOW_UPE; 590 } 591 592 if (netdev->flags & IFF_MULTICAST) { 593 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync, 594 hns3_nic_mc_unsync); 595 if (ret) { 596 netdev_err(netdev, "sync mc address fail\n"); 597 if (ret == -ENOSPC) 598 new_flags |= HNAE3_OVERFLOW_MPE; 599 } 600 } 601 602 /* User mode Promisc mode enable and vlan filtering is disabled to 603 * let all packets in. MAC-VLAN Table overflow Promisc enabled and 604 * vlan fitering is enabled 605 */ 606 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR); 607 h->netdev_flags = new_flags; 608 hns3_update_promisc_mode(netdev, new_flags); 609 } 610 611 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags) 612 { 613 struct hns3_nic_priv *priv = netdev_priv(netdev); 614 struct hnae3_handle *h = priv->ae_handle; 615 616 if (h->ae_algo->ops->set_promisc_mode) { 617 return h->ae_algo->ops->set_promisc_mode(h, 618 promisc_flags & HNAE3_UPE, 619 promisc_flags & HNAE3_MPE); 620 } 621 622 return 0; 623 } 624 625 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable) 626 { 627 struct hns3_nic_priv *priv = netdev_priv(netdev); 628 struct hnae3_handle *h = priv->ae_handle; 629 bool last_state; 630 631 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) { 632 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false; 633 if (enable != last_state) { 634 netdev_info(netdev, 635 "%s vlan filter\n", 636 enable ? "enable" : "disable"); 637 h->ae_algo->ops->enable_vlan_filter(h, enable); 638 } 639 } 640 } 641 642 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen, 643 u16 *mss, u32 *type_cs_vlan_tso) 644 { 645 u32 l4_offset, hdr_len; 646 union l3_hdr_info l3; 647 union l4_hdr_info l4; 648 u32 l4_paylen; 649 int ret; 650 651 if (!skb_is_gso(skb)) 652 return 0; 653 654 ret = skb_cow_head(skb, 0); 655 if (unlikely(ret)) 656 return ret; 657 658 l3.hdr = skb_network_header(skb); 659 l4.hdr = skb_transport_header(skb); 660 661 /* Software should clear the IPv4's checksum field when tso is 662 * needed. 663 */ 664 if (l3.v4->version == 4) 665 l3.v4->check = 0; 666 667 /* tunnel packet */ 668 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 669 SKB_GSO_GRE_CSUM | 670 SKB_GSO_UDP_TUNNEL | 671 SKB_GSO_UDP_TUNNEL_CSUM)) { 672 if ((!(skb_shinfo(skb)->gso_type & 673 SKB_GSO_PARTIAL)) && 674 (skb_shinfo(skb)->gso_type & 675 SKB_GSO_UDP_TUNNEL_CSUM)) { 676 /* Software should clear the udp's checksum 677 * field when tso is needed. 678 */ 679 l4.udp->check = 0; 680 } 681 /* reset l3&l4 pointers from outer to inner headers */ 682 l3.hdr = skb_inner_network_header(skb); 683 l4.hdr = skb_inner_transport_header(skb); 684 685 /* Software should clear the IPv4's checksum field when 686 * tso is needed. 687 */ 688 if (l3.v4->version == 4) 689 l3.v4->check = 0; 690 } 691 692 /* normal or tunnel packet */ 693 l4_offset = l4.hdr - skb->data; 694 hdr_len = (l4.tcp->doff << 2) + l4_offset; 695 696 /* remove payload length from inner pseudo checksum when tso */ 697 l4_paylen = skb->len - l4_offset; 698 csum_replace_by_diff(&l4.tcp->check, 699 (__force __wsum)htonl(l4_paylen)); 700 701 /* find the txbd field values */ 702 *paylen = skb->len - hdr_len; 703 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 704 705 /* get MSS for TSO */ 706 *mss = skb_shinfo(skb)->gso_size; 707 708 return 0; 709 } 710 711 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 712 u8 *il4_proto) 713 { 714 union l3_hdr_info l3; 715 unsigned char *l4_hdr; 716 unsigned char *exthdr; 717 u8 l4_proto_tmp; 718 __be16 frag_off; 719 720 /* find outer header point */ 721 l3.hdr = skb_network_header(skb); 722 l4_hdr = skb_transport_header(skb); 723 724 if (skb->protocol == htons(ETH_P_IPV6)) { 725 exthdr = l3.hdr + sizeof(*l3.v6); 726 l4_proto_tmp = l3.v6->nexthdr; 727 if (l4_hdr != exthdr) 728 ipv6_skip_exthdr(skb, exthdr - skb->data, 729 &l4_proto_tmp, &frag_off); 730 } else if (skb->protocol == htons(ETH_P_IP)) { 731 l4_proto_tmp = l3.v4->protocol; 732 } else { 733 return -EINVAL; 734 } 735 736 *ol4_proto = l4_proto_tmp; 737 738 /* tunnel packet */ 739 if (!skb->encapsulation) { 740 *il4_proto = 0; 741 return 0; 742 } 743 744 /* find inner header point */ 745 l3.hdr = skb_inner_network_header(skb); 746 l4_hdr = skb_inner_transport_header(skb); 747 748 if (l3.v6->version == 6) { 749 exthdr = l3.hdr + sizeof(*l3.v6); 750 l4_proto_tmp = l3.v6->nexthdr; 751 if (l4_hdr != exthdr) 752 ipv6_skip_exthdr(skb, exthdr - skb->data, 753 &l4_proto_tmp, &frag_off); 754 } else if (l3.v4->version == 4) { 755 l4_proto_tmp = l3.v4->protocol; 756 } 757 758 *il4_proto = l4_proto_tmp; 759 760 return 0; 761 } 762 763 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 764 * and it is udp packet, which has a dest port as the IANA assigned. 765 * the hardware is expected to do the checksum offload, but the 766 * hardware will not do the checksum offload when udp dest port is 767 * 4789. 768 */ 769 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 770 { 771 union l4_hdr_info l4; 772 773 l4.hdr = skb_transport_header(skb); 774 775 if (!(!skb->encapsulation && 776 l4.udp->dest == htons(IANA_VXLAN_UDP_PORT))) 777 return false; 778 779 skb_checksum_help(skb); 780 781 return true; 782 } 783 784 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 785 u32 *ol_type_vlan_len_msec) 786 { 787 u32 l2_len, l3_len, l4_len; 788 unsigned char *il2_hdr; 789 union l3_hdr_info l3; 790 union l4_hdr_info l4; 791 792 l3.hdr = skb_network_header(skb); 793 l4.hdr = skb_transport_header(skb); 794 795 /* compute OL2 header size, defined in 2 Bytes */ 796 l2_len = l3.hdr - skb->data; 797 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1); 798 799 /* compute OL3 header size, defined in 4 Bytes */ 800 l3_len = l4.hdr - l3.hdr; 801 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2); 802 803 il2_hdr = skb_inner_mac_header(skb); 804 /* compute OL4 header size, defined in 4 Bytes */ 805 l4_len = il2_hdr - l4.hdr; 806 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2); 807 808 /* define outer network header type */ 809 if (skb->protocol == htons(ETH_P_IP)) { 810 if (skb_is_gso(skb)) 811 hns3_set_field(*ol_type_vlan_len_msec, 812 HNS3_TXD_OL3T_S, 813 HNS3_OL3T_IPV4_CSUM); 814 else 815 hns3_set_field(*ol_type_vlan_len_msec, 816 HNS3_TXD_OL3T_S, 817 HNS3_OL3T_IPV4_NO_CSUM); 818 819 } else if (skb->protocol == htons(ETH_P_IPV6)) { 820 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 821 HNS3_OL3T_IPV6); 822 } 823 824 if (ol4_proto == IPPROTO_UDP) 825 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 826 HNS3_TUN_MAC_IN_UDP); 827 else if (ol4_proto == IPPROTO_GRE) 828 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 829 HNS3_TUN_NVGRE); 830 } 831 832 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 833 u8 il4_proto, u32 *type_cs_vlan_tso, 834 u32 *ol_type_vlan_len_msec) 835 { 836 unsigned char *l2_hdr = skb->data; 837 u32 l4_proto = ol4_proto; 838 union l4_hdr_info l4; 839 union l3_hdr_info l3; 840 u32 l2_len, l3_len; 841 842 l4.hdr = skb_transport_header(skb); 843 l3.hdr = skb_network_header(skb); 844 845 /* handle encapsulation skb */ 846 if (skb->encapsulation) { 847 /* If this is a not UDP/GRE encapsulation skb */ 848 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) { 849 /* drop the skb tunnel packet if hardware don't support, 850 * because hardware can't calculate csum when TSO. 851 */ 852 if (skb_is_gso(skb)) 853 return -EDOM; 854 855 /* the stack computes the IP header already, 856 * driver calculate l4 checksum when not TSO. 857 */ 858 skb_checksum_help(skb); 859 return 0; 860 } 861 862 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec); 863 864 /* switch to inner header */ 865 l2_hdr = skb_inner_mac_header(skb); 866 l3.hdr = skb_inner_network_header(skb); 867 l4.hdr = skb_inner_transport_header(skb); 868 l4_proto = il4_proto; 869 } 870 871 if (l3.v4->version == 4) { 872 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 873 HNS3_L3T_IPV4); 874 875 /* the stack computes the IP header already, the only time we 876 * need the hardware to recompute it is in the case of TSO. 877 */ 878 if (skb_is_gso(skb)) 879 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 880 } else if (l3.v6->version == 6) { 881 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 882 HNS3_L3T_IPV6); 883 } 884 885 /* compute inner(/normal) L2 header size, defined in 2 Bytes */ 886 l2_len = l3.hdr - l2_hdr; 887 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 888 889 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 890 l3_len = l4.hdr - l3.hdr; 891 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 892 893 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 894 switch (l4_proto) { 895 case IPPROTO_TCP: 896 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 897 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 898 HNS3_L4T_TCP); 899 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 900 l4.tcp->doff); 901 break; 902 case IPPROTO_UDP: 903 if (hns3_tunnel_csum_bug(skb)) 904 break; 905 906 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 907 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 908 HNS3_L4T_UDP); 909 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 910 (sizeof(struct udphdr) >> 2)); 911 break; 912 case IPPROTO_SCTP: 913 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 914 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 915 HNS3_L4T_SCTP); 916 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 917 (sizeof(struct sctphdr) >> 2)); 918 break; 919 default: 920 /* drop the skb tunnel packet if hardware don't support, 921 * because hardware can't calculate csum when TSO. 922 */ 923 if (skb_is_gso(skb)) 924 return -EDOM; 925 926 /* the stack computes the IP header already, 927 * driver calculate l4 checksum when not TSO. 928 */ 929 skb_checksum_help(skb); 930 return 0; 931 } 932 933 return 0; 934 } 935 936 static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end) 937 { 938 /* Config bd buffer end */ 939 hns3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end); 940 hns3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1); 941 } 942 943 static int hns3_fill_desc_vtags(struct sk_buff *skb, 944 struct hns3_enet_ring *tx_ring, 945 u32 *inner_vlan_flag, 946 u32 *out_vlan_flag, 947 u16 *inner_vtag, 948 u16 *out_vtag) 949 { 950 #define HNS3_TX_VLAN_PRIO_SHIFT 13 951 952 struct hnae3_handle *handle = tx_ring->tqp->handle; 953 954 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN 955 * header is allowed in skb, otherwise it will cause RAS error. 956 */ 957 if (unlikely(skb_vlan_tagged_multi(skb) && 958 handle->port_base_vlan_state == 959 HNAE3_PORT_BASE_VLAN_ENABLE)) 960 return -EINVAL; 961 962 if (skb->protocol == htons(ETH_P_8021Q) && 963 !(tx_ring->tqp->handle->kinfo.netdev->features & 964 NETIF_F_HW_VLAN_CTAG_TX)) { 965 /* When HW VLAN acceleration is turned off, and the stack 966 * sets the protocol to 802.1q, the driver just need to 967 * set the protocol to the encapsulated ethertype. 968 */ 969 skb->protocol = vlan_get_protocol(skb); 970 return 0; 971 } 972 973 if (skb_vlan_tag_present(skb)) { 974 u16 vlan_tag; 975 976 vlan_tag = skb_vlan_tag_get(skb); 977 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT; 978 979 /* Based on hw strategy, use out_vtag in two layer tag case, 980 * and use inner_vtag in one tag case. 981 */ 982 if (skb->protocol == htons(ETH_P_8021Q)) { 983 if (handle->port_base_vlan_state == 984 HNAE3_PORT_BASE_VLAN_DISABLE){ 985 hns3_set_field(*out_vlan_flag, 986 HNS3_TXD_OVLAN_B, 1); 987 *out_vtag = vlan_tag; 988 } else { 989 hns3_set_field(*inner_vlan_flag, 990 HNS3_TXD_VLAN_B, 1); 991 *inner_vtag = vlan_tag; 992 } 993 } else { 994 hns3_set_field(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1); 995 *inner_vtag = vlan_tag; 996 } 997 } else if (skb->protocol == htons(ETH_P_8021Q)) { 998 struct vlan_ethhdr *vhdr; 999 int rc; 1000 1001 rc = skb_cow_head(skb, 0); 1002 if (unlikely(rc < 0)) 1003 return rc; 1004 vhdr = (struct vlan_ethhdr *)skb->data; 1005 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7) 1006 << HNS3_TX_VLAN_PRIO_SHIFT); 1007 } 1008 1009 skb->protocol = vlan_get_protocol(skb); 1010 return 0; 1011 } 1012 1013 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 1014 unsigned int size, int frag_end, 1015 enum hns_desc_type type) 1016 { 1017 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1018 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1019 struct device *dev = ring_to_dev(ring); 1020 struct skb_frag_struct *frag; 1021 unsigned int frag_buf_num; 1022 int k, sizeoflast; 1023 dma_addr_t dma; 1024 1025 if (type == DESC_TYPE_SKB) { 1026 struct sk_buff *skb = (struct sk_buff *)priv; 1027 u32 ol_type_vlan_len_msec = 0; 1028 u32 type_cs_vlan_tso = 0; 1029 u32 paylen = skb->len; 1030 u16 inner_vtag = 0; 1031 u16 out_vtag = 0; 1032 u16 mss = 0; 1033 int ret; 1034 1035 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso, 1036 &ol_type_vlan_len_msec, 1037 &inner_vtag, &out_vtag); 1038 if (unlikely(ret)) 1039 return ret; 1040 1041 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1042 u8 ol4_proto, il4_proto; 1043 1044 skb_reset_mac_len(skb); 1045 1046 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1047 if (unlikely(ret)) 1048 return ret; 1049 1050 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto, 1051 &type_cs_vlan_tso, 1052 &ol_type_vlan_len_msec); 1053 if (unlikely(ret)) 1054 return ret; 1055 1056 ret = hns3_set_tso(skb, &paylen, &mss, 1057 &type_cs_vlan_tso); 1058 if (unlikely(ret)) 1059 return ret; 1060 } 1061 1062 /* Set txbd */ 1063 desc->tx.ol_type_vlan_len_msec = 1064 cpu_to_le32(ol_type_vlan_len_msec); 1065 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso); 1066 desc->tx.paylen = cpu_to_le32(paylen); 1067 desc->tx.mss = cpu_to_le16(mss); 1068 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1069 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1070 1071 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1072 } else { 1073 frag = (struct skb_frag_struct *)priv; 1074 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1075 } 1076 1077 if (unlikely(dma_mapping_error(dev, dma))) { 1078 ring->stats.sw_err_cnt++; 1079 return -ENOMEM; 1080 } 1081 1082 desc_cb->length = size; 1083 1084 if (likely(size <= HNS3_MAX_BD_SIZE)) { 1085 u16 bdtp_fe_sc_vld_ra_ri = 0; 1086 1087 desc_cb->priv = priv; 1088 desc_cb->dma = dma; 1089 desc_cb->type = type; 1090 desc->addr = cpu_to_le64(dma); 1091 desc->tx.send_size = cpu_to_le16(size); 1092 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, frag_end); 1093 desc->tx.bdtp_fe_sc_vld_ra_ri = 1094 cpu_to_le16(bdtp_fe_sc_vld_ra_ri); 1095 1096 ring_ptr_move_fw(ring, next_to_use); 1097 return 0; 1098 } 1099 1100 frag_buf_num = hns3_tx_bd_count(size); 1101 sizeoflast = size & HNS3_TX_LAST_SIZE_M; 1102 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1103 1104 /* When frag size is bigger than hardware limit, split this frag */ 1105 for (k = 0; k < frag_buf_num; k++) { 1106 u16 bdtp_fe_sc_vld_ra_ri = 0; 1107 1108 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */ 1109 desc_cb->priv = priv; 1110 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k; 1111 desc_cb->type = (type == DESC_TYPE_SKB && !k) ? 1112 DESC_TYPE_SKB : DESC_TYPE_PAGE; 1113 1114 /* now, fill the descriptor */ 1115 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1116 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1117 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1118 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, 1119 frag_end && (k == frag_buf_num - 1) ? 1120 1 : 0); 1121 desc->tx.bdtp_fe_sc_vld_ra_ri = 1122 cpu_to_le16(bdtp_fe_sc_vld_ra_ri); 1123 1124 /* move ring pointer to next */ 1125 ring_ptr_move_fw(ring, next_to_use); 1126 1127 desc_cb = &ring->desc_cb[ring->next_to_use]; 1128 desc = &ring->desc[ring->next_to_use]; 1129 } 1130 1131 return 0; 1132 } 1133 1134 static int hns3_nic_bd_num(struct sk_buff *skb) 1135 { 1136 int size = skb_headlen(skb); 1137 int i, bd_num; 1138 1139 /* if the total len is within the max bd limit */ 1140 if (likely(skb->len <= HNS3_MAX_BD_SIZE)) 1141 return skb_shinfo(skb)->nr_frags + 1; 1142 1143 bd_num = hns3_tx_bd_count(size); 1144 1145 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1146 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 1147 int frag_bd_num; 1148 1149 size = skb_frag_size(frag); 1150 frag_bd_num = hns3_tx_bd_count(size); 1151 1152 if (unlikely(frag_bd_num > HNS3_MAX_BD_PER_FRAG)) 1153 return -ENOMEM; 1154 1155 bd_num += frag_bd_num; 1156 } 1157 1158 return bd_num; 1159 } 1160 1161 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb) 1162 { 1163 if (!skb->encapsulation) 1164 return skb_transport_offset(skb) + tcp_hdrlen(skb); 1165 1166 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb); 1167 } 1168 1169 /* HW need every continuous 8 buffer data to be larger than MSS, 1170 * we simplify it by ensuring skb_headlen + the first continuous 1171 * 7 frags to to be larger than gso header len + mss, and the remaining 1172 * continuous 7 frags to be larger than MSS except the last 7 frags. 1173 */ 1174 static bool hns3_skb_need_linearized(struct sk_buff *skb) 1175 { 1176 int bd_limit = HNS3_MAX_BD_PER_FRAG - 1; 1177 unsigned int tot_len = 0; 1178 int i; 1179 1180 for (i = 0; i < bd_limit; i++) 1181 tot_len += skb_frag_size(&skb_shinfo(skb)->frags[i]); 1182 1183 /* ensure headlen + the first 7 frags is greater than mss + header 1184 * and the first 7 frags is greater than mss. 1185 */ 1186 if (((tot_len + skb_headlen(skb)) < (skb_shinfo(skb)->gso_size + 1187 hns3_gso_hdr_len(skb))) || (tot_len < skb_shinfo(skb)->gso_size)) 1188 return true; 1189 1190 /* ensure the remaining continuous 7 buffer is greater than mss */ 1191 for (i = 0; i < (skb_shinfo(skb)->nr_frags - bd_limit - 1); i++) { 1192 tot_len -= skb_frag_size(&skb_shinfo(skb)->frags[i]); 1193 tot_len += skb_frag_size(&skb_shinfo(skb)->frags[i + bd_limit]); 1194 1195 if (tot_len < skb_shinfo(skb)->gso_size) 1196 return true; 1197 } 1198 1199 return false; 1200 } 1201 1202 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring, 1203 struct sk_buff **out_skb) 1204 { 1205 struct sk_buff *skb = *out_skb; 1206 int bd_num; 1207 1208 bd_num = hns3_nic_bd_num(skb); 1209 if (bd_num < 0) 1210 return bd_num; 1211 1212 if (unlikely(bd_num > HNS3_MAX_BD_PER_FRAG)) { 1213 struct sk_buff *new_skb; 1214 1215 if (skb_is_gso(skb) && !hns3_skb_need_linearized(skb)) 1216 goto out; 1217 1218 bd_num = hns3_tx_bd_count(skb->len); 1219 if (unlikely(ring_space(ring) < bd_num)) 1220 return -EBUSY; 1221 /* manual split the send packet */ 1222 new_skb = skb_copy(skb, GFP_ATOMIC); 1223 if (!new_skb) 1224 return -ENOMEM; 1225 dev_kfree_skb_any(skb); 1226 *out_skb = new_skb; 1227 1228 u64_stats_update_begin(&ring->syncp); 1229 ring->stats.tx_copy++; 1230 u64_stats_update_end(&ring->syncp); 1231 } 1232 1233 out: 1234 if (unlikely(ring_space(ring) < bd_num)) 1235 return -EBUSY; 1236 1237 return bd_num; 1238 } 1239 1240 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1241 { 1242 struct device *dev = ring_to_dev(ring); 1243 unsigned int i; 1244 1245 for (i = 0; i < ring->desc_num; i++) { 1246 /* check if this is where we started */ 1247 if (ring->next_to_use == next_to_use_orig) 1248 break; 1249 1250 /* rollback one */ 1251 ring_ptr_move_bw(ring, next_to_use); 1252 1253 /* unmap the descriptor dma address */ 1254 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB) 1255 dma_unmap_single(dev, 1256 ring->desc_cb[ring->next_to_use].dma, 1257 ring->desc_cb[ring->next_to_use].length, 1258 DMA_TO_DEVICE); 1259 else if (ring->desc_cb[ring->next_to_use].length) 1260 dma_unmap_page(dev, 1261 ring->desc_cb[ring->next_to_use].dma, 1262 ring->desc_cb[ring->next_to_use].length, 1263 DMA_TO_DEVICE); 1264 1265 ring->desc_cb[ring->next_to_use].length = 0; 1266 ring->desc_cb[ring->next_to_use].dma = 0; 1267 } 1268 } 1269 1270 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1271 { 1272 struct hns3_nic_priv *priv = netdev_priv(netdev); 1273 struct hns3_nic_ring_data *ring_data = 1274 &tx_ring_data(priv, skb->queue_mapping); 1275 struct hns3_enet_ring *ring = ring_data->ring; 1276 struct netdev_queue *dev_queue; 1277 struct skb_frag_struct *frag; 1278 int next_to_use_head; 1279 int buf_num; 1280 int seg_num; 1281 int size; 1282 int ret; 1283 int i; 1284 1285 /* Prefetch the data used later */ 1286 prefetch(skb->data); 1287 1288 buf_num = hns3_nic_maybe_stop_tx(ring, &skb); 1289 if (unlikely(buf_num <= 0)) { 1290 if (buf_num == -EBUSY) { 1291 u64_stats_update_begin(&ring->syncp); 1292 ring->stats.tx_busy++; 1293 u64_stats_update_end(&ring->syncp); 1294 goto out_net_tx_busy; 1295 } else if (buf_num == -ENOMEM) { 1296 u64_stats_update_begin(&ring->syncp); 1297 ring->stats.sw_err_cnt++; 1298 u64_stats_update_end(&ring->syncp); 1299 } 1300 1301 if (net_ratelimit()) 1302 netdev_err(netdev, "xmit error: %d!\n", buf_num); 1303 1304 goto out_err_tx_ok; 1305 } 1306 1307 /* No. of segments (plus a header) */ 1308 seg_num = skb_shinfo(skb)->nr_frags + 1; 1309 /* Fill the first part */ 1310 size = skb_headlen(skb); 1311 1312 next_to_use_head = ring->next_to_use; 1313 1314 ret = hns3_fill_desc(ring, skb, size, seg_num == 1 ? 1 : 0, 1315 DESC_TYPE_SKB); 1316 if (unlikely(ret)) 1317 goto fill_err; 1318 1319 /* Fill the fragments */ 1320 for (i = 1; i < seg_num; i++) { 1321 frag = &skb_shinfo(skb)->frags[i - 1]; 1322 size = skb_frag_size(frag); 1323 1324 ret = hns3_fill_desc(ring, frag, size, 1325 seg_num - 1 == i ? 1 : 0, 1326 DESC_TYPE_PAGE); 1327 1328 if (unlikely(ret)) 1329 goto fill_err; 1330 } 1331 1332 /* Complete translate all packets */ 1333 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index); 1334 netdev_tx_sent_queue(dev_queue, skb->len); 1335 1336 wmb(); /* Commit all data before submit */ 1337 1338 hnae3_queue_xmit(ring->tqp, buf_num); 1339 1340 return NETDEV_TX_OK; 1341 1342 fill_err: 1343 hns3_clear_desc(ring, next_to_use_head); 1344 1345 out_err_tx_ok: 1346 dev_kfree_skb_any(skb); 1347 return NETDEV_TX_OK; 1348 1349 out_net_tx_busy: 1350 netif_stop_subqueue(netdev, ring_data->queue_index); 1351 smp_mb(); /* Commit all data before submit */ 1352 1353 return NETDEV_TX_BUSY; 1354 } 1355 1356 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1357 { 1358 struct hnae3_handle *h = hns3_get_handle(netdev); 1359 struct sockaddr *mac_addr = p; 1360 int ret; 1361 1362 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1363 return -EADDRNOTAVAIL; 1364 1365 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1366 netdev_info(netdev, "already using mac address %pM\n", 1367 mac_addr->sa_data); 1368 return 0; 1369 } 1370 1371 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1372 if (ret) { 1373 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1374 return ret; 1375 } 1376 1377 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1378 1379 return 0; 1380 } 1381 1382 static int hns3_nic_do_ioctl(struct net_device *netdev, 1383 struct ifreq *ifr, int cmd) 1384 { 1385 struct hnae3_handle *h = hns3_get_handle(netdev); 1386 1387 if (!netif_running(netdev)) 1388 return -EINVAL; 1389 1390 if (!h->ae_algo->ops->do_ioctl) 1391 return -EOPNOTSUPP; 1392 1393 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 1394 } 1395 1396 static int hns3_nic_set_features(struct net_device *netdev, 1397 netdev_features_t features) 1398 { 1399 netdev_features_t changed = netdev->features ^ features; 1400 struct hns3_nic_priv *priv = netdev_priv(netdev); 1401 struct hnae3_handle *h = priv->ae_handle; 1402 bool enable; 1403 int ret; 1404 1405 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 1406 enable = !!(features & NETIF_F_GRO_HW); 1407 ret = h->ae_algo->ops->set_gro_en(h, enable); 1408 if (ret) 1409 return ret; 1410 } 1411 1412 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 1413 h->ae_algo->ops->enable_vlan_filter) { 1414 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER); 1415 h->ae_algo->ops->enable_vlan_filter(h, enable); 1416 } 1417 1418 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1419 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1420 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 1421 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 1422 if (ret) 1423 return ret; 1424 } 1425 1426 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 1427 enable = !!(features & NETIF_F_NTUPLE); 1428 h->ae_algo->ops->enable_fd(h, enable); 1429 } 1430 1431 netdev->features = features; 1432 return 0; 1433 } 1434 1435 static void hns3_nic_get_stats64(struct net_device *netdev, 1436 struct rtnl_link_stats64 *stats) 1437 { 1438 struct hns3_nic_priv *priv = netdev_priv(netdev); 1439 int queue_num = priv->ae_handle->kinfo.num_tqps; 1440 struct hnae3_handle *handle = priv->ae_handle; 1441 struct hns3_enet_ring *ring; 1442 u64 rx_length_errors = 0; 1443 u64 rx_crc_errors = 0; 1444 u64 rx_multicast = 0; 1445 unsigned int start; 1446 u64 tx_errors = 0; 1447 u64 rx_errors = 0; 1448 unsigned int idx; 1449 u64 tx_bytes = 0; 1450 u64 rx_bytes = 0; 1451 u64 tx_pkts = 0; 1452 u64 rx_pkts = 0; 1453 u64 tx_drop = 0; 1454 u64 rx_drop = 0; 1455 1456 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1457 return; 1458 1459 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1460 1461 for (idx = 0; idx < queue_num; idx++) { 1462 /* fetch the tx stats */ 1463 ring = priv->ring_data[idx].ring; 1464 do { 1465 start = u64_stats_fetch_begin_irq(&ring->syncp); 1466 tx_bytes += ring->stats.tx_bytes; 1467 tx_pkts += ring->stats.tx_pkts; 1468 tx_drop += ring->stats.sw_err_cnt; 1469 tx_errors += ring->stats.sw_err_cnt; 1470 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1471 1472 /* fetch the rx stats */ 1473 ring = priv->ring_data[idx + queue_num].ring; 1474 do { 1475 start = u64_stats_fetch_begin_irq(&ring->syncp); 1476 rx_bytes += ring->stats.rx_bytes; 1477 rx_pkts += ring->stats.rx_pkts; 1478 rx_drop += ring->stats.non_vld_descs; 1479 rx_drop += ring->stats.l2_err; 1480 rx_errors += ring->stats.non_vld_descs; 1481 rx_errors += ring->stats.l2_err; 1482 rx_crc_errors += ring->stats.l2_err; 1483 rx_crc_errors += ring->stats.l3l4_csum_err; 1484 rx_multicast += ring->stats.rx_multicast; 1485 rx_length_errors += ring->stats.err_pkt_len; 1486 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1487 } 1488 1489 stats->tx_bytes = tx_bytes; 1490 stats->tx_packets = tx_pkts; 1491 stats->rx_bytes = rx_bytes; 1492 stats->rx_packets = rx_pkts; 1493 1494 stats->rx_errors = rx_errors; 1495 stats->multicast = rx_multicast; 1496 stats->rx_length_errors = rx_length_errors; 1497 stats->rx_crc_errors = rx_crc_errors; 1498 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1499 1500 stats->tx_errors = tx_errors; 1501 stats->rx_dropped = rx_drop; 1502 stats->tx_dropped = tx_drop; 1503 stats->collisions = netdev->stats.collisions; 1504 stats->rx_over_errors = netdev->stats.rx_over_errors; 1505 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1506 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1507 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1508 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1509 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1510 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1511 stats->tx_window_errors = netdev->stats.tx_window_errors; 1512 stats->rx_compressed = netdev->stats.rx_compressed; 1513 stats->tx_compressed = netdev->stats.tx_compressed; 1514 } 1515 1516 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1517 { 1518 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1519 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map; 1520 struct hnae3_knic_private_info *kinfo; 1521 u8 tc = mqprio_qopt->qopt.num_tc; 1522 u16 mode = mqprio_qopt->mode; 1523 u8 hw = mqprio_qopt->qopt.hw; 1524 struct hnae3_handle *h; 1525 1526 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1527 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1528 return -EOPNOTSUPP; 1529 1530 if (tc > HNAE3_MAX_TC) 1531 return -EINVAL; 1532 1533 if (!netdev) 1534 return -EINVAL; 1535 1536 h = hns3_get_handle(netdev); 1537 kinfo = &h->kinfo; 1538 1539 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1540 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP; 1541 } 1542 1543 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1544 void *type_data) 1545 { 1546 if (type != TC_SETUP_QDISC_MQPRIO) 1547 return -EOPNOTSUPP; 1548 1549 return hns3_setup_tc(dev, type_data); 1550 } 1551 1552 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1553 __be16 proto, u16 vid) 1554 { 1555 struct hnae3_handle *h = hns3_get_handle(netdev); 1556 int ret = -EIO; 1557 1558 if (h->ae_algo->ops->set_vlan_filter) 1559 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1560 1561 return ret; 1562 } 1563 1564 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1565 __be16 proto, u16 vid) 1566 { 1567 struct hnae3_handle *h = hns3_get_handle(netdev); 1568 int ret = -EIO; 1569 1570 if (h->ae_algo->ops->set_vlan_filter) 1571 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1572 1573 return ret; 1574 } 1575 1576 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1577 u8 qos, __be16 vlan_proto) 1578 { 1579 struct hnae3_handle *h = hns3_get_handle(netdev); 1580 int ret = -EIO; 1581 1582 if (h->ae_algo->ops->set_vf_vlan_filter) 1583 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1584 qos, vlan_proto); 1585 1586 return ret; 1587 } 1588 1589 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1590 { 1591 struct hnae3_handle *h = hns3_get_handle(netdev); 1592 int ret; 1593 1594 if (hns3_nic_resetting(netdev)) 1595 return -EBUSY; 1596 1597 if (!h->ae_algo->ops->set_mtu) 1598 return -EOPNOTSUPP; 1599 1600 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 1601 if (ret) 1602 netdev_err(netdev, "failed to change MTU in hardware %d\n", 1603 ret); 1604 else 1605 netdev->mtu = new_mtu; 1606 1607 return ret; 1608 } 1609 1610 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 1611 { 1612 struct hns3_nic_priv *priv = netdev_priv(ndev); 1613 struct hnae3_handle *h = hns3_get_handle(ndev); 1614 struct hns3_enet_ring *tx_ring = NULL; 1615 struct napi_struct *napi; 1616 int timeout_queue = 0; 1617 int hw_head, hw_tail; 1618 int fbd_num, fbd_oft; 1619 int ebd_num, ebd_oft; 1620 int bd_num, bd_err; 1621 int ring_en, tc; 1622 int i; 1623 1624 /* Find the stopped queue the same way the stack does */ 1625 for (i = 0; i < ndev->num_tx_queues; i++) { 1626 struct netdev_queue *q; 1627 unsigned long trans_start; 1628 1629 q = netdev_get_tx_queue(ndev, i); 1630 trans_start = q->trans_start; 1631 if (netif_xmit_stopped(q) && 1632 time_after(jiffies, 1633 (trans_start + ndev->watchdog_timeo))) { 1634 timeout_queue = i; 1635 break; 1636 } 1637 } 1638 1639 if (i == ndev->num_tx_queues) { 1640 netdev_info(ndev, 1641 "no netdev TX timeout queue found, timeout count: %llu\n", 1642 priv->tx_timeout_count); 1643 return false; 1644 } 1645 1646 priv->tx_timeout_count++; 1647 1648 tx_ring = priv->ring_data[timeout_queue].ring; 1649 napi = &tx_ring->tqp_vector->napi; 1650 1651 netdev_info(ndev, 1652 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n", 1653 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use, 1654 tx_ring->next_to_clean, napi->state); 1655 1656 netdev_info(ndev, 1657 "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n", 1658 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes, 1659 tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt); 1660 1661 netdev_info(ndev, 1662 "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n", 1663 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt, 1664 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy); 1665 1666 /* When mac received many pause frames continuous, it's unable to send 1667 * packets, which may cause tx timeout 1668 */ 1669 if (h->ae_algo->ops->update_stats && 1670 h->ae_algo->ops->get_mac_pause_stats) { 1671 u64 tx_pause_cnt, rx_pause_cnt; 1672 1673 h->ae_algo->ops->update_stats(h, &ndev->stats); 1674 h->ae_algo->ops->get_mac_pause_stats(h, &tx_pause_cnt, 1675 &rx_pause_cnt); 1676 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n", 1677 tx_pause_cnt, rx_pause_cnt); 1678 } 1679 1680 hw_head = readl_relaxed(tx_ring->tqp->io_base + 1681 HNS3_RING_TX_RING_HEAD_REG); 1682 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 1683 HNS3_RING_TX_RING_TAIL_REG); 1684 fbd_num = readl_relaxed(tx_ring->tqp->io_base + 1685 HNS3_RING_TX_RING_FBDNUM_REG); 1686 fbd_oft = readl_relaxed(tx_ring->tqp->io_base + 1687 HNS3_RING_TX_RING_OFFSET_REG); 1688 ebd_num = readl_relaxed(tx_ring->tqp->io_base + 1689 HNS3_RING_TX_RING_EBDNUM_REG); 1690 ebd_oft = readl_relaxed(tx_ring->tqp->io_base + 1691 HNS3_RING_TX_RING_EBD_OFFSET_REG); 1692 bd_num = readl_relaxed(tx_ring->tqp->io_base + 1693 HNS3_RING_TX_RING_BD_NUM_REG); 1694 bd_err = readl_relaxed(tx_ring->tqp->io_base + 1695 HNS3_RING_TX_RING_BD_ERR_REG); 1696 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG); 1697 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG); 1698 1699 netdev_info(ndev, 1700 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n", 1701 bd_num, hw_head, hw_tail, bd_err, 1702 readl(tx_ring->tqp_vector->mask_addr)); 1703 netdev_info(ndev, 1704 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n", 1705 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft); 1706 1707 return true; 1708 } 1709 1710 static void hns3_nic_net_timeout(struct net_device *ndev) 1711 { 1712 struct hns3_nic_priv *priv = netdev_priv(ndev); 1713 struct hnae3_handle *h = priv->ae_handle; 1714 1715 if (!hns3_get_tx_timeo_queue_info(ndev)) 1716 return; 1717 1718 /* request the reset, and let the hclge to determine 1719 * which reset level should be done 1720 */ 1721 if (h->ae_algo->ops->reset_event) 1722 h->ae_algo->ops->reset_event(h->pdev, h); 1723 } 1724 1725 #ifdef CONFIG_RFS_ACCEL 1726 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 1727 u16 rxq_index, u32 flow_id) 1728 { 1729 struct hnae3_handle *h = hns3_get_handle(dev); 1730 struct flow_keys fkeys; 1731 1732 if (!h->ae_algo->ops->add_arfs_entry) 1733 return -EOPNOTSUPP; 1734 1735 if (skb->encapsulation) 1736 return -EPROTONOSUPPORT; 1737 1738 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0)) 1739 return -EPROTONOSUPPORT; 1740 1741 if ((fkeys.basic.n_proto != htons(ETH_P_IP) && 1742 fkeys.basic.n_proto != htons(ETH_P_IPV6)) || 1743 (fkeys.basic.ip_proto != IPPROTO_TCP && 1744 fkeys.basic.ip_proto != IPPROTO_UDP)) 1745 return -EPROTONOSUPPORT; 1746 1747 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys); 1748 } 1749 #endif 1750 1751 static const struct net_device_ops hns3_nic_netdev_ops = { 1752 .ndo_open = hns3_nic_net_open, 1753 .ndo_stop = hns3_nic_net_stop, 1754 .ndo_start_xmit = hns3_nic_net_xmit, 1755 .ndo_tx_timeout = hns3_nic_net_timeout, 1756 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 1757 .ndo_do_ioctl = hns3_nic_do_ioctl, 1758 .ndo_change_mtu = hns3_nic_change_mtu, 1759 .ndo_set_features = hns3_nic_set_features, 1760 .ndo_get_stats64 = hns3_nic_get_stats64, 1761 .ndo_setup_tc = hns3_nic_setup_tc, 1762 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 1763 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 1764 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 1765 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 1766 #ifdef CONFIG_RFS_ACCEL 1767 .ndo_rx_flow_steer = hns3_rx_flow_steer, 1768 #endif 1769 1770 }; 1771 1772 bool hns3_is_phys_func(struct pci_dev *pdev) 1773 { 1774 u32 dev_id = pdev->device; 1775 1776 switch (dev_id) { 1777 case HNAE3_DEV_ID_GE: 1778 case HNAE3_DEV_ID_25GE: 1779 case HNAE3_DEV_ID_25GE_RDMA: 1780 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 1781 case HNAE3_DEV_ID_50GE_RDMA: 1782 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 1783 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 1784 return true; 1785 case HNAE3_DEV_ID_100G_VF: 1786 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF: 1787 return false; 1788 default: 1789 dev_warn(&pdev->dev, "un-recognized pci device-id %d", 1790 dev_id); 1791 } 1792 1793 return false; 1794 } 1795 1796 static void hns3_disable_sriov(struct pci_dev *pdev) 1797 { 1798 /* If our VFs are assigned we cannot shut down SR-IOV 1799 * without causing issues, so just leave the hardware 1800 * available but disabled 1801 */ 1802 if (pci_vfs_assigned(pdev)) { 1803 dev_warn(&pdev->dev, 1804 "disabling driver while VFs are assigned\n"); 1805 return; 1806 } 1807 1808 pci_disable_sriov(pdev); 1809 } 1810 1811 static void hns3_get_dev_capability(struct pci_dev *pdev, 1812 struct hnae3_ae_dev *ae_dev) 1813 { 1814 if (pdev->revision >= 0x21) { 1815 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1); 1816 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1); 1817 } 1818 } 1819 1820 /* hns3_probe - Device initialization routine 1821 * @pdev: PCI device information struct 1822 * @ent: entry in hns3_pci_tbl 1823 * 1824 * hns3_probe initializes a PF identified by a pci_dev structure. 1825 * The OS initialization, configuring of the PF private structure, 1826 * and a hardware reset occur. 1827 * 1828 * Returns 0 on success, negative on failure 1829 */ 1830 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1831 { 1832 struct hnae3_ae_dev *ae_dev; 1833 int ret; 1834 1835 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL); 1836 if (!ae_dev) { 1837 ret = -ENOMEM; 1838 return ret; 1839 } 1840 1841 ae_dev->pdev = pdev; 1842 ae_dev->flag = ent->driver_data; 1843 ae_dev->reset_type = HNAE3_NONE_RESET; 1844 hns3_get_dev_capability(pdev, ae_dev); 1845 pci_set_drvdata(pdev, ae_dev); 1846 1847 ret = hnae3_register_ae_dev(ae_dev); 1848 if (ret) { 1849 devm_kfree(&pdev->dev, ae_dev); 1850 pci_set_drvdata(pdev, NULL); 1851 } 1852 1853 return ret; 1854 } 1855 1856 /* hns3_remove - Device removal routine 1857 * @pdev: PCI device information struct 1858 */ 1859 static void hns3_remove(struct pci_dev *pdev) 1860 { 1861 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1862 1863 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 1864 hns3_disable_sriov(pdev); 1865 1866 hnae3_unregister_ae_dev(ae_dev); 1867 pci_set_drvdata(pdev, NULL); 1868 } 1869 1870 /** 1871 * hns3_pci_sriov_configure 1872 * @pdev: pointer to a pci_dev structure 1873 * @num_vfs: number of VFs to allocate 1874 * 1875 * Enable or change the number of VFs. Called when the user updates the number 1876 * of VFs in sysfs. 1877 **/ 1878 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 1879 { 1880 int ret; 1881 1882 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 1883 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 1884 return -EINVAL; 1885 } 1886 1887 if (num_vfs) { 1888 ret = pci_enable_sriov(pdev, num_vfs); 1889 if (ret) 1890 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 1891 else 1892 return num_vfs; 1893 } else if (!pci_vfs_assigned(pdev)) { 1894 pci_disable_sriov(pdev); 1895 } else { 1896 dev_warn(&pdev->dev, 1897 "Unable to free VFs because some are assigned to VMs.\n"); 1898 } 1899 1900 return 0; 1901 } 1902 1903 static void hns3_shutdown(struct pci_dev *pdev) 1904 { 1905 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1906 1907 hnae3_unregister_ae_dev(ae_dev); 1908 devm_kfree(&pdev->dev, ae_dev); 1909 pci_set_drvdata(pdev, NULL); 1910 1911 if (system_state == SYSTEM_POWER_OFF) 1912 pci_set_power_state(pdev, PCI_D3hot); 1913 } 1914 1915 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 1916 pci_channel_state_t state) 1917 { 1918 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1919 pci_ers_result_t ret; 1920 1921 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state); 1922 1923 if (state == pci_channel_io_perm_failure) 1924 return PCI_ERS_RESULT_DISCONNECT; 1925 1926 if (!ae_dev || !ae_dev->ops) { 1927 dev_err(&pdev->dev, 1928 "Can't recover - error happened before device initialized\n"); 1929 return PCI_ERS_RESULT_NONE; 1930 } 1931 1932 if (ae_dev->ops->handle_hw_ras_error) 1933 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 1934 else 1935 return PCI_ERS_RESULT_NONE; 1936 1937 return ret; 1938 } 1939 1940 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 1941 { 1942 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1943 const struct hnae3_ae_ops *ops = ae_dev->ops; 1944 enum hnae3_reset_type reset_type; 1945 struct device *dev = &pdev->dev; 1946 1947 if (!ae_dev || !ae_dev->ops) 1948 return PCI_ERS_RESULT_NONE; 1949 1950 /* request the reset */ 1951 if (ops->reset_event) { 1952 if (!ae_dev->override_pci_need_reset) { 1953 reset_type = ops->get_reset_level(ae_dev, 1954 &ae_dev->hw_err_reset_req); 1955 ops->set_default_reset_request(ae_dev, reset_type); 1956 dev_info(dev, "requesting reset due to PCI error\n"); 1957 ops->reset_event(pdev, NULL); 1958 } 1959 1960 return PCI_ERS_RESULT_RECOVERED; 1961 } 1962 1963 return PCI_ERS_RESULT_DISCONNECT; 1964 } 1965 1966 static void hns3_reset_prepare(struct pci_dev *pdev) 1967 { 1968 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1969 1970 dev_info(&pdev->dev, "hns3 flr prepare\n"); 1971 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare) 1972 ae_dev->ops->flr_prepare(ae_dev); 1973 } 1974 1975 static void hns3_reset_done(struct pci_dev *pdev) 1976 { 1977 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1978 1979 dev_info(&pdev->dev, "hns3 flr done\n"); 1980 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done) 1981 ae_dev->ops->flr_done(ae_dev); 1982 } 1983 1984 static const struct pci_error_handlers hns3_err_handler = { 1985 .error_detected = hns3_error_detected, 1986 .slot_reset = hns3_slot_reset, 1987 .reset_prepare = hns3_reset_prepare, 1988 .reset_done = hns3_reset_done, 1989 }; 1990 1991 static struct pci_driver hns3_driver = { 1992 .name = hns3_driver_name, 1993 .id_table = hns3_pci_tbl, 1994 .probe = hns3_probe, 1995 .remove = hns3_remove, 1996 .shutdown = hns3_shutdown, 1997 .sriov_configure = hns3_pci_sriov_configure, 1998 .err_handler = &hns3_err_handler, 1999 }; 2000 2001 /* set default feature to hns3 */ 2002 static void hns3_set_default_feature(struct net_device *netdev) 2003 { 2004 struct hnae3_handle *h = hns3_get_handle(netdev); 2005 struct pci_dev *pdev = h->pdev; 2006 2007 netdev->priv_flags |= IFF_UNICAST_FLT; 2008 2009 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2010 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2011 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2012 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2013 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 2014 2015 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID; 2016 2017 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 2018 2019 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2020 NETIF_F_HW_VLAN_CTAG_FILTER | 2021 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2022 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2023 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2024 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2025 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 2026 2027 netdev->vlan_features |= 2028 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | 2029 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 2030 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2031 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2032 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 2033 2034 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2035 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2036 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2037 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2038 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2039 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 2040 2041 if (pdev->revision >= 0x21) { 2042 netdev->hw_features |= NETIF_F_GRO_HW; 2043 netdev->features |= NETIF_F_GRO_HW; 2044 2045 if (!(h->flags & HNAE3_SUPPORT_VF)) { 2046 netdev->hw_features |= NETIF_F_NTUPLE; 2047 netdev->features |= NETIF_F_NTUPLE; 2048 } 2049 } 2050 } 2051 2052 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 2053 struct hns3_desc_cb *cb) 2054 { 2055 unsigned int order = hnae3_page_order(ring); 2056 struct page *p; 2057 2058 p = dev_alloc_pages(order); 2059 if (!p) 2060 return -ENOMEM; 2061 2062 cb->priv = p; 2063 cb->page_offset = 0; 2064 cb->reuse_flag = 0; 2065 cb->buf = page_address(p); 2066 cb->length = hnae3_page_size(ring); 2067 cb->type = DESC_TYPE_PAGE; 2068 2069 return 0; 2070 } 2071 2072 static void hns3_free_buffer(struct hns3_enet_ring *ring, 2073 struct hns3_desc_cb *cb) 2074 { 2075 if (cb->type == DESC_TYPE_SKB) 2076 dev_kfree_skb_any((struct sk_buff *)cb->priv); 2077 else if (!HNAE3_IS_TX_RING(ring)) 2078 put_page((struct page *)cb->priv); 2079 memset(cb, 0, sizeof(*cb)); 2080 } 2081 2082 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 2083 { 2084 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 2085 cb->length, ring_to_dma_dir(ring)); 2086 2087 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 2088 return -EIO; 2089 2090 return 0; 2091 } 2092 2093 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 2094 struct hns3_desc_cb *cb) 2095 { 2096 if (cb->type == DESC_TYPE_SKB) 2097 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 2098 ring_to_dma_dir(ring)); 2099 else if (cb->length) 2100 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 2101 ring_to_dma_dir(ring)); 2102 } 2103 2104 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 2105 { 2106 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2107 ring->desc[i].addr = 0; 2108 } 2109 2110 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i) 2111 { 2112 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 2113 2114 if (!ring->desc_cb[i].dma) 2115 return; 2116 2117 hns3_buffer_detach(ring, i); 2118 hns3_free_buffer(ring, cb); 2119 } 2120 2121 static void hns3_free_buffers(struct hns3_enet_ring *ring) 2122 { 2123 int i; 2124 2125 for (i = 0; i < ring->desc_num; i++) 2126 hns3_free_buffer_detach(ring, i); 2127 } 2128 2129 /* free desc along with its attached buffer */ 2130 static void hns3_free_desc(struct hns3_enet_ring *ring) 2131 { 2132 int size = ring->desc_num * sizeof(ring->desc[0]); 2133 2134 hns3_free_buffers(ring); 2135 2136 if (ring->desc) { 2137 dma_free_coherent(ring_to_dev(ring), size, 2138 ring->desc, ring->desc_dma_addr); 2139 ring->desc = NULL; 2140 } 2141 } 2142 2143 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 2144 { 2145 int size = ring->desc_num * sizeof(ring->desc[0]); 2146 2147 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 2148 &ring->desc_dma_addr, GFP_KERNEL); 2149 if (!ring->desc) 2150 return -ENOMEM; 2151 2152 return 0; 2153 } 2154 2155 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring, 2156 struct hns3_desc_cb *cb) 2157 { 2158 int ret; 2159 2160 ret = hns3_alloc_buffer(ring, cb); 2161 if (ret) 2162 goto out; 2163 2164 ret = hns3_map_buffer(ring, cb); 2165 if (ret) 2166 goto out_with_buf; 2167 2168 return 0; 2169 2170 out_with_buf: 2171 hns3_free_buffer(ring, cb); 2172 out: 2173 return ret; 2174 } 2175 2176 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i) 2177 { 2178 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]); 2179 2180 if (ret) 2181 return ret; 2182 2183 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2184 2185 return 0; 2186 } 2187 2188 /* Allocate memory for raw pkg, and map with dma */ 2189 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 2190 { 2191 int i, j, ret; 2192 2193 for (i = 0; i < ring->desc_num; i++) { 2194 ret = hns3_alloc_buffer_attach(ring, i); 2195 if (ret) 2196 goto out_buffer_fail; 2197 } 2198 2199 return 0; 2200 2201 out_buffer_fail: 2202 for (j = i - 1; j >= 0; j--) 2203 hns3_free_buffer_detach(ring, j); 2204 return ret; 2205 } 2206 2207 /* detach a in-used buffer and replace with a reserved one */ 2208 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 2209 struct hns3_desc_cb *res_cb) 2210 { 2211 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2212 ring->desc_cb[i] = *res_cb; 2213 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2214 ring->desc[i].rx.bd_base_info = 0; 2215 } 2216 2217 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 2218 { 2219 ring->desc_cb[i].reuse_flag = 0; 2220 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 2221 ring->desc_cb[i].page_offset); 2222 ring->desc[i].rx.bd_base_info = 0; 2223 } 2224 2225 static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head, 2226 int *bytes, int *pkts) 2227 { 2228 int ntc = ring->next_to_clean; 2229 struct hns3_desc_cb *desc_cb; 2230 2231 while (head != ntc) { 2232 desc_cb = &ring->desc_cb[ntc]; 2233 (*pkts) += (desc_cb->type == DESC_TYPE_SKB); 2234 (*bytes) += desc_cb->length; 2235 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */ 2236 hns3_free_buffer_detach(ring, ntc); 2237 2238 if (++ntc == ring->desc_num) 2239 ntc = 0; 2240 2241 /* Issue prefetch for next Tx descriptor */ 2242 prefetch(&ring->desc_cb[ntc]); 2243 } 2244 2245 /* This smp_store_release() pairs with smp_load_acquire() in 2246 * ring_space called by hns3_nic_net_xmit. 2247 */ 2248 smp_store_release(&ring->next_to_clean, ntc); 2249 } 2250 2251 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h) 2252 { 2253 int u = ring->next_to_use; 2254 int c = ring->next_to_clean; 2255 2256 if (unlikely(h > ring->desc_num)) 2257 return 0; 2258 2259 return u > c ? (h > c && h <= u) : (h > c || h <= u); 2260 } 2261 2262 void hns3_clean_tx_ring(struct hns3_enet_ring *ring) 2263 { 2264 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2265 struct hns3_nic_priv *priv = netdev_priv(netdev); 2266 struct netdev_queue *dev_queue; 2267 int bytes, pkts; 2268 int head; 2269 2270 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG); 2271 rmb(); /* Make sure head is ready before touch any data */ 2272 2273 if (is_ring_empty(ring) || head == ring->next_to_clean) 2274 return; /* no data to poll */ 2275 2276 if (unlikely(!is_valid_clean_head(ring, head))) { 2277 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head, 2278 ring->next_to_use, ring->next_to_clean); 2279 2280 u64_stats_update_begin(&ring->syncp); 2281 ring->stats.io_err_cnt++; 2282 u64_stats_update_end(&ring->syncp); 2283 return; 2284 } 2285 2286 bytes = 0; 2287 pkts = 0; 2288 hns3_nic_reclaim_desc(ring, head, &bytes, &pkts); 2289 2290 ring->tqp_vector->tx_group.total_bytes += bytes; 2291 ring->tqp_vector->tx_group.total_packets += pkts; 2292 2293 u64_stats_update_begin(&ring->syncp); 2294 ring->stats.tx_bytes += bytes; 2295 ring->stats.tx_pkts += pkts; 2296 u64_stats_update_end(&ring->syncp); 2297 2298 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 2299 netdev_tx_completed_queue(dev_queue, pkts, bytes); 2300 2301 if (unlikely(pkts && netif_carrier_ok(netdev) && 2302 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) { 2303 /* Make sure that anybody stopping the queue after this 2304 * sees the new next_to_clean. 2305 */ 2306 smp_mb(); 2307 if (netif_tx_queue_stopped(dev_queue) && 2308 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 2309 netif_tx_wake_queue(dev_queue); 2310 ring->stats.restart_queue++; 2311 } 2312 } 2313 } 2314 2315 static int hns3_desc_unused(struct hns3_enet_ring *ring) 2316 { 2317 int ntc = ring->next_to_clean; 2318 int ntu = ring->next_to_use; 2319 2320 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 2321 } 2322 2323 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, 2324 int cleand_count) 2325 { 2326 struct hns3_desc_cb *desc_cb; 2327 struct hns3_desc_cb res_cbs; 2328 int i, ret; 2329 2330 for (i = 0; i < cleand_count; i++) { 2331 desc_cb = &ring->desc_cb[ring->next_to_use]; 2332 if (desc_cb->reuse_flag) { 2333 u64_stats_update_begin(&ring->syncp); 2334 ring->stats.reuse_pg_cnt++; 2335 u64_stats_update_end(&ring->syncp); 2336 2337 hns3_reuse_buffer(ring, ring->next_to_use); 2338 } else { 2339 ret = hns3_reserve_buffer_map(ring, &res_cbs); 2340 if (ret) { 2341 u64_stats_update_begin(&ring->syncp); 2342 ring->stats.sw_err_cnt++; 2343 u64_stats_update_end(&ring->syncp); 2344 2345 netdev_err(ring->tqp->handle->kinfo.netdev, 2346 "hnae reserve buffer map failed.\n"); 2347 break; 2348 } 2349 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 2350 2351 u64_stats_update_begin(&ring->syncp); 2352 ring->stats.non_reuse_pg++; 2353 u64_stats_update_end(&ring->syncp); 2354 } 2355 2356 ring_ptr_move_fw(ring, next_to_use); 2357 } 2358 2359 wmb(); /* Make all data has been write before submit */ 2360 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2361 } 2362 2363 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2364 struct hns3_enet_ring *ring, int pull_len, 2365 struct hns3_desc_cb *desc_cb) 2366 { 2367 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 2368 int size = le16_to_cpu(desc->rx.size); 2369 u32 truesize = hnae3_buf_size(ring); 2370 2371 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2372 size - pull_len, truesize); 2373 2374 /* Avoid re-using remote pages, or the stack is still using the page 2375 * when page_offset rollback to zero, flag default unreuse 2376 */ 2377 if (unlikely(page_to_nid(desc_cb->priv) != numa_mem_id()) || 2378 (!desc_cb->page_offset && page_count(desc_cb->priv) > 1)) 2379 return; 2380 2381 /* Move offset up to the next cache line */ 2382 desc_cb->page_offset += truesize; 2383 2384 if (desc_cb->page_offset + truesize <= hnae3_page_size(ring)) { 2385 desc_cb->reuse_flag = 1; 2386 /* Bump ref count on page before it is given */ 2387 get_page(desc_cb->priv); 2388 } else if (page_count(desc_cb->priv) == 1) { 2389 desc_cb->reuse_flag = 1; 2390 desc_cb->page_offset = 0; 2391 get_page(desc_cb->priv); 2392 } 2393 } 2394 2395 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) 2396 { 2397 __be16 type = skb->protocol; 2398 struct tcphdr *th; 2399 int depth = 0; 2400 2401 while (eth_type_vlan(type)) { 2402 struct vlan_hdr *vh; 2403 2404 if ((depth + VLAN_HLEN) > skb_headlen(skb)) 2405 return -EFAULT; 2406 2407 vh = (struct vlan_hdr *)(skb->data + depth); 2408 type = vh->h_vlan_encapsulated_proto; 2409 depth += VLAN_HLEN; 2410 } 2411 2412 skb_set_network_header(skb, depth); 2413 2414 if (type == htons(ETH_P_IP)) { 2415 const struct iphdr *iph = ip_hdr(skb); 2416 2417 depth += sizeof(struct iphdr); 2418 skb_set_transport_header(skb, depth); 2419 th = tcp_hdr(skb); 2420 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr, 2421 iph->daddr, 0); 2422 } else if (type == htons(ETH_P_IPV6)) { 2423 const struct ipv6hdr *iph = ipv6_hdr(skb); 2424 2425 depth += sizeof(struct ipv6hdr); 2426 skb_set_transport_header(skb, depth); 2427 th = tcp_hdr(skb); 2428 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr, 2429 &iph->daddr, 0); 2430 } else { 2431 netdev_err(skb->dev, 2432 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n", 2433 be16_to_cpu(type), depth); 2434 return -EFAULT; 2435 } 2436 2437 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 2438 if (th->cwr) 2439 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 2440 2441 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B)) 2442 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID; 2443 2444 skb->csum_start = (unsigned char *)th - skb->head; 2445 skb->csum_offset = offsetof(struct tcphdr, check); 2446 skb->ip_summed = CHECKSUM_PARTIAL; 2447 return 0; 2448 } 2449 2450 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2451 u32 l234info, u32 bd_base_info, u32 ol_info) 2452 { 2453 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2454 int l3_type, l4_type; 2455 int ol4_type; 2456 2457 skb->ip_summed = CHECKSUM_NONE; 2458 2459 skb_checksum_none_assert(skb); 2460 2461 if (!(netdev->features & NETIF_F_RXCSUM)) 2462 return; 2463 2464 /* check if hardware has done checksum */ 2465 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 2466 return; 2467 2468 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | 2469 BIT(HNS3_RXD_OL3E_B) | 2470 BIT(HNS3_RXD_OL4E_B)))) { 2471 u64_stats_update_begin(&ring->syncp); 2472 ring->stats.l3l4_csum_err++; 2473 u64_stats_update_end(&ring->syncp); 2474 2475 return; 2476 } 2477 2478 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M, 2479 HNS3_RXD_OL4ID_S); 2480 switch (ol4_type) { 2481 case HNS3_OL4_TYPE_MAC_IN_UDP: 2482 case HNS3_OL4_TYPE_NVGRE: 2483 skb->csum_level = 1; 2484 /* fall through */ 2485 case HNS3_OL4_TYPE_NO_TUN: 2486 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2487 HNS3_RXD_L3ID_S); 2488 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 2489 HNS3_RXD_L4ID_S); 2490 2491 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 2492 if ((l3_type == HNS3_L3_TYPE_IPV4 || 2493 l3_type == HNS3_L3_TYPE_IPV6) && 2494 (l4_type == HNS3_L4_TYPE_UDP || 2495 l4_type == HNS3_L4_TYPE_TCP || 2496 l4_type == HNS3_L4_TYPE_SCTP)) 2497 skb->ip_summed = CHECKSUM_UNNECESSARY; 2498 break; 2499 default: 2500 break; 2501 } 2502 } 2503 2504 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 2505 { 2506 if (skb_has_frag_list(skb)) 2507 napi_gro_flush(&ring->tqp_vector->napi, false); 2508 2509 napi_gro_receive(&ring->tqp_vector->napi, skb); 2510 } 2511 2512 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 2513 struct hns3_desc *desc, u32 l234info, 2514 u16 *vlan_tag) 2515 { 2516 struct hnae3_handle *handle = ring->tqp->handle; 2517 struct pci_dev *pdev = ring->tqp->handle->pdev; 2518 2519 if (pdev->revision == 0x20) { 2520 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2521 if (!(*vlan_tag & VLAN_VID_MASK)) 2522 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2523 2524 return (*vlan_tag != 0); 2525 } 2526 2527 #define HNS3_STRP_OUTER_VLAN 0x1 2528 #define HNS3_STRP_INNER_VLAN 0x2 2529 #define HNS3_STRP_BOTH 0x3 2530 2531 /* Hardware always insert VLAN tag into RX descriptor when 2532 * remove the tag from packet, driver needs to determine 2533 * reporting which tag to stack. 2534 */ 2535 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 2536 HNS3_RXD_STRP_TAGP_S)) { 2537 case HNS3_STRP_OUTER_VLAN: 2538 if (handle->port_base_vlan_state != 2539 HNAE3_PORT_BASE_VLAN_DISABLE) 2540 return false; 2541 2542 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2543 return true; 2544 case HNS3_STRP_INNER_VLAN: 2545 if (handle->port_base_vlan_state != 2546 HNAE3_PORT_BASE_VLAN_DISABLE) 2547 return false; 2548 2549 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2550 return true; 2551 case HNS3_STRP_BOTH: 2552 if (handle->port_base_vlan_state == 2553 HNAE3_PORT_BASE_VLAN_DISABLE) 2554 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2555 else 2556 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2557 2558 return true; 2559 default: 2560 return false; 2561 } 2562 } 2563 2564 static int hns3_alloc_skb(struct hns3_enet_ring *ring, int length, 2565 unsigned char *va) 2566 { 2567 #define HNS3_NEED_ADD_FRAG 1 2568 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2569 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2570 struct sk_buff *skb; 2571 2572 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 2573 skb = ring->skb; 2574 if (unlikely(!skb)) { 2575 netdev_err(netdev, "alloc rx skb fail\n"); 2576 2577 u64_stats_update_begin(&ring->syncp); 2578 ring->stats.sw_err_cnt++; 2579 u64_stats_update_end(&ring->syncp); 2580 2581 return -ENOMEM; 2582 } 2583 2584 prefetchw(skb->data); 2585 2586 ring->pending_buf = 1; 2587 ring->frag_num = 0; 2588 ring->tail_skb = NULL; 2589 if (length <= HNS3_RX_HEAD_SIZE) { 2590 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 2591 2592 /* We can reuse buffer as-is, just make sure it is local */ 2593 if (likely(page_to_nid(desc_cb->priv) == numa_mem_id())) 2594 desc_cb->reuse_flag = 1; 2595 else /* This page cannot be reused so discard it */ 2596 put_page(desc_cb->priv); 2597 2598 ring_ptr_move_fw(ring, next_to_clean); 2599 return 0; 2600 } 2601 u64_stats_update_begin(&ring->syncp); 2602 ring->stats.seg_pkt_cnt++; 2603 u64_stats_update_end(&ring->syncp); 2604 2605 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE); 2606 __skb_put(skb, ring->pull_len); 2607 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 2608 desc_cb); 2609 ring_ptr_move_fw(ring, next_to_clean); 2610 2611 return HNS3_NEED_ADD_FRAG; 2612 } 2613 2614 static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc, 2615 struct sk_buff **out_skb, bool pending) 2616 { 2617 struct sk_buff *skb = *out_skb; 2618 struct sk_buff *head_skb = *out_skb; 2619 struct sk_buff *new_skb; 2620 struct hns3_desc_cb *desc_cb; 2621 struct hns3_desc *pre_desc; 2622 u32 bd_base_info; 2623 int pre_bd; 2624 2625 /* if there is pending bd, the SW param next_to_clean has moved 2626 * to next and the next is NULL 2627 */ 2628 if (pending) { 2629 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) % 2630 ring->desc_num; 2631 pre_desc = &ring->desc[pre_bd]; 2632 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info); 2633 } else { 2634 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2635 } 2636 2637 while (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { 2638 desc = &ring->desc[ring->next_to_clean]; 2639 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2640 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2641 /* make sure HW write desc complete */ 2642 dma_rmb(); 2643 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 2644 return -ENXIO; 2645 2646 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 2647 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 2648 HNS3_RX_HEAD_SIZE); 2649 if (unlikely(!new_skb)) { 2650 netdev_err(ring->tqp->handle->kinfo.netdev, 2651 "alloc rx skb frag fail\n"); 2652 return -ENXIO; 2653 } 2654 ring->frag_num = 0; 2655 2656 if (ring->tail_skb) { 2657 ring->tail_skb->next = new_skb; 2658 ring->tail_skb = new_skb; 2659 } else { 2660 skb_shinfo(skb)->frag_list = new_skb; 2661 ring->tail_skb = new_skb; 2662 } 2663 } 2664 2665 if (ring->tail_skb) { 2666 head_skb->truesize += hnae3_buf_size(ring); 2667 head_skb->data_len += le16_to_cpu(desc->rx.size); 2668 head_skb->len += le16_to_cpu(desc->rx.size); 2669 skb = ring->tail_skb; 2670 } 2671 2672 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 2673 ring_ptr_move_fw(ring, next_to_clean); 2674 ring->pending_buf++; 2675 } 2676 2677 return 0; 2678 } 2679 2680 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring, 2681 struct sk_buff *skb, u32 l234info, 2682 u32 bd_base_info, u32 ol_info) 2683 { 2684 u32 l3_type; 2685 2686 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 2687 HNS3_RXD_GRO_SIZE_M, 2688 HNS3_RXD_GRO_SIZE_S); 2689 /* if there is no HW GRO, do not set gro params */ 2690 if (!skb_shinfo(skb)->gso_size) { 2691 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info); 2692 return 0; 2693 } 2694 2695 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info, 2696 HNS3_RXD_GRO_COUNT_M, 2697 HNS3_RXD_GRO_COUNT_S); 2698 2699 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S); 2700 if (l3_type == HNS3_L3_TYPE_IPV4) 2701 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 2702 else if (l3_type == HNS3_L3_TYPE_IPV6) 2703 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 2704 else 2705 return -EFAULT; 2706 2707 return hns3_gro_complete(skb, l234info); 2708 } 2709 2710 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 2711 struct sk_buff *skb, u32 rss_hash) 2712 { 2713 struct hnae3_handle *handle = ring->tqp->handle; 2714 enum pkt_hash_types rss_type; 2715 2716 if (rss_hash) 2717 rss_type = handle->kinfo.rss_type; 2718 else 2719 rss_type = PKT_HASH_TYPE_NONE; 2720 2721 skb_set_hash(skb, rss_hash, rss_type); 2722 } 2723 2724 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb) 2725 { 2726 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2727 enum hns3_pkt_l2t_type l2_frame_type; 2728 u32 bd_base_info, l234info, ol_info; 2729 struct hns3_desc *desc; 2730 unsigned int len; 2731 int pre_ntc, ret; 2732 2733 /* bdinfo handled below is only valid on the last BD of the 2734 * current packet, and ring->next_to_clean indicates the first 2735 * descriptor of next packet, so need - 1 below. 2736 */ 2737 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) : 2738 (ring->desc_num - 1); 2739 desc = &ring->desc[pre_ntc]; 2740 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2741 l234info = le32_to_cpu(desc->rx.l234_info); 2742 ol_info = le32_to_cpu(desc->rx.ol_info); 2743 2744 /* Based on hw strategy, the tag offloaded will be stored at 2745 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 2746 * in one layer tag case. 2747 */ 2748 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 2749 u16 vlan_tag; 2750 2751 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 2752 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 2753 vlan_tag); 2754 } 2755 2756 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) { 2757 u64_stats_update_begin(&ring->syncp); 2758 ring->stats.non_vld_descs++; 2759 u64_stats_update_end(&ring->syncp); 2760 2761 return -EINVAL; 2762 } 2763 2764 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 2765 BIT(HNS3_RXD_L2E_B))))) { 2766 u64_stats_update_begin(&ring->syncp); 2767 if (l234info & BIT(HNS3_RXD_L2E_B)) 2768 ring->stats.l2_err++; 2769 else 2770 ring->stats.err_pkt_len++; 2771 u64_stats_update_end(&ring->syncp); 2772 2773 return -EFAULT; 2774 } 2775 2776 len = skb->len; 2777 2778 /* Do update ip stack process */ 2779 skb->protocol = eth_type_trans(skb, netdev); 2780 2781 /* This is needed in order to enable forwarding support */ 2782 ret = hns3_set_gro_and_checksum(ring, skb, l234info, 2783 bd_base_info, ol_info); 2784 if (unlikely(ret)) { 2785 u64_stats_update_begin(&ring->syncp); 2786 ring->stats.rx_err_cnt++; 2787 u64_stats_update_end(&ring->syncp); 2788 return ret; 2789 } 2790 2791 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 2792 HNS3_RXD_DMAC_S); 2793 2794 u64_stats_update_begin(&ring->syncp); 2795 ring->stats.rx_pkts++; 2796 ring->stats.rx_bytes += len; 2797 2798 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 2799 ring->stats.rx_multicast++; 2800 2801 u64_stats_update_end(&ring->syncp); 2802 2803 ring->tqp_vector->rx_group.total_bytes += len; 2804 2805 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash)); 2806 return 0; 2807 } 2808 2809 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring, 2810 struct sk_buff **out_skb) 2811 { 2812 struct sk_buff *skb = ring->skb; 2813 struct hns3_desc_cb *desc_cb; 2814 struct hns3_desc *desc; 2815 u32 bd_base_info; 2816 int length; 2817 int ret; 2818 2819 desc = &ring->desc[ring->next_to_clean]; 2820 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2821 2822 prefetch(desc); 2823 2824 length = le16_to_cpu(desc->rx.size); 2825 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2826 2827 /* Check valid BD */ 2828 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 2829 return -ENXIO; 2830 2831 if (!skb) 2832 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset; 2833 2834 /* Prefetch first cache line of first page 2835 * Idea is to cache few bytes of the header of the packet. Our L1 Cache 2836 * line size is 64B so need to prefetch twice to make it 128B. But in 2837 * actual we can have greater size of caches with 128B Level 1 cache 2838 * lines. In such a case, single fetch would suffice to cache in the 2839 * relevant part of the header. 2840 */ 2841 prefetch(ring->va); 2842 #if L1_CACHE_BYTES < 128 2843 prefetch(ring->va + L1_CACHE_BYTES); 2844 #endif 2845 2846 if (!skb) { 2847 ret = hns3_alloc_skb(ring, length, ring->va); 2848 *out_skb = skb = ring->skb; 2849 2850 if (ret < 0) /* alloc buffer fail */ 2851 return ret; 2852 if (ret > 0) { /* need add frag */ 2853 ret = hns3_add_frag(ring, desc, &skb, false); 2854 if (ret) 2855 return ret; 2856 2857 /* As the head data may be changed when GRO enable, copy 2858 * the head data in after other data rx completed 2859 */ 2860 memcpy(skb->data, ring->va, 2861 ALIGN(ring->pull_len, sizeof(long))); 2862 } 2863 } else { 2864 ret = hns3_add_frag(ring, desc, &skb, true); 2865 if (ret) 2866 return ret; 2867 2868 /* As the head data may be changed when GRO enable, copy 2869 * the head data in after other data rx completed 2870 */ 2871 memcpy(skb->data, ring->va, 2872 ALIGN(ring->pull_len, sizeof(long))); 2873 } 2874 2875 ret = hns3_handle_bdinfo(ring, skb); 2876 if (unlikely(ret)) { 2877 dev_kfree_skb_any(skb); 2878 return ret; 2879 } 2880 2881 skb_record_rx_queue(skb, ring->tqp->tqp_index); 2882 *out_skb = skb; 2883 2884 return 0; 2885 } 2886 2887 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget, 2888 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 2889 { 2890 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 2891 int recv_pkts, recv_bds, clean_count, err; 2892 int unused_count = hns3_desc_unused(ring); 2893 struct sk_buff *skb = ring->skb; 2894 int num; 2895 2896 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG); 2897 rmb(); /* Make sure num taken effect before the other data is touched */ 2898 2899 recv_pkts = 0, recv_bds = 0, clean_count = 0; 2900 num -= unused_count; 2901 unused_count -= ring->pending_buf; 2902 2903 while (recv_pkts < budget && recv_bds < num) { 2904 /* Reuse or realloc buffers */ 2905 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 2906 hns3_nic_alloc_rx_buffers(ring, 2907 clean_count + unused_count); 2908 clean_count = 0; 2909 unused_count = hns3_desc_unused(ring) - 2910 ring->pending_buf; 2911 } 2912 2913 /* Poll one pkt */ 2914 err = hns3_handle_rx_bd(ring, &skb); 2915 if (unlikely(!skb)) /* This fault cannot be repaired */ 2916 goto out; 2917 2918 if (err == -ENXIO) { /* Do not get FE for the packet */ 2919 goto out; 2920 } else if (unlikely(err)) { /* Do jump the err */ 2921 recv_bds += ring->pending_buf; 2922 clean_count += ring->pending_buf; 2923 ring->skb = NULL; 2924 ring->pending_buf = 0; 2925 continue; 2926 } 2927 2928 rx_fn(ring, skb); 2929 recv_bds += ring->pending_buf; 2930 clean_count += ring->pending_buf; 2931 ring->skb = NULL; 2932 ring->pending_buf = 0; 2933 2934 recv_pkts++; 2935 } 2936 2937 out: 2938 /* Make all data has been write before submit */ 2939 if (clean_count + unused_count > 0) 2940 hns3_nic_alloc_rx_buffers(ring, clean_count + unused_count); 2941 2942 return recv_pkts; 2943 } 2944 2945 static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group) 2946 { 2947 #define HNS3_RX_LOW_BYTE_RATE 10000 2948 #define HNS3_RX_MID_BYTE_RATE 20000 2949 #define HNS3_RX_ULTRA_PACKET_RATE 40 2950 2951 enum hns3_flow_level_range new_flow_level; 2952 struct hns3_enet_tqp_vector *tqp_vector; 2953 int packets_per_msecs, bytes_per_msecs; 2954 u32 time_passed_ms; 2955 2956 tqp_vector = ring_group->ring->tqp_vector; 2957 time_passed_ms = 2958 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 2959 if (!time_passed_ms) 2960 return false; 2961 2962 do_div(ring_group->total_packets, time_passed_ms); 2963 packets_per_msecs = ring_group->total_packets; 2964 2965 do_div(ring_group->total_bytes, time_passed_ms); 2966 bytes_per_msecs = ring_group->total_bytes; 2967 2968 new_flow_level = ring_group->coal.flow_level; 2969 2970 /* Simple throttlerate management 2971 * 0-10MB/s lower (50000 ints/s) 2972 * 10-20MB/s middle (20000 ints/s) 2973 * 20-1249MB/s high (18000 ints/s) 2974 * > 40000pps ultra (8000 ints/s) 2975 */ 2976 switch (new_flow_level) { 2977 case HNS3_FLOW_LOW: 2978 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 2979 new_flow_level = HNS3_FLOW_MID; 2980 break; 2981 case HNS3_FLOW_MID: 2982 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 2983 new_flow_level = HNS3_FLOW_HIGH; 2984 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 2985 new_flow_level = HNS3_FLOW_LOW; 2986 break; 2987 case HNS3_FLOW_HIGH: 2988 case HNS3_FLOW_ULTRA: 2989 default: 2990 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 2991 new_flow_level = HNS3_FLOW_MID; 2992 break; 2993 } 2994 2995 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 2996 &tqp_vector->rx_group == ring_group) 2997 new_flow_level = HNS3_FLOW_ULTRA; 2998 2999 ring_group->total_bytes = 0; 3000 ring_group->total_packets = 0; 3001 ring_group->coal.flow_level = new_flow_level; 3002 3003 return true; 3004 } 3005 3006 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 3007 { 3008 struct hns3_enet_tqp_vector *tqp_vector; 3009 u16 new_int_gl; 3010 3011 if (!ring_group->ring) 3012 return false; 3013 3014 tqp_vector = ring_group->ring->tqp_vector; 3015 if (!tqp_vector->last_jiffies) 3016 return false; 3017 3018 if (ring_group->total_packets == 0) { 3019 ring_group->coal.int_gl = HNS3_INT_GL_50K; 3020 ring_group->coal.flow_level = HNS3_FLOW_LOW; 3021 return true; 3022 } 3023 3024 if (!hns3_get_new_flow_lvl(ring_group)) 3025 return false; 3026 3027 new_int_gl = ring_group->coal.int_gl; 3028 switch (ring_group->coal.flow_level) { 3029 case HNS3_FLOW_LOW: 3030 new_int_gl = HNS3_INT_GL_50K; 3031 break; 3032 case HNS3_FLOW_MID: 3033 new_int_gl = HNS3_INT_GL_20K; 3034 break; 3035 case HNS3_FLOW_HIGH: 3036 new_int_gl = HNS3_INT_GL_18K; 3037 break; 3038 case HNS3_FLOW_ULTRA: 3039 new_int_gl = HNS3_INT_GL_8K; 3040 break; 3041 default: 3042 break; 3043 } 3044 3045 if (new_int_gl != ring_group->coal.int_gl) { 3046 ring_group->coal.int_gl = new_int_gl; 3047 return true; 3048 } 3049 return false; 3050 } 3051 3052 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 3053 { 3054 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 3055 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 3056 bool rx_update, tx_update; 3057 3058 /* update param every 1000ms */ 3059 if (time_before(jiffies, 3060 tqp_vector->last_jiffies + msecs_to_jiffies(1000))) 3061 return; 3062 3063 if (rx_group->coal.gl_adapt_enable) { 3064 rx_update = hns3_get_new_int_gl(rx_group); 3065 if (rx_update) 3066 hns3_set_vector_coalesce_rx_gl(tqp_vector, 3067 rx_group->coal.int_gl); 3068 } 3069 3070 if (tx_group->coal.gl_adapt_enable) { 3071 tx_update = hns3_get_new_int_gl(tx_group); 3072 if (tx_update) 3073 hns3_set_vector_coalesce_tx_gl(tqp_vector, 3074 tx_group->coal.int_gl); 3075 } 3076 3077 tqp_vector->last_jiffies = jiffies; 3078 } 3079 3080 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 3081 { 3082 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 3083 struct hns3_enet_ring *ring; 3084 int rx_pkt_total = 0; 3085 3086 struct hns3_enet_tqp_vector *tqp_vector = 3087 container_of(napi, struct hns3_enet_tqp_vector, napi); 3088 bool clean_complete = true; 3089 int rx_budget = budget; 3090 3091 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3092 napi_complete(napi); 3093 return 0; 3094 } 3095 3096 /* Since the actual Tx work is minimal, we can give the Tx a larger 3097 * budget and be more aggressive about cleaning up the Tx descriptors. 3098 */ 3099 hns3_for_each_ring(ring, tqp_vector->tx_group) 3100 hns3_clean_tx_ring(ring); 3101 3102 /* make sure rx ring budget not smaller than 1 */ 3103 if (tqp_vector->num_tqps > 1) 3104 rx_budget = max(budget / tqp_vector->num_tqps, 1); 3105 3106 hns3_for_each_ring(ring, tqp_vector->rx_group) { 3107 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 3108 hns3_rx_skb); 3109 3110 if (rx_cleaned >= rx_budget) 3111 clean_complete = false; 3112 3113 rx_pkt_total += rx_cleaned; 3114 } 3115 3116 tqp_vector->rx_group.total_packets += rx_pkt_total; 3117 3118 if (!clean_complete) 3119 return budget; 3120 3121 if (napi_complete(napi) && 3122 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3123 hns3_update_new_int_gl(tqp_vector); 3124 hns3_mask_vector_irq(tqp_vector, 1); 3125 } 3126 3127 return rx_pkt_total; 3128 } 3129 3130 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3131 struct hnae3_ring_chain_node *head) 3132 { 3133 struct pci_dev *pdev = tqp_vector->handle->pdev; 3134 struct hnae3_ring_chain_node *cur_chain = head; 3135 struct hnae3_ring_chain_node *chain; 3136 struct hns3_enet_ring *tx_ring; 3137 struct hns3_enet_ring *rx_ring; 3138 3139 tx_ring = tqp_vector->tx_group.ring; 3140 if (tx_ring) { 3141 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 3142 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3143 HNAE3_RING_TYPE_TX); 3144 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3145 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 3146 3147 cur_chain->next = NULL; 3148 3149 while (tx_ring->next) { 3150 tx_ring = tx_ring->next; 3151 3152 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 3153 GFP_KERNEL); 3154 if (!chain) 3155 goto err_free_chain; 3156 3157 cur_chain->next = chain; 3158 chain->tqp_index = tx_ring->tqp->tqp_index; 3159 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3160 HNAE3_RING_TYPE_TX); 3161 hnae3_set_field(chain->int_gl_idx, 3162 HNAE3_RING_GL_IDX_M, 3163 HNAE3_RING_GL_IDX_S, 3164 HNAE3_RING_GL_TX); 3165 3166 cur_chain = chain; 3167 } 3168 } 3169 3170 rx_ring = tqp_vector->rx_group.ring; 3171 if (!tx_ring && rx_ring) { 3172 cur_chain->next = NULL; 3173 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 3174 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3175 HNAE3_RING_TYPE_RX); 3176 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3177 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3178 3179 rx_ring = rx_ring->next; 3180 } 3181 3182 while (rx_ring) { 3183 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 3184 if (!chain) 3185 goto err_free_chain; 3186 3187 cur_chain->next = chain; 3188 chain->tqp_index = rx_ring->tqp->tqp_index; 3189 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3190 HNAE3_RING_TYPE_RX); 3191 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3192 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3193 3194 cur_chain = chain; 3195 3196 rx_ring = rx_ring->next; 3197 } 3198 3199 return 0; 3200 3201 err_free_chain: 3202 cur_chain = head->next; 3203 while (cur_chain) { 3204 chain = cur_chain->next; 3205 devm_kfree(&pdev->dev, cur_chain); 3206 cur_chain = chain; 3207 } 3208 head->next = NULL; 3209 3210 return -ENOMEM; 3211 } 3212 3213 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3214 struct hnae3_ring_chain_node *head) 3215 { 3216 struct pci_dev *pdev = tqp_vector->handle->pdev; 3217 struct hnae3_ring_chain_node *chain_tmp, *chain; 3218 3219 chain = head->next; 3220 3221 while (chain) { 3222 chain_tmp = chain->next; 3223 devm_kfree(&pdev->dev, chain); 3224 chain = chain_tmp; 3225 } 3226 } 3227 3228 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 3229 struct hns3_enet_ring *ring) 3230 { 3231 ring->next = group->ring; 3232 group->ring = ring; 3233 3234 group->count++; 3235 } 3236 3237 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 3238 { 3239 struct pci_dev *pdev = priv->ae_handle->pdev; 3240 struct hns3_enet_tqp_vector *tqp_vector; 3241 int num_vectors = priv->vector_num; 3242 int numa_node; 3243 int vector_i; 3244 3245 numa_node = dev_to_node(&pdev->dev); 3246 3247 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 3248 tqp_vector = &priv->tqp_vector[vector_i]; 3249 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 3250 &tqp_vector->affinity_mask); 3251 } 3252 } 3253 3254 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 3255 { 3256 struct hnae3_ring_chain_node vector_ring_chain; 3257 struct hnae3_handle *h = priv->ae_handle; 3258 struct hns3_enet_tqp_vector *tqp_vector; 3259 int ret = 0; 3260 int i; 3261 3262 hns3_nic_set_cpumask(priv); 3263 3264 for (i = 0; i < priv->vector_num; i++) { 3265 tqp_vector = &priv->tqp_vector[i]; 3266 hns3_vector_gl_rl_init_hw(tqp_vector, priv); 3267 tqp_vector->num_tqps = 0; 3268 } 3269 3270 for (i = 0; i < h->kinfo.num_tqps; i++) { 3271 u16 vector_i = i % priv->vector_num; 3272 u16 tqp_num = h->kinfo.num_tqps; 3273 3274 tqp_vector = &priv->tqp_vector[vector_i]; 3275 3276 hns3_add_ring_to_group(&tqp_vector->tx_group, 3277 priv->ring_data[i].ring); 3278 3279 hns3_add_ring_to_group(&tqp_vector->rx_group, 3280 priv->ring_data[i + tqp_num].ring); 3281 3282 priv->ring_data[i].ring->tqp_vector = tqp_vector; 3283 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector; 3284 tqp_vector->num_tqps++; 3285 } 3286 3287 for (i = 0; i < priv->vector_num; i++) { 3288 tqp_vector = &priv->tqp_vector[i]; 3289 3290 tqp_vector->rx_group.total_bytes = 0; 3291 tqp_vector->rx_group.total_packets = 0; 3292 tqp_vector->tx_group.total_bytes = 0; 3293 tqp_vector->tx_group.total_packets = 0; 3294 tqp_vector->handle = h; 3295 3296 ret = hns3_get_vector_ring_chain(tqp_vector, 3297 &vector_ring_chain); 3298 if (ret) 3299 goto map_ring_fail; 3300 3301 ret = h->ae_algo->ops->map_ring_to_vector(h, 3302 tqp_vector->vector_irq, &vector_ring_chain); 3303 3304 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3305 3306 if (ret) 3307 goto map_ring_fail; 3308 3309 netif_napi_add(priv->netdev, &tqp_vector->napi, 3310 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 3311 } 3312 3313 return 0; 3314 3315 map_ring_fail: 3316 while (i--) 3317 netif_napi_del(&priv->tqp_vector[i].napi); 3318 3319 return ret; 3320 } 3321 3322 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 3323 { 3324 #define HNS3_VECTOR_PF_MAX_NUM 64 3325 3326 struct hnae3_handle *h = priv->ae_handle; 3327 struct hns3_enet_tqp_vector *tqp_vector; 3328 struct hnae3_vector_info *vector; 3329 struct pci_dev *pdev = h->pdev; 3330 u16 tqp_num = h->kinfo.num_tqps; 3331 u16 vector_num; 3332 int ret = 0; 3333 u16 i; 3334 3335 /* RSS size, cpu online and vector_num should be the same */ 3336 /* Should consider 2p/4p later */ 3337 vector_num = min_t(u16, num_online_cpus(), tqp_num); 3338 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM); 3339 3340 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 3341 GFP_KERNEL); 3342 if (!vector) 3343 return -ENOMEM; 3344 3345 /* save the actual available vector number */ 3346 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 3347 3348 priv->vector_num = vector_num; 3349 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 3350 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 3351 GFP_KERNEL); 3352 if (!priv->tqp_vector) { 3353 ret = -ENOMEM; 3354 goto out; 3355 } 3356 3357 for (i = 0; i < priv->vector_num; i++) { 3358 tqp_vector = &priv->tqp_vector[i]; 3359 tqp_vector->idx = i; 3360 tqp_vector->mask_addr = vector[i].io_addr; 3361 tqp_vector->vector_irq = vector[i].vector; 3362 hns3_vector_gl_rl_init(tqp_vector, priv); 3363 } 3364 3365 out: 3366 devm_kfree(&pdev->dev, vector); 3367 return ret; 3368 } 3369 3370 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 3371 { 3372 group->ring = NULL; 3373 group->count = 0; 3374 } 3375 3376 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 3377 { 3378 struct hnae3_ring_chain_node vector_ring_chain; 3379 struct hnae3_handle *h = priv->ae_handle; 3380 struct hns3_enet_tqp_vector *tqp_vector; 3381 int i; 3382 3383 for (i = 0; i < priv->vector_num; i++) { 3384 tqp_vector = &priv->tqp_vector[i]; 3385 3386 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 3387 continue; 3388 3389 hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain); 3390 3391 h->ae_algo->ops->unmap_ring_from_vector(h, 3392 tqp_vector->vector_irq, &vector_ring_chain); 3393 3394 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3395 3396 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) { 3397 irq_set_affinity_hint(tqp_vector->vector_irq, NULL); 3398 free_irq(tqp_vector->vector_irq, tqp_vector); 3399 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED; 3400 } 3401 3402 hns3_clear_ring_group(&tqp_vector->rx_group); 3403 hns3_clear_ring_group(&tqp_vector->tx_group); 3404 netif_napi_del(&priv->tqp_vector[i].napi); 3405 } 3406 } 3407 3408 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 3409 { 3410 struct hnae3_handle *h = priv->ae_handle; 3411 struct pci_dev *pdev = h->pdev; 3412 int i, ret; 3413 3414 for (i = 0; i < priv->vector_num; i++) { 3415 struct hns3_enet_tqp_vector *tqp_vector; 3416 3417 tqp_vector = &priv->tqp_vector[i]; 3418 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 3419 if (ret) 3420 return ret; 3421 } 3422 3423 devm_kfree(&pdev->dev, priv->tqp_vector); 3424 return 0; 3425 } 3426 3427 static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 3428 unsigned int ring_type) 3429 { 3430 struct hns3_nic_ring_data *ring_data = priv->ring_data; 3431 int queue_num = priv->ae_handle->kinfo.num_tqps; 3432 struct pci_dev *pdev = priv->ae_handle->pdev; 3433 struct hns3_enet_ring *ring; 3434 int desc_num; 3435 3436 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL); 3437 if (!ring) 3438 return -ENOMEM; 3439 3440 if (ring_type == HNAE3_RING_TYPE_TX) { 3441 desc_num = priv->ae_handle->kinfo.num_tx_desc; 3442 ring_data[q->tqp_index].ring = ring; 3443 ring_data[q->tqp_index].queue_index = q->tqp_index; 3444 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET; 3445 } else { 3446 desc_num = priv->ae_handle->kinfo.num_rx_desc; 3447 ring_data[q->tqp_index + queue_num].ring = ring; 3448 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index; 3449 ring->io_base = q->io_base; 3450 } 3451 3452 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 3453 3454 ring->tqp = q; 3455 ring->desc = NULL; 3456 ring->desc_cb = NULL; 3457 ring->dev = priv->dev; 3458 ring->desc_dma_addr = 0; 3459 ring->buf_size = q->buf_size; 3460 ring->desc_num = desc_num; 3461 ring->next_to_use = 0; 3462 ring->next_to_clean = 0; 3463 3464 return 0; 3465 } 3466 3467 static int hns3_queue_to_ring(struct hnae3_queue *tqp, 3468 struct hns3_nic_priv *priv) 3469 { 3470 int ret; 3471 3472 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 3473 if (ret) 3474 return ret; 3475 3476 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 3477 if (ret) { 3478 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring); 3479 return ret; 3480 } 3481 3482 return 0; 3483 } 3484 3485 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 3486 { 3487 struct hnae3_handle *h = priv->ae_handle; 3488 struct pci_dev *pdev = h->pdev; 3489 int i, ret; 3490 3491 priv->ring_data = devm_kzalloc(&pdev->dev, 3492 array3_size(h->kinfo.num_tqps, 3493 sizeof(*priv->ring_data), 3494 2), 3495 GFP_KERNEL); 3496 if (!priv->ring_data) 3497 return -ENOMEM; 3498 3499 for (i = 0; i < h->kinfo.num_tqps; i++) { 3500 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv); 3501 if (ret) 3502 goto err; 3503 } 3504 3505 return 0; 3506 err: 3507 while (i--) { 3508 devm_kfree(priv->dev, priv->ring_data[i].ring); 3509 devm_kfree(priv->dev, 3510 priv->ring_data[i + h->kinfo.num_tqps].ring); 3511 } 3512 3513 devm_kfree(&pdev->dev, priv->ring_data); 3514 priv->ring_data = NULL; 3515 return ret; 3516 } 3517 3518 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 3519 { 3520 struct hnae3_handle *h = priv->ae_handle; 3521 int i; 3522 3523 if (!priv->ring_data) 3524 return; 3525 3526 for (i = 0; i < h->kinfo.num_tqps; i++) { 3527 devm_kfree(priv->dev, priv->ring_data[i].ring); 3528 devm_kfree(priv->dev, 3529 priv->ring_data[i + h->kinfo.num_tqps].ring); 3530 } 3531 devm_kfree(priv->dev, priv->ring_data); 3532 priv->ring_data = NULL; 3533 } 3534 3535 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 3536 { 3537 int ret; 3538 3539 if (ring->desc_num <= 0 || ring->buf_size <= 0) 3540 return -EINVAL; 3541 3542 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num, 3543 sizeof(ring->desc_cb[0]), GFP_KERNEL); 3544 if (!ring->desc_cb) { 3545 ret = -ENOMEM; 3546 goto out; 3547 } 3548 3549 ret = hns3_alloc_desc(ring); 3550 if (ret) 3551 goto out_with_desc_cb; 3552 3553 if (!HNAE3_IS_TX_RING(ring)) { 3554 ret = hns3_alloc_ring_buffers(ring); 3555 if (ret) 3556 goto out_with_desc; 3557 } 3558 3559 return 0; 3560 3561 out_with_desc: 3562 hns3_free_desc(ring); 3563 out_with_desc_cb: 3564 devm_kfree(ring_to_dev(ring), ring->desc_cb); 3565 ring->desc_cb = NULL; 3566 out: 3567 return ret; 3568 } 3569 3570 static void hns3_fini_ring(struct hns3_enet_ring *ring) 3571 { 3572 hns3_free_desc(ring); 3573 devm_kfree(ring_to_dev(ring), ring->desc_cb); 3574 ring->desc_cb = NULL; 3575 ring->next_to_clean = 0; 3576 ring->next_to_use = 0; 3577 ring->pending_buf = 0; 3578 if (ring->skb) { 3579 dev_kfree_skb_any(ring->skb); 3580 ring->skb = NULL; 3581 } 3582 } 3583 3584 static int hns3_buf_size2type(u32 buf_size) 3585 { 3586 int bd_size_type; 3587 3588 switch (buf_size) { 3589 case 512: 3590 bd_size_type = HNS3_BD_SIZE_512_TYPE; 3591 break; 3592 case 1024: 3593 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 3594 break; 3595 case 2048: 3596 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3597 break; 3598 case 4096: 3599 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 3600 break; 3601 default: 3602 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3603 } 3604 3605 return bd_size_type; 3606 } 3607 3608 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 3609 { 3610 dma_addr_t dma = ring->desc_dma_addr; 3611 struct hnae3_queue *q = ring->tqp; 3612 3613 if (!HNAE3_IS_TX_RING(ring)) { 3614 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma); 3615 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 3616 (u32)((dma >> 31) >> 1)); 3617 3618 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 3619 hns3_buf_size2type(ring->buf_size)); 3620 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 3621 ring->desc_num / 8 - 1); 3622 3623 } else { 3624 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 3625 (u32)dma); 3626 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 3627 (u32)((dma >> 31) >> 1)); 3628 3629 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 3630 ring->desc_num / 8 - 1); 3631 } 3632 } 3633 3634 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 3635 { 3636 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3637 int i; 3638 3639 for (i = 0; i < HNAE3_MAX_TC; i++) { 3640 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i]; 3641 int j; 3642 3643 if (!tc_info->enable) 3644 continue; 3645 3646 for (j = 0; j < tc_info->tqp_count; j++) { 3647 struct hnae3_queue *q; 3648 3649 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp; 3650 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, 3651 tc_info->tc); 3652 } 3653 } 3654 } 3655 3656 int hns3_init_all_ring(struct hns3_nic_priv *priv) 3657 { 3658 struct hnae3_handle *h = priv->ae_handle; 3659 int ring_num = h->kinfo.num_tqps * 2; 3660 int i, j; 3661 int ret; 3662 3663 for (i = 0; i < ring_num; i++) { 3664 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring); 3665 if (ret) { 3666 dev_err(priv->dev, 3667 "Alloc ring memory fail! ret=%d\n", ret); 3668 goto out_when_alloc_ring_memory; 3669 } 3670 3671 u64_stats_init(&priv->ring_data[i].ring->syncp); 3672 } 3673 3674 return 0; 3675 3676 out_when_alloc_ring_memory: 3677 for (j = i - 1; j >= 0; j--) 3678 hns3_fini_ring(priv->ring_data[j].ring); 3679 3680 return -ENOMEM; 3681 } 3682 3683 int hns3_uninit_all_ring(struct hns3_nic_priv *priv) 3684 { 3685 struct hnae3_handle *h = priv->ae_handle; 3686 int i; 3687 3688 for (i = 0; i < h->kinfo.num_tqps; i++) { 3689 hns3_fini_ring(priv->ring_data[i].ring); 3690 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring); 3691 } 3692 return 0; 3693 } 3694 3695 /* Set mac addr if it is configured. or leave it to the AE driver */ 3696 static int hns3_init_mac_addr(struct net_device *netdev, bool init) 3697 { 3698 struct hns3_nic_priv *priv = netdev_priv(netdev); 3699 struct hnae3_handle *h = priv->ae_handle; 3700 u8 mac_addr_temp[ETH_ALEN]; 3701 int ret = 0; 3702 3703 if (h->ae_algo->ops->get_mac_addr && init) { 3704 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 3705 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 3706 } 3707 3708 /* Check if the MAC address is valid, if not get a random one */ 3709 if (!is_valid_ether_addr(netdev->dev_addr)) { 3710 eth_hw_addr_random(netdev); 3711 dev_warn(priv->dev, "using random MAC address %pM\n", 3712 netdev->dev_addr); 3713 } 3714 3715 if (h->ae_algo->ops->set_mac_addr) 3716 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 3717 3718 return ret; 3719 } 3720 3721 static int hns3_init_phy(struct net_device *netdev) 3722 { 3723 struct hnae3_handle *h = hns3_get_handle(netdev); 3724 int ret = 0; 3725 3726 if (h->ae_algo->ops->mac_connect_phy) 3727 ret = h->ae_algo->ops->mac_connect_phy(h); 3728 3729 return ret; 3730 } 3731 3732 static void hns3_uninit_phy(struct net_device *netdev) 3733 { 3734 struct hnae3_handle *h = hns3_get_handle(netdev); 3735 3736 if (h->ae_algo->ops->mac_disconnect_phy) 3737 h->ae_algo->ops->mac_disconnect_phy(h); 3738 } 3739 3740 static int hns3_restore_fd_rules(struct net_device *netdev) 3741 { 3742 struct hnae3_handle *h = hns3_get_handle(netdev); 3743 int ret = 0; 3744 3745 if (h->ae_algo->ops->restore_fd_rules) 3746 ret = h->ae_algo->ops->restore_fd_rules(h); 3747 3748 return ret; 3749 } 3750 3751 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list) 3752 { 3753 struct hnae3_handle *h = hns3_get_handle(netdev); 3754 3755 if (h->ae_algo->ops->del_all_fd_entries) 3756 h->ae_algo->ops->del_all_fd_entries(h, clear_list); 3757 } 3758 3759 static int hns3_client_start(struct hnae3_handle *handle) 3760 { 3761 if (!handle->ae_algo->ops->client_start) 3762 return 0; 3763 3764 return handle->ae_algo->ops->client_start(handle); 3765 } 3766 3767 static void hns3_client_stop(struct hnae3_handle *handle) 3768 { 3769 if (!handle->ae_algo->ops->client_stop) 3770 return; 3771 3772 handle->ae_algo->ops->client_stop(handle); 3773 } 3774 3775 static void hns3_info_show(struct hns3_nic_priv *priv) 3776 { 3777 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3778 3779 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr); 3780 dev_info(priv->dev, "Task queue pairs numbers: %d\n", kinfo->num_tqps); 3781 dev_info(priv->dev, "RSS size: %d\n", kinfo->rss_size); 3782 dev_info(priv->dev, "Allocated RSS size: %d\n", kinfo->req_rss_size); 3783 dev_info(priv->dev, "RX buffer length: %d\n", kinfo->rx_buf_len); 3784 dev_info(priv->dev, "Desc num per TX queue: %d\n", kinfo->num_tx_desc); 3785 dev_info(priv->dev, "Desc num per RX queue: %d\n", kinfo->num_rx_desc); 3786 dev_info(priv->dev, "Total number of enabled TCs: %d\n", kinfo->num_tc); 3787 dev_info(priv->dev, "Max mtu size: %d\n", priv->netdev->max_mtu); 3788 } 3789 3790 static int hns3_client_init(struct hnae3_handle *handle) 3791 { 3792 struct pci_dev *pdev = handle->pdev; 3793 u16 alloc_tqps, max_rss_size; 3794 struct hns3_nic_priv *priv; 3795 struct net_device *netdev; 3796 int ret; 3797 3798 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 3799 &max_rss_size); 3800 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 3801 if (!netdev) 3802 return -ENOMEM; 3803 3804 priv = netdev_priv(netdev); 3805 priv->dev = &pdev->dev; 3806 priv->netdev = netdev; 3807 priv->ae_handle = handle; 3808 priv->tx_timeout_count = 0; 3809 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 3810 3811 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL); 3812 3813 handle->kinfo.netdev = netdev; 3814 handle->priv = (void *)priv; 3815 3816 hns3_init_mac_addr(netdev, true); 3817 3818 hns3_set_default_feature(netdev); 3819 3820 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 3821 netdev->priv_flags |= IFF_UNICAST_FLT; 3822 netdev->netdev_ops = &hns3_nic_netdev_ops; 3823 SET_NETDEV_DEV(netdev, &pdev->dev); 3824 hns3_ethtool_set_ops(netdev); 3825 3826 /* Carrier off reporting is important to ethtool even BEFORE open */ 3827 netif_carrier_off(netdev); 3828 3829 ret = hns3_get_ring_config(priv); 3830 if (ret) { 3831 ret = -ENOMEM; 3832 goto out_get_ring_cfg; 3833 } 3834 3835 ret = hns3_nic_alloc_vector_data(priv); 3836 if (ret) { 3837 ret = -ENOMEM; 3838 goto out_alloc_vector_data; 3839 } 3840 3841 ret = hns3_nic_init_vector_data(priv); 3842 if (ret) { 3843 ret = -ENOMEM; 3844 goto out_init_vector_data; 3845 } 3846 3847 ret = hns3_init_all_ring(priv); 3848 if (ret) { 3849 ret = -ENOMEM; 3850 goto out_init_ring_data; 3851 } 3852 3853 ret = hns3_init_phy(netdev); 3854 if (ret) 3855 goto out_init_phy; 3856 3857 ret = register_netdev(netdev); 3858 if (ret) { 3859 dev_err(priv->dev, "probe register netdev fail!\n"); 3860 goto out_reg_netdev_fail; 3861 } 3862 3863 ret = hns3_client_start(handle); 3864 if (ret) { 3865 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 3866 goto out_client_start; 3867 } 3868 3869 hns3_dcbnl_setup(handle); 3870 3871 hns3_dbg_init(handle); 3872 3873 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */ 3874 netdev->max_mtu = HNS3_MAX_MTU; 3875 3876 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 3877 3878 if (netif_msg_drv(handle)) 3879 hns3_info_show(priv); 3880 3881 return ret; 3882 3883 out_client_start: 3884 unregister_netdev(netdev); 3885 out_reg_netdev_fail: 3886 hns3_uninit_phy(netdev); 3887 out_init_phy: 3888 hns3_uninit_all_ring(priv); 3889 out_init_ring_data: 3890 hns3_nic_uninit_vector_data(priv); 3891 out_init_vector_data: 3892 hns3_nic_dealloc_vector_data(priv); 3893 out_alloc_vector_data: 3894 priv->ring_data = NULL; 3895 out_get_ring_cfg: 3896 priv->ae_handle = NULL; 3897 free_netdev(netdev); 3898 return ret; 3899 } 3900 3901 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 3902 { 3903 struct net_device *netdev = handle->kinfo.netdev; 3904 struct hns3_nic_priv *priv = netdev_priv(netdev); 3905 int ret; 3906 3907 hns3_remove_hw_addr(netdev); 3908 3909 if (netdev->reg_state != NETREG_UNINITIALIZED) 3910 unregister_netdev(netdev); 3911 3912 hns3_client_stop(handle); 3913 3914 hns3_uninit_phy(netdev); 3915 3916 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 3917 netdev_warn(netdev, "already uninitialized\n"); 3918 goto out_netdev_free; 3919 } 3920 3921 hns3_del_all_fd_rules(netdev, true); 3922 3923 hns3_force_clear_all_ring(handle); 3924 3925 hns3_nic_uninit_vector_data(priv); 3926 3927 ret = hns3_nic_dealloc_vector_data(priv); 3928 if (ret) 3929 netdev_err(netdev, "dealloc vector error\n"); 3930 3931 ret = hns3_uninit_all_ring(priv); 3932 if (ret) 3933 netdev_err(netdev, "uninit ring error\n"); 3934 3935 hns3_put_ring_config(priv); 3936 3937 hns3_dbg_uninit(handle); 3938 3939 out_netdev_free: 3940 free_netdev(netdev); 3941 } 3942 3943 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 3944 { 3945 struct net_device *netdev = handle->kinfo.netdev; 3946 3947 if (!netdev) 3948 return; 3949 3950 if (linkup) { 3951 netif_carrier_on(netdev); 3952 netif_tx_wake_all_queues(netdev); 3953 if (netif_msg_link(handle)) 3954 netdev_info(netdev, "link up\n"); 3955 } else { 3956 netif_carrier_off(netdev); 3957 netif_tx_stop_all_queues(netdev); 3958 if (netif_msg_link(handle)) 3959 netdev_info(netdev, "link down\n"); 3960 } 3961 } 3962 3963 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc) 3964 { 3965 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3966 struct net_device *ndev = kinfo->netdev; 3967 3968 if (tc > HNAE3_MAX_TC) 3969 return -EINVAL; 3970 3971 if (!ndev) 3972 return -ENODEV; 3973 3974 return hns3_nic_set_real_num_queue(ndev); 3975 } 3976 3977 static int hns3_recover_hw_addr(struct net_device *ndev) 3978 { 3979 struct netdev_hw_addr_list *list; 3980 struct netdev_hw_addr *ha, *tmp; 3981 int ret = 0; 3982 3983 netif_addr_lock_bh(ndev); 3984 /* go through and sync uc_addr entries to the device */ 3985 list = &ndev->uc; 3986 list_for_each_entry_safe(ha, tmp, &list->list, list) { 3987 ret = hns3_nic_uc_sync(ndev, ha->addr); 3988 if (ret) 3989 goto out; 3990 } 3991 3992 /* go through and sync mc_addr entries to the device */ 3993 list = &ndev->mc; 3994 list_for_each_entry_safe(ha, tmp, &list->list, list) { 3995 ret = hns3_nic_mc_sync(ndev, ha->addr); 3996 if (ret) 3997 goto out; 3998 } 3999 4000 out: 4001 netif_addr_unlock_bh(ndev); 4002 return ret; 4003 } 4004 4005 static void hns3_remove_hw_addr(struct net_device *netdev) 4006 { 4007 struct netdev_hw_addr_list *list; 4008 struct netdev_hw_addr *ha, *tmp; 4009 4010 hns3_nic_uc_unsync(netdev, netdev->dev_addr); 4011 4012 netif_addr_lock_bh(netdev); 4013 /* go through and unsync uc_addr entries to the device */ 4014 list = &netdev->uc; 4015 list_for_each_entry_safe(ha, tmp, &list->list, list) 4016 hns3_nic_uc_unsync(netdev, ha->addr); 4017 4018 /* go through and unsync mc_addr entries to the device */ 4019 list = &netdev->mc; 4020 list_for_each_entry_safe(ha, tmp, &list->list, list) 4021 if (ha->refcount > 1) 4022 hns3_nic_mc_unsync(netdev, ha->addr); 4023 4024 netif_addr_unlock_bh(netdev); 4025 } 4026 4027 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 4028 { 4029 while (ring->next_to_clean != ring->next_to_use) { 4030 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 4031 hns3_free_buffer_detach(ring, ring->next_to_clean); 4032 ring_ptr_move_fw(ring, next_to_clean); 4033 } 4034 } 4035 4036 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 4037 { 4038 struct hns3_desc_cb res_cbs; 4039 int ret; 4040 4041 while (ring->next_to_use != ring->next_to_clean) { 4042 /* When a buffer is not reused, it's memory has been 4043 * freed in hns3_handle_rx_bd or will be freed by 4044 * stack, so we need to replace the buffer here. 4045 */ 4046 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4047 ret = hns3_reserve_buffer_map(ring, &res_cbs); 4048 if (ret) { 4049 u64_stats_update_begin(&ring->syncp); 4050 ring->stats.sw_err_cnt++; 4051 u64_stats_update_end(&ring->syncp); 4052 /* if alloc new buffer fail, exit directly 4053 * and reclear in up flow. 4054 */ 4055 netdev_warn(ring->tqp->handle->kinfo.netdev, 4056 "reserve buffer map failed, ret = %d\n", 4057 ret); 4058 return ret; 4059 } 4060 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 4061 } 4062 ring_ptr_move_fw(ring, next_to_use); 4063 } 4064 4065 /* Free the pending skb in rx ring */ 4066 if (ring->skb) { 4067 dev_kfree_skb_any(ring->skb); 4068 ring->skb = NULL; 4069 ring->pending_buf = 0; 4070 } 4071 4072 return 0; 4073 } 4074 4075 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 4076 { 4077 while (ring->next_to_use != ring->next_to_clean) { 4078 /* When a buffer is not reused, it's memory has been 4079 * freed in hns3_handle_rx_bd or will be freed by 4080 * stack, so only need to unmap the buffer here. 4081 */ 4082 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4083 hns3_unmap_buffer(ring, 4084 &ring->desc_cb[ring->next_to_use]); 4085 ring->desc_cb[ring->next_to_use].dma = 0; 4086 } 4087 4088 ring_ptr_move_fw(ring, next_to_use); 4089 } 4090 } 4091 4092 static void hns3_force_clear_all_ring(struct hnae3_handle *h) 4093 { 4094 struct net_device *ndev = h->kinfo.netdev; 4095 struct hns3_nic_priv *priv = netdev_priv(ndev); 4096 struct hns3_enet_ring *ring; 4097 u32 i; 4098 4099 for (i = 0; i < h->kinfo.num_tqps; i++) { 4100 ring = priv->ring_data[i].ring; 4101 hns3_clear_tx_ring(ring); 4102 4103 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 4104 hns3_force_clear_rx_ring(ring); 4105 } 4106 } 4107 4108 static void hns3_clear_all_ring(struct hnae3_handle *h) 4109 { 4110 struct net_device *ndev = h->kinfo.netdev; 4111 struct hns3_nic_priv *priv = netdev_priv(ndev); 4112 u32 i; 4113 4114 for (i = 0; i < h->kinfo.num_tqps; i++) { 4115 struct netdev_queue *dev_queue; 4116 struct hns3_enet_ring *ring; 4117 4118 ring = priv->ring_data[i].ring; 4119 hns3_clear_tx_ring(ring); 4120 dev_queue = netdev_get_tx_queue(ndev, 4121 priv->ring_data[i].queue_index); 4122 netdev_tx_reset_queue(dev_queue); 4123 4124 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 4125 /* Continue to clear other rings even if clearing some 4126 * rings failed. 4127 */ 4128 hns3_clear_rx_ring(ring); 4129 } 4130 } 4131 4132 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 4133 { 4134 struct net_device *ndev = h->kinfo.netdev; 4135 struct hns3_nic_priv *priv = netdev_priv(ndev); 4136 struct hns3_enet_ring *rx_ring; 4137 int i, j; 4138 int ret; 4139 4140 for (i = 0; i < h->kinfo.num_tqps; i++) { 4141 ret = h->ae_algo->ops->reset_queue(h, i); 4142 if (ret) 4143 return ret; 4144 4145 hns3_init_ring_hw(priv->ring_data[i].ring); 4146 4147 /* We need to clear tx ring here because self test will 4148 * use the ring and will not run down before up 4149 */ 4150 hns3_clear_tx_ring(priv->ring_data[i].ring); 4151 priv->ring_data[i].ring->next_to_clean = 0; 4152 priv->ring_data[i].ring->next_to_use = 0; 4153 4154 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 4155 hns3_init_ring_hw(rx_ring); 4156 ret = hns3_clear_rx_ring(rx_ring); 4157 if (ret) 4158 return ret; 4159 4160 /* We can not know the hardware head and tail when this 4161 * function is called in reset flow, so we reuse all desc. 4162 */ 4163 for (j = 0; j < rx_ring->desc_num; j++) 4164 hns3_reuse_buffer(rx_ring, j); 4165 4166 rx_ring->next_to_clean = 0; 4167 rx_ring->next_to_use = 0; 4168 } 4169 4170 hns3_init_tx_ring_tc(priv); 4171 4172 return 0; 4173 } 4174 4175 static void hns3_store_coal(struct hns3_nic_priv *priv) 4176 { 4177 /* ethtool only support setting and querying one coal 4178 * configuation for now, so save the vector 0' coal 4179 * configuation here in order to restore it. 4180 */ 4181 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal, 4182 sizeof(struct hns3_enet_coalesce)); 4183 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal, 4184 sizeof(struct hns3_enet_coalesce)); 4185 } 4186 4187 static void hns3_restore_coal(struct hns3_nic_priv *priv) 4188 { 4189 u16 vector_num = priv->vector_num; 4190 int i; 4191 4192 for (i = 0; i < vector_num; i++) { 4193 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal, 4194 sizeof(struct hns3_enet_coalesce)); 4195 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal, 4196 sizeof(struct hns3_enet_coalesce)); 4197 } 4198 } 4199 4200 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 4201 { 4202 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4203 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4204 struct net_device *ndev = kinfo->netdev; 4205 struct hns3_nic_priv *priv = netdev_priv(ndev); 4206 4207 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 4208 return 0; 4209 4210 /* it is cumbersome for hardware to pick-and-choose entries for deletion 4211 * from table space. Hence, for function reset software intervention is 4212 * required to delete the entries 4213 */ 4214 if (hns3_dev_ongoing_func_reset(ae_dev)) { 4215 hns3_remove_hw_addr(ndev); 4216 hns3_del_all_fd_rules(ndev, false); 4217 } 4218 4219 if (!netif_running(ndev)) 4220 return 0; 4221 4222 return hns3_nic_net_stop(ndev); 4223 } 4224 4225 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 4226 { 4227 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4228 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 4229 int ret = 0; 4230 4231 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4232 4233 if (netif_running(kinfo->netdev)) { 4234 ret = hns3_nic_net_open(kinfo->netdev); 4235 if (ret) { 4236 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4237 netdev_err(kinfo->netdev, 4238 "net up fail, ret=%d!\n", ret); 4239 return ret; 4240 } 4241 } 4242 4243 return ret; 4244 } 4245 4246 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 4247 { 4248 struct net_device *netdev = handle->kinfo.netdev; 4249 struct hns3_nic_priv *priv = netdev_priv(netdev); 4250 int ret; 4251 4252 /* Carrier off reporting is important to ethtool even BEFORE open */ 4253 netif_carrier_off(netdev); 4254 4255 ret = hns3_get_ring_config(priv); 4256 if (ret) 4257 return ret; 4258 4259 ret = hns3_nic_alloc_vector_data(priv); 4260 if (ret) 4261 goto err_put_ring; 4262 4263 hns3_restore_coal(priv); 4264 4265 ret = hns3_nic_init_vector_data(priv); 4266 if (ret) 4267 goto err_dealloc_vector; 4268 4269 ret = hns3_init_all_ring(priv); 4270 if (ret) 4271 goto err_uninit_vector; 4272 4273 ret = hns3_client_start(handle); 4274 if (ret) { 4275 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4276 goto err_uninit_ring; 4277 } 4278 4279 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4280 4281 return ret; 4282 4283 err_uninit_ring: 4284 hns3_uninit_all_ring(priv); 4285 err_uninit_vector: 4286 hns3_nic_uninit_vector_data(priv); 4287 err_dealloc_vector: 4288 hns3_nic_dealloc_vector_data(priv); 4289 err_put_ring: 4290 hns3_put_ring_config(priv); 4291 4292 return ret; 4293 } 4294 4295 static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle) 4296 { 4297 struct net_device *netdev = handle->kinfo.netdev; 4298 bool vlan_filter_enable; 4299 int ret; 4300 4301 ret = hns3_init_mac_addr(netdev, false); 4302 if (ret) 4303 return ret; 4304 4305 ret = hns3_recover_hw_addr(netdev); 4306 if (ret) 4307 return ret; 4308 4309 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags); 4310 if (ret) 4311 return ret; 4312 4313 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true; 4314 hns3_enable_vlan_filter(netdev, vlan_filter_enable); 4315 4316 if (handle->ae_algo->ops->restore_vlan_table) 4317 handle->ae_algo->ops->restore_vlan_table(handle); 4318 4319 return hns3_restore_fd_rules(netdev); 4320 } 4321 4322 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 4323 { 4324 struct net_device *netdev = handle->kinfo.netdev; 4325 struct hns3_nic_priv *priv = netdev_priv(netdev); 4326 int ret; 4327 4328 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4329 netdev_warn(netdev, "already uninitialized\n"); 4330 return 0; 4331 } 4332 4333 hns3_clear_all_ring(handle); 4334 hns3_force_clear_all_ring(handle); 4335 4336 hns3_nic_uninit_vector_data(priv); 4337 4338 hns3_store_coal(priv); 4339 4340 ret = hns3_nic_dealloc_vector_data(priv); 4341 if (ret) 4342 netdev_err(netdev, "dealloc vector error\n"); 4343 4344 ret = hns3_uninit_all_ring(priv); 4345 if (ret) 4346 netdev_err(netdev, "uninit ring error\n"); 4347 4348 hns3_put_ring_config(priv); 4349 4350 return ret; 4351 } 4352 4353 static int hns3_reset_notify(struct hnae3_handle *handle, 4354 enum hnae3_reset_notify_type type) 4355 { 4356 int ret = 0; 4357 4358 switch (type) { 4359 case HNAE3_UP_CLIENT: 4360 ret = hns3_reset_notify_up_enet(handle); 4361 break; 4362 case HNAE3_DOWN_CLIENT: 4363 ret = hns3_reset_notify_down_enet(handle); 4364 break; 4365 case HNAE3_INIT_CLIENT: 4366 ret = hns3_reset_notify_init_enet(handle); 4367 break; 4368 case HNAE3_UNINIT_CLIENT: 4369 ret = hns3_reset_notify_uninit_enet(handle); 4370 break; 4371 case HNAE3_RESTORE_CLIENT: 4372 ret = hns3_reset_notify_restore_enet(handle); 4373 break; 4374 default: 4375 break; 4376 } 4377 4378 return ret; 4379 } 4380 4381 int hns3_set_channels(struct net_device *netdev, 4382 struct ethtool_channels *ch) 4383 { 4384 struct hnae3_handle *h = hns3_get_handle(netdev); 4385 struct hnae3_knic_private_info *kinfo = &h->kinfo; 4386 bool rxfh_configured = netif_is_rxfh_configured(netdev); 4387 u32 new_tqp_num = ch->combined_count; 4388 u16 org_tqp_num; 4389 int ret; 4390 4391 if (ch->rx_count || ch->tx_count) 4392 return -EINVAL; 4393 4394 if (new_tqp_num > hns3_get_max_available_channels(h) || 4395 new_tqp_num < 1) { 4396 dev_err(&netdev->dev, 4397 "Change tqps fail, the tqp range is from 1 to %d", 4398 hns3_get_max_available_channels(h)); 4399 return -EINVAL; 4400 } 4401 4402 if (kinfo->rss_size == new_tqp_num) 4403 return 0; 4404 4405 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 4406 if (ret) 4407 return ret; 4408 4409 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 4410 if (ret) 4411 return ret; 4412 4413 org_tqp_num = h->kinfo.num_tqps; 4414 ret = h->ae_algo->ops->set_channels(h, new_tqp_num, rxfh_configured); 4415 if (ret) { 4416 ret = h->ae_algo->ops->set_channels(h, org_tqp_num, 4417 rxfh_configured); 4418 if (ret) { 4419 /* If revert to old tqp failed, fatal error occurred */ 4420 dev_err(&netdev->dev, 4421 "Revert to old tqp num fail, ret=%d", ret); 4422 return ret; 4423 } 4424 dev_info(&netdev->dev, 4425 "Change tqp num fail, Revert to old tqp num"); 4426 } 4427 ret = hns3_reset_notify(h, HNAE3_INIT_CLIENT); 4428 if (ret) 4429 return ret; 4430 4431 return hns3_reset_notify(h, HNAE3_UP_CLIENT); 4432 } 4433 4434 static const struct hnae3_client_ops client_ops = { 4435 .init_instance = hns3_client_init, 4436 .uninit_instance = hns3_client_uninit, 4437 .link_status_change = hns3_link_status_change, 4438 .setup_tc = hns3_client_setup_tc, 4439 .reset_notify = hns3_reset_notify, 4440 }; 4441 4442 /* hns3_init_module - Driver registration routine 4443 * hns3_init_module is the first routine called when the driver is 4444 * loaded. All it does is register with the PCI subsystem. 4445 */ 4446 static int __init hns3_init_module(void) 4447 { 4448 int ret; 4449 4450 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 4451 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 4452 4453 client.type = HNAE3_CLIENT_KNIC; 4454 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s", 4455 hns3_driver_name); 4456 4457 client.ops = &client_ops; 4458 4459 INIT_LIST_HEAD(&client.node); 4460 4461 hns3_dbg_register_debugfs(hns3_driver_name); 4462 4463 ret = hnae3_register_client(&client); 4464 if (ret) 4465 goto err_reg_client; 4466 4467 ret = pci_register_driver(&hns3_driver); 4468 if (ret) 4469 goto err_reg_driver; 4470 4471 return ret; 4472 4473 err_reg_driver: 4474 hnae3_unregister_client(&client); 4475 err_reg_client: 4476 hns3_dbg_unregister_debugfs(); 4477 return ret; 4478 } 4479 module_init(hns3_init_module); 4480 4481 /* hns3_exit_module - Driver exit cleanup routine 4482 * hns3_exit_module is called just before the driver is removed 4483 * from memory. 4484 */ 4485 static void __exit hns3_exit_module(void) 4486 { 4487 pci_unregister_driver(&hns3_driver); 4488 hnae3_unregister_client(&client); 4489 hns3_dbg_unregister_debugfs(); 4490 } 4491 module_exit(hns3_exit_module); 4492 4493 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 4494 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 4495 MODULE_LICENSE("GPL"); 4496 MODULE_ALIAS("pci:hns-nic"); 4497 MODULE_VERSION(HNS3_MOD_VERSION); 4498