1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #ifdef CONFIG_RFS_ACCEL 8 #include <linux/cpu_rmap.h> 9 #endif 10 #include <linux/if_vlan.h> 11 #include <linux/ip.h> 12 #include <linux/ipv6.h> 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/aer.h> 16 #include <linux/skbuff.h> 17 #include <linux/sctp.h> 18 #include <net/gre.h> 19 #include <net/ip6_checksum.h> 20 #include <net/pkt_cls.h> 21 #include <net/tcp.h> 22 #include <net/vxlan.h> 23 24 #include "hnae3.h" 25 #include "hns3_enet.h" 26 /* All hns3 tracepoints are defined by the include below, which 27 * must be included exactly once across the whole kernel with 28 * CREATE_TRACE_POINTS defined 29 */ 30 #define CREATE_TRACE_POINTS 31 #include "hns3_trace.h" 32 33 #define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift))) 34 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE) 35 36 #define hns3_rl_err(fmt, ...) \ 37 do { \ 38 if (net_ratelimit()) \ 39 netdev_err(fmt, ##__VA_ARGS__); \ 40 } while (0) 41 42 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force); 43 44 static const char hns3_driver_name[] = "hns3"; 45 static const char hns3_driver_string[] = 46 "Hisilicon Ethernet Network Driver for Hip08 Family"; 47 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 48 static struct hnae3_client client; 49 50 static int debug = -1; 51 module_param(debug, int, 0); 52 MODULE_PARM_DESC(debug, " Network interface message level setting"); 53 54 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 55 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) 56 57 #define HNS3_INNER_VLAN_TAG 1 58 #define HNS3_OUTER_VLAN_TAG 2 59 60 #define HNS3_MIN_TX_LEN 33U 61 62 /* hns3_pci_tbl - PCI Device ID Table 63 * 64 * Last entry must be all 0s 65 * 66 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 67 * Class, Class Mask, private data (not used) } 68 */ 69 static const struct pci_device_id hns3_pci_tbl[] = { 70 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 71 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 72 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 73 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 75 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 77 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 79 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 80 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 81 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 83 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 84 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 85 /* required last entry */ 86 {0, } 87 }; 88 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 89 90 static irqreturn_t hns3_irq_handle(int irq, void *vector) 91 { 92 struct hns3_enet_tqp_vector *tqp_vector = vector; 93 94 napi_schedule_irqoff(&tqp_vector->napi); 95 96 return IRQ_HANDLED; 97 } 98 99 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 100 { 101 struct hns3_enet_tqp_vector *tqp_vectors; 102 unsigned int i; 103 104 for (i = 0; i < priv->vector_num; i++) { 105 tqp_vectors = &priv->tqp_vector[i]; 106 107 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 108 continue; 109 110 /* clear the affinity mask */ 111 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 112 113 /* release the irq resource */ 114 free_irq(tqp_vectors->vector_irq, tqp_vectors); 115 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 116 } 117 } 118 119 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 120 { 121 struct hns3_enet_tqp_vector *tqp_vectors; 122 int txrx_int_idx = 0; 123 int rx_int_idx = 0; 124 int tx_int_idx = 0; 125 unsigned int i; 126 int ret; 127 128 for (i = 0; i < priv->vector_num; i++) { 129 tqp_vectors = &priv->tqp_vector[i]; 130 131 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 132 continue; 133 134 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 135 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 136 "%s-%s-%s-%d", hns3_driver_name, 137 pci_name(priv->ae_handle->pdev), 138 "TxRx", txrx_int_idx++); 139 txrx_int_idx++; 140 } else if (tqp_vectors->rx_group.ring) { 141 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 142 "%s-%s-%s-%d", hns3_driver_name, 143 pci_name(priv->ae_handle->pdev), 144 "Rx", rx_int_idx++); 145 } else if (tqp_vectors->tx_group.ring) { 146 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 147 "%s-%s-%s-%d", hns3_driver_name, 148 pci_name(priv->ae_handle->pdev), 149 "Tx", tx_int_idx++); 150 } else { 151 /* Skip this unused q_vector */ 152 continue; 153 } 154 155 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 156 157 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 158 tqp_vectors->name, tqp_vectors); 159 if (ret) { 160 netdev_err(priv->netdev, "request irq(%d) fail\n", 161 tqp_vectors->vector_irq); 162 hns3_nic_uninit_irq(priv); 163 return ret; 164 } 165 166 disable_irq(tqp_vectors->vector_irq); 167 168 irq_set_affinity_hint(tqp_vectors->vector_irq, 169 &tqp_vectors->affinity_mask); 170 171 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 172 } 173 174 return 0; 175 } 176 177 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 178 u32 mask_en) 179 { 180 writel(mask_en, tqp_vector->mask_addr); 181 } 182 183 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 184 { 185 napi_enable(&tqp_vector->napi); 186 enable_irq(tqp_vector->vector_irq); 187 188 /* enable vector */ 189 hns3_mask_vector_irq(tqp_vector, 1); 190 } 191 192 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 193 { 194 /* disable vector */ 195 hns3_mask_vector_irq(tqp_vector, 0); 196 197 disable_irq(tqp_vector->vector_irq); 198 napi_disable(&tqp_vector->napi); 199 } 200 201 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 202 u32 rl_value) 203 { 204 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 205 206 /* this defines the configuration for RL (Interrupt Rate Limiter). 207 * Rl defines rate of interrupts i.e. number of interrupts-per-second 208 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 209 */ 210 211 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable && 212 !tqp_vector->rx_group.coal.gl_adapt_enable) 213 /* According to the hardware, the range of rl_reg is 214 * 0-59 and the unit is 4. 215 */ 216 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 217 218 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 219 } 220 221 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 222 u32 gl_value) 223 { 224 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value); 225 226 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 227 } 228 229 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 230 u32 gl_value) 231 { 232 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value); 233 234 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 235 } 236 237 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector, 238 struct hns3_nic_priv *priv) 239 { 240 /* initialize the configuration for interrupt coalescing. 241 * 1. GL (Interrupt Gap Limiter) 242 * 2. RL (Interrupt Rate Limiter) 243 * 244 * Default: enable interrupt coalescing self-adaptive and GL 245 */ 246 tqp_vector->tx_group.coal.gl_adapt_enable = 1; 247 tqp_vector->rx_group.coal.gl_adapt_enable = 1; 248 249 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K; 250 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K; 251 252 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW; 253 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW; 254 } 255 256 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 257 struct hns3_nic_priv *priv) 258 { 259 struct hnae3_handle *h = priv->ae_handle; 260 261 hns3_set_vector_coalesce_tx_gl(tqp_vector, 262 tqp_vector->tx_group.coal.int_gl); 263 hns3_set_vector_coalesce_rx_gl(tqp_vector, 264 tqp_vector->rx_group.coal.int_gl); 265 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 266 } 267 268 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 269 { 270 struct hnae3_handle *h = hns3_get_handle(netdev); 271 struct hnae3_knic_private_info *kinfo = &h->kinfo; 272 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc; 273 int i, ret; 274 275 if (kinfo->num_tc <= 1) { 276 netdev_reset_tc(netdev); 277 } else { 278 ret = netdev_set_num_tc(netdev, kinfo->num_tc); 279 if (ret) { 280 netdev_err(netdev, 281 "netdev_set_num_tc fail, ret=%d!\n", ret); 282 return ret; 283 } 284 285 for (i = 0; i < HNAE3_MAX_TC; i++) { 286 if (!kinfo->tc_info[i].enable) 287 continue; 288 289 netdev_set_tc_queue(netdev, 290 kinfo->tc_info[i].tc, 291 kinfo->tc_info[i].tqp_count, 292 kinfo->tc_info[i].tqp_offset); 293 } 294 } 295 296 ret = netif_set_real_num_tx_queues(netdev, queue_size); 297 if (ret) { 298 netdev_err(netdev, 299 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret); 300 return ret; 301 } 302 303 ret = netif_set_real_num_rx_queues(netdev, queue_size); 304 if (ret) { 305 netdev_err(netdev, 306 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 307 return ret; 308 } 309 310 return 0; 311 } 312 313 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 314 { 315 u16 alloc_tqps, max_rss_size, rss_size; 316 317 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 318 rss_size = alloc_tqps / h->kinfo.num_tc; 319 320 return min_t(u16, rss_size, max_rss_size); 321 } 322 323 static void hns3_tqp_enable(struct hnae3_queue *tqp) 324 { 325 u32 rcb_reg; 326 327 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 328 rcb_reg |= BIT(HNS3_RING_EN_B); 329 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 330 } 331 332 static void hns3_tqp_disable(struct hnae3_queue *tqp) 333 { 334 u32 rcb_reg; 335 336 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 337 rcb_reg &= ~BIT(HNS3_RING_EN_B); 338 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 339 } 340 341 static void hns3_free_rx_cpu_rmap(struct net_device *netdev) 342 { 343 #ifdef CONFIG_RFS_ACCEL 344 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 345 netdev->rx_cpu_rmap = NULL; 346 #endif 347 } 348 349 static int hns3_set_rx_cpu_rmap(struct net_device *netdev) 350 { 351 #ifdef CONFIG_RFS_ACCEL 352 struct hns3_nic_priv *priv = netdev_priv(netdev); 353 struct hns3_enet_tqp_vector *tqp_vector; 354 int i, ret; 355 356 if (!netdev->rx_cpu_rmap) { 357 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num); 358 if (!netdev->rx_cpu_rmap) 359 return -ENOMEM; 360 } 361 362 for (i = 0; i < priv->vector_num; i++) { 363 tqp_vector = &priv->tqp_vector[i]; 364 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap, 365 tqp_vector->vector_irq); 366 if (ret) { 367 hns3_free_rx_cpu_rmap(netdev); 368 return ret; 369 } 370 } 371 #endif 372 return 0; 373 } 374 375 static int hns3_nic_net_up(struct net_device *netdev) 376 { 377 struct hns3_nic_priv *priv = netdev_priv(netdev); 378 struct hnae3_handle *h = priv->ae_handle; 379 int i, j; 380 int ret; 381 382 ret = hns3_nic_reset_all_ring(h); 383 if (ret) 384 return ret; 385 386 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 387 388 /* enable the vectors */ 389 for (i = 0; i < priv->vector_num; i++) 390 hns3_vector_enable(&priv->tqp_vector[i]); 391 392 /* enable rcb */ 393 for (j = 0; j < h->kinfo.num_tqps; j++) 394 hns3_tqp_enable(h->kinfo.tqp[j]); 395 396 /* start the ae_dev */ 397 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 398 if (ret) { 399 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 400 while (j--) 401 hns3_tqp_disable(h->kinfo.tqp[j]); 402 403 for (j = i - 1; j >= 0; j--) 404 hns3_vector_disable(&priv->tqp_vector[j]); 405 } 406 407 return ret; 408 } 409 410 static void hns3_config_xps(struct hns3_nic_priv *priv) 411 { 412 int i; 413 414 for (i = 0; i < priv->vector_num; i++) { 415 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 416 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 417 418 while (ring) { 419 int ret; 420 421 ret = netif_set_xps_queue(priv->netdev, 422 &tqp_vector->affinity_mask, 423 ring->tqp->tqp_index); 424 if (ret) 425 netdev_warn(priv->netdev, 426 "set xps queue failed: %d", ret); 427 428 ring = ring->next; 429 } 430 } 431 } 432 433 static int hns3_nic_net_open(struct net_device *netdev) 434 { 435 struct hns3_nic_priv *priv = netdev_priv(netdev); 436 struct hnae3_handle *h = hns3_get_handle(netdev); 437 struct hnae3_knic_private_info *kinfo; 438 int i, ret; 439 440 if (hns3_nic_resetting(netdev)) 441 return -EBUSY; 442 443 netif_carrier_off(netdev); 444 445 ret = hns3_nic_set_real_num_queue(netdev); 446 if (ret) 447 return ret; 448 449 ret = hns3_nic_net_up(netdev); 450 if (ret) { 451 netdev_err(netdev, "net up fail, ret=%d!\n", ret); 452 return ret; 453 } 454 455 kinfo = &h->kinfo; 456 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 457 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]); 458 459 if (h->ae_algo->ops->set_timer_task) 460 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 461 462 hns3_config_xps(priv); 463 464 netif_dbg(h, drv, netdev, "net open\n"); 465 466 return 0; 467 } 468 469 static void hns3_reset_tx_queue(struct hnae3_handle *h) 470 { 471 struct net_device *ndev = h->kinfo.netdev; 472 struct hns3_nic_priv *priv = netdev_priv(ndev); 473 struct netdev_queue *dev_queue; 474 u32 i; 475 476 for (i = 0; i < h->kinfo.num_tqps; i++) { 477 dev_queue = netdev_get_tx_queue(ndev, 478 priv->ring[i].queue_index); 479 netdev_tx_reset_queue(dev_queue); 480 } 481 } 482 483 static void hns3_nic_net_down(struct net_device *netdev) 484 { 485 struct hns3_nic_priv *priv = netdev_priv(netdev); 486 struct hnae3_handle *h = hns3_get_handle(netdev); 487 const struct hnae3_ae_ops *ops; 488 int i; 489 490 /* disable vectors */ 491 for (i = 0; i < priv->vector_num; i++) 492 hns3_vector_disable(&priv->tqp_vector[i]); 493 494 /* disable rcb */ 495 for (i = 0; i < h->kinfo.num_tqps; i++) 496 hns3_tqp_disable(h->kinfo.tqp[i]); 497 498 /* stop ae_dev */ 499 ops = priv->ae_handle->ae_algo->ops; 500 if (ops->stop) 501 ops->stop(priv->ae_handle); 502 503 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 504 * during reset process, because driver may not be able 505 * to disable the ring through firmware when downing the netdev. 506 */ 507 if (!hns3_nic_resetting(netdev)) 508 hns3_clear_all_ring(priv->ae_handle, false); 509 510 hns3_reset_tx_queue(priv->ae_handle); 511 } 512 513 static int hns3_nic_net_stop(struct net_device *netdev) 514 { 515 struct hns3_nic_priv *priv = netdev_priv(netdev); 516 struct hnae3_handle *h = hns3_get_handle(netdev); 517 518 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 519 return 0; 520 521 netif_dbg(h, drv, netdev, "net stop\n"); 522 523 if (h->ae_algo->ops->set_timer_task) 524 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 525 526 netif_tx_stop_all_queues(netdev); 527 netif_carrier_off(netdev); 528 529 hns3_nic_net_down(netdev); 530 531 return 0; 532 } 533 534 static int hns3_nic_uc_sync(struct net_device *netdev, 535 const unsigned char *addr) 536 { 537 struct hnae3_handle *h = hns3_get_handle(netdev); 538 539 if (h->ae_algo->ops->add_uc_addr) 540 return h->ae_algo->ops->add_uc_addr(h, addr); 541 542 return 0; 543 } 544 545 static int hns3_nic_uc_unsync(struct net_device *netdev, 546 const unsigned char *addr) 547 { 548 struct hnae3_handle *h = hns3_get_handle(netdev); 549 550 /* need ignore the request of removing device address, because 551 * we store the device address and other addresses of uc list 552 * in the function's mac filter list. 553 */ 554 if (ether_addr_equal(addr, netdev->dev_addr)) 555 return 0; 556 557 if (h->ae_algo->ops->rm_uc_addr) 558 return h->ae_algo->ops->rm_uc_addr(h, addr); 559 560 return 0; 561 } 562 563 static int hns3_nic_mc_sync(struct net_device *netdev, 564 const unsigned char *addr) 565 { 566 struct hnae3_handle *h = hns3_get_handle(netdev); 567 568 if (h->ae_algo->ops->add_mc_addr) 569 return h->ae_algo->ops->add_mc_addr(h, addr); 570 571 return 0; 572 } 573 574 static int hns3_nic_mc_unsync(struct net_device *netdev, 575 const unsigned char *addr) 576 { 577 struct hnae3_handle *h = hns3_get_handle(netdev); 578 579 if (h->ae_algo->ops->rm_mc_addr) 580 return h->ae_algo->ops->rm_mc_addr(h, addr); 581 582 return 0; 583 } 584 585 static u8 hns3_get_netdev_flags(struct net_device *netdev) 586 { 587 u8 flags = 0; 588 589 if (netdev->flags & IFF_PROMISC) { 590 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 591 } else { 592 flags |= HNAE3_VLAN_FLTR; 593 if (netdev->flags & IFF_ALLMULTI) 594 flags |= HNAE3_USER_MPE; 595 } 596 597 return flags; 598 } 599 600 static void hns3_nic_set_rx_mode(struct net_device *netdev) 601 { 602 struct hnae3_handle *h = hns3_get_handle(netdev); 603 u8 new_flags; 604 605 new_flags = hns3_get_netdev_flags(netdev); 606 607 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 608 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync); 609 610 /* User mode Promisc mode enable and vlan filtering is disabled to 611 * let all packets in. 612 */ 613 h->netdev_flags = new_flags; 614 hns3_request_update_promisc_mode(h); 615 } 616 617 void hns3_request_update_promisc_mode(struct hnae3_handle *handle) 618 { 619 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 620 621 if (ops->request_update_promisc_mode) 622 ops->request_update_promisc_mode(handle); 623 } 624 625 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags) 626 { 627 struct hns3_nic_priv *priv = netdev_priv(netdev); 628 struct hnae3_handle *h = priv->ae_handle; 629 630 if (h->ae_algo->ops->set_promisc_mode) { 631 return h->ae_algo->ops->set_promisc_mode(h, 632 promisc_flags & HNAE3_UPE, 633 promisc_flags & HNAE3_MPE); 634 } 635 636 return 0; 637 } 638 639 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable) 640 { 641 struct hns3_nic_priv *priv = netdev_priv(netdev); 642 struct hnae3_handle *h = priv->ae_handle; 643 bool last_state; 644 645 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) { 646 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false; 647 if (enable != last_state) { 648 netdev_info(netdev, 649 "%s vlan filter\n", 650 enable ? "enable" : "disable"); 651 h->ae_algo->ops->enable_vlan_filter(h, enable); 652 } 653 } 654 } 655 656 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen, 657 u16 *mss, u32 *type_cs_vlan_tso) 658 { 659 u32 l4_offset, hdr_len; 660 union l3_hdr_info l3; 661 union l4_hdr_info l4; 662 u32 l4_paylen; 663 int ret; 664 665 if (!skb_is_gso(skb)) 666 return 0; 667 668 ret = skb_cow_head(skb, 0); 669 if (unlikely(ret < 0)) 670 return ret; 671 672 l3.hdr = skb_network_header(skb); 673 l4.hdr = skb_transport_header(skb); 674 675 /* Software should clear the IPv4's checksum field when tso is 676 * needed. 677 */ 678 if (l3.v4->version == 4) 679 l3.v4->check = 0; 680 681 /* tunnel packet */ 682 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 683 SKB_GSO_GRE_CSUM | 684 SKB_GSO_UDP_TUNNEL | 685 SKB_GSO_UDP_TUNNEL_CSUM)) { 686 if ((!(skb_shinfo(skb)->gso_type & 687 SKB_GSO_PARTIAL)) && 688 (skb_shinfo(skb)->gso_type & 689 SKB_GSO_UDP_TUNNEL_CSUM)) { 690 /* Software should clear the udp's checksum 691 * field when tso is needed. 692 */ 693 l4.udp->check = 0; 694 } 695 /* reset l3&l4 pointers from outer to inner headers */ 696 l3.hdr = skb_inner_network_header(skb); 697 l4.hdr = skb_inner_transport_header(skb); 698 699 /* Software should clear the IPv4's checksum field when 700 * tso is needed. 701 */ 702 if (l3.v4->version == 4) 703 l3.v4->check = 0; 704 } 705 706 /* normal or tunnel packet */ 707 l4_offset = l4.hdr - skb->data; 708 hdr_len = (l4.tcp->doff << 2) + l4_offset; 709 710 /* remove payload length from inner pseudo checksum when tso */ 711 l4_paylen = skb->len - l4_offset; 712 csum_replace_by_diff(&l4.tcp->check, 713 (__force __wsum)htonl(l4_paylen)); 714 715 /* find the txbd field values */ 716 *paylen = skb->len - hdr_len; 717 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 718 719 /* get MSS for TSO */ 720 *mss = skb_shinfo(skb)->gso_size; 721 722 trace_hns3_tso(skb); 723 724 return 0; 725 } 726 727 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 728 u8 *il4_proto) 729 { 730 union l3_hdr_info l3; 731 unsigned char *l4_hdr; 732 unsigned char *exthdr; 733 u8 l4_proto_tmp; 734 __be16 frag_off; 735 736 /* find outer header point */ 737 l3.hdr = skb_network_header(skb); 738 l4_hdr = skb_transport_header(skb); 739 740 if (skb->protocol == htons(ETH_P_IPV6)) { 741 exthdr = l3.hdr + sizeof(*l3.v6); 742 l4_proto_tmp = l3.v6->nexthdr; 743 if (l4_hdr != exthdr) 744 ipv6_skip_exthdr(skb, exthdr - skb->data, 745 &l4_proto_tmp, &frag_off); 746 } else if (skb->protocol == htons(ETH_P_IP)) { 747 l4_proto_tmp = l3.v4->protocol; 748 } else { 749 return -EINVAL; 750 } 751 752 *ol4_proto = l4_proto_tmp; 753 754 /* tunnel packet */ 755 if (!skb->encapsulation) { 756 *il4_proto = 0; 757 return 0; 758 } 759 760 /* find inner header point */ 761 l3.hdr = skb_inner_network_header(skb); 762 l4_hdr = skb_inner_transport_header(skb); 763 764 if (l3.v6->version == 6) { 765 exthdr = l3.hdr + sizeof(*l3.v6); 766 l4_proto_tmp = l3.v6->nexthdr; 767 if (l4_hdr != exthdr) 768 ipv6_skip_exthdr(skb, exthdr - skb->data, 769 &l4_proto_tmp, &frag_off); 770 } else if (l3.v4->version == 4) { 771 l4_proto_tmp = l3.v4->protocol; 772 } 773 774 *il4_proto = l4_proto_tmp; 775 776 return 0; 777 } 778 779 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 780 * and it is udp packet, which has a dest port as the IANA assigned. 781 * the hardware is expected to do the checksum offload, but the 782 * hardware will not do the checksum offload when udp dest port is 783 * 4789. 784 */ 785 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 786 { 787 union l4_hdr_info l4; 788 789 l4.hdr = skb_transport_header(skb); 790 791 if (!(!skb->encapsulation && 792 l4.udp->dest == htons(IANA_VXLAN_UDP_PORT))) 793 return false; 794 795 skb_checksum_help(skb); 796 797 return true; 798 } 799 800 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 801 u32 *ol_type_vlan_len_msec) 802 { 803 u32 l2_len, l3_len, l4_len; 804 unsigned char *il2_hdr; 805 union l3_hdr_info l3; 806 union l4_hdr_info l4; 807 808 l3.hdr = skb_network_header(skb); 809 l4.hdr = skb_transport_header(skb); 810 811 /* compute OL2 header size, defined in 2 Bytes */ 812 l2_len = l3.hdr - skb->data; 813 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1); 814 815 /* compute OL3 header size, defined in 4 Bytes */ 816 l3_len = l4.hdr - l3.hdr; 817 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2); 818 819 il2_hdr = skb_inner_mac_header(skb); 820 /* compute OL4 header size, defined in 4 Bytes */ 821 l4_len = il2_hdr - l4.hdr; 822 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2); 823 824 /* define outer network header type */ 825 if (skb->protocol == htons(ETH_P_IP)) { 826 if (skb_is_gso(skb)) 827 hns3_set_field(*ol_type_vlan_len_msec, 828 HNS3_TXD_OL3T_S, 829 HNS3_OL3T_IPV4_CSUM); 830 else 831 hns3_set_field(*ol_type_vlan_len_msec, 832 HNS3_TXD_OL3T_S, 833 HNS3_OL3T_IPV4_NO_CSUM); 834 835 } else if (skb->protocol == htons(ETH_P_IPV6)) { 836 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 837 HNS3_OL3T_IPV6); 838 } 839 840 if (ol4_proto == IPPROTO_UDP) 841 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 842 HNS3_TUN_MAC_IN_UDP); 843 else if (ol4_proto == IPPROTO_GRE) 844 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 845 HNS3_TUN_NVGRE); 846 } 847 848 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 849 u8 il4_proto, u32 *type_cs_vlan_tso, 850 u32 *ol_type_vlan_len_msec) 851 { 852 unsigned char *l2_hdr = skb->data; 853 u32 l4_proto = ol4_proto; 854 union l4_hdr_info l4; 855 union l3_hdr_info l3; 856 u32 l2_len, l3_len; 857 858 l4.hdr = skb_transport_header(skb); 859 l3.hdr = skb_network_header(skb); 860 861 /* handle encapsulation skb */ 862 if (skb->encapsulation) { 863 /* If this is a not UDP/GRE encapsulation skb */ 864 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) { 865 /* drop the skb tunnel packet if hardware don't support, 866 * because hardware can't calculate csum when TSO. 867 */ 868 if (skb_is_gso(skb)) 869 return -EDOM; 870 871 /* the stack computes the IP header already, 872 * driver calculate l4 checksum when not TSO. 873 */ 874 skb_checksum_help(skb); 875 return 0; 876 } 877 878 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec); 879 880 /* switch to inner header */ 881 l2_hdr = skb_inner_mac_header(skb); 882 l3.hdr = skb_inner_network_header(skb); 883 l4.hdr = skb_inner_transport_header(skb); 884 l4_proto = il4_proto; 885 } 886 887 if (l3.v4->version == 4) { 888 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 889 HNS3_L3T_IPV4); 890 891 /* the stack computes the IP header already, the only time we 892 * need the hardware to recompute it is in the case of TSO. 893 */ 894 if (skb_is_gso(skb)) 895 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 896 } else if (l3.v6->version == 6) { 897 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 898 HNS3_L3T_IPV6); 899 } 900 901 /* compute inner(/normal) L2 header size, defined in 2 Bytes */ 902 l2_len = l3.hdr - l2_hdr; 903 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 904 905 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 906 l3_len = l4.hdr - l3.hdr; 907 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 908 909 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 910 switch (l4_proto) { 911 case IPPROTO_TCP: 912 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 913 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 914 HNS3_L4T_TCP); 915 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 916 l4.tcp->doff); 917 break; 918 case IPPROTO_UDP: 919 if (hns3_tunnel_csum_bug(skb)) 920 break; 921 922 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 923 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 924 HNS3_L4T_UDP); 925 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 926 (sizeof(struct udphdr) >> 2)); 927 break; 928 case IPPROTO_SCTP: 929 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 930 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 931 HNS3_L4T_SCTP); 932 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 933 (sizeof(struct sctphdr) >> 2)); 934 break; 935 default: 936 /* drop the skb tunnel packet if hardware don't support, 937 * because hardware can't calculate csum when TSO. 938 */ 939 if (skb_is_gso(skb)) 940 return -EDOM; 941 942 /* the stack computes the IP header already, 943 * driver calculate l4 checksum when not TSO. 944 */ 945 skb_checksum_help(skb); 946 return 0; 947 } 948 949 return 0; 950 } 951 952 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring, 953 struct sk_buff *skb) 954 { 955 struct hnae3_handle *handle = tx_ring->tqp->handle; 956 struct vlan_ethhdr *vhdr; 957 int rc; 958 959 if (!(skb->protocol == htons(ETH_P_8021Q) || 960 skb_vlan_tag_present(skb))) 961 return 0; 962 963 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN 964 * header is allowed in skb, otherwise it will cause RAS error. 965 */ 966 if (unlikely(skb_vlan_tagged_multi(skb) && 967 handle->port_base_vlan_state == 968 HNAE3_PORT_BASE_VLAN_ENABLE)) 969 return -EINVAL; 970 971 if (skb->protocol == htons(ETH_P_8021Q) && 972 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 973 /* When HW VLAN acceleration is turned off, and the stack 974 * sets the protocol to 802.1q, the driver just need to 975 * set the protocol to the encapsulated ethertype. 976 */ 977 skb->protocol = vlan_get_protocol(skb); 978 return 0; 979 } 980 981 if (skb_vlan_tag_present(skb)) { 982 /* Based on hw strategy, use out_vtag in two layer tag case, 983 * and use inner_vtag in one tag case. 984 */ 985 if (skb->protocol == htons(ETH_P_8021Q) && 986 handle->port_base_vlan_state == 987 HNAE3_PORT_BASE_VLAN_DISABLE) 988 rc = HNS3_OUTER_VLAN_TAG; 989 else 990 rc = HNS3_INNER_VLAN_TAG; 991 992 skb->protocol = vlan_get_protocol(skb); 993 return rc; 994 } 995 996 rc = skb_cow_head(skb, 0); 997 if (unlikely(rc < 0)) 998 return rc; 999 1000 vhdr = (struct vlan_ethhdr *)skb->data; 1001 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT) 1002 & VLAN_PRIO_MASK); 1003 1004 skb->protocol = vlan_get_protocol(skb); 1005 return 0; 1006 } 1007 1008 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring, 1009 struct sk_buff *skb, struct hns3_desc *desc) 1010 { 1011 u32 ol_type_vlan_len_msec = 0; 1012 u32 type_cs_vlan_tso = 0; 1013 u32 paylen = skb->len; 1014 u16 inner_vtag = 0; 1015 u16 out_vtag = 0; 1016 u16 mss = 0; 1017 int ret; 1018 1019 ret = hns3_handle_vtags(ring, skb); 1020 if (unlikely(ret < 0)) { 1021 u64_stats_update_begin(&ring->syncp); 1022 ring->stats.tx_vlan_err++; 1023 u64_stats_update_end(&ring->syncp); 1024 return ret; 1025 } else if (ret == HNS3_INNER_VLAN_TAG) { 1026 inner_vtag = skb_vlan_tag_get(skb); 1027 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1028 VLAN_PRIO_MASK; 1029 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1); 1030 } else if (ret == HNS3_OUTER_VLAN_TAG) { 1031 out_vtag = skb_vlan_tag_get(skb); 1032 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1033 VLAN_PRIO_MASK; 1034 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B, 1035 1); 1036 } 1037 1038 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1039 u8 ol4_proto, il4_proto; 1040 1041 skb_reset_mac_len(skb); 1042 1043 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1044 if (unlikely(ret < 0)) { 1045 u64_stats_update_begin(&ring->syncp); 1046 ring->stats.tx_l4_proto_err++; 1047 u64_stats_update_end(&ring->syncp); 1048 return ret; 1049 } 1050 1051 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto, 1052 &type_cs_vlan_tso, 1053 &ol_type_vlan_len_msec); 1054 if (unlikely(ret < 0)) { 1055 u64_stats_update_begin(&ring->syncp); 1056 ring->stats.tx_l2l3l4_err++; 1057 u64_stats_update_end(&ring->syncp); 1058 return ret; 1059 } 1060 1061 ret = hns3_set_tso(skb, &paylen, &mss, 1062 &type_cs_vlan_tso); 1063 if (unlikely(ret < 0)) { 1064 u64_stats_update_begin(&ring->syncp); 1065 ring->stats.tx_tso_err++; 1066 u64_stats_update_end(&ring->syncp); 1067 return ret; 1068 } 1069 } 1070 1071 /* Set txbd */ 1072 desc->tx.ol_type_vlan_len_msec = 1073 cpu_to_le32(ol_type_vlan_len_msec); 1074 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso); 1075 desc->tx.paylen = cpu_to_le32(paylen); 1076 desc->tx.mss = cpu_to_le16(mss); 1077 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1078 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1079 1080 return 0; 1081 } 1082 1083 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 1084 unsigned int size, enum hns_desc_type type) 1085 { 1086 #define HNS3_LIKELY_BD_NUM 1 1087 1088 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1089 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1090 struct device *dev = ring_to_dev(ring); 1091 skb_frag_t *frag; 1092 unsigned int frag_buf_num; 1093 int k, sizeoflast; 1094 dma_addr_t dma; 1095 1096 if (type == DESC_TYPE_SKB) { 1097 struct sk_buff *skb = (struct sk_buff *)priv; 1098 int ret; 1099 1100 ret = hns3_fill_skb_desc(ring, skb, desc); 1101 if (unlikely(ret < 0)) 1102 return ret; 1103 1104 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1105 } else if (type == DESC_TYPE_FRAGLIST_SKB) { 1106 struct sk_buff *skb = (struct sk_buff *)priv; 1107 1108 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1109 } else { 1110 frag = (skb_frag_t *)priv; 1111 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1112 } 1113 1114 if (unlikely(dma_mapping_error(dev, dma))) { 1115 u64_stats_update_begin(&ring->syncp); 1116 ring->stats.sw_err_cnt++; 1117 u64_stats_update_end(&ring->syncp); 1118 return -ENOMEM; 1119 } 1120 1121 desc_cb->length = size; 1122 1123 if (likely(size <= HNS3_MAX_BD_SIZE)) { 1124 desc_cb->priv = priv; 1125 desc_cb->dma = dma; 1126 desc_cb->type = type; 1127 desc->addr = cpu_to_le64(dma); 1128 desc->tx.send_size = cpu_to_le16(size); 1129 desc->tx.bdtp_fe_sc_vld_ra_ri = 1130 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1131 1132 trace_hns3_tx_desc(ring, ring->next_to_use); 1133 ring_ptr_move_fw(ring, next_to_use); 1134 return HNS3_LIKELY_BD_NUM; 1135 } 1136 1137 frag_buf_num = hns3_tx_bd_count(size); 1138 sizeoflast = size & HNS3_TX_LAST_SIZE_M; 1139 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1140 1141 /* When frag size is bigger than hardware limit, split this frag */ 1142 for (k = 0; k < frag_buf_num; k++) { 1143 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */ 1144 desc_cb->priv = priv; 1145 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k; 1146 desc_cb->type = ((type == DESC_TYPE_FRAGLIST_SKB || 1147 type == DESC_TYPE_SKB) && !k) ? 1148 type : DESC_TYPE_PAGE; 1149 1150 /* now, fill the descriptor */ 1151 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1152 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1153 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1154 desc->tx.bdtp_fe_sc_vld_ra_ri = 1155 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1156 1157 trace_hns3_tx_desc(ring, ring->next_to_use); 1158 /* move ring pointer to next */ 1159 ring_ptr_move_fw(ring, next_to_use); 1160 1161 desc_cb = &ring->desc_cb[ring->next_to_use]; 1162 desc = &ring->desc[ring->next_to_use]; 1163 } 1164 1165 return frag_buf_num; 1166 } 1167 1168 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1169 unsigned int bd_num) 1170 { 1171 unsigned int size; 1172 int i; 1173 1174 size = skb_headlen(skb); 1175 while (size > HNS3_MAX_BD_SIZE) { 1176 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1177 size -= HNS3_MAX_BD_SIZE; 1178 1179 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1180 return bd_num; 1181 } 1182 1183 if (size) { 1184 bd_size[bd_num++] = size; 1185 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1186 return bd_num; 1187 } 1188 1189 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1190 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1191 size = skb_frag_size(frag); 1192 if (!size) 1193 continue; 1194 1195 while (size > HNS3_MAX_BD_SIZE) { 1196 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1197 size -= HNS3_MAX_BD_SIZE; 1198 1199 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1200 return bd_num; 1201 } 1202 1203 bd_size[bd_num++] = size; 1204 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1205 return bd_num; 1206 } 1207 1208 return bd_num; 1209 } 1210 1211 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size) 1212 { 1213 struct sk_buff *frag_skb; 1214 unsigned int bd_num = 0; 1215 1216 /* If the total len is within the max bd limit */ 1217 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !skb_has_frag_list(skb) && 1218 skb_shinfo(skb)->nr_frags < HNS3_MAX_NON_TSO_BD_NUM)) 1219 return skb_shinfo(skb)->nr_frags + 1U; 1220 1221 /* The below case will always be linearized, return 1222 * HNS3_MAX_BD_NUM_TSO + 1U to make sure it is linearized. 1223 */ 1224 if (unlikely(skb->len > HNS3_MAX_TSO_SIZE || 1225 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE))) 1226 return HNS3_MAX_TSO_BD_NUM + 1U; 1227 1228 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num); 1229 1230 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM) 1231 return bd_num; 1232 1233 skb_walk_frags(skb, frag_skb) { 1234 bd_num = hns3_skb_bd_num(frag_skb, bd_size, bd_num); 1235 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1236 return bd_num; 1237 } 1238 1239 return bd_num; 1240 } 1241 1242 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb) 1243 { 1244 if (!skb->encapsulation) 1245 return skb_transport_offset(skb) + tcp_hdrlen(skb); 1246 1247 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb); 1248 } 1249 1250 /* HW need every continuous 8 buffer data to be larger than MSS, 1251 * we simplify it by ensuring skb_headlen + the first continuous 1252 * 7 frags to to be larger than gso header len + mss, and the remaining 1253 * continuous 7 frags to be larger than MSS except the last 7 frags. 1254 */ 1255 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size, 1256 unsigned int bd_num) 1257 { 1258 unsigned int tot_len = 0; 1259 int i; 1260 1261 for (i = 0; i < HNS3_MAX_NON_TSO_BD_NUM - 1U; i++) 1262 tot_len += bd_size[i]; 1263 1264 /* ensure the first 8 frags is greater than mss + header */ 1265 if (tot_len + bd_size[HNS3_MAX_NON_TSO_BD_NUM - 1U] < 1266 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb)) 1267 return true; 1268 1269 /* ensure every continuous 7 buffer is greater than mss 1270 * except the last one. 1271 */ 1272 for (i = 0; i < bd_num - HNS3_MAX_NON_TSO_BD_NUM; i++) { 1273 tot_len -= bd_size[i]; 1274 tot_len += bd_size[i + HNS3_MAX_NON_TSO_BD_NUM - 1U]; 1275 1276 if (tot_len < skb_shinfo(skb)->gso_size) 1277 return true; 1278 } 1279 1280 return false; 1281 } 1282 1283 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size) 1284 { 1285 int i = 0; 1286 1287 for (i = 0; i < MAX_SKB_FRAGS; i++) 1288 size[i] = skb_frag_size(&shinfo->frags[i]); 1289 } 1290 1291 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring, 1292 struct net_device *netdev, 1293 struct sk_buff *skb) 1294 { 1295 struct hns3_nic_priv *priv = netdev_priv(netdev); 1296 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U]; 1297 unsigned int bd_num; 1298 1299 bd_num = hns3_tx_bd_num(skb, bd_size); 1300 if (unlikely(bd_num > HNS3_MAX_NON_TSO_BD_NUM)) { 1301 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) && 1302 !hns3_skb_need_linearized(skb, bd_size, bd_num)) { 1303 trace_hns3_over_8bd(skb); 1304 goto out; 1305 } 1306 1307 if (__skb_linearize(skb)) 1308 return -ENOMEM; 1309 1310 bd_num = hns3_tx_bd_count(skb->len); 1311 if ((skb_is_gso(skb) && bd_num > HNS3_MAX_TSO_BD_NUM) || 1312 (!skb_is_gso(skb) && 1313 bd_num > HNS3_MAX_NON_TSO_BD_NUM)) { 1314 trace_hns3_over_8bd(skb); 1315 return -ENOMEM; 1316 } 1317 1318 u64_stats_update_begin(&ring->syncp); 1319 ring->stats.tx_copy++; 1320 u64_stats_update_end(&ring->syncp); 1321 } 1322 1323 out: 1324 if (likely(ring_space(ring) >= bd_num)) 1325 return bd_num; 1326 1327 netif_stop_subqueue(netdev, ring->queue_index); 1328 smp_mb(); /* Memory barrier before checking ring_space */ 1329 1330 /* Start queue in case hns3_clean_tx_ring has just made room 1331 * available and has not seen the queue stopped state performed 1332 * by netif_stop_subqueue above. 1333 */ 1334 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) && 1335 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 1336 netif_start_subqueue(netdev, ring->queue_index); 1337 return bd_num; 1338 } 1339 1340 return -EBUSY; 1341 } 1342 1343 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1344 { 1345 struct device *dev = ring_to_dev(ring); 1346 unsigned int i; 1347 1348 for (i = 0; i < ring->desc_num; i++) { 1349 /* check if this is where we started */ 1350 if (ring->next_to_use == next_to_use_orig) 1351 break; 1352 1353 /* rollback one */ 1354 ring_ptr_move_bw(ring, next_to_use); 1355 1356 /* unmap the descriptor dma address */ 1357 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB || 1358 ring->desc_cb[ring->next_to_use].type == 1359 DESC_TYPE_FRAGLIST_SKB) 1360 dma_unmap_single(dev, 1361 ring->desc_cb[ring->next_to_use].dma, 1362 ring->desc_cb[ring->next_to_use].length, 1363 DMA_TO_DEVICE); 1364 else if (ring->desc_cb[ring->next_to_use].length) 1365 dma_unmap_page(dev, 1366 ring->desc_cb[ring->next_to_use].dma, 1367 ring->desc_cb[ring->next_to_use].length, 1368 DMA_TO_DEVICE); 1369 1370 ring->desc_cb[ring->next_to_use].length = 0; 1371 ring->desc_cb[ring->next_to_use].dma = 0; 1372 } 1373 } 1374 1375 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring, 1376 struct sk_buff *skb, enum hns_desc_type type) 1377 { 1378 unsigned int size = skb_headlen(skb); 1379 int i, ret, bd_num = 0; 1380 1381 if (size) { 1382 ret = hns3_fill_desc(ring, skb, size, type); 1383 if (unlikely(ret < 0)) 1384 return ret; 1385 1386 bd_num += ret; 1387 } 1388 1389 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1390 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1391 1392 size = skb_frag_size(frag); 1393 if (!size) 1394 continue; 1395 1396 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE); 1397 if (unlikely(ret < 0)) 1398 return ret; 1399 1400 bd_num += ret; 1401 } 1402 1403 return bd_num; 1404 } 1405 1406 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1407 { 1408 struct hns3_nic_priv *priv = netdev_priv(netdev); 1409 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping]; 1410 struct netdev_queue *dev_queue; 1411 int pre_ntu, next_to_use_head; 1412 struct sk_buff *frag_skb; 1413 int bd_num = 0; 1414 int ret; 1415 1416 /* Hardware can only handle short frames above 32 bytes */ 1417 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) 1418 return NETDEV_TX_OK; 1419 1420 /* Prefetch the data used later */ 1421 prefetch(skb->data); 1422 1423 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb); 1424 if (unlikely(ret <= 0)) { 1425 if (ret == -EBUSY) { 1426 u64_stats_update_begin(&ring->syncp); 1427 ring->stats.tx_busy++; 1428 u64_stats_update_end(&ring->syncp); 1429 return NETDEV_TX_BUSY; 1430 } else if (ret == -ENOMEM) { 1431 u64_stats_update_begin(&ring->syncp); 1432 ring->stats.sw_err_cnt++; 1433 u64_stats_update_end(&ring->syncp); 1434 } 1435 1436 hns3_rl_err(netdev, "xmit error: %d!\n", ret); 1437 goto out_err_tx_ok; 1438 } 1439 1440 next_to_use_head = ring->next_to_use; 1441 1442 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB); 1443 if (unlikely(ret < 0)) 1444 goto fill_err; 1445 1446 bd_num += ret; 1447 1448 if (!skb_has_frag_list(skb)) 1449 goto out; 1450 1451 skb_walk_frags(skb, frag_skb) { 1452 ret = hns3_fill_skb_to_desc(ring, frag_skb, 1453 DESC_TYPE_FRAGLIST_SKB); 1454 if (unlikely(ret < 0)) 1455 goto fill_err; 1456 1457 bd_num += ret; 1458 } 1459 out: 1460 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) : 1461 (ring->desc_num - 1); 1462 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |= 1463 cpu_to_le16(BIT(HNS3_TXD_FE_B)); 1464 trace_hns3_tx_desc(ring, pre_ntu); 1465 1466 /* Complete translate all packets */ 1467 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index); 1468 netdev_tx_sent_queue(dev_queue, skb->len); 1469 1470 wmb(); /* Commit all data before submit */ 1471 1472 hnae3_queue_xmit(ring->tqp, bd_num); 1473 1474 return NETDEV_TX_OK; 1475 1476 fill_err: 1477 hns3_clear_desc(ring, next_to_use_head); 1478 1479 out_err_tx_ok: 1480 dev_kfree_skb_any(skb); 1481 return NETDEV_TX_OK; 1482 } 1483 1484 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1485 { 1486 struct hnae3_handle *h = hns3_get_handle(netdev); 1487 struct sockaddr *mac_addr = p; 1488 int ret; 1489 1490 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1491 return -EADDRNOTAVAIL; 1492 1493 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1494 netdev_info(netdev, "already using mac address %pM\n", 1495 mac_addr->sa_data); 1496 return 0; 1497 } 1498 1499 /* For VF device, if there is a perm_addr, then the user will not 1500 * be allowed to change the address. 1501 */ 1502 if (!hns3_is_phys_func(h->pdev) && 1503 !is_zero_ether_addr(netdev->perm_addr)) { 1504 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n", 1505 netdev->perm_addr, mac_addr->sa_data); 1506 return -EPERM; 1507 } 1508 1509 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1510 if (ret) { 1511 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1512 return ret; 1513 } 1514 1515 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1516 1517 return 0; 1518 } 1519 1520 static int hns3_nic_do_ioctl(struct net_device *netdev, 1521 struct ifreq *ifr, int cmd) 1522 { 1523 struct hnae3_handle *h = hns3_get_handle(netdev); 1524 1525 if (!netif_running(netdev)) 1526 return -EINVAL; 1527 1528 if (!h->ae_algo->ops->do_ioctl) 1529 return -EOPNOTSUPP; 1530 1531 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 1532 } 1533 1534 static int hns3_nic_set_features(struct net_device *netdev, 1535 netdev_features_t features) 1536 { 1537 netdev_features_t changed = netdev->features ^ features; 1538 struct hns3_nic_priv *priv = netdev_priv(netdev); 1539 struct hnae3_handle *h = priv->ae_handle; 1540 bool enable; 1541 int ret; 1542 1543 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 1544 enable = !!(features & NETIF_F_GRO_HW); 1545 ret = h->ae_algo->ops->set_gro_en(h, enable); 1546 if (ret) 1547 return ret; 1548 } 1549 1550 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 1551 h->ae_algo->ops->enable_vlan_filter) { 1552 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER); 1553 h->ae_algo->ops->enable_vlan_filter(h, enable); 1554 } 1555 1556 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1557 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1558 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 1559 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 1560 if (ret) 1561 return ret; 1562 } 1563 1564 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 1565 enable = !!(features & NETIF_F_NTUPLE); 1566 h->ae_algo->ops->enable_fd(h, enable); 1567 } 1568 1569 netdev->features = features; 1570 return 0; 1571 } 1572 1573 static netdev_features_t hns3_features_check(struct sk_buff *skb, 1574 struct net_device *dev, 1575 netdev_features_t features) 1576 { 1577 #define HNS3_MAX_HDR_LEN 480U 1578 #define HNS3_MAX_L4_HDR_LEN 60U 1579 1580 size_t len; 1581 1582 if (skb->ip_summed != CHECKSUM_PARTIAL) 1583 return features; 1584 1585 if (skb->encapsulation) 1586 len = skb_inner_transport_header(skb) - skb->data; 1587 else 1588 len = skb_transport_header(skb) - skb->data; 1589 1590 /* Assume L4 is 60 byte as TCP is the only protocol with a 1591 * a flexible value, and it's max len is 60 bytes. 1592 */ 1593 len += HNS3_MAX_L4_HDR_LEN; 1594 1595 /* Hardware only supports checksum on the skb with a max header 1596 * len of 480 bytes. 1597 */ 1598 if (len > HNS3_MAX_HDR_LEN) 1599 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 1600 1601 return features; 1602 } 1603 1604 static void hns3_nic_get_stats64(struct net_device *netdev, 1605 struct rtnl_link_stats64 *stats) 1606 { 1607 struct hns3_nic_priv *priv = netdev_priv(netdev); 1608 int queue_num = priv->ae_handle->kinfo.num_tqps; 1609 struct hnae3_handle *handle = priv->ae_handle; 1610 struct hns3_enet_ring *ring; 1611 u64 rx_length_errors = 0; 1612 u64 rx_crc_errors = 0; 1613 u64 rx_multicast = 0; 1614 unsigned int start; 1615 u64 tx_errors = 0; 1616 u64 rx_errors = 0; 1617 unsigned int idx; 1618 u64 tx_bytes = 0; 1619 u64 rx_bytes = 0; 1620 u64 tx_pkts = 0; 1621 u64 rx_pkts = 0; 1622 u64 tx_drop = 0; 1623 u64 rx_drop = 0; 1624 1625 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1626 return; 1627 1628 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1629 1630 for (idx = 0; idx < queue_num; idx++) { 1631 /* fetch the tx stats */ 1632 ring = &priv->ring[idx]; 1633 do { 1634 start = u64_stats_fetch_begin_irq(&ring->syncp); 1635 tx_bytes += ring->stats.tx_bytes; 1636 tx_pkts += ring->stats.tx_pkts; 1637 tx_drop += ring->stats.sw_err_cnt; 1638 tx_drop += ring->stats.tx_vlan_err; 1639 tx_drop += ring->stats.tx_l4_proto_err; 1640 tx_drop += ring->stats.tx_l2l3l4_err; 1641 tx_drop += ring->stats.tx_tso_err; 1642 tx_errors += ring->stats.sw_err_cnt; 1643 tx_errors += ring->stats.tx_vlan_err; 1644 tx_errors += ring->stats.tx_l4_proto_err; 1645 tx_errors += ring->stats.tx_l2l3l4_err; 1646 tx_errors += ring->stats.tx_tso_err; 1647 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1648 1649 /* fetch the rx stats */ 1650 ring = &priv->ring[idx + queue_num]; 1651 do { 1652 start = u64_stats_fetch_begin_irq(&ring->syncp); 1653 rx_bytes += ring->stats.rx_bytes; 1654 rx_pkts += ring->stats.rx_pkts; 1655 rx_drop += ring->stats.l2_err; 1656 rx_errors += ring->stats.l2_err; 1657 rx_errors += ring->stats.l3l4_csum_err; 1658 rx_crc_errors += ring->stats.l2_err; 1659 rx_multicast += ring->stats.rx_multicast; 1660 rx_length_errors += ring->stats.err_pkt_len; 1661 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1662 } 1663 1664 stats->tx_bytes = tx_bytes; 1665 stats->tx_packets = tx_pkts; 1666 stats->rx_bytes = rx_bytes; 1667 stats->rx_packets = rx_pkts; 1668 1669 stats->rx_errors = rx_errors; 1670 stats->multicast = rx_multicast; 1671 stats->rx_length_errors = rx_length_errors; 1672 stats->rx_crc_errors = rx_crc_errors; 1673 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1674 1675 stats->tx_errors = tx_errors; 1676 stats->rx_dropped = rx_drop; 1677 stats->tx_dropped = tx_drop; 1678 stats->collisions = netdev->stats.collisions; 1679 stats->rx_over_errors = netdev->stats.rx_over_errors; 1680 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1681 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1682 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1683 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1684 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1685 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1686 stats->tx_window_errors = netdev->stats.tx_window_errors; 1687 stats->rx_compressed = netdev->stats.rx_compressed; 1688 stats->tx_compressed = netdev->stats.tx_compressed; 1689 } 1690 1691 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1692 { 1693 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1694 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map; 1695 struct hnae3_knic_private_info *kinfo; 1696 u8 tc = mqprio_qopt->qopt.num_tc; 1697 u16 mode = mqprio_qopt->mode; 1698 u8 hw = mqprio_qopt->qopt.hw; 1699 struct hnae3_handle *h; 1700 1701 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1702 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1703 return -EOPNOTSUPP; 1704 1705 if (tc > HNAE3_MAX_TC) 1706 return -EINVAL; 1707 1708 if (!netdev) 1709 return -EINVAL; 1710 1711 h = hns3_get_handle(netdev); 1712 kinfo = &h->kinfo; 1713 1714 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc); 1715 1716 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1717 kinfo->dcb_ops->setup_tc(h, tc ? tc : 1, prio_tc) : -EOPNOTSUPP; 1718 } 1719 1720 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1721 void *type_data) 1722 { 1723 if (type != TC_SETUP_QDISC_MQPRIO) 1724 return -EOPNOTSUPP; 1725 1726 return hns3_setup_tc(dev, type_data); 1727 } 1728 1729 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1730 __be16 proto, u16 vid) 1731 { 1732 struct hnae3_handle *h = hns3_get_handle(netdev); 1733 int ret = -EIO; 1734 1735 if (h->ae_algo->ops->set_vlan_filter) 1736 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1737 1738 return ret; 1739 } 1740 1741 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1742 __be16 proto, u16 vid) 1743 { 1744 struct hnae3_handle *h = hns3_get_handle(netdev); 1745 int ret = -EIO; 1746 1747 if (h->ae_algo->ops->set_vlan_filter) 1748 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1749 1750 return ret; 1751 } 1752 1753 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1754 u8 qos, __be16 vlan_proto) 1755 { 1756 struct hnae3_handle *h = hns3_get_handle(netdev); 1757 int ret = -EIO; 1758 1759 netif_dbg(h, drv, netdev, 1760 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n", 1761 vf, vlan, qos, ntohs(vlan_proto)); 1762 1763 if (h->ae_algo->ops->set_vf_vlan_filter) 1764 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1765 qos, vlan_proto); 1766 1767 return ret; 1768 } 1769 1770 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable) 1771 { 1772 struct hnae3_handle *handle = hns3_get_handle(netdev); 1773 1774 if (hns3_nic_resetting(netdev)) 1775 return -EBUSY; 1776 1777 if (!handle->ae_algo->ops->set_vf_spoofchk) 1778 return -EOPNOTSUPP; 1779 1780 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable); 1781 } 1782 1783 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable) 1784 { 1785 struct hnae3_handle *handle = hns3_get_handle(netdev); 1786 1787 if (!handle->ae_algo->ops->set_vf_trust) 1788 return -EOPNOTSUPP; 1789 1790 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable); 1791 } 1792 1793 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1794 { 1795 struct hnae3_handle *h = hns3_get_handle(netdev); 1796 int ret; 1797 1798 if (hns3_nic_resetting(netdev)) 1799 return -EBUSY; 1800 1801 if (!h->ae_algo->ops->set_mtu) 1802 return -EOPNOTSUPP; 1803 1804 netif_dbg(h, drv, netdev, 1805 "change mtu from %u to %d\n", netdev->mtu, new_mtu); 1806 1807 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 1808 if (ret) 1809 netdev_err(netdev, "failed to change MTU in hardware %d\n", 1810 ret); 1811 else 1812 netdev->mtu = new_mtu; 1813 1814 return ret; 1815 } 1816 1817 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 1818 { 1819 struct hns3_nic_priv *priv = netdev_priv(ndev); 1820 struct hnae3_handle *h = hns3_get_handle(ndev); 1821 struct hns3_enet_ring *tx_ring; 1822 struct napi_struct *napi; 1823 int timeout_queue = 0; 1824 int hw_head, hw_tail; 1825 int fbd_num, fbd_oft; 1826 int ebd_num, ebd_oft; 1827 int bd_num, bd_err; 1828 int ring_en, tc; 1829 int i; 1830 1831 /* Find the stopped queue the same way the stack does */ 1832 for (i = 0; i < ndev->num_tx_queues; i++) { 1833 struct netdev_queue *q; 1834 unsigned long trans_start; 1835 1836 q = netdev_get_tx_queue(ndev, i); 1837 trans_start = q->trans_start; 1838 if (netif_xmit_stopped(q) && 1839 time_after(jiffies, 1840 (trans_start + ndev->watchdog_timeo))) { 1841 timeout_queue = i; 1842 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n", 1843 q->state, 1844 jiffies_to_msecs(jiffies - trans_start)); 1845 break; 1846 } 1847 } 1848 1849 if (i == ndev->num_tx_queues) { 1850 netdev_info(ndev, 1851 "no netdev TX timeout queue found, timeout count: %llu\n", 1852 priv->tx_timeout_count); 1853 return false; 1854 } 1855 1856 priv->tx_timeout_count++; 1857 1858 tx_ring = &priv->ring[timeout_queue]; 1859 napi = &tx_ring->tqp_vector->napi; 1860 1861 netdev_info(ndev, 1862 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n", 1863 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use, 1864 tx_ring->next_to_clean, napi->state); 1865 1866 netdev_info(ndev, 1867 "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n", 1868 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes, 1869 tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt); 1870 1871 netdev_info(ndev, 1872 "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n", 1873 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt, 1874 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy); 1875 1876 /* When mac received many pause frames continuous, it's unable to send 1877 * packets, which may cause tx timeout 1878 */ 1879 if (h->ae_algo->ops->get_mac_stats) { 1880 struct hns3_mac_stats mac_stats; 1881 1882 h->ae_algo->ops->get_mac_stats(h, &mac_stats); 1883 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n", 1884 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt); 1885 } 1886 1887 hw_head = readl_relaxed(tx_ring->tqp->io_base + 1888 HNS3_RING_TX_RING_HEAD_REG); 1889 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 1890 HNS3_RING_TX_RING_TAIL_REG); 1891 fbd_num = readl_relaxed(tx_ring->tqp->io_base + 1892 HNS3_RING_TX_RING_FBDNUM_REG); 1893 fbd_oft = readl_relaxed(tx_ring->tqp->io_base + 1894 HNS3_RING_TX_RING_OFFSET_REG); 1895 ebd_num = readl_relaxed(tx_ring->tqp->io_base + 1896 HNS3_RING_TX_RING_EBDNUM_REG); 1897 ebd_oft = readl_relaxed(tx_ring->tqp->io_base + 1898 HNS3_RING_TX_RING_EBD_OFFSET_REG); 1899 bd_num = readl_relaxed(tx_ring->tqp->io_base + 1900 HNS3_RING_TX_RING_BD_NUM_REG); 1901 bd_err = readl_relaxed(tx_ring->tqp->io_base + 1902 HNS3_RING_TX_RING_BD_ERR_REG); 1903 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG); 1904 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG); 1905 1906 netdev_info(ndev, 1907 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n", 1908 bd_num, hw_head, hw_tail, bd_err, 1909 readl(tx_ring->tqp_vector->mask_addr)); 1910 netdev_info(ndev, 1911 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n", 1912 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft); 1913 1914 return true; 1915 } 1916 1917 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue) 1918 { 1919 struct hns3_nic_priv *priv = netdev_priv(ndev); 1920 struct hnae3_handle *h = priv->ae_handle; 1921 1922 if (!hns3_get_tx_timeo_queue_info(ndev)) 1923 return; 1924 1925 /* request the reset, and let the hclge to determine 1926 * which reset level should be done 1927 */ 1928 if (h->ae_algo->ops->reset_event) 1929 h->ae_algo->ops->reset_event(h->pdev, h); 1930 } 1931 1932 #ifdef CONFIG_RFS_ACCEL 1933 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 1934 u16 rxq_index, u32 flow_id) 1935 { 1936 struct hnae3_handle *h = hns3_get_handle(dev); 1937 struct flow_keys fkeys; 1938 1939 if (!h->ae_algo->ops->add_arfs_entry) 1940 return -EOPNOTSUPP; 1941 1942 if (skb->encapsulation) 1943 return -EPROTONOSUPPORT; 1944 1945 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0)) 1946 return -EPROTONOSUPPORT; 1947 1948 if ((fkeys.basic.n_proto != htons(ETH_P_IP) && 1949 fkeys.basic.n_proto != htons(ETH_P_IPV6)) || 1950 (fkeys.basic.ip_proto != IPPROTO_TCP && 1951 fkeys.basic.ip_proto != IPPROTO_UDP)) 1952 return -EPROTONOSUPPORT; 1953 1954 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys); 1955 } 1956 #endif 1957 1958 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf, 1959 struct ifla_vf_info *ivf) 1960 { 1961 struct hnae3_handle *h = hns3_get_handle(ndev); 1962 1963 if (!h->ae_algo->ops->get_vf_config) 1964 return -EOPNOTSUPP; 1965 1966 return h->ae_algo->ops->get_vf_config(h, vf, ivf); 1967 } 1968 1969 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf, 1970 int link_state) 1971 { 1972 struct hnae3_handle *h = hns3_get_handle(ndev); 1973 1974 if (!h->ae_algo->ops->set_vf_link_state) 1975 return -EOPNOTSUPP; 1976 1977 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state); 1978 } 1979 1980 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf, 1981 int min_tx_rate, int max_tx_rate) 1982 { 1983 struct hnae3_handle *h = hns3_get_handle(ndev); 1984 1985 if (!h->ae_algo->ops->set_vf_rate) 1986 return -EOPNOTSUPP; 1987 1988 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate, 1989 false); 1990 } 1991 1992 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) 1993 { 1994 struct hnae3_handle *h = hns3_get_handle(netdev); 1995 1996 if (!h->ae_algo->ops->set_vf_mac) 1997 return -EOPNOTSUPP; 1998 1999 if (is_multicast_ether_addr(mac)) { 2000 netdev_err(netdev, 2001 "Invalid MAC:%pM specified. Could not set MAC\n", 2002 mac); 2003 return -EINVAL; 2004 } 2005 2006 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac); 2007 } 2008 2009 static const struct net_device_ops hns3_nic_netdev_ops = { 2010 .ndo_open = hns3_nic_net_open, 2011 .ndo_stop = hns3_nic_net_stop, 2012 .ndo_start_xmit = hns3_nic_net_xmit, 2013 .ndo_tx_timeout = hns3_nic_net_timeout, 2014 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 2015 .ndo_do_ioctl = hns3_nic_do_ioctl, 2016 .ndo_change_mtu = hns3_nic_change_mtu, 2017 .ndo_set_features = hns3_nic_set_features, 2018 .ndo_features_check = hns3_features_check, 2019 .ndo_get_stats64 = hns3_nic_get_stats64, 2020 .ndo_setup_tc = hns3_nic_setup_tc, 2021 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 2022 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 2023 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 2024 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 2025 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk, 2026 .ndo_set_vf_trust = hns3_set_vf_trust, 2027 #ifdef CONFIG_RFS_ACCEL 2028 .ndo_rx_flow_steer = hns3_rx_flow_steer, 2029 #endif 2030 .ndo_get_vf_config = hns3_nic_get_vf_config, 2031 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state, 2032 .ndo_set_vf_rate = hns3_nic_set_vf_rate, 2033 .ndo_set_vf_mac = hns3_nic_set_vf_mac, 2034 }; 2035 2036 bool hns3_is_phys_func(struct pci_dev *pdev) 2037 { 2038 u32 dev_id = pdev->device; 2039 2040 switch (dev_id) { 2041 case HNAE3_DEV_ID_GE: 2042 case HNAE3_DEV_ID_25GE: 2043 case HNAE3_DEV_ID_25GE_RDMA: 2044 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 2045 case HNAE3_DEV_ID_50GE_RDMA: 2046 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 2047 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 2048 return true; 2049 case HNAE3_DEV_ID_100G_VF: 2050 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF: 2051 return false; 2052 default: 2053 dev_warn(&pdev->dev, "un-recognized pci device-id %u", 2054 dev_id); 2055 } 2056 2057 return false; 2058 } 2059 2060 static void hns3_disable_sriov(struct pci_dev *pdev) 2061 { 2062 /* If our VFs are assigned we cannot shut down SR-IOV 2063 * without causing issues, so just leave the hardware 2064 * available but disabled 2065 */ 2066 if (pci_vfs_assigned(pdev)) { 2067 dev_warn(&pdev->dev, 2068 "disabling driver while VFs are assigned\n"); 2069 return; 2070 } 2071 2072 pci_disable_sriov(pdev); 2073 } 2074 2075 static void hns3_get_dev_capability(struct pci_dev *pdev, 2076 struct hnae3_ae_dev *ae_dev) 2077 { 2078 if (pdev->revision >= 0x21) { 2079 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1); 2080 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1); 2081 } 2082 } 2083 2084 /* hns3_probe - Device initialization routine 2085 * @pdev: PCI device information struct 2086 * @ent: entry in hns3_pci_tbl 2087 * 2088 * hns3_probe initializes a PF identified by a pci_dev structure. 2089 * The OS initialization, configuring of the PF private structure, 2090 * and a hardware reset occur. 2091 * 2092 * Returns 0 on success, negative on failure 2093 */ 2094 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2095 { 2096 struct hnae3_ae_dev *ae_dev; 2097 int ret; 2098 2099 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL); 2100 if (!ae_dev) 2101 return -ENOMEM; 2102 2103 ae_dev->pdev = pdev; 2104 ae_dev->flag = ent->driver_data; 2105 hns3_get_dev_capability(pdev, ae_dev); 2106 pci_set_drvdata(pdev, ae_dev); 2107 2108 ret = hnae3_register_ae_dev(ae_dev); 2109 if (ret) { 2110 devm_kfree(&pdev->dev, ae_dev); 2111 pci_set_drvdata(pdev, NULL); 2112 } 2113 2114 return ret; 2115 } 2116 2117 /* hns3_remove - Device removal routine 2118 * @pdev: PCI device information struct 2119 */ 2120 static void hns3_remove(struct pci_dev *pdev) 2121 { 2122 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2123 2124 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 2125 hns3_disable_sriov(pdev); 2126 2127 hnae3_unregister_ae_dev(ae_dev); 2128 pci_set_drvdata(pdev, NULL); 2129 } 2130 2131 /** 2132 * hns3_pci_sriov_configure 2133 * @pdev: pointer to a pci_dev structure 2134 * @num_vfs: number of VFs to allocate 2135 * 2136 * Enable or change the number of VFs. Called when the user updates the number 2137 * of VFs in sysfs. 2138 **/ 2139 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 2140 { 2141 int ret; 2142 2143 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 2144 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 2145 return -EINVAL; 2146 } 2147 2148 if (num_vfs) { 2149 ret = pci_enable_sriov(pdev, num_vfs); 2150 if (ret) 2151 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 2152 else 2153 return num_vfs; 2154 } else if (!pci_vfs_assigned(pdev)) { 2155 pci_disable_sriov(pdev); 2156 } else { 2157 dev_warn(&pdev->dev, 2158 "Unable to free VFs because some are assigned to VMs.\n"); 2159 } 2160 2161 return 0; 2162 } 2163 2164 static void hns3_shutdown(struct pci_dev *pdev) 2165 { 2166 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2167 2168 hnae3_unregister_ae_dev(ae_dev); 2169 devm_kfree(&pdev->dev, ae_dev); 2170 pci_set_drvdata(pdev, NULL); 2171 2172 if (system_state == SYSTEM_POWER_OFF) 2173 pci_set_power_state(pdev, PCI_D3hot); 2174 } 2175 2176 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 2177 pci_channel_state_t state) 2178 { 2179 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2180 pci_ers_result_t ret; 2181 2182 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state); 2183 2184 if (state == pci_channel_io_perm_failure) 2185 return PCI_ERS_RESULT_DISCONNECT; 2186 2187 if (!ae_dev || !ae_dev->ops) { 2188 dev_err(&pdev->dev, 2189 "Can't recover - error happened before device initialized\n"); 2190 return PCI_ERS_RESULT_NONE; 2191 } 2192 2193 if (ae_dev->ops->handle_hw_ras_error) 2194 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 2195 else 2196 return PCI_ERS_RESULT_NONE; 2197 2198 return ret; 2199 } 2200 2201 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 2202 { 2203 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2204 const struct hnae3_ae_ops *ops; 2205 enum hnae3_reset_type reset_type; 2206 struct device *dev = &pdev->dev; 2207 2208 if (!ae_dev || !ae_dev->ops) 2209 return PCI_ERS_RESULT_NONE; 2210 2211 ops = ae_dev->ops; 2212 /* request the reset */ 2213 if (ops->reset_event && ops->get_reset_level && 2214 ops->set_default_reset_request) { 2215 if (ae_dev->hw_err_reset_req) { 2216 reset_type = ops->get_reset_level(ae_dev, 2217 &ae_dev->hw_err_reset_req); 2218 ops->set_default_reset_request(ae_dev, reset_type); 2219 dev_info(dev, "requesting reset due to PCI error\n"); 2220 ops->reset_event(pdev, NULL); 2221 } 2222 2223 return PCI_ERS_RESULT_RECOVERED; 2224 } 2225 2226 return PCI_ERS_RESULT_DISCONNECT; 2227 } 2228 2229 static void hns3_reset_prepare(struct pci_dev *pdev) 2230 { 2231 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2232 2233 dev_info(&pdev->dev, "FLR prepare\n"); 2234 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare) 2235 ae_dev->ops->flr_prepare(ae_dev); 2236 } 2237 2238 static void hns3_reset_done(struct pci_dev *pdev) 2239 { 2240 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2241 2242 dev_info(&pdev->dev, "FLR done\n"); 2243 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done) 2244 ae_dev->ops->flr_done(ae_dev); 2245 } 2246 2247 static const struct pci_error_handlers hns3_err_handler = { 2248 .error_detected = hns3_error_detected, 2249 .slot_reset = hns3_slot_reset, 2250 .reset_prepare = hns3_reset_prepare, 2251 .reset_done = hns3_reset_done, 2252 }; 2253 2254 static struct pci_driver hns3_driver = { 2255 .name = hns3_driver_name, 2256 .id_table = hns3_pci_tbl, 2257 .probe = hns3_probe, 2258 .remove = hns3_remove, 2259 .shutdown = hns3_shutdown, 2260 .sriov_configure = hns3_pci_sriov_configure, 2261 .err_handler = &hns3_err_handler, 2262 }; 2263 2264 /* set default feature to hns3 */ 2265 static void hns3_set_default_feature(struct net_device *netdev) 2266 { 2267 struct hnae3_handle *h = hns3_get_handle(netdev); 2268 struct pci_dev *pdev = h->pdev; 2269 2270 netdev->priv_flags |= IFF_UNICAST_FLT; 2271 2272 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2273 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2274 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2275 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2276 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2277 NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST; 2278 2279 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 2280 2281 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2282 NETIF_F_HW_VLAN_CTAG_FILTER | 2283 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2284 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2285 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2286 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2287 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2288 NETIF_F_FRAGLIST; 2289 2290 netdev->vlan_features |= 2291 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | 2292 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 2293 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2294 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2295 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2296 NETIF_F_FRAGLIST; 2297 2298 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2299 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2300 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2301 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2302 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2303 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2304 NETIF_F_FRAGLIST; 2305 2306 if (pdev->revision >= 0x21) { 2307 netdev->hw_features |= NETIF_F_GRO_HW; 2308 netdev->features |= NETIF_F_GRO_HW; 2309 2310 if (!(h->flags & HNAE3_SUPPORT_VF)) { 2311 netdev->hw_features |= NETIF_F_NTUPLE; 2312 netdev->features |= NETIF_F_NTUPLE; 2313 } 2314 } 2315 } 2316 2317 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 2318 struct hns3_desc_cb *cb) 2319 { 2320 unsigned int order = hns3_page_order(ring); 2321 struct page *p; 2322 2323 p = dev_alloc_pages(order); 2324 if (!p) 2325 return -ENOMEM; 2326 2327 cb->priv = p; 2328 cb->page_offset = 0; 2329 cb->reuse_flag = 0; 2330 cb->buf = page_address(p); 2331 cb->length = hns3_page_size(ring); 2332 cb->type = DESC_TYPE_PAGE; 2333 2334 return 0; 2335 } 2336 2337 static void hns3_free_buffer(struct hns3_enet_ring *ring, 2338 struct hns3_desc_cb *cb) 2339 { 2340 if (cb->type == DESC_TYPE_SKB) 2341 dev_kfree_skb_any((struct sk_buff *)cb->priv); 2342 else if (!HNAE3_IS_TX_RING(ring)) 2343 put_page((struct page *)cb->priv); 2344 memset(cb, 0, sizeof(*cb)); 2345 } 2346 2347 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 2348 { 2349 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 2350 cb->length, ring_to_dma_dir(ring)); 2351 2352 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 2353 return -EIO; 2354 2355 return 0; 2356 } 2357 2358 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 2359 struct hns3_desc_cb *cb) 2360 { 2361 if (cb->type == DESC_TYPE_SKB || cb->type == DESC_TYPE_FRAGLIST_SKB) 2362 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 2363 ring_to_dma_dir(ring)); 2364 else if (cb->length) 2365 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 2366 ring_to_dma_dir(ring)); 2367 } 2368 2369 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 2370 { 2371 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2372 ring->desc[i].addr = 0; 2373 } 2374 2375 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i) 2376 { 2377 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 2378 2379 if (!ring->desc_cb[i].dma) 2380 return; 2381 2382 hns3_buffer_detach(ring, i); 2383 hns3_free_buffer(ring, cb); 2384 } 2385 2386 static void hns3_free_buffers(struct hns3_enet_ring *ring) 2387 { 2388 int i; 2389 2390 for (i = 0; i < ring->desc_num; i++) 2391 hns3_free_buffer_detach(ring, i); 2392 } 2393 2394 /* free desc along with its attached buffer */ 2395 static void hns3_free_desc(struct hns3_enet_ring *ring) 2396 { 2397 int size = ring->desc_num * sizeof(ring->desc[0]); 2398 2399 hns3_free_buffers(ring); 2400 2401 if (ring->desc) { 2402 dma_free_coherent(ring_to_dev(ring), size, 2403 ring->desc, ring->desc_dma_addr); 2404 ring->desc = NULL; 2405 } 2406 } 2407 2408 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 2409 { 2410 int size = ring->desc_num * sizeof(ring->desc[0]); 2411 2412 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 2413 &ring->desc_dma_addr, GFP_KERNEL); 2414 if (!ring->desc) 2415 return -ENOMEM; 2416 2417 return 0; 2418 } 2419 2420 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring, 2421 struct hns3_desc_cb *cb) 2422 { 2423 int ret; 2424 2425 ret = hns3_alloc_buffer(ring, cb); 2426 if (ret) 2427 goto out; 2428 2429 ret = hns3_map_buffer(ring, cb); 2430 if (ret) 2431 goto out_with_buf; 2432 2433 return 0; 2434 2435 out_with_buf: 2436 hns3_free_buffer(ring, cb); 2437 out: 2438 return ret; 2439 } 2440 2441 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i) 2442 { 2443 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]); 2444 2445 if (ret) 2446 return ret; 2447 2448 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2449 2450 return 0; 2451 } 2452 2453 /* Allocate memory for raw pkg, and map with dma */ 2454 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 2455 { 2456 int i, j, ret; 2457 2458 for (i = 0; i < ring->desc_num; i++) { 2459 ret = hns3_alloc_buffer_attach(ring, i); 2460 if (ret) 2461 goto out_buffer_fail; 2462 } 2463 2464 return 0; 2465 2466 out_buffer_fail: 2467 for (j = i - 1; j >= 0; j--) 2468 hns3_free_buffer_detach(ring, j); 2469 return ret; 2470 } 2471 2472 /* detach a in-used buffer and replace with a reserved one */ 2473 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 2474 struct hns3_desc_cb *res_cb) 2475 { 2476 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2477 ring->desc_cb[i] = *res_cb; 2478 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2479 ring->desc[i].rx.bd_base_info = 0; 2480 } 2481 2482 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 2483 { 2484 ring->desc_cb[i].reuse_flag = 0; 2485 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 2486 ring->desc_cb[i].page_offset); 2487 ring->desc[i].rx.bd_base_info = 0; 2488 } 2489 2490 static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head, 2491 int *bytes, int *pkts) 2492 { 2493 int ntc = ring->next_to_clean; 2494 struct hns3_desc_cb *desc_cb; 2495 2496 while (head != ntc) { 2497 desc_cb = &ring->desc_cb[ntc]; 2498 (*pkts) += (desc_cb->type == DESC_TYPE_SKB); 2499 (*bytes) += desc_cb->length; 2500 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */ 2501 hns3_free_buffer_detach(ring, ntc); 2502 2503 if (++ntc == ring->desc_num) 2504 ntc = 0; 2505 2506 /* Issue prefetch for next Tx descriptor */ 2507 prefetch(&ring->desc_cb[ntc]); 2508 } 2509 2510 /* This smp_store_release() pairs with smp_load_acquire() in 2511 * ring_space called by hns3_nic_net_xmit. 2512 */ 2513 smp_store_release(&ring->next_to_clean, ntc); 2514 } 2515 2516 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h) 2517 { 2518 int u = ring->next_to_use; 2519 int c = ring->next_to_clean; 2520 2521 if (unlikely(h > ring->desc_num)) 2522 return 0; 2523 2524 return u > c ? (h > c && h <= u) : (h > c || h <= u); 2525 } 2526 2527 void hns3_clean_tx_ring(struct hns3_enet_ring *ring) 2528 { 2529 struct net_device *netdev = ring_to_netdev(ring); 2530 struct hns3_nic_priv *priv = netdev_priv(netdev); 2531 struct netdev_queue *dev_queue; 2532 int bytes, pkts; 2533 int head; 2534 2535 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG); 2536 2537 if (is_ring_empty(ring) || head == ring->next_to_clean) 2538 return; /* no data to poll */ 2539 2540 rmb(); /* Make sure head is ready before touch any data */ 2541 2542 if (unlikely(!is_valid_clean_head(ring, head))) { 2543 hns3_rl_err(netdev, "wrong head (%d, %d-%d)\n", head, 2544 ring->next_to_use, ring->next_to_clean); 2545 2546 u64_stats_update_begin(&ring->syncp); 2547 ring->stats.io_err_cnt++; 2548 u64_stats_update_end(&ring->syncp); 2549 return; 2550 } 2551 2552 bytes = 0; 2553 pkts = 0; 2554 hns3_nic_reclaim_desc(ring, head, &bytes, &pkts); 2555 2556 ring->tqp_vector->tx_group.total_bytes += bytes; 2557 ring->tqp_vector->tx_group.total_packets += pkts; 2558 2559 u64_stats_update_begin(&ring->syncp); 2560 ring->stats.tx_bytes += bytes; 2561 ring->stats.tx_pkts += pkts; 2562 u64_stats_update_end(&ring->syncp); 2563 2564 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 2565 netdev_tx_completed_queue(dev_queue, pkts, bytes); 2566 2567 if (unlikely(netif_carrier_ok(netdev) && 2568 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) { 2569 /* Make sure that anybody stopping the queue after this 2570 * sees the new next_to_clean. 2571 */ 2572 smp_mb(); 2573 if (netif_tx_queue_stopped(dev_queue) && 2574 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 2575 netif_tx_wake_queue(dev_queue); 2576 ring->stats.restart_queue++; 2577 } 2578 } 2579 } 2580 2581 static int hns3_desc_unused(struct hns3_enet_ring *ring) 2582 { 2583 int ntc = ring->next_to_clean; 2584 int ntu = ring->next_to_use; 2585 2586 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 2587 } 2588 2589 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, 2590 int cleand_count) 2591 { 2592 struct hns3_desc_cb *desc_cb; 2593 struct hns3_desc_cb res_cbs; 2594 int i, ret; 2595 2596 for (i = 0; i < cleand_count; i++) { 2597 desc_cb = &ring->desc_cb[ring->next_to_use]; 2598 if (desc_cb->reuse_flag) { 2599 u64_stats_update_begin(&ring->syncp); 2600 ring->stats.reuse_pg_cnt++; 2601 u64_stats_update_end(&ring->syncp); 2602 2603 hns3_reuse_buffer(ring, ring->next_to_use); 2604 } else { 2605 ret = hns3_reserve_buffer_map(ring, &res_cbs); 2606 if (ret) { 2607 u64_stats_update_begin(&ring->syncp); 2608 ring->stats.sw_err_cnt++; 2609 u64_stats_update_end(&ring->syncp); 2610 2611 hns3_rl_err(ring_to_netdev(ring), 2612 "alloc rx buffer failed: %d\n", 2613 ret); 2614 break; 2615 } 2616 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 2617 2618 u64_stats_update_begin(&ring->syncp); 2619 ring->stats.non_reuse_pg++; 2620 u64_stats_update_end(&ring->syncp); 2621 } 2622 2623 ring_ptr_move_fw(ring, next_to_use); 2624 } 2625 2626 wmb(); /* Make all data has been write before submit */ 2627 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2628 } 2629 2630 static bool hns3_page_is_reusable(struct page *page) 2631 { 2632 return page_to_nid(page) == numa_mem_id() && 2633 !page_is_pfmemalloc(page); 2634 } 2635 2636 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2637 struct hns3_enet_ring *ring, int pull_len, 2638 struct hns3_desc_cb *desc_cb) 2639 { 2640 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 2641 int size = le16_to_cpu(desc->rx.size); 2642 u32 truesize = hns3_buf_size(ring); 2643 2644 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2645 size - pull_len, truesize); 2646 2647 /* Avoid re-using remote pages, or the stack is still using the page 2648 * when page_offset rollback to zero, flag default unreuse 2649 */ 2650 if (unlikely(!hns3_page_is_reusable(desc_cb->priv)) || 2651 (!desc_cb->page_offset && page_count(desc_cb->priv) > 1)) 2652 return; 2653 2654 /* Move offset up to the next cache line */ 2655 desc_cb->page_offset += truesize; 2656 2657 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) { 2658 desc_cb->reuse_flag = 1; 2659 /* Bump ref count on page before it is given */ 2660 get_page(desc_cb->priv); 2661 } else if (page_count(desc_cb->priv) == 1) { 2662 desc_cb->reuse_flag = 1; 2663 desc_cb->page_offset = 0; 2664 get_page(desc_cb->priv); 2665 } 2666 } 2667 2668 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) 2669 { 2670 __be16 type = skb->protocol; 2671 struct tcphdr *th; 2672 int depth = 0; 2673 2674 while (eth_type_vlan(type)) { 2675 struct vlan_hdr *vh; 2676 2677 if ((depth + VLAN_HLEN) > skb_headlen(skb)) 2678 return -EFAULT; 2679 2680 vh = (struct vlan_hdr *)(skb->data + depth); 2681 type = vh->h_vlan_encapsulated_proto; 2682 depth += VLAN_HLEN; 2683 } 2684 2685 skb_set_network_header(skb, depth); 2686 2687 if (type == htons(ETH_P_IP)) { 2688 const struct iphdr *iph = ip_hdr(skb); 2689 2690 depth += sizeof(struct iphdr); 2691 skb_set_transport_header(skb, depth); 2692 th = tcp_hdr(skb); 2693 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr, 2694 iph->daddr, 0); 2695 } else if (type == htons(ETH_P_IPV6)) { 2696 const struct ipv6hdr *iph = ipv6_hdr(skb); 2697 2698 depth += sizeof(struct ipv6hdr); 2699 skb_set_transport_header(skb, depth); 2700 th = tcp_hdr(skb); 2701 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr, 2702 &iph->daddr, 0); 2703 } else { 2704 hns3_rl_err(skb->dev, 2705 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n", 2706 be16_to_cpu(type), depth); 2707 return -EFAULT; 2708 } 2709 2710 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 2711 if (th->cwr) 2712 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 2713 2714 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B)) 2715 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID; 2716 2717 skb->csum_start = (unsigned char *)th - skb->head; 2718 skb->csum_offset = offsetof(struct tcphdr, check); 2719 skb->ip_summed = CHECKSUM_PARTIAL; 2720 2721 trace_hns3_gro(skb); 2722 2723 return 0; 2724 } 2725 2726 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2727 u32 l234info, u32 bd_base_info, u32 ol_info) 2728 { 2729 struct net_device *netdev = ring_to_netdev(ring); 2730 int l3_type, l4_type; 2731 int ol4_type; 2732 2733 skb->ip_summed = CHECKSUM_NONE; 2734 2735 skb_checksum_none_assert(skb); 2736 2737 if (!(netdev->features & NETIF_F_RXCSUM)) 2738 return; 2739 2740 /* check if hardware has done checksum */ 2741 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 2742 return; 2743 2744 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | 2745 BIT(HNS3_RXD_OL3E_B) | 2746 BIT(HNS3_RXD_OL4E_B)))) { 2747 u64_stats_update_begin(&ring->syncp); 2748 ring->stats.l3l4_csum_err++; 2749 u64_stats_update_end(&ring->syncp); 2750 2751 return; 2752 } 2753 2754 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M, 2755 HNS3_RXD_OL4ID_S); 2756 switch (ol4_type) { 2757 case HNS3_OL4_TYPE_MAC_IN_UDP: 2758 case HNS3_OL4_TYPE_NVGRE: 2759 skb->csum_level = 1; 2760 /* fall through */ 2761 case HNS3_OL4_TYPE_NO_TUN: 2762 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2763 HNS3_RXD_L3ID_S); 2764 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 2765 HNS3_RXD_L4ID_S); 2766 2767 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 2768 if ((l3_type == HNS3_L3_TYPE_IPV4 || 2769 l3_type == HNS3_L3_TYPE_IPV6) && 2770 (l4_type == HNS3_L4_TYPE_UDP || 2771 l4_type == HNS3_L4_TYPE_TCP || 2772 l4_type == HNS3_L4_TYPE_SCTP)) 2773 skb->ip_summed = CHECKSUM_UNNECESSARY; 2774 break; 2775 default: 2776 break; 2777 } 2778 } 2779 2780 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 2781 { 2782 if (skb_has_frag_list(skb)) 2783 napi_gro_flush(&ring->tqp_vector->napi, false); 2784 2785 napi_gro_receive(&ring->tqp_vector->napi, skb); 2786 } 2787 2788 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 2789 struct hns3_desc *desc, u32 l234info, 2790 u16 *vlan_tag) 2791 { 2792 struct hnae3_handle *handle = ring->tqp->handle; 2793 struct pci_dev *pdev = ring->tqp->handle->pdev; 2794 2795 if (pdev->revision == 0x20) { 2796 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2797 if (!(*vlan_tag & VLAN_VID_MASK)) 2798 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2799 2800 return (*vlan_tag != 0); 2801 } 2802 2803 #define HNS3_STRP_OUTER_VLAN 0x1 2804 #define HNS3_STRP_INNER_VLAN 0x2 2805 #define HNS3_STRP_BOTH 0x3 2806 2807 /* Hardware always insert VLAN tag into RX descriptor when 2808 * remove the tag from packet, driver needs to determine 2809 * reporting which tag to stack. 2810 */ 2811 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 2812 HNS3_RXD_STRP_TAGP_S)) { 2813 case HNS3_STRP_OUTER_VLAN: 2814 if (handle->port_base_vlan_state != 2815 HNAE3_PORT_BASE_VLAN_DISABLE) 2816 return false; 2817 2818 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2819 return true; 2820 case HNS3_STRP_INNER_VLAN: 2821 if (handle->port_base_vlan_state != 2822 HNAE3_PORT_BASE_VLAN_DISABLE) 2823 return false; 2824 2825 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2826 return true; 2827 case HNS3_STRP_BOTH: 2828 if (handle->port_base_vlan_state == 2829 HNAE3_PORT_BASE_VLAN_DISABLE) 2830 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2831 else 2832 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2833 2834 return true; 2835 default: 2836 return false; 2837 } 2838 } 2839 2840 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length, 2841 unsigned char *va) 2842 { 2843 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2844 struct net_device *netdev = ring_to_netdev(ring); 2845 struct sk_buff *skb; 2846 2847 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 2848 skb = ring->skb; 2849 if (unlikely(!skb)) { 2850 hns3_rl_err(netdev, "alloc rx skb fail\n"); 2851 2852 u64_stats_update_begin(&ring->syncp); 2853 ring->stats.sw_err_cnt++; 2854 u64_stats_update_end(&ring->syncp); 2855 2856 return -ENOMEM; 2857 } 2858 2859 trace_hns3_rx_desc(ring); 2860 prefetchw(skb->data); 2861 2862 ring->pending_buf = 1; 2863 ring->frag_num = 0; 2864 ring->tail_skb = NULL; 2865 if (length <= HNS3_RX_HEAD_SIZE) { 2866 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 2867 2868 /* We can reuse buffer as-is, just make sure it is local */ 2869 if (likely(hns3_page_is_reusable(desc_cb->priv))) 2870 desc_cb->reuse_flag = 1; 2871 else /* This page cannot be reused so discard it */ 2872 put_page(desc_cb->priv); 2873 2874 ring_ptr_move_fw(ring, next_to_clean); 2875 return 0; 2876 } 2877 u64_stats_update_begin(&ring->syncp); 2878 ring->stats.seg_pkt_cnt++; 2879 u64_stats_update_end(&ring->syncp); 2880 2881 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE); 2882 __skb_put(skb, ring->pull_len); 2883 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 2884 desc_cb); 2885 ring_ptr_move_fw(ring, next_to_clean); 2886 2887 return 0; 2888 } 2889 2890 static int hns3_add_frag(struct hns3_enet_ring *ring) 2891 { 2892 struct sk_buff *skb = ring->skb; 2893 struct sk_buff *head_skb = skb; 2894 struct sk_buff *new_skb; 2895 struct hns3_desc_cb *desc_cb; 2896 struct hns3_desc *desc; 2897 u32 bd_base_info; 2898 2899 do { 2900 desc = &ring->desc[ring->next_to_clean]; 2901 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2902 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2903 /* make sure HW write desc complete */ 2904 dma_rmb(); 2905 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 2906 return -ENXIO; 2907 2908 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 2909 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0); 2910 if (unlikely(!new_skb)) { 2911 hns3_rl_err(ring_to_netdev(ring), 2912 "alloc rx fraglist skb fail\n"); 2913 return -ENXIO; 2914 } 2915 ring->frag_num = 0; 2916 2917 if (ring->tail_skb) { 2918 ring->tail_skb->next = new_skb; 2919 ring->tail_skb = new_skb; 2920 } else { 2921 skb_shinfo(skb)->frag_list = new_skb; 2922 ring->tail_skb = new_skb; 2923 } 2924 } 2925 2926 if (ring->tail_skb) { 2927 head_skb->truesize += hns3_buf_size(ring); 2928 head_skb->data_len += le16_to_cpu(desc->rx.size); 2929 head_skb->len += le16_to_cpu(desc->rx.size); 2930 skb = ring->tail_skb; 2931 } 2932 2933 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 2934 trace_hns3_rx_desc(ring); 2935 ring_ptr_move_fw(ring, next_to_clean); 2936 ring->pending_buf++; 2937 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B))); 2938 2939 return 0; 2940 } 2941 2942 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring, 2943 struct sk_buff *skb, u32 l234info, 2944 u32 bd_base_info, u32 ol_info) 2945 { 2946 u32 l3_type; 2947 2948 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 2949 HNS3_RXD_GRO_SIZE_M, 2950 HNS3_RXD_GRO_SIZE_S); 2951 /* if there is no HW GRO, do not set gro params */ 2952 if (!skb_shinfo(skb)->gso_size) { 2953 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info); 2954 return 0; 2955 } 2956 2957 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info, 2958 HNS3_RXD_GRO_COUNT_M, 2959 HNS3_RXD_GRO_COUNT_S); 2960 2961 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S); 2962 if (l3_type == HNS3_L3_TYPE_IPV4) 2963 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 2964 else if (l3_type == HNS3_L3_TYPE_IPV6) 2965 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 2966 else 2967 return -EFAULT; 2968 2969 return hns3_gro_complete(skb, l234info); 2970 } 2971 2972 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 2973 struct sk_buff *skb, u32 rss_hash) 2974 { 2975 struct hnae3_handle *handle = ring->tqp->handle; 2976 enum pkt_hash_types rss_type; 2977 2978 if (rss_hash) 2979 rss_type = handle->kinfo.rss_type; 2980 else 2981 rss_type = PKT_HASH_TYPE_NONE; 2982 2983 skb_set_hash(skb, rss_hash, rss_type); 2984 } 2985 2986 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb) 2987 { 2988 struct net_device *netdev = ring_to_netdev(ring); 2989 enum hns3_pkt_l2t_type l2_frame_type; 2990 u32 bd_base_info, l234info, ol_info; 2991 struct hns3_desc *desc; 2992 unsigned int len; 2993 int pre_ntc, ret; 2994 2995 /* bdinfo handled below is only valid on the last BD of the 2996 * current packet, and ring->next_to_clean indicates the first 2997 * descriptor of next packet, so need - 1 below. 2998 */ 2999 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) : 3000 (ring->desc_num - 1); 3001 desc = &ring->desc[pre_ntc]; 3002 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3003 l234info = le32_to_cpu(desc->rx.l234_info); 3004 ol_info = le32_to_cpu(desc->rx.ol_info); 3005 3006 /* Based on hw strategy, the tag offloaded will be stored at 3007 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 3008 * in one layer tag case. 3009 */ 3010 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 3011 u16 vlan_tag; 3012 3013 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 3014 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 3015 vlan_tag); 3016 } 3017 3018 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 3019 BIT(HNS3_RXD_L2E_B))))) { 3020 u64_stats_update_begin(&ring->syncp); 3021 if (l234info & BIT(HNS3_RXD_L2E_B)) 3022 ring->stats.l2_err++; 3023 else 3024 ring->stats.err_pkt_len++; 3025 u64_stats_update_end(&ring->syncp); 3026 3027 return -EFAULT; 3028 } 3029 3030 len = skb->len; 3031 3032 /* Do update ip stack process */ 3033 skb->protocol = eth_type_trans(skb, netdev); 3034 3035 /* This is needed in order to enable forwarding support */ 3036 ret = hns3_set_gro_and_checksum(ring, skb, l234info, 3037 bd_base_info, ol_info); 3038 if (unlikely(ret)) { 3039 u64_stats_update_begin(&ring->syncp); 3040 ring->stats.rx_err_cnt++; 3041 u64_stats_update_end(&ring->syncp); 3042 return ret; 3043 } 3044 3045 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 3046 HNS3_RXD_DMAC_S); 3047 3048 u64_stats_update_begin(&ring->syncp); 3049 ring->stats.rx_pkts++; 3050 ring->stats.rx_bytes += len; 3051 3052 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 3053 ring->stats.rx_multicast++; 3054 3055 u64_stats_update_end(&ring->syncp); 3056 3057 ring->tqp_vector->rx_group.total_bytes += len; 3058 3059 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash)); 3060 return 0; 3061 } 3062 3063 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring) 3064 { 3065 struct sk_buff *skb = ring->skb; 3066 struct hns3_desc_cb *desc_cb; 3067 struct hns3_desc *desc; 3068 unsigned int length; 3069 u32 bd_base_info; 3070 int ret; 3071 3072 desc = &ring->desc[ring->next_to_clean]; 3073 desc_cb = &ring->desc_cb[ring->next_to_clean]; 3074 3075 prefetch(desc); 3076 3077 length = le16_to_cpu(desc->rx.size); 3078 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3079 3080 /* Check valid BD */ 3081 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 3082 return -ENXIO; 3083 3084 if (!skb) 3085 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset; 3086 3087 /* Prefetch first cache line of first page 3088 * Idea is to cache few bytes of the header of the packet. Our L1 Cache 3089 * line size is 64B so need to prefetch twice to make it 128B. But in 3090 * actual we can have greater size of caches with 128B Level 1 cache 3091 * lines. In such a case, single fetch would suffice to cache in the 3092 * relevant part of the header. 3093 */ 3094 prefetch(ring->va); 3095 #if L1_CACHE_BYTES < 128 3096 prefetch(ring->va + L1_CACHE_BYTES); 3097 #endif 3098 3099 if (!skb) { 3100 ret = hns3_alloc_skb(ring, length, ring->va); 3101 skb = ring->skb; 3102 3103 if (ret < 0) /* alloc buffer fail */ 3104 return ret; 3105 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */ 3106 ret = hns3_add_frag(ring); 3107 if (ret) 3108 return ret; 3109 } 3110 } else { 3111 ret = hns3_add_frag(ring); 3112 if (ret) 3113 return ret; 3114 } 3115 3116 /* As the head data may be changed when GRO enable, copy 3117 * the head data in after other data rx completed 3118 */ 3119 if (skb->len > HNS3_RX_HEAD_SIZE) 3120 memcpy(skb->data, ring->va, 3121 ALIGN(ring->pull_len, sizeof(long))); 3122 3123 ret = hns3_handle_bdinfo(ring, skb); 3124 if (unlikely(ret)) { 3125 dev_kfree_skb_any(skb); 3126 return ret; 3127 } 3128 3129 skb_record_rx_queue(skb, ring->tqp->tqp_index); 3130 return 0; 3131 } 3132 3133 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget, 3134 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 3135 { 3136 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 3137 int unused_count = hns3_desc_unused(ring); 3138 int recv_pkts = 0; 3139 int recv_bds = 0; 3140 int err, num; 3141 3142 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG); 3143 num -= unused_count; 3144 unused_count -= ring->pending_buf; 3145 3146 if (num <= 0) 3147 goto out; 3148 3149 rmb(); /* Make sure num taken effect before the other data is touched */ 3150 3151 while (recv_pkts < budget && recv_bds < num) { 3152 /* Reuse or realloc buffers */ 3153 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 3154 hns3_nic_alloc_rx_buffers(ring, unused_count); 3155 unused_count = hns3_desc_unused(ring) - 3156 ring->pending_buf; 3157 } 3158 3159 /* Poll one pkt */ 3160 err = hns3_handle_rx_bd(ring); 3161 /* Do not get FE for the packet or failed to alloc skb */ 3162 if (unlikely(!ring->skb || err == -ENXIO)) { 3163 goto out; 3164 } else if (likely(!err)) { 3165 rx_fn(ring, ring->skb); 3166 recv_pkts++; 3167 } 3168 3169 recv_bds += ring->pending_buf; 3170 unused_count += ring->pending_buf; 3171 ring->skb = NULL; 3172 ring->pending_buf = 0; 3173 } 3174 3175 out: 3176 /* Make all data has been write before submit */ 3177 if (unused_count > 0) 3178 hns3_nic_alloc_rx_buffers(ring, unused_count); 3179 3180 return recv_pkts; 3181 } 3182 3183 static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group) 3184 { 3185 #define HNS3_RX_LOW_BYTE_RATE 10000 3186 #define HNS3_RX_MID_BYTE_RATE 20000 3187 #define HNS3_RX_ULTRA_PACKET_RATE 40 3188 3189 enum hns3_flow_level_range new_flow_level; 3190 struct hns3_enet_tqp_vector *tqp_vector; 3191 int packets_per_msecs, bytes_per_msecs; 3192 u32 time_passed_ms; 3193 3194 tqp_vector = ring_group->ring->tqp_vector; 3195 time_passed_ms = 3196 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 3197 if (!time_passed_ms) 3198 return false; 3199 3200 do_div(ring_group->total_packets, time_passed_ms); 3201 packets_per_msecs = ring_group->total_packets; 3202 3203 do_div(ring_group->total_bytes, time_passed_ms); 3204 bytes_per_msecs = ring_group->total_bytes; 3205 3206 new_flow_level = ring_group->coal.flow_level; 3207 3208 /* Simple throttlerate management 3209 * 0-10MB/s lower (50000 ints/s) 3210 * 10-20MB/s middle (20000 ints/s) 3211 * 20-1249MB/s high (18000 ints/s) 3212 * > 40000pps ultra (8000 ints/s) 3213 */ 3214 switch (new_flow_level) { 3215 case HNS3_FLOW_LOW: 3216 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 3217 new_flow_level = HNS3_FLOW_MID; 3218 break; 3219 case HNS3_FLOW_MID: 3220 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 3221 new_flow_level = HNS3_FLOW_HIGH; 3222 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 3223 new_flow_level = HNS3_FLOW_LOW; 3224 break; 3225 case HNS3_FLOW_HIGH: 3226 case HNS3_FLOW_ULTRA: 3227 default: 3228 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 3229 new_flow_level = HNS3_FLOW_MID; 3230 break; 3231 } 3232 3233 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 3234 &tqp_vector->rx_group == ring_group) 3235 new_flow_level = HNS3_FLOW_ULTRA; 3236 3237 ring_group->total_bytes = 0; 3238 ring_group->total_packets = 0; 3239 ring_group->coal.flow_level = new_flow_level; 3240 3241 return true; 3242 } 3243 3244 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 3245 { 3246 struct hns3_enet_tqp_vector *tqp_vector; 3247 u16 new_int_gl; 3248 3249 if (!ring_group->ring) 3250 return false; 3251 3252 tqp_vector = ring_group->ring->tqp_vector; 3253 if (!tqp_vector->last_jiffies) 3254 return false; 3255 3256 if (ring_group->total_packets == 0) { 3257 ring_group->coal.int_gl = HNS3_INT_GL_50K; 3258 ring_group->coal.flow_level = HNS3_FLOW_LOW; 3259 return true; 3260 } 3261 3262 if (!hns3_get_new_flow_lvl(ring_group)) 3263 return false; 3264 3265 new_int_gl = ring_group->coal.int_gl; 3266 switch (ring_group->coal.flow_level) { 3267 case HNS3_FLOW_LOW: 3268 new_int_gl = HNS3_INT_GL_50K; 3269 break; 3270 case HNS3_FLOW_MID: 3271 new_int_gl = HNS3_INT_GL_20K; 3272 break; 3273 case HNS3_FLOW_HIGH: 3274 new_int_gl = HNS3_INT_GL_18K; 3275 break; 3276 case HNS3_FLOW_ULTRA: 3277 new_int_gl = HNS3_INT_GL_8K; 3278 break; 3279 default: 3280 break; 3281 } 3282 3283 if (new_int_gl != ring_group->coal.int_gl) { 3284 ring_group->coal.int_gl = new_int_gl; 3285 return true; 3286 } 3287 return false; 3288 } 3289 3290 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 3291 { 3292 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 3293 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 3294 bool rx_update, tx_update; 3295 3296 /* update param every 1000ms */ 3297 if (time_before(jiffies, 3298 tqp_vector->last_jiffies + msecs_to_jiffies(1000))) 3299 return; 3300 3301 if (rx_group->coal.gl_adapt_enable) { 3302 rx_update = hns3_get_new_int_gl(rx_group); 3303 if (rx_update) 3304 hns3_set_vector_coalesce_rx_gl(tqp_vector, 3305 rx_group->coal.int_gl); 3306 } 3307 3308 if (tx_group->coal.gl_adapt_enable) { 3309 tx_update = hns3_get_new_int_gl(tx_group); 3310 if (tx_update) 3311 hns3_set_vector_coalesce_tx_gl(tqp_vector, 3312 tx_group->coal.int_gl); 3313 } 3314 3315 tqp_vector->last_jiffies = jiffies; 3316 } 3317 3318 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 3319 { 3320 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 3321 struct hns3_enet_ring *ring; 3322 int rx_pkt_total = 0; 3323 3324 struct hns3_enet_tqp_vector *tqp_vector = 3325 container_of(napi, struct hns3_enet_tqp_vector, napi); 3326 bool clean_complete = true; 3327 int rx_budget = budget; 3328 3329 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3330 napi_complete(napi); 3331 return 0; 3332 } 3333 3334 /* Since the actual Tx work is minimal, we can give the Tx a larger 3335 * budget and be more aggressive about cleaning up the Tx descriptors. 3336 */ 3337 hns3_for_each_ring(ring, tqp_vector->tx_group) 3338 hns3_clean_tx_ring(ring); 3339 3340 /* make sure rx ring budget not smaller than 1 */ 3341 if (tqp_vector->num_tqps > 1) 3342 rx_budget = max(budget / tqp_vector->num_tqps, 1); 3343 3344 hns3_for_each_ring(ring, tqp_vector->rx_group) { 3345 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 3346 hns3_rx_skb); 3347 3348 if (rx_cleaned >= rx_budget) 3349 clean_complete = false; 3350 3351 rx_pkt_total += rx_cleaned; 3352 } 3353 3354 tqp_vector->rx_group.total_packets += rx_pkt_total; 3355 3356 if (!clean_complete) 3357 return budget; 3358 3359 if (napi_complete(napi) && 3360 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3361 hns3_update_new_int_gl(tqp_vector); 3362 hns3_mask_vector_irq(tqp_vector, 1); 3363 } 3364 3365 return rx_pkt_total; 3366 } 3367 3368 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3369 struct hnae3_ring_chain_node *head) 3370 { 3371 struct pci_dev *pdev = tqp_vector->handle->pdev; 3372 struct hnae3_ring_chain_node *cur_chain = head; 3373 struct hnae3_ring_chain_node *chain; 3374 struct hns3_enet_ring *tx_ring; 3375 struct hns3_enet_ring *rx_ring; 3376 3377 tx_ring = tqp_vector->tx_group.ring; 3378 if (tx_ring) { 3379 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 3380 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3381 HNAE3_RING_TYPE_TX); 3382 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3383 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 3384 3385 cur_chain->next = NULL; 3386 3387 while (tx_ring->next) { 3388 tx_ring = tx_ring->next; 3389 3390 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 3391 GFP_KERNEL); 3392 if (!chain) 3393 goto err_free_chain; 3394 3395 cur_chain->next = chain; 3396 chain->tqp_index = tx_ring->tqp->tqp_index; 3397 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3398 HNAE3_RING_TYPE_TX); 3399 hnae3_set_field(chain->int_gl_idx, 3400 HNAE3_RING_GL_IDX_M, 3401 HNAE3_RING_GL_IDX_S, 3402 HNAE3_RING_GL_TX); 3403 3404 cur_chain = chain; 3405 } 3406 } 3407 3408 rx_ring = tqp_vector->rx_group.ring; 3409 if (!tx_ring && rx_ring) { 3410 cur_chain->next = NULL; 3411 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 3412 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3413 HNAE3_RING_TYPE_RX); 3414 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3415 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3416 3417 rx_ring = rx_ring->next; 3418 } 3419 3420 while (rx_ring) { 3421 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 3422 if (!chain) 3423 goto err_free_chain; 3424 3425 cur_chain->next = chain; 3426 chain->tqp_index = rx_ring->tqp->tqp_index; 3427 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3428 HNAE3_RING_TYPE_RX); 3429 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3430 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3431 3432 cur_chain = chain; 3433 3434 rx_ring = rx_ring->next; 3435 } 3436 3437 return 0; 3438 3439 err_free_chain: 3440 cur_chain = head->next; 3441 while (cur_chain) { 3442 chain = cur_chain->next; 3443 devm_kfree(&pdev->dev, cur_chain); 3444 cur_chain = chain; 3445 } 3446 head->next = NULL; 3447 3448 return -ENOMEM; 3449 } 3450 3451 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3452 struct hnae3_ring_chain_node *head) 3453 { 3454 struct pci_dev *pdev = tqp_vector->handle->pdev; 3455 struct hnae3_ring_chain_node *chain_tmp, *chain; 3456 3457 chain = head->next; 3458 3459 while (chain) { 3460 chain_tmp = chain->next; 3461 devm_kfree(&pdev->dev, chain); 3462 chain = chain_tmp; 3463 } 3464 } 3465 3466 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 3467 struct hns3_enet_ring *ring) 3468 { 3469 ring->next = group->ring; 3470 group->ring = ring; 3471 3472 group->count++; 3473 } 3474 3475 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 3476 { 3477 struct pci_dev *pdev = priv->ae_handle->pdev; 3478 struct hns3_enet_tqp_vector *tqp_vector; 3479 int num_vectors = priv->vector_num; 3480 int numa_node; 3481 int vector_i; 3482 3483 numa_node = dev_to_node(&pdev->dev); 3484 3485 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 3486 tqp_vector = &priv->tqp_vector[vector_i]; 3487 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 3488 &tqp_vector->affinity_mask); 3489 } 3490 } 3491 3492 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 3493 { 3494 struct hnae3_ring_chain_node vector_ring_chain; 3495 struct hnae3_handle *h = priv->ae_handle; 3496 struct hns3_enet_tqp_vector *tqp_vector; 3497 int ret = 0; 3498 int i; 3499 3500 hns3_nic_set_cpumask(priv); 3501 3502 for (i = 0; i < priv->vector_num; i++) { 3503 tqp_vector = &priv->tqp_vector[i]; 3504 hns3_vector_gl_rl_init_hw(tqp_vector, priv); 3505 tqp_vector->num_tqps = 0; 3506 } 3507 3508 for (i = 0; i < h->kinfo.num_tqps; i++) { 3509 u16 vector_i = i % priv->vector_num; 3510 u16 tqp_num = h->kinfo.num_tqps; 3511 3512 tqp_vector = &priv->tqp_vector[vector_i]; 3513 3514 hns3_add_ring_to_group(&tqp_vector->tx_group, 3515 &priv->ring[i]); 3516 3517 hns3_add_ring_to_group(&tqp_vector->rx_group, 3518 &priv->ring[i + tqp_num]); 3519 3520 priv->ring[i].tqp_vector = tqp_vector; 3521 priv->ring[i + tqp_num].tqp_vector = tqp_vector; 3522 tqp_vector->num_tqps++; 3523 } 3524 3525 for (i = 0; i < priv->vector_num; i++) { 3526 tqp_vector = &priv->tqp_vector[i]; 3527 3528 tqp_vector->rx_group.total_bytes = 0; 3529 tqp_vector->rx_group.total_packets = 0; 3530 tqp_vector->tx_group.total_bytes = 0; 3531 tqp_vector->tx_group.total_packets = 0; 3532 tqp_vector->handle = h; 3533 3534 ret = hns3_get_vector_ring_chain(tqp_vector, 3535 &vector_ring_chain); 3536 if (ret) 3537 goto map_ring_fail; 3538 3539 ret = h->ae_algo->ops->map_ring_to_vector(h, 3540 tqp_vector->vector_irq, &vector_ring_chain); 3541 3542 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3543 3544 if (ret) 3545 goto map_ring_fail; 3546 3547 netif_napi_add(priv->netdev, &tqp_vector->napi, 3548 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 3549 } 3550 3551 return 0; 3552 3553 map_ring_fail: 3554 while (i--) 3555 netif_napi_del(&priv->tqp_vector[i].napi); 3556 3557 return ret; 3558 } 3559 3560 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 3561 { 3562 #define HNS3_VECTOR_PF_MAX_NUM 64 3563 3564 struct hnae3_handle *h = priv->ae_handle; 3565 struct hns3_enet_tqp_vector *tqp_vector; 3566 struct hnae3_vector_info *vector; 3567 struct pci_dev *pdev = h->pdev; 3568 u16 tqp_num = h->kinfo.num_tqps; 3569 u16 vector_num; 3570 int ret = 0; 3571 u16 i; 3572 3573 /* RSS size, cpu online and vector_num should be the same */ 3574 /* Should consider 2p/4p later */ 3575 vector_num = min_t(u16, num_online_cpus(), tqp_num); 3576 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM); 3577 3578 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 3579 GFP_KERNEL); 3580 if (!vector) 3581 return -ENOMEM; 3582 3583 /* save the actual available vector number */ 3584 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 3585 3586 priv->vector_num = vector_num; 3587 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 3588 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 3589 GFP_KERNEL); 3590 if (!priv->tqp_vector) { 3591 ret = -ENOMEM; 3592 goto out; 3593 } 3594 3595 for (i = 0; i < priv->vector_num; i++) { 3596 tqp_vector = &priv->tqp_vector[i]; 3597 tqp_vector->idx = i; 3598 tqp_vector->mask_addr = vector[i].io_addr; 3599 tqp_vector->vector_irq = vector[i].vector; 3600 hns3_vector_gl_rl_init(tqp_vector, priv); 3601 } 3602 3603 out: 3604 devm_kfree(&pdev->dev, vector); 3605 return ret; 3606 } 3607 3608 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 3609 { 3610 group->ring = NULL; 3611 group->count = 0; 3612 } 3613 3614 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 3615 { 3616 struct hnae3_ring_chain_node vector_ring_chain; 3617 struct hnae3_handle *h = priv->ae_handle; 3618 struct hns3_enet_tqp_vector *tqp_vector; 3619 int i; 3620 3621 for (i = 0; i < priv->vector_num; i++) { 3622 tqp_vector = &priv->tqp_vector[i]; 3623 3624 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 3625 continue; 3626 3627 /* Since the mapping can be overwritten, when fail to get the 3628 * chain between vector and ring, we should go on to deal with 3629 * the remaining options. 3630 */ 3631 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain)) 3632 dev_warn(priv->dev, "failed to get ring chain\n"); 3633 3634 h->ae_algo->ops->unmap_ring_from_vector(h, 3635 tqp_vector->vector_irq, &vector_ring_chain); 3636 3637 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3638 3639 hns3_clear_ring_group(&tqp_vector->rx_group); 3640 hns3_clear_ring_group(&tqp_vector->tx_group); 3641 netif_napi_del(&priv->tqp_vector[i].napi); 3642 } 3643 } 3644 3645 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 3646 { 3647 struct hnae3_handle *h = priv->ae_handle; 3648 struct pci_dev *pdev = h->pdev; 3649 int i, ret; 3650 3651 for (i = 0; i < priv->vector_num; i++) { 3652 struct hns3_enet_tqp_vector *tqp_vector; 3653 3654 tqp_vector = &priv->tqp_vector[i]; 3655 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 3656 if (ret) 3657 return; 3658 } 3659 3660 devm_kfree(&pdev->dev, priv->tqp_vector); 3661 } 3662 3663 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 3664 unsigned int ring_type) 3665 { 3666 int queue_num = priv->ae_handle->kinfo.num_tqps; 3667 struct hns3_enet_ring *ring; 3668 int desc_num; 3669 3670 if (ring_type == HNAE3_RING_TYPE_TX) { 3671 ring = &priv->ring[q->tqp_index]; 3672 desc_num = priv->ae_handle->kinfo.num_tx_desc; 3673 ring->queue_index = q->tqp_index; 3674 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET; 3675 } else { 3676 ring = &priv->ring[q->tqp_index + queue_num]; 3677 desc_num = priv->ae_handle->kinfo.num_rx_desc; 3678 ring->queue_index = q->tqp_index; 3679 ring->io_base = q->io_base; 3680 } 3681 3682 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 3683 3684 ring->tqp = q; 3685 ring->desc = NULL; 3686 ring->desc_cb = NULL; 3687 ring->dev = priv->dev; 3688 ring->desc_dma_addr = 0; 3689 ring->buf_size = q->buf_size; 3690 ring->desc_num = desc_num; 3691 ring->next_to_use = 0; 3692 ring->next_to_clean = 0; 3693 } 3694 3695 static void hns3_queue_to_ring(struct hnae3_queue *tqp, 3696 struct hns3_nic_priv *priv) 3697 { 3698 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 3699 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 3700 } 3701 3702 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 3703 { 3704 struct hnae3_handle *h = priv->ae_handle; 3705 struct pci_dev *pdev = h->pdev; 3706 int i; 3707 3708 priv->ring = devm_kzalloc(&pdev->dev, 3709 array3_size(h->kinfo.num_tqps, 3710 sizeof(*priv->ring), 2), 3711 GFP_KERNEL); 3712 if (!priv->ring) 3713 return -ENOMEM; 3714 3715 for (i = 0; i < h->kinfo.num_tqps; i++) 3716 hns3_queue_to_ring(h->kinfo.tqp[i], priv); 3717 3718 return 0; 3719 } 3720 3721 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 3722 { 3723 if (!priv->ring) 3724 return; 3725 3726 devm_kfree(priv->dev, priv->ring); 3727 priv->ring = NULL; 3728 } 3729 3730 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 3731 { 3732 int ret; 3733 3734 if (ring->desc_num <= 0 || ring->buf_size <= 0) 3735 return -EINVAL; 3736 3737 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num, 3738 sizeof(ring->desc_cb[0]), GFP_KERNEL); 3739 if (!ring->desc_cb) { 3740 ret = -ENOMEM; 3741 goto out; 3742 } 3743 3744 ret = hns3_alloc_desc(ring); 3745 if (ret) 3746 goto out_with_desc_cb; 3747 3748 if (!HNAE3_IS_TX_RING(ring)) { 3749 ret = hns3_alloc_ring_buffers(ring); 3750 if (ret) 3751 goto out_with_desc; 3752 } 3753 3754 return 0; 3755 3756 out_with_desc: 3757 hns3_free_desc(ring); 3758 out_with_desc_cb: 3759 devm_kfree(ring_to_dev(ring), ring->desc_cb); 3760 ring->desc_cb = NULL; 3761 out: 3762 return ret; 3763 } 3764 3765 void hns3_fini_ring(struct hns3_enet_ring *ring) 3766 { 3767 hns3_free_desc(ring); 3768 devm_kfree(ring_to_dev(ring), ring->desc_cb); 3769 ring->desc_cb = NULL; 3770 ring->next_to_clean = 0; 3771 ring->next_to_use = 0; 3772 ring->pending_buf = 0; 3773 if (ring->skb) { 3774 dev_kfree_skb_any(ring->skb); 3775 ring->skb = NULL; 3776 } 3777 } 3778 3779 static int hns3_buf_size2type(u32 buf_size) 3780 { 3781 int bd_size_type; 3782 3783 switch (buf_size) { 3784 case 512: 3785 bd_size_type = HNS3_BD_SIZE_512_TYPE; 3786 break; 3787 case 1024: 3788 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 3789 break; 3790 case 2048: 3791 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3792 break; 3793 case 4096: 3794 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 3795 break; 3796 default: 3797 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3798 } 3799 3800 return bd_size_type; 3801 } 3802 3803 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 3804 { 3805 dma_addr_t dma = ring->desc_dma_addr; 3806 struct hnae3_queue *q = ring->tqp; 3807 3808 if (!HNAE3_IS_TX_RING(ring)) { 3809 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma); 3810 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 3811 (u32)((dma >> 31) >> 1)); 3812 3813 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 3814 hns3_buf_size2type(ring->buf_size)); 3815 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 3816 ring->desc_num / 8 - 1); 3817 3818 } else { 3819 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 3820 (u32)dma); 3821 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 3822 (u32)((dma >> 31) >> 1)); 3823 3824 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 3825 ring->desc_num / 8 - 1); 3826 } 3827 } 3828 3829 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 3830 { 3831 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3832 int i; 3833 3834 for (i = 0; i < HNAE3_MAX_TC; i++) { 3835 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i]; 3836 int j; 3837 3838 if (!tc_info->enable) 3839 continue; 3840 3841 for (j = 0; j < tc_info->tqp_count; j++) { 3842 struct hnae3_queue *q; 3843 3844 q = priv->ring[tc_info->tqp_offset + j].tqp; 3845 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, 3846 tc_info->tc); 3847 } 3848 } 3849 } 3850 3851 int hns3_init_all_ring(struct hns3_nic_priv *priv) 3852 { 3853 struct hnae3_handle *h = priv->ae_handle; 3854 int ring_num = h->kinfo.num_tqps * 2; 3855 int i, j; 3856 int ret; 3857 3858 for (i = 0; i < ring_num; i++) { 3859 ret = hns3_alloc_ring_memory(&priv->ring[i]); 3860 if (ret) { 3861 dev_err(priv->dev, 3862 "Alloc ring memory fail! ret=%d\n", ret); 3863 goto out_when_alloc_ring_memory; 3864 } 3865 3866 u64_stats_init(&priv->ring[i].syncp); 3867 } 3868 3869 return 0; 3870 3871 out_when_alloc_ring_memory: 3872 for (j = i - 1; j >= 0; j--) 3873 hns3_fini_ring(&priv->ring[j]); 3874 3875 return -ENOMEM; 3876 } 3877 3878 int hns3_uninit_all_ring(struct hns3_nic_priv *priv) 3879 { 3880 struct hnae3_handle *h = priv->ae_handle; 3881 int i; 3882 3883 for (i = 0; i < h->kinfo.num_tqps; i++) { 3884 hns3_fini_ring(&priv->ring[i]); 3885 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]); 3886 } 3887 return 0; 3888 } 3889 3890 /* Set mac addr if it is configured. or leave it to the AE driver */ 3891 static int hns3_init_mac_addr(struct net_device *netdev) 3892 { 3893 struct hns3_nic_priv *priv = netdev_priv(netdev); 3894 struct hnae3_handle *h = priv->ae_handle; 3895 u8 mac_addr_temp[ETH_ALEN]; 3896 int ret = 0; 3897 3898 if (h->ae_algo->ops->get_mac_addr) 3899 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 3900 3901 /* Check if the MAC address is valid, if not get a random one */ 3902 if (!is_valid_ether_addr(mac_addr_temp)) { 3903 eth_hw_addr_random(netdev); 3904 dev_warn(priv->dev, "using random MAC address %pM\n", 3905 netdev->dev_addr); 3906 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) { 3907 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 3908 ether_addr_copy(netdev->perm_addr, mac_addr_temp); 3909 } else { 3910 return 0; 3911 } 3912 3913 if (h->ae_algo->ops->set_mac_addr) 3914 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 3915 3916 return ret; 3917 } 3918 3919 static int hns3_init_phy(struct net_device *netdev) 3920 { 3921 struct hnae3_handle *h = hns3_get_handle(netdev); 3922 int ret = 0; 3923 3924 if (h->ae_algo->ops->mac_connect_phy) 3925 ret = h->ae_algo->ops->mac_connect_phy(h); 3926 3927 return ret; 3928 } 3929 3930 static void hns3_uninit_phy(struct net_device *netdev) 3931 { 3932 struct hnae3_handle *h = hns3_get_handle(netdev); 3933 3934 if (h->ae_algo->ops->mac_disconnect_phy) 3935 h->ae_algo->ops->mac_disconnect_phy(h); 3936 } 3937 3938 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list) 3939 { 3940 struct hnae3_handle *h = hns3_get_handle(netdev); 3941 3942 if (h->ae_algo->ops->del_all_fd_entries) 3943 h->ae_algo->ops->del_all_fd_entries(h, clear_list); 3944 } 3945 3946 static int hns3_client_start(struct hnae3_handle *handle) 3947 { 3948 if (!handle->ae_algo->ops->client_start) 3949 return 0; 3950 3951 return handle->ae_algo->ops->client_start(handle); 3952 } 3953 3954 static void hns3_client_stop(struct hnae3_handle *handle) 3955 { 3956 if (!handle->ae_algo->ops->client_stop) 3957 return; 3958 3959 handle->ae_algo->ops->client_stop(handle); 3960 } 3961 3962 static void hns3_info_show(struct hns3_nic_priv *priv) 3963 { 3964 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3965 3966 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr); 3967 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps); 3968 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size); 3969 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size); 3970 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len); 3971 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc); 3972 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc); 3973 dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc); 3974 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu); 3975 } 3976 3977 static int hns3_client_init(struct hnae3_handle *handle) 3978 { 3979 struct pci_dev *pdev = handle->pdev; 3980 u16 alloc_tqps, max_rss_size; 3981 struct hns3_nic_priv *priv; 3982 struct net_device *netdev; 3983 int ret; 3984 3985 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 3986 &max_rss_size); 3987 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 3988 if (!netdev) 3989 return -ENOMEM; 3990 3991 priv = netdev_priv(netdev); 3992 priv->dev = &pdev->dev; 3993 priv->netdev = netdev; 3994 priv->ae_handle = handle; 3995 priv->tx_timeout_count = 0; 3996 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 3997 3998 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL); 3999 4000 handle->kinfo.netdev = netdev; 4001 handle->priv = (void *)priv; 4002 4003 hns3_init_mac_addr(netdev); 4004 4005 hns3_set_default_feature(netdev); 4006 4007 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 4008 netdev->priv_flags |= IFF_UNICAST_FLT; 4009 netdev->netdev_ops = &hns3_nic_netdev_ops; 4010 SET_NETDEV_DEV(netdev, &pdev->dev); 4011 hns3_ethtool_set_ops(netdev); 4012 4013 /* Carrier off reporting is important to ethtool even BEFORE open */ 4014 netif_carrier_off(netdev); 4015 4016 ret = hns3_get_ring_config(priv); 4017 if (ret) { 4018 ret = -ENOMEM; 4019 goto out_get_ring_cfg; 4020 } 4021 4022 ret = hns3_nic_alloc_vector_data(priv); 4023 if (ret) { 4024 ret = -ENOMEM; 4025 goto out_alloc_vector_data; 4026 } 4027 4028 ret = hns3_nic_init_vector_data(priv); 4029 if (ret) { 4030 ret = -ENOMEM; 4031 goto out_init_vector_data; 4032 } 4033 4034 ret = hns3_init_all_ring(priv); 4035 if (ret) { 4036 ret = -ENOMEM; 4037 goto out_init_ring; 4038 } 4039 4040 ret = hns3_init_phy(netdev); 4041 if (ret) 4042 goto out_init_phy; 4043 4044 ret = register_netdev(netdev); 4045 if (ret) { 4046 dev_err(priv->dev, "probe register netdev fail!\n"); 4047 goto out_reg_netdev_fail; 4048 } 4049 4050 /* the device can work without cpu rmap, only aRFS needs it */ 4051 ret = hns3_set_rx_cpu_rmap(netdev); 4052 if (ret) 4053 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 4054 4055 ret = hns3_nic_init_irq(priv); 4056 if (ret) { 4057 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 4058 hns3_free_rx_cpu_rmap(netdev); 4059 goto out_init_irq_fail; 4060 } 4061 4062 ret = hns3_client_start(handle); 4063 if (ret) { 4064 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4065 goto out_client_start; 4066 } 4067 4068 hns3_dcbnl_setup(handle); 4069 4070 hns3_dbg_init(handle); 4071 4072 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */ 4073 netdev->max_mtu = HNS3_MAX_MTU; 4074 4075 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4076 4077 if (netif_msg_drv(handle)) 4078 hns3_info_show(priv); 4079 4080 return ret; 4081 4082 out_client_start: 4083 hns3_free_rx_cpu_rmap(netdev); 4084 hns3_nic_uninit_irq(priv); 4085 out_init_irq_fail: 4086 unregister_netdev(netdev); 4087 out_reg_netdev_fail: 4088 hns3_uninit_phy(netdev); 4089 out_init_phy: 4090 hns3_uninit_all_ring(priv); 4091 out_init_ring: 4092 hns3_nic_uninit_vector_data(priv); 4093 out_init_vector_data: 4094 hns3_nic_dealloc_vector_data(priv); 4095 out_alloc_vector_data: 4096 priv->ring = NULL; 4097 out_get_ring_cfg: 4098 priv->ae_handle = NULL; 4099 free_netdev(netdev); 4100 return ret; 4101 } 4102 4103 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 4104 { 4105 struct net_device *netdev = handle->kinfo.netdev; 4106 struct hns3_nic_priv *priv = netdev_priv(netdev); 4107 int ret; 4108 4109 if (netdev->reg_state != NETREG_UNINITIALIZED) 4110 unregister_netdev(netdev); 4111 4112 hns3_client_stop(handle); 4113 4114 hns3_uninit_phy(netdev); 4115 4116 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4117 netdev_warn(netdev, "already uninitialized\n"); 4118 goto out_netdev_free; 4119 } 4120 4121 hns3_free_rx_cpu_rmap(netdev); 4122 4123 hns3_nic_uninit_irq(priv); 4124 4125 hns3_del_all_fd_rules(netdev, true); 4126 4127 hns3_clear_all_ring(handle, true); 4128 4129 hns3_nic_uninit_vector_data(priv); 4130 4131 hns3_nic_dealloc_vector_data(priv); 4132 4133 ret = hns3_uninit_all_ring(priv); 4134 if (ret) 4135 netdev_err(netdev, "uninit ring error\n"); 4136 4137 hns3_put_ring_config(priv); 4138 4139 hns3_dbg_uninit(handle); 4140 4141 out_netdev_free: 4142 free_netdev(netdev); 4143 } 4144 4145 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 4146 { 4147 struct net_device *netdev = handle->kinfo.netdev; 4148 4149 if (!netdev) 4150 return; 4151 4152 if (linkup) { 4153 netif_carrier_on(netdev); 4154 netif_tx_wake_all_queues(netdev); 4155 if (netif_msg_link(handle)) 4156 netdev_info(netdev, "link up\n"); 4157 } else { 4158 netif_carrier_off(netdev); 4159 netif_tx_stop_all_queues(netdev); 4160 if (netif_msg_link(handle)) 4161 netdev_info(netdev, "link down\n"); 4162 } 4163 } 4164 4165 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc) 4166 { 4167 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4168 struct net_device *ndev = kinfo->netdev; 4169 4170 if (tc > HNAE3_MAX_TC) 4171 return -EINVAL; 4172 4173 if (!ndev) 4174 return -ENODEV; 4175 4176 return hns3_nic_set_real_num_queue(ndev); 4177 } 4178 4179 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 4180 { 4181 while (ring->next_to_clean != ring->next_to_use) { 4182 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 4183 hns3_free_buffer_detach(ring, ring->next_to_clean); 4184 ring_ptr_move_fw(ring, next_to_clean); 4185 } 4186 } 4187 4188 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 4189 { 4190 struct hns3_desc_cb res_cbs; 4191 int ret; 4192 4193 while (ring->next_to_use != ring->next_to_clean) { 4194 /* When a buffer is not reused, it's memory has been 4195 * freed in hns3_handle_rx_bd or will be freed by 4196 * stack, so we need to replace the buffer here. 4197 */ 4198 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4199 ret = hns3_reserve_buffer_map(ring, &res_cbs); 4200 if (ret) { 4201 u64_stats_update_begin(&ring->syncp); 4202 ring->stats.sw_err_cnt++; 4203 u64_stats_update_end(&ring->syncp); 4204 /* if alloc new buffer fail, exit directly 4205 * and reclear in up flow. 4206 */ 4207 netdev_warn(ring_to_netdev(ring), 4208 "reserve buffer map failed, ret = %d\n", 4209 ret); 4210 return ret; 4211 } 4212 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 4213 } 4214 ring_ptr_move_fw(ring, next_to_use); 4215 } 4216 4217 /* Free the pending skb in rx ring */ 4218 if (ring->skb) { 4219 dev_kfree_skb_any(ring->skb); 4220 ring->skb = NULL; 4221 ring->pending_buf = 0; 4222 } 4223 4224 return 0; 4225 } 4226 4227 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 4228 { 4229 while (ring->next_to_use != ring->next_to_clean) { 4230 /* When a buffer is not reused, it's memory has been 4231 * freed in hns3_handle_rx_bd or will be freed by 4232 * stack, so only need to unmap the buffer here. 4233 */ 4234 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4235 hns3_unmap_buffer(ring, 4236 &ring->desc_cb[ring->next_to_use]); 4237 ring->desc_cb[ring->next_to_use].dma = 0; 4238 } 4239 4240 ring_ptr_move_fw(ring, next_to_use); 4241 } 4242 } 4243 4244 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force) 4245 { 4246 struct net_device *ndev = h->kinfo.netdev; 4247 struct hns3_nic_priv *priv = netdev_priv(ndev); 4248 u32 i; 4249 4250 for (i = 0; i < h->kinfo.num_tqps; i++) { 4251 struct hns3_enet_ring *ring; 4252 4253 ring = &priv->ring[i]; 4254 hns3_clear_tx_ring(ring); 4255 4256 ring = &priv->ring[i + h->kinfo.num_tqps]; 4257 /* Continue to clear other rings even if clearing some 4258 * rings failed. 4259 */ 4260 if (force) 4261 hns3_force_clear_rx_ring(ring); 4262 else 4263 hns3_clear_rx_ring(ring); 4264 } 4265 } 4266 4267 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 4268 { 4269 struct net_device *ndev = h->kinfo.netdev; 4270 struct hns3_nic_priv *priv = netdev_priv(ndev); 4271 struct hns3_enet_ring *rx_ring; 4272 int i, j; 4273 int ret; 4274 4275 for (i = 0; i < h->kinfo.num_tqps; i++) { 4276 ret = h->ae_algo->ops->reset_queue(h, i); 4277 if (ret) 4278 return ret; 4279 4280 hns3_init_ring_hw(&priv->ring[i]); 4281 4282 /* We need to clear tx ring here because self test will 4283 * use the ring and will not run down before up 4284 */ 4285 hns3_clear_tx_ring(&priv->ring[i]); 4286 priv->ring[i].next_to_clean = 0; 4287 priv->ring[i].next_to_use = 0; 4288 4289 rx_ring = &priv->ring[i + h->kinfo.num_tqps]; 4290 hns3_init_ring_hw(rx_ring); 4291 ret = hns3_clear_rx_ring(rx_ring); 4292 if (ret) 4293 return ret; 4294 4295 /* We can not know the hardware head and tail when this 4296 * function is called in reset flow, so we reuse all desc. 4297 */ 4298 for (j = 0; j < rx_ring->desc_num; j++) 4299 hns3_reuse_buffer(rx_ring, j); 4300 4301 rx_ring->next_to_clean = 0; 4302 rx_ring->next_to_use = 0; 4303 } 4304 4305 hns3_init_tx_ring_tc(priv); 4306 4307 return 0; 4308 } 4309 4310 static void hns3_store_coal(struct hns3_nic_priv *priv) 4311 { 4312 /* ethtool only support setting and querying one coal 4313 * configuration for now, so save the vector 0' coal 4314 * configuration here in order to restore it. 4315 */ 4316 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal, 4317 sizeof(struct hns3_enet_coalesce)); 4318 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal, 4319 sizeof(struct hns3_enet_coalesce)); 4320 } 4321 4322 static void hns3_restore_coal(struct hns3_nic_priv *priv) 4323 { 4324 u16 vector_num = priv->vector_num; 4325 int i; 4326 4327 for (i = 0; i < vector_num; i++) { 4328 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal, 4329 sizeof(struct hns3_enet_coalesce)); 4330 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal, 4331 sizeof(struct hns3_enet_coalesce)); 4332 } 4333 } 4334 4335 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 4336 { 4337 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4338 struct net_device *ndev = kinfo->netdev; 4339 struct hns3_nic_priv *priv = netdev_priv(ndev); 4340 4341 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 4342 return 0; 4343 4344 if (!netif_running(ndev)) 4345 return 0; 4346 4347 return hns3_nic_net_stop(ndev); 4348 } 4349 4350 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 4351 { 4352 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4353 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 4354 int ret = 0; 4355 4356 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4357 4358 if (netif_running(kinfo->netdev)) { 4359 ret = hns3_nic_net_open(kinfo->netdev); 4360 if (ret) { 4361 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4362 netdev_err(kinfo->netdev, 4363 "net up fail, ret=%d!\n", ret); 4364 return ret; 4365 } 4366 } 4367 4368 return ret; 4369 } 4370 4371 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 4372 { 4373 struct net_device *netdev = handle->kinfo.netdev; 4374 struct hns3_nic_priv *priv = netdev_priv(netdev); 4375 int ret; 4376 4377 /* Carrier off reporting is important to ethtool even BEFORE open */ 4378 netif_carrier_off(netdev); 4379 4380 ret = hns3_get_ring_config(priv); 4381 if (ret) 4382 return ret; 4383 4384 ret = hns3_nic_alloc_vector_data(priv); 4385 if (ret) 4386 goto err_put_ring; 4387 4388 hns3_restore_coal(priv); 4389 4390 ret = hns3_nic_init_vector_data(priv); 4391 if (ret) 4392 goto err_dealloc_vector; 4393 4394 ret = hns3_init_all_ring(priv); 4395 if (ret) 4396 goto err_uninit_vector; 4397 4398 /* the device can work without cpu rmap, only aRFS needs it */ 4399 ret = hns3_set_rx_cpu_rmap(netdev); 4400 if (ret) 4401 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 4402 4403 ret = hns3_nic_init_irq(priv); 4404 if (ret) { 4405 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 4406 hns3_free_rx_cpu_rmap(netdev); 4407 goto err_init_irq_fail; 4408 } 4409 4410 if (!hns3_is_phys_func(handle->pdev)) 4411 hns3_init_mac_addr(netdev); 4412 4413 ret = hns3_client_start(handle); 4414 if (ret) { 4415 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4416 goto err_client_start_fail; 4417 } 4418 4419 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4420 4421 return ret; 4422 4423 err_client_start_fail: 4424 hns3_free_rx_cpu_rmap(netdev); 4425 hns3_nic_uninit_irq(priv); 4426 err_init_irq_fail: 4427 hns3_uninit_all_ring(priv); 4428 err_uninit_vector: 4429 hns3_nic_uninit_vector_data(priv); 4430 err_dealloc_vector: 4431 hns3_nic_dealloc_vector_data(priv); 4432 err_put_ring: 4433 hns3_put_ring_config(priv); 4434 4435 return ret; 4436 } 4437 4438 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 4439 { 4440 struct net_device *netdev = handle->kinfo.netdev; 4441 struct hns3_nic_priv *priv = netdev_priv(netdev); 4442 int ret; 4443 4444 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4445 netdev_warn(netdev, "already uninitialized\n"); 4446 return 0; 4447 } 4448 4449 hns3_free_rx_cpu_rmap(netdev); 4450 hns3_nic_uninit_irq(priv); 4451 hns3_clear_all_ring(handle, true); 4452 hns3_reset_tx_queue(priv->ae_handle); 4453 4454 hns3_nic_uninit_vector_data(priv); 4455 4456 hns3_store_coal(priv); 4457 4458 hns3_nic_dealloc_vector_data(priv); 4459 4460 ret = hns3_uninit_all_ring(priv); 4461 if (ret) 4462 netdev_err(netdev, "uninit ring error\n"); 4463 4464 hns3_put_ring_config(priv); 4465 4466 return ret; 4467 } 4468 4469 static int hns3_reset_notify(struct hnae3_handle *handle, 4470 enum hnae3_reset_notify_type type) 4471 { 4472 int ret = 0; 4473 4474 switch (type) { 4475 case HNAE3_UP_CLIENT: 4476 ret = hns3_reset_notify_up_enet(handle); 4477 break; 4478 case HNAE3_DOWN_CLIENT: 4479 ret = hns3_reset_notify_down_enet(handle); 4480 break; 4481 case HNAE3_INIT_CLIENT: 4482 ret = hns3_reset_notify_init_enet(handle); 4483 break; 4484 case HNAE3_UNINIT_CLIENT: 4485 ret = hns3_reset_notify_uninit_enet(handle); 4486 break; 4487 default: 4488 break; 4489 } 4490 4491 return ret; 4492 } 4493 4494 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num, 4495 bool rxfh_configured) 4496 { 4497 int ret; 4498 4499 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num, 4500 rxfh_configured); 4501 if (ret) { 4502 dev_err(&handle->pdev->dev, 4503 "Change tqp num(%u) fail.\n", new_tqp_num); 4504 return ret; 4505 } 4506 4507 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT); 4508 if (ret) 4509 return ret; 4510 4511 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT); 4512 if (ret) 4513 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT); 4514 4515 return ret; 4516 } 4517 4518 int hns3_set_channels(struct net_device *netdev, 4519 struct ethtool_channels *ch) 4520 { 4521 struct hnae3_handle *h = hns3_get_handle(netdev); 4522 struct hnae3_knic_private_info *kinfo = &h->kinfo; 4523 bool rxfh_configured = netif_is_rxfh_configured(netdev); 4524 u32 new_tqp_num = ch->combined_count; 4525 u16 org_tqp_num; 4526 int ret; 4527 4528 if (hns3_nic_resetting(netdev)) 4529 return -EBUSY; 4530 4531 if (ch->rx_count || ch->tx_count) 4532 return -EINVAL; 4533 4534 if (new_tqp_num > hns3_get_max_available_channels(h) || 4535 new_tqp_num < 1) { 4536 dev_err(&netdev->dev, 4537 "Change tqps fail, the tqp range is from 1 to %u", 4538 hns3_get_max_available_channels(h)); 4539 return -EINVAL; 4540 } 4541 4542 if (kinfo->rss_size == new_tqp_num) 4543 return 0; 4544 4545 netif_dbg(h, drv, netdev, 4546 "set channels: tqp_num=%u, rxfh=%d\n", 4547 new_tqp_num, rxfh_configured); 4548 4549 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 4550 if (ret) 4551 return ret; 4552 4553 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 4554 if (ret) 4555 return ret; 4556 4557 org_tqp_num = h->kinfo.num_tqps; 4558 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured); 4559 if (ret) { 4560 int ret1; 4561 4562 netdev_warn(netdev, 4563 "Change channels fail, revert to old value\n"); 4564 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured); 4565 if (ret1) { 4566 netdev_err(netdev, 4567 "revert to old channel fail\n"); 4568 return ret1; 4569 } 4570 4571 return ret; 4572 } 4573 4574 return 0; 4575 } 4576 4577 static const struct hns3_hw_error_info hns3_hw_err[] = { 4578 { .type = HNAE3_PPU_POISON_ERROR, 4579 .msg = "PPU poison" }, 4580 { .type = HNAE3_CMDQ_ECC_ERROR, 4581 .msg = "IMP CMDQ error" }, 4582 { .type = HNAE3_IMP_RD_POISON_ERROR, 4583 .msg = "IMP RD poison" }, 4584 }; 4585 4586 static void hns3_process_hw_error(struct hnae3_handle *handle, 4587 enum hnae3_hw_error_type type) 4588 { 4589 int i; 4590 4591 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) { 4592 if (hns3_hw_err[i].type == type) { 4593 dev_err(&handle->pdev->dev, "Detected %s!\n", 4594 hns3_hw_err[i].msg); 4595 break; 4596 } 4597 } 4598 } 4599 4600 static const struct hnae3_client_ops client_ops = { 4601 .init_instance = hns3_client_init, 4602 .uninit_instance = hns3_client_uninit, 4603 .link_status_change = hns3_link_status_change, 4604 .setup_tc = hns3_client_setup_tc, 4605 .reset_notify = hns3_reset_notify, 4606 .process_hw_error = hns3_process_hw_error, 4607 }; 4608 4609 /* hns3_init_module - Driver registration routine 4610 * hns3_init_module is the first routine called when the driver is 4611 * loaded. All it does is register with the PCI subsystem. 4612 */ 4613 static int __init hns3_init_module(void) 4614 { 4615 int ret; 4616 4617 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 4618 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 4619 4620 client.type = HNAE3_CLIENT_KNIC; 4621 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s", 4622 hns3_driver_name); 4623 4624 client.ops = &client_ops; 4625 4626 INIT_LIST_HEAD(&client.node); 4627 4628 hns3_dbg_register_debugfs(hns3_driver_name); 4629 4630 ret = hnae3_register_client(&client); 4631 if (ret) 4632 goto err_reg_client; 4633 4634 ret = pci_register_driver(&hns3_driver); 4635 if (ret) 4636 goto err_reg_driver; 4637 4638 return ret; 4639 4640 err_reg_driver: 4641 hnae3_unregister_client(&client); 4642 err_reg_client: 4643 hns3_dbg_unregister_debugfs(); 4644 return ret; 4645 } 4646 module_init(hns3_init_module); 4647 4648 /* hns3_exit_module - Driver exit cleanup routine 4649 * hns3_exit_module is called just before the driver is removed 4650 * from memory. 4651 */ 4652 static void __exit hns3_exit_module(void) 4653 { 4654 pci_unregister_driver(&hns3_driver); 4655 hnae3_unregister_client(&client); 4656 hns3_dbg_unregister_debugfs(); 4657 } 4658 module_exit(hns3_exit_module); 4659 4660 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 4661 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 4662 MODULE_LICENSE("GPL"); 4663 MODULE_ALIAS("pci:hns-nic"); 4664