1 /* 2 * Copyright (c) 2016~2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #include <linux/dma-mapping.h> 11 #include <linux/etherdevice.h> 12 #include <linux/interrupt.h> 13 #include <linux/if_vlan.h> 14 #include <linux/ip.h> 15 #include <linux/ipv6.h> 16 #include <linux/module.h> 17 #include <linux/pci.h> 18 #include <linux/skbuff.h> 19 #include <linux/sctp.h> 20 #include <linux/vermagic.h> 21 #include <net/gre.h> 22 #include <net/pkt_cls.h> 23 #include <net/vxlan.h> 24 25 #include "hnae3.h" 26 #include "hns3_enet.h" 27 28 static void hns3_clear_all_ring(struct hnae3_handle *h); 29 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h); 30 31 static const char hns3_driver_name[] = "hns3"; 32 const char hns3_driver_version[] = VERMAGIC_STRING; 33 static const char hns3_driver_string[] = 34 "Hisilicon Ethernet Network Driver for Hip08 Family"; 35 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 36 static struct hnae3_client client; 37 38 /* hns3_pci_tbl - PCI Device ID Table 39 * 40 * Last entry must be all 0s 41 * 42 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 43 * Class, Class Mask, private data (not used) } 44 */ 45 static const struct pci_device_id hns3_pci_tbl[] = { 46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 49 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 51 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 52 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 53 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 54 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 55 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 56 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 57 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 58 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 59 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 60 /* required last entry */ 61 {0, } 62 }; 63 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 64 65 static irqreturn_t hns3_irq_handle(int irq, void *dev) 66 { 67 struct hns3_enet_tqp_vector *tqp_vector = dev; 68 69 napi_schedule(&tqp_vector->napi); 70 71 return IRQ_HANDLED; 72 } 73 74 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 75 { 76 struct hns3_enet_tqp_vector *tqp_vectors; 77 unsigned int i; 78 79 for (i = 0; i < priv->vector_num; i++) { 80 tqp_vectors = &priv->tqp_vector[i]; 81 82 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 83 continue; 84 85 /* release the irq resource */ 86 free_irq(tqp_vectors->vector_irq, tqp_vectors); 87 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 88 } 89 } 90 91 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 92 { 93 struct hns3_enet_tqp_vector *tqp_vectors; 94 int txrx_int_idx = 0; 95 int rx_int_idx = 0; 96 int tx_int_idx = 0; 97 unsigned int i; 98 int ret; 99 100 for (i = 0; i < priv->vector_num; i++) { 101 tqp_vectors = &priv->tqp_vector[i]; 102 103 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 104 continue; 105 106 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 107 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 108 "%s-%s-%d", priv->netdev->name, "TxRx", 109 txrx_int_idx++); 110 txrx_int_idx++; 111 } else if (tqp_vectors->rx_group.ring) { 112 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 113 "%s-%s-%d", priv->netdev->name, "Rx", 114 rx_int_idx++); 115 } else if (tqp_vectors->tx_group.ring) { 116 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 117 "%s-%s-%d", priv->netdev->name, "Tx", 118 tx_int_idx++); 119 } else { 120 /* Skip this unused q_vector */ 121 continue; 122 } 123 124 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 125 126 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 127 tqp_vectors->name, 128 tqp_vectors); 129 if (ret) { 130 netdev_err(priv->netdev, "request irq(%d) fail\n", 131 tqp_vectors->vector_irq); 132 return ret; 133 } 134 135 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 136 } 137 138 return 0; 139 } 140 141 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 142 u32 mask_en) 143 { 144 writel(mask_en, tqp_vector->mask_addr); 145 } 146 147 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 148 { 149 napi_enable(&tqp_vector->napi); 150 151 /* enable vector */ 152 hns3_mask_vector_irq(tqp_vector, 1); 153 } 154 155 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 156 { 157 /* disable vector */ 158 hns3_mask_vector_irq(tqp_vector, 0); 159 160 disable_irq(tqp_vector->vector_irq); 161 napi_disable(&tqp_vector->napi); 162 } 163 164 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 165 u32 rl_value) 166 { 167 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 168 169 /* this defines the configuration for RL (Interrupt Rate Limiter). 170 * Rl defines rate of interrupts i.e. number of interrupts-per-second 171 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 172 */ 173 174 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable && 175 !tqp_vector->rx_group.coal.gl_adapt_enable) 176 /* According to the hardware, the range of rl_reg is 177 * 0-59 and the unit is 4. 178 */ 179 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 180 181 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 182 } 183 184 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 185 u32 gl_value) 186 { 187 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value); 188 189 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 190 } 191 192 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 193 u32 gl_value) 194 { 195 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value); 196 197 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 198 } 199 200 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector, 201 struct hns3_nic_priv *priv) 202 { 203 struct hnae3_handle *h = priv->ae_handle; 204 205 /* initialize the configuration for interrupt coalescing. 206 * 1. GL (Interrupt Gap Limiter) 207 * 2. RL (Interrupt Rate Limiter) 208 */ 209 210 /* Default: enable interrupt coalescing self-adaptive and GL */ 211 tqp_vector->tx_group.coal.gl_adapt_enable = 1; 212 tqp_vector->rx_group.coal.gl_adapt_enable = 1; 213 214 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K; 215 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K; 216 217 /* Default: disable RL */ 218 h->kinfo.int_rl_setting = 0; 219 220 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START; 221 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW; 222 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW; 223 } 224 225 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 226 struct hns3_nic_priv *priv) 227 { 228 struct hnae3_handle *h = priv->ae_handle; 229 230 hns3_set_vector_coalesce_tx_gl(tqp_vector, 231 tqp_vector->tx_group.coal.int_gl); 232 hns3_set_vector_coalesce_rx_gl(tqp_vector, 233 tqp_vector->rx_group.coal.int_gl); 234 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 235 } 236 237 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 238 { 239 struct hnae3_handle *h = hns3_get_handle(netdev); 240 struct hnae3_knic_private_info *kinfo = &h->kinfo; 241 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc; 242 int ret; 243 244 ret = netif_set_real_num_tx_queues(netdev, queue_size); 245 if (ret) { 246 netdev_err(netdev, 247 "netif_set_real_num_tx_queues fail, ret=%d!\n", 248 ret); 249 return ret; 250 } 251 252 ret = netif_set_real_num_rx_queues(netdev, queue_size); 253 if (ret) { 254 netdev_err(netdev, 255 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 256 return ret; 257 } 258 259 return 0; 260 } 261 262 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 263 { 264 u16 free_tqps, max_rss_size, max_tqps; 265 266 h->ae_algo->ops->get_tqps_and_rss_info(h, &free_tqps, &max_rss_size); 267 max_tqps = h->kinfo.num_tc * max_rss_size; 268 269 return min_t(u16, max_tqps, (free_tqps + h->kinfo.num_tqps)); 270 } 271 272 static int hns3_nic_net_up(struct net_device *netdev) 273 { 274 struct hns3_nic_priv *priv = netdev_priv(netdev); 275 struct hnae3_handle *h = priv->ae_handle; 276 int i, j; 277 int ret; 278 279 ret = hns3_nic_reset_all_ring(h); 280 if (ret) 281 return ret; 282 283 /* get irq resource for all vectors */ 284 ret = hns3_nic_init_irq(priv); 285 if (ret) { 286 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret); 287 return ret; 288 } 289 290 /* enable the vectors */ 291 for (i = 0; i < priv->vector_num; i++) 292 hns3_vector_enable(&priv->tqp_vector[i]); 293 294 /* start the ae_dev */ 295 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 296 if (ret) 297 goto out_start_err; 298 299 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 300 301 return 0; 302 303 out_start_err: 304 for (j = i - 1; j >= 0; j--) 305 hns3_vector_disable(&priv->tqp_vector[j]); 306 307 hns3_nic_uninit_irq(priv); 308 309 return ret; 310 } 311 312 static int hns3_nic_net_open(struct net_device *netdev) 313 { 314 struct hns3_nic_priv *priv = netdev_priv(netdev); 315 int ret; 316 317 netif_carrier_off(netdev); 318 319 ret = hns3_nic_set_real_num_queue(netdev); 320 if (ret) 321 return ret; 322 323 ret = hns3_nic_net_up(netdev); 324 if (ret) { 325 netdev_err(netdev, 326 "hns net up fail, ret=%d!\n", ret); 327 return ret; 328 } 329 330 priv->ae_handle->last_reset_time = jiffies; 331 return 0; 332 } 333 334 static void hns3_nic_net_down(struct net_device *netdev) 335 { 336 struct hns3_nic_priv *priv = netdev_priv(netdev); 337 const struct hnae3_ae_ops *ops; 338 int i; 339 340 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 341 return; 342 343 /* disable vectors */ 344 for (i = 0; i < priv->vector_num; i++) 345 hns3_vector_disable(&priv->tqp_vector[i]); 346 347 /* stop ae_dev */ 348 ops = priv->ae_handle->ae_algo->ops; 349 if (ops->stop) 350 ops->stop(priv->ae_handle); 351 352 /* free irq resources */ 353 hns3_nic_uninit_irq(priv); 354 355 hns3_clear_all_ring(priv->ae_handle); 356 } 357 358 static int hns3_nic_net_stop(struct net_device *netdev) 359 { 360 netif_tx_stop_all_queues(netdev); 361 netif_carrier_off(netdev); 362 363 hns3_nic_net_down(netdev); 364 365 return 0; 366 } 367 368 static int hns3_nic_uc_sync(struct net_device *netdev, 369 const unsigned char *addr) 370 { 371 struct hnae3_handle *h = hns3_get_handle(netdev); 372 373 if (h->ae_algo->ops->add_uc_addr) 374 return h->ae_algo->ops->add_uc_addr(h, addr); 375 376 return 0; 377 } 378 379 static int hns3_nic_uc_unsync(struct net_device *netdev, 380 const unsigned char *addr) 381 { 382 struct hnae3_handle *h = hns3_get_handle(netdev); 383 384 if (h->ae_algo->ops->rm_uc_addr) 385 return h->ae_algo->ops->rm_uc_addr(h, addr); 386 387 return 0; 388 } 389 390 static int hns3_nic_mc_sync(struct net_device *netdev, 391 const unsigned char *addr) 392 { 393 struct hnae3_handle *h = hns3_get_handle(netdev); 394 395 if (h->ae_algo->ops->add_mc_addr) 396 return h->ae_algo->ops->add_mc_addr(h, addr); 397 398 return 0; 399 } 400 401 static int hns3_nic_mc_unsync(struct net_device *netdev, 402 const unsigned char *addr) 403 { 404 struct hnae3_handle *h = hns3_get_handle(netdev); 405 406 if (h->ae_algo->ops->rm_mc_addr) 407 return h->ae_algo->ops->rm_mc_addr(h, addr); 408 409 return 0; 410 } 411 412 static void hns3_nic_set_rx_mode(struct net_device *netdev) 413 { 414 struct hnae3_handle *h = hns3_get_handle(netdev); 415 416 if (h->ae_algo->ops->set_promisc_mode) { 417 if (netdev->flags & IFF_PROMISC) 418 h->ae_algo->ops->set_promisc_mode(h, true, true); 419 else if (netdev->flags & IFF_ALLMULTI) 420 h->ae_algo->ops->set_promisc_mode(h, false, true); 421 else 422 h->ae_algo->ops->set_promisc_mode(h, false, false); 423 } 424 if (__dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync)) 425 netdev_err(netdev, "sync uc address fail\n"); 426 if (netdev->flags & IFF_MULTICAST) { 427 if (__dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync)) 428 netdev_err(netdev, "sync mc address fail\n"); 429 430 if (h->ae_algo->ops->update_mta_status) 431 h->ae_algo->ops->update_mta_status(h); 432 } 433 } 434 435 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen, 436 u16 *mss, u32 *type_cs_vlan_tso) 437 { 438 u32 l4_offset, hdr_len; 439 union l3_hdr_info l3; 440 union l4_hdr_info l4; 441 u32 l4_paylen; 442 int ret; 443 444 if (!skb_is_gso(skb)) 445 return 0; 446 447 ret = skb_cow_head(skb, 0); 448 if (ret) 449 return ret; 450 451 l3.hdr = skb_network_header(skb); 452 l4.hdr = skb_transport_header(skb); 453 454 /* Software should clear the IPv4's checksum field when tso is 455 * needed. 456 */ 457 if (l3.v4->version == 4) 458 l3.v4->check = 0; 459 460 /* tunnel packet.*/ 461 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 462 SKB_GSO_GRE_CSUM | 463 SKB_GSO_UDP_TUNNEL | 464 SKB_GSO_UDP_TUNNEL_CSUM)) { 465 if ((!(skb_shinfo(skb)->gso_type & 466 SKB_GSO_PARTIAL)) && 467 (skb_shinfo(skb)->gso_type & 468 SKB_GSO_UDP_TUNNEL_CSUM)) { 469 /* Software should clear the udp's checksum 470 * field when tso is needed. 471 */ 472 l4.udp->check = 0; 473 } 474 /* reset l3&l4 pointers from outer to inner headers */ 475 l3.hdr = skb_inner_network_header(skb); 476 l4.hdr = skb_inner_transport_header(skb); 477 478 /* Software should clear the IPv4's checksum field when 479 * tso is needed. 480 */ 481 if (l3.v4->version == 4) 482 l3.v4->check = 0; 483 } 484 485 /* normal or tunnel packet*/ 486 l4_offset = l4.hdr - skb->data; 487 hdr_len = (l4.tcp->doff * 4) + l4_offset; 488 489 /* remove payload length from inner pseudo checksum when tso*/ 490 l4_paylen = skb->len - l4_offset; 491 csum_replace_by_diff(&l4.tcp->check, 492 (__force __wsum)htonl(l4_paylen)); 493 494 /* find the txbd field values */ 495 *paylen = skb->len - hdr_len; 496 hnae3_set_bit(*type_cs_vlan_tso, 497 HNS3_TXD_TSO_B, 1); 498 499 /* get MSS for TSO */ 500 *mss = skb_shinfo(skb)->gso_size; 501 502 return 0; 503 } 504 505 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 506 u8 *il4_proto) 507 { 508 union { 509 struct iphdr *v4; 510 struct ipv6hdr *v6; 511 unsigned char *hdr; 512 } l3; 513 unsigned char *l4_hdr; 514 unsigned char *exthdr; 515 u8 l4_proto_tmp; 516 __be16 frag_off; 517 518 /* find outer header point */ 519 l3.hdr = skb_network_header(skb); 520 l4_hdr = skb_transport_header(skb); 521 522 if (skb->protocol == htons(ETH_P_IPV6)) { 523 exthdr = l3.hdr + sizeof(*l3.v6); 524 l4_proto_tmp = l3.v6->nexthdr; 525 if (l4_hdr != exthdr) 526 ipv6_skip_exthdr(skb, exthdr - skb->data, 527 &l4_proto_tmp, &frag_off); 528 } else if (skb->protocol == htons(ETH_P_IP)) { 529 l4_proto_tmp = l3.v4->protocol; 530 } else { 531 return -EINVAL; 532 } 533 534 *ol4_proto = l4_proto_tmp; 535 536 /* tunnel packet */ 537 if (!skb->encapsulation) { 538 *il4_proto = 0; 539 return 0; 540 } 541 542 /* find inner header point */ 543 l3.hdr = skb_inner_network_header(skb); 544 l4_hdr = skb_inner_transport_header(skb); 545 546 if (l3.v6->version == 6) { 547 exthdr = l3.hdr + sizeof(*l3.v6); 548 l4_proto_tmp = l3.v6->nexthdr; 549 if (l4_hdr != exthdr) 550 ipv6_skip_exthdr(skb, exthdr - skb->data, 551 &l4_proto_tmp, &frag_off); 552 } else if (l3.v4->version == 4) { 553 l4_proto_tmp = l3.v4->protocol; 554 } 555 556 *il4_proto = l4_proto_tmp; 557 558 return 0; 559 } 560 561 static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto, 562 u8 il4_proto, u32 *type_cs_vlan_tso, 563 u32 *ol_type_vlan_len_msec) 564 { 565 union { 566 struct iphdr *v4; 567 struct ipv6hdr *v6; 568 unsigned char *hdr; 569 } l3; 570 union { 571 struct tcphdr *tcp; 572 struct udphdr *udp; 573 struct gre_base_hdr *gre; 574 unsigned char *hdr; 575 } l4; 576 unsigned char *l2_hdr; 577 u8 l4_proto = ol4_proto; 578 u32 ol2_len; 579 u32 ol3_len; 580 u32 ol4_len; 581 u32 l2_len; 582 u32 l3_len; 583 584 l3.hdr = skb_network_header(skb); 585 l4.hdr = skb_transport_header(skb); 586 587 /* compute L2 header size for normal packet, defined in 2 Bytes */ 588 l2_len = l3.hdr - skb->data; 589 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M, 590 HNS3_TXD_L2LEN_S, l2_len >> 1); 591 592 /* tunnel packet*/ 593 if (skb->encapsulation) { 594 /* compute OL2 header size, defined in 2 Bytes */ 595 ol2_len = l2_len; 596 hnae3_set_field(*ol_type_vlan_len_msec, 597 HNS3_TXD_L2LEN_M, 598 HNS3_TXD_L2LEN_S, ol2_len >> 1); 599 600 /* compute OL3 header size, defined in 4 Bytes */ 601 ol3_len = l4.hdr - l3.hdr; 602 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M, 603 HNS3_TXD_L3LEN_S, ol3_len >> 2); 604 605 /* MAC in UDP, MAC in GRE (0x6558)*/ 606 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) { 607 /* switch MAC header ptr from outer to inner header.*/ 608 l2_hdr = skb_inner_mac_header(skb); 609 610 /* compute OL4 header size, defined in 4 Bytes. */ 611 ol4_len = l2_hdr - l4.hdr; 612 hnae3_set_field(*ol_type_vlan_len_msec, 613 HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S, 614 ol4_len >> 2); 615 616 /* switch IP header ptr from outer to inner header */ 617 l3.hdr = skb_inner_network_header(skb); 618 619 /* compute inner l2 header size, defined in 2 Bytes. */ 620 l2_len = l3.hdr - l2_hdr; 621 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M, 622 HNS3_TXD_L2LEN_S, l2_len >> 1); 623 } else { 624 /* skb packet types not supported by hardware, 625 * txbd len fild doesn't be filled. 626 */ 627 return; 628 } 629 630 /* switch L4 header pointer from outer to inner */ 631 l4.hdr = skb_inner_transport_header(skb); 632 633 l4_proto = il4_proto; 634 } 635 636 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 637 l3_len = l4.hdr - l3.hdr; 638 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M, 639 HNS3_TXD_L3LEN_S, l3_len >> 2); 640 641 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 642 switch (l4_proto) { 643 case IPPROTO_TCP: 644 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 645 HNS3_TXD_L4LEN_S, l4.tcp->doff); 646 break; 647 case IPPROTO_SCTP: 648 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 649 HNS3_TXD_L4LEN_S, 650 (sizeof(struct sctphdr) >> 2)); 651 break; 652 case IPPROTO_UDP: 653 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 654 HNS3_TXD_L4LEN_S, 655 (sizeof(struct udphdr) >> 2)); 656 break; 657 default: 658 /* skb packet types not supported by hardware, 659 * txbd len fild doesn't be filled. 660 */ 661 return; 662 } 663 } 664 665 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 666 * and it is udp packet, which has a dest port as the IANA assigned. 667 * the hardware is expected to do the checksum offload, but the 668 * hardware will not do the checksum offload when udp dest port is 669 * 4789. 670 */ 671 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 672 { 673 #define IANA_VXLAN_PORT 4789 674 union { 675 struct tcphdr *tcp; 676 struct udphdr *udp; 677 struct gre_base_hdr *gre; 678 unsigned char *hdr; 679 } l4; 680 681 l4.hdr = skb_transport_header(skb); 682 683 if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT))) 684 return false; 685 686 skb_checksum_help(skb); 687 688 return true; 689 } 690 691 static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto, 692 u8 il4_proto, u32 *type_cs_vlan_tso, 693 u32 *ol_type_vlan_len_msec) 694 { 695 union { 696 struct iphdr *v4; 697 struct ipv6hdr *v6; 698 unsigned char *hdr; 699 } l3; 700 u32 l4_proto = ol4_proto; 701 702 l3.hdr = skb_network_header(skb); 703 704 /* define OL3 type and tunnel type(OL4).*/ 705 if (skb->encapsulation) { 706 /* define outer network header type.*/ 707 if (skb->protocol == htons(ETH_P_IP)) { 708 if (skb_is_gso(skb)) 709 hnae3_set_field(*ol_type_vlan_len_msec, 710 HNS3_TXD_OL3T_M, 711 HNS3_TXD_OL3T_S, 712 HNS3_OL3T_IPV4_CSUM); 713 else 714 hnae3_set_field(*ol_type_vlan_len_msec, 715 HNS3_TXD_OL3T_M, 716 HNS3_TXD_OL3T_S, 717 HNS3_OL3T_IPV4_NO_CSUM); 718 719 } else if (skb->protocol == htons(ETH_P_IPV6)) { 720 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M, 721 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6); 722 } 723 724 /* define tunnel type(OL4).*/ 725 switch (l4_proto) { 726 case IPPROTO_UDP: 727 hnae3_set_field(*ol_type_vlan_len_msec, 728 HNS3_TXD_TUNTYPE_M, 729 HNS3_TXD_TUNTYPE_S, 730 HNS3_TUN_MAC_IN_UDP); 731 break; 732 case IPPROTO_GRE: 733 hnae3_set_field(*ol_type_vlan_len_msec, 734 HNS3_TXD_TUNTYPE_M, 735 HNS3_TXD_TUNTYPE_S, 736 HNS3_TUN_NVGRE); 737 break; 738 default: 739 /* drop the skb tunnel packet if hardware don't support, 740 * because hardware can't calculate csum when TSO. 741 */ 742 if (skb_is_gso(skb)) 743 return -EDOM; 744 745 /* the stack computes the IP header already, 746 * driver calculate l4 checksum when not TSO. 747 */ 748 skb_checksum_help(skb); 749 return 0; 750 } 751 752 l3.hdr = skb_inner_network_header(skb); 753 l4_proto = il4_proto; 754 } 755 756 if (l3.v4->version == 4) { 757 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M, 758 HNS3_TXD_L3T_S, HNS3_L3T_IPV4); 759 760 /* the stack computes the IP header already, the only time we 761 * need the hardware to recompute it is in the case of TSO. 762 */ 763 if (skb_is_gso(skb)) 764 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 765 766 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 767 } else if (l3.v6->version == 6) { 768 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M, 769 HNS3_TXD_L3T_S, HNS3_L3T_IPV6); 770 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 771 } 772 773 switch (l4_proto) { 774 case IPPROTO_TCP: 775 hnae3_set_field(*type_cs_vlan_tso, 776 HNS3_TXD_L4T_M, 777 HNS3_TXD_L4T_S, 778 HNS3_L4T_TCP); 779 break; 780 case IPPROTO_UDP: 781 if (hns3_tunnel_csum_bug(skb)) 782 break; 783 784 hnae3_set_field(*type_cs_vlan_tso, 785 HNS3_TXD_L4T_M, 786 HNS3_TXD_L4T_S, 787 HNS3_L4T_UDP); 788 break; 789 case IPPROTO_SCTP: 790 hnae3_set_field(*type_cs_vlan_tso, 791 HNS3_TXD_L4T_M, 792 HNS3_TXD_L4T_S, 793 HNS3_L4T_SCTP); 794 break; 795 default: 796 /* drop the skb tunnel packet if hardware don't support, 797 * because hardware can't calculate csum when TSO. 798 */ 799 if (skb_is_gso(skb)) 800 return -EDOM; 801 802 /* the stack computes the IP header already, 803 * driver calculate l4 checksum when not TSO. 804 */ 805 skb_checksum_help(skb); 806 return 0; 807 } 808 809 return 0; 810 } 811 812 static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end) 813 { 814 /* Config bd buffer end */ 815 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M, 816 HNS3_TXD_BDTYPE_S, 0); 817 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end); 818 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1); 819 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0); 820 } 821 822 static int hns3_fill_desc_vtags(struct sk_buff *skb, 823 struct hns3_enet_ring *tx_ring, 824 u32 *inner_vlan_flag, 825 u32 *out_vlan_flag, 826 u16 *inner_vtag, 827 u16 *out_vtag) 828 { 829 #define HNS3_TX_VLAN_PRIO_SHIFT 13 830 831 if (skb->protocol == htons(ETH_P_8021Q) && 832 !(tx_ring->tqp->handle->kinfo.netdev->features & 833 NETIF_F_HW_VLAN_CTAG_TX)) { 834 /* When HW VLAN acceleration is turned off, and the stack 835 * sets the protocol to 802.1q, the driver just need to 836 * set the protocol to the encapsulated ethertype. 837 */ 838 skb->protocol = vlan_get_protocol(skb); 839 return 0; 840 } 841 842 if (skb_vlan_tag_present(skb)) { 843 u16 vlan_tag; 844 845 vlan_tag = skb_vlan_tag_get(skb); 846 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT; 847 848 /* Based on hw strategy, use out_vtag in two layer tag case, 849 * and use inner_vtag in one tag case. 850 */ 851 if (skb->protocol == htons(ETH_P_8021Q)) { 852 hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1); 853 *out_vtag = vlan_tag; 854 } else { 855 hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1); 856 *inner_vtag = vlan_tag; 857 } 858 } else if (skb->protocol == htons(ETH_P_8021Q)) { 859 struct vlan_ethhdr *vhdr; 860 int rc; 861 862 rc = skb_cow_head(skb, 0); 863 if (rc < 0) 864 return rc; 865 vhdr = (struct vlan_ethhdr *)skb->data; 866 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7) 867 << HNS3_TX_VLAN_PRIO_SHIFT); 868 } 869 870 skb->protocol = vlan_get_protocol(skb); 871 return 0; 872 } 873 874 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 875 int size, dma_addr_t dma, int frag_end, 876 enum hns_desc_type type) 877 { 878 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 879 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 880 u32 ol_type_vlan_len_msec = 0; 881 u16 bdtp_fe_sc_vld_ra_ri = 0; 882 u32 type_cs_vlan_tso = 0; 883 struct sk_buff *skb; 884 u16 inner_vtag = 0; 885 u16 out_vtag = 0; 886 u32 paylen = 0; 887 u16 mss = 0; 888 u8 ol4_proto; 889 u8 il4_proto; 890 int ret; 891 892 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */ 893 desc_cb->priv = priv; 894 desc_cb->length = size; 895 desc_cb->dma = dma; 896 desc_cb->type = type; 897 898 /* now, fill the descriptor */ 899 desc->addr = cpu_to_le64(dma); 900 desc->tx.send_size = cpu_to_le16((u16)size); 901 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, frag_end); 902 desc->tx.bdtp_fe_sc_vld_ra_ri = cpu_to_le16(bdtp_fe_sc_vld_ra_ri); 903 904 if (type == DESC_TYPE_SKB) { 905 skb = (struct sk_buff *)priv; 906 paylen = skb->len; 907 908 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso, 909 &ol_type_vlan_len_msec, 910 &inner_vtag, &out_vtag); 911 if (unlikely(ret)) 912 return ret; 913 914 if (skb->ip_summed == CHECKSUM_PARTIAL) { 915 skb_reset_mac_len(skb); 916 917 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 918 if (ret) 919 return ret; 920 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto, 921 &type_cs_vlan_tso, 922 &ol_type_vlan_len_msec); 923 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto, 924 &type_cs_vlan_tso, 925 &ol_type_vlan_len_msec); 926 if (ret) 927 return ret; 928 929 ret = hns3_set_tso(skb, &paylen, &mss, 930 &type_cs_vlan_tso); 931 if (ret) 932 return ret; 933 } 934 935 /* Set txbd */ 936 desc->tx.ol_type_vlan_len_msec = 937 cpu_to_le32(ol_type_vlan_len_msec); 938 desc->tx.type_cs_vlan_tso_len = 939 cpu_to_le32(type_cs_vlan_tso); 940 desc->tx.paylen = cpu_to_le32(paylen); 941 desc->tx.mss = cpu_to_le16(mss); 942 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 943 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 944 } 945 946 /* move ring pointer to next.*/ 947 ring_ptr_move_fw(ring, next_to_use); 948 949 return 0; 950 } 951 952 static int hns3_fill_desc_tso(struct hns3_enet_ring *ring, void *priv, 953 int size, dma_addr_t dma, int frag_end, 954 enum hns_desc_type type) 955 { 956 unsigned int frag_buf_num; 957 unsigned int k; 958 int sizeoflast; 959 int ret; 960 961 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 962 sizeoflast = size % HNS3_MAX_BD_SIZE; 963 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 964 965 /* When the frag size is bigger than hardware, split this frag */ 966 for (k = 0; k < frag_buf_num; k++) { 967 ret = hns3_fill_desc(ring, priv, 968 (k == frag_buf_num - 1) ? 969 sizeoflast : HNS3_MAX_BD_SIZE, 970 dma + HNS3_MAX_BD_SIZE * k, 971 frag_end && (k == frag_buf_num - 1) ? 1 : 0, 972 (type == DESC_TYPE_SKB && !k) ? 973 DESC_TYPE_SKB : DESC_TYPE_PAGE); 974 if (ret) 975 return ret; 976 } 977 978 return 0; 979 } 980 981 static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum, 982 struct hns3_enet_ring *ring) 983 { 984 struct sk_buff *skb = *out_skb; 985 struct skb_frag_struct *frag; 986 int bdnum_for_frag; 987 int frag_num; 988 int buf_num; 989 int size; 990 int i; 991 992 size = skb_headlen(skb); 993 buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 994 995 frag_num = skb_shinfo(skb)->nr_frags; 996 for (i = 0; i < frag_num; i++) { 997 frag = &skb_shinfo(skb)->frags[i]; 998 size = skb_frag_size(frag); 999 bdnum_for_frag = 1000 (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1001 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG) 1002 return -ENOMEM; 1003 1004 buf_num += bdnum_for_frag; 1005 } 1006 1007 if (buf_num > ring_space(ring)) 1008 return -EBUSY; 1009 1010 *bnum = buf_num; 1011 return 0; 1012 } 1013 1014 static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum, 1015 struct hns3_enet_ring *ring) 1016 { 1017 struct sk_buff *skb = *out_skb; 1018 int buf_num; 1019 1020 /* No. of segments (plus a header) */ 1021 buf_num = skb_shinfo(skb)->nr_frags + 1; 1022 1023 if (buf_num > ring_space(ring)) 1024 return -EBUSY; 1025 1026 *bnum = buf_num; 1027 1028 return 0; 1029 } 1030 1031 static void hns_nic_dma_unmap(struct hns3_enet_ring *ring, int next_to_use_orig) 1032 { 1033 struct device *dev = ring_to_dev(ring); 1034 unsigned int i; 1035 1036 for (i = 0; i < ring->desc_num; i++) { 1037 /* check if this is where we started */ 1038 if (ring->next_to_use == next_to_use_orig) 1039 break; 1040 1041 /* unmap the descriptor dma address */ 1042 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB) 1043 dma_unmap_single(dev, 1044 ring->desc_cb[ring->next_to_use].dma, 1045 ring->desc_cb[ring->next_to_use].length, 1046 DMA_TO_DEVICE); 1047 else 1048 dma_unmap_page(dev, 1049 ring->desc_cb[ring->next_to_use].dma, 1050 ring->desc_cb[ring->next_to_use].length, 1051 DMA_TO_DEVICE); 1052 1053 /* rollback one */ 1054 ring_ptr_move_bw(ring, next_to_use); 1055 } 1056 } 1057 1058 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1059 { 1060 struct hns3_nic_priv *priv = netdev_priv(netdev); 1061 struct hns3_nic_ring_data *ring_data = 1062 &tx_ring_data(priv, skb->queue_mapping); 1063 struct hns3_enet_ring *ring = ring_data->ring; 1064 struct device *dev = priv->dev; 1065 struct netdev_queue *dev_queue; 1066 struct skb_frag_struct *frag; 1067 int next_to_use_head; 1068 int next_to_use_frag; 1069 dma_addr_t dma; 1070 int buf_num; 1071 int seg_num; 1072 int size; 1073 int ret; 1074 int i; 1075 1076 /* Prefetch the data used later */ 1077 prefetch(skb->data); 1078 1079 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) { 1080 case -EBUSY: 1081 u64_stats_update_begin(&ring->syncp); 1082 ring->stats.tx_busy++; 1083 u64_stats_update_end(&ring->syncp); 1084 1085 goto out_net_tx_busy; 1086 case -ENOMEM: 1087 u64_stats_update_begin(&ring->syncp); 1088 ring->stats.sw_err_cnt++; 1089 u64_stats_update_end(&ring->syncp); 1090 netdev_err(netdev, "no memory to xmit!\n"); 1091 1092 goto out_err_tx_ok; 1093 default: 1094 break; 1095 } 1096 1097 /* No. of segments (plus a header) */ 1098 seg_num = skb_shinfo(skb)->nr_frags + 1; 1099 /* Fill the first part */ 1100 size = skb_headlen(skb); 1101 1102 next_to_use_head = ring->next_to_use; 1103 1104 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1105 if (dma_mapping_error(dev, dma)) { 1106 netdev_err(netdev, "TX head DMA map failed\n"); 1107 ring->stats.sw_err_cnt++; 1108 goto out_err_tx_ok; 1109 } 1110 1111 ret = priv->ops.fill_desc(ring, skb, size, dma, seg_num == 1 ? 1 : 0, 1112 DESC_TYPE_SKB); 1113 if (ret) 1114 goto head_dma_map_err; 1115 1116 next_to_use_frag = ring->next_to_use; 1117 /* Fill the fragments */ 1118 for (i = 1; i < seg_num; i++) { 1119 frag = &skb_shinfo(skb)->frags[i - 1]; 1120 size = skb_frag_size(frag); 1121 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1122 if (dma_mapping_error(dev, dma)) { 1123 netdev_err(netdev, "TX frag(%d) DMA map failed\n", i); 1124 ring->stats.sw_err_cnt++; 1125 goto frag_dma_map_err; 1126 } 1127 ret = priv->ops.fill_desc(ring, skb_frag_page(frag), size, dma, 1128 seg_num - 1 == i ? 1 : 0, 1129 DESC_TYPE_PAGE); 1130 1131 if (ret) 1132 goto frag_dma_map_err; 1133 } 1134 1135 /* Complete translate all packets */ 1136 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index); 1137 netdev_tx_sent_queue(dev_queue, skb->len); 1138 1139 wmb(); /* Commit all data before submit */ 1140 1141 hnae3_queue_xmit(ring->tqp, buf_num); 1142 1143 return NETDEV_TX_OK; 1144 1145 frag_dma_map_err: 1146 hns_nic_dma_unmap(ring, next_to_use_frag); 1147 1148 head_dma_map_err: 1149 hns_nic_dma_unmap(ring, next_to_use_head); 1150 1151 out_err_tx_ok: 1152 dev_kfree_skb_any(skb); 1153 return NETDEV_TX_OK; 1154 1155 out_net_tx_busy: 1156 netif_stop_subqueue(netdev, ring_data->queue_index); 1157 smp_mb(); /* Commit all data before submit */ 1158 1159 return NETDEV_TX_BUSY; 1160 } 1161 1162 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1163 { 1164 struct hnae3_handle *h = hns3_get_handle(netdev); 1165 struct sockaddr *mac_addr = p; 1166 int ret; 1167 1168 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1169 return -EADDRNOTAVAIL; 1170 1171 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1172 netdev_info(netdev, "already using mac address %pM\n", 1173 mac_addr->sa_data); 1174 return 0; 1175 } 1176 1177 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1178 if (ret) { 1179 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1180 return ret; 1181 } 1182 1183 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1184 1185 return 0; 1186 } 1187 1188 static int hns3_nic_set_features(struct net_device *netdev, 1189 netdev_features_t features) 1190 { 1191 netdev_features_t changed = netdev->features ^ features; 1192 struct hns3_nic_priv *priv = netdev_priv(netdev); 1193 struct hnae3_handle *h = priv->ae_handle; 1194 int ret; 1195 1196 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) { 1197 if (features & (NETIF_F_TSO | NETIF_F_TSO6)) { 1198 priv->ops.fill_desc = hns3_fill_desc_tso; 1199 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 1200 } else { 1201 priv->ops.fill_desc = hns3_fill_desc; 1202 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 1203 } 1204 } 1205 1206 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 1207 h->ae_algo->ops->enable_vlan_filter) { 1208 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1209 h->ae_algo->ops->enable_vlan_filter(h, true); 1210 else 1211 h->ae_algo->ops->enable_vlan_filter(h, false); 1212 } 1213 1214 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1215 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1216 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1217 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true); 1218 else 1219 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false); 1220 1221 if (ret) 1222 return ret; 1223 } 1224 1225 netdev->features = features; 1226 return 0; 1227 } 1228 1229 static void hns3_nic_get_stats64(struct net_device *netdev, 1230 struct rtnl_link_stats64 *stats) 1231 { 1232 struct hns3_nic_priv *priv = netdev_priv(netdev); 1233 int queue_num = priv->ae_handle->kinfo.num_tqps; 1234 struct hnae3_handle *handle = priv->ae_handle; 1235 struct hns3_enet_ring *ring; 1236 unsigned int start; 1237 unsigned int idx; 1238 u64 tx_bytes = 0; 1239 u64 rx_bytes = 0; 1240 u64 tx_pkts = 0; 1241 u64 rx_pkts = 0; 1242 u64 tx_drop = 0; 1243 u64 rx_drop = 0; 1244 1245 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1246 return; 1247 1248 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1249 1250 for (idx = 0; idx < queue_num; idx++) { 1251 /* fetch the tx stats */ 1252 ring = priv->ring_data[idx].ring; 1253 do { 1254 start = u64_stats_fetch_begin_irq(&ring->syncp); 1255 tx_bytes += ring->stats.tx_bytes; 1256 tx_pkts += ring->stats.tx_pkts; 1257 tx_drop += ring->stats.tx_busy; 1258 tx_drop += ring->stats.sw_err_cnt; 1259 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1260 1261 /* fetch the rx stats */ 1262 ring = priv->ring_data[idx + queue_num].ring; 1263 do { 1264 start = u64_stats_fetch_begin_irq(&ring->syncp); 1265 rx_bytes += ring->stats.rx_bytes; 1266 rx_pkts += ring->stats.rx_pkts; 1267 rx_drop += ring->stats.non_vld_descs; 1268 rx_drop += ring->stats.err_pkt_len; 1269 rx_drop += ring->stats.l2_err; 1270 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1271 } 1272 1273 stats->tx_bytes = tx_bytes; 1274 stats->tx_packets = tx_pkts; 1275 stats->rx_bytes = rx_bytes; 1276 stats->rx_packets = rx_pkts; 1277 1278 stats->rx_errors = netdev->stats.rx_errors; 1279 stats->multicast = netdev->stats.multicast; 1280 stats->rx_length_errors = netdev->stats.rx_length_errors; 1281 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 1282 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1283 1284 stats->tx_errors = netdev->stats.tx_errors; 1285 stats->rx_dropped = rx_drop + netdev->stats.rx_dropped; 1286 stats->tx_dropped = tx_drop + netdev->stats.tx_dropped; 1287 stats->collisions = netdev->stats.collisions; 1288 stats->rx_over_errors = netdev->stats.rx_over_errors; 1289 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1290 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1291 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1292 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1293 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1294 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1295 stats->tx_window_errors = netdev->stats.tx_window_errors; 1296 stats->rx_compressed = netdev->stats.rx_compressed; 1297 stats->tx_compressed = netdev->stats.tx_compressed; 1298 } 1299 1300 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1301 { 1302 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1303 struct hnae3_handle *h = hns3_get_handle(netdev); 1304 struct hnae3_knic_private_info *kinfo = &h->kinfo; 1305 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map; 1306 u8 tc = mqprio_qopt->qopt.num_tc; 1307 u16 mode = mqprio_qopt->mode; 1308 u8 hw = mqprio_qopt->qopt.hw; 1309 bool if_running; 1310 unsigned int i; 1311 int ret; 1312 1313 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1314 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1315 return -EOPNOTSUPP; 1316 1317 if (tc > HNAE3_MAX_TC) 1318 return -EINVAL; 1319 1320 if (!netdev) 1321 return -EINVAL; 1322 1323 if_running = netif_running(netdev); 1324 if (if_running) { 1325 hns3_nic_net_stop(netdev); 1326 msleep(100); 1327 } 1328 1329 ret = (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1330 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP; 1331 if (ret) 1332 goto out; 1333 1334 if (tc <= 1) { 1335 netdev_reset_tc(netdev); 1336 } else { 1337 ret = netdev_set_num_tc(netdev, tc); 1338 if (ret) 1339 goto out; 1340 1341 for (i = 0; i < HNAE3_MAX_TC; i++) { 1342 if (!kinfo->tc_info[i].enable) 1343 continue; 1344 1345 netdev_set_tc_queue(netdev, 1346 kinfo->tc_info[i].tc, 1347 kinfo->tc_info[i].tqp_count, 1348 kinfo->tc_info[i].tqp_offset); 1349 } 1350 } 1351 1352 ret = hns3_nic_set_real_num_queue(netdev); 1353 1354 out: 1355 if (if_running) 1356 hns3_nic_net_open(netdev); 1357 1358 return ret; 1359 } 1360 1361 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1362 void *type_data) 1363 { 1364 if (type != TC_SETUP_QDISC_MQPRIO) 1365 return -EOPNOTSUPP; 1366 1367 return hns3_setup_tc(dev, type_data); 1368 } 1369 1370 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1371 __be16 proto, u16 vid) 1372 { 1373 struct hnae3_handle *h = hns3_get_handle(netdev); 1374 struct hns3_nic_priv *priv = netdev_priv(netdev); 1375 int ret = -EIO; 1376 1377 if (h->ae_algo->ops->set_vlan_filter) 1378 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1379 1380 if (!ret) 1381 set_bit(vid, priv->active_vlans); 1382 1383 return ret; 1384 } 1385 1386 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1387 __be16 proto, u16 vid) 1388 { 1389 struct hnae3_handle *h = hns3_get_handle(netdev); 1390 struct hns3_nic_priv *priv = netdev_priv(netdev); 1391 int ret = -EIO; 1392 1393 if (h->ae_algo->ops->set_vlan_filter) 1394 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1395 1396 if (!ret) 1397 clear_bit(vid, priv->active_vlans); 1398 1399 return ret; 1400 } 1401 1402 static void hns3_restore_vlan(struct net_device *netdev) 1403 { 1404 struct hns3_nic_priv *priv = netdev_priv(netdev); 1405 u16 vid; 1406 int ret; 1407 1408 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 1409 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 1410 if (ret) 1411 netdev_warn(netdev, "Restore vlan: %d filter, ret:%d\n", 1412 vid, ret); 1413 } 1414 } 1415 1416 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1417 u8 qos, __be16 vlan_proto) 1418 { 1419 struct hnae3_handle *h = hns3_get_handle(netdev); 1420 int ret = -EIO; 1421 1422 if (h->ae_algo->ops->set_vf_vlan_filter) 1423 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1424 qos, vlan_proto); 1425 1426 return ret; 1427 } 1428 1429 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1430 { 1431 struct hnae3_handle *h = hns3_get_handle(netdev); 1432 bool if_running = netif_running(netdev); 1433 int ret; 1434 1435 if (!h->ae_algo->ops->set_mtu) 1436 return -EOPNOTSUPP; 1437 1438 /* if this was called with netdev up then bring netdevice down */ 1439 if (if_running) { 1440 (void)hns3_nic_net_stop(netdev); 1441 msleep(100); 1442 } 1443 1444 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 1445 if (ret) { 1446 netdev_err(netdev, "failed to change MTU in hardware %d\n", 1447 ret); 1448 return ret; 1449 } 1450 1451 netdev->mtu = new_mtu; 1452 1453 /* if the netdev was running earlier, bring it up again */ 1454 if (if_running && hns3_nic_net_open(netdev)) 1455 ret = -EINVAL; 1456 1457 return ret; 1458 } 1459 1460 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 1461 { 1462 struct hns3_nic_priv *priv = netdev_priv(ndev); 1463 struct hns3_enet_ring *tx_ring = NULL; 1464 int timeout_queue = 0; 1465 int hw_head, hw_tail; 1466 int i; 1467 1468 /* Find the stopped queue the same way the stack does */ 1469 for (i = 0; i < ndev->real_num_tx_queues; i++) { 1470 struct netdev_queue *q; 1471 unsigned long trans_start; 1472 1473 q = netdev_get_tx_queue(ndev, i); 1474 trans_start = q->trans_start; 1475 if (netif_xmit_stopped(q) && 1476 time_after(jiffies, 1477 (trans_start + ndev->watchdog_timeo))) { 1478 timeout_queue = i; 1479 break; 1480 } 1481 } 1482 1483 if (i == ndev->num_tx_queues) { 1484 netdev_info(ndev, 1485 "no netdev TX timeout queue found, timeout count: %llu\n", 1486 priv->tx_timeout_count); 1487 return false; 1488 } 1489 1490 tx_ring = priv->ring_data[timeout_queue].ring; 1491 1492 hw_head = readl_relaxed(tx_ring->tqp->io_base + 1493 HNS3_RING_TX_RING_HEAD_REG); 1494 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 1495 HNS3_RING_TX_RING_TAIL_REG); 1496 netdev_info(ndev, 1497 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n", 1498 priv->tx_timeout_count, 1499 timeout_queue, 1500 tx_ring->next_to_use, 1501 tx_ring->next_to_clean, 1502 hw_head, 1503 hw_tail, 1504 readl(tx_ring->tqp_vector->mask_addr)); 1505 1506 return true; 1507 } 1508 1509 static void hns3_nic_net_timeout(struct net_device *ndev) 1510 { 1511 struct hns3_nic_priv *priv = netdev_priv(ndev); 1512 struct hnae3_handle *h = priv->ae_handle; 1513 1514 if (!hns3_get_tx_timeo_queue_info(ndev)) 1515 return; 1516 1517 priv->tx_timeout_count++; 1518 1519 if (time_before(jiffies, (h->last_reset_time + ndev->watchdog_timeo))) 1520 return; 1521 1522 /* request the reset */ 1523 if (h->ae_algo->ops->reset_event) 1524 h->ae_algo->ops->reset_event(h); 1525 } 1526 1527 static const struct net_device_ops hns3_nic_netdev_ops = { 1528 .ndo_open = hns3_nic_net_open, 1529 .ndo_stop = hns3_nic_net_stop, 1530 .ndo_start_xmit = hns3_nic_net_xmit, 1531 .ndo_tx_timeout = hns3_nic_net_timeout, 1532 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 1533 .ndo_change_mtu = hns3_nic_change_mtu, 1534 .ndo_set_features = hns3_nic_set_features, 1535 .ndo_get_stats64 = hns3_nic_get_stats64, 1536 .ndo_setup_tc = hns3_nic_setup_tc, 1537 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 1538 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 1539 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 1540 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 1541 }; 1542 1543 static bool hns3_is_phys_func(struct pci_dev *pdev) 1544 { 1545 u32 dev_id = pdev->device; 1546 1547 switch (dev_id) { 1548 case HNAE3_DEV_ID_GE: 1549 case HNAE3_DEV_ID_25GE: 1550 case HNAE3_DEV_ID_25GE_RDMA: 1551 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 1552 case HNAE3_DEV_ID_50GE_RDMA: 1553 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 1554 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 1555 return true; 1556 case HNAE3_DEV_ID_100G_VF: 1557 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF: 1558 return false; 1559 default: 1560 dev_warn(&pdev->dev, "un-recognized pci device-id %d", 1561 dev_id); 1562 } 1563 1564 return false; 1565 } 1566 1567 static void hns3_disable_sriov(struct pci_dev *pdev) 1568 { 1569 /* If our VFs are assigned we cannot shut down SR-IOV 1570 * without causing issues, so just leave the hardware 1571 * available but disabled 1572 */ 1573 if (pci_vfs_assigned(pdev)) { 1574 dev_warn(&pdev->dev, 1575 "disabling driver while VFs are assigned\n"); 1576 return; 1577 } 1578 1579 pci_disable_sriov(pdev); 1580 } 1581 1582 /* hns3_probe - Device initialization routine 1583 * @pdev: PCI device information struct 1584 * @ent: entry in hns3_pci_tbl 1585 * 1586 * hns3_probe initializes a PF identified by a pci_dev structure. 1587 * The OS initialization, configuring of the PF private structure, 1588 * and a hardware reset occur. 1589 * 1590 * Returns 0 on success, negative on failure 1591 */ 1592 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1593 { 1594 struct hnae3_ae_dev *ae_dev; 1595 int ret; 1596 1597 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), 1598 GFP_KERNEL); 1599 if (!ae_dev) { 1600 ret = -ENOMEM; 1601 return ret; 1602 } 1603 1604 ae_dev->pdev = pdev; 1605 ae_dev->flag = ent->driver_data; 1606 ae_dev->dev_type = HNAE3_DEV_KNIC; 1607 pci_set_drvdata(pdev, ae_dev); 1608 1609 hnae3_register_ae_dev(ae_dev); 1610 1611 return 0; 1612 } 1613 1614 /* hns3_remove - Device removal routine 1615 * @pdev: PCI device information struct 1616 */ 1617 static void hns3_remove(struct pci_dev *pdev) 1618 { 1619 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1620 1621 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 1622 hns3_disable_sriov(pdev); 1623 1624 hnae3_unregister_ae_dev(ae_dev); 1625 } 1626 1627 /** 1628 * hns3_pci_sriov_configure 1629 * @pdev: pointer to a pci_dev structure 1630 * @num_vfs: number of VFs to allocate 1631 * 1632 * Enable or change the number of VFs. Called when the user updates the number 1633 * of VFs in sysfs. 1634 **/ 1635 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 1636 { 1637 int ret; 1638 1639 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 1640 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 1641 return -EINVAL; 1642 } 1643 1644 if (num_vfs) { 1645 ret = pci_enable_sriov(pdev, num_vfs); 1646 if (ret) 1647 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 1648 else 1649 return num_vfs; 1650 } else if (!pci_vfs_assigned(pdev)) { 1651 pci_disable_sriov(pdev); 1652 } else { 1653 dev_warn(&pdev->dev, 1654 "Unable to free VFs because some are assigned to VMs.\n"); 1655 } 1656 1657 return 0; 1658 } 1659 1660 static struct pci_driver hns3_driver = { 1661 .name = hns3_driver_name, 1662 .id_table = hns3_pci_tbl, 1663 .probe = hns3_probe, 1664 .remove = hns3_remove, 1665 .sriov_configure = hns3_pci_sriov_configure, 1666 }; 1667 1668 /* set default feature to hns3 */ 1669 static void hns3_set_default_feature(struct net_device *netdev) 1670 { 1671 netdev->priv_flags |= IFF_UNICAST_FLT; 1672 1673 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1674 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1675 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1676 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1677 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1678 1679 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID; 1680 1681 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 1682 1683 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1684 NETIF_F_HW_VLAN_CTAG_FILTER | 1685 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1686 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1687 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1688 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1689 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1690 1691 netdev->vlan_features |= 1692 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | 1693 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 1694 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1695 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1696 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1697 1698 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1699 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1700 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1701 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1702 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1703 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1704 } 1705 1706 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 1707 struct hns3_desc_cb *cb) 1708 { 1709 unsigned int order = hnae3_page_order(ring); 1710 struct page *p; 1711 1712 p = dev_alloc_pages(order); 1713 if (!p) 1714 return -ENOMEM; 1715 1716 cb->priv = p; 1717 cb->page_offset = 0; 1718 cb->reuse_flag = 0; 1719 cb->buf = page_address(p); 1720 cb->length = hnae3_page_size(ring); 1721 cb->type = DESC_TYPE_PAGE; 1722 1723 return 0; 1724 } 1725 1726 static void hns3_free_buffer(struct hns3_enet_ring *ring, 1727 struct hns3_desc_cb *cb) 1728 { 1729 if (cb->type == DESC_TYPE_SKB) 1730 dev_kfree_skb_any((struct sk_buff *)cb->priv); 1731 else if (!HNAE3_IS_TX_RING(ring)) 1732 put_page((struct page *)cb->priv); 1733 memset(cb, 0, sizeof(*cb)); 1734 } 1735 1736 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 1737 { 1738 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 1739 cb->length, ring_to_dma_dir(ring)); 1740 1741 if (dma_mapping_error(ring_to_dev(ring), cb->dma)) 1742 return -EIO; 1743 1744 return 0; 1745 } 1746 1747 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 1748 struct hns3_desc_cb *cb) 1749 { 1750 if (cb->type == DESC_TYPE_SKB) 1751 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 1752 ring_to_dma_dir(ring)); 1753 else 1754 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 1755 ring_to_dma_dir(ring)); 1756 } 1757 1758 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 1759 { 1760 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 1761 ring->desc[i].addr = 0; 1762 } 1763 1764 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i) 1765 { 1766 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 1767 1768 if (!ring->desc_cb[i].dma) 1769 return; 1770 1771 hns3_buffer_detach(ring, i); 1772 hns3_free_buffer(ring, cb); 1773 } 1774 1775 static void hns3_free_buffers(struct hns3_enet_ring *ring) 1776 { 1777 int i; 1778 1779 for (i = 0; i < ring->desc_num; i++) 1780 hns3_free_buffer_detach(ring, i); 1781 } 1782 1783 /* free desc along with its attached buffer */ 1784 static void hns3_free_desc(struct hns3_enet_ring *ring) 1785 { 1786 int size = ring->desc_num * sizeof(ring->desc[0]); 1787 1788 hns3_free_buffers(ring); 1789 1790 if (ring->desc) { 1791 dma_free_coherent(ring_to_dev(ring), size, 1792 ring->desc, ring->desc_dma_addr); 1793 ring->desc = NULL; 1794 } 1795 } 1796 1797 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 1798 { 1799 int size = ring->desc_num * sizeof(ring->desc[0]); 1800 1801 ring->desc = dma_zalloc_coherent(ring_to_dev(ring), size, 1802 &ring->desc_dma_addr, 1803 GFP_KERNEL); 1804 if (!ring->desc) 1805 return -ENOMEM; 1806 1807 return 0; 1808 } 1809 1810 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring, 1811 struct hns3_desc_cb *cb) 1812 { 1813 int ret; 1814 1815 ret = hns3_alloc_buffer(ring, cb); 1816 if (ret) 1817 goto out; 1818 1819 ret = hns3_map_buffer(ring, cb); 1820 if (ret) 1821 goto out_with_buf; 1822 1823 return 0; 1824 1825 out_with_buf: 1826 hns3_free_buffer(ring, cb); 1827 out: 1828 return ret; 1829 } 1830 1831 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i) 1832 { 1833 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]); 1834 1835 if (ret) 1836 return ret; 1837 1838 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 1839 1840 return 0; 1841 } 1842 1843 /* Allocate memory for raw pkg, and map with dma */ 1844 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 1845 { 1846 int i, j, ret; 1847 1848 for (i = 0; i < ring->desc_num; i++) { 1849 ret = hns3_alloc_buffer_attach(ring, i); 1850 if (ret) 1851 goto out_buffer_fail; 1852 } 1853 1854 return 0; 1855 1856 out_buffer_fail: 1857 for (j = i - 1; j >= 0; j--) 1858 hns3_free_buffer_detach(ring, j); 1859 return ret; 1860 } 1861 1862 /* detach a in-used buffer and replace with a reserved one */ 1863 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 1864 struct hns3_desc_cb *res_cb) 1865 { 1866 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 1867 ring->desc_cb[i] = *res_cb; 1868 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 1869 ring->desc[i].rx.bd_base_info = 0; 1870 } 1871 1872 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 1873 { 1874 ring->desc_cb[i].reuse_flag = 0; 1875 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma 1876 + ring->desc_cb[i].page_offset); 1877 ring->desc[i].rx.bd_base_info = 0; 1878 } 1879 1880 static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes, 1881 int *pkts) 1882 { 1883 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 1884 1885 (*pkts) += (desc_cb->type == DESC_TYPE_SKB); 1886 (*bytes) += desc_cb->length; 1887 /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/ 1888 hns3_free_buffer_detach(ring, ring->next_to_clean); 1889 1890 ring_ptr_move_fw(ring, next_to_clean); 1891 } 1892 1893 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h) 1894 { 1895 int u = ring->next_to_use; 1896 int c = ring->next_to_clean; 1897 1898 if (unlikely(h > ring->desc_num)) 1899 return 0; 1900 1901 return u > c ? (h > c && h <= u) : (h > c || h <= u); 1902 } 1903 1904 bool hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget) 1905 { 1906 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 1907 struct netdev_queue *dev_queue; 1908 int bytes, pkts; 1909 int head; 1910 1911 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG); 1912 rmb(); /* Make sure head is ready before touch any data */ 1913 1914 if (is_ring_empty(ring) || head == ring->next_to_clean) 1915 return true; /* no data to poll */ 1916 1917 if (unlikely(!is_valid_clean_head(ring, head))) { 1918 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head, 1919 ring->next_to_use, ring->next_to_clean); 1920 1921 u64_stats_update_begin(&ring->syncp); 1922 ring->stats.io_err_cnt++; 1923 u64_stats_update_end(&ring->syncp); 1924 return true; 1925 } 1926 1927 bytes = 0; 1928 pkts = 0; 1929 while (head != ring->next_to_clean && budget) { 1930 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts); 1931 /* Issue prefetch for next Tx descriptor */ 1932 prefetch(&ring->desc_cb[ring->next_to_clean]); 1933 budget--; 1934 } 1935 1936 ring->tqp_vector->tx_group.total_bytes += bytes; 1937 ring->tqp_vector->tx_group.total_packets += pkts; 1938 1939 u64_stats_update_begin(&ring->syncp); 1940 ring->stats.tx_bytes += bytes; 1941 ring->stats.tx_pkts += pkts; 1942 u64_stats_update_end(&ring->syncp); 1943 1944 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 1945 netdev_tx_completed_queue(dev_queue, pkts, bytes); 1946 1947 if (unlikely(pkts && netif_carrier_ok(netdev) && 1948 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) { 1949 /* Make sure that anybody stopping the queue after this 1950 * sees the new next_to_clean. 1951 */ 1952 smp_mb(); 1953 if (netif_tx_queue_stopped(dev_queue)) { 1954 netif_tx_wake_queue(dev_queue); 1955 ring->stats.restart_queue++; 1956 } 1957 } 1958 1959 return !!budget; 1960 } 1961 1962 static int hns3_desc_unused(struct hns3_enet_ring *ring) 1963 { 1964 int ntc = ring->next_to_clean; 1965 int ntu = ring->next_to_use; 1966 1967 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 1968 } 1969 1970 static void 1971 hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count) 1972 { 1973 struct hns3_desc_cb *desc_cb; 1974 struct hns3_desc_cb res_cbs; 1975 int i, ret; 1976 1977 for (i = 0; i < cleand_count; i++) { 1978 desc_cb = &ring->desc_cb[ring->next_to_use]; 1979 if (desc_cb->reuse_flag) { 1980 u64_stats_update_begin(&ring->syncp); 1981 ring->stats.reuse_pg_cnt++; 1982 u64_stats_update_end(&ring->syncp); 1983 1984 hns3_reuse_buffer(ring, ring->next_to_use); 1985 } else { 1986 ret = hns3_reserve_buffer_map(ring, &res_cbs); 1987 if (ret) { 1988 u64_stats_update_begin(&ring->syncp); 1989 ring->stats.sw_err_cnt++; 1990 u64_stats_update_end(&ring->syncp); 1991 1992 netdev_err(ring->tqp->handle->kinfo.netdev, 1993 "hnae reserve buffer map failed.\n"); 1994 break; 1995 } 1996 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 1997 } 1998 1999 ring_ptr_move_fw(ring, next_to_use); 2000 } 2001 2002 wmb(); /* Make all data has been write before submit */ 2003 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2004 } 2005 2006 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2007 struct hns3_enet_ring *ring, int pull_len, 2008 struct hns3_desc_cb *desc_cb) 2009 { 2010 struct hns3_desc *desc; 2011 int truesize, size; 2012 int last_offset; 2013 bool twobufs; 2014 2015 twobufs = ((PAGE_SIZE < 8192) && 2016 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048); 2017 2018 desc = &ring->desc[ring->next_to_clean]; 2019 size = le16_to_cpu(desc->rx.size); 2020 2021 truesize = hnae3_buf_size(ring); 2022 2023 if (!twobufs) 2024 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring); 2025 2026 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2027 size - pull_len, truesize); 2028 2029 /* Avoid re-using remote pages,flag default unreuse */ 2030 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id())) 2031 return; 2032 2033 if (twobufs) { 2034 /* If we are only owner of page we can reuse it */ 2035 if (likely(page_count(desc_cb->priv) == 1)) { 2036 /* Flip page offset to other buffer */ 2037 desc_cb->page_offset ^= truesize; 2038 2039 desc_cb->reuse_flag = 1; 2040 /* bump ref count on page before it is given*/ 2041 get_page(desc_cb->priv); 2042 } 2043 return; 2044 } 2045 2046 /* Move offset up to the next cache line */ 2047 desc_cb->page_offset += truesize; 2048 2049 if (desc_cb->page_offset <= last_offset) { 2050 desc_cb->reuse_flag = 1; 2051 /* Bump ref count on page before it is given*/ 2052 get_page(desc_cb->priv); 2053 } 2054 } 2055 2056 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2057 struct hns3_desc *desc) 2058 { 2059 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2060 int l3_type, l4_type; 2061 u32 bd_base_info; 2062 int ol4_type; 2063 u32 l234info; 2064 2065 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2066 l234info = le32_to_cpu(desc->rx.l234_info); 2067 2068 skb->ip_summed = CHECKSUM_NONE; 2069 2070 skb_checksum_none_assert(skb); 2071 2072 if (!(netdev->features & NETIF_F_RXCSUM)) 2073 return; 2074 2075 /* check if hardware has done checksum */ 2076 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B)) 2077 return; 2078 2079 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) || 2080 hnae3_get_bit(l234info, HNS3_RXD_L4E_B) || 2081 hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) || 2082 hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) { 2083 netdev_err(netdev, "L3/L4 error pkt\n"); 2084 u64_stats_update_begin(&ring->syncp); 2085 ring->stats.l3l4_csum_err++; 2086 u64_stats_update_end(&ring->syncp); 2087 2088 return; 2089 } 2090 2091 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2092 HNS3_RXD_L3ID_S); 2093 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 2094 HNS3_RXD_L4ID_S); 2095 2096 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M, 2097 HNS3_RXD_OL4ID_S); 2098 switch (ol4_type) { 2099 case HNS3_OL4_TYPE_MAC_IN_UDP: 2100 case HNS3_OL4_TYPE_NVGRE: 2101 skb->csum_level = 1; 2102 case HNS3_OL4_TYPE_NO_TUN: 2103 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 2104 if ((l3_type == HNS3_L3_TYPE_IPV4 || 2105 l3_type == HNS3_L3_TYPE_IPV6) && 2106 (l4_type == HNS3_L4_TYPE_UDP || 2107 l4_type == HNS3_L4_TYPE_TCP || 2108 l4_type == HNS3_L4_TYPE_SCTP)) 2109 skb->ip_summed = CHECKSUM_UNNECESSARY; 2110 break; 2111 } 2112 } 2113 2114 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 2115 { 2116 napi_gro_receive(&ring->tqp_vector->napi, skb); 2117 } 2118 2119 static u16 hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 2120 struct hns3_desc *desc, u32 l234info) 2121 { 2122 struct pci_dev *pdev = ring->tqp->handle->pdev; 2123 u16 vlan_tag; 2124 2125 if (pdev->revision == 0x20) { 2126 vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2127 if (!(vlan_tag & VLAN_VID_MASK)) 2128 vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2129 2130 return vlan_tag; 2131 } 2132 2133 #define HNS3_STRP_OUTER_VLAN 0x1 2134 #define HNS3_STRP_INNER_VLAN 0x2 2135 2136 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 2137 HNS3_RXD_STRP_TAGP_S)) { 2138 case HNS3_STRP_OUTER_VLAN: 2139 vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2140 break; 2141 case HNS3_STRP_INNER_VLAN: 2142 vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2143 break; 2144 default: 2145 vlan_tag = 0; 2146 break; 2147 } 2148 2149 return vlan_tag; 2150 } 2151 2152 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring, 2153 struct sk_buff **out_skb, int *out_bnum) 2154 { 2155 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2156 struct hns3_desc_cb *desc_cb; 2157 struct hns3_desc *desc; 2158 struct sk_buff *skb; 2159 unsigned char *va; 2160 u32 bd_base_info; 2161 int pull_len; 2162 u32 l234info; 2163 int length; 2164 int bnum; 2165 2166 desc = &ring->desc[ring->next_to_clean]; 2167 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2168 2169 prefetch(desc); 2170 2171 length = le16_to_cpu(desc->rx.size); 2172 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2173 2174 /* Check valid BD */ 2175 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) 2176 return -EFAULT; 2177 2178 va = (unsigned char *)desc_cb->buf + desc_cb->page_offset; 2179 2180 /* Prefetch first cache line of first page 2181 * Idea is to cache few bytes of the header of the packet. Our L1 Cache 2182 * line size is 64B so need to prefetch twice to make it 128B. But in 2183 * actual we can have greater size of caches with 128B Level 1 cache 2184 * lines. In such a case, single fetch would suffice to cache in the 2185 * relevant part of the header. 2186 */ 2187 prefetch(va); 2188 #if L1_CACHE_BYTES < 128 2189 prefetch(va + L1_CACHE_BYTES); 2190 #endif 2191 2192 skb = *out_skb = napi_alloc_skb(&ring->tqp_vector->napi, 2193 HNS3_RX_HEAD_SIZE); 2194 if (unlikely(!skb)) { 2195 netdev_err(netdev, "alloc rx skb fail\n"); 2196 2197 u64_stats_update_begin(&ring->syncp); 2198 ring->stats.sw_err_cnt++; 2199 u64_stats_update_end(&ring->syncp); 2200 2201 return -ENOMEM; 2202 } 2203 2204 prefetchw(skb->data); 2205 2206 bnum = 1; 2207 if (length <= HNS3_RX_HEAD_SIZE) { 2208 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 2209 2210 /* We can reuse buffer as-is, just make sure it is local */ 2211 if (likely(page_to_nid(desc_cb->priv) == numa_node_id())) 2212 desc_cb->reuse_flag = 1; 2213 else /* This page cannot be reused so discard it */ 2214 put_page(desc_cb->priv); 2215 2216 ring_ptr_move_fw(ring, next_to_clean); 2217 } else { 2218 u64_stats_update_begin(&ring->syncp); 2219 ring->stats.seg_pkt_cnt++; 2220 u64_stats_update_end(&ring->syncp); 2221 2222 pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE); 2223 2224 memcpy(__skb_put(skb, pull_len), va, 2225 ALIGN(pull_len, sizeof(long))); 2226 2227 hns3_nic_reuse_page(skb, 0, ring, pull_len, desc_cb); 2228 ring_ptr_move_fw(ring, next_to_clean); 2229 2230 while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) { 2231 desc = &ring->desc[ring->next_to_clean]; 2232 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2233 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2234 hns3_nic_reuse_page(skb, bnum, ring, 0, desc_cb); 2235 ring_ptr_move_fw(ring, next_to_clean); 2236 bnum++; 2237 } 2238 } 2239 2240 *out_bnum = bnum; 2241 2242 l234info = le32_to_cpu(desc->rx.l234_info); 2243 2244 /* Based on hw strategy, the tag offloaded will be stored at 2245 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 2246 * in one layer tag case. 2247 */ 2248 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 2249 u16 vlan_tag; 2250 2251 vlan_tag = hns3_parse_vlan_tag(ring, desc, l234info); 2252 if (vlan_tag & VLAN_VID_MASK) 2253 __vlan_hwaccel_put_tag(skb, 2254 htons(ETH_P_8021Q), 2255 vlan_tag); 2256 } 2257 2258 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) { 2259 netdev_err(netdev, "no valid bd,%016llx,%016llx\n", 2260 ((u64 *)desc)[0], ((u64 *)desc)[1]); 2261 u64_stats_update_begin(&ring->syncp); 2262 ring->stats.non_vld_descs++; 2263 u64_stats_update_end(&ring->syncp); 2264 2265 dev_kfree_skb_any(skb); 2266 return -EINVAL; 2267 } 2268 2269 if (unlikely((!desc->rx.pkt_len) || 2270 hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) { 2271 netdev_err(netdev, "truncated pkt\n"); 2272 u64_stats_update_begin(&ring->syncp); 2273 ring->stats.err_pkt_len++; 2274 u64_stats_update_end(&ring->syncp); 2275 2276 dev_kfree_skb_any(skb); 2277 return -EFAULT; 2278 } 2279 2280 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) { 2281 netdev_err(netdev, "L2 error pkt\n"); 2282 u64_stats_update_begin(&ring->syncp); 2283 ring->stats.l2_err++; 2284 u64_stats_update_end(&ring->syncp); 2285 2286 dev_kfree_skb_any(skb); 2287 return -EFAULT; 2288 } 2289 2290 u64_stats_update_begin(&ring->syncp); 2291 ring->stats.rx_pkts++; 2292 ring->stats.rx_bytes += skb->len; 2293 u64_stats_update_end(&ring->syncp); 2294 2295 ring->tqp_vector->rx_group.total_bytes += skb->len; 2296 2297 hns3_rx_checksum(ring, skb, desc); 2298 return 0; 2299 } 2300 2301 int hns3_clean_rx_ring( 2302 struct hns3_enet_ring *ring, int budget, 2303 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 2304 { 2305 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 2306 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2307 int recv_pkts, recv_bds, clean_count, err; 2308 int unused_count = hns3_desc_unused(ring); 2309 struct sk_buff *skb = NULL; 2310 int num, bnum = 0; 2311 2312 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG); 2313 rmb(); /* Make sure num taken effect before the other data is touched */ 2314 2315 recv_pkts = 0, recv_bds = 0, clean_count = 0; 2316 num -= unused_count; 2317 2318 while (recv_pkts < budget && recv_bds < num) { 2319 /* Reuse or realloc buffers */ 2320 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 2321 hns3_nic_alloc_rx_buffers(ring, 2322 clean_count + unused_count); 2323 clean_count = 0; 2324 unused_count = hns3_desc_unused(ring); 2325 } 2326 2327 /* Poll one pkt */ 2328 err = hns3_handle_rx_bd(ring, &skb, &bnum); 2329 if (unlikely(!skb)) /* This fault cannot be repaired */ 2330 goto out; 2331 2332 recv_bds += bnum; 2333 clean_count += bnum; 2334 if (unlikely(err)) { /* Do jump the err */ 2335 recv_pkts++; 2336 continue; 2337 } 2338 2339 /* Do update ip stack process */ 2340 skb->protocol = eth_type_trans(skb, netdev); 2341 rx_fn(ring, skb); 2342 2343 recv_pkts++; 2344 } 2345 2346 out: 2347 /* Make all data has been write before submit */ 2348 if (clean_count + unused_count > 0) 2349 hns3_nic_alloc_rx_buffers(ring, 2350 clean_count + unused_count); 2351 2352 return recv_pkts; 2353 } 2354 2355 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 2356 { 2357 struct hns3_enet_tqp_vector *tqp_vector = 2358 ring_group->ring->tqp_vector; 2359 enum hns3_flow_level_range new_flow_level; 2360 int packets_per_msecs; 2361 int bytes_per_msecs; 2362 u32 time_passed_ms; 2363 u16 new_int_gl; 2364 2365 if (!ring_group->coal.int_gl || !tqp_vector->last_jiffies) 2366 return false; 2367 2368 if (ring_group->total_packets == 0) { 2369 ring_group->coal.int_gl = HNS3_INT_GL_50K; 2370 ring_group->coal.flow_level = HNS3_FLOW_LOW; 2371 return true; 2372 } 2373 2374 /* Simple throttlerate management 2375 * 0-10MB/s lower (50000 ints/s) 2376 * 10-20MB/s middle (20000 ints/s) 2377 * 20-1249MB/s high (18000 ints/s) 2378 * > 40000pps ultra (8000 ints/s) 2379 */ 2380 new_flow_level = ring_group->coal.flow_level; 2381 new_int_gl = ring_group->coal.int_gl; 2382 time_passed_ms = 2383 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 2384 2385 if (!time_passed_ms) 2386 return false; 2387 2388 do_div(ring_group->total_packets, time_passed_ms); 2389 packets_per_msecs = ring_group->total_packets; 2390 2391 do_div(ring_group->total_bytes, time_passed_ms); 2392 bytes_per_msecs = ring_group->total_bytes; 2393 2394 #define HNS3_RX_LOW_BYTE_RATE 10000 2395 #define HNS3_RX_MID_BYTE_RATE 20000 2396 2397 switch (new_flow_level) { 2398 case HNS3_FLOW_LOW: 2399 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 2400 new_flow_level = HNS3_FLOW_MID; 2401 break; 2402 case HNS3_FLOW_MID: 2403 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 2404 new_flow_level = HNS3_FLOW_HIGH; 2405 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 2406 new_flow_level = HNS3_FLOW_LOW; 2407 break; 2408 case HNS3_FLOW_HIGH: 2409 case HNS3_FLOW_ULTRA: 2410 default: 2411 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 2412 new_flow_level = HNS3_FLOW_MID; 2413 break; 2414 } 2415 2416 #define HNS3_RX_ULTRA_PACKET_RATE 40 2417 2418 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 2419 &tqp_vector->rx_group == ring_group) 2420 new_flow_level = HNS3_FLOW_ULTRA; 2421 2422 switch (new_flow_level) { 2423 case HNS3_FLOW_LOW: 2424 new_int_gl = HNS3_INT_GL_50K; 2425 break; 2426 case HNS3_FLOW_MID: 2427 new_int_gl = HNS3_INT_GL_20K; 2428 break; 2429 case HNS3_FLOW_HIGH: 2430 new_int_gl = HNS3_INT_GL_18K; 2431 break; 2432 case HNS3_FLOW_ULTRA: 2433 new_int_gl = HNS3_INT_GL_8K; 2434 break; 2435 default: 2436 break; 2437 } 2438 2439 ring_group->total_bytes = 0; 2440 ring_group->total_packets = 0; 2441 ring_group->coal.flow_level = new_flow_level; 2442 if (new_int_gl != ring_group->coal.int_gl) { 2443 ring_group->coal.int_gl = new_int_gl; 2444 return true; 2445 } 2446 return false; 2447 } 2448 2449 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 2450 { 2451 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 2452 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 2453 bool rx_update, tx_update; 2454 2455 if (tqp_vector->int_adapt_down > 0) { 2456 tqp_vector->int_adapt_down--; 2457 return; 2458 } 2459 2460 if (rx_group->coal.gl_adapt_enable) { 2461 rx_update = hns3_get_new_int_gl(rx_group); 2462 if (rx_update) 2463 hns3_set_vector_coalesce_rx_gl(tqp_vector, 2464 rx_group->coal.int_gl); 2465 } 2466 2467 if (tx_group->coal.gl_adapt_enable) { 2468 tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group); 2469 if (tx_update) 2470 hns3_set_vector_coalesce_tx_gl(tqp_vector, 2471 tx_group->coal.int_gl); 2472 } 2473 2474 tqp_vector->last_jiffies = jiffies; 2475 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START; 2476 } 2477 2478 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 2479 { 2480 struct hns3_enet_ring *ring; 2481 int rx_pkt_total = 0; 2482 2483 struct hns3_enet_tqp_vector *tqp_vector = 2484 container_of(napi, struct hns3_enet_tqp_vector, napi); 2485 bool clean_complete = true; 2486 int rx_budget; 2487 2488 /* Since the actual Tx work is minimal, we can give the Tx a larger 2489 * budget and be more aggressive about cleaning up the Tx descriptors. 2490 */ 2491 hns3_for_each_ring(ring, tqp_vector->tx_group) { 2492 if (!hns3_clean_tx_ring(ring, budget)) 2493 clean_complete = false; 2494 } 2495 2496 /* make sure rx ring budget not smaller than 1 */ 2497 rx_budget = max(budget / tqp_vector->num_tqps, 1); 2498 2499 hns3_for_each_ring(ring, tqp_vector->rx_group) { 2500 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 2501 hns3_rx_skb); 2502 2503 if (rx_cleaned >= rx_budget) 2504 clean_complete = false; 2505 2506 rx_pkt_total += rx_cleaned; 2507 } 2508 2509 tqp_vector->rx_group.total_packets += rx_pkt_total; 2510 2511 if (!clean_complete) 2512 return budget; 2513 2514 napi_complete(napi); 2515 hns3_update_new_int_gl(tqp_vector); 2516 hns3_mask_vector_irq(tqp_vector, 1); 2517 2518 return rx_pkt_total; 2519 } 2520 2521 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 2522 struct hnae3_ring_chain_node *head) 2523 { 2524 struct pci_dev *pdev = tqp_vector->handle->pdev; 2525 struct hnae3_ring_chain_node *cur_chain = head; 2526 struct hnae3_ring_chain_node *chain; 2527 struct hns3_enet_ring *tx_ring; 2528 struct hns3_enet_ring *rx_ring; 2529 2530 tx_ring = tqp_vector->tx_group.ring; 2531 if (tx_ring) { 2532 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 2533 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 2534 HNAE3_RING_TYPE_TX); 2535 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2536 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 2537 2538 cur_chain->next = NULL; 2539 2540 while (tx_ring->next) { 2541 tx_ring = tx_ring->next; 2542 2543 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 2544 GFP_KERNEL); 2545 if (!chain) 2546 return -ENOMEM; 2547 2548 cur_chain->next = chain; 2549 chain->tqp_index = tx_ring->tqp->tqp_index; 2550 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 2551 HNAE3_RING_TYPE_TX); 2552 hnae3_set_field(chain->int_gl_idx, 2553 HNAE3_RING_GL_IDX_M, 2554 HNAE3_RING_GL_IDX_S, 2555 HNAE3_RING_GL_TX); 2556 2557 cur_chain = chain; 2558 } 2559 } 2560 2561 rx_ring = tqp_vector->rx_group.ring; 2562 if (!tx_ring && rx_ring) { 2563 cur_chain->next = NULL; 2564 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 2565 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 2566 HNAE3_RING_TYPE_RX); 2567 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2568 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 2569 2570 rx_ring = rx_ring->next; 2571 } 2572 2573 while (rx_ring) { 2574 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 2575 if (!chain) 2576 return -ENOMEM; 2577 2578 cur_chain->next = chain; 2579 chain->tqp_index = rx_ring->tqp->tqp_index; 2580 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 2581 HNAE3_RING_TYPE_RX); 2582 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2583 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 2584 2585 cur_chain = chain; 2586 2587 rx_ring = rx_ring->next; 2588 } 2589 2590 return 0; 2591 } 2592 2593 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 2594 struct hnae3_ring_chain_node *head) 2595 { 2596 struct pci_dev *pdev = tqp_vector->handle->pdev; 2597 struct hnae3_ring_chain_node *chain_tmp, *chain; 2598 2599 chain = head->next; 2600 2601 while (chain) { 2602 chain_tmp = chain->next; 2603 devm_kfree(&pdev->dev, chain); 2604 chain = chain_tmp; 2605 } 2606 } 2607 2608 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 2609 struct hns3_enet_ring *ring) 2610 { 2611 ring->next = group->ring; 2612 group->ring = ring; 2613 2614 group->count++; 2615 } 2616 2617 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 2618 { 2619 struct hnae3_ring_chain_node vector_ring_chain; 2620 struct hnae3_handle *h = priv->ae_handle; 2621 struct hns3_enet_tqp_vector *tqp_vector; 2622 int ret = 0; 2623 u16 i; 2624 2625 for (i = 0; i < priv->vector_num; i++) { 2626 tqp_vector = &priv->tqp_vector[i]; 2627 hns3_vector_gl_rl_init_hw(tqp_vector, priv); 2628 tqp_vector->num_tqps = 0; 2629 } 2630 2631 for (i = 0; i < h->kinfo.num_tqps; i++) { 2632 u16 vector_i = i % priv->vector_num; 2633 u16 tqp_num = h->kinfo.num_tqps; 2634 2635 tqp_vector = &priv->tqp_vector[vector_i]; 2636 2637 hns3_add_ring_to_group(&tqp_vector->tx_group, 2638 priv->ring_data[i].ring); 2639 2640 hns3_add_ring_to_group(&tqp_vector->rx_group, 2641 priv->ring_data[i + tqp_num].ring); 2642 2643 priv->ring_data[i].ring->tqp_vector = tqp_vector; 2644 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector; 2645 tqp_vector->num_tqps++; 2646 } 2647 2648 for (i = 0; i < priv->vector_num; i++) { 2649 tqp_vector = &priv->tqp_vector[i]; 2650 2651 tqp_vector->rx_group.total_bytes = 0; 2652 tqp_vector->rx_group.total_packets = 0; 2653 tqp_vector->tx_group.total_bytes = 0; 2654 tqp_vector->tx_group.total_packets = 0; 2655 tqp_vector->handle = h; 2656 2657 ret = hns3_get_vector_ring_chain(tqp_vector, 2658 &vector_ring_chain); 2659 if (ret) 2660 return ret; 2661 2662 ret = h->ae_algo->ops->map_ring_to_vector(h, 2663 tqp_vector->vector_irq, &vector_ring_chain); 2664 2665 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 2666 2667 if (ret) 2668 return ret; 2669 2670 netif_napi_add(priv->netdev, &tqp_vector->napi, 2671 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 2672 } 2673 2674 return 0; 2675 } 2676 2677 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 2678 { 2679 struct hnae3_handle *h = priv->ae_handle; 2680 struct hns3_enet_tqp_vector *tqp_vector; 2681 struct hnae3_vector_info *vector; 2682 struct pci_dev *pdev = h->pdev; 2683 u16 tqp_num = h->kinfo.num_tqps; 2684 u16 vector_num; 2685 int ret = 0; 2686 u16 i; 2687 2688 /* RSS size, cpu online and vector_num should be the same */ 2689 /* Should consider 2p/4p later */ 2690 vector_num = min_t(u16, num_online_cpus(), tqp_num); 2691 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 2692 GFP_KERNEL); 2693 if (!vector) 2694 return -ENOMEM; 2695 2696 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 2697 2698 priv->vector_num = vector_num; 2699 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 2700 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 2701 GFP_KERNEL); 2702 if (!priv->tqp_vector) { 2703 ret = -ENOMEM; 2704 goto out; 2705 } 2706 2707 for (i = 0; i < priv->vector_num; i++) { 2708 tqp_vector = &priv->tqp_vector[i]; 2709 tqp_vector->idx = i; 2710 tqp_vector->mask_addr = vector[i].io_addr; 2711 tqp_vector->vector_irq = vector[i].vector; 2712 hns3_vector_gl_rl_init(tqp_vector, priv); 2713 } 2714 2715 out: 2716 devm_kfree(&pdev->dev, vector); 2717 return ret; 2718 } 2719 2720 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 2721 { 2722 group->ring = NULL; 2723 group->count = 0; 2724 } 2725 2726 static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 2727 { 2728 struct hnae3_ring_chain_node vector_ring_chain; 2729 struct hnae3_handle *h = priv->ae_handle; 2730 struct hns3_enet_tqp_vector *tqp_vector; 2731 int i, ret; 2732 2733 for (i = 0; i < priv->vector_num; i++) { 2734 tqp_vector = &priv->tqp_vector[i]; 2735 2736 ret = hns3_get_vector_ring_chain(tqp_vector, 2737 &vector_ring_chain); 2738 if (ret) 2739 return ret; 2740 2741 ret = h->ae_algo->ops->unmap_ring_from_vector(h, 2742 tqp_vector->vector_irq, &vector_ring_chain); 2743 if (ret) 2744 return ret; 2745 2746 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 2747 2748 if (priv->tqp_vector[i].irq_init_flag == HNS3_VECTOR_INITED) { 2749 (void)irq_set_affinity_hint( 2750 priv->tqp_vector[i].vector_irq, 2751 NULL); 2752 free_irq(priv->tqp_vector[i].vector_irq, 2753 &priv->tqp_vector[i]); 2754 } 2755 2756 priv->ring_data[i].ring->irq_init_flag = HNS3_VECTOR_NOT_INITED; 2757 hns3_clear_ring_group(&tqp_vector->rx_group); 2758 hns3_clear_ring_group(&tqp_vector->tx_group); 2759 netif_napi_del(&priv->tqp_vector[i].napi); 2760 } 2761 2762 return 0; 2763 } 2764 2765 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 2766 { 2767 struct hnae3_handle *h = priv->ae_handle; 2768 struct pci_dev *pdev = h->pdev; 2769 int i, ret; 2770 2771 for (i = 0; i < priv->vector_num; i++) { 2772 struct hns3_enet_tqp_vector *tqp_vector; 2773 2774 tqp_vector = &priv->tqp_vector[i]; 2775 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 2776 if (ret) 2777 return ret; 2778 } 2779 2780 devm_kfree(&pdev->dev, priv->tqp_vector); 2781 return 0; 2782 } 2783 2784 static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 2785 int ring_type) 2786 { 2787 struct hns3_nic_ring_data *ring_data = priv->ring_data; 2788 int queue_num = priv->ae_handle->kinfo.num_tqps; 2789 struct pci_dev *pdev = priv->ae_handle->pdev; 2790 struct hns3_enet_ring *ring; 2791 2792 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL); 2793 if (!ring) 2794 return -ENOMEM; 2795 2796 if (ring_type == HNAE3_RING_TYPE_TX) { 2797 ring_data[q->tqp_index].ring = ring; 2798 ring_data[q->tqp_index].queue_index = q->tqp_index; 2799 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET; 2800 } else { 2801 ring_data[q->tqp_index + queue_num].ring = ring; 2802 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index; 2803 ring->io_base = q->io_base; 2804 } 2805 2806 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 2807 2808 ring->tqp = q; 2809 ring->desc = NULL; 2810 ring->desc_cb = NULL; 2811 ring->dev = priv->dev; 2812 ring->desc_dma_addr = 0; 2813 ring->buf_size = q->buf_size; 2814 ring->desc_num = q->desc_num; 2815 ring->next_to_use = 0; 2816 ring->next_to_clean = 0; 2817 2818 return 0; 2819 } 2820 2821 static int hns3_queue_to_ring(struct hnae3_queue *tqp, 2822 struct hns3_nic_priv *priv) 2823 { 2824 int ret; 2825 2826 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 2827 if (ret) 2828 return ret; 2829 2830 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 2831 if (ret) 2832 return ret; 2833 2834 return 0; 2835 } 2836 2837 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 2838 { 2839 struct hnae3_handle *h = priv->ae_handle; 2840 struct pci_dev *pdev = h->pdev; 2841 int i, ret; 2842 2843 priv->ring_data = devm_kzalloc(&pdev->dev, 2844 array3_size(h->kinfo.num_tqps, 2845 sizeof(*priv->ring_data), 2846 2), 2847 GFP_KERNEL); 2848 if (!priv->ring_data) 2849 return -ENOMEM; 2850 2851 for (i = 0; i < h->kinfo.num_tqps; i++) { 2852 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv); 2853 if (ret) 2854 goto err; 2855 } 2856 2857 return 0; 2858 err: 2859 devm_kfree(&pdev->dev, priv->ring_data); 2860 return ret; 2861 } 2862 2863 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 2864 { 2865 struct hnae3_handle *h = priv->ae_handle; 2866 int i; 2867 2868 for (i = 0; i < h->kinfo.num_tqps; i++) { 2869 devm_kfree(priv->dev, priv->ring_data[i].ring); 2870 devm_kfree(priv->dev, 2871 priv->ring_data[i + h->kinfo.num_tqps].ring); 2872 } 2873 devm_kfree(priv->dev, priv->ring_data); 2874 } 2875 2876 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 2877 { 2878 int ret; 2879 2880 if (ring->desc_num <= 0 || ring->buf_size <= 0) 2881 return -EINVAL; 2882 2883 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]), 2884 GFP_KERNEL); 2885 if (!ring->desc_cb) { 2886 ret = -ENOMEM; 2887 goto out; 2888 } 2889 2890 ret = hns3_alloc_desc(ring); 2891 if (ret) 2892 goto out_with_desc_cb; 2893 2894 if (!HNAE3_IS_TX_RING(ring)) { 2895 ret = hns3_alloc_ring_buffers(ring); 2896 if (ret) 2897 goto out_with_desc; 2898 } 2899 2900 return 0; 2901 2902 out_with_desc: 2903 hns3_free_desc(ring); 2904 out_with_desc_cb: 2905 kfree(ring->desc_cb); 2906 ring->desc_cb = NULL; 2907 out: 2908 return ret; 2909 } 2910 2911 static void hns3_fini_ring(struct hns3_enet_ring *ring) 2912 { 2913 hns3_free_desc(ring); 2914 kfree(ring->desc_cb); 2915 ring->desc_cb = NULL; 2916 ring->next_to_clean = 0; 2917 ring->next_to_use = 0; 2918 } 2919 2920 static int hns3_buf_size2type(u32 buf_size) 2921 { 2922 int bd_size_type; 2923 2924 switch (buf_size) { 2925 case 512: 2926 bd_size_type = HNS3_BD_SIZE_512_TYPE; 2927 break; 2928 case 1024: 2929 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 2930 break; 2931 case 2048: 2932 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 2933 break; 2934 case 4096: 2935 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 2936 break; 2937 default: 2938 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 2939 } 2940 2941 return bd_size_type; 2942 } 2943 2944 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 2945 { 2946 dma_addr_t dma = ring->desc_dma_addr; 2947 struct hnae3_queue *q = ring->tqp; 2948 2949 if (!HNAE3_IS_TX_RING(ring)) { 2950 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, 2951 (u32)dma); 2952 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 2953 (u32)((dma >> 31) >> 1)); 2954 2955 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 2956 hns3_buf_size2type(ring->buf_size)); 2957 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 2958 ring->desc_num / 8 - 1); 2959 2960 } else { 2961 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 2962 (u32)dma); 2963 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 2964 (u32)((dma >> 31) >> 1)); 2965 2966 hns3_write_dev(q, HNS3_RING_TX_RING_BD_LEN_REG, 2967 hns3_buf_size2type(ring->buf_size)); 2968 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 2969 ring->desc_num / 8 - 1); 2970 } 2971 } 2972 2973 int hns3_init_all_ring(struct hns3_nic_priv *priv) 2974 { 2975 struct hnae3_handle *h = priv->ae_handle; 2976 int ring_num = h->kinfo.num_tqps * 2; 2977 int i, j; 2978 int ret; 2979 2980 for (i = 0; i < ring_num; i++) { 2981 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring); 2982 if (ret) { 2983 dev_err(priv->dev, 2984 "Alloc ring memory fail! ret=%d\n", ret); 2985 goto out_when_alloc_ring_memory; 2986 } 2987 2988 u64_stats_init(&priv->ring_data[i].ring->syncp); 2989 } 2990 2991 return 0; 2992 2993 out_when_alloc_ring_memory: 2994 for (j = i - 1; j >= 0; j--) 2995 hns3_fini_ring(priv->ring_data[j].ring); 2996 2997 return -ENOMEM; 2998 } 2999 3000 int hns3_uninit_all_ring(struct hns3_nic_priv *priv) 3001 { 3002 struct hnae3_handle *h = priv->ae_handle; 3003 int i; 3004 3005 for (i = 0; i < h->kinfo.num_tqps; i++) { 3006 if (h->ae_algo->ops->reset_queue) 3007 h->ae_algo->ops->reset_queue(h, i); 3008 3009 hns3_fini_ring(priv->ring_data[i].ring); 3010 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring); 3011 } 3012 return 0; 3013 } 3014 3015 /* Set mac addr if it is configured. or leave it to the AE driver */ 3016 static void hns3_init_mac_addr(struct net_device *netdev, bool init) 3017 { 3018 struct hns3_nic_priv *priv = netdev_priv(netdev); 3019 struct hnae3_handle *h = priv->ae_handle; 3020 u8 mac_addr_temp[ETH_ALEN]; 3021 3022 if (h->ae_algo->ops->get_mac_addr && init) { 3023 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 3024 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 3025 } 3026 3027 /* Check if the MAC address is valid, if not get a random one */ 3028 if (!is_valid_ether_addr(netdev->dev_addr)) { 3029 eth_hw_addr_random(netdev); 3030 dev_warn(priv->dev, "using random MAC address %pM\n", 3031 netdev->dev_addr); 3032 } 3033 3034 if (h->ae_algo->ops->set_mac_addr) 3035 h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 3036 3037 } 3038 3039 static void hns3_uninit_mac_addr(struct net_device *netdev) 3040 { 3041 struct hns3_nic_priv *priv = netdev_priv(netdev); 3042 struct hnae3_handle *h = priv->ae_handle; 3043 3044 if (h->ae_algo->ops->rm_uc_addr) 3045 h->ae_algo->ops->rm_uc_addr(h, netdev->dev_addr); 3046 } 3047 3048 static void hns3_nic_set_priv_ops(struct net_device *netdev) 3049 { 3050 struct hns3_nic_priv *priv = netdev_priv(netdev); 3051 3052 if ((netdev->features & NETIF_F_TSO) || 3053 (netdev->features & NETIF_F_TSO6)) { 3054 priv->ops.fill_desc = hns3_fill_desc_tso; 3055 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 3056 } else { 3057 priv->ops.fill_desc = hns3_fill_desc; 3058 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 3059 } 3060 } 3061 3062 static int hns3_client_init(struct hnae3_handle *handle) 3063 { 3064 struct pci_dev *pdev = handle->pdev; 3065 struct hns3_nic_priv *priv; 3066 struct net_device *netdev; 3067 int ret; 3068 3069 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), 3070 hns3_get_max_available_channels(handle)); 3071 if (!netdev) 3072 return -ENOMEM; 3073 3074 priv = netdev_priv(netdev); 3075 priv->dev = &pdev->dev; 3076 priv->netdev = netdev; 3077 priv->ae_handle = handle; 3078 priv->ae_handle->reset_level = HNAE3_NONE_RESET; 3079 priv->ae_handle->last_reset_time = jiffies; 3080 priv->tx_timeout_count = 0; 3081 3082 handle->kinfo.netdev = netdev; 3083 handle->priv = (void *)priv; 3084 3085 hns3_init_mac_addr(netdev, true); 3086 3087 hns3_set_default_feature(netdev); 3088 3089 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 3090 netdev->priv_flags |= IFF_UNICAST_FLT; 3091 netdev->netdev_ops = &hns3_nic_netdev_ops; 3092 SET_NETDEV_DEV(netdev, &pdev->dev); 3093 hns3_ethtool_set_ops(netdev); 3094 hns3_nic_set_priv_ops(netdev); 3095 3096 /* Carrier off reporting is important to ethtool even BEFORE open */ 3097 netif_carrier_off(netdev); 3098 3099 ret = hns3_get_ring_config(priv); 3100 if (ret) { 3101 ret = -ENOMEM; 3102 goto out_get_ring_cfg; 3103 } 3104 3105 ret = hns3_nic_alloc_vector_data(priv); 3106 if (ret) { 3107 ret = -ENOMEM; 3108 goto out_alloc_vector_data; 3109 } 3110 3111 ret = hns3_nic_init_vector_data(priv); 3112 if (ret) { 3113 ret = -ENOMEM; 3114 goto out_init_vector_data; 3115 } 3116 3117 ret = hns3_init_all_ring(priv); 3118 if (ret) { 3119 ret = -ENOMEM; 3120 goto out_init_ring_data; 3121 } 3122 3123 ret = register_netdev(netdev); 3124 if (ret) { 3125 dev_err(priv->dev, "probe register netdev fail!\n"); 3126 goto out_reg_netdev_fail; 3127 } 3128 3129 hns3_dcbnl_setup(handle); 3130 3131 /* MTU range: (ETH_MIN_MTU(kernel default) - 9706) */ 3132 netdev->max_mtu = HNS3_MAX_MTU - (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); 3133 3134 return ret; 3135 3136 out_reg_netdev_fail: 3137 out_init_ring_data: 3138 (void)hns3_nic_uninit_vector_data(priv); 3139 out_init_vector_data: 3140 hns3_nic_dealloc_vector_data(priv); 3141 out_alloc_vector_data: 3142 priv->ring_data = NULL; 3143 out_get_ring_cfg: 3144 priv->ae_handle = NULL; 3145 free_netdev(netdev); 3146 return ret; 3147 } 3148 3149 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 3150 { 3151 struct net_device *netdev = handle->kinfo.netdev; 3152 struct hns3_nic_priv *priv = netdev_priv(netdev); 3153 int ret; 3154 3155 if (netdev->reg_state != NETREG_UNINITIALIZED) 3156 unregister_netdev(netdev); 3157 3158 hns3_force_clear_all_rx_ring(handle); 3159 3160 ret = hns3_nic_uninit_vector_data(priv); 3161 if (ret) 3162 netdev_err(netdev, "uninit vector error\n"); 3163 3164 ret = hns3_nic_dealloc_vector_data(priv); 3165 if (ret) 3166 netdev_err(netdev, "dealloc vector error\n"); 3167 3168 ret = hns3_uninit_all_ring(priv); 3169 if (ret) 3170 netdev_err(netdev, "uninit ring error\n"); 3171 3172 hns3_put_ring_config(priv); 3173 3174 priv->ring_data = NULL; 3175 3176 hns3_uninit_mac_addr(netdev); 3177 3178 free_netdev(netdev); 3179 } 3180 3181 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 3182 { 3183 struct net_device *netdev = handle->kinfo.netdev; 3184 3185 if (!netdev) 3186 return; 3187 3188 if (linkup) { 3189 netif_carrier_on(netdev); 3190 netif_tx_wake_all_queues(netdev); 3191 netdev_info(netdev, "link up\n"); 3192 } else { 3193 netif_carrier_off(netdev); 3194 netif_tx_stop_all_queues(netdev); 3195 netdev_info(netdev, "link down\n"); 3196 } 3197 } 3198 3199 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc) 3200 { 3201 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3202 struct net_device *ndev = kinfo->netdev; 3203 bool if_running; 3204 int ret; 3205 u8 i; 3206 3207 if (tc > HNAE3_MAX_TC) 3208 return -EINVAL; 3209 3210 if (!ndev) 3211 return -ENODEV; 3212 3213 if_running = netif_running(ndev); 3214 3215 ret = netdev_set_num_tc(ndev, tc); 3216 if (ret) 3217 return ret; 3218 3219 if (if_running) { 3220 (void)hns3_nic_net_stop(ndev); 3221 msleep(100); 3222 } 3223 3224 ret = (kinfo->dcb_ops && kinfo->dcb_ops->map_update) ? 3225 kinfo->dcb_ops->map_update(handle) : -EOPNOTSUPP; 3226 if (ret) 3227 goto err_out; 3228 3229 if (tc <= 1) { 3230 netdev_reset_tc(ndev); 3231 goto out; 3232 } 3233 3234 for (i = 0; i < HNAE3_MAX_TC; i++) { 3235 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i]; 3236 3237 if (tc_info->enable) 3238 netdev_set_tc_queue(ndev, 3239 tc_info->tc, 3240 tc_info->tqp_count, 3241 tc_info->tqp_offset); 3242 } 3243 3244 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { 3245 netdev_set_prio_tc_map(ndev, i, 3246 kinfo->prio_tc[i]); 3247 } 3248 3249 out: 3250 ret = hns3_nic_set_real_num_queue(ndev); 3251 3252 err_out: 3253 if (if_running) 3254 (void)hns3_nic_net_open(ndev); 3255 3256 return ret; 3257 } 3258 3259 static void hns3_recover_hw_addr(struct net_device *ndev) 3260 { 3261 struct netdev_hw_addr_list *list; 3262 struct netdev_hw_addr *ha, *tmp; 3263 3264 /* go through and sync uc_addr entries to the device */ 3265 list = &ndev->uc; 3266 list_for_each_entry_safe(ha, tmp, &list->list, list) 3267 hns3_nic_uc_sync(ndev, ha->addr); 3268 3269 /* go through and sync mc_addr entries to the device */ 3270 list = &ndev->mc; 3271 list_for_each_entry_safe(ha, tmp, &list->list, list) 3272 hns3_nic_mc_sync(ndev, ha->addr); 3273 } 3274 3275 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 3276 { 3277 while (ring->next_to_clean != ring->next_to_use) { 3278 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 3279 hns3_free_buffer_detach(ring, ring->next_to_clean); 3280 ring_ptr_move_fw(ring, next_to_clean); 3281 } 3282 } 3283 3284 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 3285 { 3286 struct hns3_desc_cb res_cbs; 3287 int ret; 3288 3289 while (ring->next_to_use != ring->next_to_clean) { 3290 /* When a buffer is not reused, it's memory has been 3291 * freed in hns3_handle_rx_bd or will be freed by 3292 * stack, so we need to replace the buffer here. 3293 */ 3294 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3295 ret = hns3_reserve_buffer_map(ring, &res_cbs); 3296 if (ret) { 3297 u64_stats_update_begin(&ring->syncp); 3298 ring->stats.sw_err_cnt++; 3299 u64_stats_update_end(&ring->syncp); 3300 /* if alloc new buffer fail, exit directly 3301 * and reclear in up flow. 3302 */ 3303 netdev_warn(ring->tqp->handle->kinfo.netdev, 3304 "reserve buffer map failed, ret = %d\n", 3305 ret); 3306 return ret; 3307 } 3308 hns3_replace_buffer(ring, ring->next_to_use, 3309 &res_cbs); 3310 } 3311 ring_ptr_move_fw(ring, next_to_use); 3312 } 3313 3314 return 0; 3315 } 3316 3317 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 3318 { 3319 while (ring->next_to_use != ring->next_to_clean) { 3320 /* When a buffer is not reused, it's memory has been 3321 * freed in hns3_handle_rx_bd or will be freed by 3322 * stack, so only need to unmap the buffer here. 3323 */ 3324 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3325 hns3_unmap_buffer(ring, 3326 &ring->desc_cb[ring->next_to_use]); 3327 ring->desc_cb[ring->next_to_use].dma = 0; 3328 } 3329 3330 ring_ptr_move_fw(ring, next_to_use); 3331 } 3332 } 3333 3334 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h) 3335 { 3336 struct net_device *ndev = h->kinfo.netdev; 3337 struct hns3_nic_priv *priv = netdev_priv(ndev); 3338 struct hns3_enet_ring *ring; 3339 u32 i; 3340 3341 for (i = 0; i < h->kinfo.num_tqps; i++) { 3342 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3343 hns3_force_clear_rx_ring(ring); 3344 } 3345 } 3346 3347 static void hns3_clear_all_ring(struct hnae3_handle *h) 3348 { 3349 struct net_device *ndev = h->kinfo.netdev; 3350 struct hns3_nic_priv *priv = netdev_priv(ndev); 3351 u32 i; 3352 3353 for (i = 0; i < h->kinfo.num_tqps; i++) { 3354 struct netdev_queue *dev_queue; 3355 struct hns3_enet_ring *ring; 3356 3357 ring = priv->ring_data[i].ring; 3358 hns3_clear_tx_ring(ring); 3359 dev_queue = netdev_get_tx_queue(ndev, 3360 priv->ring_data[i].queue_index); 3361 netdev_tx_reset_queue(dev_queue); 3362 3363 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3364 /* Continue to clear other rings even if clearing some 3365 * rings failed. 3366 */ 3367 hns3_clear_rx_ring(ring); 3368 } 3369 } 3370 3371 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 3372 { 3373 struct net_device *ndev = h->kinfo.netdev; 3374 struct hns3_nic_priv *priv = netdev_priv(ndev); 3375 struct hns3_enet_ring *rx_ring; 3376 int i, j; 3377 int ret; 3378 3379 for (i = 0; i < h->kinfo.num_tqps; i++) { 3380 h->ae_algo->ops->reset_queue(h, i); 3381 hns3_init_ring_hw(priv->ring_data[i].ring); 3382 3383 /* We need to clear tx ring here because self test will 3384 * use the ring and will not run down before up 3385 */ 3386 hns3_clear_tx_ring(priv->ring_data[i].ring); 3387 priv->ring_data[i].ring->next_to_clean = 0; 3388 priv->ring_data[i].ring->next_to_use = 0; 3389 3390 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3391 hns3_init_ring_hw(rx_ring); 3392 ret = hns3_clear_rx_ring(rx_ring); 3393 if (ret) 3394 return ret; 3395 3396 /* We can not know the hardware head and tail when this 3397 * function is called in reset flow, so we reuse all desc. 3398 */ 3399 for (j = 0; j < rx_ring->desc_num; j++) 3400 hns3_reuse_buffer(rx_ring, j); 3401 3402 rx_ring->next_to_clean = 0; 3403 rx_ring->next_to_use = 0; 3404 } 3405 3406 return 0; 3407 } 3408 3409 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 3410 { 3411 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3412 struct net_device *ndev = kinfo->netdev; 3413 3414 if (!netif_running(ndev)) 3415 return -EIO; 3416 3417 return hns3_nic_net_stop(ndev); 3418 } 3419 3420 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 3421 { 3422 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3423 int ret = 0; 3424 3425 if (netif_running(kinfo->netdev)) { 3426 ret = hns3_nic_net_up(kinfo->netdev); 3427 if (ret) { 3428 netdev_err(kinfo->netdev, 3429 "hns net up fail, ret=%d!\n", ret); 3430 return ret; 3431 } 3432 handle->last_reset_time = jiffies; 3433 } 3434 3435 return ret; 3436 } 3437 3438 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 3439 { 3440 struct net_device *netdev = handle->kinfo.netdev; 3441 struct hns3_nic_priv *priv = netdev_priv(netdev); 3442 int ret; 3443 3444 hns3_init_mac_addr(netdev, false); 3445 hns3_nic_set_rx_mode(netdev); 3446 hns3_recover_hw_addr(netdev); 3447 3448 /* Hardware table is only clear when pf resets */ 3449 if (!(handle->flags & HNAE3_SUPPORT_VF)) 3450 hns3_restore_vlan(netdev); 3451 3452 /* Carrier off reporting is important to ethtool even BEFORE open */ 3453 netif_carrier_off(netdev); 3454 3455 ret = hns3_get_ring_config(priv); 3456 if (ret) 3457 return ret; 3458 3459 ret = hns3_nic_init_vector_data(priv); 3460 if (ret) 3461 return ret; 3462 3463 ret = hns3_init_all_ring(priv); 3464 if (ret) { 3465 hns3_nic_uninit_vector_data(priv); 3466 priv->ring_data = NULL; 3467 } 3468 3469 return ret; 3470 } 3471 3472 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 3473 { 3474 struct net_device *netdev = handle->kinfo.netdev; 3475 struct hns3_nic_priv *priv = netdev_priv(netdev); 3476 int ret; 3477 3478 hns3_force_clear_all_rx_ring(handle); 3479 3480 ret = hns3_nic_uninit_vector_data(priv); 3481 if (ret) { 3482 netdev_err(netdev, "uninit vector error\n"); 3483 return ret; 3484 } 3485 3486 ret = hns3_uninit_all_ring(priv); 3487 if (ret) 3488 netdev_err(netdev, "uninit ring error\n"); 3489 3490 hns3_put_ring_config(priv); 3491 3492 priv->ring_data = NULL; 3493 3494 hns3_uninit_mac_addr(netdev); 3495 3496 return ret; 3497 } 3498 3499 static int hns3_reset_notify(struct hnae3_handle *handle, 3500 enum hnae3_reset_notify_type type) 3501 { 3502 int ret = 0; 3503 3504 switch (type) { 3505 case HNAE3_UP_CLIENT: 3506 ret = hns3_reset_notify_up_enet(handle); 3507 break; 3508 case HNAE3_DOWN_CLIENT: 3509 ret = hns3_reset_notify_down_enet(handle); 3510 break; 3511 case HNAE3_INIT_CLIENT: 3512 ret = hns3_reset_notify_init_enet(handle); 3513 break; 3514 case HNAE3_UNINIT_CLIENT: 3515 ret = hns3_reset_notify_uninit_enet(handle); 3516 break; 3517 default: 3518 break; 3519 } 3520 3521 return ret; 3522 } 3523 3524 static void hns3_restore_coal(struct hns3_nic_priv *priv, 3525 struct hns3_enet_coalesce *tx, 3526 struct hns3_enet_coalesce *rx) 3527 { 3528 u16 vector_num = priv->vector_num; 3529 int i; 3530 3531 for (i = 0; i < vector_num; i++) { 3532 memcpy(&priv->tqp_vector[i].tx_group.coal, tx, 3533 sizeof(struct hns3_enet_coalesce)); 3534 memcpy(&priv->tqp_vector[i].rx_group.coal, rx, 3535 sizeof(struct hns3_enet_coalesce)); 3536 } 3537 } 3538 3539 static int hns3_modify_tqp_num(struct net_device *netdev, u16 new_tqp_num, 3540 struct hns3_enet_coalesce *tx, 3541 struct hns3_enet_coalesce *rx) 3542 { 3543 struct hns3_nic_priv *priv = netdev_priv(netdev); 3544 struct hnae3_handle *h = hns3_get_handle(netdev); 3545 int ret; 3546 3547 ret = h->ae_algo->ops->set_channels(h, new_tqp_num); 3548 if (ret) 3549 return ret; 3550 3551 ret = hns3_get_ring_config(priv); 3552 if (ret) 3553 return ret; 3554 3555 ret = hns3_nic_alloc_vector_data(priv); 3556 if (ret) 3557 goto err_alloc_vector; 3558 3559 hns3_restore_coal(priv, tx, rx); 3560 3561 ret = hns3_nic_init_vector_data(priv); 3562 if (ret) 3563 goto err_uninit_vector; 3564 3565 ret = hns3_init_all_ring(priv); 3566 if (ret) 3567 goto err_put_ring; 3568 3569 return 0; 3570 3571 err_put_ring: 3572 hns3_put_ring_config(priv); 3573 err_uninit_vector: 3574 hns3_nic_uninit_vector_data(priv); 3575 err_alloc_vector: 3576 hns3_nic_dealloc_vector_data(priv); 3577 return ret; 3578 } 3579 3580 static int hns3_adjust_tqps_num(u8 num_tc, u32 new_tqp_num) 3581 { 3582 return (new_tqp_num / num_tc) * num_tc; 3583 } 3584 3585 int hns3_set_channels(struct net_device *netdev, 3586 struct ethtool_channels *ch) 3587 { 3588 struct hns3_nic_priv *priv = netdev_priv(netdev); 3589 struct hnae3_handle *h = hns3_get_handle(netdev); 3590 struct hnae3_knic_private_info *kinfo = &h->kinfo; 3591 struct hns3_enet_coalesce tx_coal, rx_coal; 3592 bool if_running = netif_running(netdev); 3593 u32 new_tqp_num = ch->combined_count; 3594 u16 org_tqp_num; 3595 int ret; 3596 3597 if (ch->rx_count || ch->tx_count) 3598 return -EINVAL; 3599 3600 if (new_tqp_num > hns3_get_max_available_channels(h) || 3601 new_tqp_num < kinfo->num_tc) { 3602 dev_err(&netdev->dev, 3603 "Change tqps fail, the tqp range is from %d to %d", 3604 kinfo->num_tc, 3605 hns3_get_max_available_channels(h)); 3606 return -EINVAL; 3607 } 3608 3609 new_tqp_num = hns3_adjust_tqps_num(kinfo->num_tc, new_tqp_num); 3610 if (kinfo->num_tqps == new_tqp_num) 3611 return 0; 3612 3613 if (if_running) 3614 hns3_nic_net_stop(netdev); 3615 3616 ret = hns3_nic_uninit_vector_data(priv); 3617 if (ret) { 3618 dev_err(&netdev->dev, 3619 "Unbind vector with tqp fail, nothing is changed"); 3620 goto open_netdev; 3621 } 3622 3623 /* Changing the tqp num may also change the vector num, 3624 * ethtool only support setting and querying one coal 3625 * configuation for now, so save the vector 0' coal 3626 * configuation here in order to restore it. 3627 */ 3628 memcpy(&tx_coal, &priv->tqp_vector[0].tx_group.coal, 3629 sizeof(struct hns3_enet_coalesce)); 3630 memcpy(&rx_coal, &priv->tqp_vector[0].rx_group.coal, 3631 sizeof(struct hns3_enet_coalesce)); 3632 3633 hns3_nic_dealloc_vector_data(priv); 3634 3635 hns3_uninit_all_ring(priv); 3636 hns3_put_ring_config(priv); 3637 3638 org_tqp_num = h->kinfo.num_tqps; 3639 ret = hns3_modify_tqp_num(netdev, new_tqp_num, &tx_coal, &rx_coal); 3640 if (ret) { 3641 ret = hns3_modify_tqp_num(netdev, org_tqp_num, 3642 &tx_coal, &rx_coal); 3643 if (ret) { 3644 /* If revert to old tqp failed, fatal error occurred */ 3645 dev_err(&netdev->dev, 3646 "Revert to old tqp num fail, ret=%d", ret); 3647 return ret; 3648 } 3649 dev_info(&netdev->dev, 3650 "Change tqp num fail, Revert to old tqp num"); 3651 } 3652 3653 open_netdev: 3654 if (if_running) 3655 hns3_nic_net_open(netdev); 3656 3657 return ret; 3658 } 3659 3660 static const struct hnae3_client_ops client_ops = { 3661 .init_instance = hns3_client_init, 3662 .uninit_instance = hns3_client_uninit, 3663 .link_status_change = hns3_link_status_change, 3664 .setup_tc = hns3_client_setup_tc, 3665 .reset_notify = hns3_reset_notify, 3666 }; 3667 3668 /* hns3_init_module - Driver registration routine 3669 * hns3_init_module is the first routine called when the driver is 3670 * loaded. All it does is register with the PCI subsystem. 3671 */ 3672 static int __init hns3_init_module(void) 3673 { 3674 int ret; 3675 3676 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 3677 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 3678 3679 client.type = HNAE3_CLIENT_KNIC; 3680 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s", 3681 hns3_driver_name); 3682 3683 client.ops = &client_ops; 3684 3685 INIT_LIST_HEAD(&client.node); 3686 3687 ret = hnae3_register_client(&client); 3688 if (ret) 3689 return ret; 3690 3691 ret = pci_register_driver(&hns3_driver); 3692 if (ret) 3693 hnae3_unregister_client(&client); 3694 3695 return ret; 3696 } 3697 module_init(hns3_init_module); 3698 3699 /* hns3_exit_module - Driver exit cleanup routine 3700 * hns3_exit_module is called just before the driver is removed 3701 * from memory. 3702 */ 3703 static void __exit hns3_exit_module(void) 3704 { 3705 pci_unregister_driver(&hns3_driver); 3706 hnae3_unregister_client(&client); 3707 } 3708 module_exit(hns3_exit_module); 3709 3710 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 3711 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3712 MODULE_LICENSE("GPL"); 3713 MODULE_ALIAS("pci:hns-nic"); 3714 MODULE_VERSION(HNS3_MOD_VERSION); 3715