1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (c) 2018-2019 Hisilicon Limited. */ 3 4 #include <linux/debugfs.h> 5 #include <linux/device.h> 6 #include <linux/string_choices.h> 7 8 #include "hnae3.h" 9 #include "hns3_debugfs.h" 10 #include "hns3_enet.h" 11 12 static struct dentry *hns3_dbgfs_root; 13 14 static struct hns3_dbg_dentry_info hns3_dbg_dentry[] = { 15 { 16 .name = "tm" 17 }, 18 { 19 .name = "tx_bd_info" 20 }, 21 { 22 .name = "rx_bd_info" 23 }, 24 { 25 .name = "mac_list" 26 }, 27 { 28 .name = "reg" 29 }, 30 { 31 .name = "queue" 32 }, 33 { 34 .name = "fd" 35 }, 36 /* keep common at the bottom and add new directory above */ 37 { 38 .name = "common" 39 }, 40 }; 41 42 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd); 43 static int hns3_dbg_common_file_init(struct hnae3_handle *handle, u32 cmd); 44 45 static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = { 46 { 47 .name = "tm_nodes", 48 .cmd = HNAE3_DBG_CMD_TM_NODES, 49 .dentry = HNS3_DBG_DENTRY_TM, 50 .buf_len = HNS3_DBG_READ_LEN, 51 .init = hns3_dbg_common_file_init, 52 }, 53 { 54 .name = "tm_priority", 55 .cmd = HNAE3_DBG_CMD_TM_PRI, 56 .dentry = HNS3_DBG_DENTRY_TM, 57 .buf_len = HNS3_DBG_READ_LEN, 58 .init = hns3_dbg_common_file_init, 59 }, 60 { 61 .name = "tm_qset", 62 .cmd = HNAE3_DBG_CMD_TM_QSET, 63 .dentry = HNS3_DBG_DENTRY_TM, 64 .buf_len = HNS3_DBG_READ_LEN_1MB, 65 .init = hns3_dbg_common_file_init, 66 }, 67 { 68 .name = "tm_map", 69 .cmd = HNAE3_DBG_CMD_TM_MAP, 70 .dentry = HNS3_DBG_DENTRY_TM, 71 .buf_len = HNS3_DBG_READ_LEN_1MB, 72 .init = hns3_dbg_common_file_init, 73 }, 74 { 75 .name = "tm_pg", 76 .cmd = HNAE3_DBG_CMD_TM_PG, 77 .dentry = HNS3_DBG_DENTRY_TM, 78 .buf_len = HNS3_DBG_READ_LEN, 79 .init = hns3_dbg_common_file_init, 80 }, 81 { 82 .name = "tm_port", 83 .cmd = HNAE3_DBG_CMD_TM_PORT, 84 .dentry = HNS3_DBG_DENTRY_TM, 85 .buf_len = HNS3_DBG_READ_LEN, 86 .init = hns3_dbg_common_file_init, 87 }, 88 { 89 .name = "tc_sch_info", 90 .cmd = HNAE3_DBG_CMD_TC_SCH_INFO, 91 .dentry = HNS3_DBG_DENTRY_TM, 92 .buf_len = HNS3_DBG_READ_LEN, 93 .init = hns3_dbg_common_file_init, 94 }, 95 { 96 .name = "qos_pause_cfg", 97 .cmd = HNAE3_DBG_CMD_QOS_PAUSE_CFG, 98 .dentry = HNS3_DBG_DENTRY_TM, 99 .buf_len = HNS3_DBG_READ_LEN, 100 .init = hns3_dbg_common_file_init, 101 }, 102 { 103 .name = "qos_pri_map", 104 .cmd = HNAE3_DBG_CMD_QOS_PRI_MAP, 105 .dentry = HNS3_DBG_DENTRY_TM, 106 .buf_len = HNS3_DBG_READ_LEN, 107 .init = hns3_dbg_common_file_init, 108 }, 109 { 110 .name = "qos_dscp_map", 111 .cmd = HNAE3_DBG_CMD_QOS_DSCP_MAP, 112 .dentry = HNS3_DBG_DENTRY_TM, 113 .buf_len = HNS3_DBG_READ_LEN, 114 .init = hns3_dbg_common_file_init, 115 }, 116 { 117 .name = "qos_buf_cfg", 118 .cmd = HNAE3_DBG_CMD_QOS_BUF_CFG, 119 .dentry = HNS3_DBG_DENTRY_TM, 120 .buf_len = HNS3_DBG_READ_LEN, 121 .init = hns3_dbg_common_file_init, 122 }, 123 { 124 .name = "dev_info", 125 .cmd = HNAE3_DBG_CMD_DEV_INFO, 126 .dentry = HNS3_DBG_DENTRY_COMMON, 127 .buf_len = HNS3_DBG_READ_LEN, 128 .init = hns3_dbg_common_file_init, 129 }, 130 { 131 .name = "tx_bd_queue", 132 .cmd = HNAE3_DBG_CMD_TX_BD, 133 .dentry = HNS3_DBG_DENTRY_TX_BD, 134 .buf_len = HNS3_DBG_READ_LEN_5MB, 135 .init = hns3_dbg_bd_file_init, 136 }, 137 { 138 .name = "rx_bd_queue", 139 .cmd = HNAE3_DBG_CMD_RX_BD, 140 .dentry = HNS3_DBG_DENTRY_RX_BD, 141 .buf_len = HNS3_DBG_READ_LEN_4MB, 142 .init = hns3_dbg_bd_file_init, 143 }, 144 { 145 .name = "uc", 146 .cmd = HNAE3_DBG_CMD_MAC_UC, 147 .dentry = HNS3_DBG_DENTRY_MAC, 148 .buf_len = HNS3_DBG_READ_LEN_128KB, 149 .init = hns3_dbg_common_file_init, 150 }, 151 { 152 .name = "mc", 153 .cmd = HNAE3_DBG_CMD_MAC_MC, 154 .dentry = HNS3_DBG_DENTRY_MAC, 155 .buf_len = HNS3_DBG_READ_LEN, 156 .init = hns3_dbg_common_file_init, 157 }, 158 { 159 .name = "mng_tbl", 160 .cmd = HNAE3_DBG_CMD_MNG_TBL, 161 .dentry = HNS3_DBG_DENTRY_COMMON, 162 .buf_len = HNS3_DBG_READ_LEN, 163 .init = hns3_dbg_common_file_init, 164 }, 165 { 166 .name = "loopback", 167 .cmd = HNAE3_DBG_CMD_LOOPBACK, 168 .dentry = HNS3_DBG_DENTRY_COMMON, 169 .buf_len = HNS3_DBG_READ_LEN, 170 .init = hns3_dbg_common_file_init, 171 }, 172 { 173 .name = "interrupt_info", 174 .cmd = HNAE3_DBG_CMD_INTERRUPT_INFO, 175 .dentry = HNS3_DBG_DENTRY_COMMON, 176 .buf_len = HNS3_DBG_READ_LEN, 177 .init = hns3_dbg_common_file_init, 178 }, 179 { 180 .name = "reset_info", 181 .cmd = HNAE3_DBG_CMD_RESET_INFO, 182 .dentry = HNS3_DBG_DENTRY_COMMON, 183 .buf_len = HNS3_DBG_READ_LEN, 184 .init = hns3_dbg_common_file_init, 185 }, 186 { 187 .name = "imp_info", 188 .cmd = HNAE3_DBG_CMD_IMP_INFO, 189 .dentry = HNS3_DBG_DENTRY_COMMON, 190 .buf_len = HNS3_DBG_READ_LEN, 191 .init = hns3_dbg_common_file_init, 192 }, 193 { 194 .name = "ncl_config", 195 .cmd = HNAE3_DBG_CMD_NCL_CONFIG, 196 .dentry = HNS3_DBG_DENTRY_COMMON, 197 .buf_len = HNS3_DBG_READ_LEN_128KB, 198 .init = hns3_dbg_common_file_init, 199 }, 200 { 201 .name = "mac_tnl_status", 202 .cmd = HNAE3_DBG_CMD_MAC_TNL_STATUS, 203 .dentry = HNS3_DBG_DENTRY_COMMON, 204 .buf_len = HNS3_DBG_READ_LEN, 205 .init = hns3_dbg_common_file_init, 206 }, 207 { 208 .name = "bios_common", 209 .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON, 210 .dentry = HNS3_DBG_DENTRY_REG, 211 .buf_len = HNS3_DBG_READ_LEN, 212 .init = hns3_dbg_common_file_init, 213 }, 214 { 215 .name = "ssu", 216 .cmd = HNAE3_DBG_CMD_REG_SSU, 217 .dentry = HNS3_DBG_DENTRY_REG, 218 .buf_len = HNS3_DBG_READ_LEN, 219 .init = hns3_dbg_common_file_init, 220 }, 221 { 222 .name = "igu_egu", 223 .cmd = HNAE3_DBG_CMD_REG_IGU_EGU, 224 .dentry = HNS3_DBG_DENTRY_REG, 225 .buf_len = HNS3_DBG_READ_LEN, 226 .init = hns3_dbg_common_file_init, 227 }, 228 { 229 .name = "rpu", 230 .cmd = HNAE3_DBG_CMD_REG_RPU, 231 .dentry = HNS3_DBG_DENTRY_REG, 232 .buf_len = HNS3_DBG_READ_LEN, 233 .init = hns3_dbg_common_file_init, 234 }, 235 { 236 .name = "ncsi", 237 .cmd = HNAE3_DBG_CMD_REG_NCSI, 238 .dentry = HNS3_DBG_DENTRY_REG, 239 .buf_len = HNS3_DBG_READ_LEN, 240 .init = hns3_dbg_common_file_init, 241 }, 242 { 243 .name = "rtc", 244 .cmd = HNAE3_DBG_CMD_REG_RTC, 245 .dentry = HNS3_DBG_DENTRY_REG, 246 .buf_len = HNS3_DBG_READ_LEN, 247 .init = hns3_dbg_common_file_init, 248 }, 249 { 250 .name = "ppp", 251 .cmd = HNAE3_DBG_CMD_REG_PPP, 252 .dentry = HNS3_DBG_DENTRY_REG, 253 .buf_len = HNS3_DBG_READ_LEN, 254 .init = hns3_dbg_common_file_init, 255 }, 256 { 257 .name = "rcb", 258 .cmd = HNAE3_DBG_CMD_REG_RCB, 259 .dentry = HNS3_DBG_DENTRY_REG, 260 .buf_len = HNS3_DBG_READ_LEN, 261 .init = hns3_dbg_common_file_init, 262 }, 263 { 264 .name = "tqp", 265 .cmd = HNAE3_DBG_CMD_REG_TQP, 266 .dentry = HNS3_DBG_DENTRY_REG, 267 .buf_len = HNS3_DBG_READ_LEN_128KB, 268 .init = hns3_dbg_common_file_init, 269 }, 270 { 271 .name = "mac", 272 .cmd = HNAE3_DBG_CMD_REG_MAC, 273 .dentry = HNS3_DBG_DENTRY_REG, 274 .buf_len = HNS3_DBG_READ_LEN, 275 .init = hns3_dbg_common_file_init, 276 }, 277 { 278 .name = "dcb", 279 .cmd = HNAE3_DBG_CMD_REG_DCB, 280 .dentry = HNS3_DBG_DENTRY_REG, 281 .buf_len = HNS3_DBG_READ_LEN, 282 .init = hns3_dbg_common_file_init, 283 }, 284 { 285 .name = "queue_map", 286 .cmd = HNAE3_DBG_CMD_QUEUE_MAP, 287 .dentry = HNS3_DBG_DENTRY_QUEUE, 288 .buf_len = HNS3_DBG_READ_LEN, 289 .init = hns3_dbg_common_file_init, 290 }, 291 { 292 .name = "rx_queue_info", 293 .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO, 294 .dentry = HNS3_DBG_DENTRY_QUEUE, 295 .buf_len = HNS3_DBG_READ_LEN_1MB, 296 .init = hns3_dbg_common_file_init, 297 }, 298 { 299 .name = "tx_queue_info", 300 .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO, 301 .dentry = HNS3_DBG_DENTRY_QUEUE, 302 .buf_len = HNS3_DBG_READ_LEN_1MB, 303 .init = hns3_dbg_common_file_init, 304 }, 305 { 306 .name = "fd_tcam", 307 .cmd = HNAE3_DBG_CMD_FD_TCAM, 308 .dentry = HNS3_DBG_DENTRY_FD, 309 .buf_len = HNS3_DBG_READ_LEN_1MB, 310 .init = hns3_dbg_common_file_init, 311 }, 312 { 313 .name = "service_task_info", 314 .cmd = HNAE3_DBG_CMD_SERV_INFO, 315 .dentry = HNS3_DBG_DENTRY_COMMON, 316 .buf_len = HNS3_DBG_READ_LEN, 317 .init = hns3_dbg_common_file_init, 318 }, 319 { 320 .name = "vlan_config", 321 .cmd = HNAE3_DBG_CMD_VLAN_CONFIG, 322 .dentry = HNS3_DBG_DENTRY_COMMON, 323 .buf_len = HNS3_DBG_READ_LEN, 324 .init = hns3_dbg_common_file_init, 325 }, 326 { 327 .name = "ptp_info", 328 .cmd = HNAE3_DBG_CMD_PTP_INFO, 329 .dentry = HNS3_DBG_DENTRY_COMMON, 330 .buf_len = HNS3_DBG_READ_LEN, 331 .init = hns3_dbg_common_file_init, 332 }, 333 { 334 .name = "fd_counter", 335 .cmd = HNAE3_DBG_CMD_FD_COUNTER, 336 .dentry = HNS3_DBG_DENTRY_FD, 337 .buf_len = HNS3_DBG_READ_LEN, 338 .init = hns3_dbg_common_file_init, 339 }, 340 { 341 .name = "umv_info", 342 .cmd = HNAE3_DBG_CMD_UMV_INFO, 343 .dentry = HNS3_DBG_DENTRY_COMMON, 344 .buf_len = HNS3_DBG_READ_LEN, 345 .init = hns3_dbg_common_file_init, 346 }, 347 { 348 .name = "page_pool_info", 349 .cmd = HNAE3_DBG_CMD_PAGE_POOL_INFO, 350 .dentry = HNS3_DBG_DENTRY_COMMON, 351 .buf_len = HNS3_DBG_READ_LEN, 352 .init = hns3_dbg_common_file_init, 353 }, 354 { 355 .name = "coalesce_info", 356 .cmd = HNAE3_DBG_CMD_COAL_INFO, 357 .dentry = HNS3_DBG_DENTRY_COMMON, 358 .buf_len = HNS3_DBG_READ_LEN_1MB, 359 .init = hns3_dbg_common_file_init, 360 }, 361 }; 362 363 static struct hns3_dbg_cap_info hns3_dbg_cap[] = { 364 { 365 .name = "support FD", 366 .cap_bit = HNAE3_DEV_SUPPORT_FD_B, 367 }, { 368 .name = "support GRO", 369 .cap_bit = HNAE3_DEV_SUPPORT_GRO_B, 370 }, { 371 .name = "support FEC", 372 .cap_bit = HNAE3_DEV_SUPPORT_FEC_B, 373 }, { 374 .name = "support UDP GSO", 375 .cap_bit = HNAE3_DEV_SUPPORT_UDP_GSO_B, 376 }, { 377 .name = "support PTP", 378 .cap_bit = HNAE3_DEV_SUPPORT_PTP_B, 379 }, { 380 .name = "support INT QL", 381 .cap_bit = HNAE3_DEV_SUPPORT_INT_QL_B, 382 }, { 383 .name = "support HW TX csum", 384 .cap_bit = HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, 385 }, { 386 .name = "support UDP tunnel csum", 387 .cap_bit = HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, 388 }, { 389 .name = "support TX push", 390 .cap_bit = HNAE3_DEV_SUPPORT_TX_PUSH_B, 391 }, { 392 .name = "support imp-controlled PHY", 393 .cap_bit = HNAE3_DEV_SUPPORT_PHY_IMP_B, 394 }, { 395 .name = "support imp-controlled RAS", 396 .cap_bit = HNAE3_DEV_SUPPORT_RAS_IMP_B, 397 }, { 398 .name = "support rxd advanced layout", 399 .cap_bit = HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, 400 }, { 401 .name = "support port vlan bypass", 402 .cap_bit = HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, 403 }, { 404 .name = "support modify vlan filter state", 405 .cap_bit = HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, 406 }, { 407 .name = "support FEC statistics", 408 .cap_bit = HNAE3_DEV_SUPPORT_FEC_STATS_B, 409 }, { 410 .name = "support lane num", 411 .cap_bit = HNAE3_DEV_SUPPORT_LANE_NUM_B, 412 }, { 413 .name = "support wake on lan", 414 .cap_bit = HNAE3_DEV_SUPPORT_WOL_B, 415 }, { 416 .name = "support tm flush", 417 .cap_bit = HNAE3_DEV_SUPPORT_TM_FLUSH_B, 418 }, { 419 .name = "support vf fault detect", 420 .cap_bit = HNAE3_DEV_SUPPORT_VF_FAULT_B, 421 } 422 }; 423 424 static const struct hns3_dbg_item coal_info_items[] = { 425 { "VEC_ID", 2 }, 426 { "ALGO_STATE", 2 }, 427 { "PROFILE_ID", 2 }, 428 { "CQE_MODE", 2 }, 429 { "TUNE_STATE", 2 }, 430 { "STEPS_LEFT", 2 }, 431 { "STEPS_RIGHT", 2 }, 432 { "TIRED", 2 }, 433 { "SW_GL", 2 }, 434 { "SW_QL", 2 }, 435 { "HW_GL", 2 }, 436 { "HW_QL", 2 }, 437 }; 438 439 static const char * const dim_cqe_mode_str[] = { "EQE", "CQE" }; 440 static const char * const dim_state_str[] = { "START", "IN_PROG", "APPLY" }; 441 static const char * const 442 dim_tune_stat_str[] = { "ON_TOP", "TIRED", "RIGHT", "LEFT" }; 443 444 static void hns3_dbg_fill_content(char *content, u16 len, 445 const struct hns3_dbg_item *items, 446 const char **result, u16 size) 447 { 448 #define HNS3_DBG_LINE_END_LEN 2 449 char *pos = content; 450 u16 item_len; 451 u16 i; 452 453 if (!len) { 454 return; 455 } else if (len <= HNS3_DBG_LINE_END_LEN) { 456 *pos++ = '\0'; 457 return; 458 } 459 460 memset(content, ' ', len); 461 len -= HNS3_DBG_LINE_END_LEN; 462 463 for (i = 0; i < size; i++) { 464 item_len = strlen(items[i].name) + items[i].interval; 465 if (len < item_len) 466 break; 467 468 if (result) { 469 if (item_len < strlen(result[i])) 470 break; 471 memcpy(pos, result[i], strlen(result[i])); 472 } else { 473 memcpy(pos, items[i].name, strlen(items[i].name)); 474 } 475 pos += item_len; 476 len -= item_len; 477 } 478 *pos++ = '\n'; 479 *pos++ = '\0'; 480 } 481 482 static void hns3_get_coal_info(struct hns3_enet_tqp_vector *tqp_vector, 483 char **result, int i, bool is_tx) 484 { 485 unsigned int gl_offset, ql_offset; 486 struct hns3_enet_coalesce *coal; 487 unsigned int reg_val; 488 unsigned int j = 0; 489 struct dim *dim; 490 bool ql_enable; 491 492 if (is_tx) { 493 coal = &tqp_vector->tx_group.coal; 494 dim = &tqp_vector->tx_group.dim; 495 gl_offset = HNS3_VECTOR_GL1_OFFSET; 496 ql_offset = HNS3_VECTOR_TX_QL_OFFSET; 497 ql_enable = tqp_vector->tx_group.coal.ql_enable; 498 } else { 499 coal = &tqp_vector->rx_group.coal; 500 dim = &tqp_vector->rx_group.dim; 501 gl_offset = HNS3_VECTOR_GL0_OFFSET; 502 ql_offset = HNS3_VECTOR_RX_QL_OFFSET; 503 ql_enable = tqp_vector->rx_group.coal.ql_enable; 504 } 505 506 sprintf(result[j++], "%d", i); 507 sprintf(result[j++], "%s", dim->state < ARRAY_SIZE(dim_state_str) ? 508 dim_state_str[dim->state] : "unknown"); 509 sprintf(result[j++], "%u", dim->profile_ix); 510 sprintf(result[j++], "%s", dim->mode < ARRAY_SIZE(dim_cqe_mode_str) ? 511 dim_cqe_mode_str[dim->mode] : "unknown"); 512 sprintf(result[j++], "%s", 513 dim->tune_state < ARRAY_SIZE(dim_tune_stat_str) ? 514 dim_tune_stat_str[dim->tune_state] : "unknown"); 515 sprintf(result[j++], "%u", dim->steps_left); 516 sprintf(result[j++], "%u", dim->steps_right); 517 sprintf(result[j++], "%u", dim->tired); 518 sprintf(result[j++], "%u", coal->int_gl); 519 sprintf(result[j++], "%u", coal->int_ql); 520 reg_val = readl(tqp_vector->mask_addr + gl_offset) & 521 HNS3_VECTOR_GL_MASK; 522 sprintf(result[j++], "%u", reg_val); 523 if (ql_enable) { 524 reg_val = readl(tqp_vector->mask_addr + ql_offset) & 525 HNS3_VECTOR_QL_MASK; 526 sprintf(result[j++], "%u", reg_val); 527 } else { 528 sprintf(result[j++], "NA"); 529 } 530 } 531 532 static void hns3_dump_coal_info(struct hnae3_handle *h, char *buf, int len, 533 int *pos, bool is_tx) 534 { 535 char data_str[ARRAY_SIZE(coal_info_items)][HNS3_DBG_DATA_STR_LEN]; 536 char *result[ARRAY_SIZE(coal_info_items)]; 537 struct hns3_enet_tqp_vector *tqp_vector; 538 struct hns3_nic_priv *priv = h->priv; 539 char content[HNS3_DBG_INFO_LEN]; 540 unsigned int i; 541 542 for (i = 0; i < ARRAY_SIZE(coal_info_items); i++) 543 result[i] = &data_str[i][0]; 544 545 *pos += scnprintf(buf + *pos, len - *pos, 546 "%s interrupt coalesce info:\n", 547 is_tx ? "tx" : "rx"); 548 hns3_dbg_fill_content(content, sizeof(content), coal_info_items, 549 NULL, ARRAY_SIZE(coal_info_items)); 550 *pos += scnprintf(buf + *pos, len - *pos, "%s", content); 551 552 for (i = 0; i < priv->vector_num; i++) { 553 tqp_vector = &priv->tqp_vector[i]; 554 hns3_get_coal_info(tqp_vector, result, i, is_tx); 555 hns3_dbg_fill_content(content, sizeof(content), coal_info_items, 556 (const char **)result, 557 ARRAY_SIZE(coal_info_items)); 558 *pos += scnprintf(buf + *pos, len - *pos, "%s", content); 559 } 560 } 561 562 static int hns3_dbg_coal_info(struct hnae3_handle *h, char *buf, int len) 563 { 564 int pos = 0; 565 566 hns3_dump_coal_info(h, buf, len, &pos, true); 567 pos += scnprintf(buf + pos, len - pos, "\n"); 568 hns3_dump_coal_info(h, buf, len, &pos, false); 569 570 return 0; 571 } 572 573 static const struct hns3_dbg_item tx_spare_info_items[] = { 574 { "QUEUE_ID", 2 }, 575 { "COPYBREAK", 2 }, 576 { "LEN", 7 }, 577 { "NTU", 4 }, 578 { "NTC", 4 }, 579 { "LTC", 4 }, 580 { "DMA", 17 }, 581 }; 582 583 static void hns3_dbg_tx_spare_info(struct hns3_enet_ring *ring, char *buf, 584 int len, u32 ring_num, int *pos) 585 { 586 char data_str[ARRAY_SIZE(tx_spare_info_items)][HNS3_DBG_DATA_STR_LEN]; 587 struct hns3_tx_spare *tx_spare = ring->tx_spare; 588 char *result[ARRAY_SIZE(tx_spare_info_items)]; 589 char content[HNS3_DBG_INFO_LEN]; 590 u32 i, j; 591 592 if (!tx_spare) { 593 *pos += scnprintf(buf + *pos, len - *pos, 594 "tx spare buffer is not enabled\n"); 595 return; 596 } 597 598 for (i = 0; i < ARRAY_SIZE(tx_spare_info_items); i++) 599 result[i] = &data_str[i][0]; 600 601 *pos += scnprintf(buf + *pos, len - *pos, "tx spare buffer info\n"); 602 hns3_dbg_fill_content(content, sizeof(content), tx_spare_info_items, 603 NULL, ARRAY_SIZE(tx_spare_info_items)); 604 *pos += scnprintf(buf + *pos, len - *pos, "%s", content); 605 606 for (i = 0; i < ring_num; i++) { 607 j = 0; 608 sprintf(result[j++], "%u", i); 609 sprintf(result[j++], "%u", ring->tx_copybreak); 610 sprintf(result[j++], "%u", tx_spare->len); 611 sprintf(result[j++], "%u", tx_spare->next_to_use); 612 sprintf(result[j++], "%u", tx_spare->next_to_clean); 613 sprintf(result[j++], "%u", tx_spare->last_to_clean); 614 sprintf(result[j++], "%pad", &tx_spare->dma); 615 hns3_dbg_fill_content(content, sizeof(content), 616 tx_spare_info_items, 617 (const char **)result, 618 ARRAY_SIZE(tx_spare_info_items)); 619 *pos += scnprintf(buf + *pos, len - *pos, "%s", content); 620 } 621 } 622 623 static const struct hns3_dbg_item rx_queue_info_items[] = { 624 { "QUEUE_ID", 2 }, 625 { "BD_NUM", 2 }, 626 { "BD_LEN", 2 }, 627 { "TAIL", 2 }, 628 { "HEAD", 2 }, 629 { "FBDNUM", 2 }, 630 { "PKTNUM", 5 }, 631 { "COPYBREAK", 2 }, 632 { "RING_EN", 2 }, 633 { "RX_RING_EN", 2 }, 634 { "BASE_ADDR", 10 }, 635 }; 636 637 static void hns3_dump_rx_queue_info(struct hns3_enet_ring *ring, 638 struct hnae3_ae_dev *ae_dev, char **result, 639 u32 index) 640 { 641 u32 base_add_l, base_add_h; 642 u32 j = 0; 643 644 sprintf(result[j++], "%u", index); 645 646 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 647 HNS3_RING_RX_RING_BD_NUM_REG)); 648 649 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 650 HNS3_RING_RX_RING_BD_LEN_REG)); 651 652 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 653 HNS3_RING_RX_RING_TAIL_REG)); 654 655 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 656 HNS3_RING_RX_RING_HEAD_REG)); 657 658 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 659 HNS3_RING_RX_RING_FBDNUM_REG)); 660 661 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 662 HNS3_RING_RX_RING_PKTNUM_RECORD_REG)); 663 sprintf(result[j++], "%u", ring->rx_copybreak); 664 665 sprintf(result[j++], "%s", 666 str_on_off(readl_relaxed(ring->tqp->io_base + 667 HNS3_RING_EN_REG))); 668 669 if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev)) 670 sprintf(result[j++], "%s", 671 str_on_off(readl_relaxed(ring->tqp->io_base + 672 HNS3_RING_RX_EN_REG))); 673 else 674 sprintf(result[j++], "%s", "NA"); 675 676 base_add_h = readl_relaxed(ring->tqp->io_base + 677 HNS3_RING_RX_RING_BASEADDR_H_REG); 678 base_add_l = readl_relaxed(ring->tqp->io_base + 679 HNS3_RING_RX_RING_BASEADDR_L_REG); 680 sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l); 681 } 682 683 static int hns3_dbg_rx_queue_info(struct hnae3_handle *h, 684 char *buf, int len) 685 { 686 char data_str[ARRAY_SIZE(rx_queue_info_items)][HNS3_DBG_DATA_STR_LEN]; 687 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 688 char *result[ARRAY_SIZE(rx_queue_info_items)]; 689 struct hns3_nic_priv *priv = h->priv; 690 char content[HNS3_DBG_INFO_LEN]; 691 struct hns3_enet_ring *ring; 692 int pos = 0; 693 u32 i; 694 695 if (!priv->ring) { 696 dev_err(&h->pdev->dev, "priv->ring is NULL\n"); 697 return -EFAULT; 698 } 699 700 for (i = 0; i < ARRAY_SIZE(rx_queue_info_items); i++) 701 result[i] = &data_str[i][0]; 702 703 hns3_dbg_fill_content(content, sizeof(content), rx_queue_info_items, 704 NULL, ARRAY_SIZE(rx_queue_info_items)); 705 pos += scnprintf(buf + pos, len - pos, "%s", content); 706 for (i = 0; i < h->kinfo.num_tqps; i++) { 707 /* Each cycle needs to determine whether the instance is reset, 708 * to prevent reference to invalid memory. And need to ensure 709 * that the following code is executed within 100ms. 710 */ 711 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 712 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 713 return -EPERM; 714 715 ring = &priv->ring[(u32)(i + h->kinfo.num_tqps)]; 716 hns3_dump_rx_queue_info(ring, ae_dev, result, i); 717 hns3_dbg_fill_content(content, sizeof(content), 718 rx_queue_info_items, 719 (const char **)result, 720 ARRAY_SIZE(rx_queue_info_items)); 721 pos += scnprintf(buf + pos, len - pos, "%s", content); 722 } 723 724 return 0; 725 } 726 727 static const struct hns3_dbg_item tx_queue_info_items[] = { 728 { "QUEUE_ID", 2 }, 729 { "BD_NUM", 2 }, 730 { "TC", 2 }, 731 { "TAIL", 2 }, 732 { "HEAD", 2 }, 733 { "FBDNUM", 2 }, 734 { "OFFSET", 2 }, 735 { "PKTNUM", 5 }, 736 { "RING_EN", 2 }, 737 { "TX_RING_EN", 2 }, 738 { "BASE_ADDR", 10 }, 739 }; 740 741 static void hns3_dump_tx_queue_info(struct hns3_enet_ring *ring, 742 struct hnae3_ae_dev *ae_dev, char **result, 743 u32 index) 744 { 745 u32 base_add_l, base_add_h; 746 u32 j = 0; 747 748 sprintf(result[j++], "%u", index); 749 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 750 HNS3_RING_TX_RING_BD_NUM_REG)); 751 752 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 753 HNS3_RING_TX_RING_TC_REG)); 754 755 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 756 HNS3_RING_TX_RING_TAIL_REG)); 757 758 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 759 HNS3_RING_TX_RING_HEAD_REG)); 760 761 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 762 HNS3_RING_TX_RING_FBDNUM_REG)); 763 764 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 765 HNS3_RING_TX_RING_OFFSET_REG)); 766 767 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 768 HNS3_RING_TX_RING_PKTNUM_RECORD_REG)); 769 770 sprintf(result[j++], "%s", 771 str_on_off(readl_relaxed(ring->tqp->io_base + 772 HNS3_RING_EN_REG))); 773 774 if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev)) 775 sprintf(result[j++], "%s", 776 str_on_off(readl_relaxed(ring->tqp->io_base + 777 HNS3_RING_TX_EN_REG))); 778 else 779 sprintf(result[j++], "%s", "NA"); 780 781 base_add_h = readl_relaxed(ring->tqp->io_base + 782 HNS3_RING_TX_RING_BASEADDR_H_REG); 783 base_add_l = readl_relaxed(ring->tqp->io_base + 784 HNS3_RING_TX_RING_BASEADDR_L_REG); 785 sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l); 786 } 787 788 static int hns3_dbg_tx_queue_info(struct hnae3_handle *h, 789 char *buf, int len) 790 { 791 char data_str[ARRAY_SIZE(tx_queue_info_items)][HNS3_DBG_DATA_STR_LEN]; 792 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 793 char *result[ARRAY_SIZE(tx_queue_info_items)]; 794 struct hns3_nic_priv *priv = h->priv; 795 char content[HNS3_DBG_INFO_LEN]; 796 struct hns3_enet_ring *ring; 797 int pos = 0; 798 u32 i; 799 800 if (!priv->ring) { 801 dev_err(&h->pdev->dev, "priv->ring is NULL\n"); 802 return -EFAULT; 803 } 804 805 for (i = 0; i < ARRAY_SIZE(tx_queue_info_items); i++) 806 result[i] = &data_str[i][0]; 807 808 hns3_dbg_fill_content(content, sizeof(content), tx_queue_info_items, 809 NULL, ARRAY_SIZE(tx_queue_info_items)); 810 pos += scnprintf(buf + pos, len - pos, "%s", content); 811 812 for (i = 0; i < h->kinfo.num_tqps; i++) { 813 /* Each cycle needs to determine whether the instance is reset, 814 * to prevent reference to invalid memory. And need to ensure 815 * that the following code is executed within 100ms. 816 */ 817 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 818 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 819 return -EPERM; 820 821 ring = &priv->ring[i]; 822 hns3_dump_tx_queue_info(ring, ae_dev, result, i); 823 hns3_dbg_fill_content(content, sizeof(content), 824 tx_queue_info_items, 825 (const char **)result, 826 ARRAY_SIZE(tx_queue_info_items)); 827 pos += scnprintf(buf + pos, len - pos, "%s", content); 828 } 829 830 hns3_dbg_tx_spare_info(ring, buf, len, h->kinfo.num_tqps, &pos); 831 832 return 0; 833 } 834 835 static const struct hns3_dbg_item queue_map_items[] = { 836 { "local_queue_id", 2 }, 837 { "global_queue_id", 2 }, 838 { "vector_id", 2 }, 839 }; 840 841 static int hns3_dbg_queue_map(struct hnae3_handle *h, char *buf, int len) 842 { 843 char data_str[ARRAY_SIZE(queue_map_items)][HNS3_DBG_DATA_STR_LEN]; 844 char *result[ARRAY_SIZE(queue_map_items)]; 845 struct hns3_nic_priv *priv = h->priv; 846 char content[HNS3_DBG_INFO_LEN]; 847 int pos = 0; 848 int j; 849 u32 i; 850 851 if (!h->ae_algo->ops->get_global_queue_id) 852 return -EOPNOTSUPP; 853 854 for (i = 0; i < ARRAY_SIZE(queue_map_items); i++) 855 result[i] = &data_str[i][0]; 856 857 hns3_dbg_fill_content(content, sizeof(content), queue_map_items, 858 NULL, ARRAY_SIZE(queue_map_items)); 859 pos += scnprintf(buf + pos, len - pos, "%s", content); 860 for (i = 0; i < h->kinfo.num_tqps; i++) { 861 if (!priv->ring || !priv->ring[i].tqp_vector) 862 continue; 863 j = 0; 864 sprintf(result[j++], "%u", i); 865 sprintf(result[j++], "%u", 866 h->ae_algo->ops->get_global_queue_id(h, i)); 867 sprintf(result[j++], "%d", 868 priv->ring[i].tqp_vector->vector_irq); 869 hns3_dbg_fill_content(content, sizeof(content), queue_map_items, 870 (const char **)result, 871 ARRAY_SIZE(queue_map_items)); 872 pos += scnprintf(buf + pos, len - pos, "%s", content); 873 } 874 875 return 0; 876 } 877 878 static const struct hns3_dbg_item rx_bd_info_items[] = { 879 { "BD_IDX", 3 }, 880 { "L234_INFO", 2 }, 881 { "PKT_LEN", 3 }, 882 { "SIZE", 4 }, 883 { "RSS_HASH", 4 }, 884 { "FD_ID", 2 }, 885 { "VLAN_TAG", 2 }, 886 { "O_DM_VLAN_ID_FB", 2 }, 887 { "OT_VLAN_TAG", 2 }, 888 { "BD_BASE_INFO", 2 }, 889 { "PTYPE", 2 }, 890 { "HW_CSUM", 2 }, 891 }; 892 893 static void hns3_dump_rx_bd_info(struct hns3_nic_priv *priv, 894 struct hns3_desc *desc, char **result, int idx) 895 { 896 unsigned int j = 0; 897 898 sprintf(result[j++], "%d", idx); 899 sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.l234_info)); 900 sprintf(result[j++], "%u", le16_to_cpu(desc->rx.pkt_len)); 901 sprintf(result[j++], "%u", le16_to_cpu(desc->rx.size)); 902 sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.rss_hash)); 903 sprintf(result[j++], "%u", le16_to_cpu(desc->rx.fd_id)); 904 sprintf(result[j++], "%u", le16_to_cpu(desc->rx.vlan_tag)); 905 sprintf(result[j++], "%u", le16_to_cpu(desc->rx.o_dm_vlan_id_fb)); 906 sprintf(result[j++], "%u", le16_to_cpu(desc->rx.ot_vlan_tag)); 907 sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.bd_base_info)); 908 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) { 909 u32 ol_info = le32_to_cpu(desc->rx.ol_info); 910 911 sprintf(result[j++], "%5lu", hnae3_get_field(ol_info, 912 HNS3_RXD_PTYPE_M, 913 HNS3_RXD_PTYPE_S)); 914 sprintf(result[j++], "%7u", le16_to_cpu(desc->csum)); 915 } else { 916 sprintf(result[j++], "NA"); 917 sprintf(result[j++], "NA"); 918 } 919 } 920 921 static int hns3_dbg_rx_bd_info(struct hns3_dbg_data *d, char *buf, int len) 922 { 923 char data_str[ARRAY_SIZE(rx_bd_info_items)][HNS3_DBG_DATA_STR_LEN]; 924 struct hns3_nic_priv *priv = d->handle->priv; 925 char *result[ARRAY_SIZE(rx_bd_info_items)]; 926 char content[HNS3_DBG_INFO_LEN]; 927 struct hns3_enet_ring *ring; 928 struct hns3_desc *desc; 929 unsigned int i; 930 int pos = 0; 931 932 if (d->qid >= d->handle->kinfo.num_tqps) { 933 dev_err(&d->handle->pdev->dev, 934 "queue%u is not in use\n", d->qid); 935 return -EINVAL; 936 } 937 938 for (i = 0; i < ARRAY_SIZE(rx_bd_info_items); i++) 939 result[i] = &data_str[i][0]; 940 941 pos += scnprintf(buf + pos, len - pos, 942 "Queue %u rx bd info:\n", d->qid); 943 hns3_dbg_fill_content(content, sizeof(content), rx_bd_info_items, 944 NULL, ARRAY_SIZE(rx_bd_info_items)); 945 pos += scnprintf(buf + pos, len - pos, "%s", content); 946 947 ring = &priv->ring[d->qid + d->handle->kinfo.num_tqps]; 948 for (i = 0; i < ring->desc_num; i++) { 949 desc = &ring->desc[i]; 950 951 hns3_dump_rx_bd_info(priv, desc, result, i); 952 hns3_dbg_fill_content(content, sizeof(content), 953 rx_bd_info_items, (const char **)result, 954 ARRAY_SIZE(rx_bd_info_items)); 955 pos += scnprintf(buf + pos, len - pos, "%s", content); 956 } 957 958 return 0; 959 } 960 961 static const struct hns3_dbg_item tx_bd_info_items[] = { 962 { "BD_IDX", 2 }, 963 { "ADDRESS", 13 }, 964 { "VLAN_TAG", 2 }, 965 { "SIZE", 2 }, 966 { "T_CS_VLAN_TSO", 2 }, 967 { "OT_VLAN_TAG", 3 }, 968 { "TV", 5 }, 969 { "OLT_VLAN_LEN", 2 }, 970 { "PAYLEN_OL4CS", 2 }, 971 { "BD_FE_SC_VLD", 2 }, 972 { "MSS_HW_CSUM", 0 }, 973 }; 974 975 static void hns3_dump_tx_bd_info(struct hns3_desc *desc, char **result, int idx) 976 { 977 unsigned int j = 0; 978 979 sprintf(result[j++], "%d", idx); 980 sprintf(result[j++], "%#llx", le64_to_cpu(desc->addr)); 981 sprintf(result[j++], "%u", le16_to_cpu(desc->tx.vlan_tag)); 982 sprintf(result[j++], "%u", le16_to_cpu(desc->tx.send_size)); 983 sprintf(result[j++], "%#x", 984 le32_to_cpu(desc->tx.type_cs_vlan_tso_len)); 985 sprintf(result[j++], "%u", le16_to_cpu(desc->tx.outer_vlan_tag)); 986 sprintf(result[j++], "%u", le16_to_cpu(desc->tx.tv)); 987 sprintf(result[j++], "%u", 988 le32_to_cpu(desc->tx.ol_type_vlan_len_msec)); 989 sprintf(result[j++], "%#x", le32_to_cpu(desc->tx.paylen_ol4cs)); 990 sprintf(result[j++], "%#x", le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri)); 991 sprintf(result[j++], "%u", le16_to_cpu(desc->tx.mss_hw_csum)); 992 } 993 994 static int hns3_dbg_tx_bd_info(struct hns3_dbg_data *d, char *buf, int len) 995 { 996 char data_str[ARRAY_SIZE(tx_bd_info_items)][HNS3_DBG_DATA_STR_LEN]; 997 struct hns3_nic_priv *priv = d->handle->priv; 998 char *result[ARRAY_SIZE(tx_bd_info_items)]; 999 char content[HNS3_DBG_INFO_LEN]; 1000 struct hns3_enet_ring *ring; 1001 struct hns3_desc *desc; 1002 unsigned int i; 1003 int pos = 0; 1004 1005 if (d->qid >= d->handle->kinfo.num_tqps) { 1006 dev_err(&d->handle->pdev->dev, 1007 "queue%u is not in use\n", d->qid); 1008 return -EINVAL; 1009 } 1010 1011 for (i = 0; i < ARRAY_SIZE(tx_bd_info_items); i++) 1012 result[i] = &data_str[i][0]; 1013 1014 pos += scnprintf(buf + pos, len - pos, 1015 "Queue %u tx bd info:\n", d->qid); 1016 hns3_dbg_fill_content(content, sizeof(content), tx_bd_info_items, 1017 NULL, ARRAY_SIZE(tx_bd_info_items)); 1018 pos += scnprintf(buf + pos, len - pos, "%s", content); 1019 1020 ring = &priv->ring[d->qid]; 1021 for (i = 0; i < ring->desc_num; i++) { 1022 desc = &ring->desc[i]; 1023 1024 hns3_dump_tx_bd_info(desc, result, i); 1025 hns3_dbg_fill_content(content, sizeof(content), 1026 tx_bd_info_items, (const char **)result, 1027 ARRAY_SIZE(tx_bd_info_items)); 1028 pos += scnprintf(buf + pos, len - pos, "%s", content); 1029 } 1030 1031 return 0; 1032 } 1033 1034 static void 1035 hns3_dbg_dev_caps(struct hnae3_handle *h, char *buf, int len, int *pos) 1036 { 1037 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 1038 unsigned long *caps = ae_dev->caps; 1039 u32 i, state; 1040 1041 *pos += scnprintf(buf + *pos, len - *pos, "dev capability:\n"); 1042 1043 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cap); i++) { 1044 state = test_bit(hns3_dbg_cap[i].cap_bit, caps); 1045 *pos += scnprintf(buf + *pos, len - *pos, "%s: %s\n", 1046 hns3_dbg_cap[i].name, str_yes_no(state)); 1047 } 1048 1049 *pos += scnprintf(buf + *pos, len - *pos, "\n"); 1050 } 1051 1052 static void 1053 hns3_dbg_dev_specs(struct hnae3_handle *h, char *buf, int len, int *pos) 1054 { 1055 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 1056 struct hnae3_dev_specs *dev_specs = &ae_dev->dev_specs; 1057 struct hnae3_knic_private_info *kinfo = &h->kinfo; 1058 struct net_device *dev = kinfo->netdev; 1059 1060 *pos += scnprintf(buf + *pos, len - *pos, "dev_spec:\n"); 1061 *pos += scnprintf(buf + *pos, len - *pos, "MAC entry num: %u\n", 1062 dev_specs->mac_entry_num); 1063 *pos += scnprintf(buf + *pos, len - *pos, "MNG entry num: %u\n", 1064 dev_specs->mng_entry_num); 1065 *pos += scnprintf(buf + *pos, len - *pos, "MAX non tso bd num: %u\n", 1066 dev_specs->max_non_tso_bd_num); 1067 *pos += scnprintf(buf + *pos, len - *pos, "RSS ind tbl size: %u\n", 1068 dev_specs->rss_ind_tbl_size); 1069 *pos += scnprintf(buf + *pos, len - *pos, "RSS key size: %u\n", 1070 dev_specs->rss_key_size); 1071 *pos += scnprintf(buf + *pos, len - *pos, "RSS size: %u\n", 1072 kinfo->rss_size); 1073 *pos += scnprintf(buf + *pos, len - *pos, "Allocated RSS size: %u\n", 1074 kinfo->req_rss_size); 1075 *pos += scnprintf(buf + *pos, len - *pos, 1076 "Task queue pairs numbers: %u\n", 1077 kinfo->num_tqps); 1078 *pos += scnprintf(buf + *pos, len - *pos, "RX buffer length: %u\n", 1079 kinfo->rx_buf_len); 1080 *pos += scnprintf(buf + *pos, len - *pos, "Desc num per TX queue: %u\n", 1081 kinfo->num_tx_desc); 1082 *pos += scnprintf(buf + *pos, len - *pos, "Desc num per RX queue: %u\n", 1083 kinfo->num_rx_desc); 1084 *pos += scnprintf(buf + *pos, len - *pos, 1085 "Total number of enabled TCs: %u\n", 1086 kinfo->tc_info.num_tc); 1087 *pos += scnprintf(buf + *pos, len - *pos, "MAX INT QL: %u\n", 1088 dev_specs->int_ql_max); 1089 *pos += scnprintf(buf + *pos, len - *pos, "MAX INT GL: %u\n", 1090 dev_specs->max_int_gl); 1091 *pos += scnprintf(buf + *pos, len - *pos, "MAX TM RATE: %u\n", 1092 dev_specs->max_tm_rate); 1093 *pos += scnprintf(buf + *pos, len - *pos, "MAX QSET number: %u\n", 1094 dev_specs->max_qset_num); 1095 *pos += scnprintf(buf + *pos, len - *pos, "umv size: %u\n", 1096 dev_specs->umv_size); 1097 *pos += scnprintf(buf + *pos, len - *pos, "mc mac size: %u\n", 1098 dev_specs->mc_mac_size); 1099 *pos += scnprintf(buf + *pos, len - *pos, "MAC statistics number: %u\n", 1100 dev_specs->mac_stats_num); 1101 *pos += scnprintf(buf + *pos, len - *pos, 1102 "TX timeout threshold: %d seconds\n", 1103 dev->watchdog_timeo / HZ); 1104 *pos += scnprintf(buf + *pos, len - *pos, "Hilink Version: %u\n", 1105 dev_specs->hilink_version); 1106 } 1107 1108 static int hns3_dbg_dev_info(struct hnae3_handle *h, char *buf, int len) 1109 { 1110 int pos = 0; 1111 1112 hns3_dbg_dev_caps(h, buf, len, &pos); 1113 1114 hns3_dbg_dev_specs(h, buf, len, &pos); 1115 1116 return 0; 1117 } 1118 1119 static const struct hns3_dbg_item page_pool_info_items[] = { 1120 { "QUEUE_ID", 2 }, 1121 { "ALLOCATE_CNT", 2 }, 1122 { "FREE_CNT", 6 }, 1123 { "POOL_SIZE(PAGE_NUM)", 2 }, 1124 { "ORDER", 2 }, 1125 { "NUMA_ID", 2 }, 1126 { "MAX_LEN", 2 }, 1127 }; 1128 1129 static void hns3_dump_page_pool_info(struct hns3_enet_ring *ring, 1130 char **result, u32 index) 1131 { 1132 u32 j = 0; 1133 1134 sprintf(result[j++], "%u", index); 1135 sprintf(result[j++], "%u", 1136 READ_ONCE(ring->page_pool->pages_state_hold_cnt)); 1137 sprintf(result[j++], "%d", 1138 atomic_read(&ring->page_pool->pages_state_release_cnt)); 1139 sprintf(result[j++], "%u", ring->page_pool->p.pool_size); 1140 sprintf(result[j++], "%u", ring->page_pool->p.order); 1141 sprintf(result[j++], "%d", ring->page_pool->p.nid); 1142 sprintf(result[j++], "%uK", ring->page_pool->p.max_len / 1024); 1143 } 1144 1145 static int 1146 hns3_dbg_page_pool_info(struct hnae3_handle *h, char *buf, int len) 1147 { 1148 char data_str[ARRAY_SIZE(page_pool_info_items)][HNS3_DBG_DATA_STR_LEN]; 1149 char *result[ARRAY_SIZE(page_pool_info_items)]; 1150 struct hns3_nic_priv *priv = h->priv; 1151 char content[HNS3_DBG_INFO_LEN]; 1152 struct hns3_enet_ring *ring; 1153 int pos = 0; 1154 u32 i; 1155 1156 if (!priv->ring) { 1157 dev_err(&h->pdev->dev, "priv->ring is NULL\n"); 1158 return -EFAULT; 1159 } 1160 1161 if (!priv->ring[h->kinfo.num_tqps].page_pool) { 1162 dev_err(&h->pdev->dev, "page pool is not initialized\n"); 1163 return -EFAULT; 1164 } 1165 1166 for (i = 0; i < ARRAY_SIZE(page_pool_info_items); i++) 1167 result[i] = &data_str[i][0]; 1168 1169 hns3_dbg_fill_content(content, sizeof(content), page_pool_info_items, 1170 NULL, ARRAY_SIZE(page_pool_info_items)); 1171 pos += scnprintf(buf + pos, len - pos, "%s", content); 1172 for (i = 0; i < h->kinfo.num_tqps; i++) { 1173 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 1174 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 1175 return -EPERM; 1176 ring = &priv->ring[(u32)(i + h->kinfo.num_tqps)]; 1177 hns3_dump_page_pool_info(ring, result, i); 1178 hns3_dbg_fill_content(content, sizeof(content), 1179 page_pool_info_items, 1180 (const char **)result, 1181 ARRAY_SIZE(page_pool_info_items)); 1182 pos += scnprintf(buf + pos, len - pos, "%s", content); 1183 } 1184 1185 return 0; 1186 } 1187 1188 static int hns3_dbg_get_cmd_index(struct hns3_dbg_data *dbg_data, u32 *index) 1189 { 1190 u32 i; 1191 1192 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) { 1193 if (hns3_dbg_cmd[i].cmd == dbg_data->cmd) { 1194 *index = i; 1195 return 0; 1196 } 1197 } 1198 1199 dev_err(&dbg_data->handle->pdev->dev, "unknown command(%d)\n", 1200 dbg_data->cmd); 1201 return -EINVAL; 1202 } 1203 1204 static const struct hns3_dbg_func hns3_dbg_cmd_func[] = { 1205 { 1206 .cmd = HNAE3_DBG_CMD_QUEUE_MAP, 1207 .dbg_dump = hns3_dbg_queue_map, 1208 }, 1209 { 1210 .cmd = HNAE3_DBG_CMD_DEV_INFO, 1211 .dbg_dump = hns3_dbg_dev_info, 1212 }, 1213 { 1214 .cmd = HNAE3_DBG_CMD_TX_BD, 1215 .dbg_dump_bd = hns3_dbg_tx_bd_info, 1216 }, 1217 { 1218 .cmd = HNAE3_DBG_CMD_RX_BD, 1219 .dbg_dump_bd = hns3_dbg_rx_bd_info, 1220 }, 1221 { 1222 .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO, 1223 .dbg_dump = hns3_dbg_rx_queue_info, 1224 }, 1225 { 1226 .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO, 1227 .dbg_dump = hns3_dbg_tx_queue_info, 1228 }, 1229 { 1230 .cmd = HNAE3_DBG_CMD_PAGE_POOL_INFO, 1231 .dbg_dump = hns3_dbg_page_pool_info, 1232 }, 1233 { 1234 .cmd = HNAE3_DBG_CMD_COAL_INFO, 1235 .dbg_dump = hns3_dbg_coal_info, 1236 }, 1237 }; 1238 1239 static int hns3_dbg_read_cmd(struct hns3_dbg_data *dbg_data, 1240 enum hnae3_dbg_cmd cmd, char *buf, int len) 1241 { 1242 const struct hnae3_ae_ops *ops = dbg_data->handle->ae_algo->ops; 1243 const struct hns3_dbg_func *cmd_func; 1244 u32 i; 1245 1246 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd_func); i++) { 1247 if (cmd == hns3_dbg_cmd_func[i].cmd) { 1248 cmd_func = &hns3_dbg_cmd_func[i]; 1249 if (cmd_func->dbg_dump) 1250 return cmd_func->dbg_dump(dbg_data->handle, buf, 1251 len); 1252 else 1253 return cmd_func->dbg_dump_bd(dbg_data, buf, 1254 len); 1255 } 1256 } 1257 1258 if (!ops->dbg_read_cmd) 1259 return -EOPNOTSUPP; 1260 1261 return ops->dbg_read_cmd(dbg_data->handle, cmd, buf, len); 1262 } 1263 1264 static ssize_t hns3_dbg_read(struct file *filp, char __user *buffer, 1265 size_t count, loff_t *ppos) 1266 { 1267 char *buf = filp->private_data; 1268 1269 return simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf)); 1270 } 1271 1272 static int hns3_dbg_open(struct inode *inode, struct file *filp) 1273 { 1274 struct hns3_dbg_data *dbg_data = inode->i_private; 1275 struct hnae3_handle *handle = dbg_data->handle; 1276 struct hns3_nic_priv *priv = handle->priv; 1277 u32 index; 1278 char *buf; 1279 int ret; 1280 1281 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 1282 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 1283 return -EBUSY; 1284 1285 ret = hns3_dbg_get_cmd_index(dbg_data, &index); 1286 if (ret) 1287 return ret; 1288 1289 buf = kvzalloc(hns3_dbg_cmd[index].buf_len, GFP_KERNEL); 1290 if (!buf) 1291 return -ENOMEM; 1292 1293 ret = hns3_dbg_read_cmd(dbg_data, hns3_dbg_cmd[index].cmd, 1294 buf, hns3_dbg_cmd[index].buf_len); 1295 if (ret) { 1296 kvfree(buf); 1297 return ret; 1298 } 1299 1300 filp->private_data = buf; 1301 return 0; 1302 } 1303 1304 static int hns3_dbg_release(struct inode *inode, struct file *filp) 1305 { 1306 kvfree(filp->private_data); 1307 filp->private_data = NULL; 1308 return 0; 1309 } 1310 1311 static const struct file_operations hns3_dbg_fops = { 1312 .owner = THIS_MODULE, 1313 .open = hns3_dbg_open, 1314 .read = hns3_dbg_read, 1315 .release = hns3_dbg_release, 1316 }; 1317 1318 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd) 1319 { 1320 struct dentry *entry_dir; 1321 struct hns3_dbg_data *data; 1322 u16 max_queue_num; 1323 unsigned int i; 1324 1325 entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry; 1326 max_queue_num = hns3_get_max_available_channels(handle); 1327 data = devm_kzalloc(&handle->pdev->dev, max_queue_num * sizeof(*data), 1328 GFP_KERNEL); 1329 if (!data) 1330 return -ENOMEM; 1331 1332 for (i = 0; i < max_queue_num; i++) { 1333 char name[HNS3_DBG_FILE_NAME_LEN]; 1334 1335 data[i].handle = handle; 1336 data[i].cmd = hns3_dbg_cmd[cmd].cmd; 1337 data[i].qid = i; 1338 sprintf(name, "%s%u", hns3_dbg_cmd[cmd].name, i); 1339 debugfs_create_file(name, 0400, entry_dir, &data[i], 1340 &hns3_dbg_fops); 1341 } 1342 1343 return 0; 1344 } 1345 1346 static int 1347 hns3_dbg_common_file_init(struct hnae3_handle *handle, u32 cmd) 1348 { 1349 struct hns3_dbg_data *data; 1350 struct dentry *entry_dir; 1351 1352 data = devm_kzalloc(&handle->pdev->dev, sizeof(*data), GFP_KERNEL); 1353 if (!data) 1354 return -ENOMEM; 1355 1356 data->handle = handle; 1357 data->cmd = hns3_dbg_cmd[cmd].cmd; 1358 entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry; 1359 debugfs_create_file(hns3_dbg_cmd[cmd].name, 0400, entry_dir, 1360 data, &hns3_dbg_fops); 1361 1362 return 0; 1363 } 1364 1365 int hns3_dbg_init(struct hnae3_handle *handle) 1366 { 1367 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 1368 const char *name = pci_name(handle->pdev); 1369 int ret; 1370 u32 i; 1371 1372 hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry = 1373 debugfs_create_dir(name, hns3_dbgfs_root); 1374 handle->hnae3_dbgfs = hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry; 1375 1376 for (i = 0; i < HNS3_DBG_DENTRY_COMMON; i++) 1377 hns3_dbg_dentry[i].dentry = 1378 debugfs_create_dir(hns3_dbg_dentry[i].name, 1379 handle->hnae3_dbgfs); 1380 1381 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) { 1382 if ((hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_TM_NODES && 1383 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) || 1384 (hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_PTP_INFO && 1385 !test_bit(HNAE3_DEV_SUPPORT_PTP_B, ae_dev->caps))) 1386 continue; 1387 1388 if (!hns3_dbg_cmd[i].init) { 1389 dev_err(&handle->pdev->dev, 1390 "cmd %s lack of init func\n", 1391 hns3_dbg_cmd[i].name); 1392 ret = -EINVAL; 1393 goto out; 1394 } 1395 1396 ret = hns3_dbg_cmd[i].init(handle, i); 1397 if (ret) { 1398 dev_err(&handle->pdev->dev, "failed to init cmd %s\n", 1399 hns3_dbg_cmd[i].name); 1400 goto out; 1401 } 1402 } 1403 1404 return 0; 1405 1406 out: 1407 debugfs_remove_recursive(handle->hnae3_dbgfs); 1408 handle->hnae3_dbgfs = NULL; 1409 return ret; 1410 } 1411 1412 void hns3_dbg_uninit(struct hnae3_handle *handle) 1413 { 1414 debugfs_remove_recursive(handle->hnae3_dbgfs); 1415 handle->hnae3_dbgfs = NULL; 1416 } 1417 1418 void hns3_dbg_register_debugfs(const char *debugfs_dir_name) 1419 { 1420 hns3_dbgfs_root = debugfs_create_dir(debugfs_dir_name, NULL); 1421 } 1422 1423 void hns3_dbg_unregister_debugfs(void) 1424 { 1425 debugfs_remove_recursive(hns3_dbgfs_root); 1426 hns3_dbgfs_root = NULL; 1427 } 1428