1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HNAE3_H 5 #define __HNAE3_H 6 7 /* Names used in this framework: 8 * ae handle (handle): 9 * a set of queues provided by AE 10 * ring buffer queue (rbq): 11 * the channel between upper layer and the AE, can do tx and rx 12 * ring: 13 * a tx or rx channel within a rbq 14 * ring description (desc): 15 * an element in the ring with packet information 16 * buffer: 17 * a memory region referred by desc with the full packet payload 18 * 19 * "num" means a static number set as a parameter, "count" mean a dynamic 20 * number set while running 21 * "cb" means control block 22 */ 23 24 #include <linux/acpi.h> 25 #include <linux/dcbnl.h> 26 #include <linux/delay.h> 27 #include <linux/device.h> 28 #include <linux/ethtool.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/pci.h> 32 #include <linux/pkt_sched.h> 33 #include <linux/types.h> 34 #include <net/pkt_cls.h> 35 36 #define HNAE3_MOD_VERSION "1.0" 37 38 #define HNAE3_MIN_VECTOR_NUM 2 /* first one for misc, another for IO */ 39 40 /* Device version */ 41 #define HNAE3_DEVICE_VERSION_V1 0x00020 42 #define HNAE3_DEVICE_VERSION_V2 0x00021 43 #define HNAE3_DEVICE_VERSION_V3 0x00030 44 45 #define HNAE3_PCI_REVISION_BIT_SIZE 8 46 47 /* Device IDs */ 48 #define HNAE3_DEV_ID_GE 0xA220 49 #define HNAE3_DEV_ID_25GE 0xA221 50 #define HNAE3_DEV_ID_25GE_RDMA 0xA222 51 #define HNAE3_DEV_ID_25GE_RDMA_MACSEC 0xA223 52 #define HNAE3_DEV_ID_50GE_RDMA 0xA224 53 #define HNAE3_DEV_ID_50GE_RDMA_MACSEC 0xA225 54 #define HNAE3_DEV_ID_100G_RDMA_MACSEC 0xA226 55 #define HNAE3_DEV_ID_200G_RDMA 0xA228 56 #define HNAE3_DEV_ID_VF 0xA22E 57 #define HNAE3_DEV_ID_RDMA_DCB_PFC_VF 0xA22F 58 59 #define HNAE3_CLASS_NAME_SIZE 16 60 61 #define HNAE3_DEV_INITED_B 0x0 62 #define HNAE3_DEV_SUPPORT_ROCE_B 0x1 63 #define HNAE3_DEV_SUPPORT_DCB_B 0x2 64 #define HNAE3_KNIC_CLIENT_INITED_B 0x3 65 #define HNAE3_UNIC_CLIENT_INITED_B 0x4 66 #define HNAE3_ROCE_CLIENT_INITED_B 0x5 67 68 #define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\ 69 BIT(HNAE3_DEV_SUPPORT_ROCE_B)) 70 71 #define hnae3_dev_roce_supported(hdev) \ 72 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B) 73 74 #define hnae3_dev_dcb_supported(hdev) \ 75 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B) 76 77 enum HNAE3_DEV_CAP_BITS { 78 HNAE3_DEV_SUPPORT_FD_B, 79 HNAE3_DEV_SUPPORT_GRO_B, 80 HNAE3_DEV_SUPPORT_FEC_B, 81 HNAE3_DEV_SUPPORT_UDP_GSO_B, 82 HNAE3_DEV_SUPPORT_QB_B, 83 HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, 84 HNAE3_DEV_SUPPORT_PTP_B, 85 HNAE3_DEV_SUPPORT_INT_QL_B, 86 HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, 87 HNAE3_DEV_SUPPORT_TX_PUSH_B, 88 HNAE3_DEV_SUPPORT_PHY_IMP_B, 89 HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, 90 HNAE3_DEV_SUPPORT_HW_PAD_B, 91 HNAE3_DEV_SUPPORT_STASH_B, 92 HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, 93 HNAE3_DEV_SUPPORT_PAUSE_B, 94 HNAE3_DEV_SUPPORT_RAS_IMP_B, 95 HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, 96 HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, 97 HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, 98 }; 99 100 #define hnae3_dev_fd_supported(hdev) \ 101 test_bit(HNAE3_DEV_SUPPORT_FD_B, (hdev)->ae_dev->caps) 102 103 #define hnae3_dev_gro_supported(hdev) \ 104 test_bit(HNAE3_DEV_SUPPORT_GRO_B, (hdev)->ae_dev->caps) 105 106 #define hnae3_dev_fec_supported(hdev) \ 107 test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps) 108 109 #define hnae3_dev_udp_gso_supported(hdev) \ 110 test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps) 111 112 #define hnae3_dev_qb_supported(hdev) \ 113 test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps) 114 115 #define hnae3_dev_fd_forward_tc_supported(hdev) \ 116 test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps) 117 118 #define hnae3_dev_ptp_supported(hdev) \ 119 test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps) 120 121 #define hnae3_dev_int_ql_supported(hdev) \ 122 test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps) 123 124 #define hnae3_dev_hw_csum_supported(hdev) \ 125 test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, (hdev)->ae_dev->caps) 126 127 #define hnae3_dev_tx_push_supported(hdev) \ 128 test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps) 129 130 #define hnae3_dev_phy_imp_supported(hdev) \ 131 test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps) 132 133 #define hnae3_dev_ras_imp_supported(hdev) \ 134 test_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, (hdev)->ae_dev->caps) 135 136 #define hnae3_dev_tqp_txrx_indep_supported(hdev) \ 137 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps) 138 139 #define hnae3_dev_hw_pad_supported(hdev) \ 140 test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps) 141 142 #define hnae3_dev_stash_supported(hdev) \ 143 test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps) 144 145 #define hnae3_dev_pause_supported(hdev) \ 146 test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, (hdev)->ae_dev->caps) 147 148 #define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) \ 149 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (ae_dev)->caps) 150 151 #define hnae3_ae_dev_rxd_adv_layout_supported(ae_dev) \ 152 test_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, (ae_dev)->caps) 153 154 enum HNAE3_PF_CAP_BITS { 155 HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0, 156 }; 157 #define ring_ptr_move_fw(ring, p) \ 158 ((ring)->p = ((ring)->p + 1) % (ring)->desc_num) 159 #define ring_ptr_move_bw(ring, p) \ 160 ((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num) 161 162 enum hns_desc_type { 163 DESC_TYPE_UNKNOWN, 164 DESC_TYPE_SKB, 165 DESC_TYPE_FRAGLIST_SKB, 166 DESC_TYPE_PAGE, 167 }; 168 169 struct hnae3_handle; 170 171 struct hnae3_queue { 172 void __iomem *io_base; 173 struct hnae3_ae_algo *ae_algo; 174 struct hnae3_handle *handle; 175 int tqp_index; /* index in a handle */ 176 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 177 u16 tx_desc_num; /* total number of tx desc */ 178 u16 rx_desc_num; /* total number of rx desc */ 179 }; 180 181 struct hns3_mac_stats { 182 u64 tx_pause_cnt; 183 u64 rx_pause_cnt; 184 }; 185 186 /* hnae3 loop mode */ 187 enum hnae3_loop { 188 HNAE3_LOOP_APP, 189 HNAE3_LOOP_SERIAL_SERDES, 190 HNAE3_LOOP_PARALLEL_SERDES, 191 HNAE3_LOOP_PHY, 192 HNAE3_LOOP_NONE, 193 }; 194 195 enum hnae3_client_type { 196 HNAE3_CLIENT_KNIC, 197 HNAE3_CLIENT_ROCE, 198 }; 199 200 /* mac media type */ 201 enum hnae3_media_type { 202 HNAE3_MEDIA_TYPE_UNKNOWN, 203 HNAE3_MEDIA_TYPE_FIBER, 204 HNAE3_MEDIA_TYPE_COPPER, 205 HNAE3_MEDIA_TYPE_BACKPLANE, 206 HNAE3_MEDIA_TYPE_NONE, 207 }; 208 209 /* must be consistent with definition in firmware */ 210 enum hnae3_module_type { 211 HNAE3_MODULE_TYPE_UNKNOWN = 0x00, 212 HNAE3_MODULE_TYPE_FIBRE_LR = 0x01, 213 HNAE3_MODULE_TYPE_FIBRE_SR = 0x02, 214 HNAE3_MODULE_TYPE_AOC = 0x03, 215 HNAE3_MODULE_TYPE_CR = 0x04, 216 HNAE3_MODULE_TYPE_KR = 0x05, 217 HNAE3_MODULE_TYPE_TP = 0x06, 218 }; 219 220 enum hnae3_fec_mode { 221 HNAE3_FEC_AUTO = 0, 222 HNAE3_FEC_BASER, 223 HNAE3_FEC_RS, 224 HNAE3_FEC_USER_DEF, 225 }; 226 227 enum hnae3_reset_notify_type { 228 HNAE3_UP_CLIENT, 229 HNAE3_DOWN_CLIENT, 230 HNAE3_INIT_CLIENT, 231 HNAE3_UNINIT_CLIENT, 232 }; 233 234 enum hnae3_hw_error_type { 235 HNAE3_PPU_POISON_ERROR, 236 HNAE3_CMDQ_ECC_ERROR, 237 HNAE3_IMP_RD_POISON_ERROR, 238 HNAE3_ROCEE_AXI_RESP_ERROR, 239 }; 240 241 enum hnae3_reset_type { 242 HNAE3_VF_RESET, 243 HNAE3_VF_FUNC_RESET, 244 HNAE3_VF_PF_FUNC_RESET, 245 HNAE3_VF_FULL_RESET, 246 HNAE3_FLR_RESET, 247 HNAE3_FUNC_RESET, 248 HNAE3_GLOBAL_RESET, 249 HNAE3_IMP_RESET, 250 HNAE3_NONE_RESET, 251 HNAE3_MAX_RESET, 252 }; 253 254 enum hnae3_port_base_vlan_state { 255 HNAE3_PORT_BASE_VLAN_DISABLE, 256 HNAE3_PORT_BASE_VLAN_ENABLE, 257 HNAE3_PORT_BASE_VLAN_MODIFY, 258 HNAE3_PORT_BASE_VLAN_NOCHANGE, 259 }; 260 261 enum hnae3_dbg_cmd { 262 HNAE3_DBG_CMD_TM_NODES, 263 HNAE3_DBG_CMD_TM_PRI, 264 HNAE3_DBG_CMD_TM_QSET, 265 HNAE3_DBG_CMD_TM_MAP, 266 HNAE3_DBG_CMD_TM_PG, 267 HNAE3_DBG_CMD_TM_PORT, 268 HNAE3_DBG_CMD_TC_SCH_INFO, 269 HNAE3_DBG_CMD_QOS_PAUSE_CFG, 270 HNAE3_DBG_CMD_QOS_PRI_MAP, 271 HNAE3_DBG_CMD_QOS_BUF_CFG, 272 HNAE3_DBG_CMD_DEV_INFO, 273 HNAE3_DBG_CMD_TX_BD, 274 HNAE3_DBG_CMD_RX_BD, 275 HNAE3_DBG_CMD_MAC_UC, 276 HNAE3_DBG_CMD_MAC_MC, 277 HNAE3_DBG_CMD_MNG_TBL, 278 HNAE3_DBG_CMD_LOOPBACK, 279 HNAE3_DBG_CMD_INTERRUPT_INFO, 280 HNAE3_DBG_CMD_RESET_INFO, 281 HNAE3_DBG_CMD_IMP_INFO, 282 HNAE3_DBG_CMD_NCL_CONFIG, 283 HNAE3_DBG_CMD_REG_BIOS_COMMON, 284 HNAE3_DBG_CMD_REG_SSU, 285 HNAE3_DBG_CMD_REG_IGU_EGU, 286 HNAE3_DBG_CMD_REG_RPU, 287 HNAE3_DBG_CMD_REG_NCSI, 288 HNAE3_DBG_CMD_REG_RTC, 289 HNAE3_DBG_CMD_REG_PPP, 290 HNAE3_DBG_CMD_REG_RCB, 291 HNAE3_DBG_CMD_REG_TQP, 292 HNAE3_DBG_CMD_REG_MAC, 293 HNAE3_DBG_CMD_REG_DCB, 294 HNAE3_DBG_CMD_VLAN_CONFIG, 295 HNAE3_DBG_CMD_QUEUE_MAP, 296 HNAE3_DBG_CMD_RX_QUEUE_INFO, 297 HNAE3_DBG_CMD_TX_QUEUE_INFO, 298 HNAE3_DBG_CMD_FD_TCAM, 299 HNAE3_DBG_CMD_MAC_TNL_STATUS, 300 HNAE3_DBG_CMD_SERV_INFO, 301 HNAE3_DBG_CMD_UNKNOWN, 302 }; 303 304 struct hnae3_vector_info { 305 u8 __iomem *io_addr; 306 int vector; 307 }; 308 309 #define HNAE3_RING_TYPE_B 0 310 #define HNAE3_RING_TYPE_TX 0 311 #define HNAE3_RING_TYPE_RX 1 312 #define HNAE3_RING_GL_IDX_S 0 313 #define HNAE3_RING_GL_IDX_M GENMASK(1, 0) 314 #define HNAE3_RING_GL_RX 0 315 #define HNAE3_RING_GL_TX 1 316 317 #define HNAE3_FW_VERSION_BYTE3_SHIFT 24 318 #define HNAE3_FW_VERSION_BYTE3_MASK GENMASK(31, 24) 319 #define HNAE3_FW_VERSION_BYTE2_SHIFT 16 320 #define HNAE3_FW_VERSION_BYTE2_MASK GENMASK(23, 16) 321 #define HNAE3_FW_VERSION_BYTE1_SHIFT 8 322 #define HNAE3_FW_VERSION_BYTE1_MASK GENMASK(15, 8) 323 #define HNAE3_FW_VERSION_BYTE0_SHIFT 0 324 #define HNAE3_FW_VERSION_BYTE0_MASK GENMASK(7, 0) 325 326 struct hnae3_ring_chain_node { 327 struct hnae3_ring_chain_node *next; 328 u32 tqp_index; 329 u32 flag; 330 u32 int_gl_idx; 331 }; 332 333 #define HNAE3_IS_TX_RING(node) \ 334 (((node)->flag & 1 << HNAE3_RING_TYPE_B) == HNAE3_RING_TYPE_TX) 335 336 /* device specification info from firmware */ 337 struct hnae3_dev_specs { 338 u32 mac_entry_num; /* number of mac-vlan table entry */ 339 u32 mng_entry_num; /* number of manager table entry */ 340 u32 max_tm_rate; 341 u16 rss_ind_tbl_size; 342 u16 rss_key_size; 343 u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */ 344 u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */ 345 u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */ 346 u16 max_frm_size; 347 u16 max_qset_num; 348 }; 349 350 struct hnae3_client_ops { 351 int (*init_instance)(struct hnae3_handle *handle); 352 void (*uninit_instance)(struct hnae3_handle *handle, bool reset); 353 void (*link_status_change)(struct hnae3_handle *handle, bool state); 354 int (*reset_notify)(struct hnae3_handle *handle, 355 enum hnae3_reset_notify_type type); 356 void (*process_hw_error)(struct hnae3_handle *handle, 357 enum hnae3_hw_error_type); 358 }; 359 360 #define HNAE3_CLIENT_NAME_LENGTH 16 361 struct hnae3_client { 362 char name[HNAE3_CLIENT_NAME_LENGTH]; 363 unsigned long state; 364 enum hnae3_client_type type; 365 const struct hnae3_client_ops *ops; 366 struct list_head node; 367 }; 368 369 #define HNAE3_DEV_CAPS_MAX_NUM 96 370 struct hnae3_ae_dev { 371 struct pci_dev *pdev; 372 const struct hnae3_ae_ops *ops; 373 struct list_head node; 374 u32 flag; 375 unsigned long hw_err_reset_req; 376 struct hnae3_dev_specs dev_specs; 377 u32 dev_version; 378 unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)]; 379 void *priv; 380 }; 381 382 /* This struct defines the operation on the handle. 383 * 384 * init_ae_dev(): (mandatory) 385 * Get PF configure from pci_dev and initialize PF hardware 386 * uninit_ae_dev() 387 * Disable PF device and release PF resource 388 * register_client 389 * Register client to ae_dev 390 * unregister_client() 391 * Unregister client from ae_dev 392 * start() 393 * Enable the hardware 394 * stop() 395 * Disable the hardware 396 * start_client() 397 * Inform the hclge that client has been started 398 * stop_client() 399 * Inform the hclge that client has been stopped 400 * get_status() 401 * Get the carrier state of the back channel of the handle, 1 for ok, 0 for 402 * non-ok 403 * get_ksettings_an_result() 404 * Get negotiation status,speed and duplex 405 * get_media_type() 406 * Get media type of MAC 407 * check_port_speed() 408 * Check target speed whether is supported 409 * adjust_link() 410 * Adjust link status 411 * set_loopback() 412 * Set loopback 413 * set_promisc_mode 414 * Set promisc mode 415 * request_update_promisc_mode 416 * request to hclge(vf) to update promisc mode 417 * set_mtu() 418 * set mtu 419 * get_pauseparam() 420 * get tx and rx of pause frame use 421 * set_pauseparam() 422 * set tx and rx of pause frame use 423 * set_autoneg() 424 * set auto autonegotiation of pause frame use 425 * get_autoneg() 426 * get auto autonegotiation of pause frame use 427 * restart_autoneg() 428 * restart autonegotiation 429 * halt_autoneg() 430 * halt/resume autonegotiation when autonegotiation on 431 * get_coalesce_usecs() 432 * get usecs to delay a TX interrupt after a packet is sent 433 * get_rx_max_coalesced_frames() 434 * get Maximum number of packets to be sent before a TX interrupt. 435 * set_coalesce_usecs() 436 * set usecs to delay a TX interrupt after a packet is sent 437 * set_coalesce_frames() 438 * set Maximum number of packets to be sent before a TX interrupt. 439 * get_mac_addr() 440 * get mac address 441 * set_mac_addr() 442 * set mac address 443 * add_uc_addr 444 * Add unicast addr to mac table 445 * rm_uc_addr 446 * Remove unicast addr from mac table 447 * set_mc_addr() 448 * Set multicast address 449 * add_mc_addr 450 * Add multicast address to mac table 451 * rm_mc_addr 452 * Remove multicast address from mac table 453 * update_stats() 454 * Update Old network device statistics 455 * get_mac_stats() 456 * get mac pause statistics including tx_cnt and rx_cnt 457 * get_ethtool_stats() 458 * Get ethtool network device statistics 459 * get_strings() 460 * Get a set of strings that describe the requested objects 461 * get_sset_count() 462 * Get number of strings that @get_strings will write 463 * update_led_status() 464 * Update the led status 465 * set_led_id() 466 * Set led id 467 * get_regs() 468 * Get regs dump 469 * get_regs_len() 470 * Get the len of the regs dump 471 * get_rss_key_size() 472 * Get rss key size 473 * get_rss() 474 * Get rss table 475 * set_rss() 476 * Set rss table 477 * get_tc_size() 478 * Get tc size of handle 479 * get_vector() 480 * Get vector number and vector information 481 * put_vector() 482 * Put the vector in hdev 483 * map_ring_to_vector() 484 * Map rings to vector 485 * unmap_ring_from_vector() 486 * Unmap rings from vector 487 * reset_queue() 488 * Reset queue 489 * get_fw_version() 490 * Get firmware version 491 * get_mdix_mode() 492 * Get media typr of phy 493 * enable_vlan_filter() 494 * Enable vlan filter 495 * set_vlan_filter() 496 * Set vlan filter config of Ports 497 * set_vf_vlan_filter() 498 * Set vlan filter config of vf 499 * enable_hw_strip_rxvtag() 500 * Enable/disable hardware strip vlan tag of packets received 501 * set_gro_en 502 * Enable/disable HW GRO 503 * add_arfs_entry 504 * Check the 5-tuples of flow, and create flow director rule 505 * get_vf_config 506 * Get the VF configuration setting by the host 507 * set_vf_link_state 508 * Set VF link status 509 * set_vf_spoofchk 510 * Enable/disable spoof check for specified vf 511 * set_vf_trust 512 * Enable/disable trust for specified vf, if the vf being trusted, then 513 * it can enable promisc mode 514 * set_vf_rate 515 * Set the max tx rate of specified vf. 516 * set_vf_mac 517 * Configure the default MAC for specified VF 518 * get_module_eeprom 519 * Get the optical module eeprom info. 520 * add_cls_flower 521 * Add clsflower rule 522 * del_cls_flower 523 * Delete clsflower rule 524 * cls_flower_active 525 * Check if any cls flower rule exist 526 * dbg_read_cmd 527 * Execute debugfs read command. 528 */ 529 struct hnae3_ae_ops { 530 int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev); 531 void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev); 532 void (*reset_prepare)(struct hnae3_ae_dev *ae_dev, 533 enum hnae3_reset_type rst_type); 534 void (*reset_done)(struct hnae3_ae_dev *ae_dev); 535 int (*init_client_instance)(struct hnae3_client *client, 536 struct hnae3_ae_dev *ae_dev); 537 void (*uninit_client_instance)(struct hnae3_client *client, 538 struct hnae3_ae_dev *ae_dev); 539 int (*start)(struct hnae3_handle *handle); 540 void (*stop)(struct hnae3_handle *handle); 541 int (*client_start)(struct hnae3_handle *handle); 542 void (*client_stop)(struct hnae3_handle *handle); 543 int (*get_status)(struct hnae3_handle *handle); 544 void (*get_ksettings_an_result)(struct hnae3_handle *handle, 545 u8 *auto_neg, u32 *speed, u8 *duplex); 546 547 int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed, 548 u8 duplex); 549 550 void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type, 551 u8 *module_type); 552 int (*check_port_speed)(struct hnae3_handle *handle, u32 speed); 553 void (*get_fec)(struct hnae3_handle *handle, u8 *fec_ability, 554 u8 *fec_mode); 555 int (*set_fec)(struct hnae3_handle *handle, u32 fec_mode); 556 void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex); 557 int (*set_loopback)(struct hnae3_handle *handle, 558 enum hnae3_loop loop_mode, bool en); 559 560 int (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc, 561 bool en_mc_pmc); 562 void (*request_update_promisc_mode)(struct hnae3_handle *handle); 563 int (*set_mtu)(struct hnae3_handle *handle, int new_mtu); 564 565 void (*get_pauseparam)(struct hnae3_handle *handle, 566 u32 *auto_neg, u32 *rx_en, u32 *tx_en); 567 int (*set_pauseparam)(struct hnae3_handle *handle, 568 u32 auto_neg, u32 rx_en, u32 tx_en); 569 570 int (*set_autoneg)(struct hnae3_handle *handle, bool enable); 571 int (*get_autoneg)(struct hnae3_handle *handle); 572 int (*restart_autoneg)(struct hnae3_handle *handle); 573 int (*halt_autoneg)(struct hnae3_handle *handle, bool halt); 574 575 void (*get_coalesce_usecs)(struct hnae3_handle *handle, 576 u32 *tx_usecs, u32 *rx_usecs); 577 void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle, 578 u32 *tx_frames, u32 *rx_frames); 579 int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout); 580 int (*set_coalesce_frames)(struct hnae3_handle *handle, 581 u32 coalesce_frames); 582 void (*get_coalesce_range)(struct hnae3_handle *handle, 583 u32 *tx_frames_low, u32 *rx_frames_low, 584 u32 *tx_frames_high, u32 *rx_frames_high, 585 u32 *tx_usecs_low, u32 *rx_usecs_low, 586 u32 *tx_usecs_high, u32 *rx_usecs_high); 587 588 void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p); 589 int (*set_mac_addr)(struct hnae3_handle *handle, void *p, 590 bool is_first); 591 int (*do_ioctl)(struct hnae3_handle *handle, 592 struct ifreq *ifr, int cmd); 593 int (*add_uc_addr)(struct hnae3_handle *handle, 594 const unsigned char *addr); 595 int (*rm_uc_addr)(struct hnae3_handle *handle, 596 const unsigned char *addr); 597 int (*set_mc_addr)(struct hnae3_handle *handle, void *addr); 598 int (*add_mc_addr)(struct hnae3_handle *handle, 599 const unsigned char *addr); 600 int (*rm_mc_addr)(struct hnae3_handle *handle, 601 const unsigned char *addr); 602 void (*set_tso_stats)(struct hnae3_handle *handle, int enable); 603 void (*update_stats)(struct hnae3_handle *handle, 604 struct net_device_stats *net_stats); 605 void (*get_stats)(struct hnae3_handle *handle, u64 *data); 606 void (*get_mac_stats)(struct hnae3_handle *handle, 607 struct hns3_mac_stats *mac_stats); 608 void (*get_strings)(struct hnae3_handle *handle, 609 u32 stringset, u8 *data); 610 int (*get_sset_count)(struct hnae3_handle *handle, int stringset); 611 612 void (*get_regs)(struct hnae3_handle *handle, u32 *version, 613 void *data); 614 int (*get_regs_len)(struct hnae3_handle *handle); 615 616 u32 (*get_rss_key_size)(struct hnae3_handle *handle); 617 int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key, 618 u8 *hfunc); 619 int (*set_rss)(struct hnae3_handle *handle, const u32 *indir, 620 const u8 *key, const u8 hfunc); 621 int (*set_rss_tuple)(struct hnae3_handle *handle, 622 struct ethtool_rxnfc *cmd); 623 int (*get_rss_tuple)(struct hnae3_handle *handle, 624 struct ethtool_rxnfc *cmd); 625 626 int (*get_tc_size)(struct hnae3_handle *handle); 627 628 int (*get_vector)(struct hnae3_handle *handle, u16 vector_num, 629 struct hnae3_vector_info *vector_info); 630 int (*put_vector)(struct hnae3_handle *handle, int vector_num); 631 int (*map_ring_to_vector)(struct hnae3_handle *handle, 632 int vector_num, 633 struct hnae3_ring_chain_node *vr_chain); 634 int (*unmap_ring_from_vector)(struct hnae3_handle *handle, 635 int vector_num, 636 struct hnae3_ring_chain_node *vr_chain); 637 638 int (*reset_queue)(struct hnae3_handle *handle); 639 u32 (*get_fw_version)(struct hnae3_handle *handle); 640 void (*get_mdix_mode)(struct hnae3_handle *handle, 641 u8 *tp_mdix_ctrl, u8 *tp_mdix); 642 643 int (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable); 644 int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto, 645 u16 vlan_id, bool is_kill); 646 int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid, 647 u16 vlan, u8 qos, __be16 proto); 648 int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable); 649 void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle); 650 enum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *ae_dev, 651 unsigned long *addr); 652 void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev, 653 enum hnae3_reset_type rst_type); 654 void (*get_channels)(struct hnae3_handle *handle, 655 struct ethtool_channels *ch); 656 void (*get_tqps_and_rss_info)(struct hnae3_handle *h, 657 u16 *alloc_tqps, u16 *max_rss_size); 658 int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num, 659 bool rxfh_configured); 660 void (*get_flowctrl_adv)(struct hnae3_handle *handle, 661 u32 *flowctrl_adv); 662 int (*set_led_id)(struct hnae3_handle *handle, 663 enum ethtool_phys_id_state status); 664 void (*get_link_mode)(struct hnae3_handle *handle, 665 unsigned long *supported, 666 unsigned long *advertising); 667 int (*add_fd_entry)(struct hnae3_handle *handle, 668 struct ethtool_rxnfc *cmd); 669 int (*del_fd_entry)(struct hnae3_handle *handle, 670 struct ethtool_rxnfc *cmd); 671 int (*get_fd_rule_cnt)(struct hnae3_handle *handle, 672 struct ethtool_rxnfc *cmd); 673 int (*get_fd_rule_info)(struct hnae3_handle *handle, 674 struct ethtool_rxnfc *cmd); 675 int (*get_fd_all_rules)(struct hnae3_handle *handle, 676 struct ethtool_rxnfc *cmd, u32 *rule_locs); 677 void (*enable_fd)(struct hnae3_handle *handle, bool enable); 678 int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id, 679 u16 flow_id, struct flow_keys *fkeys); 680 int (*dbg_read_cmd)(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, 681 char *buf, int len); 682 pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev); 683 bool (*get_hw_reset_stat)(struct hnae3_handle *handle); 684 bool (*ae_dev_resetting)(struct hnae3_handle *handle); 685 unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle); 686 int (*set_gro_en)(struct hnae3_handle *handle, bool enable); 687 u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id); 688 void (*set_timer_task)(struct hnae3_handle *handle, bool enable); 689 int (*mac_connect_phy)(struct hnae3_handle *handle); 690 void (*mac_disconnect_phy)(struct hnae3_handle *handle); 691 int (*get_vf_config)(struct hnae3_handle *handle, int vf, 692 struct ifla_vf_info *ivf); 693 int (*set_vf_link_state)(struct hnae3_handle *handle, int vf, 694 int link_state); 695 int (*set_vf_spoofchk)(struct hnae3_handle *handle, int vf, 696 bool enable); 697 int (*set_vf_trust)(struct hnae3_handle *handle, int vf, bool enable); 698 int (*set_vf_rate)(struct hnae3_handle *handle, int vf, 699 int min_tx_rate, int max_tx_rate, bool force); 700 int (*set_vf_mac)(struct hnae3_handle *handle, int vf, u8 *p); 701 int (*get_module_eeprom)(struct hnae3_handle *handle, u32 offset, 702 u32 len, u8 *data); 703 bool (*get_cmdq_stat)(struct hnae3_handle *handle); 704 int (*add_cls_flower)(struct hnae3_handle *handle, 705 struct flow_cls_offload *cls_flower, int tc); 706 int (*del_cls_flower)(struct hnae3_handle *handle, 707 struct flow_cls_offload *cls_flower); 708 bool (*cls_flower_active)(struct hnae3_handle *handle); 709 int (*get_phy_link_ksettings)(struct hnae3_handle *handle, 710 struct ethtool_link_ksettings *cmd); 711 int (*set_phy_link_ksettings)(struct hnae3_handle *handle, 712 const struct ethtool_link_ksettings *cmd); 713 }; 714 715 struct hnae3_dcb_ops { 716 /* IEEE 802.1Qaz std */ 717 int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *); 718 int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *); 719 int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *); 720 int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *); 721 722 /* DCBX configuration */ 723 u8 (*getdcbx)(struct hnae3_handle *); 724 u8 (*setdcbx)(struct hnae3_handle *, u8); 725 726 int (*setup_tc)(struct hnae3_handle *handle, 727 struct tc_mqprio_qopt_offload *mqprio_qopt); 728 }; 729 730 struct hnae3_ae_algo { 731 const struct hnae3_ae_ops *ops; 732 struct list_head node; 733 const struct pci_device_id *pdev_id_table; 734 }; 735 736 #define HNAE3_INT_NAME_LEN 32 737 #define HNAE3_ITR_COUNTDOWN_START 100 738 739 #define HNAE3_MAX_TC 8 740 #define HNAE3_MAX_USER_PRIO 8 741 struct hnae3_tc_info { 742 u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */ 743 u16 tqp_count[HNAE3_MAX_TC]; 744 u16 tqp_offset[HNAE3_MAX_TC]; 745 unsigned long tc_en; /* bitmap of TC enabled */ 746 u8 num_tc; /* Total number of enabled TCs */ 747 bool mqprio_active; 748 }; 749 750 struct hnae3_knic_private_info { 751 struct net_device *netdev; /* Set by KNIC client when init instance */ 752 u16 rss_size; /* Allocated RSS queues */ 753 u16 req_rss_size; 754 u16 rx_buf_len; 755 u16 num_tx_desc; 756 u16 num_rx_desc; 757 758 struct hnae3_tc_info tc_info; 759 760 u16 num_tqps; /* total number of TQPs in this handle */ 761 struct hnae3_queue **tqp; /* array base of all TQPs in this instance */ 762 const struct hnae3_dcb_ops *dcb_ops; 763 764 u16 int_rl_setting; 765 enum pkt_hash_types rss_type; 766 }; 767 768 struct hnae3_roce_private_info { 769 struct net_device *netdev; 770 void __iomem *roce_io_base; 771 void __iomem *roce_mem_base; 772 int base_vector; 773 int num_vectors; 774 775 /* The below attributes defined for RoCE client, hnae3 gives 776 * initial values to them, and RoCE client can modify and use 777 * them. 778 */ 779 unsigned long reset_state; 780 unsigned long instance_state; 781 unsigned long state; 782 }; 783 784 #define HNAE3_SUPPORT_APP_LOOPBACK BIT(0) 785 #define HNAE3_SUPPORT_PHY_LOOPBACK BIT(1) 786 #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK BIT(2) 787 #define HNAE3_SUPPORT_VF BIT(3) 788 #define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK BIT(4) 789 790 #define HNAE3_USER_UPE BIT(0) /* unicast promisc enabled by user */ 791 #define HNAE3_USER_MPE BIT(1) /* mulitcast promisc enabled by user */ 792 #define HNAE3_BPE BIT(2) /* broadcast promisc enable */ 793 #define HNAE3_OVERFLOW_UPE BIT(3) /* unicast mac vlan overflow */ 794 #define HNAE3_OVERFLOW_MPE BIT(4) /* multicast mac vlan overflow */ 795 #define HNAE3_UPE (HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE) 796 #define HNAE3_MPE (HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE) 797 798 enum hnae3_pflag { 799 HNAE3_PFLAG_LIMIT_PROMISC, 800 HNAE3_PFLAG_MAX 801 }; 802 803 struct hnae3_handle { 804 struct hnae3_client *client; 805 struct pci_dev *pdev; 806 void *priv; 807 struct hnae3_ae_algo *ae_algo; /* the class who provides this handle */ 808 u64 flags; /* Indicate the capabilities for this handle */ 809 810 union { 811 struct net_device *netdev; /* first member */ 812 struct hnae3_knic_private_info kinfo; 813 struct hnae3_roce_private_info rinfo; 814 }; 815 816 u32 numa_node_mask; /* for multi-chip support */ 817 818 enum hnae3_port_base_vlan_state port_base_vlan_state; 819 820 u8 netdev_flags; 821 struct dentry *hnae3_dbgfs; 822 823 /* Network interface message level enabled bits */ 824 u32 msg_enable; 825 826 unsigned long supported_pflags; 827 unsigned long priv_flags; 828 }; 829 830 #define hnae3_set_field(origin, mask, shift, val) \ 831 do { \ 832 (origin) &= (~(mask)); \ 833 (origin) |= ((val) << (shift)) & (mask); \ 834 } while (0) 835 #define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift)) 836 837 #define hnae3_set_bit(origin, shift, val) \ 838 hnae3_set_field(origin, 0x1 << (shift), shift, val) 839 #define hnae3_get_bit(origin, shift) \ 840 hnae3_get_field(origin, 0x1 << (shift), shift) 841 842 int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev); 843 void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev); 844 845 void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo); 846 void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo); 847 848 void hnae3_unregister_client(struct hnae3_client *client); 849 int hnae3_register_client(struct hnae3_client *client); 850 851 void hnae3_set_client_init_flag(struct hnae3_client *client, 852 struct hnae3_ae_dev *ae_dev, 853 unsigned int inited); 854 #endif 855