1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (c) 2014-2015 Hisilicon Limited. 4 */ 5 6 #ifndef __HNS_DSAF_MAIN_H 7 #define __HNS_DSAF_MAIN_H 8 #include "hnae.h" 9 10 #include "hns_dsaf_reg.h" 11 #include "hns_dsaf_mac.h" 12 13 struct hns_mac_cb; 14 15 #define DSAF_DRV_NAME "hns_dsaf" 16 #define DSAF_MOD_VERSION "v1.0" 17 #define DSAF_DEVICE_NAME "dsaf" 18 19 #define HNS_DSAF_DEBUG_NW_REG_OFFSET 0x100000 20 21 #define DSAF_BASE_INNER_PORT_NUM 127/* mac tbl qid*/ 22 23 #define DSAF_MAX_CHIP_NUM 2 /*max 2 chips */ 24 25 #define DSAF_DEFAUTL_QUEUE_NUM_PER_PPE 22 26 27 #define HNS_DSAF_MAX_DESC_CNT 1024 28 #define HNS_DSAF_MIN_DESC_CNT 16 29 30 #define DSAF_INVALID_ENTRY_IDX 0xffff 31 32 #define DSAF_CFG_READ_CNT 30 33 34 #define DSAF_DUMP_REGS_NUM 504 35 #define DSAF_STATIC_NUM 28 36 #define DSAF_V2_STATIC_NUM 44 37 #define DSAF_PRIO_NR 8 38 #define DSAF_REG_PER_ZONE 3 39 40 #define DSAF_ROCE_CREDIT_CHN 8 41 #define DSAF_ROCE_CHAN_MODE 3 42 43 #define HNS_MAX_WAIT_CNT 10000 44 45 #define DSAF_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset)))) 46 #define HNS_DSAF_IS_DEBUG(dev) ((dev)->dsaf_mode == DSAF_MODE_DISABLE_SP) 47 48 enum hal_dsaf_mode { 49 HRD_DSAF_NO_DSAF_MODE = 0x0, 50 HRD_DSAF_MODE = 0x1, 51 }; 52 53 enum hal_dsaf_tc_mode { 54 HRD_DSAF_4TC_MODE = 0X0, 55 HRD_DSAF_8TC_MODE = 0X1, 56 }; 57 58 struct dsaf_vm_def_vlan { 59 u32 vm_def_vlan_id; 60 u32 vm_def_vlan_cfi; 61 u32 vm_def_vlan_pri; 62 }; 63 64 struct dsaf_tbl_tcam_data { 65 u32 tbl_tcam_data_high; 66 u32 tbl_tcam_data_low; 67 }; 68 69 #define DSAF_PORT_MSK_NUM \ 70 ((DSAF_TOTAL_QUEUE_NUM + DSAF_SERVICE_NW_NUM - 1) / 32 + 1) 71 struct dsaf_tbl_tcam_mcast_cfg { 72 u8 tbl_mcast_old_en; 73 u8 tbl_mcast_item_vld; 74 u32 tbl_mcast_port_msk[DSAF_PORT_MSK_NUM]; 75 }; 76 77 struct dsaf_tbl_tcam_ucast_cfg { 78 u32 tbl_ucast_old_en; 79 u32 tbl_ucast_item_vld; 80 u32 tbl_ucast_mac_discard; 81 u32 tbl_ucast_dvc; 82 u32 tbl_ucast_out_port; 83 }; 84 85 struct dsaf_tbl_line_cfg { 86 u32 tbl_line_mac_discard; 87 u32 tbl_line_dvc; 88 u32 tbl_line_out_port; 89 }; 90 91 enum dsaf_port_rate_mode { 92 DSAF_PORT_RATE_1000 = 0, 93 DSAF_PORT_RATE_2500, 94 DSAF_PORT_RATE_10000 95 }; 96 97 enum dsaf_stp_port_type { 98 DSAF_STP_PORT_TYPE_DISCARD = 0, 99 DSAF_STP_PORT_TYPE_BLOCK = 1, 100 DSAF_STP_PORT_TYPE_LISTEN = 2, 101 DSAF_STP_PORT_TYPE_LEARN = 3, 102 DSAF_STP_PORT_TYPE_FORWARD = 4 103 }; 104 105 enum dsaf_sw_port_type { 106 DSAF_SW_PORT_TYPE_NON_VLAN = 0, 107 DSAF_SW_PORT_TYPE_ACCESS = 1, 108 DSAF_SW_PORT_TYPE_TRUNK = 2, 109 }; 110 111 #define DSAF_SUB_BASE_SIZE (0x10000) 112 113 /* dsaf mode define */ 114 enum dsaf_mode { 115 DSAF_MODE_INVALID = 0, /**< Invalid dsaf mode */ 116 DSAF_MODE_ENABLE_FIX, /**< en DSAF-mode, fixed to queue*/ 117 DSAF_MODE_ENABLE_0VM, /**< en DSAF-mode, support 0 VM */ 118 DSAF_MODE_ENABLE_8VM, /**< en DSAF-mode, support 8 VM */ 119 DSAF_MODE_ENABLE_16VM, /**< en DSAF-mode, support 16 VM */ 120 DSAF_MODE_ENABLE_32VM, /**< en DSAF-mode, support 32 VM */ 121 DSAF_MODE_ENABLE_128VM, /**< en DSAF-mode, support 128 VM */ 122 DSAF_MODE_ENABLE, /**< before is enable DSAF mode*/ 123 DSAF_MODE_DISABLE_SP, /* <non-dsaf, single port mode */ 124 DSAF_MODE_DISABLE_FIX, /**< non-dasf, fixed to queue*/ 125 DSAF_MODE_DISABLE_2PORT_8VM, /**< non-dasf, 2port 8VM */ 126 DSAF_MODE_DISABLE_2PORT_16VM, /**< non-dasf, 2port 16VM */ 127 DSAF_MODE_DISABLE_2PORT_64VM, /**< non-dasf, 2port 64VM */ 128 DSAF_MODE_DISABLE_6PORT_0VM, /**< non-dasf, 6port 0VM */ 129 DSAF_MODE_DISABLE_6PORT_2VM, /**< non-dasf, 6port 2VM */ 130 DSAF_MODE_DISABLE_6PORT_4VM, /**< non-dasf, 6port 4VM */ 131 DSAF_MODE_DISABLE_6PORT_16VM, /**< non-dasf, 6port 16VM */ 132 DSAF_MODE_MAX /**< the last one, use as the num */ 133 }; 134 135 #define DSAF_DEST_PORT_NUM 256 /* DSAF max port num */ 136 #define DSAF_WORD_BIT_CNT 32 /* the num bit of word */ 137 138 /*mac entry, mc or uc entry*/ 139 struct dsaf_drv_mac_single_dest_entry { 140 /* mac addr, match the entry*/ 141 u8 addr[ETH_ALEN]; 142 u16 in_vlan_id; /* value of VlanId */ 143 144 /* the vld input port num, dsaf-mode fix 0, */ 145 /* non-dasf is the entry whitch port vld*/ 146 u8 in_port_num; 147 148 u8 port_num; /*output port num*/ 149 u8 rsv[6]; 150 }; 151 152 /*only mc entry*/ 153 struct dsaf_drv_mac_multi_dest_entry { 154 /* mac addr, match the entry*/ 155 u8 addr[ETH_ALEN]; 156 u16 in_vlan_id; 157 /* this mac addr output port,*/ 158 /* bit0-bit5 means Port0-Port5(1bit is vld)**/ 159 u32 port_mask[DSAF_DEST_PORT_NUM / DSAF_WORD_BIT_CNT]; 160 161 /* the vld input port num, dsaf-mode fix 0,*/ 162 /* non-dasf is the entry whitch port vld*/ 163 u8 in_port_num; 164 u8 rsv[7]; 165 }; 166 167 struct dsaf_hw_stats { 168 u64 pad_drop; 169 u64 man_pkts; 170 u64 rx_pkts; 171 u64 rx_pkt_id; 172 u64 rx_pause_frame; 173 u64 release_buf_num; 174 u64 sbm_drop; 175 u64 crc_false; 176 u64 bp_drop; 177 u64 rslt_drop; 178 u64 local_addr_false; 179 u64 vlan_drop; 180 u64 stp_drop; 181 u64 rx_pfc[DSAF_PRIO_NR]; 182 u64 tx_pfc[DSAF_PRIO_NR]; 183 u64 tx_pkts; 184 }; 185 186 struct hnae_vf_cb { 187 u8 port_index; 188 struct hns_mac_cb *mac_cb; 189 struct dsaf_device *dsaf_dev; 190 struct hnae_handle ae_handle; /* must be the last member */ 191 }; 192 193 struct dsaf_int_xge_src { 194 u32 xid_xge_ecc_err_int_src; 195 u32 xid_xge_fsm_timout_int_src; 196 u32 sbm_xge_lnk_fsm_timout_int_src; 197 u32 sbm_xge_lnk_ecc_2bit_int_src; 198 u32 sbm_xge_mib_req_failed_int_src; 199 u32 sbm_xge_mib_req_fsm_timout_int_src; 200 u32 sbm_xge_mib_rels_fsm_timout_int_src; 201 u32 sbm_xge_sram_ecc_2bit_int_src; 202 u32 sbm_xge_mib_buf_sum_err_int_src; 203 u32 sbm_xge_mib_req_extra_int_src; 204 u32 sbm_xge_mib_rels_extra_int_src; 205 u32 voq_xge_start_to_over_0_int_src; 206 u32 voq_xge_start_to_over_1_int_src; 207 u32 voq_xge_ecc_err_int_src; 208 }; 209 210 struct dsaf_int_ppe_src { 211 u32 xid_ppe_fsm_timout_int_src; 212 u32 sbm_ppe_lnk_fsm_timout_int_src; 213 u32 sbm_ppe_lnk_ecc_2bit_int_src; 214 u32 sbm_ppe_mib_req_failed_int_src; 215 u32 sbm_ppe_mib_req_fsm_timout_int_src; 216 u32 sbm_ppe_mib_rels_fsm_timout_int_src; 217 u32 sbm_ppe_sram_ecc_2bit_int_src; 218 u32 sbm_ppe_mib_buf_sum_err_int_src; 219 u32 sbm_ppe_mib_req_extra_int_src; 220 u32 sbm_ppe_mib_rels_extra_int_src; 221 u32 voq_ppe_start_to_over_0_int_src; 222 u32 voq_ppe_ecc_err_int_src; 223 u32 xod_ppe_fifo_rd_empty_int_src; 224 u32 xod_ppe_fifo_wr_full_int_src; 225 }; 226 227 struct dsaf_int_rocee_src { 228 u32 xid_rocee_fsm_timout_int_src; 229 u32 sbm_rocee_lnk_fsm_timout_int_src; 230 u32 sbm_rocee_lnk_ecc_2bit_int_src; 231 u32 sbm_rocee_mib_req_failed_int_src; 232 u32 sbm_rocee_mib_req_fsm_timout_int_src; 233 u32 sbm_rocee_mib_rels_fsm_timout_int_src; 234 u32 sbm_rocee_sram_ecc_2bit_int_src; 235 u32 sbm_rocee_mib_buf_sum_err_int_src; 236 u32 sbm_rocee_mib_req_extra_int_src; 237 u32 sbm_rocee_mib_rels_extra_int_src; 238 u32 voq_rocee_start_to_over_0_int_src; 239 u32 voq_rocee_ecc_err_int_src; 240 }; 241 242 struct dsaf_int_tbl_src { 243 u32 tbl_da0_mis_src; 244 u32 tbl_da1_mis_src; 245 u32 tbl_da2_mis_src; 246 u32 tbl_da3_mis_src; 247 u32 tbl_da4_mis_src; 248 u32 tbl_da5_mis_src; 249 u32 tbl_da6_mis_src; 250 u32 tbl_da7_mis_src; 251 u32 tbl_sa_mis_src; 252 u32 tbl_old_sech_end_src; 253 u32 lram_ecc_err1_src; 254 u32 lram_ecc_err2_src; 255 u32 tram_ecc_err1_src; 256 u32 tram_ecc_err2_src; 257 u32 tbl_ucast_bcast_xge0_src; 258 u32 tbl_ucast_bcast_xge1_src; 259 u32 tbl_ucast_bcast_xge2_src; 260 u32 tbl_ucast_bcast_xge3_src; 261 u32 tbl_ucast_bcast_xge4_src; 262 u32 tbl_ucast_bcast_xge5_src; 263 u32 tbl_ucast_bcast_ppe_src; 264 u32 tbl_ucast_bcast_rocee_src; 265 }; 266 267 struct dsaf_int_stat { 268 struct dsaf_int_xge_src dsaf_int_xge_stat[DSAF_COMM_CHN]; 269 struct dsaf_int_ppe_src dsaf_int_ppe_stat[DSAF_COMM_CHN]; 270 struct dsaf_int_rocee_src dsaf_int_rocee_stat[DSAF_COMM_CHN]; 271 struct dsaf_int_tbl_src dsaf_int_tbl_stat[1]; 272 273 }; 274 275 struct dsaf_misc_op { 276 void (*cpld_set_led)(struct hns_mac_cb *mac_cb, int link_status, 277 u16 speed, int data); 278 void (*cpld_reset_led)(struct hns_mac_cb *mac_cb); 279 int (*cpld_set_led_id)(struct hns_mac_cb *mac_cb, 280 enum hnae_led_state status); 281 /* reset series function, it will be reset if the dereset is 0 */ 282 void (*dsaf_reset)(struct dsaf_device *dsaf_dev, bool dereset); 283 void (*xge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset); 284 void (*ge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset); 285 void (*ppe_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset); 286 void (*ppe_comm_srst)(struct dsaf_device *dsaf_dev, bool dereset); 287 288 phy_interface_t (*get_phy_if)(struct hns_mac_cb *mac_cb); 289 int (*get_sfp_prsnt)(struct hns_mac_cb *mac_cb, int *sfp_prsnt); 290 291 int (*cfg_serdes_loopback)(struct hns_mac_cb *mac_cb, bool en); 292 }; 293 294 /* Dsaf device struct define ,and mac -> dsaf */ 295 struct dsaf_device { 296 struct device *dev; 297 struct hnae_ae_dev ae_dev; 298 299 u8 __iomem *sc_base; 300 u8 __iomem *sds_base; 301 u8 __iomem *ppe_base; 302 u8 __iomem *io_base; 303 struct regmap *sub_ctrl; 304 phys_addr_t ppe_paddr; 305 306 u32 desc_num; /* desc num per queue*/ 307 u32 buf_size; /* ring buffer size */ 308 u32 reset_offset; /* reset field offset in sub sysctrl */ 309 int buf_size_type; /* ring buffer size-type */ 310 enum dsaf_mode dsaf_mode; /* dsaf mode */ 311 enum hal_dsaf_mode dsaf_en; 312 enum hal_dsaf_tc_mode dsaf_tc_mode; 313 u32 dsaf_ver; 314 u16 tcam_max_num; /* max TCAM entry for user except promisc */ 315 316 struct ppe_common_cb *ppe_common[DSAF_COMM_DEV_NUM]; 317 struct rcb_common_cb *rcb_common[DSAF_COMM_DEV_NUM]; 318 struct hns_mac_cb *mac_cb[DSAF_MAX_PORT_NUM]; 319 struct dsaf_misc_op *misc_op; 320 321 struct dsaf_hw_stats hw_stats[DSAF_NODE_NUM]; 322 struct dsaf_int_stat int_stat; 323 /* make sure tcam table config spinlock */ 324 spinlock_t tcam_lock; 325 }; 326 327 static inline void *hns_dsaf_dev_priv(const struct dsaf_device *dsaf_dev) 328 { 329 return (void *)((u8 *)dsaf_dev + sizeof(*dsaf_dev)); 330 } 331 332 #define DSAF_TBL_TCAM_KEY_PORT_S 0 333 #define DSAF_TBL_TCAM_KEY_PORT_M (((1ULL << 4) - 1) << 0) 334 #define DSAF_TBL_TCAM_KEY_VLAN_S 4 335 #define DSAF_TBL_TCAM_KEY_VLAN_M (((1ULL << 12) - 1) << 4) 336 337 struct dsaf_drv_tbl_tcam_key { 338 union { 339 struct { 340 u8 mac_3; 341 u8 mac_2; 342 u8 mac_1; 343 u8 mac_0; 344 } bits; 345 346 u32 val; 347 } high; 348 union { 349 struct { 350 u16 port_vlan; 351 u8 mac_5; 352 u8 mac_4; 353 } bits; 354 355 u32 val; 356 } low; 357 }; 358 359 struct dsaf_drv_soft_mac_tbl { 360 struct dsaf_drv_tbl_tcam_key tcam_key; 361 u16 index; /*the entry's index in tcam tab*/ 362 }; 363 364 struct dsaf_drv_priv { 365 /* soft tab Mac key, for hardware tab*/ 366 struct dsaf_drv_soft_mac_tbl *soft_mac_tbl; 367 }; 368 369 static inline void hns_dsaf_tbl_tcam_addr_cfg(struct dsaf_device *dsaf_dev, 370 u32 tab_tcam_addr) 371 { 372 dsaf_set_dev_field(dsaf_dev, DSAF_TBL_TCAM_ADDR_0_REG, 373 DSAF_TBL_TCAM_ADDR_M, DSAF_TBL_TCAM_ADDR_S, 374 tab_tcam_addr); 375 } 376 377 static inline void hns_dsaf_tbl_tcam_load_pul(struct dsaf_device *dsaf_dev) 378 { 379 u32 o_tbl_pul; 380 381 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); 382 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 1); 383 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 384 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 0); 385 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 386 } 387 388 static inline void hns_dsaf_tbl_line_addr_cfg(struct dsaf_device *dsaf_dev, 389 u32 tab_line_addr) 390 { 391 dsaf_set_dev_field(dsaf_dev, DSAF_TBL_LINE_ADDR_0_REG, 392 DSAF_TBL_LINE_ADDR_M, DSAF_TBL_LINE_ADDR_S, 393 tab_line_addr); 394 } 395 396 static inline struct hnae_vf_cb *hns_ae_get_vf_cb( 397 struct hnae_handle *handle) 398 { 399 return container_of(handle, struct hnae_vf_cb, ae_handle); 400 } 401 402 int hns_dsaf_set_mac_uc_entry(struct dsaf_device *dsaf_dev, 403 struct dsaf_drv_mac_single_dest_entry *mac_entry); 404 int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev, 405 struct dsaf_drv_mac_single_dest_entry *mac_entry); 406 int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id, 407 u8 in_port_num, u8 *addr); 408 int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev, 409 struct dsaf_drv_mac_single_dest_entry *mac_entry); 410 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb); 411 412 int hns_dsaf_ae_init(struct dsaf_device *dsaf_dev); 413 void hns_dsaf_ae_uninit(struct dsaf_device *dsaf_dev); 414 415 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 inode_num); 416 417 int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset); 418 void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port); 419 void hns_dsaf_get_strings(int stringset, u8 **data, int port, 420 struct dsaf_device *dsaf_dev); 421 422 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data); 423 int hns_dsaf_get_regs_count(void); 424 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en); 425 void hns_dsaf_set_promisc_tcam(struct dsaf_device *dsaf_dev, 426 u32 port, bool enable); 427 428 void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id, 429 u32 *en); 430 int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id, 431 u32 en); 432 int hns_dsaf_rm_mac_addr( 433 struct dsaf_device *dsaf_dev, 434 struct dsaf_drv_mac_single_dest_entry *mac_entry); 435 436 int hns_dsaf_clr_mac_mc_port(struct dsaf_device *dsaf_dev, 437 u8 mac_id, u8 port_num); 438 int hns_dsaf_wait_pkt_clean(struct dsaf_device *dsaf_dev, int port); 439 440 #endif /* __HNS_DSAF_MAIN_H__ */ 441