1 /* 2 * Copyright (c) 2014-2015 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/device.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/netdevice.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/of_irq.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/vmalloc.h> 24 25 #include "hns_dsaf_mac.h" 26 #include "hns_dsaf_main.h" 27 #include "hns_dsaf_ppe.h" 28 #include "hns_dsaf_rcb.h" 29 #include "hns_dsaf_misc.h" 30 31 const char *g_dsaf_mode_match[DSAF_MODE_MAX] = { 32 [DSAF_MODE_DISABLE_2PORT_64VM] = "2port-64vf", 33 [DSAF_MODE_DISABLE_6PORT_0VM] = "6port-16rss", 34 [DSAF_MODE_DISABLE_6PORT_16VM] = "6port-16vf", 35 [DSAF_MODE_DISABLE_SP] = "single-port", 36 }; 37 38 static const struct acpi_device_id hns_dsaf_acpi_match[] = { 39 { "HISI00B1", 0 }, 40 { "HISI00B2", 0 }, 41 { }, 42 }; 43 MODULE_DEVICE_TABLE(acpi, hns_dsaf_acpi_match); 44 45 int hns_dsaf_get_cfg(struct dsaf_device *dsaf_dev) 46 { 47 int ret, i; 48 u32 desc_num; 49 u32 buf_size; 50 u32 reset_offset = 0; 51 u32 res_idx = 0; 52 const char *mode_str; 53 struct regmap *syscon; 54 struct resource *res; 55 struct device_node *np = dsaf_dev->dev->of_node, *np_temp; 56 struct platform_device *pdev = to_platform_device(dsaf_dev->dev); 57 58 if (dev_of_node(dsaf_dev->dev)) { 59 if (of_device_is_compatible(np, "hisilicon,hns-dsaf-v1")) 60 dsaf_dev->dsaf_ver = AE_VERSION_1; 61 else 62 dsaf_dev->dsaf_ver = AE_VERSION_2; 63 } else if (is_acpi_node(dsaf_dev->dev->fwnode)) { 64 if (acpi_dev_found(hns_dsaf_acpi_match[0].id)) 65 dsaf_dev->dsaf_ver = AE_VERSION_1; 66 else if (acpi_dev_found(hns_dsaf_acpi_match[1].id)) 67 dsaf_dev->dsaf_ver = AE_VERSION_2; 68 else 69 return -ENXIO; 70 } else { 71 dev_err(dsaf_dev->dev, "cannot get cfg data from of or acpi\n"); 72 return -ENXIO; 73 } 74 75 ret = device_property_read_string(dsaf_dev->dev, "mode", &mode_str); 76 if (ret) { 77 dev_err(dsaf_dev->dev, "get dsaf mode fail, ret=%d!\n", ret); 78 return ret; 79 } 80 for (i = 0; i < DSAF_MODE_MAX; i++) { 81 if (g_dsaf_mode_match[i] && 82 !strcmp(mode_str, g_dsaf_mode_match[i])) 83 break; 84 } 85 if (i >= DSAF_MODE_MAX || 86 i == DSAF_MODE_INVALID || i == DSAF_MODE_ENABLE) { 87 dev_err(dsaf_dev->dev, 88 "%s prs mode str fail!\n", dsaf_dev->ae_dev.name); 89 return -EINVAL; 90 } 91 dsaf_dev->dsaf_mode = (enum dsaf_mode)i; 92 93 if (dsaf_dev->dsaf_mode > DSAF_MODE_ENABLE) 94 dsaf_dev->dsaf_en = HRD_DSAF_NO_DSAF_MODE; 95 else 96 dsaf_dev->dsaf_en = HRD_DSAF_MODE; 97 98 if ((i == DSAF_MODE_ENABLE_16VM) || 99 (i == DSAF_MODE_DISABLE_2PORT_8VM) || 100 (i == DSAF_MODE_DISABLE_6PORT_2VM)) 101 dsaf_dev->dsaf_tc_mode = HRD_DSAF_8TC_MODE; 102 else 103 dsaf_dev->dsaf_tc_mode = HRD_DSAF_4TC_MODE; 104 105 if (dev_of_node(dsaf_dev->dev)) { 106 np_temp = of_parse_phandle(np, "subctrl-syscon", 0); 107 syscon = syscon_node_to_regmap(np_temp); 108 of_node_put(np_temp); 109 if (IS_ERR_OR_NULL(syscon)) { 110 res = platform_get_resource(pdev, IORESOURCE_MEM, 111 res_idx++); 112 if (!res) { 113 dev_err(dsaf_dev->dev, "subctrl info is needed!\n"); 114 return -ENOMEM; 115 } 116 117 dsaf_dev->sc_base = devm_ioremap_resource(&pdev->dev, 118 res); 119 if (IS_ERR(dsaf_dev->sc_base)) 120 return PTR_ERR(dsaf_dev->sc_base); 121 122 res = platform_get_resource(pdev, IORESOURCE_MEM, 123 res_idx++); 124 if (!res) { 125 dev_err(dsaf_dev->dev, "serdes-ctrl info is needed!\n"); 126 return -ENOMEM; 127 } 128 129 dsaf_dev->sds_base = devm_ioremap_resource(&pdev->dev, 130 res); 131 if (IS_ERR(dsaf_dev->sds_base)) 132 return PTR_ERR(dsaf_dev->sds_base); 133 } else { 134 dsaf_dev->sub_ctrl = syscon; 135 } 136 } 137 138 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ppe-base"); 139 if (!res) { 140 res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx++); 141 if (!res) { 142 dev_err(dsaf_dev->dev, "ppe-base info is needed!\n"); 143 return -ENOMEM; 144 } 145 } 146 dsaf_dev->ppe_base = devm_ioremap_resource(&pdev->dev, res); 147 if (IS_ERR(dsaf_dev->ppe_base)) 148 return PTR_ERR(dsaf_dev->ppe_base); 149 dsaf_dev->ppe_paddr = res->start; 150 151 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) { 152 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 153 "dsaf-base"); 154 if (!res) { 155 res = platform_get_resource(pdev, IORESOURCE_MEM, 156 res_idx); 157 if (!res) { 158 dev_err(dsaf_dev->dev, 159 "dsaf-base info is needed!\n"); 160 return -ENOMEM; 161 } 162 } 163 dsaf_dev->io_base = devm_ioremap_resource(&pdev->dev, res); 164 if (IS_ERR(dsaf_dev->io_base)) 165 return PTR_ERR(dsaf_dev->io_base); 166 } 167 168 ret = device_property_read_u32(dsaf_dev->dev, "desc-num", &desc_num); 169 if (ret < 0 || desc_num < HNS_DSAF_MIN_DESC_CNT || 170 desc_num > HNS_DSAF_MAX_DESC_CNT) { 171 dev_err(dsaf_dev->dev, "get desc-num(%d) fail, ret=%d!\n", 172 desc_num, ret); 173 return -EINVAL; 174 } 175 dsaf_dev->desc_num = desc_num; 176 177 ret = device_property_read_u32(dsaf_dev->dev, "reset-field-offset", 178 &reset_offset); 179 if (ret < 0) { 180 dev_dbg(dsaf_dev->dev, 181 "get reset-field-offset fail, ret=%d!\r\n", ret); 182 } 183 dsaf_dev->reset_offset = reset_offset; 184 185 ret = device_property_read_u32(dsaf_dev->dev, "buf-size", &buf_size); 186 if (ret < 0) { 187 dev_err(dsaf_dev->dev, 188 "get buf-size fail, ret=%d!\r\n", ret); 189 return ret; 190 } 191 dsaf_dev->buf_size = buf_size; 192 193 dsaf_dev->buf_size_type = hns_rcb_buf_size2type(buf_size); 194 if (dsaf_dev->buf_size_type < 0) { 195 dev_err(dsaf_dev->dev, 196 "buf_size(%d) is wrong!\n", buf_size); 197 return -EINVAL; 198 } 199 200 dsaf_dev->misc_op = hns_misc_op_get(dsaf_dev); 201 if (!dsaf_dev->misc_op) 202 return -ENOMEM; 203 204 if (!dma_set_mask_and_coherent(dsaf_dev->dev, DMA_BIT_MASK(64ULL))) 205 dev_dbg(dsaf_dev->dev, "set mask to 64bit\n"); 206 else 207 dev_err(dsaf_dev->dev, "set mask to 64bit fail!\n"); 208 209 return 0; 210 } 211 212 /** 213 * hns_dsaf_sbm_link_sram_init_en - config dsaf_sbm_init_en 214 * @dsaf_id: dsa fabric id 215 */ 216 static void hns_dsaf_sbm_link_sram_init_en(struct dsaf_device *dsaf_dev) 217 { 218 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, DSAF_CFG_SBM_INIT_S, 1); 219 } 220 221 /** 222 * hns_dsaf_reg_cnt_clr_ce - config hns_dsaf_reg_cnt_clr_ce 223 * @dsaf_id: dsa fabric id 224 * @hns_dsaf_reg_cnt_clr_ce: config value 225 */ 226 static void 227 hns_dsaf_reg_cnt_clr_ce(struct dsaf_device *dsaf_dev, u32 reg_cnt_clr_ce) 228 { 229 dsaf_set_dev_bit(dsaf_dev, DSAF_DSA_REG_CNT_CLR_CE_REG, 230 DSAF_CNT_CLR_CE_S, reg_cnt_clr_ce); 231 } 232 233 /** 234 * hns_ppe_qid_cfg - config ppe qid 235 * @dsaf_id: dsa fabric id 236 * @pppe_qid_cfg: value array 237 */ 238 static void 239 hns_dsaf_ppe_qid_cfg(struct dsaf_device *dsaf_dev, u32 qid_cfg) 240 { 241 u32 i; 242 243 for (i = 0; i < DSAF_COMM_CHN; i++) { 244 dsaf_set_dev_field(dsaf_dev, 245 DSAF_PPE_QID_CFG_0_REG + 0x0004 * i, 246 DSAF_PPE_QID_CFG_M, DSAF_PPE_QID_CFG_S, 247 qid_cfg); 248 } 249 } 250 251 static void hns_dsaf_mix_def_qid_cfg(struct dsaf_device *dsaf_dev) 252 { 253 u16 max_q_per_vf, max_vfn; 254 u32 q_id, q_num_per_port; 255 u32 i; 256 257 hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf); 258 q_num_per_port = max_vfn * max_q_per_vf; 259 260 for (i = 0, q_id = 0; i < DSAF_SERVICE_NW_NUM; i++) { 261 dsaf_set_dev_field(dsaf_dev, 262 DSAF_MIX_DEF_QID_0_REG + 0x0004 * i, 263 0xff, 0, q_id); 264 q_id += q_num_per_port; 265 } 266 } 267 268 static void hns_dsaf_inner_qid_cfg(struct dsaf_device *dsaf_dev) 269 { 270 u16 max_q_per_vf, max_vfn; 271 u32 q_id, q_num_per_port; 272 u32 mac_id; 273 274 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) 275 return; 276 277 hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf); 278 q_num_per_port = max_vfn * max_q_per_vf; 279 280 for (mac_id = 0, q_id = 0; mac_id < DSAF_SERVICE_NW_NUM; mac_id++) { 281 dsaf_set_dev_field(dsaf_dev, 282 DSAFV2_SERDES_LBK_0_REG + 4 * mac_id, 283 DSAFV2_SERDES_LBK_QID_M, 284 DSAFV2_SERDES_LBK_QID_S, 285 q_id); 286 q_id += q_num_per_port; 287 } 288 } 289 290 /** 291 * hns_dsaf_sw_port_type_cfg - cfg sw type 292 * @dsaf_id: dsa fabric id 293 * @psw_port_type: array 294 */ 295 static void hns_dsaf_sw_port_type_cfg(struct dsaf_device *dsaf_dev, 296 enum dsaf_sw_port_type port_type) 297 { 298 u32 i; 299 300 for (i = 0; i < DSAF_SW_PORT_NUM; i++) { 301 dsaf_set_dev_field(dsaf_dev, 302 DSAF_SW_PORT_TYPE_0_REG + 0x0004 * i, 303 DSAF_SW_PORT_TYPE_M, DSAF_SW_PORT_TYPE_S, 304 port_type); 305 } 306 } 307 308 /** 309 * hns_dsaf_stp_port_type_cfg - cfg stp type 310 * @dsaf_id: dsa fabric id 311 * @pstp_port_type: array 312 */ 313 static void hns_dsaf_stp_port_type_cfg(struct dsaf_device *dsaf_dev, 314 enum dsaf_stp_port_type port_type) 315 { 316 u32 i; 317 318 for (i = 0; i < DSAF_COMM_CHN; i++) { 319 dsaf_set_dev_field(dsaf_dev, 320 DSAF_STP_PORT_TYPE_0_REG + 0x0004 * i, 321 DSAF_STP_PORT_TYPE_M, DSAF_STP_PORT_TYPE_S, 322 port_type); 323 } 324 } 325 326 #define HNS_DSAF_SBM_NUM(dev) \ 327 (AE_IS_VER1((dev)->dsaf_ver) ? DSAF_SBM_NUM : DSAFV2_SBM_NUM) 328 /** 329 * hns_dsaf_sbm_cfg - config sbm 330 * @dsaf_id: dsa fabric id 331 */ 332 static void hns_dsaf_sbm_cfg(struct dsaf_device *dsaf_dev) 333 { 334 u32 o_sbm_cfg; 335 u32 i; 336 337 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { 338 o_sbm_cfg = dsaf_read_dev(dsaf_dev, 339 DSAF_SBM_CFG_REG_0_REG + 0x80 * i); 340 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_EN_S, 1); 341 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_SHCUT_EN_S, 0); 342 dsaf_write_dev(dsaf_dev, 343 DSAF_SBM_CFG_REG_0_REG + 0x80 * i, o_sbm_cfg); 344 } 345 } 346 347 /** 348 * hns_dsaf_sbm_cfg_mib_en - config sbm 349 * @dsaf_id: dsa fabric id 350 */ 351 static int hns_dsaf_sbm_cfg_mib_en(struct dsaf_device *dsaf_dev) 352 { 353 u32 sbm_cfg_mib_en; 354 u32 i; 355 u32 reg; 356 u32 read_cnt; 357 358 /* validate configure by setting SBM_CFG_MIB_EN bit from 0 to 1. */ 359 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { 360 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i; 361 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 0); 362 } 363 364 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { 365 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i; 366 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 1); 367 } 368 369 /* waitint for all sbm enable finished */ 370 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { 371 read_cnt = 0; 372 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i; 373 do { 374 udelay(1); 375 sbm_cfg_mib_en = dsaf_get_dev_bit( 376 dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S); 377 read_cnt++; 378 } while (sbm_cfg_mib_en == 0 && 379 read_cnt < DSAF_CFG_READ_CNT); 380 381 if (sbm_cfg_mib_en == 0) { 382 dev_err(dsaf_dev->dev, 383 "sbm_cfg_mib_en fail,%s,sbm_num=%d\n", 384 dsaf_dev->ae_dev.name, i); 385 return -ENODEV; 386 } 387 } 388 389 return 0; 390 } 391 392 /** 393 * hns_dsaf_sbm_bp_wl_cfg - config sbm 394 * @dsaf_id: dsa fabric id 395 */ 396 static void hns_dsaf_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev) 397 { 398 u32 o_sbm_bp_cfg; 399 u32 reg; 400 u32 i; 401 402 /* XGE */ 403 for (i = 0; i < DSAF_XGE_NUM; i++) { 404 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i; 405 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 406 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M, 407 DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S, 512); 408 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M, 409 DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0); 410 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M, 411 DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0); 412 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 413 414 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i; 415 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 416 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M, 417 DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0); 418 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M, 419 DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0); 420 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 421 422 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i; 423 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 424 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M, 425 DSAF_SBM_CFG2_SET_BUF_NUM_S, 104); 426 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M, 427 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 128); 428 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 429 430 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i; 431 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 432 dsaf_set_field(o_sbm_bp_cfg, 433 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M, 434 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 110); 435 dsaf_set_field(o_sbm_bp_cfg, 436 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M, 437 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 160); 438 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 439 440 /* for no enable pfc mode */ 441 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i; 442 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 443 dsaf_set_field(o_sbm_bp_cfg, 444 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M, 445 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 128); 446 dsaf_set_field(o_sbm_bp_cfg, 447 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M, 448 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 192); 449 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 450 } 451 452 /* PPE */ 453 for (i = 0; i < DSAF_COMM_CHN; i++) { 454 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i; 455 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 456 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M, 457 DSAF_SBM_CFG2_SET_BUF_NUM_S, 10); 458 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M, 459 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 12); 460 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 461 } 462 463 /* RoCEE */ 464 for (i = 0; i < DSAF_COMM_CHN; i++) { 465 reg = DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i; 466 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 467 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M, 468 DSAF_SBM_CFG2_SET_BUF_NUM_S, 2); 469 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M, 470 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 4); 471 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 472 } 473 } 474 475 static void hns_dsafv2_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev) 476 { 477 u32 o_sbm_bp_cfg; 478 u32 reg; 479 u32 i; 480 481 /* XGE */ 482 for (i = 0; i < DSAFV2_SBM_XGE_CHN; i++) { 483 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i; 484 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 485 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M, 486 DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S, 256); 487 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M, 488 DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0); 489 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M, 490 DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0); 491 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 492 493 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i; 494 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 495 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M, 496 DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0); 497 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M, 498 DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0); 499 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 500 501 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i; 502 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 503 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_SET_BUF_NUM_M, 504 DSAFV2_SBM_CFG2_SET_BUF_NUM_S, 104); 505 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_RESET_BUF_NUM_M, 506 DSAFV2_SBM_CFG2_RESET_BUF_NUM_S, 128); 507 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 508 509 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i; 510 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 511 dsaf_set_field(o_sbm_bp_cfg, 512 DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M, 513 DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 48); 514 dsaf_set_field(o_sbm_bp_cfg, 515 DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M, 516 DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 80); 517 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 518 519 /* for no enable pfc mode */ 520 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i; 521 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 522 dsaf_set_field(o_sbm_bp_cfg, 523 DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M, 524 DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S, 192); 525 dsaf_set_field(o_sbm_bp_cfg, 526 DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M, 527 DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S, 240); 528 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 529 } 530 531 /* PPE */ 532 for (i = 0; i < DSAFV2_SBM_PPE_CHN; i++) { 533 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i; 534 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 535 dsaf_set_field(o_sbm_bp_cfg, 536 DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_M, 537 DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_S, 2); 538 dsaf_set_field(o_sbm_bp_cfg, 539 DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_M, 540 DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_S, 3); 541 dsaf_set_field(o_sbm_bp_cfg, 542 DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_M, 543 DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_S, 52); 544 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 545 } 546 547 /* RoCEE */ 548 for (i = 0; i < DASFV2_ROCEE_CRD_NUM; i++) { 549 reg = DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i; 550 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 551 dsaf_set_field(o_sbm_bp_cfg, 552 DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_M, 553 DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_S, 2); 554 dsaf_set_field(o_sbm_bp_cfg, 555 DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_M, 556 DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_S, 4); 557 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 558 } 559 } 560 561 /** 562 * hns_dsaf_voq_bp_all_thrd_cfg - voq 563 * @dsaf_id: dsa fabric id 564 */ 565 static void hns_dsaf_voq_bp_all_thrd_cfg(struct dsaf_device *dsaf_dev) 566 { 567 u32 voq_bp_all_thrd; 568 u32 i; 569 570 for (i = 0; i < DSAF_VOQ_NUM; i++) { 571 voq_bp_all_thrd = dsaf_read_dev( 572 dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i); 573 if (i < DSAF_XGE_NUM) { 574 dsaf_set_field(voq_bp_all_thrd, 575 DSAF_VOQ_BP_ALL_DOWNTHRD_M, 576 DSAF_VOQ_BP_ALL_DOWNTHRD_S, 930); 577 dsaf_set_field(voq_bp_all_thrd, 578 DSAF_VOQ_BP_ALL_UPTHRD_M, 579 DSAF_VOQ_BP_ALL_UPTHRD_S, 950); 580 } else { 581 dsaf_set_field(voq_bp_all_thrd, 582 DSAF_VOQ_BP_ALL_DOWNTHRD_M, 583 DSAF_VOQ_BP_ALL_DOWNTHRD_S, 220); 584 dsaf_set_field(voq_bp_all_thrd, 585 DSAF_VOQ_BP_ALL_UPTHRD_M, 586 DSAF_VOQ_BP_ALL_UPTHRD_S, 230); 587 } 588 dsaf_write_dev( 589 dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i, 590 voq_bp_all_thrd); 591 } 592 } 593 594 /** 595 * hns_dsaf_tbl_tcam_data_cfg - tbl 596 * @dsaf_id: dsa fabric id 597 * @ptbl_tcam_data: addr 598 */ 599 static void hns_dsaf_tbl_tcam_data_cfg( 600 struct dsaf_device *dsaf_dev, 601 struct dsaf_tbl_tcam_data *ptbl_tcam_data) 602 { 603 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_LOW_0_REG, 604 ptbl_tcam_data->tbl_tcam_data_low); 605 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_HIGH_0_REG, 606 ptbl_tcam_data->tbl_tcam_data_high); 607 } 608 609 /** 610 * dsaf_tbl_tcam_mcast_cfg - tbl 611 * @dsaf_id: dsa fabric id 612 * @ptbl_tcam_mcast: addr 613 */ 614 static void hns_dsaf_tbl_tcam_mcast_cfg( 615 struct dsaf_device *dsaf_dev, 616 struct dsaf_tbl_tcam_mcast_cfg *mcast) 617 { 618 u32 mcast_cfg4; 619 620 mcast_cfg4 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG); 621 dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S, 622 mcast->tbl_mcast_item_vld); 623 dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_OLD_EN_S, 624 mcast->tbl_mcast_old_en); 625 dsaf_set_field(mcast_cfg4, DSAF_TBL_MCAST_CFG4_VM128_112_M, 626 DSAF_TBL_MCAST_CFG4_VM128_112_S, 627 mcast->tbl_mcast_port_msk[4]); 628 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, mcast_cfg4); 629 630 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 631 mcast->tbl_mcast_port_msk[3]); 632 633 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 634 mcast->tbl_mcast_port_msk[2]); 635 636 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 637 mcast->tbl_mcast_port_msk[1]); 638 639 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 640 mcast->tbl_mcast_port_msk[0]); 641 } 642 643 /** 644 * hns_dsaf_tbl_tcam_ucast_cfg - tbl 645 * @dsaf_id: dsa fabric id 646 * @ptbl_tcam_ucast: addr 647 */ 648 static void hns_dsaf_tbl_tcam_ucast_cfg( 649 struct dsaf_device *dsaf_dev, 650 struct dsaf_tbl_tcam_ucast_cfg *tbl_tcam_ucast) 651 { 652 u32 ucast_cfg1; 653 654 ucast_cfg1 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG); 655 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S, 656 tbl_tcam_ucast->tbl_ucast_mac_discard); 657 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_ITEM_VLD_S, 658 tbl_tcam_ucast->tbl_ucast_item_vld); 659 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OLD_EN_S, 660 tbl_tcam_ucast->tbl_ucast_old_en); 661 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_DVC_S, 662 tbl_tcam_ucast->tbl_ucast_dvc); 663 dsaf_set_field(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OUT_PORT_M, 664 DSAF_TBL_UCAST_CFG1_OUT_PORT_S, 665 tbl_tcam_ucast->tbl_ucast_out_port); 666 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG, ucast_cfg1); 667 } 668 669 /** 670 * hns_dsaf_tbl_line_cfg - tbl 671 * @dsaf_id: dsa fabric id 672 * @ptbl_lin: addr 673 */ 674 static void hns_dsaf_tbl_line_cfg(struct dsaf_device *dsaf_dev, 675 struct dsaf_tbl_line_cfg *tbl_lin) 676 { 677 u32 tbl_line; 678 679 tbl_line = dsaf_read_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG); 680 dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_MAC_DISCARD_S, 681 tbl_lin->tbl_line_mac_discard); 682 dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_DVC_S, 683 tbl_lin->tbl_line_dvc); 684 dsaf_set_field(tbl_line, DSAF_TBL_LINE_CFG_OUT_PORT_M, 685 DSAF_TBL_LINE_CFG_OUT_PORT_S, 686 tbl_lin->tbl_line_out_port); 687 dsaf_write_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG, tbl_line); 688 } 689 690 /** 691 * hns_dsaf_tbl_tcam_mcast_pul - tbl 692 * @dsaf_id: dsa fabric id 693 */ 694 static void hns_dsaf_tbl_tcam_mcast_pul(struct dsaf_device *dsaf_dev) 695 { 696 u32 o_tbl_pul; 697 698 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); 699 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1); 700 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 701 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0); 702 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 703 } 704 705 /** 706 * hns_dsaf_tbl_line_pul - tbl 707 * @dsaf_id: dsa fabric id 708 */ 709 static void hns_dsaf_tbl_line_pul(struct dsaf_device *dsaf_dev) 710 { 711 u32 tbl_pul; 712 713 tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); 714 dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 1); 715 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul); 716 dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 0); 717 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul); 718 } 719 720 /** 721 * hns_dsaf_tbl_tcam_data_mcast_pul - tbl 722 * @dsaf_id: dsa fabric id 723 */ 724 static void hns_dsaf_tbl_tcam_data_mcast_pul( 725 struct dsaf_device *dsaf_dev) 726 { 727 u32 o_tbl_pul; 728 729 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); 730 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1); 731 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1); 732 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 733 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0); 734 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0); 735 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 736 } 737 738 /** 739 * hns_dsaf_tbl_tcam_data_ucast_pul - tbl 740 * @dsaf_id: dsa fabric id 741 */ 742 static void hns_dsaf_tbl_tcam_data_ucast_pul( 743 struct dsaf_device *dsaf_dev) 744 { 745 u32 o_tbl_pul; 746 747 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); 748 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1); 749 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 1); 750 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 751 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0); 752 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 0); 753 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 754 } 755 756 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en) 757 { 758 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) 759 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, 760 DSAF_CFG_MIX_MODE_S, !!en); 761 } 762 763 void hns_dsaf_set_inner_lb(struct dsaf_device *dsaf_dev, u32 mac_id, u32 en) 764 { 765 if (AE_IS_VER1(dsaf_dev->dsaf_ver) || 766 dsaf_dev->mac_cb[mac_id]->mac_type == HNAE_PORT_DEBUG) 767 return; 768 769 dsaf_set_dev_bit(dsaf_dev, DSAFV2_SERDES_LBK_0_REG + 4 * mac_id, 770 DSAFV2_SERDES_LBK_EN_B, !!en); 771 } 772 773 /** 774 * hns_dsaf_tbl_stat_en - tbl 775 * @dsaf_id: dsa fabric id 776 * @ptbl_stat_en: addr 777 */ 778 static void hns_dsaf_tbl_stat_en(struct dsaf_device *dsaf_dev) 779 { 780 u32 o_tbl_ctrl; 781 782 o_tbl_ctrl = dsaf_read_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG); 783 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S, 1); 784 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_UC_LKUP_NUM_EN_S, 1); 785 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_MC_LKUP_NUM_EN_S, 1); 786 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_BC_LKUP_NUM_EN_S, 1); 787 dsaf_write_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG, o_tbl_ctrl); 788 } 789 790 /** 791 * hns_dsaf_rocee_bp_en - rocee back press enable 792 * @dsaf_id: dsa fabric id 793 */ 794 static void hns_dsaf_rocee_bp_en(struct dsaf_device *dsaf_dev) 795 { 796 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) 797 dsaf_set_dev_bit(dsaf_dev, DSAF_XGE_CTRL_SIG_CFG_0_REG, 798 DSAF_FC_XGE_TX_PAUSE_S, 1); 799 } 800 801 /* set msk for dsaf exception irq*/ 802 static void hns_dsaf_int_xge_msk_set(struct dsaf_device *dsaf_dev, 803 u32 chnn_num, u32 mask_set) 804 { 805 dsaf_write_dev(dsaf_dev, 806 DSAF_XGE_INT_MSK_0_REG + 0x4 * chnn_num, mask_set); 807 } 808 809 static void hns_dsaf_int_ppe_msk_set(struct dsaf_device *dsaf_dev, 810 u32 chnn_num, u32 msk_set) 811 { 812 dsaf_write_dev(dsaf_dev, 813 DSAF_PPE_INT_MSK_0_REG + 0x4 * chnn_num, msk_set); 814 } 815 816 static void hns_dsaf_int_rocee_msk_set(struct dsaf_device *dsaf_dev, 817 u32 chnn, u32 msk_set) 818 { 819 dsaf_write_dev(dsaf_dev, 820 DSAF_ROCEE_INT_MSK_0_REG + 0x4 * chnn, msk_set); 821 } 822 823 static void 824 hns_dsaf_int_tbl_msk_set(struct dsaf_device *dsaf_dev, u32 msk_set) 825 { 826 dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_MSK_0_REG, msk_set); 827 } 828 829 /* clr dsaf exception irq*/ 830 static void hns_dsaf_int_xge_src_clr(struct dsaf_device *dsaf_dev, 831 u32 chnn_num, u32 int_src) 832 { 833 dsaf_write_dev(dsaf_dev, 834 DSAF_XGE_INT_SRC_0_REG + 0x4 * chnn_num, int_src); 835 } 836 837 static void hns_dsaf_int_ppe_src_clr(struct dsaf_device *dsaf_dev, 838 u32 chnn, u32 int_src) 839 { 840 dsaf_write_dev(dsaf_dev, 841 DSAF_PPE_INT_SRC_0_REG + 0x4 * chnn, int_src); 842 } 843 844 static void hns_dsaf_int_rocee_src_clr(struct dsaf_device *dsaf_dev, 845 u32 chnn, u32 int_src) 846 { 847 dsaf_write_dev(dsaf_dev, 848 DSAF_ROCEE_INT_SRC_0_REG + 0x4 * chnn, int_src); 849 } 850 851 static void hns_dsaf_int_tbl_src_clr(struct dsaf_device *dsaf_dev, 852 u32 int_src) 853 { 854 dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_SRC_0_REG, int_src); 855 } 856 857 /** 858 * hns_dsaf_single_line_tbl_cfg - INT 859 * @dsaf_id: dsa fabric id 860 * @address: 861 * @ptbl_line: 862 */ 863 static void hns_dsaf_single_line_tbl_cfg( 864 struct dsaf_device *dsaf_dev, 865 u32 address, struct dsaf_tbl_line_cfg *ptbl_line) 866 { 867 spin_lock_bh(&dsaf_dev->tcam_lock); 868 869 /*Write Addr*/ 870 hns_dsaf_tbl_line_addr_cfg(dsaf_dev, address); 871 872 /*Write Line*/ 873 hns_dsaf_tbl_line_cfg(dsaf_dev, ptbl_line); 874 875 /*Write Plus*/ 876 hns_dsaf_tbl_line_pul(dsaf_dev); 877 878 spin_unlock_bh(&dsaf_dev->tcam_lock); 879 } 880 881 /** 882 * hns_dsaf_tcam_uc_cfg - INT 883 * @dsaf_id: dsa fabric id 884 * @address, 885 * @ptbl_tcam_data, 886 */ 887 static void hns_dsaf_tcam_uc_cfg( 888 struct dsaf_device *dsaf_dev, u32 address, 889 struct dsaf_tbl_tcam_data *ptbl_tcam_data, 890 struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast) 891 { 892 spin_lock_bh(&dsaf_dev->tcam_lock); 893 894 /*Write Addr*/ 895 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 896 /*Write Tcam Data*/ 897 hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data); 898 /*Write Tcam Ucast*/ 899 hns_dsaf_tbl_tcam_ucast_cfg(dsaf_dev, ptbl_tcam_ucast); 900 /*Write Plus*/ 901 hns_dsaf_tbl_tcam_data_ucast_pul(dsaf_dev); 902 903 spin_unlock_bh(&dsaf_dev->tcam_lock); 904 } 905 906 /** 907 * hns_dsaf_tcam_mc_cfg - INT 908 * @dsaf_id: dsa fabric id 909 * @address, 910 * @ptbl_tcam_data, 911 * @ptbl_tcam_mcast, 912 */ 913 static void hns_dsaf_tcam_mc_cfg( 914 struct dsaf_device *dsaf_dev, u32 address, 915 struct dsaf_tbl_tcam_data *ptbl_tcam_data, 916 struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast) 917 { 918 spin_lock_bh(&dsaf_dev->tcam_lock); 919 920 /*Write Addr*/ 921 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 922 /*Write Tcam Data*/ 923 hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data); 924 /*Write Tcam Mcast*/ 925 hns_dsaf_tbl_tcam_mcast_cfg(dsaf_dev, ptbl_tcam_mcast); 926 /*Write Plus*/ 927 hns_dsaf_tbl_tcam_data_mcast_pul(dsaf_dev); 928 929 spin_unlock_bh(&dsaf_dev->tcam_lock); 930 } 931 932 /** 933 * hns_dsaf_tcam_mc_invld - INT 934 * @dsaf_id: dsa fabric id 935 * @address 936 */ 937 static void hns_dsaf_tcam_mc_invld(struct dsaf_device *dsaf_dev, u32 address) 938 { 939 spin_lock_bh(&dsaf_dev->tcam_lock); 940 941 /*Write Addr*/ 942 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 943 944 /*write tcam mcast*/ 945 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 0); 946 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 0); 947 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 0); 948 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 0); 949 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, 0); 950 951 /*Write Plus*/ 952 hns_dsaf_tbl_tcam_mcast_pul(dsaf_dev); 953 954 spin_unlock_bh(&dsaf_dev->tcam_lock); 955 } 956 957 /** 958 * hns_dsaf_tcam_uc_get - INT 959 * @dsaf_id: dsa fabric id 960 * @address 961 * @ptbl_tcam_data 962 * @ptbl_tcam_ucast 963 */ 964 static void hns_dsaf_tcam_uc_get( 965 struct dsaf_device *dsaf_dev, u32 address, 966 struct dsaf_tbl_tcam_data *ptbl_tcam_data, 967 struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast) 968 { 969 u32 tcam_read_data0; 970 u32 tcam_read_data4; 971 972 spin_lock_bh(&dsaf_dev->tcam_lock); 973 974 /*Write Addr*/ 975 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 976 977 /*read tcam item puls*/ 978 hns_dsaf_tbl_tcam_load_pul(dsaf_dev); 979 980 /*read tcam data*/ 981 ptbl_tcam_data->tbl_tcam_data_high 982 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG); 983 ptbl_tcam_data->tbl_tcam_data_low 984 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG); 985 986 /*read tcam mcast*/ 987 tcam_read_data0 = dsaf_read_dev(dsaf_dev, 988 DSAF_TBL_TCAM_RAM_RDATA0_0_REG); 989 tcam_read_data4 = dsaf_read_dev(dsaf_dev, 990 DSAF_TBL_TCAM_RAM_RDATA4_0_REG); 991 992 ptbl_tcam_ucast->tbl_ucast_item_vld 993 = dsaf_get_bit(tcam_read_data4, 994 DSAF_TBL_MCAST_CFG4_ITEM_VLD_S); 995 ptbl_tcam_ucast->tbl_ucast_old_en 996 = dsaf_get_bit(tcam_read_data4, DSAF_TBL_MCAST_CFG4_OLD_EN_S); 997 ptbl_tcam_ucast->tbl_ucast_mac_discard 998 = dsaf_get_bit(tcam_read_data0, 999 DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S); 1000 ptbl_tcam_ucast->tbl_ucast_out_port 1001 = dsaf_get_field(tcam_read_data0, 1002 DSAF_TBL_UCAST_CFG1_OUT_PORT_M, 1003 DSAF_TBL_UCAST_CFG1_OUT_PORT_S); 1004 ptbl_tcam_ucast->tbl_ucast_dvc 1005 = dsaf_get_bit(tcam_read_data0, DSAF_TBL_UCAST_CFG1_DVC_S); 1006 1007 spin_unlock_bh(&dsaf_dev->tcam_lock); 1008 } 1009 1010 /** 1011 * hns_dsaf_tcam_mc_get - INT 1012 * @dsaf_id: dsa fabric id 1013 * @address 1014 * @ptbl_tcam_data 1015 * @ptbl_tcam_ucast 1016 */ 1017 static void hns_dsaf_tcam_mc_get( 1018 struct dsaf_device *dsaf_dev, u32 address, 1019 struct dsaf_tbl_tcam_data *ptbl_tcam_data, 1020 struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast) 1021 { 1022 u32 data_tmp; 1023 1024 spin_lock_bh(&dsaf_dev->tcam_lock); 1025 1026 /*Write Addr*/ 1027 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 1028 1029 /*read tcam item puls*/ 1030 hns_dsaf_tbl_tcam_load_pul(dsaf_dev); 1031 1032 /*read tcam data*/ 1033 ptbl_tcam_data->tbl_tcam_data_high = 1034 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG); 1035 ptbl_tcam_data->tbl_tcam_data_low = 1036 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG); 1037 1038 /*read tcam mcast*/ 1039 ptbl_tcam_mcast->tbl_mcast_port_msk[0] = 1040 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG); 1041 ptbl_tcam_mcast->tbl_mcast_port_msk[1] = 1042 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG); 1043 ptbl_tcam_mcast->tbl_mcast_port_msk[2] = 1044 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG); 1045 ptbl_tcam_mcast->tbl_mcast_port_msk[3] = 1046 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG); 1047 1048 data_tmp = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG); 1049 ptbl_tcam_mcast->tbl_mcast_item_vld = 1050 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S); 1051 ptbl_tcam_mcast->tbl_mcast_old_en = 1052 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_OLD_EN_S); 1053 ptbl_tcam_mcast->tbl_mcast_port_msk[4] = 1054 dsaf_get_field(data_tmp, DSAF_TBL_MCAST_CFG4_VM128_112_M, 1055 DSAF_TBL_MCAST_CFG4_VM128_112_S); 1056 1057 spin_unlock_bh(&dsaf_dev->tcam_lock); 1058 } 1059 1060 /** 1061 * hns_dsaf_tbl_line_init - INT 1062 * @dsaf_id: dsa fabric id 1063 */ 1064 static void hns_dsaf_tbl_line_init(struct dsaf_device *dsaf_dev) 1065 { 1066 u32 i; 1067 /* defaultly set all lineal mac table entry resulting discard */ 1068 struct dsaf_tbl_line_cfg tbl_line[] = {{1, 0, 0} }; 1069 1070 for (i = 0; i < DSAF_LINE_SUM; i++) 1071 hns_dsaf_single_line_tbl_cfg(dsaf_dev, i, tbl_line); 1072 } 1073 1074 /** 1075 * hns_dsaf_tbl_tcam_init - INT 1076 * @dsaf_id: dsa fabric id 1077 */ 1078 static void hns_dsaf_tbl_tcam_init(struct dsaf_device *dsaf_dev) 1079 { 1080 u32 i; 1081 struct dsaf_tbl_tcam_data tcam_data[] = {{0, 0} }; 1082 struct dsaf_tbl_tcam_ucast_cfg tcam_ucast[] = {{0, 0, 0, 0, 0} }; 1083 1084 /*tcam tbl*/ 1085 for (i = 0; i < DSAF_TCAM_SUM; i++) 1086 hns_dsaf_tcam_uc_cfg(dsaf_dev, i, tcam_data, tcam_ucast); 1087 } 1088 1089 /** 1090 * hns_dsaf_pfc_en_cfg - dsaf pfc pause cfg 1091 * @mac_cb: mac contrl block 1092 */ 1093 static void hns_dsaf_pfc_en_cfg(struct dsaf_device *dsaf_dev, 1094 int mac_id, int tc_en) 1095 { 1096 dsaf_write_dev(dsaf_dev, DSAF_PFC_EN_0_REG + mac_id * 4, tc_en); 1097 } 1098 1099 static void hns_dsaf_set_pfc_pause(struct dsaf_device *dsaf_dev, 1100 int mac_id, int tx_en, int rx_en) 1101 { 1102 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1103 if (!tx_en || !rx_en) 1104 dev_err(dsaf_dev->dev, "dsaf v1 can not close pfc!\n"); 1105 1106 return; 1107 } 1108 1109 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4, 1110 DSAF_PFC_PAUSE_RX_EN_B, !!rx_en); 1111 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4, 1112 DSAF_PFC_PAUSE_TX_EN_B, !!tx_en); 1113 } 1114 1115 int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id, 1116 u32 en) 1117 { 1118 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1119 if (!en) { 1120 dev_err(dsaf_dev->dev, "dsafv1 can't close rx_pause!\n"); 1121 return -EINVAL; 1122 } 1123 } 1124 1125 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4, 1126 DSAF_MAC_PAUSE_RX_EN_B, !!en); 1127 1128 return 0; 1129 } 1130 1131 void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id, 1132 u32 *en) 1133 { 1134 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) 1135 *en = 1; 1136 else 1137 *en = dsaf_get_dev_bit(dsaf_dev, 1138 DSAF_PAUSE_CFG_REG + mac_id * 4, 1139 DSAF_MAC_PAUSE_RX_EN_B); 1140 } 1141 1142 /** 1143 * hns_dsaf_tbl_tcam_init - INT 1144 * @dsaf_id: dsa fabric id 1145 * @dsaf_mode 1146 */ 1147 static void hns_dsaf_comm_init(struct dsaf_device *dsaf_dev) 1148 { 1149 u32 i; 1150 u32 o_dsaf_cfg; 1151 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver); 1152 1153 o_dsaf_cfg = dsaf_read_dev(dsaf_dev, DSAF_CFG_0_REG); 1154 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_EN_S, dsaf_dev->dsaf_en); 1155 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_TC_MODE_S, dsaf_dev->dsaf_tc_mode); 1156 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_CRC_EN_S, 0); 1157 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_MIX_MODE_S, 0); 1158 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_LOCA_ADDR_EN_S, 0); 1159 dsaf_write_dev(dsaf_dev, DSAF_CFG_0_REG, o_dsaf_cfg); 1160 1161 hns_dsaf_reg_cnt_clr_ce(dsaf_dev, 1); 1162 hns_dsaf_stp_port_type_cfg(dsaf_dev, DSAF_STP_PORT_TYPE_FORWARD); 1163 1164 /* set 22 queue per tx ppe engine, only used in switch mode */ 1165 hns_dsaf_ppe_qid_cfg(dsaf_dev, DSAF_DEFAUTL_QUEUE_NUM_PER_PPE); 1166 1167 /* set promisc def queue id */ 1168 hns_dsaf_mix_def_qid_cfg(dsaf_dev); 1169 1170 /* set inner loopback queue id */ 1171 hns_dsaf_inner_qid_cfg(dsaf_dev); 1172 1173 /* in non switch mode, set all port to access mode */ 1174 hns_dsaf_sw_port_type_cfg(dsaf_dev, DSAF_SW_PORT_TYPE_NON_VLAN); 1175 1176 /*set dsaf pfc to 0 for parseing rx pause*/ 1177 for (i = 0; i < DSAF_COMM_CHN; i++) { 1178 hns_dsaf_pfc_en_cfg(dsaf_dev, i, 0); 1179 hns_dsaf_set_pfc_pause(dsaf_dev, i, is_ver1, is_ver1); 1180 } 1181 1182 /*msk and clr exception irqs */ 1183 for (i = 0; i < DSAF_COMM_CHN; i++) { 1184 hns_dsaf_int_xge_src_clr(dsaf_dev, i, 0xfffffffful); 1185 hns_dsaf_int_ppe_src_clr(dsaf_dev, i, 0xfffffffful); 1186 hns_dsaf_int_rocee_src_clr(dsaf_dev, i, 0xfffffffful); 1187 1188 hns_dsaf_int_xge_msk_set(dsaf_dev, i, 0xfffffffful); 1189 hns_dsaf_int_ppe_msk_set(dsaf_dev, i, 0xfffffffful); 1190 hns_dsaf_int_rocee_msk_set(dsaf_dev, i, 0xfffffffful); 1191 } 1192 hns_dsaf_int_tbl_src_clr(dsaf_dev, 0xfffffffful); 1193 hns_dsaf_int_tbl_msk_set(dsaf_dev, 0xfffffffful); 1194 } 1195 1196 /** 1197 * hns_dsaf_inode_init - INT 1198 * @dsaf_id: dsa fabric id 1199 */ 1200 static void hns_dsaf_inode_init(struct dsaf_device *dsaf_dev) 1201 { 1202 u32 reg; 1203 u32 tc_cfg; 1204 u32 i; 1205 1206 if (dsaf_dev->dsaf_tc_mode == HRD_DSAF_4TC_MODE) 1207 tc_cfg = HNS_DSAF_I4TC_CFG; 1208 else 1209 tc_cfg = HNS_DSAF_I8TC_CFG; 1210 1211 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1212 for (i = 0; i < DSAF_INODE_NUM; i++) { 1213 reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i; 1214 dsaf_set_dev_field(dsaf_dev, reg, 1215 DSAF_INODE_IN_PORT_NUM_M, 1216 DSAF_INODE_IN_PORT_NUM_S, 1217 i % DSAF_XGE_NUM); 1218 } 1219 } else { 1220 for (i = 0; i < DSAF_PORT_TYPE_NUM; i++) { 1221 reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i; 1222 dsaf_set_dev_field(dsaf_dev, reg, 1223 DSAF_INODE_IN_PORT_NUM_M, 1224 DSAF_INODE_IN_PORT_NUM_S, 0); 1225 dsaf_set_dev_field(dsaf_dev, reg, 1226 DSAFV2_INODE_IN_PORT1_NUM_M, 1227 DSAFV2_INODE_IN_PORT1_NUM_S, 1); 1228 dsaf_set_dev_field(dsaf_dev, reg, 1229 DSAFV2_INODE_IN_PORT2_NUM_M, 1230 DSAFV2_INODE_IN_PORT2_NUM_S, 2); 1231 dsaf_set_dev_field(dsaf_dev, reg, 1232 DSAFV2_INODE_IN_PORT3_NUM_M, 1233 DSAFV2_INODE_IN_PORT3_NUM_S, 3); 1234 dsaf_set_dev_field(dsaf_dev, reg, 1235 DSAFV2_INODE_IN_PORT4_NUM_M, 1236 DSAFV2_INODE_IN_PORT4_NUM_S, 4); 1237 dsaf_set_dev_field(dsaf_dev, reg, 1238 DSAFV2_INODE_IN_PORT5_NUM_M, 1239 DSAFV2_INODE_IN_PORT5_NUM_S, 5); 1240 } 1241 } 1242 for (i = 0; i < DSAF_INODE_NUM; i++) { 1243 reg = DSAF_INODE_PRI_TC_CFG_0_REG + 0x80 * i; 1244 dsaf_write_dev(dsaf_dev, reg, tc_cfg); 1245 } 1246 } 1247 1248 /** 1249 * hns_dsaf_sbm_init - INT 1250 * @dsaf_id: dsa fabric id 1251 */ 1252 static int hns_dsaf_sbm_init(struct dsaf_device *dsaf_dev) 1253 { 1254 u32 flag; 1255 u32 finish_msk; 1256 u32 cnt = 0; 1257 int ret; 1258 1259 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1260 hns_dsaf_sbm_bp_wl_cfg(dsaf_dev); 1261 finish_msk = DSAF_SRAM_INIT_OVER_M; 1262 } else { 1263 hns_dsafv2_sbm_bp_wl_cfg(dsaf_dev); 1264 finish_msk = DSAFV2_SRAM_INIT_OVER_M; 1265 } 1266 1267 /* enable sbm chanel, disable sbm chanel shcut function*/ 1268 hns_dsaf_sbm_cfg(dsaf_dev); 1269 1270 /* enable sbm mib */ 1271 ret = hns_dsaf_sbm_cfg_mib_en(dsaf_dev); 1272 if (ret) { 1273 dev_err(dsaf_dev->dev, 1274 "hns_dsaf_sbm_cfg_mib_en fail,%s, ret=%d\n", 1275 dsaf_dev->ae_dev.name, ret); 1276 return ret; 1277 } 1278 1279 /* enable sbm initial link sram */ 1280 hns_dsaf_sbm_link_sram_init_en(dsaf_dev); 1281 1282 do { 1283 usleep_range(200, 210);/*udelay(200);*/ 1284 flag = dsaf_get_dev_field(dsaf_dev, DSAF_SRAM_INIT_OVER_0_REG, 1285 finish_msk, DSAF_SRAM_INIT_OVER_S); 1286 cnt++; 1287 } while (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S) && 1288 cnt < DSAF_CFG_READ_CNT); 1289 1290 if (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S)) { 1291 dev_err(dsaf_dev->dev, 1292 "hns_dsaf_sbm_init fail %s, flag=%d, cnt=%d\n", 1293 dsaf_dev->ae_dev.name, flag, cnt); 1294 return -ENODEV; 1295 } 1296 1297 hns_dsaf_rocee_bp_en(dsaf_dev); 1298 1299 return 0; 1300 } 1301 1302 /** 1303 * hns_dsaf_tbl_init - INT 1304 * @dsaf_id: dsa fabric id 1305 */ 1306 static void hns_dsaf_tbl_init(struct dsaf_device *dsaf_dev) 1307 { 1308 hns_dsaf_tbl_stat_en(dsaf_dev); 1309 1310 hns_dsaf_tbl_tcam_init(dsaf_dev); 1311 hns_dsaf_tbl_line_init(dsaf_dev); 1312 } 1313 1314 /** 1315 * hns_dsaf_voq_init - INT 1316 * @dsaf_id: dsa fabric id 1317 */ 1318 static void hns_dsaf_voq_init(struct dsaf_device *dsaf_dev) 1319 { 1320 hns_dsaf_voq_bp_all_thrd_cfg(dsaf_dev); 1321 } 1322 1323 /** 1324 * hns_dsaf_init_hw - init dsa fabric hardware 1325 * @dsaf_dev: dsa fabric device struct pointer 1326 */ 1327 static int hns_dsaf_init_hw(struct dsaf_device *dsaf_dev) 1328 { 1329 int ret; 1330 1331 dev_dbg(dsaf_dev->dev, 1332 "hns_dsaf_init_hw begin %s !\n", dsaf_dev->ae_dev.name); 1333 1334 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0); 1335 mdelay(10); 1336 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 1); 1337 1338 hns_dsaf_comm_init(dsaf_dev); 1339 1340 /*init XBAR_INODE*/ 1341 hns_dsaf_inode_init(dsaf_dev); 1342 1343 /*init SBM*/ 1344 ret = hns_dsaf_sbm_init(dsaf_dev); 1345 if (ret) 1346 return ret; 1347 1348 /*init TBL*/ 1349 hns_dsaf_tbl_init(dsaf_dev); 1350 1351 /*init VOQ*/ 1352 hns_dsaf_voq_init(dsaf_dev); 1353 1354 return 0; 1355 } 1356 1357 /** 1358 * hns_dsaf_remove_hw - uninit dsa fabric hardware 1359 * @dsaf_dev: dsa fabric device struct pointer 1360 */ 1361 static void hns_dsaf_remove_hw(struct dsaf_device *dsaf_dev) 1362 { 1363 /*reset*/ 1364 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0); 1365 } 1366 1367 /** 1368 * hns_dsaf_init - init dsa fabric 1369 * @dsaf_dev: dsa fabric device struct pointer 1370 * retuen 0 - success , negative --fail 1371 */ 1372 static int hns_dsaf_init(struct dsaf_device *dsaf_dev) 1373 { 1374 struct dsaf_drv_priv *priv = 1375 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1376 u32 i; 1377 int ret; 1378 1379 if (HNS_DSAF_IS_DEBUG(dsaf_dev)) 1380 return 0; 1381 1382 spin_lock_init(&dsaf_dev->tcam_lock); 1383 ret = hns_dsaf_init_hw(dsaf_dev); 1384 if (ret) 1385 return ret; 1386 1387 /* malloc mem for tcam mac key(vlan+mac) */ 1388 priv->soft_mac_tbl = vzalloc(sizeof(*priv->soft_mac_tbl) 1389 * DSAF_TCAM_SUM); 1390 if (!priv->soft_mac_tbl) { 1391 ret = -ENOMEM; 1392 goto remove_hw; 1393 } 1394 1395 /*all entry invall */ 1396 for (i = 0; i < DSAF_TCAM_SUM; i++) 1397 (priv->soft_mac_tbl + i)->index = DSAF_INVALID_ENTRY_IDX; 1398 1399 return 0; 1400 1401 remove_hw: 1402 hns_dsaf_remove_hw(dsaf_dev); 1403 return ret; 1404 } 1405 1406 /** 1407 * hns_dsaf_free - free dsa fabric 1408 * @dsaf_dev: dsa fabric device struct pointer 1409 */ 1410 static void hns_dsaf_free(struct dsaf_device *dsaf_dev) 1411 { 1412 struct dsaf_drv_priv *priv = 1413 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1414 1415 hns_dsaf_remove_hw(dsaf_dev); 1416 1417 /* free all mac mem */ 1418 vfree(priv->soft_mac_tbl); 1419 priv->soft_mac_tbl = NULL; 1420 } 1421 1422 /** 1423 * hns_dsaf_find_soft_mac_entry - find dsa fabric soft entry 1424 * @dsaf_dev: dsa fabric device struct pointer 1425 * @mac_key: mac entry struct pointer 1426 */ 1427 static u16 hns_dsaf_find_soft_mac_entry( 1428 struct dsaf_device *dsaf_dev, 1429 struct dsaf_drv_tbl_tcam_key *mac_key) 1430 { 1431 struct dsaf_drv_priv *priv = 1432 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1433 struct dsaf_drv_soft_mac_tbl *soft_mac_entry; 1434 u32 i; 1435 1436 soft_mac_entry = priv->soft_mac_tbl; 1437 for (i = 0; i < DSAF_TCAM_SUM; i++) { 1438 /* invall tab entry */ 1439 if ((soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX) && 1440 (soft_mac_entry->tcam_key.high.val == mac_key->high.val) && 1441 (soft_mac_entry->tcam_key.low.val == mac_key->low.val)) 1442 /* return find result --soft index */ 1443 return soft_mac_entry->index; 1444 1445 soft_mac_entry++; 1446 } 1447 return DSAF_INVALID_ENTRY_IDX; 1448 } 1449 1450 /** 1451 * hns_dsaf_find_empty_mac_entry - search dsa fabric soft empty-entry 1452 * @dsaf_dev: dsa fabric device struct pointer 1453 */ 1454 static u16 hns_dsaf_find_empty_mac_entry(struct dsaf_device *dsaf_dev) 1455 { 1456 struct dsaf_drv_priv *priv = 1457 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1458 struct dsaf_drv_soft_mac_tbl *soft_mac_entry; 1459 u32 i; 1460 1461 soft_mac_entry = priv->soft_mac_tbl; 1462 for (i = 0; i < DSAF_TCAM_SUM; i++) { 1463 /* inv all entry */ 1464 if (soft_mac_entry->index == DSAF_INVALID_ENTRY_IDX) 1465 /* return find result --soft index */ 1466 return i; 1467 1468 soft_mac_entry++; 1469 } 1470 return DSAF_INVALID_ENTRY_IDX; 1471 } 1472 1473 /** 1474 * hns_dsaf_set_mac_key - set mac key 1475 * @dsaf_dev: dsa fabric device struct pointer 1476 * @mac_key: tcam key pointer 1477 * @vlan_id: vlan id 1478 * @in_port_num: input port num 1479 * @addr: mac addr 1480 */ 1481 static void hns_dsaf_set_mac_key( 1482 struct dsaf_device *dsaf_dev, 1483 struct dsaf_drv_tbl_tcam_key *mac_key, u16 vlan_id, u8 in_port_num, 1484 u8 *addr) 1485 { 1486 u8 port; 1487 1488 if (dsaf_dev->dsaf_mode <= DSAF_MODE_ENABLE) 1489 /*DSAF mode : in port id fixed 0*/ 1490 port = 0; 1491 else 1492 /*non-dsaf mode*/ 1493 port = in_port_num; 1494 1495 mac_key->high.bits.mac_0 = addr[0]; 1496 mac_key->high.bits.mac_1 = addr[1]; 1497 mac_key->high.bits.mac_2 = addr[2]; 1498 mac_key->high.bits.mac_3 = addr[3]; 1499 mac_key->low.bits.mac_4 = addr[4]; 1500 mac_key->low.bits.mac_5 = addr[5]; 1501 mac_key->low.bits.vlan = vlan_id; 1502 mac_key->low.bits.port = port; 1503 } 1504 1505 /** 1506 * hns_dsaf_set_mac_uc_entry - set mac uc-entry 1507 * @dsaf_dev: dsa fabric device struct pointer 1508 * @mac_entry: uc-mac entry 1509 */ 1510 int hns_dsaf_set_mac_uc_entry( 1511 struct dsaf_device *dsaf_dev, 1512 struct dsaf_drv_mac_single_dest_entry *mac_entry) 1513 { 1514 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1515 struct dsaf_drv_tbl_tcam_key mac_key; 1516 struct dsaf_tbl_tcam_ucast_cfg mac_data; 1517 struct dsaf_drv_priv *priv = 1518 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1519 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl; 1520 1521 /* mac addr check */ 1522 if (MAC_IS_ALL_ZEROS(mac_entry->addr) || 1523 MAC_IS_BROADCAST(mac_entry->addr) || 1524 MAC_IS_MULTICAST(mac_entry->addr)) { 1525 dev_err(dsaf_dev->dev, "set_uc %s Mac %pM err!\n", 1526 dsaf_dev->ae_dev.name, mac_entry->addr); 1527 return -EINVAL; 1528 } 1529 1530 /* config key */ 1531 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id, 1532 mac_entry->in_port_num, mac_entry->addr); 1533 1534 /* entry ie exist? */ 1535 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1536 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1537 /*if has not inv entry,find a empty entry */ 1538 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev); 1539 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1540 /* has not empty,return error */ 1541 dev_err(dsaf_dev->dev, 1542 "set_uc_entry failed, %s Mac key(%#x:%#x)\n", 1543 dsaf_dev->ae_dev.name, 1544 mac_key.high.val, mac_key.low.val); 1545 return -EINVAL; 1546 } 1547 } 1548 1549 dev_dbg(dsaf_dev->dev, 1550 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n", 1551 dsaf_dev->ae_dev.name, mac_key.high.val, 1552 mac_key.low.val, entry_index); 1553 1554 /* config hardware entry */ 1555 mac_data.tbl_ucast_item_vld = 1; 1556 mac_data.tbl_ucast_mac_discard = 0; 1557 mac_data.tbl_ucast_old_en = 0; 1558 /* default config dvc to 0 */ 1559 mac_data.tbl_ucast_dvc = 0; 1560 mac_data.tbl_ucast_out_port = mac_entry->port_num; 1561 hns_dsaf_tcam_uc_cfg( 1562 dsaf_dev, entry_index, 1563 (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data); 1564 1565 /* config software entry */ 1566 soft_mac_entry += entry_index; 1567 soft_mac_entry->index = entry_index; 1568 soft_mac_entry->tcam_key.high.val = mac_key.high.val; 1569 soft_mac_entry->tcam_key.low.val = mac_key.low.val; 1570 1571 return 0; 1572 } 1573 1574 /** 1575 * hns_dsaf_set_mac_mc_entry - set mac mc-entry 1576 * @dsaf_dev: dsa fabric device struct pointer 1577 * @mac_entry: mc-mac entry 1578 */ 1579 int hns_dsaf_set_mac_mc_entry( 1580 struct dsaf_device *dsaf_dev, 1581 struct dsaf_drv_mac_multi_dest_entry *mac_entry) 1582 { 1583 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1584 struct dsaf_drv_tbl_tcam_key mac_key; 1585 struct dsaf_tbl_tcam_mcast_cfg mac_data; 1586 struct dsaf_drv_priv *priv = 1587 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1588 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl; 1589 struct dsaf_drv_tbl_tcam_key tmp_mac_key; 1590 1591 /* mac addr check */ 1592 if (MAC_IS_ALL_ZEROS(mac_entry->addr)) { 1593 dev_err(dsaf_dev->dev, "set uc %s Mac %pM err!\n", 1594 dsaf_dev->ae_dev.name, mac_entry->addr); 1595 return -EINVAL; 1596 } 1597 1598 /*config key */ 1599 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 1600 mac_entry->in_vlan_id, 1601 mac_entry->in_port_num, mac_entry->addr); 1602 1603 /* entry ie exist? */ 1604 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1605 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1606 /*if hasnot, find enpty entry*/ 1607 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev); 1608 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1609 /*if hasnot empty, error*/ 1610 dev_err(dsaf_dev->dev, 1611 "set_uc_entry failed, %s Mac key(%#x:%#x)\n", 1612 dsaf_dev->ae_dev.name, 1613 mac_key.high.val, mac_key.low.val); 1614 return -EINVAL; 1615 } 1616 1617 /* config hardware entry */ 1618 memset(mac_data.tbl_mcast_port_msk, 1619 0, sizeof(mac_data.tbl_mcast_port_msk)); 1620 } else { 1621 /* config hardware entry */ 1622 hns_dsaf_tcam_mc_get( 1623 dsaf_dev, entry_index, 1624 (struct dsaf_tbl_tcam_data *)(&tmp_mac_key), &mac_data); 1625 } 1626 mac_data.tbl_mcast_old_en = 0; 1627 mac_data.tbl_mcast_item_vld = 1; 1628 dsaf_set_field(mac_data.tbl_mcast_port_msk[0], 1629 0x3F, 0, mac_entry->port_mask[0]); 1630 1631 dev_dbg(dsaf_dev->dev, 1632 "set_uc_entry, %s key(%#x:%#x) entry_index%d\n", 1633 dsaf_dev->ae_dev.name, mac_key.high.val, 1634 mac_key.low.val, entry_index); 1635 1636 hns_dsaf_tcam_mc_cfg( 1637 dsaf_dev, entry_index, 1638 (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data); 1639 1640 /* config software entry */ 1641 soft_mac_entry += entry_index; 1642 soft_mac_entry->index = entry_index; 1643 soft_mac_entry->tcam_key.high.val = mac_key.high.val; 1644 soft_mac_entry->tcam_key.low.val = mac_key.low.val; 1645 1646 return 0; 1647 } 1648 1649 /** 1650 * hns_dsaf_add_mac_mc_port - add mac mc-port 1651 * @dsaf_dev: dsa fabric device struct pointer 1652 * @mac_entry: mc-mac entry 1653 */ 1654 int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev, 1655 struct dsaf_drv_mac_single_dest_entry *mac_entry) 1656 { 1657 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1658 struct dsaf_drv_tbl_tcam_key mac_key; 1659 struct dsaf_tbl_tcam_mcast_cfg mac_data; 1660 struct dsaf_drv_priv *priv = 1661 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1662 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl; 1663 struct dsaf_drv_tbl_tcam_key tmp_mac_key; 1664 int mskid; 1665 1666 /*chechk mac addr */ 1667 if (MAC_IS_ALL_ZEROS(mac_entry->addr)) { 1668 dev_err(dsaf_dev->dev, "set_entry failed,addr %pM!\n", 1669 mac_entry->addr); 1670 return -EINVAL; 1671 } 1672 1673 /*config key */ 1674 hns_dsaf_set_mac_key( 1675 dsaf_dev, &mac_key, mac_entry->in_vlan_id, 1676 mac_entry->in_port_num, mac_entry->addr); 1677 1678 memset(&mac_data, 0, sizeof(struct dsaf_tbl_tcam_mcast_cfg)); 1679 1680 /*check exist? */ 1681 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1682 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1683 /*if hasnot , find a empty*/ 1684 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev); 1685 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1686 /*if hasnot empty, error*/ 1687 dev_err(dsaf_dev->dev, 1688 "set_uc_entry failed, %s Mac key(%#x:%#x)\n", 1689 dsaf_dev->ae_dev.name, mac_key.high.val, 1690 mac_key.low.val); 1691 return -EINVAL; 1692 } 1693 } else { 1694 /*if exist, add in */ 1695 hns_dsaf_tcam_mc_get( 1696 dsaf_dev, entry_index, 1697 (struct dsaf_tbl_tcam_data *)(&tmp_mac_key), &mac_data); 1698 } 1699 /* config hardware entry */ 1700 if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) { 1701 mskid = mac_entry->port_num; 1702 } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) { 1703 mskid = mac_entry->port_num - 1704 DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM; 1705 } else { 1706 dev_err(dsaf_dev->dev, 1707 "%s,pnum(%d)error,key(%#x:%#x)\n", 1708 dsaf_dev->ae_dev.name, mac_entry->port_num, 1709 mac_key.high.val, mac_key.low.val); 1710 return -EINVAL; 1711 } 1712 dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 1); 1713 mac_data.tbl_mcast_old_en = 0; 1714 mac_data.tbl_mcast_item_vld = 1; 1715 1716 dev_dbg(dsaf_dev->dev, 1717 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n", 1718 dsaf_dev->ae_dev.name, mac_key.high.val, 1719 mac_key.low.val, entry_index); 1720 1721 hns_dsaf_tcam_mc_cfg( 1722 dsaf_dev, entry_index, 1723 (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data); 1724 1725 /*config software entry */ 1726 soft_mac_entry += entry_index; 1727 soft_mac_entry->index = entry_index; 1728 soft_mac_entry->tcam_key.high.val = mac_key.high.val; 1729 soft_mac_entry->tcam_key.low.val = mac_key.low.val; 1730 1731 return 0; 1732 } 1733 1734 /** 1735 * hns_dsaf_del_mac_entry - del mac mc-port 1736 * @dsaf_dev: dsa fabric device struct pointer 1737 * @vlan_id: vlian id 1738 * @in_port_num: input port num 1739 * @addr : mac addr 1740 */ 1741 int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id, 1742 u8 in_port_num, u8 *addr) 1743 { 1744 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1745 struct dsaf_drv_tbl_tcam_key mac_key; 1746 struct dsaf_drv_priv *priv = 1747 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1748 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl; 1749 1750 /*check mac addr */ 1751 if (MAC_IS_ALL_ZEROS(addr) || MAC_IS_BROADCAST(addr)) { 1752 dev_err(dsaf_dev->dev, "del_entry failed,addr %pM!\n", 1753 addr); 1754 return -EINVAL; 1755 } 1756 1757 /*config key */ 1758 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, addr); 1759 1760 /*exist ?*/ 1761 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1762 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1763 /*not exist, error */ 1764 dev_err(dsaf_dev->dev, 1765 "del_mac_entry failed, %s Mac key(%#x:%#x)\n", 1766 dsaf_dev->ae_dev.name, 1767 mac_key.high.val, mac_key.low.val); 1768 return -EINVAL; 1769 } 1770 dev_dbg(dsaf_dev->dev, 1771 "del_mac_entry, %s Mac key(%#x:%#x) entry_index%d\n", 1772 dsaf_dev->ae_dev.name, mac_key.high.val, 1773 mac_key.low.val, entry_index); 1774 1775 /*do del opt*/ 1776 hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index); 1777 1778 /*del soft emtry */ 1779 soft_mac_entry += entry_index; 1780 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX; 1781 1782 return 0; 1783 } 1784 1785 /** 1786 * hns_dsaf_del_mac_mc_port - del mac mc- port 1787 * @dsaf_dev: dsa fabric device struct pointer 1788 * @mac_entry: mac entry 1789 */ 1790 int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev, 1791 struct dsaf_drv_mac_single_dest_entry *mac_entry) 1792 { 1793 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1794 struct dsaf_drv_tbl_tcam_key mac_key; 1795 struct dsaf_drv_priv *priv = 1796 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1797 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl; 1798 u16 vlan_id; 1799 u8 in_port_num; 1800 struct dsaf_tbl_tcam_mcast_cfg mac_data; 1801 struct dsaf_drv_tbl_tcam_key tmp_mac_key; 1802 int mskid; 1803 const u8 empty_msk[sizeof(mac_data.tbl_mcast_port_msk)] = {0}; 1804 1805 if (!(void *)mac_entry) { 1806 dev_err(dsaf_dev->dev, 1807 "hns_dsaf_del_mac_mc_port mac_entry is NULL\n"); 1808 return -EINVAL; 1809 } 1810 1811 /*get key info*/ 1812 vlan_id = mac_entry->in_vlan_id; 1813 in_port_num = mac_entry->in_port_num; 1814 1815 /*check mac addr */ 1816 if (MAC_IS_ALL_ZEROS(mac_entry->addr)) { 1817 dev_err(dsaf_dev->dev, "del_port failed, addr %pM!\n", 1818 mac_entry->addr); 1819 return -EINVAL; 1820 } 1821 1822 /*config key */ 1823 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, 1824 mac_entry->addr); 1825 1826 /*check is exist? */ 1827 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1828 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1829 /*find none */ 1830 dev_err(dsaf_dev->dev, 1831 "find_soft_mac_entry failed, %s Mac key(%#x:%#x)\n", 1832 dsaf_dev->ae_dev.name, 1833 mac_key.high.val, mac_key.low.val); 1834 return -EINVAL; 1835 } 1836 1837 dev_dbg(dsaf_dev->dev, 1838 "del_mac_mc_port, %s key(%#x:%#x) index%d\n", 1839 dsaf_dev->ae_dev.name, mac_key.high.val, 1840 mac_key.low.val, entry_index); 1841 1842 /*read entry*/ 1843 hns_dsaf_tcam_mc_get( 1844 dsaf_dev, entry_index, 1845 (struct dsaf_tbl_tcam_data *)(&tmp_mac_key), &mac_data); 1846 1847 /*del the port*/ 1848 if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) { 1849 mskid = mac_entry->port_num; 1850 } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) { 1851 mskid = mac_entry->port_num - 1852 DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM; 1853 } else { 1854 dev_err(dsaf_dev->dev, 1855 "%s,pnum(%d)error,key(%#x:%#x)\n", 1856 dsaf_dev->ae_dev.name, mac_entry->port_num, 1857 mac_key.high.val, mac_key.low.val); 1858 return -EINVAL; 1859 } 1860 dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 0); 1861 1862 /*check non port, do del entry */ 1863 if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk, 1864 sizeof(mac_data.tbl_mcast_port_msk))) { 1865 hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index); 1866 1867 /* del soft entry */ 1868 soft_mac_entry += entry_index; 1869 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX; 1870 } else { /* not zer, just del port, updata*/ 1871 hns_dsaf_tcam_mc_cfg( 1872 dsaf_dev, entry_index, 1873 (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data); 1874 } 1875 1876 return 0; 1877 } 1878 1879 /** 1880 * hns_dsaf_get_mac_uc_entry - get mac uc entry 1881 * @dsaf_dev: dsa fabric device struct pointer 1882 * @mac_entry: mac entry 1883 */ 1884 int hns_dsaf_get_mac_uc_entry(struct dsaf_device *dsaf_dev, 1885 struct dsaf_drv_mac_single_dest_entry *mac_entry) 1886 { 1887 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1888 struct dsaf_drv_tbl_tcam_key mac_key; 1889 1890 struct dsaf_tbl_tcam_ucast_cfg mac_data; 1891 1892 /* check macaddr */ 1893 if (MAC_IS_ALL_ZEROS(mac_entry->addr) || 1894 MAC_IS_BROADCAST(mac_entry->addr)) { 1895 dev_err(dsaf_dev->dev, "get_entry failed,addr %pM\n", 1896 mac_entry->addr); 1897 return -EINVAL; 1898 } 1899 1900 /*config key */ 1901 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id, 1902 mac_entry->in_port_num, mac_entry->addr); 1903 1904 /*check exist? */ 1905 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1906 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1907 /*find none, error */ 1908 dev_err(dsaf_dev->dev, 1909 "get_uc_entry failed, %s Mac key(%#x:%#x)\n", 1910 dsaf_dev->ae_dev.name, 1911 mac_key.high.val, mac_key.low.val); 1912 return -EINVAL; 1913 } 1914 dev_dbg(dsaf_dev->dev, 1915 "get_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n", 1916 dsaf_dev->ae_dev.name, mac_key.high.val, 1917 mac_key.low.val, entry_index); 1918 1919 /*read entry*/ 1920 hns_dsaf_tcam_uc_get(dsaf_dev, entry_index, 1921 (struct dsaf_tbl_tcam_data *)&mac_key, &mac_data); 1922 mac_entry->port_num = mac_data.tbl_ucast_out_port; 1923 1924 return 0; 1925 } 1926 1927 /** 1928 * hns_dsaf_get_mac_mc_entry - get mac mc entry 1929 * @dsaf_dev: dsa fabric device struct pointer 1930 * @mac_entry: mac entry 1931 */ 1932 int hns_dsaf_get_mac_mc_entry(struct dsaf_device *dsaf_dev, 1933 struct dsaf_drv_mac_multi_dest_entry *mac_entry) 1934 { 1935 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1936 struct dsaf_drv_tbl_tcam_key mac_key; 1937 1938 struct dsaf_tbl_tcam_mcast_cfg mac_data; 1939 1940 /*check mac addr */ 1941 if (MAC_IS_ALL_ZEROS(mac_entry->addr) || 1942 MAC_IS_BROADCAST(mac_entry->addr)) { 1943 dev_err(dsaf_dev->dev, "get_entry failed,addr %pM\n", 1944 mac_entry->addr); 1945 return -EINVAL; 1946 } 1947 1948 /*config key */ 1949 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id, 1950 mac_entry->in_port_num, mac_entry->addr); 1951 1952 /*check exist? */ 1953 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1954 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1955 /* find none, error */ 1956 dev_err(dsaf_dev->dev, 1957 "get_mac_uc_entry failed, %s Mac key(%#x:%#x)\n", 1958 dsaf_dev->ae_dev.name, mac_key.high.val, 1959 mac_key.low.val); 1960 return -EINVAL; 1961 } 1962 dev_dbg(dsaf_dev->dev, 1963 "get_mac_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n", 1964 dsaf_dev->ae_dev.name, mac_key.high.val, 1965 mac_key.low.val, entry_index); 1966 1967 /*read entry */ 1968 hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, 1969 (struct dsaf_tbl_tcam_data *)&mac_key, &mac_data); 1970 1971 mac_entry->port_mask[0] = mac_data.tbl_mcast_port_msk[0] & 0x3F; 1972 return 0; 1973 } 1974 1975 /** 1976 * hns_dsaf_get_mac_entry_by_index - get mac entry by tab index 1977 * @dsaf_dev: dsa fabric device struct pointer 1978 * @entry_index: tab entry index 1979 * @mac_entry: mac entry 1980 */ 1981 int hns_dsaf_get_mac_entry_by_index( 1982 struct dsaf_device *dsaf_dev, 1983 u16 entry_index, struct dsaf_drv_mac_multi_dest_entry *mac_entry) 1984 { 1985 struct dsaf_drv_tbl_tcam_key mac_key; 1986 1987 struct dsaf_tbl_tcam_mcast_cfg mac_data; 1988 struct dsaf_tbl_tcam_ucast_cfg mac_uc_data; 1989 char mac_addr[MAC_NUM_OCTETS_PER_ADDR] = {0}; 1990 1991 if (entry_index >= DSAF_TCAM_SUM) { 1992 /* find none, del error */ 1993 dev_err(dsaf_dev->dev, "get_uc_entry failed, %s\n", 1994 dsaf_dev->ae_dev.name); 1995 return -EINVAL; 1996 } 1997 1998 /* mc entry, do read opt */ 1999 hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, 2000 (struct dsaf_tbl_tcam_data *)&mac_key, &mac_data); 2001 2002 mac_entry->port_mask[0] = mac_data.tbl_mcast_port_msk[0] & 0x3F; 2003 2004 /***get mac addr*/ 2005 mac_addr[0] = mac_key.high.bits.mac_0; 2006 mac_addr[1] = mac_key.high.bits.mac_1; 2007 mac_addr[2] = mac_key.high.bits.mac_2; 2008 mac_addr[3] = mac_key.high.bits.mac_3; 2009 mac_addr[4] = mac_key.low.bits.mac_4; 2010 mac_addr[5] = mac_key.low.bits.mac_5; 2011 /**is mc or uc*/ 2012 if (MAC_IS_MULTICAST((u8 *)mac_addr) || 2013 MAC_IS_L3_MULTICAST((u8 *)mac_addr)) { 2014 /**mc donot do*/ 2015 } else { 2016 /*is not mc, just uc... */ 2017 hns_dsaf_tcam_uc_get(dsaf_dev, entry_index, 2018 (struct dsaf_tbl_tcam_data *)&mac_key, 2019 &mac_uc_data); 2020 mac_entry->port_mask[0] = (1 << mac_uc_data.tbl_ucast_out_port); 2021 } 2022 2023 return 0; 2024 } 2025 2026 static struct dsaf_device *hns_dsaf_alloc_dev(struct device *dev, 2027 size_t sizeof_priv) 2028 { 2029 struct dsaf_device *dsaf_dev; 2030 2031 dsaf_dev = devm_kzalloc(dev, 2032 sizeof(*dsaf_dev) + sizeof_priv, GFP_KERNEL); 2033 if (unlikely(!dsaf_dev)) { 2034 dsaf_dev = ERR_PTR(-ENOMEM); 2035 } else { 2036 dsaf_dev->dev = dev; 2037 dev_set_drvdata(dev, dsaf_dev); 2038 } 2039 2040 return dsaf_dev; 2041 } 2042 2043 /** 2044 * hns_dsaf_free_dev - free dev mem 2045 * @dev: struct device pointer 2046 */ 2047 static void hns_dsaf_free_dev(struct dsaf_device *dsaf_dev) 2048 { 2049 (void)dev_set_drvdata(dsaf_dev->dev, NULL); 2050 } 2051 2052 /** 2053 * dsaf_pfc_unit_cnt - set pfc unit count 2054 * @dsaf_id: dsa fabric id 2055 * @pport_rate: value array 2056 * @pdsaf_pfc_unit_cnt: value array 2057 */ 2058 static void hns_dsaf_pfc_unit_cnt(struct dsaf_device *dsaf_dev, int mac_id, 2059 enum dsaf_port_rate_mode rate) 2060 { 2061 u32 unit_cnt; 2062 2063 switch (rate) { 2064 case DSAF_PORT_RATE_10000: 2065 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE; 2066 break; 2067 case DSAF_PORT_RATE_1000: 2068 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000; 2069 break; 2070 case DSAF_PORT_RATE_2500: 2071 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000; 2072 break; 2073 default: 2074 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE; 2075 } 2076 2077 dsaf_set_dev_field(dsaf_dev, 2078 (DSAF_PFC_UNIT_CNT_0_REG + 0x4 * (u64)mac_id), 2079 DSAF_PFC_UNINT_CNT_M, DSAF_PFC_UNINT_CNT_S, 2080 unit_cnt); 2081 } 2082 2083 /** 2084 * dsaf_port_work_rate_cfg - fifo 2085 * @dsaf_id: dsa fabric id 2086 * @xge_ge_work_mode 2087 */ 2088 void hns_dsaf_port_work_rate_cfg(struct dsaf_device *dsaf_dev, int mac_id, 2089 enum dsaf_port_rate_mode rate_mode) 2090 { 2091 u32 port_work_mode; 2092 2093 port_work_mode = dsaf_read_dev( 2094 dsaf_dev, DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id); 2095 2096 if (rate_mode == DSAF_PORT_RATE_10000) 2097 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 1); 2098 else 2099 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 0); 2100 2101 dsaf_write_dev(dsaf_dev, 2102 DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id, 2103 port_work_mode); 2104 2105 hns_dsaf_pfc_unit_cnt(dsaf_dev, mac_id, rate_mode); 2106 } 2107 2108 /** 2109 * hns_dsaf_fix_mac_mode - dsaf modify mac mode 2110 * @mac_cb: mac contrl block 2111 */ 2112 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb) 2113 { 2114 enum dsaf_port_rate_mode mode; 2115 struct dsaf_device *dsaf_dev = mac_cb->dsaf_dev; 2116 int mac_id = mac_cb->mac_id; 2117 2118 if (mac_cb->mac_type != HNAE_PORT_SERVICE) 2119 return; 2120 if (mac_cb->phy_if == PHY_INTERFACE_MODE_XGMII) 2121 mode = DSAF_PORT_RATE_10000; 2122 else 2123 mode = DSAF_PORT_RATE_1000; 2124 2125 hns_dsaf_port_work_rate_cfg(dsaf_dev, mac_id, mode); 2126 } 2127 2128 static u32 hns_dsaf_get_inode_prio_reg(int index) 2129 { 2130 int base_index, offset; 2131 u32 base_addr = DSAF_INODE_IN_PRIO_PAUSE_BASE_REG; 2132 2133 base_index = (index + 1) / DSAF_REG_PER_ZONE; 2134 offset = (index + 1) % DSAF_REG_PER_ZONE; 2135 2136 return base_addr + DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET * base_index + 2137 DSAF_INODE_IN_PRIO_PAUSE_OFFSET * offset; 2138 } 2139 2140 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 node_num) 2141 { 2142 struct dsaf_hw_stats *hw_stats 2143 = &dsaf_dev->hw_stats[node_num]; 2144 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver); 2145 int i; 2146 u32 reg_tmp; 2147 2148 hw_stats->pad_drop += dsaf_read_dev(dsaf_dev, 2149 DSAF_INODE_PAD_DISCARD_NUM_0_REG + 0x80 * (u64)node_num); 2150 hw_stats->man_pkts += dsaf_read_dev(dsaf_dev, 2151 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + 0x80 * (u64)node_num); 2152 hw_stats->rx_pkts += dsaf_read_dev(dsaf_dev, 2153 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + 0x80 * (u64)node_num); 2154 hw_stats->rx_pkt_id += dsaf_read_dev(dsaf_dev, 2155 DSAF_INODE_SBM_PID_NUM_0_REG + 0x80 * (u64)node_num); 2156 2157 reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG : 2158 DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG; 2159 hw_stats->rx_pause_frame += 2160 dsaf_read_dev(dsaf_dev, reg_tmp + 0x80 * (u64)node_num); 2161 2162 hw_stats->release_buf_num += dsaf_read_dev(dsaf_dev, 2163 DSAF_INODE_SBM_RELS_NUM_0_REG + 0x80 * (u64)node_num); 2164 hw_stats->sbm_drop += dsaf_read_dev(dsaf_dev, 2165 DSAF_INODE_SBM_DROP_NUM_0_REG + 0x80 * (u64)node_num); 2166 hw_stats->crc_false += dsaf_read_dev(dsaf_dev, 2167 DSAF_INODE_CRC_FALSE_NUM_0_REG + 0x80 * (u64)node_num); 2168 hw_stats->bp_drop += dsaf_read_dev(dsaf_dev, 2169 DSAF_INODE_BP_DISCARD_NUM_0_REG + 0x80 * (u64)node_num); 2170 hw_stats->rslt_drop += dsaf_read_dev(dsaf_dev, 2171 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + 0x80 * (u64)node_num); 2172 hw_stats->local_addr_false += dsaf_read_dev(dsaf_dev, 2173 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + 0x80 * (u64)node_num); 2174 2175 hw_stats->vlan_drop += dsaf_read_dev(dsaf_dev, 2176 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + 0x80 * (u64)node_num); 2177 hw_stats->stp_drop += dsaf_read_dev(dsaf_dev, 2178 DSAF_INODE_IN_DATA_STP_DISC_0_REG + 0x80 * (u64)node_num); 2179 2180 /* pfc pause frame statistics stored in dsaf inode*/ 2181 if ((node_num < DSAF_SERVICE_NW_NUM) && !is_ver1) { 2182 for (i = 0; i < DSAF_PRIO_NR; i++) { 2183 reg_tmp = hns_dsaf_get_inode_prio_reg(i); 2184 hw_stats->rx_pfc[i] += dsaf_read_dev(dsaf_dev, 2185 reg_tmp + 0x4 * (u64)node_num); 2186 hw_stats->tx_pfc[i] += dsaf_read_dev(dsaf_dev, 2187 DSAF_XOD_XGE_PFC_PRIO_CNT_BASE_REG + 2188 DSAF_XOD_XGE_PFC_PRIO_CNT_OFFSET * i + 2189 0xF0 * (u64)node_num); 2190 } 2191 } 2192 hw_stats->tx_pkts += dsaf_read_dev(dsaf_dev, 2193 DSAF_XOD_RCVPKT_CNT_0_REG + 0x90 * (u64)node_num); 2194 } 2195 2196 /** 2197 *hns_dsaf_get_regs - dump dsaf regs 2198 *@dsaf_dev: dsaf device 2199 *@data:data for value of regs 2200 */ 2201 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data) 2202 { 2203 u32 i = 0; 2204 u32 j; 2205 u32 *p = data; 2206 u32 reg_tmp; 2207 bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver); 2208 2209 /* dsaf common registers */ 2210 p[0] = dsaf_read_dev(ddev, DSAF_SRAM_INIT_OVER_0_REG); 2211 p[1] = dsaf_read_dev(ddev, DSAF_CFG_0_REG); 2212 p[2] = dsaf_read_dev(ddev, DSAF_ECC_ERR_INVERT_0_REG); 2213 p[3] = dsaf_read_dev(ddev, DSAF_ABNORMAL_TIMEOUT_0_REG); 2214 p[4] = dsaf_read_dev(ddev, DSAF_FSM_TIMEOUT_0_REG); 2215 p[5] = dsaf_read_dev(ddev, DSAF_DSA_REG_CNT_CLR_CE_REG); 2216 p[6] = dsaf_read_dev(ddev, DSAF_DSA_SBM_INF_FIFO_THRD_REG); 2217 p[7] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_SEL_REG); 2218 p[8] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_CNT_REG); 2219 2220 p[9] = dsaf_read_dev(ddev, DSAF_PFC_EN_0_REG + port * 4); 2221 p[10] = dsaf_read_dev(ddev, DSAF_PFC_UNIT_CNT_0_REG + port * 4); 2222 p[11] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4); 2223 p[12] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4); 2224 p[13] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4); 2225 p[14] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4); 2226 p[15] = dsaf_read_dev(ddev, DSAF_PPE_INT_MSK_0_REG + port * 4); 2227 p[16] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_MSK_0_REG + port * 4); 2228 p[17] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4); 2229 p[18] = dsaf_read_dev(ddev, DSAF_PPE_INT_SRC_0_REG + port * 4); 2230 p[19] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_SRC_0_REG + port * 4); 2231 p[20] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4); 2232 p[21] = dsaf_read_dev(ddev, DSAF_PPE_INT_STS_0_REG + port * 4); 2233 p[22] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_STS_0_REG + port * 4); 2234 p[23] = dsaf_read_dev(ddev, DSAF_PPE_QID_CFG_0_REG + port * 4); 2235 2236 for (i = 0; i < DSAF_SW_PORT_NUM; i++) 2237 p[24 + i] = dsaf_read_dev(ddev, 2238 DSAF_SW_PORT_TYPE_0_REG + i * 4); 2239 2240 p[32] = dsaf_read_dev(ddev, DSAF_MIX_DEF_QID_0_REG + port * 4); 2241 2242 for (i = 0; i < DSAF_SW_PORT_NUM; i++) 2243 p[33 + i] = dsaf_read_dev(ddev, 2244 DSAF_PORT_DEF_VLAN_0_REG + i * 4); 2245 2246 for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++) 2247 p[41 + i] = dsaf_read_dev(ddev, 2248 DSAF_VM_DEF_VLAN_0_REG + i * 4); 2249 2250 /* dsaf inode registers */ 2251 p[170] = dsaf_read_dev(ddev, DSAF_INODE_CUT_THROUGH_CFG_0_REG); 2252 2253 p[171] = dsaf_read_dev(ddev, 2254 DSAF_INODE_ECC_ERR_ADDR_0_REG + port * 0x80); 2255 2256 for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) { 2257 j = i * DSAF_COMM_CHN + port; 2258 p[172 + i] = dsaf_read_dev(ddev, 2259 DSAF_INODE_IN_PORT_NUM_0_REG + j * 0x80); 2260 p[175 + i] = dsaf_read_dev(ddev, 2261 DSAF_INODE_PRI_TC_CFG_0_REG + j * 0x80); 2262 p[178 + i] = dsaf_read_dev(ddev, 2263 DSAF_INODE_BP_STATUS_0_REG + j * 0x80); 2264 p[181 + i] = dsaf_read_dev(ddev, 2265 DSAF_INODE_PAD_DISCARD_NUM_0_REG + j * 0x80); 2266 p[184 + i] = dsaf_read_dev(ddev, 2267 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + j * 0x80); 2268 p[187 + i] = dsaf_read_dev(ddev, 2269 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + j * 0x80); 2270 p[190 + i] = dsaf_read_dev(ddev, 2271 DSAF_INODE_SBM_PID_NUM_0_REG + j * 0x80); 2272 reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG : 2273 DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG; 2274 p[193 + i] = dsaf_read_dev(ddev, reg_tmp + j * 0x80); 2275 p[196 + i] = dsaf_read_dev(ddev, 2276 DSAF_INODE_SBM_RELS_NUM_0_REG + j * 0x80); 2277 p[199 + i] = dsaf_read_dev(ddev, 2278 DSAF_INODE_SBM_DROP_NUM_0_REG + j * 0x80); 2279 p[202 + i] = dsaf_read_dev(ddev, 2280 DSAF_INODE_CRC_FALSE_NUM_0_REG + j * 0x80); 2281 p[205 + i] = dsaf_read_dev(ddev, 2282 DSAF_INODE_BP_DISCARD_NUM_0_REG + j * 0x80); 2283 p[208 + i] = dsaf_read_dev(ddev, 2284 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + j * 0x80); 2285 p[211 + i] = dsaf_read_dev(ddev, 2286 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + j * 0x80); 2287 p[214 + i] = dsaf_read_dev(ddev, 2288 DSAF_INODE_VOQ_OVER_NUM_0_REG + j * 0x80); 2289 p[217 + i] = dsaf_read_dev(ddev, 2290 DSAF_INODE_BD_SAVE_STATUS_0_REG + j * 4); 2291 p[220 + i] = dsaf_read_dev(ddev, 2292 DSAF_INODE_BD_ORDER_STATUS_0_REG + j * 4); 2293 p[223 + i] = dsaf_read_dev(ddev, 2294 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + j * 4); 2295 p[224 + i] = dsaf_read_dev(ddev, 2296 DSAF_INODE_IN_DATA_STP_DISC_0_REG + j * 4); 2297 } 2298 2299 p[227] = dsaf_read_dev(ddev, DSAF_INODE_GE_FC_EN_0_REG + port * 4); 2300 2301 for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) { 2302 j = i * DSAF_COMM_CHN + port; 2303 p[228 + i] = dsaf_read_dev(ddev, 2304 DSAF_INODE_VC0_IN_PKT_NUM_0_REG + j * 4); 2305 } 2306 2307 p[231] = dsaf_read_dev(ddev, 2308 DSAF_INODE_VC1_IN_PKT_NUM_0_REG + port * 4); 2309 2310 /* dsaf inode registers */ 2311 for (i = 0; i < HNS_DSAF_SBM_NUM(ddev) / DSAF_COMM_CHN; i++) { 2312 j = i * DSAF_COMM_CHN + port; 2313 p[232 + i] = dsaf_read_dev(ddev, 2314 DSAF_SBM_CFG_REG_0_REG + j * 0x80); 2315 p[235 + i] = dsaf_read_dev(ddev, 2316 DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + j * 0x80); 2317 p[238 + i] = dsaf_read_dev(ddev, 2318 DSAF_SBM_BP_CFG_1_REG_0_REG + j * 0x80); 2319 p[241 + i] = dsaf_read_dev(ddev, 2320 DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + j * 0x80); 2321 p[244 + i] = dsaf_read_dev(ddev, 2322 DSAF_SBM_FREE_CNT_0_0_REG + j * 0x80); 2323 p[245 + i] = dsaf_read_dev(ddev, 2324 DSAF_SBM_FREE_CNT_1_0_REG + j * 0x80); 2325 p[248 + i] = dsaf_read_dev(ddev, 2326 DSAF_SBM_BP_CNT_0_0_REG + j * 0x80); 2327 p[251 + i] = dsaf_read_dev(ddev, 2328 DSAF_SBM_BP_CNT_1_0_REG + j * 0x80); 2329 p[254 + i] = dsaf_read_dev(ddev, 2330 DSAF_SBM_BP_CNT_2_0_REG + j * 0x80); 2331 p[257 + i] = dsaf_read_dev(ddev, 2332 DSAF_SBM_BP_CNT_3_0_REG + j * 0x80); 2333 p[260 + i] = dsaf_read_dev(ddev, 2334 DSAF_SBM_INER_ST_0_REG + j * 0x80); 2335 p[263 + i] = dsaf_read_dev(ddev, 2336 DSAF_SBM_MIB_REQ_FAILED_TC_0_REG + j * 0x80); 2337 p[266 + i] = dsaf_read_dev(ddev, 2338 DSAF_SBM_LNK_INPORT_CNT_0_REG + j * 0x80); 2339 p[269 + i] = dsaf_read_dev(ddev, 2340 DSAF_SBM_LNK_DROP_CNT_0_REG + j * 0x80); 2341 p[272 + i] = dsaf_read_dev(ddev, 2342 DSAF_SBM_INF_OUTPORT_CNT_0_REG + j * 0x80); 2343 p[275 + i] = dsaf_read_dev(ddev, 2344 DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG + j * 0x80); 2345 p[278 + i] = dsaf_read_dev(ddev, 2346 DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG + j * 0x80); 2347 p[281 + i] = dsaf_read_dev(ddev, 2348 DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG + j * 0x80); 2349 p[284 + i] = dsaf_read_dev(ddev, 2350 DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG + j * 0x80); 2351 p[287 + i] = dsaf_read_dev(ddev, 2352 DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG + j * 0x80); 2353 p[290 + i] = dsaf_read_dev(ddev, 2354 DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG + j * 0x80); 2355 p[293 + i] = dsaf_read_dev(ddev, 2356 DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG + j * 0x80); 2357 p[296 + i] = dsaf_read_dev(ddev, 2358 DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG + j * 0x80); 2359 p[299 + i] = dsaf_read_dev(ddev, 2360 DSAF_SBM_LNK_REQ_CNT_0_REG + j * 0x80); 2361 p[302 + i] = dsaf_read_dev(ddev, 2362 DSAF_SBM_LNK_RELS_CNT_0_REG + j * 0x80); 2363 p[305 + i] = dsaf_read_dev(ddev, 2364 DSAF_SBM_BP_CFG_3_REG_0_REG + j * 0x80); 2365 p[308 + i] = dsaf_read_dev(ddev, 2366 DSAF_SBM_BP_CFG_4_REG_0_REG + j * 0x80); 2367 } 2368 2369 /* dsaf onode registers */ 2370 for (i = 0; i < DSAF_XOD_NUM; i++) { 2371 p[311 + i] = dsaf_read_dev(ddev, 2372 DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG + i * 0x90); 2373 p[319 + i] = dsaf_read_dev(ddev, 2374 DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG + i * 0x90); 2375 p[327 + i] = dsaf_read_dev(ddev, 2376 DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG + i * 0x90); 2377 p[335 + i] = dsaf_read_dev(ddev, 2378 DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG + i * 0x90); 2379 p[343 + i] = dsaf_read_dev(ddev, 2380 DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG + i * 0x90); 2381 p[351 + i] = dsaf_read_dev(ddev, 2382 DSAF_XOD_ETS_TOKEN_CFG_0_REG + i * 0x90); 2383 } 2384 2385 p[359] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_0_0_REG + port * 0x90); 2386 p[360] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_1_0_REG + port * 0x90); 2387 p[361] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_2_0_REG + port * 0x90); 2388 2389 for (i = 0; i < DSAF_XOD_BIG_NUM / DSAF_COMM_CHN; i++) { 2390 j = i * DSAF_COMM_CHN + port; 2391 p[362 + i] = dsaf_read_dev(ddev, 2392 DSAF_XOD_GNT_L_0_REG + j * 0x90); 2393 p[365 + i] = dsaf_read_dev(ddev, 2394 DSAF_XOD_GNT_H_0_REG + j * 0x90); 2395 p[368 + i] = dsaf_read_dev(ddev, 2396 DSAF_XOD_CONNECT_STATE_0_REG + j * 0x90); 2397 p[371 + i] = dsaf_read_dev(ddev, 2398 DSAF_XOD_RCVPKT_CNT_0_REG + j * 0x90); 2399 p[374 + i] = dsaf_read_dev(ddev, 2400 DSAF_XOD_RCVTC0_CNT_0_REG + j * 0x90); 2401 p[377 + i] = dsaf_read_dev(ddev, 2402 DSAF_XOD_RCVTC1_CNT_0_REG + j * 0x90); 2403 p[380 + i] = dsaf_read_dev(ddev, 2404 DSAF_XOD_RCVTC2_CNT_0_REG + j * 0x90); 2405 p[383 + i] = dsaf_read_dev(ddev, 2406 DSAF_XOD_RCVTC3_CNT_0_REG + j * 0x90); 2407 p[386 + i] = dsaf_read_dev(ddev, 2408 DSAF_XOD_RCVVC0_CNT_0_REG + j * 0x90); 2409 p[389 + i] = dsaf_read_dev(ddev, 2410 DSAF_XOD_RCVVC1_CNT_0_REG + j * 0x90); 2411 } 2412 2413 p[392] = dsaf_read_dev(ddev, 2414 DSAF_XOD_XGE_RCVIN0_CNT_0_REG + port * 0x90); 2415 p[393] = dsaf_read_dev(ddev, 2416 DSAF_XOD_XGE_RCVIN1_CNT_0_REG + port * 0x90); 2417 p[394] = dsaf_read_dev(ddev, 2418 DSAF_XOD_XGE_RCVIN2_CNT_0_REG + port * 0x90); 2419 p[395] = dsaf_read_dev(ddev, 2420 DSAF_XOD_XGE_RCVIN3_CNT_0_REG + port * 0x90); 2421 p[396] = dsaf_read_dev(ddev, 2422 DSAF_XOD_XGE_RCVIN4_CNT_0_REG + port * 0x90); 2423 p[397] = dsaf_read_dev(ddev, 2424 DSAF_XOD_XGE_RCVIN5_CNT_0_REG + port * 0x90); 2425 p[398] = dsaf_read_dev(ddev, 2426 DSAF_XOD_XGE_RCVIN6_CNT_0_REG + port * 0x90); 2427 p[399] = dsaf_read_dev(ddev, 2428 DSAF_XOD_XGE_RCVIN7_CNT_0_REG + port * 0x90); 2429 p[400] = dsaf_read_dev(ddev, 2430 DSAF_XOD_PPE_RCVIN0_CNT_0_REG + port * 0x90); 2431 p[401] = dsaf_read_dev(ddev, 2432 DSAF_XOD_PPE_RCVIN1_CNT_0_REG + port * 0x90); 2433 p[402] = dsaf_read_dev(ddev, 2434 DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG + port * 0x90); 2435 p[403] = dsaf_read_dev(ddev, 2436 DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG + port * 0x90); 2437 p[404] = dsaf_read_dev(ddev, 2438 DSAF_XOD_FIFO_STATUS_0_REG + port * 0x90); 2439 2440 /* dsaf voq registers */ 2441 for (i = 0; i < DSAF_VOQ_NUM / DSAF_COMM_CHN; i++) { 2442 j = (i * DSAF_COMM_CHN + port) * 0x90; 2443 p[405 + i] = dsaf_read_dev(ddev, 2444 DSAF_VOQ_ECC_INVERT_EN_0_REG + j); 2445 p[408 + i] = dsaf_read_dev(ddev, 2446 DSAF_VOQ_SRAM_PKT_NUM_0_REG + j); 2447 p[411 + i] = dsaf_read_dev(ddev, DSAF_VOQ_IN_PKT_NUM_0_REG + j); 2448 p[414 + i] = dsaf_read_dev(ddev, 2449 DSAF_VOQ_OUT_PKT_NUM_0_REG + j); 2450 p[417 + i] = dsaf_read_dev(ddev, 2451 DSAF_VOQ_ECC_ERR_ADDR_0_REG + j); 2452 p[420 + i] = dsaf_read_dev(ddev, DSAF_VOQ_BP_STATUS_0_REG + j); 2453 p[423 + i] = dsaf_read_dev(ddev, DSAF_VOQ_SPUP_IDLE_0_REG + j); 2454 p[426 + i] = dsaf_read_dev(ddev, 2455 DSAF_VOQ_XGE_XOD_REQ_0_0_REG + j); 2456 p[429 + i] = dsaf_read_dev(ddev, 2457 DSAF_VOQ_XGE_XOD_REQ_1_0_REG + j); 2458 p[432 + i] = dsaf_read_dev(ddev, 2459 DSAF_VOQ_PPE_XOD_REQ_0_REG + j); 2460 p[435 + i] = dsaf_read_dev(ddev, 2461 DSAF_VOQ_ROCEE_XOD_REQ_0_REG + j); 2462 p[438 + i] = dsaf_read_dev(ddev, 2463 DSAF_VOQ_BP_ALL_THRD_0_REG + j); 2464 } 2465 2466 /* dsaf tbl registers */ 2467 p[441] = dsaf_read_dev(ddev, DSAF_TBL_CTRL_0_REG); 2468 p[442] = dsaf_read_dev(ddev, DSAF_TBL_INT_MSK_0_REG); 2469 p[443] = dsaf_read_dev(ddev, DSAF_TBL_INT_SRC_0_REG); 2470 p[444] = dsaf_read_dev(ddev, DSAF_TBL_INT_STS_0_REG); 2471 p[445] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_ADDR_0_REG); 2472 p[446] = dsaf_read_dev(ddev, DSAF_TBL_LINE_ADDR_0_REG); 2473 p[447] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_HIGH_0_REG); 2474 p[448] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_LOW_0_REG); 2475 p[449] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG); 2476 p[450] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG); 2477 p[451] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG); 2478 p[452] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG); 2479 p[453] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG); 2480 p[454] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_UCAST_CFG_0_REG); 2481 p[455] = dsaf_read_dev(ddev, DSAF_TBL_LIN_CFG_0_REG); 2482 p[456] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG); 2483 p[457] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_LOW_0_REG); 2484 p[458] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG); 2485 p[459] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG); 2486 p[460] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG); 2487 p[461] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG); 2488 p[462] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG); 2489 p[463] = dsaf_read_dev(ddev, DSAF_TBL_LIN_RDATA_0_REG); 2490 2491 for (i = 0; i < DSAF_SW_PORT_NUM; i++) { 2492 j = i * 0x8; 2493 p[464 + 2 * i] = dsaf_read_dev(ddev, 2494 DSAF_TBL_DA0_MIS_INFO1_0_REG + j); 2495 p[465 + 2 * i] = dsaf_read_dev(ddev, 2496 DSAF_TBL_DA0_MIS_INFO0_0_REG + j); 2497 } 2498 2499 p[480] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO2_0_REG); 2500 p[481] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO1_0_REG); 2501 p[482] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO0_0_REG); 2502 p[483] = dsaf_read_dev(ddev, DSAF_TBL_PUL_0_REG); 2503 p[484] = dsaf_read_dev(ddev, DSAF_TBL_OLD_RSLT_0_REG); 2504 p[485] = dsaf_read_dev(ddev, DSAF_TBL_OLD_SCAN_VAL_0_REG); 2505 p[486] = dsaf_read_dev(ddev, DSAF_TBL_DFX_CTRL_0_REG); 2506 p[487] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_0_REG); 2507 p[488] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_2_0_REG); 2508 p[489] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_I_0_REG); 2509 p[490] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_O_0_REG); 2510 p[491] = dsaf_read_dev(ddev, DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG); 2511 2512 /* dsaf other registers */ 2513 p[492] = dsaf_read_dev(ddev, DSAF_INODE_FIFO_WL_0_REG + port * 0x4); 2514 p[493] = dsaf_read_dev(ddev, DSAF_ONODE_FIFO_WL_0_REG + port * 0x4); 2515 p[494] = dsaf_read_dev(ddev, DSAF_XGE_GE_WORK_MODE_0_REG + port * 0x4); 2516 p[495] = dsaf_read_dev(ddev, 2517 DSAF_XGE_APP_RX_LINK_UP_0_REG + port * 0x4); 2518 p[496] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4); 2519 p[497] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4); 2520 2521 if (!is_ver1) 2522 p[498] = dsaf_read_dev(ddev, DSAF_PAUSE_CFG_REG + port * 0x4); 2523 2524 /* mark end of dsaf regs */ 2525 for (i = 499; i < 504; i++) 2526 p[i] = 0xdddddddd; 2527 } 2528 2529 static char *hns_dsaf_get_node_stats_strings(char *data, int node, 2530 struct dsaf_device *dsaf_dev) 2531 { 2532 char *buff = data; 2533 int i; 2534 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver); 2535 2536 snprintf(buff, ETH_GSTRING_LEN, "innod%d_pad_drop_pkts", node); 2537 buff += ETH_GSTRING_LEN; 2538 snprintf(buff, ETH_GSTRING_LEN, "innod%d_manage_pkts", node); 2539 buff += ETH_GSTRING_LEN; 2540 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkts", node); 2541 buff += ETH_GSTRING_LEN; 2542 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkt_id", node); 2543 buff += ETH_GSTRING_LEN; 2544 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pause_frame", node); 2545 buff += ETH_GSTRING_LEN; 2546 snprintf(buff, ETH_GSTRING_LEN, "innod%d_release_buf_num", node); 2547 buff += ETH_GSTRING_LEN; 2548 snprintf(buff, ETH_GSTRING_LEN, "innod%d_sbm_drop_pkts", node); 2549 buff += ETH_GSTRING_LEN; 2550 snprintf(buff, ETH_GSTRING_LEN, "innod%d_crc_false_pkts", node); 2551 buff += ETH_GSTRING_LEN; 2552 snprintf(buff, ETH_GSTRING_LEN, "innod%d_bp_drop_pkts", node); 2553 buff += ETH_GSTRING_LEN; 2554 snprintf(buff, ETH_GSTRING_LEN, "innod%d_lookup_rslt_drop_pkts", node); 2555 buff += ETH_GSTRING_LEN; 2556 snprintf(buff, ETH_GSTRING_LEN, "innod%d_local_rslt_fail_pkts", node); 2557 buff += ETH_GSTRING_LEN; 2558 snprintf(buff, ETH_GSTRING_LEN, "innod%d_vlan_drop_pkts", node); 2559 buff += ETH_GSTRING_LEN; 2560 snprintf(buff, ETH_GSTRING_LEN, "innod%d_stp_drop_pkts", node); 2561 buff += ETH_GSTRING_LEN; 2562 if (node < DSAF_SERVICE_NW_NUM && !is_ver1) { 2563 for (i = 0; i < DSAF_PRIO_NR; i++) { 2564 snprintf(buff + 0 * ETH_GSTRING_LEN * DSAF_PRIO_NR, 2565 ETH_GSTRING_LEN, "inod%d_pfc_prio%d_pkts", 2566 node, i); 2567 snprintf(buff + 1 * ETH_GSTRING_LEN * DSAF_PRIO_NR, 2568 ETH_GSTRING_LEN, "onod%d_pfc_prio%d_pkts", 2569 node, i); 2570 buff += ETH_GSTRING_LEN; 2571 } 2572 buff += 1 * DSAF_PRIO_NR * ETH_GSTRING_LEN; 2573 } 2574 snprintf(buff, ETH_GSTRING_LEN, "onnod%d_tx_pkts", node); 2575 buff += ETH_GSTRING_LEN; 2576 2577 return buff; 2578 } 2579 2580 static u64 *hns_dsaf_get_node_stats(struct dsaf_device *ddev, u64 *data, 2581 int node_num) 2582 { 2583 u64 *p = data; 2584 int i; 2585 struct dsaf_hw_stats *hw_stats = &ddev->hw_stats[node_num]; 2586 bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver); 2587 2588 p[0] = hw_stats->pad_drop; 2589 p[1] = hw_stats->man_pkts; 2590 p[2] = hw_stats->rx_pkts; 2591 p[3] = hw_stats->rx_pkt_id; 2592 p[4] = hw_stats->rx_pause_frame; 2593 p[5] = hw_stats->release_buf_num; 2594 p[6] = hw_stats->sbm_drop; 2595 p[7] = hw_stats->crc_false; 2596 p[8] = hw_stats->bp_drop; 2597 p[9] = hw_stats->rslt_drop; 2598 p[10] = hw_stats->local_addr_false; 2599 p[11] = hw_stats->vlan_drop; 2600 p[12] = hw_stats->stp_drop; 2601 if (node_num < DSAF_SERVICE_NW_NUM && !is_ver1) { 2602 for (i = 0; i < DSAF_PRIO_NR; i++) { 2603 p[13 + i + 0 * DSAF_PRIO_NR] = hw_stats->rx_pfc[i]; 2604 p[13 + i + 1 * DSAF_PRIO_NR] = hw_stats->tx_pfc[i]; 2605 } 2606 p[29] = hw_stats->tx_pkts; 2607 return &p[30]; 2608 } 2609 2610 p[13] = hw_stats->tx_pkts; 2611 return &p[14]; 2612 } 2613 2614 /** 2615 *hns_dsaf_get_stats - get dsaf statistic 2616 *@ddev: dsaf device 2617 *@data:statistic value 2618 *@port: port num 2619 */ 2620 void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port) 2621 { 2622 u64 *p = data; 2623 int node_num = port; 2624 2625 /* for ge/xge node info */ 2626 p = hns_dsaf_get_node_stats(ddev, p, node_num); 2627 2628 /* for ppe node info */ 2629 node_num = port + DSAF_PPE_INODE_BASE; 2630 (void)hns_dsaf_get_node_stats(ddev, p, node_num); 2631 } 2632 2633 /** 2634 *hns_dsaf_get_sset_count - get dsaf string set count 2635 *@stringset: type of values in data 2636 *return dsaf string name count 2637 */ 2638 int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset) 2639 { 2640 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver); 2641 2642 if (stringset == ETH_SS_STATS) { 2643 if (is_ver1) 2644 return DSAF_STATIC_NUM; 2645 else 2646 return DSAF_V2_STATIC_NUM; 2647 } 2648 return 0; 2649 } 2650 2651 /** 2652 *hns_dsaf_get_strings - get dsaf string set 2653 *@stringset:srting set index 2654 *@data:strings name value 2655 *@port:port index 2656 */ 2657 void hns_dsaf_get_strings(int stringset, u8 *data, int port, 2658 struct dsaf_device *dsaf_dev) 2659 { 2660 char *buff = (char *)data; 2661 int node = port; 2662 2663 if (stringset != ETH_SS_STATS) 2664 return; 2665 2666 /* for ge/xge node info */ 2667 buff = hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev); 2668 2669 /* for ppe node info */ 2670 node = port + DSAF_PPE_INODE_BASE; 2671 (void)hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev); 2672 } 2673 2674 /** 2675 *hns_dsaf_get_sset_count - get dsaf regs count 2676 *return dsaf regs count 2677 */ 2678 int hns_dsaf_get_regs_count(void) 2679 { 2680 return DSAF_DUMP_REGS_NUM; 2681 } 2682 2683 /** 2684 * dsaf_probe - probo dsaf dev 2685 * @pdev: dasf platform device 2686 * retuen 0 - success , negative --fail 2687 */ 2688 static int hns_dsaf_probe(struct platform_device *pdev) 2689 { 2690 struct dsaf_device *dsaf_dev; 2691 int ret; 2692 2693 dsaf_dev = hns_dsaf_alloc_dev(&pdev->dev, sizeof(struct dsaf_drv_priv)); 2694 if (IS_ERR(dsaf_dev)) { 2695 ret = PTR_ERR(dsaf_dev); 2696 dev_err(&pdev->dev, 2697 "dsaf_probe dsaf_alloc_dev failed, ret = %#x!\n", ret); 2698 return ret; 2699 } 2700 2701 ret = hns_dsaf_get_cfg(dsaf_dev); 2702 if (ret) 2703 goto free_dev; 2704 2705 ret = hns_dsaf_init(dsaf_dev); 2706 if (ret) 2707 goto free_dev; 2708 2709 ret = hns_mac_init(dsaf_dev); 2710 if (ret) 2711 goto uninit_dsaf; 2712 2713 ret = hns_ppe_init(dsaf_dev); 2714 if (ret) 2715 goto uninit_mac; 2716 2717 ret = hns_dsaf_ae_init(dsaf_dev); 2718 if (ret) 2719 goto uninit_ppe; 2720 2721 return 0; 2722 2723 uninit_ppe: 2724 hns_ppe_uninit(dsaf_dev); 2725 2726 uninit_mac: 2727 hns_mac_uninit(dsaf_dev); 2728 2729 uninit_dsaf: 2730 hns_dsaf_free(dsaf_dev); 2731 2732 free_dev: 2733 hns_dsaf_free_dev(dsaf_dev); 2734 2735 return ret; 2736 } 2737 2738 /** 2739 * dsaf_remove - remove dsaf dev 2740 * @pdev: dasf platform device 2741 */ 2742 static int hns_dsaf_remove(struct platform_device *pdev) 2743 { 2744 struct dsaf_device *dsaf_dev = dev_get_drvdata(&pdev->dev); 2745 2746 hns_dsaf_ae_uninit(dsaf_dev); 2747 2748 hns_ppe_uninit(dsaf_dev); 2749 2750 hns_mac_uninit(dsaf_dev); 2751 2752 hns_dsaf_free(dsaf_dev); 2753 2754 hns_dsaf_free_dev(dsaf_dev); 2755 2756 return 0; 2757 } 2758 2759 static const struct of_device_id g_dsaf_match[] = { 2760 {.compatible = "hisilicon,hns-dsaf-v1"}, 2761 {.compatible = "hisilicon,hns-dsaf-v2"}, 2762 {} 2763 }; 2764 2765 static struct platform_driver g_dsaf_driver = { 2766 .probe = hns_dsaf_probe, 2767 .remove = hns_dsaf_remove, 2768 .driver = { 2769 .name = DSAF_DRV_NAME, 2770 .of_match_table = g_dsaf_match, 2771 .acpi_match_table = hns_dsaf_acpi_match, 2772 }, 2773 }; 2774 2775 module_platform_driver(g_dsaf_driver); 2776 2777 /** 2778 * hns_dsaf_roce_reset - reset dsaf and roce 2779 * @dsaf_fwnode: Pointer to framework node for the dasf 2780 * @enable: false - request reset , true - drop reset 2781 * retuen 0 - success , negative -fail 2782 */ 2783 int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset) 2784 { 2785 struct dsaf_device *dsaf_dev; 2786 struct platform_device *pdev; 2787 u32 mp; 2788 u32 sl; 2789 u32 credit; 2790 int i; 2791 const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = { 2792 {DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0}, 2793 {DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0}, 2794 {DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0}, 2795 {DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0}, 2796 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1}, 2797 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1}, 2798 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1}, 2799 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1}, 2800 }; 2801 const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = { 2802 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0}, 2803 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1}, 2804 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2}, 2805 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3}, 2806 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0}, 2807 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1}, 2808 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2}, 2809 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3}, 2810 }; 2811 2812 /* find the platform device corresponding to fwnode */ 2813 if (is_of_node(dsaf_fwnode)) { 2814 pdev = of_find_device_by_node(to_of_node(dsaf_fwnode)); 2815 } else if (is_acpi_device_node(dsaf_fwnode)) { 2816 pdev = hns_dsaf_find_platform_device(dsaf_fwnode); 2817 } else { 2818 pr_err("fwnode is neither OF or ACPI type\n"); 2819 return -EINVAL; 2820 } 2821 2822 /* check if we were a success in fetching pdev */ 2823 if (!pdev) { 2824 pr_err("couldn't find platform device for node\n"); 2825 return -ENODEV; 2826 } 2827 2828 /* retrieve the dsaf_device from the driver data */ 2829 dsaf_dev = dev_get_drvdata(&pdev->dev); 2830 if (!dsaf_dev) { 2831 dev_err(&pdev->dev, "dsaf_dev is NULL\n"); 2832 return -ENODEV; 2833 } 2834 2835 /* now, make sure we are running on compatible SoC */ 2836 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 2837 dev_err(dsaf_dev->dev, "%s v1 chip doesn't support RoCE!\n", 2838 dsaf_dev->ae_dev.name); 2839 return -ENODEV; 2840 } 2841 2842 /* do reset or de-reset according to the flag */ 2843 if (!dereset) { 2844 /* reset rocee-channels in dsaf and rocee */ 2845 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK, 2846 false); 2847 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, false); 2848 } else { 2849 /* configure dsaf tx roce correspond to port map and sl map */ 2850 mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG); 2851 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++) 2852 dsaf_set_field(mp, 7 << i * 3, i * 3, 2853 port_map[i][DSAF_ROCE_6PORT_MODE]); 2854 dsaf_set_field(mp, 3 << i * 3, i * 3, 0); 2855 dsaf_write_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG, mp); 2856 2857 sl = dsaf_read_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG); 2858 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++) 2859 dsaf_set_field(sl, 3 << i * 2, i * 2, 2860 sl_map[i][DSAF_ROCE_6PORT_MODE]); 2861 dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl); 2862 2863 /* de-reset rocee-channels in dsaf and rocee */ 2864 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK, 2865 true); 2866 msleep(SRST_TIME_INTERVAL); 2867 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, true); 2868 2869 /* enable dsaf channel rocee credit */ 2870 credit = dsaf_read_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG); 2871 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 0); 2872 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit); 2873 2874 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 1); 2875 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit); 2876 } 2877 return 0; 2878 } 2879 EXPORT_SYMBOL(hns_dsaf_roce_reset); 2880 2881 MODULE_LICENSE("GPL"); 2882 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2883 MODULE_DESCRIPTION("HNS DSAF driver"); 2884 MODULE_VERSION(DSAF_MOD_VERSION); 2885