1 /* 2 * Copyright (c) 2014-2015 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #ifndef __HNAE_H 11 #define __HNAE_H 12 13 /* Names used in this framework: 14 * ae handle (handle): 15 * a set of queues provided by AE 16 * ring buffer queue (rbq): 17 * the channel between upper layer and the AE, can do tx and rx 18 * ring: 19 * a tx or rx channel within a rbq 20 * ring description (desc): 21 * an element in the ring with packet information 22 * buffer: 23 * a memory region referred by desc with the full packet payload 24 * 25 * "num" means a static number set as a parameter, "count" mean a dynamic 26 * number set while running 27 * "cb" means control block 28 */ 29 30 #include <linux/acpi.h> 31 #include <linux/delay.h> 32 #include <linux/device.h> 33 #include <linux/module.h> 34 #include <linux/netdevice.h> 35 #include <linux/notifier.h> 36 #include <linux/phy.h> 37 #include <linux/types.h> 38 39 #define HNAE_DRIVER_VERSION "2.0" 40 #define HNAE_DRIVER_NAME "hns" 41 #define HNAE_COPYRIGHT "Copyright(c) 2015 Huawei Corporation." 42 #define HNAE_DRIVER_STRING "Hisilicon Network Subsystem Driver" 43 #define HNAE_DEFAULT_DEVICE_DESCR "Hisilicon Network Subsystem" 44 45 #ifdef DEBUG 46 47 #ifndef assert 48 #define assert(expr) \ 49 do { \ 50 if (!(expr)) { \ 51 pr_err("Assertion failed! %s, %s, %s, line %d\n", \ 52 #expr, __FILE__, __func__, __LINE__); \ 53 } \ 54 } while (0) 55 #endif 56 57 #else 58 59 #ifndef assert 60 #define assert(expr) 61 #endif 62 63 #endif 64 65 #define AE_VERSION_1 ('6' << 16 | '6' << 8 | '0') 66 #define AE_VERSION_2 ('1' << 24 | '6' << 16 | '1' << 8 | '0') 67 #define AE_IS_VER1(ver) ((ver) == AE_VERSION_1) 68 #define AE_NAME_SIZE 16 69 70 #define BD_SIZE_2048_MAX_MTU 6000 71 72 /* some said the RX and TX RCB format should not be the same in the future. But 73 * it is the same now... 74 */ 75 #define RCB_REG_BASEADDR_L 0x00 /* P660 support only 32bit accessing */ 76 #define RCB_REG_BASEADDR_H 0x04 77 #define RCB_REG_BD_NUM 0x08 78 #define RCB_REG_BD_LEN 0x0C 79 #define RCB_REG_PKTLINE 0x10 80 #define RCB_REG_TAIL 0x18 81 #define RCB_REG_HEAD 0x1C 82 #define RCB_REG_FBDNUM 0x20 83 #define RCB_REG_OFFSET 0x24 /* pkt num to be handled */ 84 #define RCB_REG_PKTNUM_RECORD 0x2C /* total pkt received */ 85 86 #define HNS_RX_HEAD_SIZE 256 87 88 #define HNAE_AE_REGISTER 0x1 89 90 #define RCB_RING_NAME_LEN (IFNAMSIZ + 4) 91 92 #define HNAE_LOWEST_LATENCY_COAL_PARAM 30 93 #define HNAE_LOW_LATENCY_COAL_PARAM 80 94 #define HNAE_BULK_LATENCY_COAL_PARAM 150 95 96 enum hnae_led_state { 97 HNAE_LED_INACTIVE, 98 HNAE_LED_ACTIVE, 99 HNAE_LED_ON, 100 HNAE_LED_OFF 101 }; 102 103 #define HNS_RX_FLAG_VLAN_PRESENT 0x1 104 #define HNS_RX_FLAG_L3ID_IPV4 0x0 105 #define HNS_RX_FLAG_L3ID_IPV6 0x1 106 #define HNS_RX_FLAG_L4ID_UDP 0x0 107 #define HNS_RX_FLAG_L4ID_TCP 0x1 108 #define HNS_RX_FLAG_L4ID_SCTP 0x3 109 110 #define HNS_TXD_ASID_S 0 111 #define HNS_TXD_ASID_M (0xff << HNS_TXD_ASID_S) 112 #define HNS_TXD_BUFNUM_S 8 113 #define HNS_TXD_BUFNUM_M (0x3 << HNS_TXD_BUFNUM_S) 114 #define HNS_TXD_PORTID_S 10 115 #define HNS_TXD_PORTID_M (0x7 << HNS_TXD_PORTID_S) 116 117 #define HNS_TXD_RA_B 8 118 #define HNS_TXD_RI_B 9 119 #define HNS_TXD_L4CS_B 10 120 #define HNS_TXD_L3CS_B 11 121 #define HNS_TXD_FE_B 12 122 #define HNS_TXD_VLD_B 13 123 #define HNS_TXD_IPOFFSET_S 14 124 #define HNS_TXD_IPOFFSET_M (0xff << HNS_TXD_IPOFFSET_S) 125 126 #define HNS_RXD_IPOFFSET_S 0 127 #define HNS_RXD_IPOFFSET_M (0xff << HNS_TXD_IPOFFSET_S) 128 #define HNS_RXD_BUFNUM_S 8 129 #define HNS_RXD_BUFNUM_M (0x3 << HNS_RXD_BUFNUM_S) 130 #define HNS_RXD_PORTID_S 10 131 #define HNS_RXD_PORTID_M (0x7 << HNS_RXD_PORTID_S) 132 #define HNS_RXD_DMAC_S 13 133 #define HNS_RXD_DMAC_M (0x3 << HNS_RXD_DMAC_S) 134 #define HNS_RXD_VLAN_S 15 135 #define HNS_RXD_VLAN_M (0x3 << HNS_RXD_VLAN_S) 136 #define HNS_RXD_L3ID_S 17 137 #define HNS_RXD_L3ID_M (0xf << HNS_RXD_L3ID_S) 138 #define HNS_RXD_L4ID_S 21 139 #define HNS_RXD_L4ID_M (0xf << HNS_RXD_L4ID_S) 140 #define HNS_RXD_FE_B 25 141 #define HNS_RXD_FRAG_B 26 142 #define HNS_RXD_VLD_B 27 143 #define HNS_RXD_L2E_B 28 144 #define HNS_RXD_L3E_B 29 145 #define HNS_RXD_L4E_B 30 146 #define HNS_RXD_DROP_B 31 147 148 #define HNS_RXD_VLANID_S 8 149 #define HNS_RXD_VLANID_M (0xfff << HNS_RXD_VLANID_S) 150 #define HNS_RXD_CFI_B 20 151 #define HNS_RXD_PRI_S 21 152 #define HNS_RXD_PRI_M (0x7 << HNS_RXD_PRI_S) 153 #define HNS_RXD_ASID_S 24 154 #define HNS_RXD_ASID_M (0xff << HNS_RXD_ASID_S) 155 156 #define HNSV2_TXD_BUFNUM_S 0 157 #define HNSV2_TXD_BUFNUM_M (0x7 << HNSV2_TXD_BUFNUM_S) 158 #define HNSV2_TXD_PORTID_S 4 159 #define HNSV2_TXD_PORTID_M (0X7 << HNSV2_TXD_PORTID_S) 160 #define HNSV2_TXD_RI_B 1 161 #define HNSV2_TXD_L4CS_B 2 162 #define HNSV2_TXD_L3CS_B 3 163 #define HNSV2_TXD_FE_B 4 164 #define HNSV2_TXD_VLD_B 5 165 166 #define HNSV2_TXD_TSE_B 0 167 #define HNSV2_TXD_VLAN_EN_B 1 168 #define HNSV2_TXD_SNAP_B 2 169 #define HNSV2_TXD_IPV6_B 3 170 #define HNSV2_TXD_SCTP_B 4 171 172 /* hardware spec ring buffer format */ 173 struct __packed hnae_desc { 174 __le64 addr; 175 union { 176 struct { 177 union { 178 __le16 asid_bufnum_pid; 179 __le16 asid; 180 }; 181 __le16 send_size; 182 union { 183 __le32 flag_ipoffset; 184 struct { 185 __u8 bn_pid; 186 __u8 ra_ri_cs_fe_vld; 187 __u8 ip_offset; 188 __u8 tse_vlan_snap_v6_sctp_nth; 189 }; 190 }; 191 __le16 mss; 192 __u8 l4_len; 193 __u8 reserved1; 194 __le16 paylen; 195 __u8 vmid; 196 __u8 qid; 197 __le32 reserved2[2]; 198 } tx; 199 200 struct { 201 __le32 ipoff_bnum_pid_flag; 202 __le16 pkt_len; 203 __le16 size; 204 union { 205 __le32 vlan_pri_asid; 206 struct { 207 __le16 asid; 208 __le16 vlan_cfi_pri; 209 }; 210 }; 211 __le32 rss_hash; 212 __le32 reserved_1[2]; 213 } rx; 214 }; 215 }; 216 217 struct hnae_desc_cb { 218 dma_addr_t dma; /* dma address of this desc */ 219 void *buf; /* cpu addr for a desc */ 220 221 /* priv data for the desc, e.g. skb when use with ip stack*/ 222 void *priv; 223 u32 page_offset; 224 u32 length; /* length of the buffer */ 225 226 u16 reuse_flag; 227 228 /* desc type, used by the ring user to mark the type of the priv data */ 229 u16 type; 230 }; 231 232 #define setflags(flags, bits) ((flags) |= (bits)) 233 #define unsetflags(flags, bits) ((flags) &= ~(bits)) 234 235 /* hnae_ring->flags fields */ 236 #define RINGF_DIR 0x1 /* TX or RX ring, set if TX */ 237 #define is_tx_ring(ring) ((ring)->flags & RINGF_DIR) 238 #define is_rx_ring(ring) (!is_tx_ring(ring)) 239 #define ring_to_dma_dir(ring) (is_tx_ring(ring) ? \ 240 DMA_TO_DEVICE : DMA_FROM_DEVICE) 241 242 struct ring_stats { 243 u64 io_err_cnt; 244 u64 sw_err_cnt; 245 u64 seg_pkt_cnt; 246 union { 247 struct { 248 u64 tx_pkts; 249 u64 tx_bytes; 250 u64 tx_err_cnt; 251 u64 restart_queue; 252 u64 tx_busy; 253 }; 254 struct { 255 u64 rx_pkts; 256 u64 rx_bytes; 257 u64 rx_err_cnt; 258 u64 reuse_pg_cnt; 259 u64 err_pkt_len; 260 u64 non_vld_descs; 261 u64 err_bd_num; 262 u64 l2_err; 263 u64 l3l4_csum_err; 264 }; 265 }; 266 }; 267 268 struct hnae_queue; 269 270 struct hnae_ring { 271 u8 __iomem *io_base; /* base io address for the ring */ 272 struct hnae_desc *desc; /* dma map address space */ 273 struct hnae_desc_cb *desc_cb; 274 struct hnae_queue *q; 275 int irq; 276 char ring_name[RCB_RING_NAME_LEN]; 277 278 /* statistic */ 279 struct ring_stats stats; 280 281 /* ring lock for poll one */ 282 spinlock_t lock; 283 284 dma_addr_t desc_dma_addr; 285 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 286 u16 desc_num; /* total number of desc */ 287 u16 max_desc_num_per_pkt; 288 u16 max_raw_data_sz_per_desc; 289 u16 max_pkt_size; 290 int next_to_use; /* idx of next spare desc */ 291 292 /* idx of lastest sent desc, the ring is empty when equal to 293 * next_to_use 294 */ 295 int next_to_clean; 296 297 int flags; /* ring attribute */ 298 int irq_init_flag; 299 300 /* total rx bytes after last rx rate calucated */ 301 u64 coal_last_rx_bytes; 302 unsigned long coal_last_jiffies; 303 u32 coal_param; 304 u32 coal_rx_rate; /* rx rate in MB */ 305 }; 306 307 #define ring_ptr_move_fw(ring, p) \ 308 ((ring)->p = ((ring)->p + 1) % (ring)->desc_num) 309 #define ring_ptr_move_bw(ring, p) \ 310 ((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num) 311 312 enum hns_desc_type { 313 DESC_TYPE_SKB, 314 DESC_TYPE_PAGE, 315 }; 316 317 #define assert_is_ring_idx(ring, idx) \ 318 assert((idx) >= 0 && (idx) < (ring)->desc_num) 319 320 /* the distance between [begin, end) in a ring buffer 321 * note: there is a unuse slot between the begin and the end 322 */ 323 static inline int ring_dist(struct hnae_ring *ring, int begin, int end) 324 { 325 assert_is_ring_idx(ring, begin); 326 assert_is_ring_idx(ring, end); 327 328 return (end - begin + ring->desc_num) % ring->desc_num; 329 } 330 331 static inline int ring_space(struct hnae_ring *ring) 332 { 333 return ring->desc_num - 334 ring_dist(ring, ring->next_to_clean, ring->next_to_use) - 1; 335 } 336 337 static inline int is_ring_empty(struct hnae_ring *ring) 338 { 339 assert_is_ring_idx(ring, ring->next_to_use); 340 assert_is_ring_idx(ring, ring->next_to_clean); 341 342 return ring->next_to_use == ring->next_to_clean; 343 } 344 345 #define hnae_buf_size(_ring) ((_ring)->buf_size) 346 #define hnae_page_order(_ring) (get_order(hnae_buf_size(_ring))) 347 #define hnae_page_size(_ring) (PAGE_SIZE << hnae_page_order(_ring)) 348 349 struct hnae_handle; 350 351 /* allocate and dma map space for hnae desc */ 352 struct hnae_buf_ops { 353 int (*alloc_buffer)(struct hnae_ring *ring, struct hnae_desc_cb *cb); 354 void (*free_buffer)(struct hnae_ring *ring, struct hnae_desc_cb *cb); 355 int (*map_buffer)(struct hnae_ring *ring, struct hnae_desc_cb *cb); 356 void (*unmap_buffer)(struct hnae_ring *ring, struct hnae_desc_cb *cb); 357 }; 358 359 struct hnae_queue { 360 u8 __iomem *io_base; 361 phys_addr_t phy_base; 362 struct hnae_ae_dev *dev; /* the device who use this queue */ 363 struct hnae_ring rx_ring ____cacheline_internodealigned_in_smp; 364 struct hnae_ring tx_ring ____cacheline_internodealigned_in_smp; 365 struct hnae_handle *handle; 366 }; 367 368 /*hnae loop mode*/ 369 enum hnae_loop { 370 MAC_INTERNALLOOP_MAC = 0, 371 MAC_INTERNALLOOP_SERDES, 372 MAC_INTERNALLOOP_PHY, 373 MAC_LOOP_PHY_NONE, 374 MAC_LOOP_NONE, 375 }; 376 377 /*hnae port type*/ 378 enum hnae_port_type { 379 HNAE_PORT_SERVICE = 0, 380 HNAE_PORT_DEBUG 381 }; 382 383 /* mac media type */ 384 enum hnae_media_type { 385 HNAE_MEDIA_TYPE_UNKNOWN = 0, 386 HNAE_MEDIA_TYPE_FIBER, 387 HNAE_MEDIA_TYPE_COPPER, 388 HNAE_MEDIA_TYPE_BACKPLANE, 389 }; 390 391 /* This struct defines the operation on the handle. 392 * 393 * get_handle(): (mandatory) 394 * Get a handle from AE according to its name and options. 395 * the AE driver should manage the space used by handle and its queues while 396 * the HNAE framework will allocate desc and desc_cb for all rings in the 397 * queues. 398 * put_handle(): 399 * Release the handle. 400 * start(): 401 * Enable the hardware, include all queues 402 * stop(): 403 * Disable the hardware 404 * set_opts(): (mandatory) 405 * Set options to the AE 406 * get_opts(): (mandatory) 407 * Get options from the AE 408 * get_status(): 409 * Get the carrier state of the back channel of the handle, 1 for ok, 0 for 410 * non-ok 411 * toggle_ring_irq(): (mandatory) 412 * Set the ring irq to be enabled(0) or disable(1) 413 * toggle_queue_status(): (mandatory) 414 * Set the queue to be enabled(1) or disable(0), this will not change the 415 * ring irq state 416 * adjust_link() 417 * adjust link status 418 * set_loopback() 419 * set loopback 420 * get_ring_bdnum_limit() 421 * get ring bd number limit 422 * get_pauseparam() 423 * get tx and rx of pause frame use 424 * set_autoneg() 425 * set auto autonegotiation of pause frame use 426 * get_autoneg() 427 * get auto autonegotiation of pause frame use 428 * set_pauseparam() 429 * set tx and rx of pause frame use 430 * get_coalesce_usecs() 431 * get usecs to delay a TX interrupt after a packet is sent 432 * get_rx_max_coalesced_frames() 433 * get Maximum number of packets to be sent before a TX interrupt. 434 * set_coalesce_usecs() 435 * set usecs to delay a TX interrupt after a packet is sent 436 * set_coalesce_frames() 437 * set Maximum number of packets to be sent before a TX interrupt. 438 * get_ringnum() 439 * get RX/TX ring number 440 * get_max_ringnum() 441 * get RX/TX ring maximum number 442 * get_mac_addr() 443 * get mac address 444 * set_mac_addr() 445 * set mac address 446 * clr_mc_addr() 447 * clear mcast tcam table 448 * set_mc_addr() 449 * set multicast mode 450 * add_uc_addr() 451 * add ucast address 452 * rm_uc_addr() 453 * remove ucast address 454 * set_mtu() 455 * set mtu 456 * update_stats() 457 * update Old network device statistics 458 * get_ethtool_stats() 459 * get ethtool network device statistics 460 * get_strings() 461 * get a set of strings that describe the requested objects 462 * get_sset_count() 463 * get number of strings that @get_strings will write 464 * update_led_status() 465 * update the led status 466 * set_led_id() 467 * set led id 468 * get_regs() 469 * get regs dump 470 * get_regs_len() 471 * get the len of the regs dump 472 */ 473 struct hnae_ae_ops { 474 struct hnae_handle *(*get_handle)(struct hnae_ae_dev *dev, 475 u32 port_id); 476 void (*put_handle)(struct hnae_handle *handle); 477 void (*init_queue)(struct hnae_queue *q); 478 void (*fini_queue)(struct hnae_queue *q); 479 int (*start)(struct hnae_handle *handle); 480 void (*stop)(struct hnae_handle *handle); 481 void (*reset)(struct hnae_handle *handle); 482 int (*set_opts)(struct hnae_handle *handle, int type, void *opts); 483 int (*get_opts)(struct hnae_handle *handle, int type, void **opts); 484 int (*get_status)(struct hnae_handle *handle); 485 int (*get_info)(struct hnae_handle *handle, 486 u8 *auto_neg, u16 *speed, u8 *duplex); 487 void (*toggle_ring_irq)(struct hnae_ring *ring, u32 val); 488 void (*adjust_link)(struct hnae_handle *handle, int speed, int duplex); 489 bool (*need_adjust_link)(struct hnae_handle *handle, 490 int speed, int duplex); 491 int (*set_loopback)(struct hnae_handle *handle, 492 enum hnae_loop loop_mode, int en); 493 void (*get_ring_bdnum_limit)(struct hnae_queue *queue, 494 u32 *uplimit); 495 void (*get_pauseparam)(struct hnae_handle *handle, 496 u32 *auto_neg, u32 *rx_en, u32 *tx_en); 497 int (*set_autoneg)(struct hnae_handle *handle, u8 enable); 498 int (*get_autoneg)(struct hnae_handle *handle); 499 int (*set_pauseparam)(struct hnae_handle *handle, 500 u32 auto_neg, u32 rx_en, u32 tx_en); 501 void (*get_coalesce_usecs)(struct hnae_handle *handle, 502 u32 *tx_usecs, u32 *rx_usecs); 503 void (*get_max_coalesced_frames)(struct hnae_handle *handle, 504 u32 *tx_frames, u32 *rx_frames); 505 int (*set_coalesce_usecs)(struct hnae_handle *handle, u32 timeout); 506 int (*set_coalesce_frames)(struct hnae_handle *handle, 507 u32 tx_frames, u32 rx_frames); 508 void (*get_coalesce_range)(struct hnae_handle *handle, 509 u32 *tx_frames_low, u32 *rx_frames_low, 510 u32 *tx_frames_high, u32 *rx_frames_high, 511 u32 *tx_usecs_low, u32 *rx_usecs_low, 512 u32 *tx_usecs_high, u32 *rx_usecs_high); 513 void (*set_promisc_mode)(struct hnae_handle *handle, u32 en); 514 int (*get_mac_addr)(struct hnae_handle *handle, void **p); 515 int (*set_mac_addr)(struct hnae_handle *handle, void *p); 516 int (*add_uc_addr)(struct hnae_handle *handle, 517 const unsigned char *addr); 518 int (*rm_uc_addr)(struct hnae_handle *handle, 519 const unsigned char *addr); 520 int (*clr_mc_addr)(struct hnae_handle *handle); 521 int (*set_mc_addr)(struct hnae_handle *handle, void *addr); 522 int (*set_mtu)(struct hnae_handle *handle, int new_mtu); 523 void (*set_tso_stats)(struct hnae_handle *handle, int enable); 524 void (*update_stats)(struct hnae_handle *handle, 525 struct net_device_stats *net_stats); 526 void (*get_stats)(struct hnae_handle *handle, u64 *data); 527 void (*get_strings)(struct hnae_handle *handle, 528 u32 stringset, u8 *data); 529 int (*get_sset_count)(struct hnae_handle *handle, int stringset); 530 void (*update_led_status)(struct hnae_handle *handle); 531 int (*set_led_id)(struct hnae_handle *handle, 532 enum hnae_led_state status); 533 void (*get_regs)(struct hnae_handle *handle, void *data); 534 int (*get_regs_len)(struct hnae_handle *handle); 535 u32 (*get_rss_key_size)(struct hnae_handle *handle); 536 u32 (*get_rss_indir_size)(struct hnae_handle *handle); 537 int (*get_rss)(struct hnae_handle *handle, u32 *indir, u8 *key, 538 u8 *hfunc); 539 int (*set_rss)(struct hnae_handle *handle, const u32 *indir, 540 const u8 *key, const u8 hfunc); 541 }; 542 543 struct hnae_ae_dev { 544 struct device cls_dev; /* the class dev */ 545 struct device *dev; /* the presented dev */ 546 struct hnae_ae_ops *ops; 547 struct list_head node; 548 struct module *owner; /* the module who provides this dev */ 549 int id; 550 char name[AE_NAME_SIZE]; 551 struct list_head handle_list; 552 spinlock_t lock; /* lock to protect the handle_list */ 553 }; 554 555 struct hnae_handle { 556 struct device *owner_dev; /* the device which make use of this handle */ 557 struct hnae_ae_dev *dev; /* the device who provides this handle */ 558 struct phy_device *phy_dev; 559 phy_interface_t phy_if; 560 u32 if_support; 561 int q_num; 562 int vf_id; 563 unsigned long coal_last_jiffies; 564 u32 coal_param; /* self adapt coalesce param */ 565 /* the ring index of last ring that set coal param */ 566 u32 coal_ring_idx; 567 u32 eport_id; 568 u32 dport_id; /* v2 tx bd should fill the dport_id */ 569 bool coal_adapt_en; 570 enum hnae_port_type port_type; 571 enum hnae_media_type media_type; 572 struct list_head node; /* list to hnae_ae_dev->handle_list */ 573 struct hnae_buf_ops *bops; /* operation for the buffer */ 574 struct hnae_queue **qs; /* array base of all queues */ 575 }; 576 577 #define ring_to_dev(ring) ((ring)->q->dev->dev) 578 579 struct hnae_handle *hnae_get_handle(struct device *owner_dev, 580 const struct fwnode_handle *fwnode, 581 u32 port_id, 582 struct hnae_buf_ops *bops); 583 584 void hnae_put_handle(struct hnae_handle *handle); 585 int hnae_ae_register(struct hnae_ae_dev *dev, struct module *owner); 586 void hnae_ae_unregister(struct hnae_ae_dev *dev); 587 588 int hnae_register_notifier(struct notifier_block *nb); 589 void hnae_unregister_notifier(struct notifier_block *nb); 590 int hnae_reinit_handle(struct hnae_handle *handle); 591 592 #define hnae_queue_xmit(q, buf_num) writel_relaxed(buf_num, \ 593 (q)->tx_ring.io_base + RCB_REG_TAIL) 594 595 #ifndef assert 596 #define assert(cond) 597 #endif 598 599 static inline int hnae_reserve_buffer_map(struct hnae_ring *ring, 600 struct hnae_desc_cb *cb) 601 { 602 struct hnae_buf_ops *bops = ring->q->handle->bops; 603 int ret; 604 605 ret = bops->alloc_buffer(ring, cb); 606 if (ret) 607 goto out; 608 609 ret = bops->map_buffer(ring, cb); 610 if (ret) 611 goto out_with_buf; 612 613 return 0; 614 615 out_with_buf: 616 bops->free_buffer(ring, cb); 617 out: 618 return ret; 619 } 620 621 static inline int hnae_alloc_buffer_attach(struct hnae_ring *ring, int i) 622 { 623 int ret = hnae_reserve_buffer_map(ring, &ring->desc_cb[i]); 624 625 if (ret) 626 return ret; 627 628 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 629 630 return 0; 631 } 632 633 static inline void hnae_buffer_detach(struct hnae_ring *ring, int i) 634 { 635 ring->q->handle->bops->unmap_buffer(ring, &ring->desc_cb[i]); 636 ring->desc[i].addr = 0; 637 } 638 639 static inline void hnae_free_buffer_detach(struct hnae_ring *ring, int i) 640 { 641 struct hnae_buf_ops *bops = ring->q->handle->bops; 642 struct hnae_desc_cb *cb = &ring->desc_cb[i]; 643 644 if (!ring->desc_cb[i].dma) 645 return; 646 647 hnae_buffer_detach(ring, i); 648 bops->free_buffer(ring, cb); 649 } 650 651 /* detach a in-used buffer and replace with a reserved one */ 652 static inline void hnae_replace_buffer(struct hnae_ring *ring, int i, 653 struct hnae_desc_cb *res_cb) 654 { 655 struct hnae_buf_ops *bops = ring->q->handle->bops; 656 657 bops->unmap_buffer(ring, &ring->desc_cb[i]); 658 ring->desc_cb[i] = *res_cb; 659 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 660 ring->desc[i].rx.ipoff_bnum_pid_flag = 0; 661 } 662 663 static inline void hnae_reuse_buffer(struct hnae_ring *ring, int i) 664 { 665 ring->desc_cb[i].reuse_flag = 0; 666 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma 667 + ring->desc_cb[i].page_offset); 668 ring->desc[i].rx.ipoff_bnum_pid_flag = 0; 669 } 670 671 /* when reinit buffer size, we should reinit buffer description */ 672 static inline void hnae_reinit_all_ring_desc(struct hnae_handle *h) 673 { 674 int i, j; 675 struct hnae_ring *ring; 676 677 for (i = 0; i < h->q_num; i++) { 678 ring = &h->qs[i]->rx_ring; 679 for (j = 0; j < ring->desc_num; j++) 680 ring->desc[j].addr = cpu_to_le64(ring->desc_cb[j].dma); 681 } 682 683 wmb(); /* commit all data before submit */ 684 } 685 686 /* when reinit buffer size, we should reinit page offset */ 687 static inline void hnae_reinit_all_ring_page_off(struct hnae_handle *h) 688 { 689 int i, j; 690 struct hnae_ring *ring; 691 692 for (i = 0; i < h->q_num; i++) { 693 ring = &h->qs[i]->rx_ring; 694 for (j = 0; j < ring->desc_num; j++) { 695 ring->desc_cb[j].page_offset = 0; 696 if (ring->desc[j].addr != 697 cpu_to_le64(ring->desc_cb[j].dma)) 698 ring->desc[j].addr = 699 cpu_to_le64(ring->desc_cb[j].dma); 700 } 701 } 702 703 wmb(); /* commit all data before submit */ 704 } 705 706 #define hnae_set_field(origin, mask, shift, val) \ 707 do { \ 708 (origin) &= (~(mask)); \ 709 (origin) |= ((val) << (shift)) & (mask); \ 710 } while (0) 711 712 #define hnae_set_bit(origin, shift, val) \ 713 hnae_set_field((origin), (0x1 << (shift)), (shift), (val)) 714 715 #define hnae_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift)) 716 717 #define hnae_get_bit(origin, shift) \ 718 hnae_get_field((origin), (0x1 << (shift)), (shift)) 719 720 #endif 721