1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2024 Hisilicon Limited. */ 3 4 #ifndef __HBG_REG_H 5 #define __HBG_REG_H 6 7 /* DEV SPEC */ 8 #define HBG_REG_SPEC_VALID_ADDR 0x0000 9 #define HBG_REG_EVENT_REQ_ADDR 0x0004 10 #define HBG_REG_MAC_ID_ADDR 0x0008 11 #define HBG_REG_PHY_ID_ADDR 0x000C 12 #define HBG_REG_MAC_ADDR_ADDR 0x0010 13 #define HBG_REG_MDIO_FREQ_ADDR 0x0024 14 #define HBG_REG_MAX_MTU_ADDR 0x0028 15 #define HBG_REG_MIN_MTU_ADDR 0x002C 16 #define HBG_REG_TX_FIFO_NUM_ADDR 0x0030 17 #define HBG_REG_RX_FIFO_NUM_ADDR 0x0034 18 #define HBG_REG_VLAN_LAYERS_ADDR 0x0038 19 20 /* MDIO */ 21 #define HBG_REG_MDIO_BASE 0x8000 22 #define HBG_REG_MDIO_COMMAND_ADDR (HBG_REG_MDIO_BASE + 0x0000) 23 #define HBG_REG_MDIO_COMMAND_CLK_SEL_EXP_B BIT(17) 24 #define HBG_REG_MDIO_COMMAND_AUTO_SCAN_B BIT(16) 25 #define HBG_REG_MDIO_COMMAND_CLK_SEL_B BIT(15) 26 #define HBG_REG_MDIO_COMMAND_START_B BIT(14) 27 #define HBG_REG_MDIO_COMMAND_ST_M GENMASK(13, 12) 28 #define HBG_REG_MDIO_COMMAND_OP_M GENMASK(11, 10) 29 #define HBG_REG_MDIO_COMMAND_PRTAD_M GENMASK(9, 5) 30 #define HBG_REG_MDIO_COMMAND_DEVAD_M GENMASK(4, 0) 31 #define HBG_REG_MDIO_WDATA_ADDR (HBG_REG_MDIO_BASE + 0x0008) 32 #define HBG_REG_MDIO_WDATA_M GENMASK(15, 0) 33 #define HBG_REG_MDIO_RDATA_ADDR (HBG_REG_MDIO_BASE + 0x000C) 34 #define HBG_REG_MDIO_STA_ADDR (HBG_REG_MDIO_BASE + 0x0010) 35 36 /* GMAC */ 37 #define HBG_REG_SGMII_BASE 0x10000 38 #define HBG_REG_DUPLEX_TYPE_ADDR (HBG_REG_SGMII_BASE + 0x0008) 39 #define HBG_REG_DUPLEX_B BIT(0) 40 #define HBG_REG_MAX_FRAME_SIZE_ADDR (HBG_REG_SGMII_BASE + 0x003C) 41 #define HBG_REG_PORT_MODE_ADDR (HBG_REG_SGMII_BASE + 0x0040) 42 #define HBG_REG_PORT_MODE_M GENMASK(3, 0) 43 #define HBG_REG_PORT_ENABLE_ADDR (HBG_REG_SGMII_BASE + 0x0044) 44 #define HBG_REG_PORT_ENABLE_RX_B BIT(1) 45 #define HBG_REG_PORT_ENABLE_TX_B BIT(2) 46 #define HBG_REG_TRANSMIT_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x0060) 47 #define HBG_REG_TRANSMIT_CTRL_PAD_EN_B BIT(7) 48 #define HBG_REG_TRANSMIT_CTRL_CRC_ADD_B BIT(6) 49 #define HBG_REG_TRANSMIT_CTRL_AN_EN_B BIT(5) 50 #define HBG_REG_CF_CRC_STRIP_ADDR (HBG_REG_SGMII_BASE + 0x01B0) 51 #define HBG_REG_CF_CRC_STRIP_B BIT(0) 52 #define HBG_REG_MODE_CHANGE_EN_ADDR (HBG_REG_SGMII_BASE + 0x01B4) 53 #define HBG_REG_MODE_CHANGE_EN_B BIT(0) 54 #define HBG_REG_RECV_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x01E0) 55 #define HBG_REG_RECV_CTRL_STRIP_PAD_EN_B BIT(3) 56 #define HBG_REG_STATION_ADDR_LOW_2_ADDR (HBG_REG_SGMII_BASE + 0x0210) 57 #define HBG_REG_STATION_ADDR_HIGH_2_ADDR (HBG_REG_SGMII_BASE + 0x0214) 58 59 /* PCU */ 60 #define HBG_REG_CF_INTRPT_MSK_ADDR (HBG_REG_SGMII_BASE + 0x042C) 61 #define HBG_INT_MSK_WE_ERR_B BIT(31) 62 #define HBG_INT_MSK_RBREQ_ERR_B BIT(30) 63 #define HBG_INT_MSK_MAC_FIFO_ERR_B BIT(29) 64 #define HBG_INT_MSK_RX_AHB_ERR_B BIT(28) 65 #define HBG_INT_MSK_RX_DROP_B BIT(26) 66 #define HBG_INT_MSK_TX_DROP_B BIT(25) 67 #define HBG_INT_MSK_TXCFG_AVL_B BIT(24) 68 #define HBG_INT_MSK_REL_BUF_ERR_B BIT(23) 69 #define HBG_INT_MSK_RX_BUF_AVL_B BIT(22) 70 #define HBG_INT_MSK_TX_AHB_ERR_B BIT(21) 71 #define HBG_INT_MSK_SRAM_PARITY_ERR_B BIT(20) 72 #define HBG_INT_MSK_MAC_APP_TX_FIFO_ERR_B BIT(19) 73 #define HBG_INT_MSK_MAC_APP_RX_FIFO_ERR_B BIT(18) 74 #define HBG_INT_MSK_MAC_PCS_TX_FIFO_ERR_B BIT(17) 75 #define HBG_INT_MSK_MAC_PCS_RX_FIFO_ERR_B BIT(16) 76 #define HBG_INT_MSK_MAC_MII_FIFO_ERR_B BIT(15) 77 #define HBG_INT_MSK_TX_B BIT(1) /* just used in driver */ 78 #define HBG_INT_MSK_RX_B BIT(0) /* just used in driver */ 79 #define HBG_REG_CF_INTRPT_STAT_ADDR (HBG_REG_SGMII_BASE + 0x0434) 80 #define HBG_REG_CF_INTRPT_CLR_ADDR (HBG_REG_SGMII_BASE + 0x0438) 81 #define HBG_REG_MAX_FRAME_LEN_ADDR (HBG_REG_SGMII_BASE + 0x0444) 82 #define HBG_REG_MAX_FRAME_LEN_M GENMASK(15, 0) 83 #define HBG_REG_RX_BUF_SIZE_ADDR (HBG_REG_SGMII_BASE + 0x04E4) 84 #define HBG_REG_RX_BUF_SIZE_M GENMASK(15, 0) 85 #define HBG_REG_BUS_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x04E8) 86 #define HBG_REG_BUS_CTRL_ENDIAN_M GENMASK(2, 1) 87 #define HBG_REG_RX_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x04F0) 88 #define HBG_REG_RX_CTRL_RXBUF_1ST_SKIP_SIZE_M GENMASK(31, 28) 89 #define HBG_REG_RX_CTRL_TIME_INF_EN_B BIT(23) 90 #define HBG_REG_RX_CTRL_RX_ALIGN_NUM_M GENMASK(18, 17) 91 #define HBG_REG_RX_CTRL_PORT_NUM GENMASK(16, 13) 92 #define HBG_REG_RX_CTRL_RX_GET_ADDR_MODE_B BIT(12) 93 #define HBG_REG_RX_CTRL_RXBUF_1ST_SKIP_SIZE2_M GENMASK(3, 0) 94 #define HBG_REG_RX_PKT_MODE_ADDR (HBG_REG_SGMII_BASE + 0x04F4) 95 #define HBG_REG_RX_PKT_MODE_PARSE_MODE_M GENMASK(22, 21) 96 #define HBG_REG_CF_IND_TXINT_MSK_ADDR (HBG_REG_SGMII_BASE + 0x0694) 97 #define HBG_REG_IND_INTR_MASK_B BIT(0) 98 #define HBG_REG_CF_IND_TXINT_STAT_ADDR (HBG_REG_SGMII_BASE + 0x0698) 99 #define HBG_REG_CF_IND_TXINT_CLR_ADDR (HBG_REG_SGMII_BASE + 0x069C) 100 #define HBG_REG_CF_IND_RXINT_MSK_ADDR (HBG_REG_SGMII_BASE + 0x06a0) 101 #define HBG_REG_CF_IND_RXINT_STAT_ADDR (HBG_REG_SGMII_BASE + 0x06a4) 102 #define HBG_REG_CF_IND_RXINT_CLR_ADDR (HBG_REG_SGMII_BASE + 0x06a8) 103 104 enum hbg_port_mode { 105 /* 0x0 ~ 0x5 are reserved */ 106 HBG_PORT_MODE_SGMII_10M = 0x6, 107 HBG_PORT_MODE_SGMII_100M = 0x7, 108 HBG_PORT_MODE_SGMII_1000M = 0x8, 109 }; 110 111 #endif 112