1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2024 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/if_vlan.h> 6 #include <linux/netdevice.h> 7 #include <linux/pci.h> 8 #include "hbg_common.h" 9 #include "hbg_ethtool.h" 10 #include "hbg_hw.h" 11 #include "hbg_irq.h" 12 #include "hbg_mdio.h" 13 #include "hbg_txrx.h" 14 15 static void hbg_change_mtu(struct hbg_priv *priv, int new_mtu); 16 17 static void hbg_all_irq_enable(struct hbg_priv *priv, bool enabled) 18 { 19 struct hbg_irq_info *info; 20 u32 i; 21 22 for (i = 0; i < priv->vectors.info_array_len; i++) { 23 info = &priv->vectors.info_array[i]; 24 hbg_hw_irq_enable(priv, info->mask, enabled); 25 } 26 } 27 28 static int hbg_net_open(struct net_device *netdev) 29 { 30 struct hbg_priv *priv = netdev_priv(netdev); 31 int ret; 32 33 ret = hbg_txrx_init(priv); 34 if (ret) 35 return ret; 36 37 hbg_all_irq_enable(priv, true); 38 hbg_hw_mac_enable(priv, HBG_STATUS_ENABLE); 39 netif_start_queue(netdev); 40 hbg_phy_start(priv); 41 42 return 0; 43 } 44 45 /* This function only can be called after hbg_txrx_uninit() */ 46 static int hbg_hw_txrx_clear(struct hbg_priv *priv) 47 { 48 int ret; 49 50 /* After ring buffers have been released, 51 * do a reset to release hw fifo rx ring buffer 52 */ 53 ret = hbg_hw_event_notify(priv, HBG_HW_EVENT_RESET); 54 if (ret) 55 return ret; 56 57 /* After reset, regs need to be reconfigured */ 58 hbg_hw_init(priv); 59 hbg_hw_set_uc_addr(priv, ether_addr_to_u64(priv->netdev->dev_addr)); 60 hbg_change_mtu(priv, priv->netdev->mtu); 61 62 return 0; 63 } 64 65 static int hbg_net_stop(struct net_device *netdev) 66 { 67 struct hbg_priv *priv = netdev_priv(netdev); 68 69 hbg_phy_stop(priv); 70 netif_stop_queue(netdev); 71 hbg_hw_mac_enable(priv, HBG_STATUS_DISABLE); 72 hbg_all_irq_enable(priv, false); 73 hbg_txrx_uninit(priv); 74 return hbg_hw_txrx_clear(priv); 75 } 76 77 static int hbg_net_set_mac_address(struct net_device *netdev, void *addr) 78 { 79 struct hbg_priv *priv = netdev_priv(netdev); 80 u8 *mac_addr; 81 82 mac_addr = ((struct sockaddr *)addr)->sa_data; 83 84 if (!is_valid_ether_addr(mac_addr)) 85 return -EADDRNOTAVAIL; 86 87 hbg_hw_set_uc_addr(priv, ether_addr_to_u64(mac_addr)); 88 dev_addr_set(netdev, mac_addr); 89 90 return 0; 91 } 92 93 static void hbg_change_mtu(struct hbg_priv *priv, int new_mtu) 94 { 95 u32 frame_len; 96 97 frame_len = new_mtu + VLAN_HLEN * priv->dev_specs.vlan_layers + 98 ETH_HLEN + ETH_FCS_LEN; 99 hbg_hw_set_mtu(priv, frame_len); 100 } 101 102 static int hbg_net_change_mtu(struct net_device *netdev, int new_mtu) 103 { 104 struct hbg_priv *priv = netdev_priv(netdev); 105 106 if (netif_running(netdev)) 107 return -EBUSY; 108 109 hbg_change_mtu(priv, new_mtu); 110 WRITE_ONCE(netdev->mtu, new_mtu); 111 112 dev_dbg(&priv->pdev->dev, 113 "change mtu from %u to %u\n", netdev->mtu, new_mtu); 114 115 return 0; 116 } 117 118 static void hbg_net_tx_timeout(struct net_device *netdev, unsigned int txqueue) 119 { 120 struct hbg_priv *priv = netdev_priv(netdev); 121 struct hbg_ring *ring = &priv->tx_ring; 122 char *buf = ring->tout_log_buf; 123 u32 pos = 0; 124 125 pos += scnprintf(buf + pos, HBG_TX_TIMEOUT_BUF_LEN - pos, 126 "ring used num: %u, fifo used num: %u\n", 127 hbg_get_queue_used_num(ring), 128 hbg_hw_get_fifo_used_num(priv, HBG_DIR_TX)); 129 pos += scnprintf(buf + pos, HBG_TX_TIMEOUT_BUF_LEN - pos, 130 "ntc: %u, ntu: %u, irq enabled: %u\n", 131 ring->ntc, ring->ntu, 132 hbg_hw_irq_is_enabled(priv, HBG_INT_MSK_TX_B)); 133 134 netdev_info(netdev, "%s", buf); 135 } 136 137 static const struct net_device_ops hbg_netdev_ops = { 138 .ndo_open = hbg_net_open, 139 .ndo_stop = hbg_net_stop, 140 .ndo_start_xmit = hbg_net_start_xmit, 141 .ndo_validate_addr = eth_validate_addr, 142 .ndo_set_mac_address = hbg_net_set_mac_address, 143 .ndo_change_mtu = hbg_net_change_mtu, 144 .ndo_tx_timeout = hbg_net_tx_timeout, 145 }; 146 147 static int hbg_init(struct hbg_priv *priv) 148 { 149 int ret; 150 151 ret = hbg_hw_event_notify(priv, HBG_HW_EVENT_INIT); 152 if (ret) 153 return ret; 154 155 ret = hbg_hw_init(priv); 156 if (ret) 157 return ret; 158 159 ret = hbg_irq_init(priv); 160 if (ret) 161 return ret; 162 163 return hbg_mdio_init(priv); 164 } 165 166 static int hbg_pci_init(struct pci_dev *pdev) 167 { 168 struct net_device *netdev = pci_get_drvdata(pdev); 169 struct hbg_priv *priv = netdev_priv(netdev); 170 struct device *dev = &pdev->dev; 171 int ret; 172 173 ret = pcim_enable_device(pdev); 174 if (ret) 175 return dev_err_probe(dev, ret, "failed to enable PCI device\n"); 176 177 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 178 if (ret) 179 return dev_err_probe(dev, ret, "failed to set PCI DMA mask\n"); 180 181 ret = pcim_iomap_regions(pdev, BIT(0), dev_driver_string(dev)); 182 if (ret) 183 return dev_err_probe(dev, ret, "failed to map PCI bar space\n"); 184 185 priv->io_base = pcim_iomap_table(pdev)[0]; 186 if (!priv->io_base) 187 return dev_err_probe(dev, -ENOMEM, "failed to get io base\n"); 188 189 pci_set_master(pdev); 190 return 0; 191 } 192 193 static int hbg_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 194 { 195 struct device *dev = &pdev->dev; 196 struct net_device *netdev; 197 struct hbg_priv *priv; 198 int ret; 199 200 netdev = devm_alloc_etherdev(dev, sizeof(struct hbg_priv)); 201 if (!netdev) 202 return -ENOMEM; 203 204 pci_set_drvdata(pdev, netdev); 205 SET_NETDEV_DEV(netdev, dev); 206 207 priv = netdev_priv(netdev); 208 priv->netdev = netdev; 209 priv->pdev = pdev; 210 211 ret = hbg_pci_init(pdev); 212 if (ret) 213 return ret; 214 215 ret = hbg_init(priv); 216 if (ret) 217 return ret; 218 219 netdev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 220 netdev->max_mtu = priv->dev_specs.max_mtu; 221 netdev->min_mtu = priv->dev_specs.min_mtu; 222 netdev->netdev_ops = &hbg_netdev_ops; 223 netdev->watchdog_timeo = 5 * HZ; 224 225 hbg_change_mtu(priv, ETH_DATA_LEN); 226 hbg_net_set_mac_address(priv->netdev, &priv->dev_specs.mac_addr); 227 hbg_ethtool_set_ops(netdev); 228 229 ret = devm_register_netdev(dev, netdev); 230 if (ret) 231 return dev_err_probe(dev, ret, "failed to register netdev\n"); 232 233 netif_carrier_off(netdev); 234 return 0; 235 } 236 237 static const struct pci_device_id hbg_pci_tbl[] = { 238 {PCI_VDEVICE(HUAWEI, 0x3730), 0}, 239 { } 240 }; 241 MODULE_DEVICE_TABLE(pci, hbg_pci_tbl); 242 243 static struct pci_driver hbg_driver = { 244 .name = "hibmcge", 245 .id_table = hbg_pci_tbl, 246 .probe = hbg_probe, 247 }; 248 module_pci_driver(hbg_driver); 249 250 MODULE_LICENSE("GPL"); 251 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 252 MODULE_DESCRIPTION("hibmcge driver"); 253 MODULE_VERSION("1.0"); 254