1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2024 Hisilicon Limited. 3 4 #include <linux/interrupt.h> 5 #include "hbg_irq.h" 6 #include "hbg_hw.h" 7 8 static void hbg_irq_handle_err(struct hbg_priv *priv, 9 struct hbg_irq_info *irq_info) 10 { 11 if (irq_info->need_print) 12 dev_err(&priv->pdev->dev, 13 "receive error interrupt: %s\n", irq_info->name); 14 } 15 16 #define HBG_TXRX_IRQ_I(name, handle) \ 17 {#name, HBG_INT_MSK_##name##_B, false, false, 0, handle} 18 #define HBG_ERR_IRQ_I(name, need_print) \ 19 {#name, HBG_INT_MSK_##name##_B, true, need_print, 0, hbg_irq_handle_err} 20 21 static struct hbg_irq_info hbg_irqs[] = { 22 HBG_TXRX_IRQ_I(RX, NULL), 23 HBG_TXRX_IRQ_I(TX, NULL), 24 HBG_ERR_IRQ_I(MAC_MII_FIFO_ERR, true), 25 HBG_ERR_IRQ_I(MAC_PCS_RX_FIFO_ERR, true), 26 HBG_ERR_IRQ_I(MAC_PCS_TX_FIFO_ERR, true), 27 HBG_ERR_IRQ_I(MAC_APP_RX_FIFO_ERR, true), 28 HBG_ERR_IRQ_I(MAC_APP_TX_FIFO_ERR, true), 29 HBG_ERR_IRQ_I(SRAM_PARITY_ERR, true), 30 HBG_ERR_IRQ_I(TX_AHB_ERR, true), 31 HBG_ERR_IRQ_I(RX_BUF_AVL, false), 32 HBG_ERR_IRQ_I(REL_BUF_ERR, true), 33 HBG_ERR_IRQ_I(TXCFG_AVL, false), 34 HBG_ERR_IRQ_I(TX_DROP, false), 35 HBG_ERR_IRQ_I(RX_DROP, false), 36 HBG_ERR_IRQ_I(RX_AHB_ERR, true), 37 HBG_ERR_IRQ_I(MAC_FIFO_ERR, false), 38 HBG_ERR_IRQ_I(RBREQ_ERR, false), 39 HBG_ERR_IRQ_I(WE_ERR, false), 40 }; 41 42 static irqreturn_t hbg_irq_handle(int irq_num, void *p) 43 { 44 struct hbg_irq_info *info; 45 struct hbg_priv *priv = p; 46 u32 status; 47 u32 i; 48 49 status = hbg_hw_get_irq_status(priv); 50 for (i = 0; i < priv->vectors.info_array_len; i++) { 51 info = &priv->vectors.info_array[i]; 52 if (status & info->mask) { 53 if (!hbg_hw_irq_is_enabled(priv, info->mask)) 54 continue; 55 56 hbg_hw_irq_enable(priv, info->mask, false); 57 hbg_hw_irq_clear(priv, info->mask); 58 59 info->count++; 60 if (info->irq_handle) 61 info->irq_handle(priv, info); 62 63 if (info->re_enable) 64 hbg_hw_irq_enable(priv, info->mask, true); 65 } 66 } 67 68 return IRQ_HANDLED; 69 } 70 71 static const char *irq_names_map[HBG_VECTOR_NUM] = { "tx", "rx", 72 "err", "mdio" }; 73 74 int hbg_irq_init(struct hbg_priv *priv) 75 { 76 struct hbg_vector *vectors = &priv->vectors; 77 struct device *dev = &priv->pdev->dev; 78 int ret, id; 79 u32 i; 80 81 /* used pcim_enable_device(), so the vectors become device managed */ 82 ret = pci_alloc_irq_vectors(priv->pdev, HBG_VECTOR_NUM, HBG_VECTOR_NUM, 83 PCI_IRQ_MSI | PCI_IRQ_MSIX); 84 if (ret < 0) 85 return dev_err_probe(dev, ret, "failed to allocate vectors\n"); 86 87 if (ret != HBG_VECTOR_NUM) 88 return dev_err_probe(dev, -EINVAL, 89 "requested %u MSI, but allocated %d MSI\n", 90 HBG_VECTOR_NUM, ret); 91 92 /* mdio irq not requested, so the number of requested interrupts 93 * is HBG_VECTOR_NUM - 1. 94 */ 95 for (i = 0; i < HBG_VECTOR_NUM - 1; i++) { 96 id = pci_irq_vector(priv->pdev, i); 97 if (id < 0) 98 return dev_err_probe(dev, id, "failed to get irq id\n"); 99 100 snprintf(vectors->name[i], sizeof(vectors->name[i]), "%s-%s-%s", 101 dev_driver_string(dev), pci_name(priv->pdev), 102 irq_names_map[i]); 103 104 ret = devm_request_irq(dev, id, hbg_irq_handle, 0, 105 vectors->name[i], priv); 106 if (ret) 107 return dev_err_probe(dev, ret, 108 "failed to request irq: %s\n", 109 irq_names_map[i]); 110 } 111 112 vectors->info_array = hbg_irqs; 113 vectors->info_array_len = ARRAY_SIZE(hbg_irqs); 114 return 0; 115 } 116