1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2024 Hisilicon Limited. */ 3 4 #ifndef __HBG_COMMON_H 5 #define __HBG_COMMON_H 6 7 #include <linux/netdevice.h> 8 #include <linux/pci.h> 9 #include "hbg_reg.h" 10 11 #define HBG_STATUS_DISABLE 0x0 12 #define HBG_STATUS_ENABLE 0x1 13 #define HBG_RX_SKIP1 0x00 14 #define HBG_RX_SKIP2 0x01 15 #define HBG_VECTOR_NUM 4 16 #define HBG_PCU_CACHE_LINE_SIZE 32 17 #define HBG_TX_TIMEOUT_BUF_LEN 1024 18 #define HBG_RX_DESCR 0x01 19 20 #define HBG_PACKET_HEAD_SIZE ((HBG_RX_SKIP1 + HBG_RX_SKIP2 + \ 21 HBG_RX_DESCR) * HBG_PCU_CACHE_LINE_SIZE) 22 23 enum hbg_dir { 24 HBG_DIR_TX = 1 << 0, 25 HBG_DIR_RX = 1 << 1, 26 HBG_DIR_TX_RX = HBG_DIR_TX | HBG_DIR_RX, 27 }; 28 29 enum hbg_tx_state { 30 HBG_TX_STATE_COMPLETE = 0, /* clear state, must fix to 0 */ 31 HBG_TX_STATE_START, 32 }; 33 34 enum hbg_nic_state { 35 HBG_NIC_STATE_EVENT_HANDLING = 0, 36 }; 37 38 struct hbg_buffer { 39 u32 state; 40 dma_addr_t state_dma; 41 42 struct sk_buff *skb; 43 dma_addr_t skb_dma; 44 u32 skb_len; 45 46 enum hbg_dir dir; 47 struct hbg_ring *ring; 48 struct hbg_priv *priv; 49 }; 50 51 struct hbg_ring { 52 struct hbg_buffer *queue; 53 dma_addr_t queue_dma; 54 55 union { 56 u32 head; 57 u32 ntc; 58 }; 59 union { 60 u32 tail; 61 u32 ntu; 62 }; 63 u32 len; 64 65 enum hbg_dir dir; 66 struct hbg_priv *priv; 67 struct napi_struct napi; 68 char *tout_log_buf; /* tx timeout log buffer */ 69 }; 70 71 enum hbg_hw_event_type { 72 HBG_HW_EVENT_NONE = 0, 73 HBG_HW_EVENT_INIT, /* driver is loading */ 74 HBG_HW_EVENT_RESET, 75 }; 76 77 struct hbg_dev_specs { 78 u32 mac_id; 79 struct sockaddr mac_addr; 80 u32 phy_addr; 81 u32 mdio_frequency; 82 u32 rx_fifo_num; 83 u32 tx_fifo_num; 84 u32 vlan_layers; 85 u32 max_mtu; 86 u32 min_mtu; 87 88 u32 max_frame_len; 89 u32 rx_buf_size; 90 }; 91 92 struct hbg_irq_info { 93 const char *name; 94 u32 mask; 95 bool re_enable; 96 bool need_print; 97 u64 count; 98 99 void (*irq_handle)(struct hbg_priv *priv, struct hbg_irq_info *info); 100 }; 101 102 struct hbg_vector { 103 char name[HBG_VECTOR_NUM][32]; 104 struct hbg_irq_info *info_array; 105 u32 info_array_len; 106 }; 107 108 struct hbg_mac { 109 struct mii_bus *mdio_bus; 110 struct phy_device *phydev; 111 u8 phy_addr; 112 113 u32 speed; 114 u32 duplex; 115 u32 autoneg; 116 u32 link_status; 117 }; 118 119 struct hbg_priv { 120 struct net_device *netdev; 121 struct pci_dev *pdev; 122 u8 __iomem *io_base; 123 struct hbg_dev_specs dev_specs; 124 unsigned long state; 125 struct hbg_mac mac; 126 struct hbg_vector vectors; 127 struct hbg_ring tx_ring; 128 struct hbg_ring rx_ring; 129 }; 130 131 #endif 132