1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2024 Hisilicon Limited. */ 3 4 #ifndef __HBG_COMMON_H 5 #define __HBG_COMMON_H 6 7 #include <linux/ethtool.h> 8 #include <linux/netdevice.h> 9 #include <linux/pci.h> 10 #include "hbg_reg.h" 11 12 #define HBG_STATUS_DISABLE 0x0 13 #define HBG_STATUS_ENABLE 0x1 14 #define HBG_RX_SKIP1 0x00 15 #define HBG_RX_SKIP2 0x01 16 #define HBG_VECTOR_NUM 4 17 #define HBG_PCU_CACHE_LINE_SIZE 32 18 #define HBG_TX_TIMEOUT_BUF_LEN 1024 19 #define HBG_RX_DESCR 0x01 20 #define HBG_NO_PHY 0xFF 21 22 #define HBG_PACKET_HEAD_SIZE ((HBG_RX_SKIP1 + HBG_RX_SKIP2 + \ 23 HBG_RX_DESCR) * HBG_PCU_CACHE_LINE_SIZE) 24 25 enum hbg_dir { 26 HBG_DIR_TX = 1 << 0, 27 HBG_DIR_RX = 1 << 1, 28 HBG_DIR_TX_RX = HBG_DIR_TX | HBG_DIR_RX, 29 }; 30 31 enum hbg_tx_state { 32 HBG_TX_STATE_COMPLETE = 0, /* clear state, must fix to 0 */ 33 HBG_TX_STATE_START, 34 }; 35 36 enum hbg_nic_state { 37 HBG_NIC_STATE_EVENT_HANDLING = 0, 38 HBG_NIC_STATE_RESETTING, 39 HBG_NIC_STATE_RESET_FAIL, 40 HBG_NIC_STATE_NEED_RESET, /* trigger a reset in scheduled task */ 41 HBG_NIC_STATE_NP_LINK_FAIL, 42 }; 43 44 enum hbg_reset_type { 45 HBG_RESET_TYPE_NONE = 0, 46 HBG_RESET_TYPE_FLR, 47 HBG_RESET_TYPE_FUNCTION, 48 }; 49 50 struct hbg_buffer { 51 u32 state; 52 dma_addr_t state_dma; 53 54 struct sk_buff *skb; 55 dma_addr_t skb_dma; 56 u32 skb_len; 57 58 enum hbg_dir dir; 59 struct hbg_ring *ring; 60 struct hbg_priv *priv; 61 }; 62 63 struct hbg_ring { 64 struct hbg_buffer *queue; 65 dma_addr_t queue_dma; 66 67 union { 68 u32 head; 69 u32 ntc; 70 }; 71 union { 72 u32 tail; 73 u32 ntu; 74 }; 75 u32 len; 76 77 enum hbg_dir dir; 78 struct hbg_priv *priv; 79 struct napi_struct napi; 80 char *tout_log_buf; /* tx timeout log buffer */ 81 }; 82 83 enum hbg_hw_event_type { 84 HBG_HW_EVENT_NONE = 0, 85 HBG_HW_EVENT_INIT, /* driver is loading */ 86 HBG_HW_EVENT_RESET, 87 HBG_HW_EVENT_CORE_RESET, 88 }; 89 90 struct hbg_dev_specs { 91 u32 mac_id; 92 struct sockaddr mac_addr; 93 u32 phy_addr; 94 u32 mdio_frequency; 95 u32 rx_fifo_num; 96 u32 tx_fifo_num; 97 u32 vlan_layers; 98 u32 max_mtu; 99 u32 min_mtu; 100 u32 uc_mac_num; 101 102 u32 max_frame_len; 103 u32 rx_buf_size; 104 }; 105 106 struct hbg_irq_info { 107 const char *name; 108 u32 mask; 109 bool re_enable; 110 bool need_print; 111 bool need_reset; 112 113 void (*irq_handle)(struct hbg_priv *priv, 114 const struct hbg_irq_info *info); 115 }; 116 117 struct hbg_vector { 118 char name[HBG_VECTOR_NUM][32]; 119 120 u64 *stats_array; 121 const struct hbg_irq_info *info_array; 122 u32 info_array_len; 123 }; 124 125 struct hbg_mac { 126 struct mii_bus *mdio_bus; 127 struct phy_device *phydev; 128 u8 phy_addr; 129 130 u32 speed; 131 u32 duplex; 132 u32 autoneg; 133 u32 link_status; 134 u32 pause_autoneg; 135 }; 136 137 struct hbg_mac_table_entry { 138 u8 addr[ETH_ALEN]; 139 }; 140 141 struct hbg_mac_filter { 142 struct hbg_mac_table_entry *mac_table; 143 u32 table_max_len; 144 bool enabled; 145 }; 146 147 /* saved for restore after rest */ 148 struct hbg_user_def { 149 struct ethtool_pauseparam pause_param; 150 }; 151 152 struct hbg_stats { 153 u64 rx_desc_drop; 154 u64 rx_desc_l2_err_cnt; 155 u64 rx_desc_pkt_len_err_cnt; 156 u64 rx_desc_l3l4_err_cnt; 157 u64 rx_desc_l3_wrong_head_cnt; 158 u64 rx_desc_l3_csum_err_cnt; 159 u64 rx_desc_l3_len_err_cnt; 160 u64 rx_desc_l3_zero_ttl_cnt; 161 u64 rx_desc_l3_other_cnt; 162 u64 rx_desc_l4_err_cnt; 163 u64 rx_desc_l4_wrong_head_cnt; 164 u64 rx_desc_l4_len_err_cnt; 165 u64 rx_desc_l4_csum_err_cnt; 166 u64 rx_desc_l4_zero_port_num_cnt; 167 u64 rx_desc_l4_other_cnt; 168 u64 rx_desc_frag_cnt; 169 u64 rx_desc_ip_ver_err_cnt; 170 u64 rx_desc_ipv4_pkt_cnt; 171 u64 rx_desc_ipv6_pkt_cnt; 172 u64 rx_desc_no_ip_pkt_cnt; 173 u64 rx_desc_ip_pkt_cnt; 174 u64 rx_desc_tcp_pkt_cnt; 175 u64 rx_desc_udp_pkt_cnt; 176 u64 rx_desc_vlan_pkt_cnt; 177 u64 rx_desc_icmp_pkt_cnt; 178 u64 rx_desc_arp_pkt_cnt; 179 u64 rx_desc_rarp_pkt_cnt; 180 u64 rx_desc_multicast_pkt_cnt; 181 u64 rx_desc_broadcast_pkt_cnt; 182 u64 rx_desc_ipsec_pkt_cnt; 183 u64 rx_desc_ip_opt_pkt_cnt; 184 u64 rx_desc_key_not_match_cnt; 185 186 u64 rx_octets_total_ok_cnt; 187 u64 rx_uc_pkt_cnt; 188 u64 rx_mc_pkt_cnt; 189 u64 rx_bc_pkt_cnt; 190 u64 rx_vlan_pkt_cnt; 191 u64 rx_octets_bad_cnt; 192 u64 rx_octets_total_filt_cnt; 193 u64 rx_filt_pkt_cnt; 194 u64 rx_trans_pkt_cnt; 195 u64 rx_framesize_64; 196 u64 rx_framesize_65_127; 197 u64 rx_framesize_128_255; 198 u64 rx_framesize_256_511; 199 u64 rx_framesize_512_1023; 200 u64 rx_framesize_1024_1518; 201 u64 rx_framesize_bt_1518; 202 u64 rx_fcs_error_cnt; 203 u64 rx_data_error_cnt; 204 u64 rx_align_error_cnt; 205 u64 rx_pause_macctl_frame_cnt; 206 u64 rx_unknown_macctl_frame_cnt; 207 /* crc ok, > max_frm_size, < 2max_frm_size */ 208 u64 rx_frame_long_err_cnt; 209 /* crc fail, > max_frm_size, < 2max_frm_size */ 210 u64 rx_jabber_err_cnt; 211 /* > 2max_frm_size */ 212 u64 rx_frame_very_long_err_cnt; 213 /* < 64byte, >= short_runts_thr */ 214 u64 rx_frame_runt_err_cnt; 215 /* < short_runts_thr */ 216 u64 rx_frame_short_err_cnt; 217 /* PCU: dropped when the RX FIFO is full.*/ 218 u64 rx_overflow_cnt; 219 /* GMAC: the count of overflows of the RX FIFO */ 220 u64 rx_overrun_cnt; 221 /* PCU: the count of buffer alloc errors in RX */ 222 u64 rx_bufrq_err_cnt; 223 /* PCU: the count of write descriptor errors in RX */ 224 u64 rx_we_err_cnt; 225 /* GMAC: the count of pkts that contain PAD but length is not 64 */ 226 u64 rx_lengthfield_err_cnt; 227 u64 rx_fail_comma_cnt; 228 229 u64 rx_dma_err_cnt; 230 u64 rx_fifo_less_empty_thrsld_cnt; 231 232 u64 tx_octets_total_ok_cnt; 233 u64 tx_uc_pkt_cnt; 234 u64 tx_mc_pkt_cnt; 235 u64 tx_bc_pkt_cnt; 236 u64 tx_vlan_pkt_cnt; 237 u64 tx_octets_bad_cnt; 238 u64 tx_trans_pkt_cnt; 239 u64 tx_pause_frame_cnt; 240 u64 tx_framesize_64; 241 u64 tx_framesize_65_127; 242 u64 tx_framesize_128_255; 243 u64 tx_framesize_256_511; 244 u64 tx_framesize_512_1023; 245 u64 tx_framesize_1024_1518; 246 u64 tx_framesize_bt_1518; 247 /* GMAC: the count of times that frames fail to be transmitted 248 * due to internal errors. 249 */ 250 u64 tx_underrun_err_cnt; 251 u64 tx_add_cs_fail_cnt; 252 /* PCU: the count of buffer free errors in TX */ 253 u64 tx_bufrl_err_cnt; 254 u64 tx_crc_err_cnt; 255 u64 tx_drop_cnt; 256 u64 tx_excessive_length_drop_cnt; 257 258 u64 tx_timeout_cnt; 259 u64 tx_dma_err_cnt; 260 261 u64 np_link_fail_cnt; 262 u64 reset_fail_cnt; 263 }; 264 265 struct hbg_priv { 266 struct net_device *netdev; 267 struct pci_dev *pdev; 268 u8 __iomem *io_base; 269 struct hbg_dev_specs dev_specs; 270 unsigned long state; 271 struct hbg_mac mac; 272 struct hbg_vector vectors; 273 struct hbg_ring tx_ring; 274 struct hbg_ring rx_ring; 275 struct hbg_mac_filter filter; 276 enum hbg_reset_type reset_type; 277 struct hbg_user_def user_def; 278 struct hbg_stats stats; 279 unsigned long last_update_stats_time; 280 struct delayed_work service_task; 281 }; 282 283 void hbg_err_reset_task_schedule(struct hbg_priv *priv); 284 void hbg_np_link_fail_task_schedule(struct hbg_priv *priv); 285 286 #endif 287