1a95ac4f9SJijie Shao /* SPDX-License-Identifier: GPL-2.0+ */ 2a95ac4f9SJijie Shao /* Copyright (c) 2024 Hisilicon Limited. */ 3a95ac4f9SJijie Shao 4a95ac4f9SJijie Shao #ifndef __HBG_COMMON_H 5a95ac4f9SJijie Shao #define __HBG_COMMON_H 6a95ac4f9SJijie Shao 7a95ac4f9SJijie Shao #include <linux/netdevice.h> 8a95ac4f9SJijie Shao #include <linux/pci.h> 9a239b2b1SJijie Shao #include "hbg_reg.h" 10a239b2b1SJijie Shao 11a239b2b1SJijie Shao #define HBG_STATUS_DISABLE 0x0 12a239b2b1SJijie Shao #define HBG_STATUS_ENABLE 0x1 13a239b2b1SJijie Shao #define HBG_RX_SKIP1 0x00 14a239b2b1SJijie Shao #define HBG_RX_SKIP2 0x01 154d089035SJijie Shao #define HBG_VECTOR_NUM 4 16*40735e75SJijie Shao #define HBG_PCU_CACHE_LINE_SIZE 32 17*40735e75SJijie Shao #define HBG_TX_TIMEOUT_BUF_LEN 1024 18*40735e75SJijie Shao 19*40735e75SJijie Shao enum hbg_dir { 20*40735e75SJijie Shao HBG_DIR_TX = 1 << 0, 21*40735e75SJijie Shao HBG_DIR_RX = 1 << 1, 22*40735e75SJijie Shao HBG_DIR_TX_RX = HBG_DIR_TX | HBG_DIR_RX, 23*40735e75SJijie Shao }; 24*40735e75SJijie Shao 25*40735e75SJijie Shao enum hbg_tx_state { 26*40735e75SJijie Shao HBG_TX_STATE_COMPLETE = 0, /* clear state, must fix to 0 */ 27*40735e75SJijie Shao HBG_TX_STATE_START, 28*40735e75SJijie Shao }; 29a95ac4f9SJijie Shao 30fc1992baSJijie Shao enum hbg_nic_state { 31fc1992baSJijie Shao HBG_NIC_STATE_EVENT_HANDLING = 0, 32fc1992baSJijie Shao }; 33fc1992baSJijie Shao 34*40735e75SJijie Shao struct hbg_buffer { 35*40735e75SJijie Shao u32 state; 36*40735e75SJijie Shao dma_addr_t state_dma; 37*40735e75SJijie Shao 38*40735e75SJijie Shao struct sk_buff *skb; 39*40735e75SJijie Shao dma_addr_t skb_dma; 40*40735e75SJijie Shao u32 skb_len; 41*40735e75SJijie Shao 42*40735e75SJijie Shao enum hbg_dir dir; 43*40735e75SJijie Shao struct hbg_ring *ring; 44*40735e75SJijie Shao struct hbg_priv *priv; 45*40735e75SJijie Shao }; 46*40735e75SJijie Shao 47*40735e75SJijie Shao struct hbg_ring { 48*40735e75SJijie Shao struct hbg_buffer *queue; 49*40735e75SJijie Shao dma_addr_t queue_dma; 50*40735e75SJijie Shao 51*40735e75SJijie Shao union { 52*40735e75SJijie Shao u32 head; 53*40735e75SJijie Shao u32 ntc; 54*40735e75SJijie Shao }; 55*40735e75SJijie Shao union { 56*40735e75SJijie Shao u32 tail; 57*40735e75SJijie Shao u32 ntu; 58*40735e75SJijie Shao }; 59*40735e75SJijie Shao u32 len; 60*40735e75SJijie Shao 61*40735e75SJijie Shao enum hbg_dir dir; 62*40735e75SJijie Shao struct hbg_priv *priv; 63*40735e75SJijie Shao struct napi_struct napi; 64*40735e75SJijie Shao char *tout_log_buf; /* tx timeout log buffer */ 65*40735e75SJijie Shao }; 66*40735e75SJijie Shao 67fc1992baSJijie Shao enum hbg_hw_event_type { 68fc1992baSJijie Shao HBG_HW_EVENT_NONE = 0, 69fc1992baSJijie Shao HBG_HW_EVENT_INIT, /* driver is loading */ 70*40735e75SJijie Shao HBG_HW_EVENT_RESET, 71fc1992baSJijie Shao }; 72fc1992baSJijie Shao 73fc1992baSJijie Shao struct hbg_dev_specs { 74fc1992baSJijie Shao u32 mac_id; 75fc1992baSJijie Shao struct sockaddr mac_addr; 76fc1992baSJijie Shao u32 phy_addr; 77fc1992baSJijie Shao u32 mdio_frequency; 78fc1992baSJijie Shao u32 rx_fifo_num; 79fc1992baSJijie Shao u32 tx_fifo_num; 80fc1992baSJijie Shao u32 vlan_layers; 81fc1992baSJijie Shao u32 max_mtu; 82fc1992baSJijie Shao u32 min_mtu; 83fc1992baSJijie Shao 84fc1992baSJijie Shao u32 max_frame_len; 85fc1992baSJijie Shao u32 rx_buf_size; 86fc1992baSJijie Shao }; 87fc1992baSJijie Shao 884d089035SJijie Shao struct hbg_irq_info { 894d089035SJijie Shao const char *name; 904d089035SJijie Shao u32 mask; 914d089035SJijie Shao bool re_enable; 924d089035SJijie Shao bool need_print; 934d089035SJijie Shao u64 count; 944d089035SJijie Shao 954d089035SJijie Shao void (*irq_handle)(struct hbg_priv *priv, struct hbg_irq_info *info); 964d089035SJijie Shao }; 974d089035SJijie Shao 984d089035SJijie Shao struct hbg_vector { 994d089035SJijie Shao char name[HBG_VECTOR_NUM][32]; 1004d089035SJijie Shao struct hbg_irq_info *info_array; 1014d089035SJijie Shao u32 info_array_len; 1024d089035SJijie Shao }; 1034d089035SJijie Shao 104a239b2b1SJijie Shao struct hbg_mac { 105a239b2b1SJijie Shao struct mii_bus *mdio_bus; 106a239b2b1SJijie Shao struct phy_device *phydev; 107a239b2b1SJijie Shao u8 phy_addr; 108a239b2b1SJijie Shao 109a239b2b1SJijie Shao u32 speed; 110a239b2b1SJijie Shao u32 duplex; 111a239b2b1SJijie Shao u32 autoneg; 112a239b2b1SJijie Shao u32 link_status; 113a239b2b1SJijie Shao }; 114a239b2b1SJijie Shao 115a95ac4f9SJijie Shao struct hbg_priv { 116a95ac4f9SJijie Shao struct net_device *netdev; 117a95ac4f9SJijie Shao struct pci_dev *pdev; 118a95ac4f9SJijie Shao u8 __iomem *io_base; 119fc1992baSJijie Shao struct hbg_dev_specs dev_specs; 120fc1992baSJijie Shao unsigned long state; 121a239b2b1SJijie Shao struct hbg_mac mac; 1224d089035SJijie Shao struct hbg_vector vectors; 123*40735e75SJijie Shao struct hbg_ring tx_ring; 124a95ac4f9SJijie Shao }; 125a95ac4f9SJijie Shao 126a95ac4f9SJijie Shao #endif 127