1a95ac4f9SJijie Shao /* SPDX-License-Identifier: GPL-2.0+ */ 2a95ac4f9SJijie Shao /* Copyright (c) 2024 Hisilicon Limited. */ 3a95ac4f9SJijie Shao 4a95ac4f9SJijie Shao #ifndef __HBG_COMMON_H 5a95ac4f9SJijie Shao #define __HBG_COMMON_H 6a95ac4f9SJijie Shao 7a95ac4f9SJijie Shao #include <linux/netdevice.h> 8a95ac4f9SJijie Shao #include <linux/pci.h> 9a239b2b1SJijie Shao #include "hbg_reg.h" 10a239b2b1SJijie Shao 11a239b2b1SJijie Shao #define HBG_STATUS_DISABLE 0x0 12a239b2b1SJijie Shao #define HBG_STATUS_ENABLE 0x1 13a239b2b1SJijie Shao #define HBG_RX_SKIP1 0x00 14a239b2b1SJijie Shao #define HBG_RX_SKIP2 0x01 154d089035SJijie Shao #define HBG_VECTOR_NUM 4 1640735e75SJijie Shao #define HBG_PCU_CACHE_LINE_SIZE 32 1740735e75SJijie Shao #define HBG_TX_TIMEOUT_BUF_LEN 1024 18*f72e2559SJijie Shao #define HBG_RX_DESCR 0x01 19*f72e2559SJijie Shao 20*f72e2559SJijie Shao #define HBG_PACKET_HEAD_SIZE ((HBG_RX_SKIP1 + HBG_RX_SKIP2 + \ 21*f72e2559SJijie Shao HBG_RX_DESCR) * HBG_PCU_CACHE_LINE_SIZE) 2240735e75SJijie Shao 2340735e75SJijie Shao enum hbg_dir { 2440735e75SJijie Shao HBG_DIR_TX = 1 << 0, 2540735e75SJijie Shao HBG_DIR_RX = 1 << 1, 2640735e75SJijie Shao HBG_DIR_TX_RX = HBG_DIR_TX | HBG_DIR_RX, 2740735e75SJijie Shao }; 2840735e75SJijie Shao 2940735e75SJijie Shao enum hbg_tx_state { 3040735e75SJijie Shao HBG_TX_STATE_COMPLETE = 0, /* clear state, must fix to 0 */ 3140735e75SJijie Shao HBG_TX_STATE_START, 3240735e75SJijie Shao }; 33a95ac4f9SJijie Shao 34fc1992baSJijie Shao enum hbg_nic_state { 35fc1992baSJijie Shao HBG_NIC_STATE_EVENT_HANDLING = 0, 36fc1992baSJijie Shao }; 37fc1992baSJijie Shao 3840735e75SJijie Shao struct hbg_buffer { 3940735e75SJijie Shao u32 state; 4040735e75SJijie Shao dma_addr_t state_dma; 4140735e75SJijie Shao 4240735e75SJijie Shao struct sk_buff *skb; 4340735e75SJijie Shao dma_addr_t skb_dma; 4440735e75SJijie Shao u32 skb_len; 4540735e75SJijie Shao 4640735e75SJijie Shao enum hbg_dir dir; 4740735e75SJijie Shao struct hbg_ring *ring; 4840735e75SJijie Shao struct hbg_priv *priv; 4940735e75SJijie Shao }; 5040735e75SJijie Shao 5140735e75SJijie Shao struct hbg_ring { 5240735e75SJijie Shao struct hbg_buffer *queue; 5340735e75SJijie Shao dma_addr_t queue_dma; 5440735e75SJijie Shao 5540735e75SJijie Shao union { 5640735e75SJijie Shao u32 head; 5740735e75SJijie Shao u32 ntc; 5840735e75SJijie Shao }; 5940735e75SJijie Shao union { 6040735e75SJijie Shao u32 tail; 6140735e75SJijie Shao u32 ntu; 6240735e75SJijie Shao }; 6340735e75SJijie Shao u32 len; 6440735e75SJijie Shao 6540735e75SJijie Shao enum hbg_dir dir; 6640735e75SJijie Shao struct hbg_priv *priv; 6740735e75SJijie Shao struct napi_struct napi; 6840735e75SJijie Shao char *tout_log_buf; /* tx timeout log buffer */ 6940735e75SJijie Shao }; 7040735e75SJijie Shao 71fc1992baSJijie Shao enum hbg_hw_event_type { 72fc1992baSJijie Shao HBG_HW_EVENT_NONE = 0, 73fc1992baSJijie Shao HBG_HW_EVENT_INIT, /* driver is loading */ 7440735e75SJijie Shao HBG_HW_EVENT_RESET, 75fc1992baSJijie Shao }; 76fc1992baSJijie Shao 77fc1992baSJijie Shao struct hbg_dev_specs { 78fc1992baSJijie Shao u32 mac_id; 79fc1992baSJijie Shao struct sockaddr mac_addr; 80fc1992baSJijie Shao u32 phy_addr; 81fc1992baSJijie Shao u32 mdio_frequency; 82fc1992baSJijie Shao u32 rx_fifo_num; 83fc1992baSJijie Shao u32 tx_fifo_num; 84fc1992baSJijie Shao u32 vlan_layers; 85fc1992baSJijie Shao u32 max_mtu; 86fc1992baSJijie Shao u32 min_mtu; 87fc1992baSJijie Shao 88fc1992baSJijie Shao u32 max_frame_len; 89fc1992baSJijie Shao u32 rx_buf_size; 90fc1992baSJijie Shao }; 91fc1992baSJijie Shao 924d089035SJijie Shao struct hbg_irq_info { 934d089035SJijie Shao const char *name; 944d089035SJijie Shao u32 mask; 954d089035SJijie Shao bool re_enable; 964d089035SJijie Shao bool need_print; 974d089035SJijie Shao u64 count; 984d089035SJijie Shao 994d089035SJijie Shao void (*irq_handle)(struct hbg_priv *priv, struct hbg_irq_info *info); 1004d089035SJijie Shao }; 1014d089035SJijie Shao 1024d089035SJijie Shao struct hbg_vector { 1034d089035SJijie Shao char name[HBG_VECTOR_NUM][32]; 1044d089035SJijie Shao struct hbg_irq_info *info_array; 1054d089035SJijie Shao u32 info_array_len; 1064d089035SJijie Shao }; 1074d089035SJijie Shao 108a239b2b1SJijie Shao struct hbg_mac { 109a239b2b1SJijie Shao struct mii_bus *mdio_bus; 110a239b2b1SJijie Shao struct phy_device *phydev; 111a239b2b1SJijie Shao u8 phy_addr; 112a239b2b1SJijie Shao 113a239b2b1SJijie Shao u32 speed; 114a239b2b1SJijie Shao u32 duplex; 115a239b2b1SJijie Shao u32 autoneg; 116a239b2b1SJijie Shao u32 link_status; 117a239b2b1SJijie Shao }; 118a239b2b1SJijie Shao 119a95ac4f9SJijie Shao struct hbg_priv { 120a95ac4f9SJijie Shao struct net_device *netdev; 121a95ac4f9SJijie Shao struct pci_dev *pdev; 122a95ac4f9SJijie Shao u8 __iomem *io_base; 123fc1992baSJijie Shao struct hbg_dev_specs dev_specs; 124fc1992baSJijie Shao unsigned long state; 125a239b2b1SJijie Shao struct hbg_mac mac; 1264d089035SJijie Shao struct hbg_vector vectors; 12740735e75SJijie Shao struct hbg_ring tx_ring; 128*f72e2559SJijie Shao struct hbg_ring rx_ring; 129a95ac4f9SJijie Shao }; 130a95ac4f9SJijie Shao 131a95ac4f9SJijie Shao #endif 132