1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 * Google virtual Ethernet (gve) driver 3 * 4 * Copyright (C) 2015-2021 Google, Inc. 5 */ 6 7 #ifndef _GVE_DQO_H_ 8 #define _GVE_DQO_H_ 9 10 #include "gve_adminq.h" 11 12 #define GVE_ITR_ENABLE_BIT_DQO BIT(0) 13 #define GVE_ITR_CLEAR_PBA_BIT_DQO BIT(1) 14 #define GVE_ITR_NO_UPDATE_DQO (3 << 3) 15 16 #define GVE_ITR_INTERVAL_DQO_SHIFT 5 17 #define GVE_ITR_INTERVAL_DQO_MASK ((1 << 12) - 1) 18 19 #define GVE_TX_IRQ_RATELIMIT_US_DQO 50 20 #define GVE_RX_IRQ_RATELIMIT_US_DQO 20 21 #define GVE_MAX_ITR_INTERVAL_DQO (GVE_ITR_INTERVAL_DQO_MASK * 2) 22 23 /* Timeout in seconds to wait for a reinjection completion after receiving 24 * its corresponding miss completion. 25 */ 26 #define GVE_REINJECT_COMPL_TIMEOUT 1 27 28 /* Timeout in seconds to deallocate the completion tag for a packet that was 29 * prematurely freed for not receiving a valid completion. This should be large 30 * enough to rule out the possibility of receiving the corresponding valid 31 * completion after this interval. 32 */ 33 #define GVE_DEALLOCATE_COMPL_TIMEOUT 60 34 35 netdev_tx_t gve_tx_dqo(struct sk_buff *skb, struct net_device *dev); 36 netdev_features_t gve_features_check_dqo(struct sk_buff *skb, 37 struct net_device *dev, 38 netdev_features_t features); 39 bool gve_tx_poll_dqo(struct gve_notify_block *block, bool do_clean); 40 int gve_rx_poll_dqo(struct gve_notify_block *block, int budget); 41 int gve_tx_alloc_rings_dqo(struct gve_priv *priv); 42 void gve_tx_free_rings_dqo(struct gve_priv *priv); 43 int gve_rx_alloc_rings_dqo(struct gve_priv *priv); 44 void gve_rx_free_rings_dqo(struct gve_priv *priv); 45 int gve_clean_tx_done_dqo(struct gve_priv *priv, struct gve_tx_ring *tx, 46 struct napi_struct *napi); 47 void gve_rx_post_buffers_dqo(struct gve_rx_ring *rx); 48 void gve_rx_write_doorbell_dqo(const struct gve_priv *priv, int queue_idx); 49 50 static inline void 51 gve_tx_put_doorbell_dqo(const struct gve_priv *priv, 52 const struct gve_queue_resources *q_resources, u32 val) 53 { 54 u64 index; 55 56 index = be32_to_cpu(q_resources->db_index); 57 iowrite32(val, &priv->db_bar2[index]); 58 } 59 60 /* Builds register value to write to DQO IRQ doorbell to enable with specified 61 * ITR interval. 62 */ 63 static inline u32 gve_setup_itr_interval_dqo(u32 interval_us) 64 { 65 u32 result = GVE_ITR_ENABLE_BIT_DQO; 66 67 /* Interval has 2us granularity. */ 68 interval_us >>= 1; 69 70 interval_us &= GVE_ITR_INTERVAL_DQO_MASK; 71 result |= (interval_us << GVE_ITR_INTERVAL_DQO_SHIFT); 72 73 return result; 74 } 75 76 static inline void 77 gve_write_irq_doorbell_dqo(const struct gve_priv *priv, 78 const struct gve_notify_block *block, u32 val) 79 { 80 u32 index = be32_to_cpu(*block->irq_db_index); 81 82 iowrite32(val, &priv->db_bar2[index]); 83 } 84 85 /* Sets interrupt throttling interval and enables interrupt 86 * by writing to IRQ doorbell. 87 */ 88 static inline void 89 gve_set_itr_coalesce_usecs_dqo(struct gve_priv *priv, 90 struct gve_notify_block *block, 91 u32 usecs) 92 { 93 gve_write_irq_doorbell_dqo(priv, block, 94 gve_setup_itr_interval_dqo(usecs)); 95 } 96 #endif /* _GVE_DQO_H_ */ 97