1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 * Google virtual Ethernet (gve) driver 3 * 4 * Copyright (C) 2015-2021 Google, Inc. 5 */ 6 7 #ifndef _GVE_ADMINQ_H 8 #define _GVE_ADMINQ_H 9 10 #include <linux/build_bug.h> 11 12 /* Admin queue opcodes */ 13 enum gve_adminq_opcodes { 14 GVE_ADMINQ_DESCRIBE_DEVICE = 0x1, 15 GVE_ADMINQ_CONFIGURE_DEVICE_RESOURCES = 0x2, 16 GVE_ADMINQ_REGISTER_PAGE_LIST = 0x3, 17 GVE_ADMINQ_UNREGISTER_PAGE_LIST = 0x4, 18 GVE_ADMINQ_CREATE_TX_QUEUE = 0x5, 19 GVE_ADMINQ_CREATE_RX_QUEUE = 0x6, 20 GVE_ADMINQ_DESTROY_TX_QUEUE = 0x7, 21 GVE_ADMINQ_DESTROY_RX_QUEUE = 0x8, 22 GVE_ADMINQ_DECONFIGURE_DEVICE_RESOURCES = 0x9, 23 GVE_ADMINQ_SET_DRIVER_PARAMETER = 0xB, 24 GVE_ADMINQ_REPORT_STATS = 0xC, 25 GVE_ADMINQ_REPORT_LINK_SPEED = 0xD, 26 GVE_ADMINQ_GET_PTYPE_MAP = 0xE, 27 GVE_ADMINQ_VERIFY_DRIVER_COMPATIBILITY = 0xF, 28 }; 29 30 /* Admin queue status codes */ 31 enum gve_adminq_statuses { 32 GVE_ADMINQ_COMMAND_UNSET = 0x0, 33 GVE_ADMINQ_COMMAND_PASSED = 0x1, 34 GVE_ADMINQ_COMMAND_ERROR_ABORTED = 0xFFFFFFF0, 35 GVE_ADMINQ_COMMAND_ERROR_ALREADY_EXISTS = 0xFFFFFFF1, 36 GVE_ADMINQ_COMMAND_ERROR_CANCELLED = 0xFFFFFFF2, 37 GVE_ADMINQ_COMMAND_ERROR_DATALOSS = 0xFFFFFFF3, 38 GVE_ADMINQ_COMMAND_ERROR_DEADLINE_EXCEEDED = 0xFFFFFFF4, 39 GVE_ADMINQ_COMMAND_ERROR_FAILED_PRECONDITION = 0xFFFFFFF5, 40 GVE_ADMINQ_COMMAND_ERROR_INTERNAL_ERROR = 0xFFFFFFF6, 41 GVE_ADMINQ_COMMAND_ERROR_INVALID_ARGUMENT = 0xFFFFFFF7, 42 GVE_ADMINQ_COMMAND_ERROR_NOT_FOUND = 0xFFFFFFF8, 43 GVE_ADMINQ_COMMAND_ERROR_OUT_OF_RANGE = 0xFFFFFFF9, 44 GVE_ADMINQ_COMMAND_ERROR_PERMISSION_DENIED = 0xFFFFFFFA, 45 GVE_ADMINQ_COMMAND_ERROR_UNAUTHENTICATED = 0xFFFFFFFB, 46 GVE_ADMINQ_COMMAND_ERROR_RESOURCE_EXHAUSTED = 0xFFFFFFFC, 47 GVE_ADMINQ_COMMAND_ERROR_UNAVAILABLE = 0xFFFFFFFD, 48 GVE_ADMINQ_COMMAND_ERROR_UNIMPLEMENTED = 0xFFFFFFFE, 49 GVE_ADMINQ_COMMAND_ERROR_UNKNOWN_ERROR = 0xFFFFFFFF, 50 }; 51 52 #define GVE_ADMINQ_DEVICE_DESCRIPTOR_VERSION 1 53 54 /* All AdminQ command structs should be naturally packed. The static_assert 55 * calls make sure this is the case at compile time. 56 */ 57 58 struct gve_adminq_describe_device { 59 __be64 device_descriptor_addr; 60 __be32 device_descriptor_version; 61 __be32 available_length; 62 }; 63 64 static_assert(sizeof(struct gve_adminq_describe_device) == 16); 65 66 struct gve_device_descriptor { 67 __be64 max_registered_pages; 68 __be16 reserved1; 69 __be16 tx_queue_entries; 70 __be16 rx_queue_entries; 71 __be16 default_num_queues; 72 __be16 mtu; 73 __be16 counters; 74 __be16 tx_pages_per_qpl; 75 __be16 rx_pages_per_qpl; 76 u8 mac[ETH_ALEN]; 77 __be16 num_device_options; 78 __be16 total_length; 79 u8 reserved2[6]; 80 }; 81 82 static_assert(sizeof(struct gve_device_descriptor) == 40); 83 84 struct gve_device_option { 85 __be16 option_id; 86 __be16 option_length; 87 __be32 required_features_mask; 88 }; 89 90 static_assert(sizeof(struct gve_device_option) == 8); 91 92 struct gve_device_option_gqi_rda { 93 __be32 supported_features_mask; 94 }; 95 96 static_assert(sizeof(struct gve_device_option_gqi_rda) == 4); 97 98 struct gve_device_option_gqi_qpl { 99 __be32 supported_features_mask; 100 }; 101 102 static_assert(sizeof(struct gve_device_option_gqi_qpl) == 4); 103 104 struct gve_device_option_dqo_rda { 105 __be32 supported_features_mask; 106 __be16 tx_comp_ring_entries; 107 __be16 rx_buff_ring_entries; 108 }; 109 110 static_assert(sizeof(struct gve_device_option_dqo_rda) == 8); 111 112 struct gve_device_option_dqo_qpl { 113 __be32 supported_features_mask; 114 __be16 tx_pages_per_qpl; 115 __be16 rx_pages_per_qpl; 116 }; 117 118 static_assert(sizeof(struct gve_device_option_dqo_qpl) == 8); 119 120 struct gve_device_option_jumbo_frames { 121 __be32 supported_features_mask; 122 __be16 max_mtu; 123 u8 padding[2]; 124 }; 125 126 static_assert(sizeof(struct gve_device_option_jumbo_frames) == 8); 127 128 /* Terminology: 129 * 130 * RDA - Raw DMA Addressing - Buffers associated with SKBs are directly DMA 131 * mapped and read/updated by the device. 132 * 133 * QPL - Queue Page Lists - Driver uses bounce buffers which are DMA mapped with 134 * the device for read/write and data is copied from/to SKBs. 135 */ 136 enum gve_dev_opt_id { 137 GVE_DEV_OPT_ID_GQI_RAW_ADDRESSING = 0x1, 138 GVE_DEV_OPT_ID_GQI_RDA = 0x2, 139 GVE_DEV_OPT_ID_GQI_QPL = 0x3, 140 GVE_DEV_OPT_ID_DQO_RDA = 0x4, 141 GVE_DEV_OPT_ID_DQO_QPL = 0x7, 142 GVE_DEV_OPT_ID_JUMBO_FRAMES = 0x8, 143 }; 144 145 enum gve_dev_opt_req_feat_mask { 146 GVE_DEV_OPT_REQ_FEAT_MASK_GQI_RAW_ADDRESSING = 0x0, 147 GVE_DEV_OPT_REQ_FEAT_MASK_GQI_RDA = 0x0, 148 GVE_DEV_OPT_REQ_FEAT_MASK_GQI_QPL = 0x0, 149 GVE_DEV_OPT_REQ_FEAT_MASK_DQO_RDA = 0x0, 150 GVE_DEV_OPT_REQ_FEAT_MASK_JUMBO_FRAMES = 0x0, 151 GVE_DEV_OPT_REQ_FEAT_MASK_DQO_QPL = 0x0, 152 }; 153 154 enum gve_sup_feature_mask { 155 GVE_SUP_JUMBO_FRAMES_MASK = 1 << 2, 156 }; 157 158 #define GVE_DEV_OPT_LEN_GQI_RAW_ADDRESSING 0x0 159 160 #define GVE_VERSION_STR_LEN 128 161 162 enum gve_driver_capbility { 163 gve_driver_capability_gqi_qpl = 0, 164 gve_driver_capability_gqi_rda = 1, 165 gve_driver_capability_dqo_qpl = 2, /* reserved for future use */ 166 gve_driver_capability_dqo_rda = 3, 167 gve_driver_capability_alt_miss_compl = 4, 168 }; 169 170 #define GVE_CAP1(a) BIT((int)a) 171 #define GVE_CAP2(a) BIT(((int)a) - 64) 172 #define GVE_CAP3(a) BIT(((int)a) - 128) 173 #define GVE_CAP4(a) BIT(((int)a) - 192) 174 175 #define GVE_DRIVER_CAPABILITY_FLAGS1 \ 176 (GVE_CAP1(gve_driver_capability_gqi_qpl) | \ 177 GVE_CAP1(gve_driver_capability_gqi_rda) | \ 178 GVE_CAP1(gve_driver_capability_dqo_rda) | \ 179 GVE_CAP1(gve_driver_capability_alt_miss_compl)) 180 181 #define GVE_DRIVER_CAPABILITY_FLAGS2 0x0 182 #define GVE_DRIVER_CAPABILITY_FLAGS3 0x0 183 #define GVE_DRIVER_CAPABILITY_FLAGS4 0x0 184 185 struct gve_driver_info { 186 u8 os_type; /* 0x01 = Linux */ 187 u8 driver_major; 188 u8 driver_minor; 189 u8 driver_sub; 190 __be32 os_version_major; 191 __be32 os_version_minor; 192 __be32 os_version_sub; 193 __be64 driver_capability_flags[4]; 194 u8 os_version_str1[GVE_VERSION_STR_LEN]; 195 u8 os_version_str2[GVE_VERSION_STR_LEN]; 196 }; 197 198 struct gve_adminq_verify_driver_compatibility { 199 __be64 driver_info_len; 200 __be64 driver_info_addr; 201 }; 202 203 static_assert(sizeof(struct gve_adminq_verify_driver_compatibility) == 16); 204 205 struct gve_adminq_configure_device_resources { 206 __be64 counter_array; 207 __be64 irq_db_addr; 208 __be32 num_counters; 209 __be32 num_irq_dbs; 210 __be32 irq_db_stride; 211 __be32 ntfy_blk_msix_base_idx; 212 u8 queue_format; 213 u8 padding[7]; 214 }; 215 216 static_assert(sizeof(struct gve_adminq_configure_device_resources) == 40); 217 218 struct gve_adminq_register_page_list { 219 __be32 page_list_id; 220 __be32 num_pages; 221 __be64 page_address_list_addr; 222 __be64 page_size; 223 }; 224 225 static_assert(sizeof(struct gve_adminq_register_page_list) == 24); 226 227 struct gve_adminq_unregister_page_list { 228 __be32 page_list_id; 229 }; 230 231 static_assert(sizeof(struct gve_adminq_unregister_page_list) == 4); 232 233 #define GVE_RAW_ADDRESSING_QPL_ID 0xFFFFFFFF 234 235 struct gve_adminq_create_tx_queue { 236 __be32 queue_id; 237 __be32 reserved; 238 __be64 queue_resources_addr; 239 __be64 tx_ring_addr; 240 __be32 queue_page_list_id; 241 __be32 ntfy_id; 242 __be64 tx_comp_ring_addr; 243 __be16 tx_ring_size; 244 __be16 tx_comp_ring_size; 245 u8 padding[4]; 246 }; 247 248 static_assert(sizeof(struct gve_adminq_create_tx_queue) == 48); 249 250 struct gve_adminq_create_rx_queue { 251 __be32 queue_id; 252 __be32 index; 253 __be32 reserved; 254 __be32 ntfy_id; 255 __be64 queue_resources_addr; 256 __be64 rx_desc_ring_addr; 257 __be64 rx_data_ring_addr; 258 __be32 queue_page_list_id; 259 __be16 rx_ring_size; 260 __be16 packet_buffer_size; 261 __be16 rx_buff_ring_size; 262 u8 enable_rsc; 263 u8 padding[5]; 264 }; 265 266 static_assert(sizeof(struct gve_adminq_create_rx_queue) == 56); 267 268 /* Queue resources that are shared with the device */ 269 struct gve_queue_resources { 270 union { 271 struct { 272 __be32 db_index; /* Device -> Guest */ 273 __be32 counter_index; /* Device -> Guest */ 274 }; 275 u8 reserved[64]; 276 }; 277 }; 278 279 static_assert(sizeof(struct gve_queue_resources) == 64); 280 281 struct gve_adminq_destroy_tx_queue { 282 __be32 queue_id; 283 }; 284 285 static_assert(sizeof(struct gve_adminq_destroy_tx_queue) == 4); 286 287 struct gve_adminq_destroy_rx_queue { 288 __be32 queue_id; 289 }; 290 291 static_assert(sizeof(struct gve_adminq_destroy_rx_queue) == 4); 292 293 /* GVE Set Driver Parameter Types */ 294 enum gve_set_driver_param_types { 295 GVE_SET_PARAM_MTU = 0x1, 296 }; 297 298 struct gve_adminq_set_driver_parameter { 299 __be32 parameter_type; 300 u8 reserved[4]; 301 __be64 parameter_value; 302 }; 303 304 static_assert(sizeof(struct gve_adminq_set_driver_parameter) == 16); 305 306 struct gve_adminq_report_stats { 307 __be64 stats_report_len; 308 __be64 stats_report_addr; 309 __be64 interval; 310 }; 311 312 static_assert(sizeof(struct gve_adminq_report_stats) == 24); 313 314 struct gve_adminq_report_link_speed { 315 __be64 link_speed_address; 316 }; 317 318 static_assert(sizeof(struct gve_adminq_report_link_speed) == 8); 319 320 struct stats { 321 __be32 stat_name; 322 __be32 queue_id; 323 __be64 value; 324 }; 325 326 static_assert(sizeof(struct stats) == 16); 327 328 struct gve_stats_report { 329 __be64 written_count; 330 struct stats stats[]; 331 }; 332 333 static_assert(sizeof(struct gve_stats_report) == 8); 334 335 enum gve_stat_names { 336 // stats from gve 337 TX_WAKE_CNT = 1, 338 TX_STOP_CNT = 2, 339 TX_FRAMES_SENT = 3, 340 TX_BYTES_SENT = 4, 341 TX_LAST_COMPLETION_PROCESSED = 5, 342 RX_NEXT_EXPECTED_SEQUENCE = 6, 343 RX_BUFFERS_POSTED = 7, 344 TX_TIMEOUT_CNT = 8, 345 // stats from NIC 346 RX_QUEUE_DROP_CNT = 65, 347 RX_NO_BUFFERS_POSTED = 66, 348 RX_DROPS_PACKET_OVER_MRU = 67, 349 RX_DROPS_INVALID_CHECKSUM = 68, 350 }; 351 352 enum gve_l3_type { 353 /* Must be zero so zero initialized LUT is unknown. */ 354 GVE_L3_TYPE_UNKNOWN = 0, 355 GVE_L3_TYPE_OTHER, 356 GVE_L3_TYPE_IPV4, 357 GVE_L3_TYPE_IPV6, 358 }; 359 360 enum gve_l4_type { 361 /* Must be zero so zero initialized LUT is unknown. */ 362 GVE_L4_TYPE_UNKNOWN = 0, 363 GVE_L4_TYPE_OTHER, 364 GVE_L4_TYPE_TCP, 365 GVE_L4_TYPE_UDP, 366 GVE_L4_TYPE_ICMP, 367 GVE_L4_TYPE_SCTP, 368 }; 369 370 /* These are control path types for PTYPE which are the same as the data path 371 * types. 372 */ 373 struct gve_ptype_entry { 374 u8 l3_type; 375 u8 l4_type; 376 }; 377 378 struct gve_ptype_map { 379 struct gve_ptype_entry ptypes[1 << 10]; /* PTYPES are always 10 bits. */ 380 }; 381 382 struct gve_adminq_get_ptype_map { 383 __be64 ptype_map_len; 384 __be64 ptype_map_addr; 385 }; 386 387 union gve_adminq_command { 388 struct { 389 __be32 opcode; 390 __be32 status; 391 union { 392 struct gve_adminq_configure_device_resources 393 configure_device_resources; 394 struct gve_adminq_create_tx_queue create_tx_queue; 395 struct gve_adminq_create_rx_queue create_rx_queue; 396 struct gve_adminq_destroy_tx_queue destroy_tx_queue; 397 struct gve_adminq_destroy_rx_queue destroy_rx_queue; 398 struct gve_adminq_describe_device describe_device; 399 struct gve_adminq_register_page_list reg_page_list; 400 struct gve_adminq_unregister_page_list unreg_page_list; 401 struct gve_adminq_set_driver_parameter set_driver_param; 402 struct gve_adminq_report_stats report_stats; 403 struct gve_adminq_report_link_speed report_link_speed; 404 struct gve_adminq_get_ptype_map get_ptype_map; 405 struct gve_adminq_verify_driver_compatibility 406 verify_driver_compatibility; 407 }; 408 }; 409 u8 reserved[64]; 410 }; 411 412 static_assert(sizeof(union gve_adminq_command) == 64); 413 414 int gve_adminq_alloc(struct device *dev, struct gve_priv *priv); 415 void gve_adminq_free(struct device *dev, struct gve_priv *priv); 416 void gve_adminq_release(struct gve_priv *priv); 417 int gve_adminq_describe_device(struct gve_priv *priv); 418 int gve_adminq_configure_device_resources(struct gve_priv *priv, 419 dma_addr_t counter_array_bus_addr, 420 u32 num_counters, 421 dma_addr_t db_array_bus_addr, 422 u32 num_ntfy_blks); 423 int gve_adminq_deconfigure_device_resources(struct gve_priv *priv); 424 int gve_adminq_create_tx_queues(struct gve_priv *priv, u32 start_id, u32 num_queues); 425 int gve_adminq_destroy_tx_queues(struct gve_priv *priv, u32 start_id, u32 num_queues); 426 int gve_adminq_create_rx_queues(struct gve_priv *priv, u32 num_queues); 427 int gve_adminq_destroy_rx_queues(struct gve_priv *priv, u32 queue_id); 428 int gve_adminq_register_page_list(struct gve_priv *priv, 429 struct gve_queue_page_list *qpl); 430 int gve_adminq_unregister_page_list(struct gve_priv *priv, u32 page_list_id); 431 int gve_adminq_set_mtu(struct gve_priv *priv, u64 mtu); 432 int gve_adminq_report_stats(struct gve_priv *priv, u64 stats_report_len, 433 dma_addr_t stats_report_addr, u64 interval); 434 int gve_adminq_verify_driver_compatibility(struct gve_priv *priv, 435 u64 driver_info_len, 436 dma_addr_t driver_info_addr); 437 int gve_adminq_report_link_speed(struct gve_priv *priv); 438 439 struct gve_ptype_lut; 440 int gve_adminq_get_ptype_map_dqo(struct gve_priv *priv, 441 struct gve_ptype_lut *ptype_lut); 442 443 #endif /* _GVE_ADMINQ_H */ 444