1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 3 #ifndef _FUNETH_TXRX_H 4 #define _FUNETH_TXRX_H 5 6 #include <linux/netdevice.h> 7 #include <linux/u64_stats_sync.h> 8 9 /* Tx descriptor size */ 10 #define FUNETH_SQE_SIZE 64U 11 12 /* Size of device headers per Tx packet */ 13 #define FUNETH_FUNOS_HDR_SZ (sizeof(struct fun_eth_tx_req)) 14 15 /* Number of gather list entries per Tx descriptor */ 16 #define FUNETH_GLE_PER_DESC (FUNETH_SQE_SIZE / sizeof(struct fun_dataop_gl)) 17 18 /* Max gather list size in bytes for an sk_buff. */ 19 #define FUNETH_MAX_GL_SZ ((MAX_SKB_FRAGS + 1) * sizeof(struct fun_dataop_gl)) 20 21 #if IS_ENABLED(CONFIG_TLS_DEVICE) 22 # define FUNETH_TLS_SZ sizeof(struct fun_eth_tls) 23 #else 24 # define FUNETH_TLS_SZ 0 25 #endif 26 27 /* Max number of Tx descriptors for an sk_buff using a gather list. */ 28 #define FUNETH_MAX_GL_DESC \ 29 DIV_ROUND_UP((FUNETH_FUNOS_HDR_SZ + FUNETH_MAX_GL_SZ + FUNETH_TLS_SZ), \ 30 FUNETH_SQE_SIZE) 31 32 /* Max number of Tx descriptors for any packet. */ 33 #define FUNETH_MAX_PKT_DESC FUNETH_MAX_GL_DESC 34 35 /* Rx CQ descriptor size. */ 36 #define FUNETH_CQE_SIZE 64U 37 38 /* Offset of cqe_info within a CQE. */ 39 #define FUNETH_CQE_INFO_OFFSET (FUNETH_CQE_SIZE - sizeof(struct fun_cqe_info)) 40 41 /* Construct the IRQ portion of a CQ doorbell. The resulting value arms the 42 * interrupt with the supplied time delay and packet count moderation settings. 43 */ 44 #define FUN_IRQ_CQ_DB(usec, pkts) \ 45 (FUN_DB_IRQ_ARM_F | ((usec) << FUN_DB_INTCOAL_USEC_S) | \ 46 ((pkts) << FUN_DB_INTCOAL_ENTRIES_S)) 47 48 /* As above for SQ doorbells. */ 49 #define FUN_IRQ_SQ_DB(usec, pkts) \ 50 (FUN_DB_IRQ_ARM_F | \ 51 ((usec) << FUN_DB_INTCOAL_USEC_S) | \ 52 ((pkts) << FUN_DB_INTCOAL_ENTRIES_S)) 53 54 /* Per packet tailroom. Present only for 1-frag packets. */ 55 #define FUN_RX_TAILROOM SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) 56 57 /* Per packet headroom for XDP. Preferred over XDP_PACKET_HEADROOM to 58 * accommodate two packets per buffer for 4K pages and 1500B MTUs. 59 */ 60 #define FUN_XDP_HEADROOM 192 61 62 /* Initialization state of a queue. */ 63 enum { 64 FUN_QSTATE_DESTROYED, /* what queue? */ 65 FUN_QSTATE_INIT_SW, /* exists in SW, not on the device */ 66 FUN_QSTATE_INIT_FULL, /* exists both in SW and on device */ 67 }; 68 69 /* Initialization state of an interrupt. */ 70 enum { 71 FUN_IRQ_INIT, /* initialized and in the XArray but inactive */ 72 FUN_IRQ_REQUESTED, /* request_irq() done */ 73 FUN_IRQ_ENABLED, /* processing enabled */ 74 FUN_IRQ_DISABLED, /* processing disabled */ 75 }; 76 77 struct bpf_prog; 78 79 struct funeth_txq_stats { /* per Tx queue SW counters */ 80 u64 tx_pkts; /* # of Tx packets */ 81 u64 tx_bytes; /* total bytes of Tx packets */ 82 u64 tx_cso; /* # of packets with checksum offload */ 83 u64 tx_tso; /* # of non-encapsulated TSO super-packets */ 84 u64 tx_encap_tso; /* # of encapsulated TSO super-packets */ 85 u64 tx_uso; /* # of non-encapsulated UDP LSO super-packets */ 86 u64 tx_more; /* # of DBs elided due to xmit_more */ 87 u64 tx_nstops; /* # of times the queue has stopped */ 88 u64 tx_nrestarts; /* # of times the queue has restarted */ 89 u64 tx_map_err; /* # of packets dropped due to DMA mapping errors */ 90 u64 tx_xdp_full; /* # of XDP packets that could not be enqueued */ 91 u64 tx_tls_pkts; /* # of Tx TLS packets offloaded to HW */ 92 u64 tx_tls_bytes; /* Tx bytes of HW-handled TLS payload */ 93 u64 tx_tls_fallback; /* attempted Tx TLS offloads punted to SW */ 94 u64 tx_tls_drops; /* attempted Tx TLS offloads dropped */ 95 }; 96 97 struct funeth_tx_info { /* per Tx descriptor state */ 98 union { 99 struct sk_buff *skb; /* associated packet (sk_buff path) */ 100 struct xdp_frame *xdpf; /* associated XDP frame (XDP path) */ 101 }; 102 }; 103 104 struct funeth_txq { 105 /* RO cacheline of frequently accessed data */ 106 u32 mask; /* queue depth - 1 */ 107 u32 hw_qid; /* device ID of the queue */ 108 void *desc; /* base address of descriptor ring */ 109 struct funeth_tx_info *info; 110 struct device *dma_dev; /* device for DMA mappings */ 111 volatile __be64 *hw_wb; /* HW write-back location */ 112 u32 __iomem *db; /* SQ doorbell register address */ 113 struct netdev_queue *ndq; 114 dma_addr_t dma_addr; /* DMA address of descriptor ring */ 115 /* producer R/W cacheline */ 116 u16 qidx; /* queue index within net_device */ 117 u16 ethid; 118 u32 prod_cnt; /* producer counter */ 119 struct funeth_txq_stats stats; 120 /* shared R/W cacheline, primarily accessed by consumer */ 121 u32 irq_db_val; /* value written to IRQ doorbell */ 122 u32 cons_cnt; /* consumer (cleanup) counter */ 123 struct net_device *netdev; 124 struct fun_irq *irq; 125 int numa_node; 126 u8 init_state; /* queue initialization state */ 127 struct u64_stats_sync syncp; 128 }; 129 130 struct funeth_rxq_stats { /* per Rx queue SW counters */ 131 u64 rx_pkts; /* # of received packets, including SW drops */ 132 u64 rx_bytes; /* total size of received packets */ 133 u64 rx_cso; /* # of packets with checksum offload */ 134 u64 rx_bufs; /* total # of Rx buffers provided to device */ 135 u64 gro_pkts; /* # of GRO superpackets */ 136 u64 gro_merged; /* # of pkts merged into existing GRO superpackets */ 137 u64 rx_page_alloc; /* # of page allocations for Rx buffers */ 138 u64 rx_budget; /* NAPI iterations that exhausted their budget */ 139 u64 rx_mem_drops; /* # of packets dropped due to memory shortage */ 140 u64 rx_map_err; /* # of page DMA mapping errors */ 141 u64 xdp_drops; /* XDP_DROPped packets */ 142 u64 xdp_tx; /* successful XDP transmits */ 143 u64 xdp_redir; /* successful XDP redirects */ 144 u64 xdp_err; /* packets dropped due to XDP errors */ 145 }; 146 147 struct funeth_rxbuf { /* per Rx buffer state */ 148 struct page *page; /* associated page */ 149 dma_addr_t dma_addr; /* DMA address of page start */ 150 int pg_refs; /* page refs held by driver */ 151 int node; /* page node, or -1 if it is PF_MEMALLOC */ 152 }; 153 154 struct funeth_rx_cache { /* cache of DMA-mapped previously used buffers */ 155 struct funeth_rxbuf *bufs; /* base of Rx buffer state ring */ 156 unsigned int prod_cnt; /* producer counter */ 157 unsigned int cons_cnt; /* consumer counter */ 158 unsigned int mask; /* depth - 1 */ 159 }; 160 161 /* An Rx queue consists of a CQ and an SQ used to provide Rx buffers. */ 162 struct funeth_rxq { 163 struct net_device *netdev; 164 struct napi_struct *napi; 165 struct device *dma_dev; /* device for DMA mappings */ 166 void *cqes; /* base of CQ descriptor ring */ 167 const void *next_cqe_info; /* fun_cqe_info of next CQE */ 168 u32 __iomem *cq_db; /* CQ doorbell register address */ 169 unsigned int cq_head; /* CQ head index */ 170 unsigned int cq_mask; /* CQ depth - 1 */ 171 u16 phase; /* CQ phase tag */ 172 u16 qidx; /* queue index within net_device */ 173 unsigned int irq_db_val; /* IRQ info for CQ doorbell */ 174 struct fun_eprq_rqbuf *rqes; /* base of RQ descriptor ring */ 175 struct funeth_rxbuf *bufs; /* base of Rx buffer state ring */ 176 struct funeth_rxbuf *cur_buf; /* currently active buffer */ 177 u32 __iomem *rq_db; /* RQ doorbell register address */ 178 unsigned int rq_cons; /* RQ consumer counter */ 179 unsigned int rq_mask; /* RQ depth - 1 */ 180 unsigned int buf_offset; /* offset of next pkt in head buffer */ 181 u8 xdp_flush; /* XDP flush types needed at NAPI end */ 182 u8 init_state; /* queue initialization state */ 183 u16 headroom; /* per packet headroom */ 184 unsigned int rq_cons_db; /* value of rq_cons at last RQ db */ 185 unsigned int rq_db_thres; /* # of new buffers needed to write RQ db */ 186 struct funeth_rxbuf spare_buf; /* spare for next buffer replacement */ 187 struct funeth_rx_cache cache; /* used buffer cache */ 188 struct bpf_prog *xdp_prog; /* optional XDP BPF program */ 189 struct funeth_rxq_stats stats; 190 dma_addr_t cq_dma_addr; /* DMA address of CQE ring */ 191 dma_addr_t rq_dma_addr; /* DMA address of RQE ring */ 192 u16 irq_cnt; 193 u32 hw_cqid; /* device ID of the queue's CQ */ 194 u32 hw_sqid; /* device ID of the queue's SQ */ 195 int numa_node; 196 struct u64_stats_sync syncp; 197 struct xdp_rxq_info xdp_rxq; 198 }; 199 200 #define FUN_QSTAT_INC(q, counter) \ 201 do { \ 202 u64_stats_update_begin(&(q)->syncp); \ 203 (q)->stats.counter++; \ 204 u64_stats_update_end(&(q)->syncp); \ 205 } while (0) 206 207 #define FUN_QSTAT_READ(q, seq, stats_copy) \ 208 do { \ 209 seq = u64_stats_fetch_begin_irq(&(q)->syncp); \ 210 stats_copy = (q)->stats; \ 211 } while (u64_stats_fetch_retry_irq(&(q)->syncp, (seq))) 212 213 #define FUN_INT_NAME_LEN (IFNAMSIZ + 16) 214 215 struct fun_irq { 216 struct napi_struct napi; 217 struct funeth_txq *txq; 218 struct funeth_rxq *rxq; 219 u8 state; 220 u16 irq_idx; /* index of MSI-X interrupt */ 221 int irq; /* Linux IRQ vector */ 222 cpumask_t affinity_mask; /* IRQ affinity */ 223 struct irq_affinity_notify aff_notify; 224 char name[FUN_INT_NAME_LEN]; 225 } ____cacheline_internodealigned_in_smp; 226 227 /* Return the start address of the idx-th Tx descriptor. */ 228 static inline void *fun_tx_desc_addr(const struct funeth_txq *q, 229 unsigned int idx) 230 { 231 return q->desc + idx * FUNETH_SQE_SIZE; 232 } 233 234 static inline void fun_txq_wr_db(const struct funeth_txq *q) 235 { 236 unsigned int tail = q->prod_cnt & q->mask; 237 238 writel(tail, q->db); 239 } 240 241 static inline int fun_irq_node(const struct fun_irq *p) 242 { 243 return cpu_to_mem(cpumask_first(&p->affinity_mask)); 244 } 245 246 int fun_rxq_napi_poll(struct napi_struct *napi, int budget); 247 int fun_txq_napi_poll(struct napi_struct *napi, int budget); 248 netdev_tx_t fun_start_xmit(struct sk_buff *skb, struct net_device *netdev); 249 bool fun_xdp_tx(struct funeth_txq *q, struct xdp_frame *xdpf); 250 int fun_xdp_xmit_frames(struct net_device *dev, int n, 251 struct xdp_frame **frames, u32 flags); 252 253 int funeth_txq_create(struct net_device *dev, unsigned int qidx, 254 unsigned int ndesc, struct fun_irq *irq, int state, 255 struct funeth_txq **qp); 256 int fun_txq_create_dev(struct funeth_txq *q, struct fun_irq *irq); 257 struct funeth_txq *funeth_txq_free(struct funeth_txq *q, int state); 258 int funeth_rxq_create(struct net_device *dev, unsigned int qidx, 259 unsigned int ncqe, unsigned int nrqe, struct fun_irq *irq, 260 int state, struct funeth_rxq **qp); 261 int fun_rxq_create_dev(struct funeth_rxq *q, struct fun_irq *irq); 262 struct funeth_rxq *funeth_rxq_free(struct funeth_rxq *q, int state); 263 int fun_rxq_set_bpf(struct funeth_rxq *q, struct bpf_prog *prog); 264 265 #endif /* _FUNETH_TXRX_H */ 266