1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * drivers/net/ethernet/freescale/gianfar.h 4 * 5 * Gianfar Ethernet Driver 6 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560 7 * Based on 8260_io/fcc_enet.c 8 * 9 * Author: Andy Fleming 10 * Maintainer: Kumar Gala 11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 12 * 13 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc. 14 * 15 * Still left to do: 16 * -Add support for module parameters 17 * -Add patch for ethtool phys id 18 */ 19 #ifndef __GIANFAR_H 20 #define __GIANFAR_H 21 22 #include <linux/kernel.h> 23 #include <linux/sched.h> 24 #include <linux/string.h> 25 #include <linux/errno.h> 26 #include <linux/slab.h> 27 #include <linux/interrupt.h> 28 #include <linux/delay.h> 29 #include <linux/netdevice.h> 30 #include <linux/etherdevice.h> 31 #include <linux/skbuff.h> 32 #include <linux/spinlock.h> 33 #include <linux/mm.h> 34 #include <linux/mii.h> 35 #include <linux/phy.h> 36 37 #include <asm/io.h> 38 #include <asm/irq.h> 39 #include <linux/uaccess.h> 40 #include <linux/module.h> 41 #include <linux/crc32.h> 42 #include <linux/workqueue.h> 43 #include <linux/ethtool.h> 44 45 struct ethtool_flow_spec_container { 46 struct ethtool_rx_flow_spec fs; 47 struct list_head list; 48 }; 49 50 struct ethtool_rx_list { 51 struct list_head list; 52 unsigned int count; 53 }; 54 55 /* Length for FCB */ 56 #define GMAC_FCB_LEN 8 57 58 /* Length for TxPAL */ 59 #define GMAC_TXPAL_LEN 16 60 61 /* Default padding amount */ 62 #define DEFAULT_PADDING 2 63 64 /* Number of bytes to align the rx bufs to */ 65 #define RXBUF_ALIGNMENT 64 66 67 #define DRV_NAME "gfar-enet" 68 69 /* MAXIMUM NUMBER OF QUEUES SUPPORTED */ 70 #define MAX_TX_QS 0x8 71 #define MAX_RX_QS 0x8 72 73 /* MAXIMUM NUMBER OF GROUPS SUPPORTED */ 74 #define MAXGROUPS 0x2 75 76 /* These need to be powers of 2 for this driver */ 77 #define DEFAULT_TX_RING_SIZE 256 78 #define DEFAULT_RX_RING_SIZE 256 79 80 #define GFAR_RX_BUFF_ALLOC 16 81 82 #define GFAR_RX_MAX_RING_SIZE 256 83 #define GFAR_TX_MAX_RING_SIZE 256 84 85 #define FBTHR_SHIFT 24 86 #define DEFAULT_RX_LFC_THR 16 87 #define DEFAULT_LFC_PTVVAL 4 88 89 #define GFAR_RXB_TRUESIZE 2048 90 #define GFAR_SKBFRAG_OVR (RXBUF_ALIGNMENT \ 91 + SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 92 #define GFAR_RXB_SIZE rounddown(GFAR_RXB_TRUESIZE - GFAR_SKBFRAG_OVR, 64) 93 #define GFAR_SKBFRAG_SIZE (GFAR_RXB_SIZE + GFAR_SKBFRAG_OVR) 94 95 #define TX_RING_MOD_MASK(size) (size-1) 96 #define RX_RING_MOD_MASK(size) (size-1) 97 #define GFAR_JUMBO_FRAME_SIZE 9600 98 99 #define DEFAULT_FIFO_TX_THR 0x100 100 #define DEFAULT_FIFO_TX_STARVE 0x40 101 #define DEFAULT_FIFO_TX_STARVE_OFF 0x80 102 103 /* The number of Exact Match registers */ 104 #define GFAR_EM_NUM 15 105 106 /* Latency of interface clock in nanoseconds */ 107 /* Interface clock latency , in this case, means the 108 * time described by a value of 1 in the interrupt 109 * coalescing registers' time fields. Since those fields 110 * refer to the time it takes for 64 clocks to pass, the 111 * latencies are as such: 112 * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick 113 * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick 114 * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick 115 */ 116 #define GFAR_GBIT_TIME 512 117 #define GFAR_100_TIME 2560 118 #define GFAR_10_TIME 25600 119 120 #define DEFAULT_TX_COALESCE 1 121 #define DEFAULT_TXCOUNT 16 122 #define DEFAULT_TXTIME 21 123 124 #define DEFAULT_RXTIME 21 125 126 #define DEFAULT_RX_COALESCE 0 127 #define DEFAULT_RXCOUNT 0 128 129 /* TBI register addresses */ 130 #define MII_TBICON 0x11 131 132 /* TBICON register bit fields */ 133 #define TBICON_CLK_SELECT 0x0020 134 135 /* MAC register bits */ 136 #define MACCFG1_SOFT_RESET 0x80000000 137 #define MACCFG1_RESET_RX_MC 0x00080000 138 #define MACCFG1_RESET_TX_MC 0x00040000 139 #define MACCFG1_RESET_RX_FUN 0x00020000 140 #define MACCFG1_RESET_TX_FUN 0x00010000 141 #define MACCFG1_LOOPBACK 0x00000100 142 #define MACCFG1_RX_FLOW 0x00000020 143 #define MACCFG1_TX_FLOW 0x00000010 144 #define MACCFG1_SYNCD_RX_EN 0x00000008 145 #define MACCFG1_RX_EN 0x00000004 146 #define MACCFG1_SYNCD_TX_EN 0x00000002 147 #define MACCFG1_TX_EN 0x00000001 148 149 #define MACCFG2_INIT_SETTINGS 0x00007205 150 #define MACCFG2_FULL_DUPLEX 0x00000001 151 #define MACCFG2_IF 0x00000300 152 #define MACCFG2_MII 0x00000100 153 #define MACCFG2_GMII 0x00000200 154 #define MACCFG2_HUGEFRAME 0x00000020 155 #define MACCFG2_LENGTHCHECK 0x00000010 156 #define MACCFG2_MPEN 0x00000008 157 158 #define ECNTRL_FIFM 0x00008000 159 #define ECNTRL_INIT_SETTINGS 0x00001000 160 #define ECNTRL_TBI_MODE 0x00000020 161 #define ECNTRL_REDUCED_MODE 0x00000010 162 #define ECNTRL_R100 0x00000008 163 #define ECNTRL_REDUCED_MII_MODE 0x00000004 164 #define ECNTRL_SGMII_MODE 0x00000002 165 166 #define MINFLR_INIT_SETTINGS 0x00000040 167 168 /* Tqueue control */ 169 #define TQUEUE_EN0 0x00008000 170 #define TQUEUE_EN1 0x00004000 171 #define TQUEUE_EN2 0x00002000 172 #define TQUEUE_EN3 0x00001000 173 #define TQUEUE_EN4 0x00000800 174 #define TQUEUE_EN5 0x00000400 175 #define TQUEUE_EN6 0x00000200 176 #define TQUEUE_EN7 0x00000100 177 #define TQUEUE_EN_ALL 0x0000FF00 178 179 #define TR03WT_WT0_MASK 0xFF000000 180 #define TR03WT_WT1_MASK 0x00FF0000 181 #define TR03WT_WT2_MASK 0x0000FF00 182 #define TR03WT_WT3_MASK 0x000000FF 183 184 #define TR47WT_WT4_MASK 0xFF000000 185 #define TR47WT_WT5_MASK 0x00FF0000 186 #define TR47WT_WT6_MASK 0x0000FF00 187 #define TR47WT_WT7_MASK 0x000000FF 188 189 /* Rqueue control */ 190 #define RQUEUE_EX0 0x00800000 191 #define RQUEUE_EX1 0x00400000 192 #define RQUEUE_EX2 0x00200000 193 #define RQUEUE_EX3 0x00100000 194 #define RQUEUE_EX4 0x00080000 195 #define RQUEUE_EX5 0x00040000 196 #define RQUEUE_EX6 0x00020000 197 #define RQUEUE_EX7 0x00010000 198 #define RQUEUE_EX_ALL 0x00FF0000 199 200 #define RQUEUE_EN0 0x00000080 201 #define RQUEUE_EN1 0x00000040 202 #define RQUEUE_EN2 0x00000020 203 #define RQUEUE_EN3 0x00000010 204 #define RQUEUE_EN4 0x00000008 205 #define RQUEUE_EN5 0x00000004 206 #define RQUEUE_EN6 0x00000002 207 #define RQUEUE_EN7 0x00000001 208 #define RQUEUE_EN_ALL 0x000000FF 209 210 /* Init to do tx snooping for buffers and descriptors */ 211 #define DMACTRL_INIT_SETTINGS 0x000000c3 212 #define DMACTRL_GRS 0x00000010 213 #define DMACTRL_GTS 0x00000008 214 215 #define TSTAT_CLEAR_THALT_ALL 0xFF000000 216 #define TSTAT_CLEAR_THALT 0x80000000 217 #define TSTAT_CLEAR_THALT0 0x80000000 218 #define TSTAT_CLEAR_THALT1 0x40000000 219 #define TSTAT_CLEAR_THALT2 0x20000000 220 #define TSTAT_CLEAR_THALT3 0x10000000 221 #define TSTAT_CLEAR_THALT4 0x08000000 222 #define TSTAT_CLEAR_THALT5 0x04000000 223 #define TSTAT_CLEAR_THALT6 0x02000000 224 #define TSTAT_CLEAR_THALT7 0x01000000 225 226 /* Interrupt coalescing macros */ 227 #define IC_ICEN 0x80000000 228 #define IC_ICFT_MASK 0x1fe00000 229 #define IC_ICFT_SHIFT 21 230 #define mk_ic_icft(x) \ 231 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK) 232 #define IC_ICTT_MASK 0x0000ffff 233 #define mk_ic_ictt(x) (x&IC_ICTT_MASK) 234 235 #define mk_ic_value(count, time) (IC_ICEN | \ 236 mk_ic_icft(count) | \ 237 mk_ic_ictt(time)) 238 #define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \ 239 IC_ICFT_SHIFT) 240 #define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK) 241 242 #define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME) 243 #define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME) 244 245 #define RCTRL_TS_ENABLE 0x01000000 246 #define RCTRL_PAL_MASK 0x001f0000 247 #define RCTRL_LFC 0x00004000 248 #define RCTRL_VLEX 0x00002000 249 #define RCTRL_FILREN 0x00001000 250 #define RCTRL_GHTX 0x00000400 251 #define RCTRL_IPCSEN 0x00000200 252 #define RCTRL_TUCSEN 0x00000100 253 #define RCTRL_PRSDEP_MASK 0x000000c0 254 #define RCTRL_PRSDEP_INIT 0x000000c0 255 #define RCTRL_PRSFM 0x00000020 256 #define RCTRL_PROM 0x00000008 257 #define RCTRL_EMEN 0x00000002 258 #define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \ 259 RCTRL_TUCSEN | RCTRL_FILREN) 260 #define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \ 261 RCTRL_PRSDEP_INIT) 262 #define RCTRL_EXTHASH (RCTRL_GHTX) 263 #define RCTRL_VLAN (RCTRL_PRSDEP_INIT) 264 #define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK) 265 266 267 #define RSTAT_CLEAR_RHALT 0x00800000 268 #define RSTAT_CLEAR_RXF0 0x00000080 269 #define RSTAT_RXF_MASK 0x000000ff 270 271 #define TCTRL_IPCSEN 0x00004000 272 #define TCTRL_TUCSEN 0x00002000 273 #define TCTRL_VLINS 0x00001000 274 #define TCTRL_THDF 0x00000800 275 #define TCTRL_RFCPAUSE 0x00000010 276 #define TCTRL_TFCPAUSE 0x00000008 277 #define TCTRL_TXSCHED_MASK 0x00000006 278 #define TCTRL_TXSCHED_INIT 0x00000000 279 /* priority scheduling */ 280 #define TCTRL_TXSCHED_PRIO 0x00000002 281 /* weighted round-robin scheduling (WRRS) */ 282 #define TCTRL_TXSCHED_WRRS 0x00000004 283 /* default WRRS weight and policy setting, 284 * tailored to the tr03wt and tr47wt registers: 285 * equal weight for all Tx Qs, measured in 64byte units 286 */ 287 #define DEFAULT_WRRS_WEIGHT 0x18181818 288 289 #define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN) 290 291 #define IEVENT_INIT_CLEAR 0xffffffff 292 #define IEVENT_BABR 0x80000000 293 #define IEVENT_RXC 0x40000000 294 #define IEVENT_BSY 0x20000000 295 #define IEVENT_EBERR 0x10000000 296 #define IEVENT_MSRO 0x04000000 297 #define IEVENT_GTSC 0x02000000 298 #define IEVENT_BABT 0x01000000 299 #define IEVENT_TXC 0x00800000 300 #define IEVENT_TXE 0x00400000 301 #define IEVENT_TXB 0x00200000 302 #define IEVENT_TXF 0x00100000 303 #define IEVENT_LC 0x00040000 304 #define IEVENT_CRL 0x00020000 305 #define IEVENT_XFUN 0x00010000 306 #define IEVENT_RXB0 0x00008000 307 #define IEVENT_MAG 0x00000800 308 #define IEVENT_GRSC 0x00000100 309 #define IEVENT_RXF0 0x00000080 310 #define IEVENT_FGPI 0x00000010 311 #define IEVENT_FIR 0x00000008 312 #define IEVENT_FIQ 0x00000004 313 #define IEVENT_DPE 0x00000002 314 #define IEVENT_PERR 0x00000001 315 #define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY) 316 #define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF) 317 #define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK) 318 #define IEVENT_ERR_MASK \ 319 (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \ 320 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \ 321 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \ 322 | IEVENT_MAG | IEVENT_BABR) 323 324 #define IMASK_INIT_CLEAR 0x00000000 325 #define IMASK_BABR 0x80000000 326 #define IMASK_RXC 0x40000000 327 #define IMASK_BSY 0x20000000 328 #define IMASK_EBERR 0x10000000 329 #define IMASK_MSRO 0x04000000 330 #define IMASK_GTSC 0x02000000 331 #define IMASK_BABT 0x01000000 332 #define IMASK_TXC 0x00800000 333 #define IMASK_TXEEN 0x00400000 334 #define IMASK_TXBEN 0x00200000 335 #define IMASK_TXFEN 0x00100000 336 #define IMASK_LC 0x00040000 337 #define IMASK_CRL 0x00020000 338 #define IMASK_XFUN 0x00010000 339 #define IMASK_RXB0 0x00008000 340 #define IMASK_MAG 0x00000800 341 #define IMASK_GRSC 0x00000100 342 #define IMASK_RXFEN0 0x00000080 343 #define IMASK_FGPI 0x00000010 344 #define IMASK_FIR 0x00000008 345 #define IMASK_FIQ 0x00000004 346 #define IMASK_DPE 0x00000002 347 #define IMASK_PERR 0x00000001 348 #define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \ 349 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \ 350 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \ 351 | IMASK_PERR) 352 #define IMASK_RX_DEFAULT (IMASK_RXFEN0 | IMASK_BSY) 353 #define IMASK_TX_DEFAULT (IMASK_TXFEN | IMASK_TXBEN) 354 355 #define IMASK_RX_DISABLED ((~(IMASK_RX_DEFAULT)) & IMASK_DEFAULT) 356 #define IMASK_TX_DISABLED ((~(IMASK_TX_DEFAULT)) & IMASK_DEFAULT) 357 358 /* Attribute fields */ 359 360 /* This enables rx snooping for buffers and descriptors */ 361 #define ATTR_BDSTASH 0x00000800 362 363 #define ATTR_BUFSTASH 0x00004000 364 365 #define ATTR_SNOOPING 0x000000c0 366 #define ATTR_INIT_SETTINGS ATTR_SNOOPING 367 368 #define ATTRELI_INIT_SETTINGS 0x0 369 #define ATTRELI_EL_MASK 0x3fff0000 370 #define ATTRELI_EL(x) (x << 16) 371 #define ATTRELI_EI_MASK 0x00003fff 372 #define ATTRELI_EI(x) (x) 373 374 #define BD_LFLAG(flags) ((flags) << 16) 375 #define BD_LENGTH_MASK 0x0000ffff 376 377 #define FPR_FILER_MASK 0xFFFFFFFF 378 #define MAX_FILER_IDX 0xFF 379 380 /* This default RIR value directly corresponds 381 * to the 3-bit hash value generated */ 382 #define DEFAULT_8RXQ_RIR0 0x05397700 383 /* Map even hash values to Q0, and odd ones to Q1 */ 384 #define DEFAULT_2RXQ_RIR0 0x04104100 385 386 /* RQFCR register bits */ 387 #define RQFCR_GPI 0x80000000 388 #define RQFCR_HASHTBL_Q 0x00000000 389 #define RQFCR_HASHTBL_0 0x00020000 390 #define RQFCR_HASHTBL_1 0x00040000 391 #define RQFCR_HASHTBL_2 0x00060000 392 #define RQFCR_HASHTBL_3 0x00080000 393 #define RQFCR_HASH 0x00010000 394 #define RQFCR_QUEUE 0x0000FC00 395 #define RQFCR_CLE 0x00000200 396 #define RQFCR_RJE 0x00000100 397 #define RQFCR_AND 0x00000080 398 #define RQFCR_CMP_EXACT 0x00000000 399 #define RQFCR_CMP_MATCH 0x00000020 400 #define RQFCR_CMP_NOEXACT 0x00000040 401 #define RQFCR_CMP_NOMATCH 0x00000060 402 403 /* RQFCR PID values */ 404 #define RQFCR_PID_MASK 0x00000000 405 #define RQFCR_PID_PARSE 0x00000001 406 #define RQFCR_PID_ARB 0x00000002 407 #define RQFCR_PID_DAH 0x00000003 408 #define RQFCR_PID_DAL 0x00000004 409 #define RQFCR_PID_SAH 0x00000005 410 #define RQFCR_PID_SAL 0x00000006 411 #define RQFCR_PID_ETY 0x00000007 412 #define RQFCR_PID_VID 0x00000008 413 #define RQFCR_PID_PRI 0x00000009 414 #define RQFCR_PID_TOS 0x0000000A 415 #define RQFCR_PID_L4P 0x0000000B 416 #define RQFCR_PID_DIA 0x0000000C 417 #define RQFCR_PID_SIA 0x0000000D 418 #define RQFCR_PID_DPT 0x0000000E 419 #define RQFCR_PID_SPT 0x0000000F 420 421 /* RQFPR when PID is 0x0001 */ 422 #define RQFPR_HDR_GE_512 0x00200000 423 #define RQFPR_LERR 0x00100000 424 #define RQFPR_RAR 0x00080000 425 #define RQFPR_RARQ 0x00040000 426 #define RQFPR_AR 0x00020000 427 #define RQFPR_ARQ 0x00010000 428 #define RQFPR_EBC 0x00008000 429 #define RQFPR_VLN 0x00004000 430 #define RQFPR_CFI 0x00002000 431 #define RQFPR_JUM 0x00001000 432 #define RQFPR_IPF 0x00000800 433 #define RQFPR_FIF 0x00000400 434 #define RQFPR_IPV4 0x00000200 435 #define RQFPR_IPV6 0x00000100 436 #define RQFPR_ICC 0x00000080 437 #define RQFPR_ICV 0x00000040 438 #define RQFPR_TCP 0x00000020 439 #define RQFPR_UDP 0x00000010 440 #define RQFPR_TUC 0x00000008 441 #define RQFPR_TUV 0x00000004 442 #define RQFPR_PER 0x00000002 443 #define RQFPR_EER 0x00000001 444 445 /* CAR1 bits */ 446 #define CAR1_C164 0x80000000 447 #define CAR1_C1127 0x40000000 448 #define CAR1_C1255 0x20000000 449 #define CAR1_C1511 0x10000000 450 #define CAR1_C11K 0x08000000 451 #define CAR1_C1MAX 0x04000000 452 #define CAR1_C1MGV 0x02000000 453 #define CAR1_C1REJ 0x00020000 454 #define CAR1_C1RBY 0x00010000 455 #define CAR1_C1RPK 0x00008000 456 #define CAR1_C1RFC 0x00004000 457 #define CAR1_C1RMC 0x00002000 458 #define CAR1_C1RBC 0x00001000 459 #define CAR1_C1RXC 0x00000800 460 #define CAR1_C1RXP 0x00000400 461 #define CAR1_C1RXU 0x00000200 462 #define CAR1_C1RAL 0x00000100 463 #define CAR1_C1RFL 0x00000080 464 #define CAR1_C1RCD 0x00000040 465 #define CAR1_C1RCS 0x00000020 466 #define CAR1_C1RUN 0x00000010 467 #define CAR1_C1ROV 0x00000008 468 #define CAR1_C1RFR 0x00000004 469 #define CAR1_C1RJB 0x00000002 470 #define CAR1_C1RDR 0x00000001 471 472 /* CAM1 bits */ 473 #define CAM1_M164 0x80000000 474 #define CAM1_M1127 0x40000000 475 #define CAM1_M1255 0x20000000 476 #define CAM1_M1511 0x10000000 477 #define CAM1_M11K 0x08000000 478 #define CAM1_M1MAX 0x04000000 479 #define CAM1_M1MGV 0x02000000 480 #define CAM1_M1REJ 0x00020000 481 #define CAM1_M1RBY 0x00010000 482 #define CAM1_M1RPK 0x00008000 483 #define CAM1_M1RFC 0x00004000 484 #define CAM1_M1RMC 0x00002000 485 #define CAM1_M1RBC 0x00001000 486 #define CAM1_M1RXC 0x00000800 487 #define CAM1_M1RXP 0x00000400 488 #define CAM1_M1RXU 0x00000200 489 #define CAM1_M1RAL 0x00000100 490 #define CAM1_M1RFL 0x00000080 491 #define CAM1_M1RCD 0x00000040 492 #define CAM1_M1RCS 0x00000020 493 #define CAM1_M1RUN 0x00000010 494 #define CAM1_M1ROV 0x00000008 495 #define CAM1_M1RFR 0x00000004 496 #define CAM1_M1RJB 0x00000002 497 #define CAM1_M1RDR 0x00000001 498 499 /* TxBD status field bits */ 500 #define TXBD_READY 0x8000 501 #define TXBD_PADCRC 0x4000 502 #define TXBD_WRAP 0x2000 503 #define TXBD_INTERRUPT 0x1000 504 #define TXBD_LAST 0x0800 505 #define TXBD_CRC 0x0400 506 #define TXBD_DEF 0x0200 507 #define TXBD_HUGEFRAME 0x0080 508 #define TXBD_LATECOLLISION 0x0080 509 #define TXBD_RETRYLIMIT 0x0040 510 #define TXBD_RETRYCOUNTMASK 0x003c 511 #define TXBD_UNDERRUN 0x0002 512 #define TXBD_TOE 0x0002 513 514 /* Tx FCB param bits */ 515 #define TXFCB_VLN 0x80 516 #define TXFCB_IP 0x40 517 #define TXFCB_IP6 0x20 518 #define TXFCB_TUP 0x10 519 #define TXFCB_UDP 0x08 520 #define TXFCB_CIP 0x04 521 #define TXFCB_CTU 0x02 522 #define TXFCB_NPH 0x01 523 #define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH) 524 525 /* RxBD status field bits */ 526 #define RXBD_EMPTY 0x8000 527 #define RXBD_RO1 0x4000 528 #define RXBD_WRAP 0x2000 529 #define RXBD_INTERRUPT 0x1000 530 #define RXBD_LAST 0x0800 531 #define RXBD_FIRST 0x0400 532 #define RXBD_MISS 0x0100 533 #define RXBD_BROADCAST 0x0080 534 #define RXBD_MULTICAST 0x0040 535 #define RXBD_LARGE 0x0020 536 #define RXBD_NONOCTET 0x0010 537 #define RXBD_SHORT 0x0008 538 #define RXBD_CRCERR 0x0004 539 #define RXBD_OVERRUN 0x0002 540 #define RXBD_TRUNCATED 0x0001 541 #define RXBD_STATS 0x01ff 542 #define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \ 543 | RXBD_CRCERR | RXBD_OVERRUN \ 544 | RXBD_TRUNCATED) 545 546 /* Rx FCB status field bits */ 547 #define RXFCB_VLN 0x8000 548 #define RXFCB_IP 0x4000 549 #define RXFCB_IP6 0x2000 550 #define RXFCB_TUP 0x1000 551 #define RXFCB_CIP 0x0800 552 #define RXFCB_CTU 0x0400 553 #define RXFCB_EIP 0x0200 554 #define RXFCB_ETU 0x0100 555 #define RXFCB_CSUM_MASK 0x0f00 556 #define RXFCB_PERR_MASK 0x000c 557 #define RXFCB_PERR_BADL3 0x0008 558 559 #define GFAR_INT_NAME_MAX (IFNAMSIZ + 6) /* '_g#_xx' */ 560 561 #define GFAR_WOL_MAGIC 0x00000001 562 #define GFAR_WOL_FILER_UCAST 0x00000002 563 564 struct txbd8 565 { 566 union { 567 struct { 568 __be16 status; /* Status Fields */ 569 __be16 length; /* Buffer length */ 570 }; 571 __be32 lstatus; 572 }; 573 __be32 bufPtr; /* Buffer Pointer */ 574 }; 575 576 struct txfcb { 577 u8 flags; 578 u8 ptp; /* Flag to enable tx timestamping */ 579 u8 l4os; /* Level 4 Header Offset */ 580 u8 l3os; /* Level 3 Header Offset */ 581 __be16 phcs; /* Pseudo-header Checksum */ 582 __be16 vlctl; /* VLAN control word */ 583 }; 584 585 struct rxbd8 586 { 587 union { 588 struct { 589 __be16 status; /* Status Fields */ 590 __be16 length; /* Buffer Length */ 591 }; 592 __be32 lstatus; 593 }; 594 __be32 bufPtr; /* Buffer Pointer */ 595 }; 596 597 struct rxfcb { 598 __be16 flags; 599 u8 rq; /* Receive Queue index */ 600 u8 pro; /* Layer 4 Protocol */ 601 u16 reserved; 602 __be16 vlctl; /* VLAN control word */ 603 }; 604 605 struct gianfar_skb_cb { 606 unsigned int bytes_sent; /* bytes-on-wire (i.e. no FCB) */ 607 }; 608 609 #define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb)) 610 611 struct rmon_mib 612 { 613 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */ 614 u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */ 615 u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */ 616 u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */ 617 u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */ 618 u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */ 619 u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ 620 u32 rbyt; /* 0x.69c - Receive Byte Counter */ 621 u32 rpkt; /* 0x.6a0 - Receive Packet Counter */ 622 u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */ 623 u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */ 624 u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */ 625 u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */ 626 u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */ 627 u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */ 628 u32 raln; /* 0x.6bc - Receive Alignment Error Counter */ 629 u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */ 630 u32 rcde; /* 0x.6c4 - Receive Code Error Counter */ 631 u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */ 632 u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */ 633 u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */ 634 u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */ 635 u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */ 636 u32 rdrp; /* 0x.6dc - Receive Drop Counter */ 637 u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */ 638 u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */ 639 u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */ 640 u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */ 641 u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */ 642 u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */ 643 u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */ 644 u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */ 645 u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */ 646 u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */ 647 u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */ 648 u32 tncl; /* 0x.70c - Transmit Total Collision Counter */ 649 u8 res1[4]; 650 u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */ 651 u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */ 652 u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */ 653 u32 txcf; /* 0x.720 - Transmit Control Frame Counter */ 654 u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */ 655 u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */ 656 u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */ 657 u32 car1; /* 0x.730 - Carry Register One */ 658 u32 car2; /* 0x.734 - Carry Register Two */ 659 u32 cam1; /* 0x.738 - Carry Mask Register One */ 660 u32 cam2; /* 0x.73c - Carry Mask Register Two */ 661 }; 662 663 struct rmon_overflow { 664 /* lock for synchronization of the rdrp field of this struct, and 665 * CAR1/CAR2 registers 666 */ 667 spinlock_t lock; 668 u32 imask; 669 u64 rdrp; 670 }; 671 672 struct gfar_extra_stats { 673 atomic64_t rx_alloc_err; 674 atomic64_t rx_large; 675 atomic64_t rx_short; 676 atomic64_t rx_nonoctet; 677 atomic64_t rx_crcerr; 678 atomic64_t rx_overrun; 679 atomic64_t rx_bsy; 680 atomic64_t rx_babr; 681 atomic64_t rx_trunc; 682 atomic64_t eberr; 683 atomic64_t tx_babt; 684 atomic64_t tx_underrun; 685 atomic64_t tx_timeout; 686 }; 687 688 #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32)) 689 #define GFAR_EXTRA_STATS_LEN \ 690 (sizeof(struct gfar_extra_stats)/sizeof(atomic64_t)) 691 692 /* Number of stats exported via ethtool */ 693 #define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN) 694 695 struct gfar { 696 u32 tsec_id; /* 0x.000 - Controller ID register */ 697 u32 tsec_id2; /* 0x.004 - Controller ID2 register */ 698 u8 res1[8]; 699 u32 ievent; /* 0x.010 - Interrupt Event Register */ 700 u32 imask; /* 0x.014 - Interrupt Mask Register */ 701 u32 edis; /* 0x.018 - Error Disabled Register */ 702 u32 emapg; /* 0x.01c - Group Error mapping register */ 703 u32 ecntrl; /* 0x.020 - Ethernet Control Register */ 704 u32 minflr; /* 0x.024 - Minimum Frame Length Register */ 705 u32 ptv; /* 0x.028 - Pause Time Value Register */ 706 u32 dmactrl; /* 0x.02c - DMA Control Register */ 707 u32 tbipa; /* 0x.030 - TBI PHY Address Register */ 708 u8 res2[28]; 709 u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold 710 register */ 711 u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff 712 register */ 713 u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold 714 register */ 715 u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve 716 shutoff register */ 717 u8 res3[44]; 718 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */ 719 u8 res4[8]; 720 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */ 721 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */ 722 u8 res5[96]; 723 u32 tctrl; /* 0x.100 - Transmit Control Register */ 724 u32 tstat; /* 0x.104 - Transmit Status Register */ 725 u32 dfvlan; /* 0x.108 - Default VLAN Control word */ 726 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */ 727 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */ 728 u32 tqueue; /* 0x.114 - Transmit queue control register */ 729 u8 res7[40]; 730 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */ 731 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */ 732 u8 res8[52]; 733 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */ 734 u8 res9a[4]; 735 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */ 736 u8 res9b[4]; 737 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */ 738 u8 res9c[4]; 739 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */ 740 u8 res9d[4]; 741 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */ 742 u8 res9e[4]; 743 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */ 744 u8 res9f[4]; 745 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */ 746 u8 res9g[4]; 747 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */ 748 u8 res9h[4]; 749 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */ 750 u8 res9[64]; 751 u32 tbaseh; /* 0x.200 - TxBD base address high */ 752 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */ 753 u8 res10a[4]; 754 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */ 755 u8 res10b[4]; 756 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */ 757 u8 res10c[4]; 758 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */ 759 u8 res10d[4]; 760 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */ 761 u8 res10e[4]; 762 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */ 763 u8 res10f[4]; 764 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */ 765 u8 res10g[4]; 766 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */ 767 u8 res10[192]; 768 u32 rctrl; /* 0x.300 - Receive Control Register */ 769 u32 rstat; /* 0x.304 - Receive Status Register */ 770 u8 res12[8]; 771 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */ 772 u32 rqueue; /* 0x.314 - Receive queue control register */ 773 u32 rir0; /* 0x.318 - Ring mapping register 0 */ 774 u32 rir1; /* 0x.31c - Ring mapping register 1 */ 775 u32 rir2; /* 0x.320 - Ring mapping register 2 */ 776 u32 rir3; /* 0x.324 - Ring mapping register 3 */ 777 u8 res13[8]; 778 u32 rbifx; /* 0x.330 - Receive bit field extract control register */ 779 u32 rqfar; /* 0x.334 - Receive queue filing table address register */ 780 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */ 781 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */ 782 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */ 783 u8 res14[56]; 784 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */ 785 u8 res15a[4]; 786 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */ 787 u8 res15b[4]; 788 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */ 789 u8 res15c[4]; 790 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */ 791 u8 res15d[4]; 792 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */ 793 u8 res15e[4]; 794 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */ 795 u8 res15f[4]; 796 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */ 797 u8 res15g[4]; 798 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */ 799 u8 res15h[4]; 800 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */ 801 u8 res16[64]; 802 u32 rbaseh; /* 0x.400 - RxBD base address high */ 803 u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */ 804 u8 res17a[4]; 805 u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */ 806 u8 res17b[4]; 807 u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */ 808 u8 res17c[4]; 809 u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */ 810 u8 res17d[4]; 811 u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */ 812 u8 res17e[4]; 813 u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */ 814 u8 res17f[4]; 815 u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */ 816 u8 res17g[4]; 817 u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */ 818 u8 res17[192]; 819 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */ 820 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */ 821 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */ 822 u32 hafdup; /* 0x.50c - Half Duplex Register */ 823 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */ 824 u8 res18[12]; 825 u8 gfar_mii_regs[24]; /* See gianfar_phy.h */ 826 u32 ifctrl; /* 0x.538 - Interface control register */ 827 u32 ifstat; /* 0x.53c - Interface Status Register */ 828 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */ 829 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */ 830 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */ 831 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */ 832 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */ 833 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */ 834 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */ 835 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */ 836 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */ 837 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */ 838 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */ 839 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */ 840 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */ 841 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */ 842 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */ 843 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */ 844 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */ 845 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */ 846 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */ 847 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */ 848 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/ 849 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/ 850 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/ 851 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/ 852 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/ 853 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/ 854 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/ 855 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/ 856 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/ 857 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/ 858 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/ 859 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/ 860 u8 res20[192]; 861 struct rmon_mib rmon; /* 0x.680-0x.73c */ 862 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */ 863 u8 res21[188]; 864 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/ 865 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/ 866 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/ 867 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/ 868 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/ 869 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/ 870 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/ 871 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/ 872 u8 res22[96]; 873 u32 gaddr0; /* 0x.880 - Group address register 0 */ 874 u32 gaddr1; /* 0x.884 - Group address register 1 */ 875 u32 gaddr2; /* 0x.888 - Group address register 2 */ 876 u32 gaddr3; /* 0x.88c - Group address register 3 */ 877 u32 gaddr4; /* 0x.890 - Group address register 4 */ 878 u32 gaddr5; /* 0x.894 - Group address register 5 */ 879 u32 gaddr6; /* 0x.898 - Group address register 6 */ 880 u32 gaddr7; /* 0x.89c - Group address register 7 */ 881 u8 res23a[352]; 882 u32 fifocfg; /* 0x.a00 - FIFO interface config register */ 883 u8 res23b[252]; 884 u8 res23c[248]; 885 u32 attr; /* 0x.bf8 - Attributes Register */ 886 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */ 887 u32 rqprm0; /* 0x.c00 - Receive queue parameters register 0 */ 888 u32 rqprm1; /* 0x.c04 - Receive queue parameters register 1 */ 889 u32 rqprm2; /* 0x.c08 - Receive queue parameters register 2 */ 890 u32 rqprm3; /* 0x.c0c - Receive queue parameters register 3 */ 891 u32 rqprm4; /* 0x.c10 - Receive queue parameters register 4 */ 892 u32 rqprm5; /* 0x.c14 - Receive queue parameters register 5 */ 893 u32 rqprm6; /* 0x.c18 - Receive queue parameters register 6 */ 894 u32 rqprm7; /* 0x.c1c - Receive queue parameters register 7 */ 895 u8 res24[36]; 896 u32 rfbptr0; /* 0x.c44 - Last free RxBD pointer for ring 0 */ 897 u8 res24a[4]; 898 u32 rfbptr1; /* 0x.c4c - Last free RxBD pointer for ring 1 */ 899 u8 res24b[4]; 900 u32 rfbptr2; /* 0x.c54 - Last free RxBD pointer for ring 2 */ 901 u8 res24c[4]; 902 u32 rfbptr3; /* 0x.c5c - Last free RxBD pointer for ring 3 */ 903 u8 res24d[4]; 904 u32 rfbptr4; /* 0x.c64 - Last free RxBD pointer for ring 4 */ 905 u8 res24e[4]; 906 u32 rfbptr5; /* 0x.c6c - Last free RxBD pointer for ring 5 */ 907 u8 res24f[4]; 908 u32 rfbptr6; /* 0x.c74 - Last free RxBD pointer for ring 6 */ 909 u8 res24g[4]; 910 u32 rfbptr7; /* 0x.c7c - Last free RxBD pointer for ring 7 */ 911 u8 res24h[4]; 912 u8 res24x[556]; 913 u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */ 914 u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */ 915 u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */ 916 u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */ 917 u8 res25[16]; 918 u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */ 919 u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */ 920 u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */ 921 u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */ 922 u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */ 923 u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */ 924 u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */ 925 u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */ 926 u8 res26[32]; 927 u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */ 928 u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */ 929 u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */ 930 u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */ 931 u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */ 932 u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */ 933 u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */ 934 u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */ 935 u8 res27[208]; 936 }; 937 938 /* Flags related to gianfar device features */ 939 #define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001 940 #define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002 941 #define FSL_GIANFAR_DEV_HAS_RMON 0x00000004 942 #define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008 943 #define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010 944 #define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020 945 #define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040 946 #define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100 947 #define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200 948 #define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400 949 #define FSL_GIANFAR_DEV_HAS_TIMER 0x00000800 950 #define FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER 0x00001000 951 #define FSL_GIANFAR_DEV_HAS_RX_FILER 0x00002000 952 953 #if (MAXGROUPS == 2) 954 #define DEFAULT_MAPPING 0xAA 955 #else 956 #define DEFAULT_MAPPING 0xFF 957 #endif 958 959 #define ISRG_RR0 0x80000000 960 #define ISRG_TR0 0x00800000 961 962 /* The same driver can operate in two modes */ 963 /* SQ_SG_MODE: Single Queue Single Group Mode 964 * (Backward compatible mode) 965 * MQ_MG_MODE: Multi Queue Multi Group mode 966 */ 967 enum { 968 SQ_SG_MODE = 0, 969 MQ_MG_MODE 970 }; 971 972 /* 973 * Per TX queue stats 974 */ 975 struct tx_q_stats { 976 u64 tx_packets; 977 u64 tx_bytes; 978 }; 979 980 /** 981 * struct gfar_priv_tx_q - per tx queue structure 982 * @txlock: per queue tx spin lock 983 * @tx_skbuff:skb pointers 984 * @skb_curtx: to be used skb pointer 985 * @skb_dirtytx:the last used skb pointer 986 * @stats: bytes/packets stats 987 * @qindex: index of this queue 988 * @dev: back pointer to the dev structure 989 * @grp: back pointer to the group to which this queue belongs 990 * @tx_bd_base: First tx buffer descriptor 991 * @cur_tx: Next free ring entry 992 * @dirty_tx: First buffer in line to be transmitted 993 * @tx_ring_size: Tx ring size 994 * @num_txbdfree: number of free TxBds 995 * @txcoalescing: enable/disable tx coalescing 996 * @txic: transmit interrupt coalescing value 997 * @txcount: coalescing value if based on tx frame count 998 * @txtime: coalescing value if based on time 999 */ 1000 struct gfar_priv_tx_q { 1001 /* cacheline 1 */ 1002 spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES))); 1003 struct txbd8 *tx_bd_base; 1004 struct txbd8 *cur_tx; 1005 unsigned int num_txbdfree; 1006 unsigned short skb_curtx; 1007 unsigned short tx_ring_size; 1008 struct tx_q_stats stats; 1009 struct gfar_priv_grp *grp; 1010 /* cacheline 2 */ 1011 struct net_device *dev; 1012 struct sk_buff **tx_skbuff; 1013 struct txbd8 *dirty_tx; 1014 unsigned short skb_dirtytx; 1015 unsigned short qindex; 1016 /* Configuration info for the coalescing features */ 1017 unsigned int txcoalescing; 1018 unsigned long txic; 1019 dma_addr_t tx_bd_dma_base; 1020 }; 1021 1022 /* 1023 * Per RX queue stats 1024 */ 1025 struct rx_q_stats { 1026 u64 rx_packets; 1027 u64 rx_bytes; 1028 u64 rx_dropped; 1029 }; 1030 1031 struct gfar_rx_buff { 1032 dma_addr_t dma; 1033 struct page *page; 1034 unsigned int page_offset; 1035 }; 1036 1037 /** 1038 * struct gfar_priv_rx_q - per rx queue structure 1039 * @rx_buff: Array of buffer info metadata structs 1040 * @rx_bd_base: First rx buffer descriptor 1041 * @next_to_use: index of the next buffer to be alloc'd 1042 * @next_to_clean: index of the next buffer to be cleaned 1043 * @qindex: index of this queue 1044 * @ndev: back pointer to net_device 1045 * @rx_ring_size: Rx ring size 1046 * @rxcoalescing: enable/disable rx-coalescing 1047 * @rxic: receive interrupt coalescing vlaue 1048 */ 1049 1050 struct gfar_priv_rx_q { 1051 struct gfar_rx_buff *rx_buff __aligned(SMP_CACHE_BYTES); 1052 struct rxbd8 *rx_bd_base; 1053 struct net_device *ndev; 1054 struct device *dev; 1055 u16 rx_ring_size; 1056 u16 qindex; 1057 struct gfar_priv_grp *grp; 1058 u16 next_to_clean; 1059 u16 next_to_use; 1060 u16 next_to_alloc; 1061 struct sk_buff *skb; 1062 struct rx_q_stats stats; 1063 u32 __iomem *rfbptr; 1064 unsigned char rxcoalescing; 1065 unsigned long rxic; 1066 dma_addr_t rx_bd_dma_base; 1067 }; 1068 1069 enum gfar_irqinfo_id { 1070 GFAR_TX = 0, 1071 GFAR_RX = 1, 1072 GFAR_ER = 2, 1073 GFAR_NUM_IRQS = 3 1074 }; 1075 1076 struct gfar_irqinfo { 1077 unsigned int irq; 1078 char name[GFAR_INT_NAME_MAX]; 1079 }; 1080 1081 /** 1082 * struct gfar_priv_grp - per group structure 1083 * @napi: the napi poll function 1084 * @priv: back pointer to the priv structure 1085 * @regs: the ioremapped register space for this group 1086 * @irqinfo: TX/RX/ER irq data for this group 1087 */ 1088 1089 struct gfar_priv_grp { 1090 spinlock_t grplock __aligned(SMP_CACHE_BYTES); 1091 struct napi_struct napi_rx; 1092 struct napi_struct napi_tx; 1093 struct gfar __iomem *regs; 1094 struct gfar_priv_tx_q *tx_queue; 1095 struct gfar_priv_rx_q *rx_queue; 1096 unsigned int tstat; 1097 unsigned int rstat; 1098 1099 struct gfar_private *priv; 1100 unsigned long num_tx_queues; 1101 unsigned long tx_bit_map; 1102 unsigned long num_rx_queues; 1103 unsigned long rx_bit_map; 1104 1105 struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS]; 1106 }; 1107 1108 #define gfar_irq(grp, ID) \ 1109 ((grp)->irqinfo[GFAR_##ID]) 1110 1111 enum gfar_errata { 1112 GFAR_ERRATA_74 = 0x01, 1113 GFAR_ERRATA_76 = 0x02, 1114 GFAR_ERRATA_A002 = 0x04, 1115 GFAR_ERRATA_12 = 0x08, /* a.k.a errata eTSEC49 */ 1116 }; 1117 1118 enum gfar_dev_state { 1119 GFAR_DOWN = 1, 1120 GFAR_RESETTING 1121 }; 1122 1123 /* Struct stolen almost completely (and shamelessly) from the FCC enet source 1124 * (Ok, that's not so true anymore, but there is a family resemblance) 1125 * The GFAR buffer descriptors track the ring buffers. The rx_bd_base 1126 * and tx_bd_base always point to the currently available buffer. 1127 * The dirty_tx tracks the current buffer that is being sent by the 1128 * controller. The cur_tx and dirty_tx are equal under both completely 1129 * empty and completely full conditions. The empty/ready indicator in 1130 * the buffer descriptor determines the actual condition. 1131 */ 1132 struct gfar_private { 1133 struct device *dev; 1134 struct net_device *ndev; 1135 enum gfar_errata errata; 1136 1137 u16 uses_rxfcb; 1138 u16 padding; 1139 u32 device_flags; 1140 1141 /* HW time stamping enabled flag */ 1142 int hwts_rx_en; 1143 int hwts_tx_en; 1144 1145 struct gfar_priv_tx_q *tx_queue[MAX_TX_QS]; 1146 struct gfar_priv_rx_q *rx_queue[MAX_RX_QS]; 1147 struct gfar_priv_grp gfargrp[MAXGROUPS]; 1148 1149 unsigned long state; 1150 1151 unsigned short mode; 1152 unsigned int num_tx_queues; 1153 unsigned int num_rx_queues; 1154 unsigned int num_grps; 1155 int tx_actual_en; 1156 1157 /* Network Statistics */ 1158 struct gfar_extra_stats extra_stats; 1159 struct rmon_overflow rmon_overflow; 1160 1161 /* PHY stuff */ 1162 phy_interface_t interface; 1163 struct device_node *phy_node; 1164 struct device_node *tbi_node; 1165 struct mii_bus *mii_bus; 1166 int oldspeed; 1167 int oldduplex; 1168 int oldlink; 1169 1170 uint32_t msg_enable; 1171 1172 struct work_struct reset_task; 1173 1174 struct platform_device *ofdev; 1175 unsigned char 1176 extended_hash:1, 1177 bd_stash_en:1, 1178 rx_filer_enable:1, 1179 /* Enable priorty based Tx scheduling in Hw */ 1180 prio_sched_en:1, 1181 /* Flow control flags */ 1182 pause_aneg_en:1, 1183 tx_pause_en:1, 1184 rx_pause_en:1; 1185 1186 /* The total tx and rx ring size for the enabled queues */ 1187 unsigned int total_tx_ring_size; 1188 unsigned int total_rx_ring_size; 1189 1190 u32 rqueue; 1191 u32 tqueue; 1192 1193 /* RX per device parameters */ 1194 unsigned int rx_stash_size; 1195 unsigned int rx_stash_index; 1196 1197 u32 cur_filer_idx; 1198 1199 /* RX queue filer rule set*/ 1200 struct ethtool_rx_list rx_list; 1201 struct mutex rx_queue_access; 1202 1203 /* Hash registers and their width */ 1204 u32 __iomem *hash_regs[16]; 1205 int hash_width; 1206 1207 /* wake-on-lan settings */ 1208 u16 wol_opts; 1209 u16 wol_supported; 1210 1211 /*Filer table*/ 1212 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1]; 1213 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1]; 1214 }; 1215 1216 1217 static inline int gfar_has_errata(struct gfar_private *priv, 1218 enum gfar_errata err) 1219 { 1220 return priv->errata & err; 1221 } 1222 1223 static inline u32 gfar_read(unsigned __iomem *addr) 1224 { 1225 u32 val; 1226 val = ioread32be(addr); 1227 return val; 1228 } 1229 1230 static inline void gfar_write(unsigned __iomem *addr, u32 val) 1231 { 1232 iowrite32be(val, addr); 1233 } 1234 1235 static inline void gfar_write_filer(struct gfar_private *priv, 1236 unsigned int far, unsigned int fcr, unsigned int fpr) 1237 { 1238 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1239 1240 gfar_write(®s->rqfar, far); 1241 gfar_write(®s->rqfcr, fcr); 1242 gfar_write(®s->rqfpr, fpr); 1243 } 1244 1245 static inline void gfar_read_filer(struct gfar_private *priv, 1246 unsigned int far, unsigned int *fcr, unsigned int *fpr) 1247 { 1248 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1249 1250 gfar_write(®s->rqfar, far); 1251 *fcr = gfar_read(®s->rqfcr); 1252 *fpr = gfar_read(®s->rqfpr); 1253 } 1254 1255 static inline void gfar_write_isrg(struct gfar_private *priv) 1256 { 1257 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1258 u32 __iomem *baddr = ®s->isrg0; 1259 u32 isrg = 0; 1260 int grp_idx, i; 1261 1262 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { 1263 struct gfar_priv_grp *grp = &priv->gfargrp[grp_idx]; 1264 1265 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) { 1266 isrg |= (ISRG_RR0 >> i); 1267 } 1268 1269 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) { 1270 isrg |= (ISRG_TR0 >> i); 1271 } 1272 1273 gfar_write(baddr, isrg); 1274 1275 baddr++; 1276 isrg = 0; 1277 } 1278 } 1279 1280 static inline int gfar_is_dma_stopped(struct gfar_private *priv) 1281 { 1282 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1283 1284 return ((gfar_read(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) == 1285 (IEVENT_GRSC | IEVENT_GTSC)); 1286 } 1287 1288 static inline int gfar_is_rx_dma_stopped(struct gfar_private *priv) 1289 { 1290 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1291 1292 return gfar_read(®s->ievent) & IEVENT_GRSC; 1293 } 1294 1295 static inline void gfar_wmb(void) 1296 { 1297 #if defined(CONFIG_PPC) 1298 /* The powerpc-specific eieio() is used, as wmb() has too strong 1299 * semantics (it requires synchronization between cacheable and 1300 * uncacheable mappings, which eieio() doesn't provide and which we 1301 * don't need), thus requiring a more expensive sync instruction. At 1302 * some point, the set of architecture-independent barrier functions 1303 * should be expanded to include weaker barriers. 1304 */ 1305 eieio(); 1306 #else 1307 wmb(); /* order write acesses for BD (or FCB) fields */ 1308 #endif 1309 } 1310 1311 static inline void gfar_clear_txbd_status(struct txbd8 *bdp) 1312 { 1313 u32 lstatus = be32_to_cpu(bdp->lstatus); 1314 1315 lstatus &= BD_LFLAG(TXBD_WRAP); 1316 bdp->lstatus = cpu_to_be32(lstatus); 1317 } 1318 1319 static inline int gfar_rxbd_unused(struct gfar_priv_rx_q *rxq) 1320 { 1321 if (rxq->next_to_clean > rxq->next_to_use) 1322 return rxq->next_to_clean - rxq->next_to_use - 1; 1323 1324 return rxq->rx_ring_size + rxq->next_to_clean - rxq->next_to_use - 1; 1325 } 1326 1327 static inline u32 gfar_rxbd_dma_lastfree(struct gfar_priv_rx_q *rxq) 1328 { 1329 struct rxbd8 *bdp; 1330 u32 bdp_dma; 1331 int i; 1332 1333 i = rxq->next_to_use ? rxq->next_to_use - 1 : rxq->rx_ring_size - 1; 1334 bdp = &rxq->rx_bd_base[i]; 1335 bdp_dma = lower_32_bits(rxq->rx_bd_dma_base); 1336 bdp_dma += (uintptr_t)bdp - (uintptr_t)rxq->rx_bd_base; 1337 1338 return bdp_dma; 1339 } 1340 1341 int startup_gfar(struct net_device *dev); 1342 void stop_gfar(struct net_device *dev); 1343 void gfar_mac_reset(struct gfar_private *priv); 1344 int gfar_set_features(struct net_device *dev, netdev_features_t features); 1345 1346 extern const struct ethtool_ops gfar_ethtool_ops; 1347 1348 #define MAX_FILER_CACHE_IDX (2*(MAX_FILER_IDX)) 1349 1350 #define RQFCR_PID_PRI_MASK 0xFFFFFFF8 1351 #define RQFCR_PID_L4P_MASK 0xFFFFFF00 1352 #define RQFCR_PID_VID_MASK 0xFFFFF000 1353 #define RQFCR_PID_PORT_MASK 0xFFFF0000 1354 #define RQFCR_PID_MAC_MASK 0xFF000000 1355 1356 /* Represents a receive filer table entry */ 1357 struct gfar_filer_entry { 1358 u32 ctrl; 1359 u32 prop; 1360 }; 1361 1362 1363 /* The 20 additional entries are a shadow for one extra element */ 1364 struct filer_table { 1365 u32 index; 1366 struct gfar_filer_entry fe[MAX_FILER_CACHE_IDX + 20]; 1367 }; 1368 1369 #endif /* __GIANFAR_H */ 1370