1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* drivers/net/ethernet/freescale/gianfar.c 3 * 4 * Gianfar Ethernet Driver 5 * This driver is designed for the non-CPM ethernet controllers 6 * on the 85xx and 83xx family of integrated processors 7 * Based on 8260_io/fcc_enet.c 8 * 9 * Author: Andy Fleming 10 * Maintainer: Kumar Gala 11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 12 * 13 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc. 14 * Copyright 2007 MontaVista Software, Inc. 15 * 16 * Gianfar: AKA Lambda Draconis, "Dragon" 17 * RA 11 31 24.2 18 * Dec +69 19 52 19 * V 3.84 20 * B-V +1.62 21 * 22 * Theory of operation 23 * 24 * The driver is initialized through of_device. Configuration information 25 * is therefore conveyed through an OF-style device tree. 26 * 27 * The Gianfar Ethernet Controller uses a ring of buffer 28 * descriptors. The beginning is indicated by a register 29 * pointing to the physical address of the start of the ring. 30 * The end is determined by a "wrap" bit being set in the 31 * last descriptor of the ring. 32 * 33 * When a packet is received, the RXF bit in the 34 * IEVENT register is set, triggering an interrupt when the 35 * corresponding bit in the IMASK register is also set (if 36 * interrupt coalescing is active, then the interrupt may not 37 * happen immediately, but will wait until either a set number 38 * of frames or amount of time have passed). In NAPI, the 39 * interrupt handler will signal there is work to be done, and 40 * exit. This method will start at the last known empty 41 * descriptor, and process every subsequent descriptor until there 42 * are none left with data (NAPI will stop after a set number of 43 * packets to give time to other tasks, but will eventually 44 * process all the packets). The data arrives inside a 45 * pre-allocated skb, and so after the skb is passed up to the 46 * stack, a new skb must be allocated, and the address field in 47 * the buffer descriptor must be updated to indicate this new 48 * skb. 49 * 50 * When the kernel requests that a packet be transmitted, the 51 * driver starts where it left off last time, and points the 52 * descriptor at the buffer which was passed in. The driver 53 * then informs the DMA engine that there are packets ready to 54 * be transmitted. Once the controller is finished transmitting 55 * the packet, an interrupt may be triggered (under the same 56 * conditions as for reception, but depending on the TXF bit). 57 * The driver then cleans up the buffer. 58 */ 59 60 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 61 62 #include <linux/kernel.h> 63 #include <linux/platform_device.h> 64 #include <linux/string.h> 65 #include <linux/errno.h> 66 #include <linux/unistd.h> 67 #include <linux/slab.h> 68 #include <linux/interrupt.h> 69 #include <linux/delay.h> 70 #include <linux/netdevice.h> 71 #include <linux/etherdevice.h> 72 #include <linux/skbuff.h> 73 #include <linux/if_vlan.h> 74 #include <linux/spinlock.h> 75 #include <linux/mm.h> 76 #include <linux/of_address.h> 77 #include <linux/of_irq.h> 78 #include <linux/of_mdio.h> 79 #include <linux/ip.h> 80 #include <linux/tcp.h> 81 #include <linux/udp.h> 82 #include <linux/in.h> 83 #include <linux/net_tstamp.h> 84 85 #include <asm/io.h> 86 #ifdef CONFIG_PPC 87 #include <asm/reg.h> 88 #include <asm/mpc85xx.h> 89 #endif 90 #include <asm/irq.h> 91 #include <linux/uaccess.h> 92 #include <linux/module.h> 93 #include <linux/dma-mapping.h> 94 #include <linux/crc32.h> 95 #include <linux/mii.h> 96 #include <linux/phy.h> 97 #include <linux/phy_fixed.h> 98 #include <linux/of.h> 99 #include <linux/of_net.h> 100 101 #include "gianfar.h" 102 103 #define TX_TIMEOUT (5*HZ) 104 105 MODULE_AUTHOR("Freescale Semiconductor, Inc"); 106 MODULE_DESCRIPTION("Gianfar Ethernet Driver"); 107 MODULE_LICENSE("GPL"); 108 109 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, 110 dma_addr_t buf) 111 { 112 u32 lstatus; 113 114 bdp->bufPtr = cpu_to_be32(buf); 115 116 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); 117 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) 118 lstatus |= BD_LFLAG(RXBD_WRAP); 119 120 gfar_wmb(); 121 122 bdp->lstatus = cpu_to_be32(lstatus); 123 } 124 125 static void gfar_init_tx_rx_base(struct gfar_private *priv) 126 { 127 struct gfar __iomem *regs = priv->gfargrp[0].regs; 128 u32 __iomem *baddr; 129 int i; 130 131 baddr = ®s->tbase0; 132 for (i = 0; i < priv->num_tx_queues; i++) { 133 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); 134 baddr += 2; 135 } 136 137 baddr = ®s->rbase0; 138 for (i = 0; i < priv->num_rx_queues; i++) { 139 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); 140 baddr += 2; 141 } 142 } 143 144 static void gfar_init_rqprm(struct gfar_private *priv) 145 { 146 struct gfar __iomem *regs = priv->gfargrp[0].regs; 147 u32 __iomem *baddr; 148 int i; 149 150 baddr = ®s->rqprm0; 151 for (i = 0; i < priv->num_rx_queues; i++) { 152 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size | 153 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT)); 154 baddr++; 155 } 156 } 157 158 static void gfar_rx_offload_en(struct gfar_private *priv) 159 { 160 /* set this when rx hw offload (TOE) functions are being used */ 161 priv->uses_rxfcb = 0; 162 163 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) 164 priv->uses_rxfcb = 1; 165 166 if (priv->hwts_rx_en || priv->rx_filer_enable) 167 priv->uses_rxfcb = 1; 168 } 169 170 static void gfar_mac_rx_config(struct gfar_private *priv) 171 { 172 struct gfar __iomem *regs = priv->gfargrp[0].regs; 173 u32 rctrl = 0; 174 175 if (priv->rx_filer_enable) { 176 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT; 177 /* Program the RIR0 reg with the required distribution */ 178 gfar_write(®s->rir0, DEFAULT_2RXQ_RIR0); 179 } 180 181 /* Restore PROMISC mode */ 182 if (priv->ndev->flags & IFF_PROMISC) 183 rctrl |= RCTRL_PROM; 184 185 if (priv->ndev->features & NETIF_F_RXCSUM) 186 rctrl |= RCTRL_CHECKSUMMING; 187 188 if (priv->extended_hash) 189 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN; 190 191 if (priv->padding) { 192 rctrl &= ~RCTRL_PAL_MASK; 193 rctrl |= RCTRL_PADDING(priv->padding); 194 } 195 196 /* Enable HW time stamping if requested from user space */ 197 if (priv->hwts_rx_en) 198 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; 199 200 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) 201 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; 202 203 /* Clear the LFC bit */ 204 gfar_write(®s->rctrl, rctrl); 205 /* Init flow control threshold values */ 206 gfar_init_rqprm(priv); 207 gfar_write(®s->ptv, DEFAULT_LFC_PTVVAL); 208 rctrl |= RCTRL_LFC; 209 210 /* Init rctrl based on our settings */ 211 gfar_write(®s->rctrl, rctrl); 212 } 213 214 static void gfar_mac_tx_config(struct gfar_private *priv) 215 { 216 struct gfar __iomem *regs = priv->gfargrp[0].regs; 217 u32 tctrl = 0; 218 219 if (priv->ndev->features & NETIF_F_IP_CSUM) 220 tctrl |= TCTRL_INIT_CSUM; 221 222 if (priv->prio_sched_en) 223 tctrl |= TCTRL_TXSCHED_PRIO; 224 else { 225 tctrl |= TCTRL_TXSCHED_WRRS; 226 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT); 227 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT); 228 } 229 230 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX) 231 tctrl |= TCTRL_VLINS; 232 233 gfar_write(®s->tctrl, tctrl); 234 } 235 236 static void gfar_configure_coalescing(struct gfar_private *priv, 237 unsigned long tx_mask, unsigned long rx_mask) 238 { 239 struct gfar __iomem *regs = priv->gfargrp[0].regs; 240 u32 __iomem *baddr; 241 242 if (priv->mode == MQ_MG_MODE) { 243 int i = 0; 244 245 baddr = ®s->txic0; 246 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { 247 gfar_write(baddr + i, 0); 248 if (likely(priv->tx_queue[i]->txcoalescing)) 249 gfar_write(baddr + i, priv->tx_queue[i]->txic); 250 } 251 252 baddr = ®s->rxic0; 253 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { 254 gfar_write(baddr + i, 0); 255 if (likely(priv->rx_queue[i]->rxcoalescing)) 256 gfar_write(baddr + i, priv->rx_queue[i]->rxic); 257 } 258 } else { 259 /* Backward compatible case -- even if we enable 260 * multiple queues, there's only single reg to program 261 */ 262 gfar_write(®s->txic, 0); 263 if (likely(priv->tx_queue[0]->txcoalescing)) 264 gfar_write(®s->txic, priv->tx_queue[0]->txic); 265 266 gfar_write(®s->rxic, 0); 267 if (unlikely(priv->rx_queue[0]->rxcoalescing)) 268 gfar_write(®s->rxic, priv->rx_queue[0]->rxic); 269 } 270 } 271 272 static void gfar_configure_coalescing_all(struct gfar_private *priv) 273 { 274 gfar_configure_coalescing(priv, 0xFF, 0xFF); 275 } 276 277 static void gfar_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 278 { 279 struct gfar_private *priv = netdev_priv(dev); 280 int i; 281 282 for (i = 0; i < priv->num_rx_queues; i++) { 283 stats->rx_packets += priv->rx_queue[i]->stats.rx_packets; 284 stats->rx_bytes += priv->rx_queue[i]->stats.rx_bytes; 285 stats->rx_dropped += priv->rx_queue[i]->stats.rx_dropped; 286 } 287 288 for (i = 0; i < priv->num_tx_queues; i++) { 289 stats->tx_bytes += priv->tx_queue[i]->stats.tx_bytes; 290 stats->tx_packets += priv->tx_queue[i]->stats.tx_packets; 291 } 292 293 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { 294 struct rmon_mib __iomem *rmon = &priv->gfargrp[0].regs->rmon; 295 unsigned long flags; 296 u32 rdrp, car, car_before; 297 u64 rdrp_offset; 298 299 spin_lock_irqsave(&priv->rmon_overflow.lock, flags); 300 car = gfar_read(&rmon->car1) & CAR1_C1RDR; 301 do { 302 car_before = car; 303 rdrp = gfar_read(&rmon->rdrp); 304 car = gfar_read(&rmon->car1) & CAR1_C1RDR; 305 } while (car != car_before); 306 if (car) { 307 priv->rmon_overflow.rdrp++; 308 gfar_write(&rmon->car1, car); 309 } 310 rdrp_offset = priv->rmon_overflow.rdrp; 311 spin_unlock_irqrestore(&priv->rmon_overflow.lock, flags); 312 313 stats->rx_missed_errors = rdrp + (rdrp_offset << 16); 314 } 315 } 316 317 /* Set the appropriate hash bit for the given addr */ 318 /* The algorithm works like so: 319 * 1) Take the Destination Address (ie the multicast address), and 320 * do a CRC on it (little endian), and reverse the bits of the 321 * result. 322 * 2) Use the 8 most significant bits as a hash into a 256-entry 323 * table. The table is controlled through 8 32-bit registers: 324 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 325 * gaddr7. This means that the 3 most significant bits in the 326 * hash index which gaddr register to use, and the 5 other bits 327 * indicate which bit (assuming an IBM numbering scheme, which 328 * for PowerPC (tm) is usually the case) in the register holds 329 * the entry. 330 */ 331 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) 332 { 333 u32 tempval; 334 struct gfar_private *priv = netdev_priv(dev); 335 u32 result = ether_crc(ETH_ALEN, addr); 336 int width = priv->hash_width; 337 u8 whichbit = (result >> (32 - width)) & 0x1f; 338 u8 whichreg = result >> (32 - width + 5); 339 u32 value = (1 << (31-whichbit)); 340 341 tempval = gfar_read(priv->hash_regs[whichreg]); 342 tempval |= value; 343 gfar_write(priv->hash_regs[whichreg], tempval); 344 } 345 346 /* There are multiple MAC Address register pairs on some controllers 347 * This function sets the numth pair to a given address 348 */ 349 static void gfar_set_mac_for_addr(struct net_device *dev, int num, 350 const u8 *addr) 351 { 352 struct gfar_private *priv = netdev_priv(dev); 353 struct gfar __iomem *regs = priv->gfargrp[0].regs; 354 u32 tempval; 355 u32 __iomem *macptr = ®s->macstnaddr1; 356 357 macptr += num*2; 358 359 /* For a station address of 0x12345678ABCD in transmission 360 * order (BE), MACnADDR1 is set to 0xCDAB7856 and 361 * MACnADDR2 is set to 0x34120000. 362 */ 363 tempval = (addr[5] << 24) | (addr[4] << 16) | 364 (addr[3] << 8) | addr[2]; 365 366 gfar_write(macptr, tempval); 367 368 tempval = (addr[1] << 24) | (addr[0] << 16); 369 370 gfar_write(macptr+1, tempval); 371 } 372 373 static int gfar_set_mac_addr(struct net_device *dev, void *p) 374 { 375 int ret; 376 377 ret = eth_mac_addr(dev, p); 378 if (ret) 379 return ret; 380 381 gfar_set_mac_for_addr(dev, 0, dev->dev_addr); 382 383 return 0; 384 } 385 386 static void gfar_ints_disable(struct gfar_private *priv) 387 { 388 int i; 389 for (i = 0; i < priv->num_grps; i++) { 390 struct gfar __iomem *regs = priv->gfargrp[i].regs; 391 /* Clear IEVENT */ 392 gfar_write(®s->ievent, IEVENT_INIT_CLEAR); 393 394 /* Initialize IMASK */ 395 gfar_write(®s->imask, IMASK_INIT_CLEAR); 396 } 397 } 398 399 static void gfar_ints_enable(struct gfar_private *priv) 400 { 401 int i; 402 for (i = 0; i < priv->num_grps; i++) { 403 struct gfar __iomem *regs = priv->gfargrp[i].regs; 404 /* Unmask the interrupts we look for */ 405 gfar_write(®s->imask, 406 IMASK_DEFAULT | priv->rmon_overflow.imask); 407 } 408 } 409 410 static int gfar_alloc_tx_queues(struct gfar_private *priv) 411 { 412 int i; 413 414 for (i = 0; i < priv->num_tx_queues; i++) { 415 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q), 416 GFP_KERNEL); 417 if (!priv->tx_queue[i]) 418 return -ENOMEM; 419 420 priv->tx_queue[i]->tx_skbuff = NULL; 421 priv->tx_queue[i]->qindex = i; 422 priv->tx_queue[i]->dev = priv->ndev; 423 spin_lock_init(&(priv->tx_queue[i]->txlock)); 424 } 425 return 0; 426 } 427 428 static int gfar_alloc_rx_queues(struct gfar_private *priv) 429 { 430 int i; 431 432 for (i = 0; i < priv->num_rx_queues; i++) { 433 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q), 434 GFP_KERNEL); 435 if (!priv->rx_queue[i]) 436 return -ENOMEM; 437 438 priv->rx_queue[i]->qindex = i; 439 priv->rx_queue[i]->ndev = priv->ndev; 440 } 441 return 0; 442 } 443 444 static void gfar_free_tx_queues(struct gfar_private *priv) 445 { 446 int i; 447 448 for (i = 0; i < priv->num_tx_queues; i++) 449 kfree(priv->tx_queue[i]); 450 } 451 452 static void gfar_free_rx_queues(struct gfar_private *priv) 453 { 454 int i; 455 456 for (i = 0; i < priv->num_rx_queues; i++) 457 kfree(priv->rx_queue[i]); 458 } 459 460 static void unmap_group_regs(struct gfar_private *priv) 461 { 462 int i; 463 464 for (i = 0; i < MAXGROUPS; i++) 465 if (priv->gfargrp[i].regs) 466 iounmap(priv->gfargrp[i].regs); 467 } 468 469 static void free_gfar_dev(struct gfar_private *priv) 470 { 471 int i, j; 472 473 for (i = 0; i < priv->num_grps; i++) 474 for (j = 0; j < GFAR_NUM_IRQS; j++) { 475 kfree(priv->gfargrp[i].irqinfo[j]); 476 priv->gfargrp[i].irqinfo[j] = NULL; 477 } 478 479 free_netdev(priv->ndev); 480 } 481 482 static void disable_napi(struct gfar_private *priv) 483 { 484 int i; 485 486 for (i = 0; i < priv->num_grps; i++) { 487 napi_disable(&priv->gfargrp[i].napi_rx); 488 napi_disable(&priv->gfargrp[i].napi_tx); 489 } 490 } 491 492 static void enable_napi(struct gfar_private *priv) 493 { 494 int i; 495 496 for (i = 0; i < priv->num_grps; i++) { 497 napi_enable(&priv->gfargrp[i].napi_rx); 498 napi_enable(&priv->gfargrp[i].napi_tx); 499 } 500 } 501 502 static int gfar_parse_group(struct device_node *np, 503 struct gfar_private *priv, const char *model) 504 { 505 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps]; 506 int i; 507 508 for (i = 0; i < GFAR_NUM_IRQS; i++) { 509 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo), 510 GFP_KERNEL); 511 if (!grp->irqinfo[i]) 512 return -ENOMEM; 513 } 514 515 grp->regs = of_iomap(np, 0); 516 if (!grp->regs) 517 return -ENOMEM; 518 519 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0); 520 521 /* If we aren't the FEC we have multiple interrupts */ 522 if (model && strcasecmp(model, "FEC")) { 523 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1); 524 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2); 525 if (!gfar_irq(grp, TX)->irq || 526 !gfar_irq(grp, RX)->irq || 527 !gfar_irq(grp, ER)->irq) 528 return -EINVAL; 529 } 530 531 grp->priv = priv; 532 spin_lock_init(&grp->grplock); 533 if (priv->mode == MQ_MG_MODE) { 534 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */ 535 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps); 536 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps); 537 } else { 538 grp->rx_bit_map = 0xFF; 539 grp->tx_bit_map = 0xFF; 540 } 541 542 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses 543 * right to left, so we need to revert the 8 bits to get the q index 544 */ 545 grp->rx_bit_map = bitrev8(grp->rx_bit_map); 546 grp->tx_bit_map = bitrev8(grp->tx_bit_map); 547 548 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, 549 * also assign queues to groups 550 */ 551 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) { 552 if (!grp->rx_queue) 553 grp->rx_queue = priv->rx_queue[i]; 554 grp->num_rx_queues++; 555 grp->rstat |= (RSTAT_CLEAR_RHALT >> i); 556 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i); 557 priv->rx_queue[i]->grp = grp; 558 } 559 560 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) { 561 if (!grp->tx_queue) 562 grp->tx_queue = priv->tx_queue[i]; 563 grp->num_tx_queues++; 564 grp->tstat |= (TSTAT_CLEAR_THALT >> i); 565 priv->tqueue |= (TQUEUE_EN0 >> i); 566 priv->tx_queue[i]->grp = grp; 567 } 568 569 priv->num_grps++; 570 571 return 0; 572 } 573 574 static int gfar_of_group_count(struct device_node *np) 575 { 576 struct device_node *child; 577 int num = 0; 578 579 for_each_available_child_of_node(np, child) 580 if (of_node_name_eq(child, "queue-group")) 581 num++; 582 583 return num; 584 } 585 586 /* Reads the controller's registers to determine what interface 587 * connects it to the PHY. 588 */ 589 static phy_interface_t gfar_get_interface(struct net_device *dev) 590 { 591 struct gfar_private *priv = netdev_priv(dev); 592 struct gfar __iomem *regs = priv->gfargrp[0].regs; 593 u32 ecntrl; 594 595 ecntrl = gfar_read(®s->ecntrl); 596 597 if (ecntrl & ECNTRL_SGMII_MODE) 598 return PHY_INTERFACE_MODE_SGMII; 599 600 if (ecntrl & ECNTRL_TBI_MODE) { 601 if (ecntrl & ECNTRL_REDUCED_MODE) 602 return PHY_INTERFACE_MODE_RTBI; 603 else 604 return PHY_INTERFACE_MODE_TBI; 605 } 606 607 if (ecntrl & ECNTRL_REDUCED_MODE) { 608 if (ecntrl & ECNTRL_REDUCED_MII_MODE) { 609 return PHY_INTERFACE_MODE_RMII; 610 } 611 else { 612 phy_interface_t interface = priv->interface; 613 614 /* This isn't autodetected right now, so it must 615 * be set by the device tree or platform code. 616 */ 617 if (interface == PHY_INTERFACE_MODE_RGMII_ID) 618 return PHY_INTERFACE_MODE_RGMII_ID; 619 620 return PHY_INTERFACE_MODE_RGMII; 621 } 622 } 623 624 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) 625 return PHY_INTERFACE_MODE_GMII; 626 627 return PHY_INTERFACE_MODE_MII; 628 } 629 630 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) 631 { 632 const char *model; 633 int err = 0, i; 634 phy_interface_t interface; 635 struct net_device *dev = NULL; 636 struct gfar_private *priv = NULL; 637 struct device_node *np = ofdev->dev.of_node; 638 struct device_node *child = NULL; 639 u32 stash_len = 0; 640 u32 stash_idx = 0; 641 unsigned int num_tx_qs, num_rx_qs; 642 unsigned short mode; 643 644 if (!np) 645 return -ENODEV; 646 647 if (of_device_is_compatible(np, "fsl,etsec2")) 648 mode = MQ_MG_MODE; 649 else 650 mode = SQ_SG_MODE; 651 652 if (mode == SQ_SG_MODE) { 653 num_tx_qs = 1; 654 num_rx_qs = 1; 655 } else { /* MQ_MG_MODE */ 656 /* get the actual number of supported groups */ 657 unsigned int num_grps = gfar_of_group_count(np); 658 659 if (num_grps == 0 || num_grps > MAXGROUPS) { 660 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n", 661 num_grps); 662 pr_err("Cannot do alloc_etherdev, aborting\n"); 663 return -EINVAL; 664 } 665 666 num_tx_qs = num_grps; /* one txq per int group */ 667 num_rx_qs = num_grps; /* one rxq per int group */ 668 } 669 670 if (num_tx_qs > MAX_TX_QS) { 671 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", 672 num_tx_qs, MAX_TX_QS); 673 pr_err("Cannot do alloc_etherdev, aborting\n"); 674 return -EINVAL; 675 } 676 677 if (num_rx_qs > MAX_RX_QS) { 678 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", 679 num_rx_qs, MAX_RX_QS); 680 pr_err("Cannot do alloc_etherdev, aborting\n"); 681 return -EINVAL; 682 } 683 684 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); 685 dev = *pdev; 686 if (NULL == dev) 687 return -ENOMEM; 688 689 priv = netdev_priv(dev); 690 priv->ndev = dev; 691 692 priv->mode = mode; 693 694 priv->num_tx_queues = num_tx_qs; 695 netif_set_real_num_rx_queues(dev, num_rx_qs); 696 priv->num_rx_queues = num_rx_qs; 697 698 err = gfar_alloc_tx_queues(priv); 699 if (err) 700 goto tx_alloc_failed; 701 702 err = gfar_alloc_rx_queues(priv); 703 if (err) 704 goto rx_alloc_failed; 705 706 err = of_property_read_string(np, "model", &model); 707 if (err) { 708 pr_err("Device model property missing, aborting\n"); 709 goto rx_alloc_failed; 710 } 711 712 /* Init Rx queue filer rule set linked list */ 713 INIT_LIST_HEAD(&priv->rx_list.list); 714 priv->rx_list.count = 0; 715 mutex_init(&priv->rx_queue_access); 716 717 for (i = 0; i < MAXGROUPS; i++) 718 priv->gfargrp[i].regs = NULL; 719 720 /* Parse and initialize group specific information */ 721 if (priv->mode == MQ_MG_MODE) { 722 for_each_available_child_of_node(np, child) { 723 if (!of_node_name_eq(child, "queue-group")) 724 continue; 725 726 err = gfar_parse_group(child, priv, model); 727 if (err) { 728 of_node_put(child); 729 goto err_grp_init; 730 } 731 } 732 } else { /* SQ_SG_MODE */ 733 err = gfar_parse_group(np, priv, model); 734 if (err) 735 goto err_grp_init; 736 } 737 738 if (of_property_read_bool(np, "bd-stash")) { 739 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; 740 priv->bd_stash_en = 1; 741 } 742 743 err = of_property_read_u32(np, "rx-stash-len", &stash_len); 744 745 if (err == 0) 746 priv->rx_stash_size = stash_len; 747 748 err = of_property_read_u32(np, "rx-stash-idx", &stash_idx); 749 750 if (err == 0) 751 priv->rx_stash_index = stash_idx; 752 753 if (stash_len || stash_idx) 754 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; 755 756 err = of_get_ethdev_address(np, dev); 757 if (err == -EPROBE_DEFER) 758 goto err_grp_init; 759 if (err) { 760 eth_hw_addr_random(dev); 761 dev_info(&ofdev->dev, "Using random MAC address: %pM\n", dev->dev_addr); 762 } 763 764 if (model && !strcasecmp(model, "TSEC")) 765 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT | 766 FSL_GIANFAR_DEV_HAS_COALESCE | 767 FSL_GIANFAR_DEV_HAS_RMON | 768 FSL_GIANFAR_DEV_HAS_MULTI_INTR; 769 770 if (model && !strcasecmp(model, "eTSEC")) 771 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT | 772 FSL_GIANFAR_DEV_HAS_COALESCE | 773 FSL_GIANFAR_DEV_HAS_RMON | 774 FSL_GIANFAR_DEV_HAS_MULTI_INTR | 775 FSL_GIANFAR_DEV_HAS_CSUM | 776 FSL_GIANFAR_DEV_HAS_VLAN | 777 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | 778 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | 779 FSL_GIANFAR_DEV_HAS_TIMER | 780 FSL_GIANFAR_DEV_HAS_RX_FILER; 781 782 /* Use PHY connection type from the DT node if one is specified there. 783 * rgmii-id really needs to be specified. Other types can be 784 * detected by hardware 785 */ 786 err = of_get_phy_mode(np, &interface); 787 if (!err) 788 priv->interface = interface; 789 else 790 priv->interface = gfar_get_interface(dev); 791 792 if (of_property_read_bool(np, "fsl,magic-packet")) 793 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; 794 795 if (of_property_read_bool(np, "fsl,wake-on-filer")) 796 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER; 797 798 priv->phy_node = of_parse_phandle(np, "phy-handle", 0); 799 800 /* In the case of a fixed PHY, the DT node associated 801 * to the PHY is the Ethernet MAC DT node. 802 */ 803 if (!priv->phy_node && of_phy_is_fixed_link(np)) { 804 err = of_phy_register_fixed_link(np); 805 if (err) 806 goto err_grp_init; 807 808 priv->phy_node = of_node_get(np); 809 } 810 811 /* Find the TBI PHY. If it's not there, we don't support SGMII */ 812 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); 813 814 return 0; 815 816 err_grp_init: 817 unmap_group_regs(priv); 818 rx_alloc_failed: 819 gfar_free_rx_queues(priv); 820 tx_alloc_failed: 821 gfar_free_tx_queues(priv); 822 free_gfar_dev(priv); 823 return err; 824 } 825 826 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, 827 u32 class) 828 { 829 u32 rqfpr = FPR_FILER_MASK; 830 u32 rqfcr = 0x0; 831 832 rqfar--; 833 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; 834 priv->ftp_rqfpr[rqfar] = rqfpr; 835 priv->ftp_rqfcr[rqfar] = rqfcr; 836 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 837 838 rqfar--; 839 rqfcr = RQFCR_CMP_NOMATCH; 840 priv->ftp_rqfpr[rqfar] = rqfpr; 841 priv->ftp_rqfcr[rqfar] = rqfcr; 842 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 843 844 rqfar--; 845 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; 846 rqfpr = class; 847 priv->ftp_rqfcr[rqfar] = rqfcr; 848 priv->ftp_rqfpr[rqfar] = rqfpr; 849 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 850 851 rqfar--; 852 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; 853 rqfpr = class; 854 priv->ftp_rqfcr[rqfar] = rqfcr; 855 priv->ftp_rqfpr[rqfar] = rqfpr; 856 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 857 858 return rqfar; 859 } 860 861 static void gfar_init_filer_table(struct gfar_private *priv) 862 { 863 int i = 0x0; 864 u32 rqfar = MAX_FILER_IDX; 865 u32 rqfcr = 0x0; 866 u32 rqfpr = FPR_FILER_MASK; 867 868 /* Default rule */ 869 rqfcr = RQFCR_CMP_MATCH; 870 priv->ftp_rqfcr[rqfar] = rqfcr; 871 priv->ftp_rqfpr[rqfar] = rqfpr; 872 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 873 874 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); 875 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); 876 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); 877 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); 878 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); 879 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); 880 881 /* cur_filer_idx indicated the first non-masked rule */ 882 priv->cur_filer_idx = rqfar; 883 884 /* Rest are masked rules */ 885 rqfcr = RQFCR_CMP_NOMATCH; 886 for (i = 0; i < rqfar; i++) { 887 priv->ftp_rqfcr[i] = rqfcr; 888 priv->ftp_rqfpr[i] = rqfpr; 889 gfar_write_filer(priv, i, rqfcr, rqfpr); 890 } 891 } 892 893 #ifdef CONFIG_PPC 894 static void __gfar_detect_errata_83xx(struct gfar_private *priv) 895 { 896 unsigned int pvr = mfspr(SPRN_PVR); 897 unsigned int svr = mfspr(SPRN_SVR); 898 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */ 899 unsigned int rev = svr & 0xffff; 900 901 /* MPC8313 Rev 2.0 and higher; All MPC837x */ 902 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) || 903 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) 904 priv->errata |= GFAR_ERRATA_74; 905 906 /* MPC8313 and MPC837x all rev */ 907 if ((pvr == 0x80850010 && mod == 0x80b0) || 908 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) 909 priv->errata |= GFAR_ERRATA_76; 910 911 /* MPC8313 Rev < 2.0 */ 912 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) 913 priv->errata |= GFAR_ERRATA_12; 914 } 915 916 static void __gfar_detect_errata_85xx(struct gfar_private *priv) 917 { 918 unsigned int svr = mfspr(SPRN_SVR); 919 920 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20)) 921 priv->errata |= GFAR_ERRATA_12; 922 /* P2020/P1010 Rev 1; MPC8548 Rev 2 */ 923 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) || 924 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) || 925 ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31))) 926 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */ 927 } 928 #endif 929 930 static void gfar_detect_errata(struct gfar_private *priv) 931 { 932 struct device *dev = &priv->ofdev->dev; 933 934 /* no plans to fix */ 935 priv->errata |= GFAR_ERRATA_A002; 936 937 #ifdef CONFIG_PPC 938 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)) 939 __gfar_detect_errata_85xx(priv); 940 else /* non-mpc85xx parts, i.e. e300 core based */ 941 __gfar_detect_errata_83xx(priv); 942 #endif 943 944 if (priv->errata) 945 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n", 946 priv->errata); 947 } 948 949 static void gfar_init_addr_hash_table(struct gfar_private *priv) 950 { 951 struct gfar __iomem *regs = priv->gfargrp[0].regs; 952 953 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { 954 priv->extended_hash = 1; 955 priv->hash_width = 9; 956 957 priv->hash_regs[0] = ®s->igaddr0; 958 priv->hash_regs[1] = ®s->igaddr1; 959 priv->hash_regs[2] = ®s->igaddr2; 960 priv->hash_regs[3] = ®s->igaddr3; 961 priv->hash_regs[4] = ®s->igaddr4; 962 priv->hash_regs[5] = ®s->igaddr5; 963 priv->hash_regs[6] = ®s->igaddr6; 964 priv->hash_regs[7] = ®s->igaddr7; 965 priv->hash_regs[8] = ®s->gaddr0; 966 priv->hash_regs[9] = ®s->gaddr1; 967 priv->hash_regs[10] = ®s->gaddr2; 968 priv->hash_regs[11] = ®s->gaddr3; 969 priv->hash_regs[12] = ®s->gaddr4; 970 priv->hash_regs[13] = ®s->gaddr5; 971 priv->hash_regs[14] = ®s->gaddr6; 972 priv->hash_regs[15] = ®s->gaddr7; 973 974 } else { 975 priv->extended_hash = 0; 976 priv->hash_width = 8; 977 978 priv->hash_regs[0] = ®s->gaddr0; 979 priv->hash_regs[1] = ®s->gaddr1; 980 priv->hash_regs[2] = ®s->gaddr2; 981 priv->hash_regs[3] = ®s->gaddr3; 982 priv->hash_regs[4] = ®s->gaddr4; 983 priv->hash_regs[5] = ®s->gaddr5; 984 priv->hash_regs[6] = ®s->gaddr6; 985 priv->hash_regs[7] = ®s->gaddr7; 986 } 987 } 988 989 static int __gfar_is_rx_idle(struct gfar_private *priv) 990 { 991 u32 res; 992 993 /* Normaly TSEC should not hang on GRS commands, so we should 994 * actually wait for IEVENT_GRSC flag. 995 */ 996 if (!gfar_has_errata(priv, GFAR_ERRATA_A002)) 997 return 0; 998 999 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are 1000 * the same as bits 23-30, the eTSEC Rx is assumed to be idle 1001 * and the Rx can be safely reset. 1002 */ 1003 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c); 1004 res &= 0x7f807f80; 1005 if ((res & 0xffff) == (res >> 16)) 1006 return 1; 1007 1008 return 0; 1009 } 1010 1011 /* Halt the receive and transmit queues */ 1012 static void gfar_halt_nodisable(struct gfar_private *priv) 1013 { 1014 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1015 u32 tempval; 1016 unsigned int timeout; 1017 int stopped; 1018 1019 gfar_ints_disable(priv); 1020 1021 if (gfar_is_dma_stopped(priv)) 1022 return; 1023 1024 /* Stop the DMA, and wait for it to stop */ 1025 tempval = gfar_read(®s->dmactrl); 1026 tempval |= (DMACTRL_GRS | DMACTRL_GTS); 1027 gfar_write(®s->dmactrl, tempval); 1028 1029 retry: 1030 timeout = 1000; 1031 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) { 1032 cpu_relax(); 1033 timeout--; 1034 } 1035 1036 if (!timeout) 1037 stopped = gfar_is_dma_stopped(priv); 1038 1039 if (!stopped && !gfar_is_rx_dma_stopped(priv) && 1040 !__gfar_is_rx_idle(priv)) 1041 goto retry; 1042 } 1043 1044 /* Halt the receive and transmit queues */ 1045 static void gfar_halt(struct gfar_private *priv) 1046 { 1047 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1048 u32 tempval; 1049 1050 /* Dissable the Rx/Tx hw queues */ 1051 gfar_write(®s->rqueue, 0); 1052 gfar_write(®s->tqueue, 0); 1053 1054 mdelay(10); 1055 1056 gfar_halt_nodisable(priv); 1057 1058 /* Disable Rx/Tx DMA */ 1059 tempval = gfar_read(®s->maccfg1); 1060 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); 1061 gfar_write(®s->maccfg1, tempval); 1062 } 1063 1064 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) 1065 { 1066 struct txbd8 *txbdp; 1067 struct gfar_private *priv = netdev_priv(tx_queue->dev); 1068 int i, j; 1069 1070 txbdp = tx_queue->tx_bd_base; 1071 1072 for (i = 0; i < tx_queue->tx_ring_size; i++) { 1073 if (!tx_queue->tx_skbuff[i]) 1074 continue; 1075 1076 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr), 1077 be16_to_cpu(txbdp->length), DMA_TO_DEVICE); 1078 txbdp->lstatus = 0; 1079 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; 1080 j++) { 1081 txbdp++; 1082 dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr), 1083 be16_to_cpu(txbdp->length), 1084 DMA_TO_DEVICE); 1085 } 1086 txbdp++; 1087 dev_kfree_skb_any(tx_queue->tx_skbuff[i]); 1088 tx_queue->tx_skbuff[i] = NULL; 1089 } 1090 kfree(tx_queue->tx_skbuff); 1091 tx_queue->tx_skbuff = NULL; 1092 } 1093 1094 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) 1095 { 1096 int i; 1097 1098 struct rxbd8 *rxbdp = rx_queue->rx_bd_base; 1099 1100 dev_kfree_skb(rx_queue->skb); 1101 1102 for (i = 0; i < rx_queue->rx_ring_size; i++) { 1103 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[i]; 1104 1105 rxbdp->lstatus = 0; 1106 rxbdp->bufPtr = 0; 1107 rxbdp++; 1108 1109 if (!rxb->page) 1110 continue; 1111 1112 dma_unmap_page(rx_queue->dev, rxb->dma, 1113 PAGE_SIZE, DMA_FROM_DEVICE); 1114 __free_page(rxb->page); 1115 1116 rxb->page = NULL; 1117 } 1118 1119 kfree(rx_queue->rx_buff); 1120 rx_queue->rx_buff = NULL; 1121 } 1122 1123 /* If there are any tx skbs or rx skbs still around, free them. 1124 * Then free tx_skbuff and rx_skbuff 1125 */ 1126 static void free_skb_resources(struct gfar_private *priv) 1127 { 1128 struct gfar_priv_tx_q *tx_queue = NULL; 1129 struct gfar_priv_rx_q *rx_queue = NULL; 1130 int i; 1131 1132 /* Go through all the buffer descriptors and free their data buffers */ 1133 for (i = 0; i < priv->num_tx_queues; i++) { 1134 struct netdev_queue *txq; 1135 1136 tx_queue = priv->tx_queue[i]; 1137 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); 1138 if (tx_queue->tx_skbuff) 1139 free_skb_tx_queue(tx_queue); 1140 netdev_tx_reset_queue(txq); 1141 } 1142 1143 for (i = 0; i < priv->num_rx_queues; i++) { 1144 rx_queue = priv->rx_queue[i]; 1145 if (rx_queue->rx_buff) 1146 free_skb_rx_queue(rx_queue); 1147 } 1148 1149 dma_free_coherent(priv->dev, 1150 sizeof(struct txbd8) * priv->total_tx_ring_size + 1151 sizeof(struct rxbd8) * priv->total_rx_ring_size, 1152 priv->tx_queue[0]->tx_bd_base, 1153 priv->tx_queue[0]->tx_bd_dma_base); 1154 } 1155 1156 void stop_gfar(struct net_device *dev) 1157 { 1158 struct gfar_private *priv = netdev_priv(dev); 1159 1160 netif_tx_stop_all_queues(dev); 1161 1162 smp_mb__before_atomic(); 1163 set_bit(GFAR_DOWN, &priv->state); 1164 smp_mb__after_atomic(); 1165 1166 disable_napi(priv); 1167 1168 /* disable ints and gracefully shut down Rx/Tx DMA */ 1169 gfar_halt(priv); 1170 1171 phy_stop(dev->phydev); 1172 1173 free_skb_resources(priv); 1174 } 1175 1176 static void gfar_start(struct gfar_private *priv) 1177 { 1178 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1179 u32 tempval; 1180 int i = 0; 1181 1182 /* Enable Rx/Tx hw queues */ 1183 gfar_write(®s->rqueue, priv->rqueue); 1184 gfar_write(®s->tqueue, priv->tqueue); 1185 1186 /* Initialize DMACTRL to have WWR and WOP */ 1187 tempval = gfar_read(®s->dmactrl); 1188 tempval |= DMACTRL_INIT_SETTINGS; 1189 gfar_write(®s->dmactrl, tempval); 1190 1191 /* Make sure we aren't stopped */ 1192 tempval = gfar_read(®s->dmactrl); 1193 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); 1194 gfar_write(®s->dmactrl, tempval); 1195 1196 for (i = 0; i < priv->num_grps; i++) { 1197 regs = priv->gfargrp[i].regs; 1198 /* Clear THLT/RHLT, so that the DMA starts polling now */ 1199 gfar_write(®s->tstat, priv->gfargrp[i].tstat); 1200 gfar_write(®s->rstat, priv->gfargrp[i].rstat); 1201 } 1202 1203 /* Enable Rx/Tx DMA */ 1204 tempval = gfar_read(®s->maccfg1); 1205 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 1206 gfar_write(®s->maccfg1, tempval); 1207 1208 gfar_ints_enable(priv); 1209 1210 netif_trans_update(priv->ndev); /* prevent tx timeout */ 1211 } 1212 1213 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb) 1214 { 1215 struct page *page; 1216 dma_addr_t addr; 1217 1218 page = dev_alloc_page(); 1219 if (unlikely(!page)) 1220 return false; 1221 1222 addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 1223 if (unlikely(dma_mapping_error(rxq->dev, addr))) { 1224 __free_page(page); 1225 1226 return false; 1227 } 1228 1229 rxb->dma = addr; 1230 rxb->page = page; 1231 rxb->page_offset = 0; 1232 1233 return true; 1234 } 1235 1236 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue) 1237 { 1238 struct gfar_private *priv = netdev_priv(rx_queue->ndev); 1239 struct gfar_extra_stats *estats = &priv->extra_stats; 1240 1241 netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n"); 1242 atomic64_inc(&estats->rx_alloc_err); 1243 } 1244 1245 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue, 1246 int alloc_cnt) 1247 { 1248 struct rxbd8 *bdp; 1249 struct gfar_rx_buff *rxb; 1250 int i; 1251 1252 i = rx_queue->next_to_use; 1253 bdp = &rx_queue->rx_bd_base[i]; 1254 rxb = &rx_queue->rx_buff[i]; 1255 1256 while (alloc_cnt--) { 1257 /* try reuse page */ 1258 if (unlikely(!rxb->page)) { 1259 if (unlikely(!gfar_new_page(rx_queue, rxb))) { 1260 gfar_rx_alloc_err(rx_queue); 1261 break; 1262 } 1263 } 1264 1265 /* Setup the new RxBD */ 1266 gfar_init_rxbdp(rx_queue, bdp, 1267 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT); 1268 1269 /* Update to the next pointer */ 1270 bdp++; 1271 rxb++; 1272 1273 if (unlikely(++i == rx_queue->rx_ring_size)) { 1274 i = 0; 1275 bdp = rx_queue->rx_bd_base; 1276 rxb = rx_queue->rx_buff; 1277 } 1278 } 1279 1280 rx_queue->next_to_use = i; 1281 rx_queue->next_to_alloc = i; 1282 } 1283 1284 static void gfar_init_bds(struct net_device *ndev) 1285 { 1286 struct gfar_private *priv = netdev_priv(ndev); 1287 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1288 struct gfar_priv_tx_q *tx_queue = NULL; 1289 struct gfar_priv_rx_q *rx_queue = NULL; 1290 struct txbd8 *txbdp; 1291 u32 __iomem *rfbptr; 1292 int i, j; 1293 1294 for (i = 0; i < priv->num_tx_queues; i++) { 1295 tx_queue = priv->tx_queue[i]; 1296 /* Initialize some variables in our dev structure */ 1297 tx_queue->num_txbdfree = tx_queue->tx_ring_size; 1298 tx_queue->dirty_tx = tx_queue->tx_bd_base; 1299 tx_queue->cur_tx = tx_queue->tx_bd_base; 1300 tx_queue->skb_curtx = 0; 1301 tx_queue->skb_dirtytx = 0; 1302 1303 /* Initialize Transmit Descriptor Ring */ 1304 txbdp = tx_queue->tx_bd_base; 1305 for (j = 0; j < tx_queue->tx_ring_size; j++) { 1306 txbdp->lstatus = 0; 1307 txbdp->bufPtr = 0; 1308 txbdp++; 1309 } 1310 1311 /* Set the last descriptor in the ring to indicate wrap */ 1312 txbdp--; 1313 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) | 1314 TXBD_WRAP); 1315 } 1316 1317 rfbptr = ®s->rfbptr0; 1318 for (i = 0; i < priv->num_rx_queues; i++) { 1319 rx_queue = priv->rx_queue[i]; 1320 1321 rx_queue->next_to_clean = 0; 1322 rx_queue->next_to_use = 0; 1323 rx_queue->next_to_alloc = 0; 1324 1325 /* make sure next_to_clean != next_to_use after this 1326 * by leaving at least 1 unused descriptor 1327 */ 1328 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue)); 1329 1330 rx_queue->rfbptr = rfbptr; 1331 rfbptr += 2; 1332 } 1333 } 1334 1335 static int gfar_alloc_skb_resources(struct net_device *ndev) 1336 { 1337 void *vaddr; 1338 dma_addr_t addr; 1339 int i, j; 1340 struct gfar_private *priv = netdev_priv(ndev); 1341 struct device *dev = priv->dev; 1342 struct gfar_priv_tx_q *tx_queue = NULL; 1343 struct gfar_priv_rx_q *rx_queue = NULL; 1344 1345 priv->total_tx_ring_size = 0; 1346 for (i = 0; i < priv->num_tx_queues; i++) 1347 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; 1348 1349 priv->total_rx_ring_size = 0; 1350 for (i = 0; i < priv->num_rx_queues; i++) 1351 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; 1352 1353 /* Allocate memory for the buffer descriptors */ 1354 vaddr = dma_alloc_coherent(dev, 1355 (priv->total_tx_ring_size * 1356 sizeof(struct txbd8)) + 1357 (priv->total_rx_ring_size * 1358 sizeof(struct rxbd8)), 1359 &addr, GFP_KERNEL); 1360 if (!vaddr) 1361 return -ENOMEM; 1362 1363 for (i = 0; i < priv->num_tx_queues; i++) { 1364 tx_queue = priv->tx_queue[i]; 1365 tx_queue->tx_bd_base = vaddr; 1366 tx_queue->tx_bd_dma_base = addr; 1367 tx_queue->dev = ndev; 1368 /* enet DMA only understands physical addresses */ 1369 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size; 1370 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size; 1371 } 1372 1373 /* Start the rx descriptor ring where the tx ring leaves off */ 1374 for (i = 0; i < priv->num_rx_queues; i++) { 1375 rx_queue = priv->rx_queue[i]; 1376 rx_queue->rx_bd_base = vaddr; 1377 rx_queue->rx_bd_dma_base = addr; 1378 rx_queue->ndev = ndev; 1379 rx_queue->dev = dev; 1380 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; 1381 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; 1382 } 1383 1384 /* Setup the skbuff rings */ 1385 for (i = 0; i < priv->num_tx_queues; i++) { 1386 tx_queue = priv->tx_queue[i]; 1387 tx_queue->tx_skbuff = 1388 kmalloc_array(tx_queue->tx_ring_size, 1389 sizeof(*tx_queue->tx_skbuff), 1390 GFP_KERNEL); 1391 if (!tx_queue->tx_skbuff) 1392 goto cleanup; 1393 1394 for (j = 0; j < tx_queue->tx_ring_size; j++) 1395 tx_queue->tx_skbuff[j] = NULL; 1396 } 1397 1398 for (i = 0; i < priv->num_rx_queues; i++) { 1399 rx_queue = priv->rx_queue[i]; 1400 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size, 1401 sizeof(*rx_queue->rx_buff), 1402 GFP_KERNEL); 1403 if (!rx_queue->rx_buff) 1404 goto cleanup; 1405 } 1406 1407 gfar_init_bds(ndev); 1408 1409 return 0; 1410 1411 cleanup: 1412 free_skb_resources(priv); 1413 return -ENOMEM; 1414 } 1415 1416 /* Bring the controller up and running */ 1417 int startup_gfar(struct net_device *ndev) 1418 { 1419 struct gfar_private *priv = netdev_priv(ndev); 1420 int err; 1421 1422 gfar_mac_reset(priv); 1423 1424 err = gfar_alloc_skb_resources(ndev); 1425 if (err) 1426 return err; 1427 1428 gfar_init_tx_rx_base(priv); 1429 1430 smp_mb__before_atomic(); 1431 clear_bit(GFAR_DOWN, &priv->state); 1432 smp_mb__after_atomic(); 1433 1434 /* Start Rx/Tx DMA and enable the interrupts */ 1435 gfar_start(priv); 1436 1437 /* force link state update after mac reset */ 1438 priv->oldlink = 0; 1439 priv->oldspeed = 0; 1440 priv->oldduplex = -1; 1441 1442 phy_start(ndev->phydev); 1443 1444 enable_napi(priv); 1445 1446 netif_tx_wake_all_queues(ndev); 1447 1448 return 0; 1449 } 1450 1451 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv) 1452 { 1453 struct net_device *ndev = priv->ndev; 1454 struct phy_device *phydev = ndev->phydev; 1455 u32 val = 0; 1456 1457 if (!phydev->duplex) 1458 return val; 1459 1460 if (!priv->pause_aneg_en) { 1461 if (priv->tx_pause_en) 1462 val |= MACCFG1_TX_FLOW; 1463 if (priv->rx_pause_en) 1464 val |= MACCFG1_RX_FLOW; 1465 } else { 1466 u16 lcl_adv, rmt_adv; 1467 u8 flowctrl; 1468 /* get link partner capabilities */ 1469 rmt_adv = 0; 1470 if (phydev->pause) 1471 rmt_adv = LPA_PAUSE_CAP; 1472 if (phydev->asym_pause) 1473 rmt_adv |= LPA_PAUSE_ASYM; 1474 1475 lcl_adv = linkmode_adv_to_lcl_adv_t(phydev->advertising); 1476 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 1477 if (flowctrl & FLOW_CTRL_TX) 1478 val |= MACCFG1_TX_FLOW; 1479 if (flowctrl & FLOW_CTRL_RX) 1480 val |= MACCFG1_RX_FLOW; 1481 } 1482 1483 return val; 1484 } 1485 1486 static noinline void gfar_update_link_state(struct gfar_private *priv) 1487 { 1488 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1489 struct net_device *ndev = priv->ndev; 1490 struct phy_device *phydev = ndev->phydev; 1491 struct gfar_priv_rx_q *rx_queue = NULL; 1492 int i; 1493 1494 if (unlikely(test_bit(GFAR_RESETTING, &priv->state))) 1495 return; 1496 1497 if (phydev->link) { 1498 u32 tempval1 = gfar_read(®s->maccfg1); 1499 u32 tempval = gfar_read(®s->maccfg2); 1500 u32 ecntrl = gfar_read(®s->ecntrl); 1501 u32 tx_flow_oldval = (tempval1 & MACCFG1_TX_FLOW); 1502 1503 if (phydev->duplex != priv->oldduplex) { 1504 if (!(phydev->duplex)) 1505 tempval &= ~(MACCFG2_FULL_DUPLEX); 1506 else 1507 tempval |= MACCFG2_FULL_DUPLEX; 1508 1509 priv->oldduplex = phydev->duplex; 1510 } 1511 1512 if (phydev->speed != priv->oldspeed) { 1513 switch (phydev->speed) { 1514 case 1000: 1515 tempval = 1516 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); 1517 1518 ecntrl &= ~(ECNTRL_R100); 1519 break; 1520 case 100: 1521 case 10: 1522 tempval = 1523 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); 1524 1525 /* Reduced mode distinguishes 1526 * between 10 and 100 1527 */ 1528 if (phydev->speed == SPEED_100) 1529 ecntrl |= ECNTRL_R100; 1530 else 1531 ecntrl &= ~(ECNTRL_R100); 1532 break; 1533 default: 1534 netif_warn(priv, link, priv->ndev, 1535 "Ack! Speed (%d) is not 10/100/1000!\n", 1536 phydev->speed); 1537 break; 1538 } 1539 1540 priv->oldspeed = phydev->speed; 1541 } 1542 1543 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); 1544 tempval1 |= gfar_get_flowctrl_cfg(priv); 1545 1546 /* Turn last free buffer recording on */ 1547 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) { 1548 for (i = 0; i < priv->num_rx_queues; i++) { 1549 u32 bdp_dma; 1550 1551 rx_queue = priv->rx_queue[i]; 1552 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue); 1553 gfar_write(rx_queue->rfbptr, bdp_dma); 1554 } 1555 1556 priv->tx_actual_en = 1; 1557 } 1558 1559 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval)) 1560 priv->tx_actual_en = 0; 1561 1562 gfar_write(®s->maccfg1, tempval1); 1563 gfar_write(®s->maccfg2, tempval); 1564 gfar_write(®s->ecntrl, ecntrl); 1565 1566 if (!priv->oldlink) 1567 priv->oldlink = 1; 1568 1569 } else if (priv->oldlink) { 1570 priv->oldlink = 0; 1571 priv->oldspeed = 0; 1572 priv->oldduplex = -1; 1573 } 1574 1575 if (netif_msg_link(priv)) 1576 phy_print_status(phydev); 1577 } 1578 1579 /* Called every time the controller might need to be made 1580 * aware of new link state. The PHY code conveys this 1581 * information through variables in the phydev structure, and this 1582 * function converts those variables into the appropriate 1583 * register values, and can bring down the device if needed. 1584 */ 1585 static void adjust_link(struct net_device *dev) 1586 { 1587 struct gfar_private *priv = netdev_priv(dev); 1588 struct phy_device *phydev = dev->phydev; 1589 1590 if (unlikely(phydev->link != priv->oldlink || 1591 (phydev->link && (phydev->duplex != priv->oldduplex || 1592 phydev->speed != priv->oldspeed)))) 1593 gfar_update_link_state(priv); 1594 } 1595 1596 /* Initialize TBI PHY interface for communicating with the 1597 * SERDES lynx PHY on the chip. We communicate with this PHY 1598 * through the MDIO bus on each controller, treating it as a 1599 * "normal" PHY at the address found in the TBIPA register. We assume 1600 * that the TBIPA register is valid. Either the MDIO bus code will set 1601 * it to a value that doesn't conflict with other PHYs on the bus, or the 1602 * value doesn't matter, as there are no other PHYs on the bus. 1603 */ 1604 static void gfar_configure_serdes(struct net_device *dev) 1605 { 1606 struct gfar_private *priv = netdev_priv(dev); 1607 struct phy_device *tbiphy; 1608 1609 if (!priv->tbi_node) { 1610 dev_warn(&dev->dev, "error: SGMII mode requires that the " 1611 "device tree specify a tbi-handle\n"); 1612 return; 1613 } 1614 1615 tbiphy = of_phy_find_device(priv->tbi_node); 1616 if (!tbiphy) { 1617 dev_err(&dev->dev, "error: Could not get TBI device\n"); 1618 return; 1619 } 1620 1621 /* If the link is already up, we must already be ok, and don't need to 1622 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured 1623 * everything for us? Resetting it takes the link down and requires 1624 * several seconds for it to come back. 1625 */ 1626 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) { 1627 put_device(&tbiphy->mdio.dev); 1628 return; 1629 } 1630 1631 /* Single clk mode, mii mode off(for serdes communication) */ 1632 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); 1633 1634 phy_write(tbiphy, MII_ADVERTISE, 1635 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | 1636 ADVERTISE_1000XPSE_ASYM); 1637 1638 phy_write(tbiphy, MII_BMCR, 1639 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | 1640 BMCR_SPEED1000); 1641 1642 put_device(&tbiphy->mdio.dev); 1643 } 1644 1645 /* Initializes driver's PHY state, and attaches to the PHY. 1646 * Returns 0 on success. 1647 */ 1648 static int init_phy(struct net_device *dev) 1649 { 1650 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1651 struct gfar_private *priv = netdev_priv(dev); 1652 phy_interface_t interface = priv->interface; 1653 struct phy_device *phydev; 1654 struct ethtool_keee edata; 1655 1656 linkmode_set_bit_array(phy_10_100_features_array, 1657 ARRAY_SIZE(phy_10_100_features_array), 1658 mask); 1659 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask); 1660 linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask); 1661 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) 1662 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mask); 1663 1664 priv->oldlink = 0; 1665 priv->oldspeed = 0; 1666 priv->oldduplex = -1; 1667 1668 phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, 1669 interface); 1670 if (!phydev) { 1671 dev_err(&dev->dev, "could not attach to PHY\n"); 1672 return -ENODEV; 1673 } 1674 1675 if (interface == PHY_INTERFACE_MODE_SGMII) 1676 gfar_configure_serdes(dev); 1677 1678 /* Remove any features not supported by the controller */ 1679 linkmode_and(phydev->supported, phydev->supported, mask); 1680 linkmode_copy(phydev->advertising, phydev->supported); 1681 1682 /* Add support for flow control */ 1683 phy_support_asym_pause(phydev); 1684 1685 /* disable EEE autoneg, EEE not supported by eTSEC */ 1686 memset(&edata, 0, sizeof(struct ethtool_keee)); 1687 phy_ethtool_set_eee(phydev, &edata); 1688 1689 return 0; 1690 } 1691 1692 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) 1693 { 1694 struct txfcb *fcb = skb_push(skb, GMAC_FCB_LEN); 1695 1696 memset(fcb, 0, GMAC_FCB_LEN); 1697 1698 return fcb; 1699 } 1700 1701 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb, 1702 int fcb_length) 1703 { 1704 /* If we're here, it's a IP packet with a TCP or UDP 1705 * payload. We set it to checksum, using a pseudo-header 1706 * we provide 1707 */ 1708 u8 flags = TXFCB_DEFAULT; 1709 1710 /* Tell the controller what the protocol is 1711 * And provide the already calculated phcs 1712 */ 1713 if (ip_hdr(skb)->protocol == IPPROTO_UDP) { 1714 flags |= TXFCB_UDP; 1715 fcb->phcs = (__force __be16)(udp_hdr(skb)->check); 1716 } else 1717 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check); 1718 1719 /* l3os is the distance between the start of the 1720 * frame (skb->data) and the start of the IP hdr. 1721 * l4os is the distance between the start of the 1722 * l3 hdr and the l4 hdr 1723 */ 1724 fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length); 1725 fcb->l4os = skb_network_header_len(skb); 1726 1727 fcb->flags = flags; 1728 } 1729 1730 static inline void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) 1731 { 1732 fcb->flags |= TXFCB_VLN; 1733 fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb)); 1734 } 1735 1736 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, 1737 struct txbd8 *base, int ring_size) 1738 { 1739 struct txbd8 *new_bd = bdp + stride; 1740 1741 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; 1742 } 1743 1744 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, 1745 int ring_size) 1746 { 1747 return skip_txbd(bdp, 1, base, ring_size); 1748 } 1749 1750 /* eTSEC12: csum generation not supported for some fcb offsets */ 1751 static inline bool gfar_csum_errata_12(struct gfar_private *priv, 1752 unsigned long fcb_addr) 1753 { 1754 return (gfar_has_errata(priv, GFAR_ERRATA_12) && 1755 (fcb_addr % 0x20) > 0x18); 1756 } 1757 1758 /* eTSEC76: csum generation for frames larger than 2500 may 1759 * cause excess delays before start of transmission 1760 */ 1761 static inline bool gfar_csum_errata_76(struct gfar_private *priv, 1762 unsigned int len) 1763 { 1764 return (gfar_has_errata(priv, GFAR_ERRATA_76) && 1765 (len > 2500)); 1766 } 1767 1768 /* This is called by the kernel when a frame is ready for transmission. 1769 * It is pointed to by the dev->hard_start_xmit function pointer 1770 */ 1771 static netdev_tx_t gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) 1772 { 1773 struct gfar_private *priv = netdev_priv(dev); 1774 struct gfar_priv_tx_q *tx_queue = NULL; 1775 struct netdev_queue *txq; 1776 struct gfar __iomem *regs = NULL; 1777 struct txfcb *fcb = NULL; 1778 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; 1779 u32 lstatus; 1780 skb_frag_t *frag; 1781 int i, rq = 0; 1782 int do_tstamp, do_csum, do_vlan; 1783 u32 bufaddr; 1784 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0; 1785 1786 rq = skb->queue_mapping; 1787 tx_queue = priv->tx_queue[rq]; 1788 txq = netdev_get_tx_queue(dev, rq); 1789 base = tx_queue->tx_bd_base; 1790 regs = tx_queue->grp->regs; 1791 1792 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed); 1793 do_vlan = skb_vlan_tag_present(skb); 1794 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1795 priv->hwts_tx_en; 1796 1797 if (do_csum || do_vlan) 1798 fcb_len = GMAC_FCB_LEN; 1799 1800 /* check if time stamp should be generated */ 1801 if (unlikely(do_tstamp)) 1802 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN; 1803 1804 /* make space for additional header when fcb is needed */ 1805 if (fcb_len) { 1806 if (unlikely(skb_cow_head(skb, fcb_len))) { 1807 dev->stats.tx_errors++; 1808 dev_kfree_skb_any(skb); 1809 return NETDEV_TX_OK; 1810 } 1811 } 1812 1813 /* total number of fragments in the SKB */ 1814 nr_frags = skb_shinfo(skb)->nr_frags; 1815 1816 /* calculate the required number of TxBDs for this skb */ 1817 if (unlikely(do_tstamp)) 1818 nr_txbds = nr_frags + 2; 1819 else 1820 nr_txbds = nr_frags + 1; 1821 1822 /* check if there is space to queue this packet */ 1823 if (nr_txbds > tx_queue->num_txbdfree) { 1824 /* no space, stop the queue */ 1825 netif_tx_stop_queue(txq); 1826 dev->stats.tx_fifo_errors++; 1827 return NETDEV_TX_BUSY; 1828 } 1829 1830 /* Update transmit stats */ 1831 bytes_sent = skb->len; 1832 tx_queue->stats.tx_bytes += bytes_sent; 1833 /* keep Tx bytes on wire for BQL accounting */ 1834 GFAR_CB(skb)->bytes_sent = bytes_sent; 1835 tx_queue->stats.tx_packets++; 1836 1837 txbdp = txbdp_start = tx_queue->cur_tx; 1838 lstatus = be32_to_cpu(txbdp->lstatus); 1839 1840 /* Add TxPAL between FCB and frame if required */ 1841 if (unlikely(do_tstamp)) { 1842 skb_push(skb, GMAC_TXPAL_LEN); 1843 memset(skb->data, 0, GMAC_TXPAL_LEN); 1844 } 1845 1846 /* Add TxFCB if required */ 1847 if (fcb_len) { 1848 fcb = gfar_add_fcb(skb); 1849 lstatus |= BD_LFLAG(TXBD_TOE); 1850 } 1851 1852 /* Set up checksumming */ 1853 if (do_csum) { 1854 gfar_tx_checksum(skb, fcb, fcb_len); 1855 1856 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) || 1857 unlikely(gfar_csum_errata_76(priv, skb->len))) { 1858 __skb_pull(skb, GMAC_FCB_LEN); 1859 skb_checksum_help(skb); 1860 if (do_vlan || do_tstamp) { 1861 /* put back a new fcb for vlan/tstamp TOE */ 1862 fcb = gfar_add_fcb(skb); 1863 } else { 1864 /* Tx TOE not used */ 1865 lstatus &= ~(BD_LFLAG(TXBD_TOE)); 1866 fcb = NULL; 1867 } 1868 } 1869 } 1870 1871 if (do_vlan) 1872 gfar_tx_vlan(skb, fcb); 1873 1874 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb), 1875 DMA_TO_DEVICE); 1876 if (unlikely(dma_mapping_error(priv->dev, bufaddr))) 1877 goto dma_map_err; 1878 1879 txbdp_start->bufPtr = cpu_to_be32(bufaddr); 1880 1881 /* Time stamp insertion requires one additional TxBD */ 1882 if (unlikely(do_tstamp)) 1883 txbdp_tstamp = txbdp = next_txbd(txbdp, base, 1884 tx_queue->tx_ring_size); 1885 1886 if (likely(!nr_frags)) { 1887 if (likely(!do_tstamp)) 1888 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 1889 } else { 1890 u32 lstatus_start = lstatus; 1891 1892 /* Place the fragment addresses and lengths into the TxBDs */ 1893 frag = &skb_shinfo(skb)->frags[0]; 1894 for (i = 0; i < nr_frags; i++, frag++) { 1895 unsigned int size; 1896 1897 /* Point at the next BD, wrapping as needed */ 1898 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 1899 1900 size = skb_frag_size(frag); 1901 1902 lstatus = be32_to_cpu(txbdp->lstatus) | size | 1903 BD_LFLAG(TXBD_READY); 1904 1905 /* Handle the last BD specially */ 1906 if (i == nr_frags - 1) 1907 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 1908 1909 bufaddr = skb_frag_dma_map(priv->dev, frag, 0, 1910 size, DMA_TO_DEVICE); 1911 if (unlikely(dma_mapping_error(priv->dev, bufaddr))) 1912 goto dma_map_err; 1913 1914 /* set the TxBD length and buffer pointer */ 1915 txbdp->bufPtr = cpu_to_be32(bufaddr); 1916 txbdp->lstatus = cpu_to_be32(lstatus); 1917 } 1918 1919 lstatus = lstatus_start; 1920 } 1921 1922 /* If time stamping is requested one additional TxBD must be set up. The 1923 * first TxBD points to the FCB and must have a data length of 1924 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with 1925 * the full frame length. 1926 */ 1927 if (unlikely(do_tstamp)) { 1928 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus); 1929 1930 bufaddr = be32_to_cpu(txbdp_start->bufPtr); 1931 bufaddr += fcb_len; 1932 1933 lstatus_ts |= BD_LFLAG(TXBD_READY) | 1934 (skb_headlen(skb) - fcb_len); 1935 if (!nr_frags) 1936 lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 1937 1938 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr); 1939 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts); 1940 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN; 1941 1942 /* Setup tx hardware time stamping */ 1943 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1944 fcb->ptp = 1; 1945 } else { 1946 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); 1947 } 1948 1949 skb_tx_timestamp(skb); 1950 netdev_tx_sent_queue(txq, bytes_sent); 1951 1952 gfar_wmb(); 1953 1954 txbdp_start->lstatus = cpu_to_be32(lstatus); 1955 1956 gfar_wmb(); /* force lstatus write before tx_skbuff */ 1957 1958 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; 1959 1960 /* Update the current skb pointer to the next entry we will use 1961 * (wrapping if necessary) 1962 */ 1963 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & 1964 TX_RING_MOD_MASK(tx_queue->tx_ring_size); 1965 1966 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); 1967 1968 /* We can work in parallel with gfar_clean_tx_ring(), except 1969 * when modifying num_txbdfree. Note that we didn't grab the lock 1970 * when we were reading the num_txbdfree and checking for available 1971 * space, that's because outside of this function it can only grow. 1972 */ 1973 spin_lock_bh(&tx_queue->txlock); 1974 /* reduce TxBD free count */ 1975 tx_queue->num_txbdfree -= (nr_txbds); 1976 spin_unlock_bh(&tx_queue->txlock); 1977 1978 /* If the next BD still needs to be cleaned up, then the bds 1979 * are full. We need to tell the kernel to stop sending us stuff. 1980 */ 1981 if (!tx_queue->num_txbdfree) { 1982 netif_tx_stop_queue(txq); 1983 1984 dev->stats.tx_fifo_errors++; 1985 } 1986 1987 /* Tell the DMA to go go go */ 1988 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); 1989 1990 return NETDEV_TX_OK; 1991 1992 dma_map_err: 1993 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size); 1994 if (do_tstamp) 1995 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 1996 for (i = 0; i < nr_frags; i++) { 1997 lstatus = be32_to_cpu(txbdp->lstatus); 1998 if (!(lstatus & BD_LFLAG(TXBD_READY))) 1999 break; 2000 2001 lstatus &= ~BD_LFLAG(TXBD_READY); 2002 txbdp->lstatus = cpu_to_be32(lstatus); 2003 bufaddr = be32_to_cpu(txbdp->bufPtr); 2004 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length), 2005 DMA_TO_DEVICE); 2006 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2007 } 2008 gfar_wmb(); 2009 dev_kfree_skb_any(skb); 2010 return NETDEV_TX_OK; 2011 } 2012 2013 /* Changes the mac address if the controller is not running. */ 2014 static int gfar_set_mac_address(struct net_device *dev) 2015 { 2016 gfar_set_mac_for_addr(dev, 0, dev->dev_addr); 2017 2018 return 0; 2019 } 2020 2021 static int gfar_change_mtu(struct net_device *dev, int new_mtu) 2022 { 2023 struct gfar_private *priv = netdev_priv(dev); 2024 2025 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state)) 2026 cpu_relax(); 2027 2028 if (dev->flags & IFF_UP) 2029 stop_gfar(dev); 2030 2031 WRITE_ONCE(dev->mtu, new_mtu); 2032 2033 if (dev->flags & IFF_UP) 2034 startup_gfar(dev); 2035 2036 clear_bit_unlock(GFAR_RESETTING, &priv->state); 2037 2038 return 0; 2039 } 2040 2041 static void reset_gfar(struct net_device *ndev) 2042 { 2043 struct gfar_private *priv = netdev_priv(ndev); 2044 2045 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state)) 2046 cpu_relax(); 2047 2048 stop_gfar(ndev); 2049 startup_gfar(ndev); 2050 2051 clear_bit_unlock(GFAR_RESETTING, &priv->state); 2052 } 2053 2054 /* gfar_reset_task gets scheduled when a packet has not been 2055 * transmitted after a set amount of time. 2056 * For now, assume that clearing out all the structures, and 2057 * starting over will fix the problem. 2058 */ 2059 static void gfar_reset_task(struct work_struct *work) 2060 { 2061 struct gfar_private *priv = container_of(work, struct gfar_private, 2062 reset_task); 2063 reset_gfar(priv->ndev); 2064 } 2065 2066 static void gfar_timeout(struct net_device *dev, unsigned int txqueue) 2067 { 2068 struct gfar_private *priv = netdev_priv(dev); 2069 2070 dev->stats.tx_errors++; 2071 schedule_work(&priv->reset_task); 2072 } 2073 2074 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 2075 { 2076 struct hwtstamp_config config; 2077 struct gfar_private *priv = netdev_priv(netdev); 2078 2079 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 2080 return -EFAULT; 2081 2082 switch (config.tx_type) { 2083 case HWTSTAMP_TX_OFF: 2084 priv->hwts_tx_en = 0; 2085 break; 2086 case HWTSTAMP_TX_ON: 2087 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) 2088 return -ERANGE; 2089 priv->hwts_tx_en = 1; 2090 break; 2091 default: 2092 return -ERANGE; 2093 } 2094 2095 switch (config.rx_filter) { 2096 case HWTSTAMP_FILTER_NONE: 2097 if (priv->hwts_rx_en) { 2098 priv->hwts_rx_en = 0; 2099 reset_gfar(netdev); 2100 } 2101 break; 2102 default: 2103 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) 2104 return -ERANGE; 2105 if (!priv->hwts_rx_en) { 2106 priv->hwts_rx_en = 1; 2107 reset_gfar(netdev); 2108 } 2109 config.rx_filter = HWTSTAMP_FILTER_ALL; 2110 break; 2111 } 2112 2113 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 2114 -EFAULT : 0; 2115 } 2116 2117 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 2118 { 2119 struct hwtstamp_config config; 2120 struct gfar_private *priv = netdev_priv(netdev); 2121 2122 config.flags = 0; 2123 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 2124 config.rx_filter = (priv->hwts_rx_en ? 2125 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE); 2126 2127 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 2128 -EFAULT : 0; 2129 } 2130 2131 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2132 { 2133 struct phy_device *phydev = dev->phydev; 2134 2135 if (!netif_running(dev)) 2136 return -EINVAL; 2137 2138 if (cmd == SIOCSHWTSTAMP) 2139 return gfar_hwtstamp_set(dev, rq); 2140 if (cmd == SIOCGHWTSTAMP) 2141 return gfar_hwtstamp_get(dev, rq); 2142 2143 if (!phydev) 2144 return -ENODEV; 2145 2146 return phy_mii_ioctl(phydev, rq, cmd); 2147 } 2148 2149 /* Interrupt Handler for Transmit complete */ 2150 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) 2151 { 2152 struct net_device *dev = tx_queue->dev; 2153 struct netdev_queue *txq; 2154 struct gfar_private *priv = netdev_priv(dev); 2155 struct txbd8 *bdp, *next = NULL; 2156 struct txbd8 *lbdp = NULL; 2157 struct txbd8 *base = tx_queue->tx_bd_base; 2158 struct sk_buff *skb; 2159 int skb_dirtytx; 2160 int tx_ring_size = tx_queue->tx_ring_size; 2161 int frags = 0, nr_txbds = 0; 2162 int i; 2163 int howmany = 0; 2164 int tqi = tx_queue->qindex; 2165 unsigned int bytes_sent = 0; 2166 u32 lstatus; 2167 size_t buflen; 2168 2169 txq = netdev_get_tx_queue(dev, tqi); 2170 bdp = tx_queue->dirty_tx; 2171 skb_dirtytx = tx_queue->skb_dirtytx; 2172 2173 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { 2174 bool do_tstamp; 2175 2176 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2177 priv->hwts_tx_en; 2178 2179 frags = skb_shinfo(skb)->nr_frags; 2180 2181 /* When time stamping, one additional TxBD must be freed. 2182 * Also, we need to dma_unmap_single() the TxPAL. 2183 */ 2184 if (unlikely(do_tstamp)) 2185 nr_txbds = frags + 2; 2186 else 2187 nr_txbds = frags + 1; 2188 2189 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); 2190 2191 lstatus = be32_to_cpu(lbdp->lstatus); 2192 2193 /* Only clean completed frames */ 2194 if ((lstatus & BD_LFLAG(TXBD_READY)) && 2195 (lstatus & BD_LENGTH_MASK)) 2196 break; 2197 2198 if (unlikely(do_tstamp)) { 2199 next = next_txbd(bdp, base, tx_ring_size); 2200 buflen = be16_to_cpu(next->length) + 2201 GMAC_FCB_LEN + GMAC_TXPAL_LEN; 2202 } else 2203 buflen = be16_to_cpu(bdp->length); 2204 2205 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr), 2206 buflen, DMA_TO_DEVICE); 2207 2208 if (unlikely(do_tstamp)) { 2209 struct skb_shared_hwtstamps shhwtstamps; 2210 __be64 *ns; 2211 2212 ns = (__be64 *)(((uintptr_t)skb->data + 0x10) & ~0x7UL); 2213 2214 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 2215 shhwtstamps.hwtstamp = ns_to_ktime(be64_to_cpu(*ns)); 2216 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN); 2217 skb_tstamp_tx(skb, &shhwtstamps); 2218 gfar_clear_txbd_status(bdp); 2219 bdp = next; 2220 } 2221 2222 gfar_clear_txbd_status(bdp); 2223 bdp = next_txbd(bdp, base, tx_ring_size); 2224 2225 for (i = 0; i < frags; i++) { 2226 dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr), 2227 be16_to_cpu(bdp->length), 2228 DMA_TO_DEVICE); 2229 gfar_clear_txbd_status(bdp); 2230 bdp = next_txbd(bdp, base, tx_ring_size); 2231 } 2232 2233 bytes_sent += GFAR_CB(skb)->bytes_sent; 2234 2235 dev_kfree_skb_any(skb); 2236 2237 tx_queue->tx_skbuff[skb_dirtytx] = NULL; 2238 2239 skb_dirtytx = (skb_dirtytx + 1) & 2240 TX_RING_MOD_MASK(tx_ring_size); 2241 2242 howmany++; 2243 spin_lock(&tx_queue->txlock); 2244 tx_queue->num_txbdfree += nr_txbds; 2245 spin_unlock(&tx_queue->txlock); 2246 } 2247 2248 /* If we freed a buffer, we can restart transmission, if necessary */ 2249 if (tx_queue->num_txbdfree && 2250 netif_tx_queue_stopped(txq) && 2251 !(test_bit(GFAR_DOWN, &priv->state))) 2252 netif_wake_subqueue(priv->ndev, tqi); 2253 2254 /* Update dirty indicators */ 2255 tx_queue->skb_dirtytx = skb_dirtytx; 2256 tx_queue->dirty_tx = bdp; 2257 2258 netdev_tx_completed_queue(txq, howmany, bytes_sent); 2259 } 2260 2261 static void count_errors(u32 lstatus, struct net_device *ndev) 2262 { 2263 struct gfar_private *priv = netdev_priv(ndev); 2264 struct net_device_stats *stats = &ndev->stats; 2265 struct gfar_extra_stats *estats = &priv->extra_stats; 2266 2267 /* If the packet was truncated, none of the other errors matter */ 2268 if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) { 2269 stats->rx_length_errors++; 2270 2271 atomic64_inc(&estats->rx_trunc); 2272 2273 return; 2274 } 2275 /* Count the errors, if there were any */ 2276 if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) { 2277 stats->rx_length_errors++; 2278 2279 if (lstatus & BD_LFLAG(RXBD_LARGE)) 2280 atomic64_inc(&estats->rx_large); 2281 else 2282 atomic64_inc(&estats->rx_short); 2283 } 2284 if (lstatus & BD_LFLAG(RXBD_NONOCTET)) { 2285 stats->rx_frame_errors++; 2286 atomic64_inc(&estats->rx_nonoctet); 2287 } 2288 if (lstatus & BD_LFLAG(RXBD_CRCERR)) { 2289 atomic64_inc(&estats->rx_crcerr); 2290 stats->rx_crc_errors++; 2291 } 2292 if (lstatus & BD_LFLAG(RXBD_OVERRUN)) { 2293 atomic64_inc(&estats->rx_overrun); 2294 stats->rx_over_errors++; 2295 } 2296 } 2297 2298 static irqreturn_t gfar_receive(int irq, void *grp_id) 2299 { 2300 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id; 2301 unsigned long flags; 2302 u32 imask, ievent; 2303 2304 ievent = gfar_read(&grp->regs->ievent); 2305 2306 if (unlikely(ievent & IEVENT_FGPI)) { 2307 gfar_write(&grp->regs->ievent, IEVENT_FGPI); 2308 return IRQ_HANDLED; 2309 } 2310 2311 if (likely(napi_schedule_prep(&grp->napi_rx))) { 2312 spin_lock_irqsave(&grp->grplock, flags); 2313 imask = gfar_read(&grp->regs->imask); 2314 imask &= IMASK_RX_DISABLED | grp->priv->rmon_overflow.imask; 2315 gfar_write(&grp->regs->imask, imask); 2316 spin_unlock_irqrestore(&grp->grplock, flags); 2317 __napi_schedule(&grp->napi_rx); 2318 } else { 2319 /* Clear IEVENT, so interrupts aren't called again 2320 * because of the packets that have already arrived. 2321 */ 2322 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK); 2323 } 2324 2325 return IRQ_HANDLED; 2326 } 2327 2328 /* Interrupt Handler for Transmit complete */ 2329 static irqreturn_t gfar_transmit(int irq, void *grp_id) 2330 { 2331 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id; 2332 unsigned long flags; 2333 u32 imask; 2334 2335 if (likely(napi_schedule_prep(&grp->napi_tx))) { 2336 spin_lock_irqsave(&grp->grplock, flags); 2337 imask = gfar_read(&grp->regs->imask); 2338 imask &= IMASK_TX_DISABLED | grp->priv->rmon_overflow.imask; 2339 gfar_write(&grp->regs->imask, imask); 2340 spin_unlock_irqrestore(&grp->grplock, flags); 2341 __napi_schedule(&grp->napi_tx); 2342 } else { 2343 /* Clear IEVENT, so interrupts aren't called again 2344 * because of the packets that have already arrived. 2345 */ 2346 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK); 2347 } 2348 2349 return IRQ_HANDLED; 2350 } 2351 2352 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus, 2353 struct sk_buff *skb, bool first) 2354 { 2355 int size = lstatus & BD_LENGTH_MASK; 2356 struct page *page = rxb->page; 2357 2358 if (likely(first)) { 2359 skb_put(skb, size); 2360 } else { 2361 /* the last fragments' length contains the full frame length */ 2362 if (lstatus & BD_LFLAG(RXBD_LAST)) 2363 size -= skb->len; 2364 2365 WARN(size < 0, "gianfar: rx fragment size underflow"); 2366 if (size < 0) 2367 return false; 2368 2369 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 2370 rxb->page_offset + RXBUF_ALIGNMENT, 2371 size, GFAR_RXB_TRUESIZE); 2372 } 2373 2374 /* try reuse page */ 2375 if (unlikely(page_count(page) != 1 || page_is_pfmemalloc(page))) 2376 return false; 2377 2378 /* change offset to the other half */ 2379 rxb->page_offset ^= GFAR_RXB_TRUESIZE; 2380 2381 page_ref_inc(page); 2382 2383 return true; 2384 } 2385 2386 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq, 2387 struct gfar_rx_buff *old_rxb) 2388 { 2389 struct gfar_rx_buff *new_rxb; 2390 u16 nta = rxq->next_to_alloc; 2391 2392 new_rxb = &rxq->rx_buff[nta]; 2393 2394 /* find next buf that can reuse a page */ 2395 nta++; 2396 rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0; 2397 2398 /* copy page reference */ 2399 *new_rxb = *old_rxb; 2400 2401 /* sync for use by the device */ 2402 dma_sync_single_range_for_device(rxq->dev, old_rxb->dma, 2403 old_rxb->page_offset, 2404 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE); 2405 } 2406 2407 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue, 2408 u32 lstatus, struct sk_buff *skb) 2409 { 2410 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean]; 2411 struct page *page = rxb->page; 2412 bool first = false; 2413 2414 if (likely(!skb)) { 2415 void *buff_addr = page_address(page) + rxb->page_offset; 2416 2417 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE); 2418 if (unlikely(!skb)) { 2419 gfar_rx_alloc_err(rx_queue); 2420 return NULL; 2421 } 2422 skb_reserve(skb, RXBUF_ALIGNMENT); 2423 first = true; 2424 } 2425 2426 dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset, 2427 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE); 2428 2429 if (gfar_add_rx_frag(rxb, lstatus, skb, first)) { 2430 /* reuse the free half of the page */ 2431 gfar_reuse_rx_page(rx_queue, rxb); 2432 } else { 2433 /* page cannot be reused, unmap it */ 2434 dma_unmap_page(rx_queue->dev, rxb->dma, 2435 PAGE_SIZE, DMA_FROM_DEVICE); 2436 } 2437 2438 /* clear rxb content */ 2439 rxb->page = NULL; 2440 2441 return skb; 2442 } 2443 2444 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) 2445 { 2446 /* If valid headers were found, and valid sums 2447 * were verified, then we tell the kernel that no 2448 * checksumming is necessary. Otherwise, it is [FIXME] 2449 */ 2450 if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) == 2451 (RXFCB_CIP | RXFCB_CTU)) 2452 skb->ip_summed = CHECKSUM_UNNECESSARY; 2453 else 2454 skb_checksum_none_assert(skb); 2455 } 2456 2457 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */ 2458 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb) 2459 { 2460 struct gfar_private *priv = netdev_priv(ndev); 2461 struct rxfcb *fcb = NULL; 2462 2463 /* fcb is at the beginning if exists */ 2464 fcb = (struct rxfcb *)skb->data; 2465 2466 /* Remove the FCB from the skb 2467 * Remove the padded bytes, if there are any 2468 */ 2469 if (priv->uses_rxfcb) 2470 skb_pull(skb, GMAC_FCB_LEN); 2471 2472 /* Get receive timestamp from the skb */ 2473 if (priv->hwts_rx_en) { 2474 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); 2475 __be64 *ns = (__be64 *)skb->data; 2476 2477 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 2478 shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns)); 2479 } 2480 2481 if (priv->padding) 2482 skb_pull(skb, priv->padding); 2483 2484 /* Trim off the FCS */ 2485 pskb_trim(skb, skb->len - ETH_FCS_LEN); 2486 2487 if (ndev->features & NETIF_F_RXCSUM) 2488 gfar_rx_checksum(skb, fcb); 2489 2490 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here. 2491 * Even if vlan rx accel is disabled, on some chips 2492 * RXFCB_VLN is pseudo randomly set. 2493 */ 2494 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX && 2495 be16_to_cpu(fcb->flags) & RXFCB_VLN) 2496 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 2497 be16_to_cpu(fcb->vlctl)); 2498 } 2499 2500 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring 2501 * until the budget/quota has been reached. Returns the number 2502 * of frames handled 2503 */ 2504 static int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, 2505 int rx_work_limit) 2506 { 2507 struct net_device *ndev = rx_queue->ndev; 2508 struct gfar_private *priv = netdev_priv(ndev); 2509 struct rxbd8 *bdp; 2510 int i, howmany = 0; 2511 struct sk_buff *skb = rx_queue->skb; 2512 int cleaned_cnt = gfar_rxbd_unused(rx_queue); 2513 unsigned int total_bytes = 0, total_pkts = 0; 2514 2515 /* Get the first full descriptor */ 2516 i = rx_queue->next_to_clean; 2517 2518 while (rx_work_limit--) { 2519 u32 lstatus; 2520 2521 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) { 2522 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt); 2523 cleaned_cnt = 0; 2524 } 2525 2526 bdp = &rx_queue->rx_bd_base[i]; 2527 lstatus = be32_to_cpu(bdp->lstatus); 2528 if (lstatus & BD_LFLAG(RXBD_EMPTY)) 2529 break; 2530 2531 /* lost RXBD_LAST descriptor due to overrun */ 2532 if (skb && 2533 (lstatus & BD_LFLAG(RXBD_FIRST))) { 2534 /* discard faulty buffer */ 2535 dev_kfree_skb(skb); 2536 skb = NULL; 2537 rx_queue->stats.rx_dropped++; 2538 2539 /* can continue normally */ 2540 } 2541 2542 /* order rx buffer descriptor reads */ 2543 rmb(); 2544 2545 /* fetch next to clean buffer from the ring */ 2546 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb); 2547 if (unlikely(!skb)) 2548 break; 2549 2550 cleaned_cnt++; 2551 howmany++; 2552 2553 if (unlikely(++i == rx_queue->rx_ring_size)) 2554 i = 0; 2555 2556 rx_queue->next_to_clean = i; 2557 2558 /* fetch next buffer if not the last in frame */ 2559 if (!(lstatus & BD_LFLAG(RXBD_LAST))) 2560 continue; 2561 2562 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) { 2563 count_errors(lstatus, ndev); 2564 2565 /* discard faulty buffer */ 2566 dev_kfree_skb(skb); 2567 skb = NULL; 2568 rx_queue->stats.rx_dropped++; 2569 continue; 2570 } 2571 2572 gfar_process_frame(ndev, skb); 2573 2574 /* Increment the number of packets */ 2575 total_pkts++; 2576 total_bytes += skb->len; 2577 2578 skb_record_rx_queue(skb, rx_queue->qindex); 2579 2580 skb->protocol = eth_type_trans(skb, ndev); 2581 2582 /* Send the packet up the stack */ 2583 napi_gro_receive(&rx_queue->grp->napi_rx, skb); 2584 2585 skb = NULL; 2586 } 2587 2588 /* Store incomplete frames for completion */ 2589 rx_queue->skb = skb; 2590 2591 rx_queue->stats.rx_packets += total_pkts; 2592 rx_queue->stats.rx_bytes += total_bytes; 2593 2594 if (cleaned_cnt) 2595 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt); 2596 2597 /* Update Last Free RxBD pointer for LFC */ 2598 if (unlikely(priv->tx_actual_en)) { 2599 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue); 2600 2601 gfar_write(rx_queue->rfbptr, bdp_dma); 2602 } 2603 2604 return howmany; 2605 } 2606 2607 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget) 2608 { 2609 struct gfar_priv_grp *gfargrp = 2610 container_of(napi, struct gfar_priv_grp, napi_rx); 2611 struct gfar __iomem *regs = gfargrp->regs; 2612 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue; 2613 int work_done = 0; 2614 2615 /* Clear IEVENT, so interrupts aren't called again 2616 * because of the packets that have already arrived 2617 */ 2618 gfar_write(®s->ievent, IEVENT_RX_MASK); 2619 2620 work_done = gfar_clean_rx_ring(rx_queue, budget); 2621 2622 if (work_done < budget) { 2623 u32 imask; 2624 napi_complete_done(napi, work_done); 2625 /* Clear the halt bit in RSTAT */ 2626 gfar_write(®s->rstat, gfargrp->rstat); 2627 2628 spin_lock_irq(&gfargrp->grplock); 2629 imask = gfar_read(®s->imask); 2630 imask |= IMASK_RX_DEFAULT; 2631 gfar_write(®s->imask, imask); 2632 spin_unlock_irq(&gfargrp->grplock); 2633 } 2634 2635 return work_done; 2636 } 2637 2638 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget) 2639 { 2640 struct gfar_priv_grp *gfargrp = 2641 container_of(napi, struct gfar_priv_grp, napi_tx); 2642 struct gfar __iomem *regs = gfargrp->regs; 2643 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue; 2644 u32 imask; 2645 2646 /* Clear IEVENT, so interrupts aren't called again 2647 * because of the packets that have already arrived 2648 */ 2649 gfar_write(®s->ievent, IEVENT_TX_MASK); 2650 2651 /* run Tx cleanup to completion */ 2652 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) 2653 gfar_clean_tx_ring(tx_queue); 2654 2655 napi_complete(napi); 2656 2657 spin_lock_irq(&gfargrp->grplock); 2658 imask = gfar_read(®s->imask); 2659 imask |= IMASK_TX_DEFAULT; 2660 gfar_write(®s->imask, imask); 2661 spin_unlock_irq(&gfargrp->grplock); 2662 2663 return 0; 2664 } 2665 2666 /* GFAR error interrupt handler */ 2667 static irqreturn_t gfar_error(int irq, void *grp_id) 2668 { 2669 struct gfar_priv_grp *gfargrp = grp_id; 2670 struct gfar __iomem *regs = gfargrp->regs; 2671 struct gfar_private *priv= gfargrp->priv; 2672 struct net_device *dev = priv->ndev; 2673 2674 /* Save ievent for future reference */ 2675 u32 events = gfar_read(®s->ievent); 2676 2677 /* Clear IEVENT */ 2678 gfar_write(®s->ievent, events & IEVENT_ERR_MASK); 2679 2680 /* Magic Packet is not an error. */ 2681 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && 2682 (events & IEVENT_MAG)) 2683 events &= ~IEVENT_MAG; 2684 2685 /* Hmm... */ 2686 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) 2687 netdev_dbg(dev, 2688 "error interrupt (ievent=0x%08x imask=0x%08x)\n", 2689 events, gfar_read(®s->imask)); 2690 2691 /* Update the error counters */ 2692 if (events & IEVENT_TXE) { 2693 dev->stats.tx_errors++; 2694 2695 if (events & IEVENT_LC) 2696 dev->stats.tx_window_errors++; 2697 if (events & IEVENT_CRL) 2698 dev->stats.tx_aborted_errors++; 2699 if (events & IEVENT_XFUN) { 2700 netif_dbg(priv, tx_err, dev, 2701 "TX FIFO underrun, packet dropped\n"); 2702 dev->stats.tx_dropped++; 2703 atomic64_inc(&priv->extra_stats.tx_underrun); 2704 2705 schedule_work(&priv->reset_task); 2706 } 2707 netif_dbg(priv, tx_err, dev, "Transmit Error\n"); 2708 } 2709 if (events & IEVENT_MSRO) { 2710 struct rmon_mib __iomem *rmon = ®s->rmon; 2711 u32 car; 2712 2713 spin_lock(&priv->rmon_overflow.lock); 2714 car = gfar_read(&rmon->car1) & CAR1_C1RDR; 2715 if (car) { 2716 priv->rmon_overflow.rdrp++; 2717 gfar_write(&rmon->car1, car); 2718 } 2719 spin_unlock(&priv->rmon_overflow.lock); 2720 } 2721 if (events & IEVENT_BSY) { 2722 dev->stats.rx_over_errors++; 2723 atomic64_inc(&priv->extra_stats.rx_bsy); 2724 2725 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n", 2726 gfar_read(®s->rstat)); 2727 } 2728 if (events & IEVENT_BABR) { 2729 dev->stats.rx_errors++; 2730 atomic64_inc(&priv->extra_stats.rx_babr); 2731 2732 netif_dbg(priv, rx_err, dev, "babbling RX error\n"); 2733 } 2734 if (events & IEVENT_EBERR) { 2735 atomic64_inc(&priv->extra_stats.eberr); 2736 netif_dbg(priv, rx_err, dev, "bus error\n"); 2737 } 2738 if (events & IEVENT_RXC) 2739 netif_dbg(priv, rx_status, dev, "control frame\n"); 2740 2741 if (events & IEVENT_BABT) { 2742 atomic64_inc(&priv->extra_stats.tx_babt); 2743 netif_dbg(priv, tx_err, dev, "babbling TX error\n"); 2744 } 2745 return IRQ_HANDLED; 2746 } 2747 2748 /* The interrupt handler for devices with one interrupt */ 2749 static irqreturn_t gfar_interrupt(int irq, void *grp_id) 2750 { 2751 struct gfar_priv_grp *gfargrp = grp_id; 2752 2753 /* Save ievent for future reference */ 2754 u32 events = gfar_read(&gfargrp->regs->ievent); 2755 2756 /* Check for reception */ 2757 if (events & IEVENT_RX_MASK) 2758 gfar_receive(irq, grp_id); 2759 2760 /* Check for transmit completion */ 2761 if (events & IEVENT_TX_MASK) 2762 gfar_transmit(irq, grp_id); 2763 2764 /* Check for errors */ 2765 if (events & IEVENT_ERR_MASK) 2766 gfar_error(irq, grp_id); 2767 2768 return IRQ_HANDLED; 2769 } 2770 2771 #ifdef CONFIG_NET_POLL_CONTROLLER 2772 /* Polling 'interrupt' - used by things like netconsole to send skbs 2773 * without having to re-enable interrupts. It's not called while 2774 * the interrupt routine is executing. 2775 */ 2776 static void gfar_netpoll(struct net_device *dev) 2777 { 2778 struct gfar_private *priv = netdev_priv(dev); 2779 int i; 2780 2781 /* If the device has multiple interrupts, run tx/rx */ 2782 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 2783 for (i = 0; i < priv->num_grps; i++) { 2784 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 2785 2786 disable_irq(gfar_irq(grp, TX)->irq); 2787 disable_irq(gfar_irq(grp, RX)->irq); 2788 disable_irq(gfar_irq(grp, ER)->irq); 2789 gfar_interrupt(gfar_irq(grp, TX)->irq, grp); 2790 enable_irq(gfar_irq(grp, ER)->irq); 2791 enable_irq(gfar_irq(grp, RX)->irq); 2792 enable_irq(gfar_irq(grp, TX)->irq); 2793 } 2794 } else { 2795 for (i = 0; i < priv->num_grps; i++) { 2796 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 2797 2798 disable_irq(gfar_irq(grp, TX)->irq); 2799 gfar_interrupt(gfar_irq(grp, TX)->irq, grp); 2800 enable_irq(gfar_irq(grp, TX)->irq); 2801 } 2802 } 2803 } 2804 #endif 2805 2806 static void free_grp_irqs(struct gfar_priv_grp *grp) 2807 { 2808 free_irq(gfar_irq(grp, TX)->irq, grp); 2809 free_irq(gfar_irq(grp, RX)->irq, grp); 2810 free_irq(gfar_irq(grp, ER)->irq, grp); 2811 } 2812 2813 static int register_grp_irqs(struct gfar_priv_grp *grp) 2814 { 2815 struct gfar_private *priv = grp->priv; 2816 struct net_device *dev = priv->ndev; 2817 int err; 2818 2819 /* If the device has multiple interrupts, register for 2820 * them. Otherwise, only register for the one 2821 */ 2822 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 2823 /* Install our interrupt handlers for Error, 2824 * Transmit, and Receive 2825 */ 2826 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0, 2827 gfar_irq(grp, ER)->name, grp); 2828 if (err < 0) { 2829 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2830 gfar_irq(grp, ER)->irq); 2831 2832 goto err_irq_fail; 2833 } 2834 enable_irq_wake(gfar_irq(grp, ER)->irq); 2835 2836 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0, 2837 gfar_irq(grp, TX)->name, grp); 2838 if (err < 0) { 2839 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2840 gfar_irq(grp, TX)->irq); 2841 goto tx_irq_fail; 2842 } 2843 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0, 2844 gfar_irq(grp, RX)->name, grp); 2845 if (err < 0) { 2846 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2847 gfar_irq(grp, RX)->irq); 2848 goto rx_irq_fail; 2849 } 2850 enable_irq_wake(gfar_irq(grp, RX)->irq); 2851 2852 } else { 2853 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0, 2854 gfar_irq(grp, TX)->name, grp); 2855 if (err < 0) { 2856 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2857 gfar_irq(grp, TX)->irq); 2858 goto err_irq_fail; 2859 } 2860 enable_irq_wake(gfar_irq(grp, TX)->irq); 2861 } 2862 2863 return 0; 2864 2865 rx_irq_fail: 2866 free_irq(gfar_irq(grp, TX)->irq, grp); 2867 tx_irq_fail: 2868 free_irq(gfar_irq(grp, ER)->irq, grp); 2869 err_irq_fail: 2870 return err; 2871 2872 } 2873 2874 static void gfar_free_irq(struct gfar_private *priv) 2875 { 2876 int i; 2877 2878 /* Free the IRQs */ 2879 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 2880 for (i = 0; i < priv->num_grps; i++) 2881 free_grp_irqs(&priv->gfargrp[i]); 2882 } else { 2883 for (i = 0; i < priv->num_grps; i++) 2884 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq, 2885 &priv->gfargrp[i]); 2886 } 2887 } 2888 2889 static int gfar_request_irq(struct gfar_private *priv) 2890 { 2891 int err, i, j; 2892 2893 for (i = 0; i < priv->num_grps; i++) { 2894 err = register_grp_irqs(&priv->gfargrp[i]); 2895 if (err) { 2896 for (j = 0; j < i; j++) 2897 free_grp_irqs(&priv->gfargrp[j]); 2898 return err; 2899 } 2900 } 2901 2902 return 0; 2903 } 2904 2905 /* Called when something needs to use the ethernet device 2906 * Returns 0 for success. 2907 */ 2908 static int gfar_enet_open(struct net_device *dev) 2909 { 2910 struct gfar_private *priv = netdev_priv(dev); 2911 int err; 2912 2913 err = init_phy(dev); 2914 if (err) 2915 return err; 2916 2917 err = gfar_request_irq(priv); 2918 if (err) 2919 return err; 2920 2921 err = startup_gfar(dev); 2922 if (err) 2923 return err; 2924 2925 return err; 2926 } 2927 2928 /* Stops the kernel queue, and halts the controller */ 2929 static int gfar_close(struct net_device *dev) 2930 { 2931 struct gfar_private *priv = netdev_priv(dev); 2932 2933 cancel_work_sync(&priv->reset_task); 2934 stop_gfar(dev); 2935 2936 /* Disconnect from the PHY */ 2937 phy_disconnect(dev->phydev); 2938 2939 gfar_free_irq(priv); 2940 2941 return 0; 2942 } 2943 2944 /* Clears each of the exact match registers to zero, so they 2945 * don't interfere with normal reception 2946 */ 2947 static void gfar_clear_exact_match(struct net_device *dev) 2948 { 2949 int idx; 2950 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; 2951 2952 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++) 2953 gfar_set_mac_for_addr(dev, idx, zero_arr); 2954 } 2955 2956 /* Update the hash table based on the current list of multicast 2957 * addresses we subscribe to. Also, change the promiscuity of 2958 * the device based on the flags (this function is called 2959 * whenever dev->flags is changed 2960 */ 2961 static void gfar_set_multi(struct net_device *dev) 2962 { 2963 struct netdev_hw_addr *ha; 2964 struct gfar_private *priv = netdev_priv(dev); 2965 struct gfar __iomem *regs = priv->gfargrp[0].regs; 2966 u32 tempval; 2967 2968 if (dev->flags & IFF_PROMISC) { 2969 /* Set RCTRL to PROM */ 2970 tempval = gfar_read(®s->rctrl); 2971 tempval |= RCTRL_PROM; 2972 gfar_write(®s->rctrl, tempval); 2973 } else { 2974 /* Set RCTRL to not PROM */ 2975 tempval = gfar_read(®s->rctrl); 2976 tempval &= ~(RCTRL_PROM); 2977 gfar_write(®s->rctrl, tempval); 2978 } 2979 2980 if (dev->flags & IFF_ALLMULTI) { 2981 /* Set the hash to rx all multicast frames */ 2982 gfar_write(®s->igaddr0, 0xffffffff); 2983 gfar_write(®s->igaddr1, 0xffffffff); 2984 gfar_write(®s->igaddr2, 0xffffffff); 2985 gfar_write(®s->igaddr3, 0xffffffff); 2986 gfar_write(®s->igaddr4, 0xffffffff); 2987 gfar_write(®s->igaddr5, 0xffffffff); 2988 gfar_write(®s->igaddr6, 0xffffffff); 2989 gfar_write(®s->igaddr7, 0xffffffff); 2990 gfar_write(®s->gaddr0, 0xffffffff); 2991 gfar_write(®s->gaddr1, 0xffffffff); 2992 gfar_write(®s->gaddr2, 0xffffffff); 2993 gfar_write(®s->gaddr3, 0xffffffff); 2994 gfar_write(®s->gaddr4, 0xffffffff); 2995 gfar_write(®s->gaddr5, 0xffffffff); 2996 gfar_write(®s->gaddr6, 0xffffffff); 2997 gfar_write(®s->gaddr7, 0xffffffff); 2998 } else { 2999 int em_num; 3000 int idx; 3001 3002 /* zero out the hash */ 3003 gfar_write(®s->igaddr0, 0x0); 3004 gfar_write(®s->igaddr1, 0x0); 3005 gfar_write(®s->igaddr2, 0x0); 3006 gfar_write(®s->igaddr3, 0x0); 3007 gfar_write(®s->igaddr4, 0x0); 3008 gfar_write(®s->igaddr5, 0x0); 3009 gfar_write(®s->igaddr6, 0x0); 3010 gfar_write(®s->igaddr7, 0x0); 3011 gfar_write(®s->gaddr0, 0x0); 3012 gfar_write(®s->gaddr1, 0x0); 3013 gfar_write(®s->gaddr2, 0x0); 3014 gfar_write(®s->gaddr3, 0x0); 3015 gfar_write(®s->gaddr4, 0x0); 3016 gfar_write(®s->gaddr5, 0x0); 3017 gfar_write(®s->gaddr6, 0x0); 3018 gfar_write(®s->gaddr7, 0x0); 3019 3020 /* If we have extended hash tables, we need to 3021 * clear the exact match registers to prepare for 3022 * setting them 3023 */ 3024 if (priv->extended_hash) { 3025 em_num = GFAR_EM_NUM + 1; 3026 gfar_clear_exact_match(dev); 3027 idx = 1; 3028 } else { 3029 idx = 0; 3030 em_num = 0; 3031 } 3032 3033 if (netdev_mc_empty(dev)) 3034 return; 3035 3036 /* Parse the list, and set the appropriate bits */ 3037 netdev_for_each_mc_addr(ha, dev) { 3038 if (idx < em_num) { 3039 gfar_set_mac_for_addr(dev, idx, ha->addr); 3040 idx++; 3041 } else 3042 gfar_set_hash_for_addr(dev, ha->addr); 3043 } 3044 } 3045 } 3046 3047 void gfar_mac_reset(struct gfar_private *priv) 3048 { 3049 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3050 u32 tempval; 3051 3052 /* Reset MAC layer */ 3053 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); 3054 3055 /* We need to delay at least 3 TX clocks */ 3056 udelay(3); 3057 3058 /* the soft reset bit is not self-resetting, so we need to 3059 * clear it before resuming normal operation 3060 */ 3061 gfar_write(®s->maccfg1, 0); 3062 3063 udelay(3); 3064 3065 gfar_rx_offload_en(priv); 3066 3067 /* Initialize the max receive frame/buffer lengths */ 3068 gfar_write(®s->maxfrm, GFAR_JUMBO_FRAME_SIZE); 3069 gfar_write(®s->mrblr, GFAR_RXB_SIZE); 3070 3071 /* Initialize the Minimum Frame Length Register */ 3072 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); 3073 3074 /* Initialize MACCFG2. */ 3075 tempval = MACCFG2_INIT_SETTINGS; 3076 3077 /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1 3078 * are marked as truncated. Avoid this by MACCFG2[Huge Frame]=1, 3079 * and by checking RxBD[LG] and discarding larger than MAXFRM. 3080 */ 3081 if (gfar_has_errata(priv, GFAR_ERRATA_74)) 3082 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK; 3083 3084 gfar_write(®s->maccfg2, tempval); 3085 3086 /* Clear mac addr hash registers */ 3087 gfar_write(®s->igaddr0, 0); 3088 gfar_write(®s->igaddr1, 0); 3089 gfar_write(®s->igaddr2, 0); 3090 gfar_write(®s->igaddr3, 0); 3091 gfar_write(®s->igaddr4, 0); 3092 gfar_write(®s->igaddr5, 0); 3093 gfar_write(®s->igaddr6, 0); 3094 gfar_write(®s->igaddr7, 0); 3095 3096 gfar_write(®s->gaddr0, 0); 3097 gfar_write(®s->gaddr1, 0); 3098 gfar_write(®s->gaddr2, 0); 3099 gfar_write(®s->gaddr3, 0); 3100 gfar_write(®s->gaddr4, 0); 3101 gfar_write(®s->gaddr5, 0); 3102 gfar_write(®s->gaddr6, 0); 3103 gfar_write(®s->gaddr7, 0); 3104 3105 if (priv->extended_hash) 3106 gfar_clear_exact_match(priv->ndev); 3107 3108 gfar_mac_rx_config(priv); 3109 3110 gfar_mac_tx_config(priv); 3111 3112 gfar_set_mac_address(priv->ndev); 3113 3114 gfar_set_multi(priv->ndev); 3115 3116 /* clear ievent and imask before configuring coalescing */ 3117 gfar_ints_disable(priv); 3118 3119 /* Configure the coalescing support */ 3120 gfar_configure_coalescing_all(priv); 3121 } 3122 3123 static void gfar_hw_init(struct gfar_private *priv) 3124 { 3125 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3126 u32 attrs; 3127 3128 /* Stop the DMA engine now, in case it was running before 3129 * (The firmware could have used it, and left it running). 3130 */ 3131 gfar_halt(priv); 3132 3133 gfar_mac_reset(priv); 3134 3135 /* Zero out the rmon mib registers if it has them */ 3136 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { 3137 memset_io(®s->rmon, 0, offsetof(struct rmon_mib, car1)); 3138 3139 /* Mask off the CAM interrupts */ 3140 gfar_write(®s->rmon.cam1, 0xffffffff); 3141 gfar_write(®s->rmon.cam2, 0xffffffff); 3142 /* Clear the CAR registers (w1c style) */ 3143 gfar_write(®s->rmon.car1, 0xffffffff); 3144 gfar_write(®s->rmon.car2, 0xffffffff); 3145 } 3146 3147 /* Initialize ECNTRL */ 3148 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); 3149 3150 /* Set the extraction length and index */ 3151 attrs = ATTRELI_EL(priv->rx_stash_size) | 3152 ATTRELI_EI(priv->rx_stash_index); 3153 3154 gfar_write(®s->attreli, attrs); 3155 3156 /* Start with defaults, and add stashing 3157 * depending on driver parameters 3158 */ 3159 attrs = ATTR_INIT_SETTINGS; 3160 3161 if (priv->bd_stash_en) 3162 attrs |= ATTR_BDSTASH; 3163 3164 if (priv->rx_stash_size != 0) 3165 attrs |= ATTR_BUFSTASH; 3166 3167 gfar_write(®s->attr, attrs); 3168 3169 /* FIFO configs */ 3170 gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR); 3171 gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE); 3172 gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF); 3173 3174 /* Program the interrupt steering regs, only for MG devices */ 3175 if (priv->num_grps > 1) 3176 gfar_write_isrg(priv); 3177 } 3178 3179 static const struct net_device_ops gfar_netdev_ops = { 3180 .ndo_open = gfar_enet_open, 3181 .ndo_start_xmit = gfar_start_xmit, 3182 .ndo_stop = gfar_close, 3183 .ndo_change_mtu = gfar_change_mtu, 3184 .ndo_set_features = gfar_set_features, 3185 .ndo_set_rx_mode = gfar_set_multi, 3186 .ndo_tx_timeout = gfar_timeout, 3187 .ndo_eth_ioctl = gfar_ioctl, 3188 .ndo_get_stats64 = gfar_get_stats64, 3189 .ndo_change_carrier = fixed_phy_change_carrier, 3190 .ndo_set_mac_address = gfar_set_mac_addr, 3191 .ndo_validate_addr = eth_validate_addr, 3192 #ifdef CONFIG_NET_POLL_CONTROLLER 3193 .ndo_poll_controller = gfar_netpoll, 3194 #endif 3195 }; 3196 3197 /* Set up the ethernet device structure, private data, 3198 * and anything else we need before we start 3199 */ 3200 static int gfar_probe(struct platform_device *ofdev) 3201 { 3202 struct device_node *np = ofdev->dev.of_node; 3203 struct net_device *dev = NULL; 3204 struct gfar_private *priv = NULL; 3205 int err = 0, i; 3206 3207 err = gfar_of_init(ofdev, &dev); 3208 3209 if (err) 3210 return err; 3211 3212 priv = netdev_priv(dev); 3213 priv->ndev = dev; 3214 priv->ofdev = ofdev; 3215 priv->dev = &ofdev->dev; 3216 SET_NETDEV_DEV(dev, &ofdev->dev); 3217 3218 INIT_WORK(&priv->reset_task, gfar_reset_task); 3219 3220 platform_set_drvdata(ofdev, priv); 3221 3222 gfar_detect_errata(priv); 3223 3224 /* Set the dev->base_addr to the gfar reg region */ 3225 dev->base_addr = (unsigned long) priv->gfargrp[0].regs; 3226 3227 /* Fill in the dev structure */ 3228 dev->watchdog_timeo = TX_TIMEOUT; 3229 /* MTU range: 50 - 9586 */ 3230 dev->mtu = 1500; 3231 dev->min_mtu = 50; 3232 dev->max_mtu = GFAR_JUMBO_FRAME_SIZE - ETH_HLEN; 3233 dev->netdev_ops = &gfar_netdev_ops; 3234 dev->ethtool_ops = &gfar_ethtool_ops; 3235 3236 /* Register for napi ...We are registering NAPI for each grp */ 3237 for (i = 0; i < priv->num_grps; i++) { 3238 netif_napi_add(dev, &priv->gfargrp[i].napi_rx, 3239 gfar_poll_rx_sq); 3240 netif_napi_add_tx_weight(dev, &priv->gfargrp[i].napi_tx, 3241 gfar_poll_tx_sq, 2); 3242 } 3243 3244 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { 3245 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | 3246 NETIF_F_RXCSUM; 3247 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | 3248 NETIF_F_RXCSUM | NETIF_F_HIGHDMA; 3249 } 3250 3251 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { 3252 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 3253 NETIF_F_HW_VLAN_CTAG_RX; 3254 dev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3255 } 3256 3257 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 3258 3259 gfar_init_addr_hash_table(priv); 3260 3261 /* Insert receive time stamps into padding alignment bytes, and 3262 * plus 2 bytes padding to ensure the cpu alignment. 3263 */ 3264 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) 3265 priv->padding = 8 + DEFAULT_PADDING; 3266 3267 if (dev->features & NETIF_F_IP_CSUM || 3268 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) 3269 dev->needed_headroom = GMAC_FCB_LEN + GMAC_TXPAL_LEN; 3270 3271 /* Initializing some of the rx/tx queue level parameters */ 3272 for (i = 0; i < priv->num_tx_queues; i++) { 3273 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; 3274 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; 3275 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; 3276 priv->tx_queue[i]->txic = DEFAULT_TXIC; 3277 } 3278 3279 for (i = 0; i < priv->num_rx_queues; i++) { 3280 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; 3281 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; 3282 priv->rx_queue[i]->rxic = DEFAULT_RXIC; 3283 } 3284 3285 /* Always enable rx filer if available */ 3286 priv->rx_filer_enable = 3287 (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0; 3288 /* Enable most messages by default */ 3289 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; 3290 /* use pritority h/w tx queue scheduling for single queue devices */ 3291 if (priv->num_tx_queues == 1) 3292 priv->prio_sched_en = 1; 3293 3294 set_bit(GFAR_DOWN, &priv->state); 3295 3296 gfar_hw_init(priv); 3297 3298 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { 3299 struct rmon_mib __iomem *rmon = &priv->gfargrp[0].regs->rmon; 3300 3301 spin_lock_init(&priv->rmon_overflow.lock); 3302 priv->rmon_overflow.imask = IMASK_MSRO; 3303 gfar_write(&rmon->cam1, gfar_read(&rmon->cam1) & ~CAM1_M1RDR); 3304 } 3305 3306 /* Carrier starts down, phylib will bring it up */ 3307 netif_carrier_off(dev); 3308 3309 err = register_netdev(dev); 3310 3311 if (err) { 3312 pr_err("%s: Cannot register net device, aborting\n", dev->name); 3313 goto register_fail; 3314 } 3315 3316 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) 3317 priv->wol_supported |= GFAR_WOL_MAGIC; 3318 3319 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) && 3320 priv->rx_filer_enable) 3321 priv->wol_supported |= GFAR_WOL_FILER_UCAST; 3322 3323 device_set_wakeup_capable(&ofdev->dev, priv->wol_supported); 3324 3325 /* fill out IRQ number and name fields */ 3326 for (i = 0; i < priv->num_grps; i++) { 3327 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 3328 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 3329 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s", 3330 dev->name, "_g", '0' + i, "_tx"); 3331 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s", 3332 dev->name, "_g", '0' + i, "_rx"); 3333 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s", 3334 dev->name, "_g", '0' + i, "_er"); 3335 } else 3336 strcpy(gfar_irq(grp, TX)->name, dev->name); 3337 } 3338 3339 /* Initialize the filer table */ 3340 gfar_init_filer_table(priv); 3341 3342 /* Print out the device info */ 3343 netdev_info(dev, "mac: %pM\n", dev->dev_addr); 3344 3345 /* Even more device info helps when determining which kernel 3346 * provided which set of benchmarks. 3347 */ 3348 netdev_info(dev, "Running with NAPI enabled\n"); 3349 for (i = 0; i < priv->num_rx_queues; i++) 3350 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n", 3351 i, priv->rx_queue[i]->rx_ring_size); 3352 for (i = 0; i < priv->num_tx_queues; i++) 3353 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n", 3354 i, priv->tx_queue[i]->tx_ring_size); 3355 3356 return 0; 3357 3358 register_fail: 3359 if (of_phy_is_fixed_link(np)) 3360 of_phy_deregister_fixed_link(np); 3361 unmap_group_regs(priv); 3362 gfar_free_rx_queues(priv); 3363 gfar_free_tx_queues(priv); 3364 of_node_put(priv->phy_node); 3365 of_node_put(priv->tbi_node); 3366 free_gfar_dev(priv); 3367 return err; 3368 } 3369 3370 static void gfar_remove(struct platform_device *ofdev) 3371 { 3372 struct gfar_private *priv = platform_get_drvdata(ofdev); 3373 struct device_node *np = ofdev->dev.of_node; 3374 3375 of_node_put(priv->phy_node); 3376 of_node_put(priv->tbi_node); 3377 3378 unregister_netdev(priv->ndev); 3379 3380 if (of_phy_is_fixed_link(np)) 3381 of_phy_deregister_fixed_link(np); 3382 3383 unmap_group_regs(priv); 3384 gfar_free_rx_queues(priv); 3385 gfar_free_tx_queues(priv); 3386 free_gfar_dev(priv); 3387 } 3388 3389 #ifdef CONFIG_PM 3390 3391 static void __gfar_filer_disable(struct gfar_private *priv) 3392 { 3393 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3394 u32 temp; 3395 3396 temp = gfar_read(®s->rctrl); 3397 temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT); 3398 gfar_write(®s->rctrl, temp); 3399 } 3400 3401 static void __gfar_filer_enable(struct gfar_private *priv) 3402 { 3403 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3404 u32 temp; 3405 3406 temp = gfar_read(®s->rctrl); 3407 temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT; 3408 gfar_write(®s->rctrl, temp); 3409 } 3410 3411 /* Filer rules implementing wol capabilities */ 3412 static void gfar_filer_config_wol(struct gfar_private *priv) 3413 { 3414 unsigned int i; 3415 u32 rqfcr; 3416 3417 __gfar_filer_disable(priv); 3418 3419 /* clear the filer table, reject any packet by default */ 3420 rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH; 3421 for (i = 0; i <= MAX_FILER_IDX; i++) 3422 gfar_write_filer(priv, i, rqfcr, 0); 3423 3424 i = 0; 3425 if (priv->wol_opts & GFAR_WOL_FILER_UCAST) { 3426 /* unicast packet, accept it */ 3427 struct net_device *ndev = priv->ndev; 3428 /* get the default rx queue index */ 3429 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex; 3430 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) | 3431 (ndev->dev_addr[1] << 8) | 3432 ndev->dev_addr[2]; 3433 3434 rqfcr = (qindex << 10) | RQFCR_AND | 3435 RQFCR_CMP_EXACT | RQFCR_PID_DAH; 3436 3437 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr); 3438 3439 dest_mac_addr = (ndev->dev_addr[3] << 16) | 3440 (ndev->dev_addr[4] << 8) | 3441 ndev->dev_addr[5]; 3442 rqfcr = (qindex << 10) | RQFCR_GPI | 3443 RQFCR_CMP_EXACT | RQFCR_PID_DAL; 3444 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr); 3445 } 3446 3447 __gfar_filer_enable(priv); 3448 } 3449 3450 static void gfar_filer_restore_table(struct gfar_private *priv) 3451 { 3452 u32 rqfcr, rqfpr; 3453 unsigned int i; 3454 3455 __gfar_filer_disable(priv); 3456 3457 for (i = 0; i <= MAX_FILER_IDX; i++) { 3458 rqfcr = priv->ftp_rqfcr[i]; 3459 rqfpr = priv->ftp_rqfpr[i]; 3460 gfar_write_filer(priv, i, rqfcr, rqfpr); 3461 } 3462 3463 __gfar_filer_enable(priv); 3464 } 3465 3466 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */ 3467 static void gfar_start_wol_filer(struct gfar_private *priv) 3468 { 3469 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3470 u32 tempval; 3471 int i = 0; 3472 3473 /* Enable Rx hw queues */ 3474 gfar_write(®s->rqueue, priv->rqueue); 3475 3476 /* Initialize DMACTRL to have WWR and WOP */ 3477 tempval = gfar_read(®s->dmactrl); 3478 tempval |= DMACTRL_INIT_SETTINGS; 3479 gfar_write(®s->dmactrl, tempval); 3480 3481 /* Make sure we aren't stopped */ 3482 tempval = gfar_read(®s->dmactrl); 3483 tempval &= ~DMACTRL_GRS; 3484 gfar_write(®s->dmactrl, tempval); 3485 3486 for (i = 0; i < priv->num_grps; i++) { 3487 regs = priv->gfargrp[i].regs; 3488 /* Clear RHLT, so that the DMA starts polling now */ 3489 gfar_write(®s->rstat, priv->gfargrp[i].rstat); 3490 /* enable the Filer General Purpose Interrupt */ 3491 gfar_write(®s->imask, IMASK_FGPI); 3492 } 3493 3494 /* Enable Rx DMA */ 3495 tempval = gfar_read(®s->maccfg1); 3496 tempval |= MACCFG1_RX_EN; 3497 gfar_write(®s->maccfg1, tempval); 3498 } 3499 3500 static int gfar_suspend(struct device *dev) 3501 { 3502 struct gfar_private *priv = dev_get_drvdata(dev); 3503 struct net_device *ndev = priv->ndev; 3504 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3505 u32 tempval; 3506 u16 wol = priv->wol_opts; 3507 3508 if (!netif_running(ndev)) 3509 return 0; 3510 3511 disable_napi(priv); 3512 netif_tx_lock(ndev); 3513 netif_device_detach(ndev); 3514 netif_tx_unlock(ndev); 3515 3516 gfar_halt(priv); 3517 3518 if (wol & GFAR_WOL_MAGIC) { 3519 /* Enable interrupt on Magic Packet */ 3520 gfar_write(®s->imask, IMASK_MAG); 3521 3522 /* Enable Magic Packet mode */ 3523 tempval = gfar_read(®s->maccfg2); 3524 tempval |= MACCFG2_MPEN; 3525 gfar_write(®s->maccfg2, tempval); 3526 3527 /* re-enable the Rx block */ 3528 tempval = gfar_read(®s->maccfg1); 3529 tempval |= MACCFG1_RX_EN; 3530 gfar_write(®s->maccfg1, tempval); 3531 3532 } else if (wol & GFAR_WOL_FILER_UCAST) { 3533 gfar_filer_config_wol(priv); 3534 gfar_start_wol_filer(priv); 3535 3536 } else { 3537 phy_stop(ndev->phydev); 3538 } 3539 3540 return 0; 3541 } 3542 3543 static int gfar_resume(struct device *dev) 3544 { 3545 struct gfar_private *priv = dev_get_drvdata(dev); 3546 struct net_device *ndev = priv->ndev; 3547 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3548 u32 tempval; 3549 u16 wol = priv->wol_opts; 3550 3551 if (!netif_running(ndev)) 3552 return 0; 3553 3554 if (wol & GFAR_WOL_MAGIC) { 3555 /* Disable Magic Packet mode */ 3556 tempval = gfar_read(®s->maccfg2); 3557 tempval &= ~MACCFG2_MPEN; 3558 gfar_write(®s->maccfg2, tempval); 3559 3560 } else if (wol & GFAR_WOL_FILER_UCAST) { 3561 /* need to stop rx only, tx is already down */ 3562 gfar_halt(priv); 3563 gfar_filer_restore_table(priv); 3564 3565 } else { 3566 phy_start(ndev->phydev); 3567 } 3568 3569 gfar_start(priv); 3570 3571 netif_device_attach(ndev); 3572 enable_napi(priv); 3573 3574 return 0; 3575 } 3576 3577 static int gfar_restore(struct device *dev) 3578 { 3579 struct gfar_private *priv = dev_get_drvdata(dev); 3580 struct net_device *ndev = priv->ndev; 3581 3582 if (!netif_running(ndev)) { 3583 netif_device_attach(ndev); 3584 3585 return 0; 3586 } 3587 3588 gfar_init_bds(ndev); 3589 3590 gfar_mac_reset(priv); 3591 3592 gfar_init_tx_rx_base(priv); 3593 3594 gfar_start(priv); 3595 3596 priv->oldlink = 0; 3597 priv->oldspeed = 0; 3598 priv->oldduplex = -1; 3599 3600 if (ndev->phydev) 3601 phy_start(ndev->phydev); 3602 3603 netif_device_attach(ndev); 3604 enable_napi(priv); 3605 3606 return 0; 3607 } 3608 3609 static const struct dev_pm_ops gfar_pm_ops = { 3610 .suspend = gfar_suspend, 3611 .resume = gfar_resume, 3612 .freeze = gfar_suspend, 3613 .thaw = gfar_resume, 3614 .restore = gfar_restore, 3615 }; 3616 3617 #define GFAR_PM_OPS (&gfar_pm_ops) 3618 3619 #else 3620 3621 #define GFAR_PM_OPS NULL 3622 3623 #endif 3624 3625 static const struct of_device_id gfar_match[] = 3626 { 3627 { 3628 .type = "network", 3629 .compatible = "gianfar", 3630 }, 3631 { 3632 .compatible = "fsl,etsec2", 3633 }, 3634 {}, 3635 }; 3636 MODULE_DEVICE_TABLE(of, gfar_match); 3637 3638 /* Structure for a device driver */ 3639 static struct platform_driver gfar_driver = { 3640 .driver = { 3641 .name = "fsl-gianfar", 3642 .pm = GFAR_PM_OPS, 3643 .of_match_table = gfar_match, 3644 }, 3645 .probe = gfar_probe, 3646 .remove = gfar_remove, 3647 }; 3648 3649 module_platform_driver(gfar_driver); 3650