1 /* 2 * FCC driver for Motorola MPC82xx (PQ2). 3 * 4 * Copyright (c) 2003 Intracom S.A. 5 * by Pantelis Antoniou <panto@intracom.gr> 6 * 7 * 2005 (c) MontaVista Software, Inc. 8 * Vitaly Bordug <vbordug@ru.mvista.com> 9 * 10 * This file is licensed under the terms of the GNU General Public License 11 * version 2. This program is licensed "as is" without any warranty of any 12 * kind, whether express or implied. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/types.h> 18 #include <linux/string.h> 19 #include <linux/ptrace.h> 20 #include <linux/errno.h> 21 #include <linux/ioport.h> 22 #include <linux/interrupt.h> 23 #include <linux/delay.h> 24 #include <linux/netdevice.h> 25 #include <linux/etherdevice.h> 26 #include <linux/skbuff.h> 27 #include <linux/spinlock.h> 28 #include <linux/mii.h> 29 #include <linux/ethtool.h> 30 #include <linux/bitops.h> 31 #include <linux/fs.h> 32 #include <linux/platform_device.h> 33 #include <linux/phy.h> 34 #include <linux/of_address.h> 35 #include <linux/of_device.h> 36 #include <linux/of_irq.h> 37 #include <linux/gfp.h> 38 39 #include <asm/immap_cpm2.h> 40 #include <asm/mpc8260.h> 41 #include <asm/cpm2.h> 42 43 #include <asm/pgtable.h> 44 #include <asm/irq.h> 45 #include <asm/uaccess.h> 46 47 #include "fs_enet.h" 48 49 /*************************************************/ 50 51 /* FCC access macros */ 52 53 /* write, read, set bits, clear bits */ 54 #define W32(_p, _m, _v) out_be32(&(_p)->_m, (_v)) 55 #define R32(_p, _m) in_be32(&(_p)->_m) 56 #define S32(_p, _m, _v) W32(_p, _m, R32(_p, _m) | (_v)) 57 #define C32(_p, _m, _v) W32(_p, _m, R32(_p, _m) & ~(_v)) 58 59 #define W16(_p, _m, _v) out_be16(&(_p)->_m, (_v)) 60 #define R16(_p, _m) in_be16(&(_p)->_m) 61 #define S16(_p, _m, _v) W16(_p, _m, R16(_p, _m) | (_v)) 62 #define C16(_p, _m, _v) W16(_p, _m, R16(_p, _m) & ~(_v)) 63 64 #define W8(_p, _m, _v) out_8(&(_p)->_m, (_v)) 65 #define R8(_p, _m) in_8(&(_p)->_m) 66 #define S8(_p, _m, _v) W8(_p, _m, R8(_p, _m) | (_v)) 67 #define C8(_p, _m, _v) W8(_p, _m, R8(_p, _m) & ~(_v)) 68 69 /*************************************************/ 70 71 #define FCC_MAX_MULTICAST_ADDRS 64 72 73 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) 74 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) 75 #define mk_mii_end 0 76 77 #define MAX_CR_CMD_LOOPS 10000 78 79 static inline int fcc_cr_cmd(struct fs_enet_private *fep, u32 op) 80 { 81 const struct fs_platform_info *fpi = fep->fpi; 82 83 return cpm_command(fpi->cp_command, op); 84 } 85 86 static int do_pd_setup(struct fs_enet_private *fep) 87 { 88 struct platform_device *ofdev = to_platform_device(fep->dev); 89 struct fs_platform_info *fpi = fep->fpi; 90 int ret = -EINVAL; 91 92 fep->interrupt = irq_of_parse_and_map(ofdev->dev.of_node, 0); 93 if (fep->interrupt == NO_IRQ) 94 goto out; 95 96 fep->fcc.fccp = of_iomap(ofdev->dev.of_node, 0); 97 if (!fep->fcc.fccp) 98 goto out; 99 100 fep->fcc.ep = of_iomap(ofdev->dev.of_node, 1); 101 if (!fep->fcc.ep) 102 goto out_fccp; 103 104 fep->fcc.fcccp = of_iomap(ofdev->dev.of_node, 2); 105 if (!fep->fcc.fcccp) 106 goto out_ep; 107 108 fep->fcc.mem = (void __iomem *)cpm2_immr; 109 fpi->dpram_offset = cpm_dpalloc(128, 32); 110 if (IS_ERR_VALUE(fpi->dpram_offset)) { 111 ret = fpi->dpram_offset; 112 goto out_fcccp; 113 } 114 115 return 0; 116 117 out_fcccp: 118 iounmap(fep->fcc.fcccp); 119 out_ep: 120 iounmap(fep->fcc.ep); 121 out_fccp: 122 iounmap(fep->fcc.fccp); 123 out: 124 return ret; 125 } 126 127 #define FCC_NAPI_RX_EVENT_MSK (FCC_ENET_RXF | FCC_ENET_RXB) 128 #define FCC_RX_EVENT (FCC_ENET_RXF) 129 #define FCC_TX_EVENT (FCC_ENET_TXB) 130 #define FCC_ERR_EVENT_MSK (FCC_ENET_TXE) 131 132 static int setup_data(struct net_device *dev) 133 { 134 struct fs_enet_private *fep = netdev_priv(dev); 135 136 if (do_pd_setup(fep) != 0) 137 return -EINVAL; 138 139 fep->ev_napi_rx = FCC_NAPI_RX_EVENT_MSK; 140 fep->ev_rx = FCC_RX_EVENT; 141 fep->ev_tx = FCC_TX_EVENT; 142 fep->ev_err = FCC_ERR_EVENT_MSK; 143 144 return 0; 145 } 146 147 static int allocate_bd(struct net_device *dev) 148 { 149 struct fs_enet_private *fep = netdev_priv(dev); 150 const struct fs_platform_info *fpi = fep->fpi; 151 152 fep->ring_base = (void __iomem __force *)dma_alloc_coherent(fep->dev, 153 (fpi->tx_ring + fpi->rx_ring) * 154 sizeof(cbd_t), &fep->ring_mem_addr, 155 GFP_KERNEL); 156 if (fep->ring_base == NULL) 157 return -ENOMEM; 158 159 return 0; 160 } 161 162 static void free_bd(struct net_device *dev) 163 { 164 struct fs_enet_private *fep = netdev_priv(dev); 165 const struct fs_platform_info *fpi = fep->fpi; 166 167 if (fep->ring_base) 168 dma_free_coherent(fep->dev, 169 (fpi->tx_ring + fpi->rx_ring) * sizeof(cbd_t), 170 (void __force *)fep->ring_base, fep->ring_mem_addr); 171 } 172 173 static void cleanup_data(struct net_device *dev) 174 { 175 /* nothing */ 176 } 177 178 static void set_promiscuous_mode(struct net_device *dev) 179 { 180 struct fs_enet_private *fep = netdev_priv(dev); 181 fcc_t __iomem *fccp = fep->fcc.fccp; 182 183 S32(fccp, fcc_fpsmr, FCC_PSMR_PRO); 184 } 185 186 static void set_multicast_start(struct net_device *dev) 187 { 188 struct fs_enet_private *fep = netdev_priv(dev); 189 fcc_enet_t __iomem *ep = fep->fcc.ep; 190 191 W32(ep, fen_gaddrh, 0); 192 W32(ep, fen_gaddrl, 0); 193 } 194 195 static void set_multicast_one(struct net_device *dev, const u8 *mac) 196 { 197 struct fs_enet_private *fep = netdev_priv(dev); 198 fcc_enet_t __iomem *ep = fep->fcc.ep; 199 u16 taddrh, taddrm, taddrl; 200 201 taddrh = ((u16)mac[5] << 8) | mac[4]; 202 taddrm = ((u16)mac[3] << 8) | mac[2]; 203 taddrl = ((u16)mac[1] << 8) | mac[0]; 204 205 W16(ep, fen_taddrh, taddrh); 206 W16(ep, fen_taddrm, taddrm); 207 W16(ep, fen_taddrl, taddrl); 208 fcc_cr_cmd(fep, CPM_CR_SET_GADDR); 209 } 210 211 static void set_multicast_finish(struct net_device *dev) 212 { 213 struct fs_enet_private *fep = netdev_priv(dev); 214 fcc_t __iomem *fccp = fep->fcc.fccp; 215 fcc_enet_t __iomem *ep = fep->fcc.ep; 216 217 /* clear promiscuous always */ 218 C32(fccp, fcc_fpsmr, FCC_PSMR_PRO); 219 220 /* if all multi or too many multicasts; just enable all */ 221 if ((dev->flags & IFF_ALLMULTI) != 0 || 222 netdev_mc_count(dev) > FCC_MAX_MULTICAST_ADDRS) { 223 224 W32(ep, fen_gaddrh, 0xffffffff); 225 W32(ep, fen_gaddrl, 0xffffffff); 226 } 227 228 /* read back */ 229 fep->fcc.gaddrh = R32(ep, fen_gaddrh); 230 fep->fcc.gaddrl = R32(ep, fen_gaddrl); 231 } 232 233 static void set_multicast_list(struct net_device *dev) 234 { 235 struct netdev_hw_addr *ha; 236 237 if ((dev->flags & IFF_PROMISC) == 0) { 238 set_multicast_start(dev); 239 netdev_for_each_mc_addr(ha, dev) 240 set_multicast_one(dev, ha->addr); 241 set_multicast_finish(dev); 242 } else 243 set_promiscuous_mode(dev); 244 } 245 246 static void restart(struct net_device *dev) 247 { 248 struct fs_enet_private *fep = netdev_priv(dev); 249 const struct fs_platform_info *fpi = fep->fpi; 250 fcc_t __iomem *fccp = fep->fcc.fccp; 251 fcc_c_t __iomem *fcccp = fep->fcc.fcccp; 252 fcc_enet_t __iomem *ep = fep->fcc.ep; 253 dma_addr_t rx_bd_base_phys, tx_bd_base_phys; 254 u16 paddrh, paddrm, paddrl; 255 const unsigned char *mac; 256 int i; 257 258 C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); 259 260 /* clear everything (slow & steady does it) */ 261 for (i = 0; i < sizeof(*ep); i++) 262 out_8((u8 __iomem *)ep + i, 0); 263 264 /* get physical address */ 265 rx_bd_base_phys = fep->ring_mem_addr; 266 tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring; 267 268 /* point to bds */ 269 W32(ep, fen_genfcc.fcc_rbase, rx_bd_base_phys); 270 W32(ep, fen_genfcc.fcc_tbase, tx_bd_base_phys); 271 272 /* Set maximum bytes per receive buffer. 273 * It must be a multiple of 32. 274 */ 275 W16(ep, fen_genfcc.fcc_mrblr, PKT_MAXBLR_SIZE); 276 277 W32(ep, fen_genfcc.fcc_rstate, (CPMFCR_GBL | CPMFCR_EB) << 24); 278 W32(ep, fen_genfcc.fcc_tstate, (CPMFCR_GBL | CPMFCR_EB) << 24); 279 280 /* Allocate space in the reserved FCC area of DPRAM for the 281 * internal buffers. No one uses this space (yet), so we 282 * can do this. Later, we will add resource management for 283 * this area. 284 */ 285 286 W16(ep, fen_genfcc.fcc_riptr, fpi->dpram_offset); 287 W16(ep, fen_genfcc.fcc_tiptr, fpi->dpram_offset + 32); 288 289 W16(ep, fen_padptr, fpi->dpram_offset + 64); 290 291 /* fill with special symbol... */ 292 memset_io(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32); 293 294 W32(ep, fen_genfcc.fcc_rbptr, 0); 295 W32(ep, fen_genfcc.fcc_tbptr, 0); 296 W32(ep, fen_genfcc.fcc_rcrc, 0); 297 W32(ep, fen_genfcc.fcc_tcrc, 0); 298 W16(ep, fen_genfcc.fcc_res1, 0); 299 W32(ep, fen_genfcc.fcc_res2, 0); 300 301 /* no CAM */ 302 W32(ep, fen_camptr, 0); 303 304 /* Set CRC preset and mask */ 305 W32(ep, fen_cmask, 0xdebb20e3); 306 W32(ep, fen_cpres, 0xffffffff); 307 308 W32(ep, fen_crcec, 0); /* CRC Error counter */ 309 W32(ep, fen_alec, 0); /* alignment error counter */ 310 W32(ep, fen_disfc, 0); /* discard frame counter */ 311 W16(ep, fen_retlim, 15); /* Retry limit threshold */ 312 W16(ep, fen_pper, 0); /* Normal persistence */ 313 314 /* set group address */ 315 W32(ep, fen_gaddrh, fep->fcc.gaddrh); 316 W32(ep, fen_gaddrl, fep->fcc.gaddrh); 317 318 /* Clear hash filter tables */ 319 W32(ep, fen_iaddrh, 0); 320 W32(ep, fen_iaddrl, 0); 321 322 /* Clear the Out-of-sequence TxBD */ 323 W16(ep, fen_tfcstat, 0); 324 W16(ep, fen_tfclen, 0); 325 W32(ep, fen_tfcptr, 0); 326 327 W16(ep, fen_mflr, PKT_MAXBUF_SIZE); /* maximum frame length register */ 328 W16(ep, fen_minflr, PKT_MINBUF_SIZE); /* minimum frame length register */ 329 330 /* set address */ 331 mac = dev->dev_addr; 332 paddrh = ((u16)mac[5] << 8) | mac[4]; 333 paddrm = ((u16)mac[3] << 8) | mac[2]; 334 paddrl = ((u16)mac[1] << 8) | mac[0]; 335 336 W16(ep, fen_paddrh, paddrh); 337 W16(ep, fen_paddrm, paddrm); 338 W16(ep, fen_paddrl, paddrl); 339 340 W16(ep, fen_taddrh, 0); 341 W16(ep, fen_taddrm, 0); 342 W16(ep, fen_taddrl, 0); 343 344 W16(ep, fen_maxd1, 1520); /* maximum DMA1 length */ 345 W16(ep, fen_maxd2, 1520); /* maximum DMA2 length */ 346 347 /* Clear stat counters, in case we ever enable RMON */ 348 W32(ep, fen_octc, 0); 349 W32(ep, fen_colc, 0); 350 W32(ep, fen_broc, 0); 351 W32(ep, fen_mulc, 0); 352 W32(ep, fen_uspc, 0); 353 W32(ep, fen_frgc, 0); 354 W32(ep, fen_ospc, 0); 355 W32(ep, fen_jbrc, 0); 356 W32(ep, fen_p64c, 0); 357 W32(ep, fen_p65c, 0); 358 W32(ep, fen_p128c, 0); 359 W32(ep, fen_p256c, 0); 360 W32(ep, fen_p512c, 0); 361 W32(ep, fen_p1024c, 0); 362 363 W16(ep, fen_rfthr, 0); /* Suggested by manual */ 364 W16(ep, fen_rfcnt, 0); 365 W16(ep, fen_cftype, 0); 366 367 fs_init_bds(dev); 368 369 /* adjust to speed (for RMII mode) */ 370 if (fpi->use_rmii) { 371 if (fep->phydev->speed == 100) 372 C8(fcccp, fcc_gfemr, 0x20); 373 else 374 S8(fcccp, fcc_gfemr, 0x20); 375 } 376 377 fcc_cr_cmd(fep, CPM_CR_INIT_TRX); 378 379 /* clear events */ 380 W16(fccp, fcc_fcce, 0xffff); 381 382 /* Enable interrupts we wish to service */ 383 W16(fccp, fcc_fccm, FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB); 384 385 /* Set GFMR to enable Ethernet operating mode */ 386 W32(fccp, fcc_gfmr, FCC_GFMR_TCI | FCC_GFMR_MODE_ENET); 387 388 /* set sync/delimiters */ 389 W16(fccp, fcc_fdsr, 0xd555); 390 391 W32(fccp, fcc_fpsmr, FCC_PSMR_ENCRC); 392 393 if (fpi->use_rmii) 394 S32(fccp, fcc_fpsmr, FCC_PSMR_RMII); 395 396 /* adjust to duplex mode */ 397 if (fep->phydev->duplex) 398 S32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB); 399 else 400 C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB); 401 402 /* Restore multicast and promiscuous settings */ 403 set_multicast_list(dev); 404 405 S32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); 406 } 407 408 static void stop(struct net_device *dev) 409 { 410 struct fs_enet_private *fep = netdev_priv(dev); 411 fcc_t __iomem *fccp = fep->fcc.fccp; 412 413 /* stop ethernet */ 414 C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); 415 416 /* clear events */ 417 W16(fccp, fcc_fcce, 0xffff); 418 419 /* clear interrupt mask */ 420 W16(fccp, fcc_fccm, 0); 421 422 fs_cleanup_bds(dev); 423 } 424 425 static void napi_clear_rx_event(struct net_device *dev) 426 { 427 struct fs_enet_private *fep = netdev_priv(dev); 428 fcc_t __iomem *fccp = fep->fcc.fccp; 429 430 W16(fccp, fcc_fcce, FCC_NAPI_RX_EVENT_MSK); 431 } 432 433 static void napi_enable_rx(struct net_device *dev) 434 { 435 struct fs_enet_private *fep = netdev_priv(dev); 436 fcc_t __iomem *fccp = fep->fcc.fccp; 437 438 S16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK); 439 } 440 441 static void napi_disable_rx(struct net_device *dev) 442 { 443 struct fs_enet_private *fep = netdev_priv(dev); 444 fcc_t __iomem *fccp = fep->fcc.fccp; 445 446 C16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK); 447 } 448 449 static void rx_bd_done(struct net_device *dev) 450 { 451 /* nothing */ 452 } 453 454 static void tx_kickstart(struct net_device *dev) 455 { 456 struct fs_enet_private *fep = netdev_priv(dev); 457 fcc_t __iomem *fccp = fep->fcc.fccp; 458 459 S16(fccp, fcc_ftodr, 0x8000); 460 } 461 462 static u32 get_int_events(struct net_device *dev) 463 { 464 struct fs_enet_private *fep = netdev_priv(dev); 465 fcc_t __iomem *fccp = fep->fcc.fccp; 466 467 return (u32)R16(fccp, fcc_fcce); 468 } 469 470 static void clear_int_events(struct net_device *dev, u32 int_events) 471 { 472 struct fs_enet_private *fep = netdev_priv(dev); 473 fcc_t __iomem *fccp = fep->fcc.fccp; 474 475 W16(fccp, fcc_fcce, int_events & 0xffff); 476 } 477 478 static void ev_error(struct net_device *dev, u32 int_events) 479 { 480 struct fs_enet_private *fep = netdev_priv(dev); 481 482 dev_warn(fep->dev, "FS_ENET ERROR(s) 0x%x\n", int_events); 483 } 484 485 static int get_regs(struct net_device *dev, void *p, int *sizep) 486 { 487 struct fs_enet_private *fep = netdev_priv(dev); 488 489 if (*sizep < sizeof(fcc_t) + sizeof(fcc_enet_t) + 1) 490 return -EINVAL; 491 492 memcpy_fromio(p, fep->fcc.fccp, sizeof(fcc_t)); 493 p = (char *)p + sizeof(fcc_t); 494 495 memcpy_fromio(p, fep->fcc.ep, sizeof(fcc_enet_t)); 496 p = (char *)p + sizeof(fcc_enet_t); 497 498 memcpy_fromio(p, fep->fcc.fcccp, 1); 499 return 0; 500 } 501 502 static int get_regs_len(struct net_device *dev) 503 { 504 return sizeof(fcc_t) + sizeof(fcc_enet_t) + 1; 505 } 506 507 /* Some transmit errors cause the transmitter to shut 508 * down. We now issue a restart transmit. 509 * Also, to workaround 8260 device erratum CPM37, we must 510 * disable and then re-enable the transmitterfollowing a 511 * Late Collision, Underrun, or Retry Limit error. 512 * In addition, tbptr may point beyond BDs beyond still marked 513 * as ready due to internal pipelining, so we need to look back 514 * through the BDs and adjust tbptr to point to the last BD 515 * marked as ready. This may result in some buffers being 516 * retransmitted. 517 */ 518 static void tx_restart(struct net_device *dev) 519 { 520 struct fs_enet_private *fep = netdev_priv(dev); 521 fcc_t __iomem *fccp = fep->fcc.fccp; 522 const struct fs_platform_info *fpi = fep->fpi; 523 fcc_enet_t __iomem *ep = fep->fcc.ep; 524 cbd_t __iomem *curr_tbptr; 525 cbd_t __iomem *recheck_bd; 526 cbd_t __iomem *prev_bd; 527 cbd_t __iomem *last_tx_bd; 528 529 last_tx_bd = fep->tx_bd_base + (fpi->tx_ring * sizeof(cbd_t)); 530 531 /* get the current bd held in TBPTR and scan back from this point */ 532 recheck_bd = curr_tbptr = (cbd_t __iomem *) 533 ((R32(ep, fen_genfcc.fcc_tbptr) - fep->ring_mem_addr) + 534 fep->ring_base); 535 536 prev_bd = (recheck_bd == fep->tx_bd_base) ? last_tx_bd : recheck_bd - 1; 537 538 /* Move through the bds in reverse, look for the earliest buffer 539 * that is not ready. Adjust TBPTR to the following buffer */ 540 while ((CBDR_SC(prev_bd) & BD_ENET_TX_READY) != 0) { 541 /* Go back one buffer */ 542 recheck_bd = prev_bd; 543 544 /* update the previous buffer */ 545 prev_bd = (prev_bd == fep->tx_bd_base) ? last_tx_bd : prev_bd - 1; 546 547 /* We should never see all bds marked as ready, check anyway */ 548 if (recheck_bd == curr_tbptr) 549 break; 550 } 551 /* Now update the TBPTR and dirty flag to the current buffer */ 552 W32(ep, fen_genfcc.fcc_tbptr, 553 (uint) (((void *)recheck_bd - fep->ring_base) + 554 fep->ring_mem_addr)); 555 fep->dirty_tx = recheck_bd; 556 557 C32(fccp, fcc_gfmr, FCC_GFMR_ENT); 558 udelay(10); 559 S32(fccp, fcc_gfmr, FCC_GFMR_ENT); 560 561 fcc_cr_cmd(fep, CPM_CR_RESTART_TX); 562 } 563 564 /*************************************************************************/ 565 566 const struct fs_ops fs_fcc_ops = { 567 .setup_data = setup_data, 568 .cleanup_data = cleanup_data, 569 .set_multicast_list = set_multicast_list, 570 .restart = restart, 571 .stop = stop, 572 .napi_clear_rx_event = napi_clear_rx_event, 573 .napi_enable_rx = napi_enable_rx, 574 .napi_disable_rx = napi_disable_rx, 575 .rx_bd_done = rx_bd_done, 576 .tx_kickstart = tx_kickstart, 577 .get_int_events = get_int_events, 578 .clear_int_events = clear_int_events, 579 .ev_error = ev_error, 580 .get_regs = get_regs, 581 .get_regs_len = get_regs_len, 582 .tx_restart = tx_restart, 583 .allocate_bd = allocate_bd, 584 .free_bd = free_bd, 585 }; 586