1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * FCC driver for Motorola MPC82xx (PQ2). 4 * 5 * Copyright (c) 2003 Intracom S.A. 6 * by Pantelis Antoniou <panto@intracom.gr> 7 * 8 * 2005 (c) MontaVista Software, Inc. 9 * Vitaly Bordug <vbordug@ru.mvista.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/types.h> 15 #include <linux/string.h> 16 #include <linux/ptrace.h> 17 #include <linux/errno.h> 18 #include <linux/ioport.h> 19 #include <linux/interrupt.h> 20 #include <linux/delay.h> 21 #include <linux/netdevice.h> 22 #include <linux/etherdevice.h> 23 #include <linux/skbuff.h> 24 #include <linux/spinlock.h> 25 #include <linux/ethtool.h> 26 #include <linux/bitops.h> 27 #include <linux/fs.h> 28 #include <linux/platform_device.h> 29 #include <linux/phy.h> 30 #include <linux/of_address.h> 31 #include <linux/of_irq.h> 32 #include <linux/gfp.h> 33 #include <linux/pgtable.h> 34 35 #include <asm/immap_cpm2.h> 36 #include <asm/cpm2.h> 37 38 #include <asm/irq.h> 39 #include <linux/uaccess.h> 40 41 #include "fs_enet.h" 42 43 /*************************************************/ 44 45 /* FCC access macros */ 46 47 /* write, read, set bits, clear bits */ 48 #define W32(_p, _m, _v) out_be32(&(_p)->_m, (_v)) 49 #define R32(_p, _m) in_be32(&(_p)->_m) 50 #define S32(_p, _m, _v) W32(_p, _m, R32(_p, _m) | (_v)) 51 #define C32(_p, _m, _v) W32(_p, _m, R32(_p, _m) & ~(_v)) 52 53 #define W16(_p, _m, _v) out_be16(&(_p)->_m, (_v)) 54 #define R16(_p, _m) in_be16(&(_p)->_m) 55 #define S16(_p, _m, _v) W16(_p, _m, R16(_p, _m) | (_v)) 56 #define C16(_p, _m, _v) W16(_p, _m, R16(_p, _m) & ~(_v)) 57 58 #define W8(_p, _m, _v) out_8(&(_p)->_m, (_v)) 59 #define R8(_p, _m) in_8(&(_p)->_m) 60 #define S8(_p, _m, _v) W8(_p, _m, R8(_p, _m) | (_v)) 61 #define C8(_p, _m, _v) W8(_p, _m, R8(_p, _m) & ~(_v)) 62 63 /*************************************************/ 64 65 #define FCC_MAX_MULTICAST_ADDRS 64 66 67 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) 68 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) 69 #define mk_mii_end 0 70 71 #define MAX_CR_CMD_LOOPS 10000 72 73 static inline int fcc_cr_cmd(struct fs_enet_private *fep, u32 op) 74 { 75 const struct fs_platform_info *fpi = fep->fpi; 76 77 return cpm_command(fpi->cp_command, op); 78 } 79 80 static int do_pd_setup(struct fs_enet_private *fep) 81 { 82 struct platform_device *ofdev = to_platform_device(fep->dev); 83 struct fs_platform_info *fpi = fep->fpi; 84 int ret = -EINVAL; 85 86 fep->interrupt = irq_of_parse_and_map(ofdev->dev.of_node, 0); 87 if (!fep->interrupt) 88 goto out; 89 90 fep->fcc.fccp = of_iomap(ofdev->dev.of_node, 0); 91 if (!fep->fcc.fccp) 92 goto out; 93 94 fep->fcc.ep = of_iomap(ofdev->dev.of_node, 1); 95 if (!fep->fcc.ep) 96 goto out_fccp; 97 98 fep->fcc.fcccp = of_iomap(ofdev->dev.of_node, 2); 99 if (!fep->fcc.fcccp) 100 goto out_ep; 101 102 fep->fcc.mem = (void __iomem *)cpm2_immr; 103 fpi->dpram_offset = cpm_muram_alloc(128, 32); 104 if (IS_ERR_VALUE(fpi->dpram_offset)) { 105 ret = fpi->dpram_offset; 106 goto out_fcccp; 107 } 108 109 return 0; 110 111 out_fcccp: 112 iounmap(fep->fcc.fcccp); 113 out_ep: 114 iounmap(fep->fcc.ep); 115 out_fccp: 116 iounmap(fep->fcc.fccp); 117 out: 118 return ret; 119 } 120 121 #define FCC_NAPI_EVENT_MSK (FCC_ENET_RXF | FCC_ENET_RXB | FCC_ENET_TXB) 122 #define FCC_EVENT (FCC_ENET_RXF | FCC_ENET_TXB) 123 #define FCC_ERR_EVENT_MSK (FCC_ENET_TXE) 124 125 static int setup_data(struct net_device *dev) 126 { 127 struct fs_enet_private *fep = netdev_priv(dev); 128 129 if (do_pd_setup(fep) != 0) 130 return -EINVAL; 131 132 fep->ev_napi = FCC_NAPI_EVENT_MSK; 133 fep->ev = FCC_EVENT; 134 fep->ev_err = FCC_ERR_EVENT_MSK; 135 136 return 0; 137 } 138 139 static int allocate_bd(struct net_device *dev) 140 { 141 struct fs_enet_private *fep = netdev_priv(dev); 142 const struct fs_platform_info *fpi = fep->fpi; 143 144 fep->ring_base = (void __iomem __force *)dma_alloc_coherent(fep->dev, 145 (fpi->tx_ring + fpi->rx_ring) * 146 sizeof(cbd_t), &fep->ring_mem_addr, 147 GFP_KERNEL); 148 if (fep->ring_base == NULL) 149 return -ENOMEM; 150 151 return 0; 152 } 153 154 static void free_bd(struct net_device *dev) 155 { 156 struct fs_enet_private *fep = netdev_priv(dev); 157 const struct fs_platform_info *fpi = fep->fpi; 158 159 if (fep->ring_base) 160 dma_free_coherent(fep->dev, 161 (fpi->tx_ring + fpi->rx_ring) * sizeof(cbd_t), 162 (void __force *)fep->ring_base, fep->ring_mem_addr); 163 } 164 165 static void cleanup_data(struct net_device *dev) 166 { 167 /* nothing */ 168 } 169 170 static void set_promiscuous_mode(struct net_device *dev) 171 { 172 struct fs_enet_private *fep = netdev_priv(dev); 173 fcc_t __iomem *fccp = fep->fcc.fccp; 174 175 S32(fccp, fcc_fpsmr, FCC_PSMR_PRO); 176 } 177 178 static void set_multicast_start(struct net_device *dev) 179 { 180 struct fs_enet_private *fep = netdev_priv(dev); 181 fcc_enet_t __iomem *ep = fep->fcc.ep; 182 183 W32(ep, fen_gaddrh, 0); 184 W32(ep, fen_gaddrl, 0); 185 } 186 187 static void set_multicast_one(struct net_device *dev, const u8 *mac) 188 { 189 struct fs_enet_private *fep = netdev_priv(dev); 190 fcc_enet_t __iomem *ep = fep->fcc.ep; 191 u16 taddrh, taddrm, taddrl; 192 193 taddrh = ((u16)mac[5] << 8) | mac[4]; 194 taddrm = ((u16)mac[3] << 8) | mac[2]; 195 taddrl = ((u16)mac[1] << 8) | mac[0]; 196 197 W16(ep, fen_taddrh, taddrh); 198 W16(ep, fen_taddrm, taddrm); 199 W16(ep, fen_taddrl, taddrl); 200 fcc_cr_cmd(fep, CPM_CR_SET_GADDR); 201 } 202 203 static void set_multicast_finish(struct net_device *dev) 204 { 205 struct fs_enet_private *fep = netdev_priv(dev); 206 fcc_t __iomem *fccp = fep->fcc.fccp; 207 fcc_enet_t __iomem *ep = fep->fcc.ep; 208 209 /* clear promiscuous always */ 210 C32(fccp, fcc_fpsmr, FCC_PSMR_PRO); 211 212 /* if all multi or too many multicasts; just enable all */ 213 if ((dev->flags & IFF_ALLMULTI) != 0 || 214 netdev_mc_count(dev) > FCC_MAX_MULTICAST_ADDRS) { 215 216 W32(ep, fen_gaddrh, 0xffffffff); 217 W32(ep, fen_gaddrl, 0xffffffff); 218 } 219 220 /* read back */ 221 fep->fcc.gaddrh = R32(ep, fen_gaddrh); 222 fep->fcc.gaddrl = R32(ep, fen_gaddrl); 223 } 224 225 static void set_multicast_list(struct net_device *dev) 226 { 227 struct netdev_hw_addr *ha; 228 229 if ((dev->flags & IFF_PROMISC) == 0) { 230 set_multicast_start(dev); 231 netdev_for_each_mc_addr(ha, dev) 232 set_multicast_one(dev, ha->addr); 233 set_multicast_finish(dev); 234 } else 235 set_promiscuous_mode(dev); 236 } 237 238 static void restart(struct net_device *dev, phy_interface_t interface, 239 int speed, int duplex) 240 { 241 struct fs_enet_private *fep = netdev_priv(dev); 242 const struct fs_platform_info *fpi = fep->fpi; 243 fcc_t __iomem *fccp = fep->fcc.fccp; 244 fcc_c_t __iomem *fcccp = fep->fcc.fcccp; 245 fcc_enet_t __iomem *ep = fep->fcc.ep; 246 dma_addr_t rx_bd_base_phys, tx_bd_base_phys; 247 u16 paddrh, paddrm, paddrl; 248 const unsigned char *mac; 249 int i; 250 251 C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); 252 253 /* clear everything (slow & steady does it) */ 254 for (i = 0; i < sizeof(*ep); i++) 255 out_8((u8 __iomem *)ep + i, 0); 256 257 /* get physical address */ 258 rx_bd_base_phys = fep->ring_mem_addr; 259 tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring; 260 261 /* point to bds */ 262 W32(ep, fen_genfcc.fcc_rbase, rx_bd_base_phys); 263 W32(ep, fen_genfcc.fcc_tbase, tx_bd_base_phys); 264 265 /* Set maximum bytes per receive buffer. 266 * It must be a multiple of 32. 267 */ 268 W16(ep, fen_genfcc.fcc_mrblr, PKT_MAXBLR_SIZE); 269 270 W32(ep, fen_genfcc.fcc_rstate, (CPMFCR_GBL | CPMFCR_EB) << 24); 271 W32(ep, fen_genfcc.fcc_tstate, (CPMFCR_GBL | CPMFCR_EB) << 24); 272 273 /* Allocate space in the reserved FCC area of DPRAM for the 274 * internal buffers. No one uses this space (yet), so we 275 * can do this. Later, we will add resource management for 276 * this area. 277 */ 278 279 W16(ep, fen_genfcc.fcc_riptr, fpi->dpram_offset); 280 W16(ep, fen_genfcc.fcc_tiptr, fpi->dpram_offset + 32); 281 282 W16(ep, fen_padptr, fpi->dpram_offset + 64); 283 284 /* fill with special symbol... */ 285 memset_io(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32); 286 287 W32(ep, fen_genfcc.fcc_rbptr, 0); 288 W32(ep, fen_genfcc.fcc_tbptr, 0); 289 W32(ep, fen_genfcc.fcc_rcrc, 0); 290 W32(ep, fen_genfcc.fcc_tcrc, 0); 291 W16(ep, fen_genfcc.fcc_res1, 0); 292 W32(ep, fen_genfcc.fcc_res2, 0); 293 294 /* no CAM */ 295 W32(ep, fen_camptr, 0); 296 297 /* Set CRC preset and mask */ 298 W32(ep, fen_cmask, 0xdebb20e3); 299 W32(ep, fen_cpres, 0xffffffff); 300 301 W32(ep, fen_crcec, 0); /* CRC Error counter */ 302 W32(ep, fen_alec, 0); /* alignment error counter */ 303 W32(ep, fen_disfc, 0); /* discard frame counter */ 304 W16(ep, fen_retlim, 15); /* Retry limit threshold */ 305 W16(ep, fen_pper, 0); /* Normal persistence */ 306 307 /* set group address */ 308 W32(ep, fen_gaddrh, fep->fcc.gaddrh); 309 W32(ep, fen_gaddrl, fep->fcc.gaddrh); 310 311 /* Clear hash filter tables */ 312 W32(ep, fen_iaddrh, 0); 313 W32(ep, fen_iaddrl, 0); 314 315 /* Clear the Out-of-sequence TxBD */ 316 W16(ep, fen_tfcstat, 0); 317 W16(ep, fen_tfclen, 0); 318 W32(ep, fen_tfcptr, 0); 319 320 W16(ep, fen_mflr, PKT_MAXBUF_SIZE); /* maximum frame length register */ 321 W16(ep, fen_minflr, PKT_MINBUF_SIZE); /* minimum frame length register */ 322 323 /* set address */ 324 mac = dev->dev_addr; 325 paddrh = ((u16)mac[5] << 8) | mac[4]; 326 paddrm = ((u16)mac[3] << 8) | mac[2]; 327 paddrl = ((u16)mac[1] << 8) | mac[0]; 328 329 W16(ep, fen_paddrh, paddrh); 330 W16(ep, fen_paddrm, paddrm); 331 W16(ep, fen_paddrl, paddrl); 332 333 W16(ep, fen_taddrh, 0); 334 W16(ep, fen_taddrm, 0); 335 W16(ep, fen_taddrl, 0); 336 337 W16(ep, fen_maxd1, 1520); /* maximum DMA1 length */ 338 W16(ep, fen_maxd2, 1520); /* maximum DMA2 length */ 339 340 /* Clear stat counters, in case we ever enable RMON */ 341 W32(ep, fen_octc, 0); 342 W32(ep, fen_colc, 0); 343 W32(ep, fen_broc, 0); 344 W32(ep, fen_mulc, 0); 345 W32(ep, fen_uspc, 0); 346 W32(ep, fen_frgc, 0); 347 W32(ep, fen_ospc, 0); 348 W32(ep, fen_jbrc, 0); 349 W32(ep, fen_p64c, 0); 350 W32(ep, fen_p65c, 0); 351 W32(ep, fen_p128c, 0); 352 W32(ep, fen_p256c, 0); 353 W32(ep, fen_p512c, 0); 354 W32(ep, fen_p1024c, 0); 355 356 W16(ep, fen_rfthr, 0); /* Suggested by manual */ 357 W16(ep, fen_rfcnt, 0); 358 W16(ep, fen_cftype, 0); 359 360 fs_init_bds(dev); 361 362 /* adjust to speed (for RMII mode) */ 363 if (interface == PHY_INTERFACE_MODE_RMII) { 364 if (speed == SPEED_100) 365 C8(fcccp, fcc_gfemr, 0x20); 366 else 367 S8(fcccp, fcc_gfemr, 0x20); 368 } 369 370 fcc_cr_cmd(fep, CPM_CR_INIT_TRX); 371 372 /* clear events */ 373 W16(fccp, fcc_fcce, 0xffff); 374 375 /* Enable interrupts we wish to service */ 376 W16(fccp, fcc_fccm, FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB); 377 378 /* Set GFMR to enable Ethernet operating mode */ 379 W32(fccp, fcc_gfmr, FCC_GFMR_TCI | FCC_GFMR_MODE_ENET); 380 381 /* set sync/delimiters */ 382 W16(fccp, fcc_fdsr, 0xd555); 383 384 W32(fccp, fcc_fpsmr, FCC_PSMR_ENCRC); 385 386 if (interface == PHY_INTERFACE_MODE_RMII) 387 S32(fccp, fcc_fpsmr, FCC_PSMR_RMII); 388 389 /* adjust to duplex mode */ 390 if (duplex == DUPLEX_FULL) 391 S32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB); 392 else 393 C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB); 394 395 /* Restore multicast and promiscuous settings */ 396 set_multicast_list(dev); 397 398 S32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); 399 } 400 401 static void stop(struct net_device *dev) 402 { 403 struct fs_enet_private *fep = netdev_priv(dev); 404 fcc_t __iomem *fccp = fep->fcc.fccp; 405 406 /* stop ethernet */ 407 C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); 408 409 /* clear events */ 410 W16(fccp, fcc_fcce, 0xffff); 411 412 /* clear interrupt mask */ 413 W16(fccp, fcc_fccm, 0); 414 415 fs_cleanup_bds(dev); 416 } 417 418 static void napi_clear_event_fs(struct net_device *dev) 419 { 420 struct fs_enet_private *fep = netdev_priv(dev); 421 fcc_t __iomem *fccp = fep->fcc.fccp; 422 423 W16(fccp, fcc_fcce, FCC_NAPI_EVENT_MSK); 424 } 425 426 static void napi_enable_fs(struct net_device *dev) 427 { 428 struct fs_enet_private *fep = netdev_priv(dev); 429 fcc_t __iomem *fccp = fep->fcc.fccp; 430 431 S16(fccp, fcc_fccm, FCC_NAPI_EVENT_MSK); 432 } 433 434 static void napi_disable_fs(struct net_device *dev) 435 { 436 struct fs_enet_private *fep = netdev_priv(dev); 437 fcc_t __iomem *fccp = fep->fcc.fccp; 438 439 C16(fccp, fcc_fccm, FCC_NAPI_EVENT_MSK); 440 } 441 442 static void rx_bd_done(struct net_device *dev) 443 { 444 /* nothing */ 445 } 446 447 static void tx_kickstart(struct net_device *dev) 448 { 449 struct fs_enet_private *fep = netdev_priv(dev); 450 fcc_t __iomem *fccp = fep->fcc.fccp; 451 452 S16(fccp, fcc_ftodr, 0x8000); 453 } 454 455 static u32 get_int_events(struct net_device *dev) 456 { 457 struct fs_enet_private *fep = netdev_priv(dev); 458 fcc_t __iomem *fccp = fep->fcc.fccp; 459 460 return (u32)R16(fccp, fcc_fcce); 461 } 462 463 static void clear_int_events(struct net_device *dev, u32 int_events) 464 { 465 struct fs_enet_private *fep = netdev_priv(dev); 466 fcc_t __iomem *fccp = fep->fcc.fccp; 467 468 W16(fccp, fcc_fcce, int_events & 0xffff); 469 } 470 471 static void ev_error(struct net_device *dev, u32 int_events) 472 { 473 struct fs_enet_private *fep = netdev_priv(dev); 474 475 dev_warn(fep->dev, "FS_ENET ERROR(s) 0x%x\n", int_events); 476 } 477 478 static int get_regs(struct net_device *dev, void *p, int *sizep) 479 { 480 struct fs_enet_private *fep = netdev_priv(dev); 481 482 if (*sizep < sizeof(fcc_t) + sizeof(fcc_enet_t) + 1) 483 return -EINVAL; 484 485 memcpy_fromio(p, fep->fcc.fccp, sizeof(fcc_t)); 486 p = (char *)p + sizeof(fcc_t); 487 488 memcpy_fromio(p, fep->fcc.ep, sizeof(fcc_enet_t)); 489 p = (char *)p + sizeof(fcc_enet_t); 490 491 memcpy_fromio(p, fep->fcc.fcccp, 1); 492 return 0; 493 } 494 495 static int get_regs_len(struct net_device *dev) 496 { 497 return sizeof(fcc_t) + sizeof(fcc_enet_t) + 1; 498 } 499 500 /* Some transmit errors cause the transmitter to shut 501 * down. We now issue a restart transmit. 502 * Also, to workaround 8260 device erratum CPM37, we must 503 * disable and then re-enable the transmitterfollowing a 504 * Late Collision, Underrun, or Retry Limit error. 505 * In addition, tbptr may point beyond BDs beyond still marked 506 * as ready due to internal pipelining, so we need to look back 507 * through the BDs and adjust tbptr to point to the last BD 508 * marked as ready. This may result in some buffers being 509 * retransmitted. 510 */ 511 static void tx_restart(struct net_device *dev) 512 { 513 struct fs_enet_private *fep = netdev_priv(dev); 514 fcc_t __iomem *fccp = fep->fcc.fccp; 515 const struct fs_platform_info *fpi = fep->fpi; 516 fcc_enet_t __iomem *ep = fep->fcc.ep; 517 cbd_t __iomem *curr_tbptr; 518 cbd_t __iomem *recheck_bd; 519 cbd_t __iomem *prev_bd; 520 cbd_t __iomem *last_tx_bd; 521 522 last_tx_bd = fep->tx_bd_base + (fpi->tx_ring - 1); 523 524 /* get the current bd held in TBPTR and scan back from this point */ 525 recheck_bd = curr_tbptr = (cbd_t __iomem *) 526 ((R32(ep, fen_genfcc.fcc_tbptr) - fep->ring_mem_addr) + 527 fep->ring_base); 528 529 prev_bd = (recheck_bd == fep->tx_bd_base) ? last_tx_bd : recheck_bd - 1; 530 531 /* Move through the bds in reverse, look for the earliest buffer 532 * that is not ready. Adjust TBPTR to the following buffer */ 533 while ((CBDR_SC(prev_bd) & BD_ENET_TX_READY) != 0) { 534 /* Go back one buffer */ 535 recheck_bd = prev_bd; 536 537 /* update the previous buffer */ 538 prev_bd = (prev_bd == fep->tx_bd_base) ? last_tx_bd : prev_bd - 1; 539 540 /* We should never see all bds marked as ready, check anyway */ 541 if (recheck_bd == curr_tbptr) 542 break; 543 } 544 /* Now update the TBPTR and dirty flag to the current buffer */ 545 W32(ep, fen_genfcc.fcc_tbptr, 546 (uint)(((void __iomem *)recheck_bd - fep->ring_base) + 547 fep->ring_mem_addr)); 548 fep->dirty_tx = recheck_bd; 549 550 C32(fccp, fcc_gfmr, FCC_GFMR_ENT); 551 udelay(10); 552 S32(fccp, fcc_gfmr, FCC_GFMR_ENT); 553 554 fcc_cr_cmd(fep, CPM_CR_RESTART_TX); 555 } 556 557 /*************************************************************************/ 558 559 const struct fs_ops fs_fcc_ops = { 560 .setup_data = setup_data, 561 .cleanup_data = cleanup_data, 562 .set_multicast_list = set_multicast_list, 563 .restart = restart, 564 .stop = stop, 565 .napi_clear_event = napi_clear_event_fs, 566 .napi_enable = napi_enable_fs, 567 .napi_disable = napi_disable_fs, 568 .rx_bd_done = rx_bd_done, 569 .tx_kickstart = tx_kickstart, 570 .get_int_events = get_int_events, 571 .clear_int_events = clear_int_events, 572 .ev_error = ev_error, 573 .get_regs = get_regs, 574 .get_regs_len = get_regs_len, 575 .tx_restart = tx_restart, 576 .allocate_bd = allocate_bd, 577 .free_bd = free_bd, 578 }; 579