1 /* 2 * Copyright 2008 - 2015 Freescale Semiconductor Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * 16 * ALTERNATIVELY, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL") as published by the Free Software 18 * Foundation, either version 2 of that License or (at your option) any 19 * later version. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 34 35 #include "fman_port.h" 36 #include "fman.h" 37 #include "fman_sp.h" 38 39 #include <linux/io.h> 40 #include <linux/slab.h> 41 #include <linux/module.h> 42 #include <linux/interrupt.h> 43 #include <linux/of_platform.h> 44 #include <linux/of_address.h> 45 #include <linux/delay.h> 46 #include <linux/libfdt_env.h> 47 48 /* Queue ID */ 49 #define DFLT_FQ_ID 0x00FFFFFF 50 51 /* General defines */ 52 #define PORT_BMI_FIFO_UNITS 0x100 53 54 #define MAX_PORT_FIFO_SIZE(bmi_max_fifo_size) \ 55 min((u32)bmi_max_fifo_size, (u32)1024 * FMAN_BMI_FIFO_UNITS) 56 57 #define PORT_CG_MAP_NUM 8 58 #define PORT_PRS_RESULT_WORDS_NUM 8 59 #define PORT_IC_OFFSET_UNITS 0x10 60 61 #define MIN_EXT_BUF_SIZE 64 62 63 #define BMI_PORT_REGS_OFFSET 0 64 #define QMI_PORT_REGS_OFFSET 0x400 65 66 /* Default values */ 67 #define DFLT_PORT_BUFFER_PREFIX_CONTEXT_DATA_ALIGN \ 68 DFLT_FM_SP_BUFFER_PREFIX_CONTEXT_DATA_ALIGN 69 70 #define DFLT_PORT_CUT_BYTES_FROM_END 4 71 72 #define DFLT_PORT_ERRORS_TO_DISCARD FM_PORT_FRM_ERR_CLS_DISCARD 73 #define DFLT_PORT_MAX_FRAME_LENGTH 9600 74 75 #define DFLT_PORT_RX_FIFO_PRI_ELEVATION_LEV(bmi_max_fifo_size) \ 76 MAX_PORT_FIFO_SIZE(bmi_max_fifo_size) 77 78 #define DFLT_PORT_RX_FIFO_THRESHOLD(major, bmi_max_fifo_size) \ 79 (major == 6 ? \ 80 MAX_PORT_FIFO_SIZE(bmi_max_fifo_size) : \ 81 (MAX_PORT_FIFO_SIZE(bmi_max_fifo_size) * 3 / 4)) \ 82 83 #define DFLT_PORT_EXTRA_NUM_OF_FIFO_BUFS 0 84 85 /* QMI defines */ 86 #define QMI_DEQ_CFG_SUBPORTAL_MASK 0x1f 87 88 #define QMI_PORT_CFG_EN 0x80000000 89 #define QMI_PORT_STATUS_DEQ_FD_BSY 0x20000000 90 91 #define QMI_DEQ_CFG_PRI 0x80000000 92 #define QMI_DEQ_CFG_TYPE1 0x10000000 93 #define QMI_DEQ_CFG_TYPE2 0x20000000 94 #define QMI_DEQ_CFG_TYPE3 0x30000000 95 #define QMI_DEQ_CFG_PREFETCH_PARTIAL 0x01000000 96 #define QMI_DEQ_CFG_PREFETCH_FULL 0x03000000 97 #define QMI_DEQ_CFG_SP_MASK 0xf 98 #define QMI_DEQ_CFG_SP_SHIFT 20 99 100 #define QMI_BYTE_COUNT_LEVEL_CONTROL(_type) \ 101 (_type == FMAN_PORT_TYPE_TX ? 0x1400 : 0x400) 102 103 /* BMI defins */ 104 #define BMI_EBD_EN 0x80000000 105 106 #define BMI_PORT_CFG_EN 0x80000000 107 108 #define BMI_PORT_STATUS_BSY 0x80000000 109 110 #define BMI_DMA_ATTR_SWP_SHIFT FMAN_SP_DMA_ATTR_SWP_SHIFT 111 #define BMI_DMA_ATTR_WRITE_OPTIMIZE FMAN_SP_DMA_ATTR_WRITE_OPTIMIZE 112 113 #define BMI_RX_FIFO_PRI_ELEVATION_SHIFT 16 114 #define BMI_RX_FIFO_THRESHOLD_ETHE 0x80000000 115 116 #define BMI_FRAME_END_CS_IGNORE_SHIFT 24 117 #define BMI_FRAME_END_CS_IGNORE_MASK 0x0000001f 118 119 #define BMI_RX_FRAME_END_CUT_SHIFT 16 120 #define BMI_RX_FRAME_END_CUT_MASK 0x0000001f 121 122 #define BMI_IC_TO_EXT_SHIFT FMAN_SP_IC_TO_EXT_SHIFT 123 #define BMI_IC_TO_EXT_MASK 0x0000001f 124 #define BMI_IC_FROM_INT_SHIFT FMAN_SP_IC_FROM_INT_SHIFT 125 #define BMI_IC_FROM_INT_MASK 0x0000000f 126 #define BMI_IC_SIZE_MASK 0x0000001f 127 128 #define BMI_INT_BUF_MARG_SHIFT 28 129 #define BMI_INT_BUF_MARG_MASK 0x0000000f 130 #define BMI_EXT_BUF_MARG_START_SHIFT FMAN_SP_EXT_BUF_MARG_START_SHIFT 131 #define BMI_EXT_BUF_MARG_START_MASK 0x000001ff 132 #define BMI_EXT_BUF_MARG_END_MASK 0x000001ff 133 134 #define BMI_CMD_MR_LEAC 0x00200000 135 #define BMI_CMD_MR_SLEAC 0x00100000 136 #define BMI_CMD_MR_MA 0x00080000 137 #define BMI_CMD_MR_DEAS 0x00040000 138 #define BMI_CMD_RX_MR_DEF (BMI_CMD_MR_LEAC | \ 139 BMI_CMD_MR_SLEAC | \ 140 BMI_CMD_MR_MA | \ 141 BMI_CMD_MR_DEAS) 142 #define BMI_CMD_TX_MR_DEF 0 143 144 #define BMI_CMD_ATTR_ORDER 0x80000000 145 #define BMI_CMD_ATTR_SYNC 0x02000000 146 #define BMI_CMD_ATTR_COLOR_SHIFT 26 147 148 #define BMI_FIFO_PIPELINE_DEPTH_SHIFT 12 149 #define BMI_FIFO_PIPELINE_DEPTH_MASK 0x0000000f 150 #define BMI_NEXT_ENG_FD_BITS_SHIFT 24 151 152 #define BMI_EXT_BUF_POOL_VALID FMAN_SP_EXT_BUF_POOL_VALID 153 #define BMI_EXT_BUF_POOL_EN_COUNTER FMAN_SP_EXT_BUF_POOL_EN_COUNTER 154 #define BMI_EXT_BUF_POOL_BACKUP FMAN_SP_EXT_BUF_POOL_BACKUP 155 #define BMI_EXT_BUF_POOL_ID_SHIFT 16 156 #define BMI_EXT_BUF_POOL_ID_MASK 0x003F0000 157 #define BMI_POOL_DEP_NUM_OF_POOLS_SHIFT 16 158 159 #define BMI_TX_FIFO_MIN_FILL_SHIFT 16 160 161 #define BMI_PRIORITY_ELEVATION_LEVEL ((0x3FF + 1) * PORT_BMI_FIFO_UNITS) 162 #define BMI_FIFO_THRESHOLD ((0x3FF + 1) * PORT_BMI_FIFO_UNITS) 163 164 #define BMI_DEQUEUE_PIPELINE_DEPTH(_type, _speed) \ 165 ((_type == FMAN_PORT_TYPE_TX && _speed == 10000) ? 4 : 1) 166 167 #define RX_ERRS_TO_ENQ \ 168 (FM_PORT_FRM_ERR_DMA | \ 169 FM_PORT_FRM_ERR_PHYSICAL | \ 170 FM_PORT_FRM_ERR_SIZE | \ 171 FM_PORT_FRM_ERR_EXTRACTION | \ 172 FM_PORT_FRM_ERR_NO_SCHEME | \ 173 FM_PORT_FRM_ERR_PRS_TIMEOUT | \ 174 FM_PORT_FRM_ERR_PRS_ILL_INSTRUCT | \ 175 FM_PORT_FRM_ERR_BLOCK_LIMIT_EXCEEDED | \ 176 FM_PORT_FRM_ERR_PRS_HDR_ERR | \ 177 FM_PORT_FRM_ERR_KEYSIZE_OVERFLOW | \ 178 FM_PORT_FRM_ERR_IPRE) 179 180 /* NIA defines */ 181 #define NIA_ORDER_RESTOR 0x00800000 182 #define NIA_ENG_BMI 0x00500000 183 #define NIA_ENG_QMI_ENQ 0x00540000 184 #define NIA_ENG_QMI_DEQ 0x00580000 185 186 #define NIA_BMI_AC_ENQ_FRAME 0x00000002 187 #define NIA_BMI_AC_TX_RELEASE 0x000002C0 188 #define NIA_BMI_AC_RELEASE 0x000000C0 189 #define NIA_BMI_AC_TX 0x00000274 190 #define NIA_BMI_AC_FETCH_ALL_FRAME 0x0000020c 191 192 /* Port IDs */ 193 #define TX_10G_PORT_BASE 0x30 194 #define RX_10G_PORT_BASE 0x10 195 196 /* BMI Rx port register map */ 197 struct fman_port_rx_bmi_regs { 198 u32 fmbm_rcfg; /* Rx Configuration */ 199 u32 fmbm_rst; /* Rx Status */ 200 u32 fmbm_rda; /* Rx DMA attributes */ 201 u32 fmbm_rfp; /* Rx FIFO Parameters */ 202 u32 fmbm_rfed; /* Rx Frame End Data */ 203 u32 fmbm_ricp; /* Rx Internal Context Parameters */ 204 u32 fmbm_rim; /* Rx Internal Buffer Margins */ 205 u32 fmbm_rebm; /* Rx External Buffer Margins */ 206 u32 fmbm_rfne; /* Rx Frame Next Engine */ 207 u32 fmbm_rfca; /* Rx Frame Command Attributes. */ 208 u32 fmbm_rfpne; /* Rx Frame Parser Next Engine */ 209 u32 fmbm_rpso; /* Rx Parse Start Offset */ 210 u32 fmbm_rpp; /* Rx Policer Profile */ 211 u32 fmbm_rccb; /* Rx Coarse Classification Base */ 212 u32 fmbm_reth; /* Rx Excessive Threshold */ 213 u32 reserved003c[1]; /* (0x03C 0x03F) */ 214 u32 fmbm_rprai[PORT_PRS_RESULT_WORDS_NUM]; 215 /* Rx Parse Results Array Init */ 216 u32 fmbm_rfqid; /* Rx Frame Queue ID */ 217 u32 fmbm_refqid; /* Rx Error Frame Queue ID */ 218 u32 fmbm_rfsdm; /* Rx Frame Status Discard Mask */ 219 u32 fmbm_rfsem; /* Rx Frame Status Error Mask */ 220 u32 fmbm_rfene; /* Rx Frame Enqueue Next Engine */ 221 u32 reserved0074[0x2]; /* (0x074-0x07C) */ 222 u32 fmbm_rcmne; /* Rx Frame Continuous Mode Next Engine */ 223 u32 reserved0080[0x20]; /* (0x080 0x0FF) */ 224 u32 fmbm_ebmpi[FMAN_PORT_MAX_EXT_POOLS_NUM]; 225 /* Buffer Manager pool Information- */ 226 u32 fmbm_acnt[FMAN_PORT_MAX_EXT_POOLS_NUM]; /* Allocate Counter- */ 227 u32 reserved0130[8]; /* 0x130/0x140 - 0x15F reserved - */ 228 u32 fmbm_rcgm[PORT_CG_MAP_NUM]; /* Congestion Group Map */ 229 u32 fmbm_mpd; /* BM Pool Depletion */ 230 u32 reserved0184[0x1F]; /* (0x184 0x1FF) */ 231 u32 fmbm_rstc; /* Rx Statistics Counters */ 232 u32 fmbm_rfrc; /* Rx Frame Counter */ 233 u32 fmbm_rfbc; /* Rx Bad Frames Counter */ 234 u32 fmbm_rlfc; /* Rx Large Frames Counter */ 235 u32 fmbm_rffc; /* Rx Filter Frames Counter */ 236 u32 fmbm_rfdc; /* Rx Frame Discard Counter */ 237 u32 fmbm_rfldec; /* Rx Frames List DMA Error Counter */ 238 u32 fmbm_rodc; /* Rx Out of Buffers Discard nntr */ 239 u32 fmbm_rbdc; /* Rx Buffers Deallocate Counter */ 240 u32 fmbm_rpec; /* RX Prepare to enqueue Counte */ 241 u32 reserved0224[0x16]; /* (0x224 0x27F) */ 242 u32 fmbm_rpc; /* Rx Performance Counters */ 243 u32 fmbm_rpcp; /* Rx Performance Count Parameters */ 244 u32 fmbm_rccn; /* Rx Cycle Counter */ 245 u32 fmbm_rtuc; /* Rx Tasks Utilization Counter */ 246 u32 fmbm_rrquc; /* Rx Receive Queue Utilization cntr */ 247 u32 fmbm_rduc; /* Rx DMA Utilization Counter */ 248 u32 fmbm_rfuc; /* Rx FIFO Utilization Counter */ 249 u32 fmbm_rpac; /* Rx Pause Activation Counter */ 250 u32 reserved02a0[0x18]; /* (0x2A0 0x2FF) */ 251 u32 fmbm_rdcfg[0x3]; /* Rx Debug Configuration */ 252 u32 fmbm_rgpr; /* Rx General Purpose Register */ 253 u32 reserved0310[0x3a]; 254 }; 255 256 /* BMI Tx port register map */ 257 struct fman_port_tx_bmi_regs { 258 u32 fmbm_tcfg; /* Tx Configuration */ 259 u32 fmbm_tst; /* Tx Status */ 260 u32 fmbm_tda; /* Tx DMA attributes */ 261 u32 fmbm_tfp; /* Tx FIFO Parameters */ 262 u32 fmbm_tfed; /* Tx Frame End Data */ 263 u32 fmbm_ticp; /* Tx Internal Context Parameters */ 264 u32 fmbm_tfdne; /* Tx Frame Dequeue Next Engine. */ 265 u32 fmbm_tfca; /* Tx Frame Command attribute. */ 266 u32 fmbm_tcfqid; /* Tx Confirmation Frame Queue ID. */ 267 u32 fmbm_tefqid; /* Tx Frame Error Queue ID */ 268 u32 fmbm_tfene; /* Tx Frame Enqueue Next Engine */ 269 u32 fmbm_trlmts; /* Tx Rate Limiter Scale */ 270 u32 fmbm_trlmt; /* Tx Rate Limiter */ 271 u32 reserved0034[0x0e]; /* (0x034-0x6c) */ 272 u32 fmbm_tccb; /* Tx Coarse Classification base */ 273 u32 fmbm_tfne; /* Tx Frame Next Engine */ 274 u32 fmbm_tpfcm[0x02]; 275 /* Tx Priority based Flow Control (PFC) Mapping */ 276 u32 fmbm_tcmne; /* Tx Frame Continuous Mode Next Engine */ 277 u32 reserved0080[0x60]; /* (0x080-0x200) */ 278 u32 fmbm_tstc; /* Tx Statistics Counters */ 279 u32 fmbm_tfrc; /* Tx Frame Counter */ 280 u32 fmbm_tfdc; /* Tx Frames Discard Counter */ 281 u32 fmbm_tfledc; /* Tx Frame len error discard cntr */ 282 u32 fmbm_tfufdc; /* Tx Frame unsprt frmt discard cntr */ 283 u32 fmbm_tbdc; /* Tx Buffers Deallocate Counter */ 284 u32 reserved0218[0x1A]; /* (0x218-0x280) */ 285 u32 fmbm_tpc; /* Tx Performance Counters */ 286 u32 fmbm_tpcp; /* Tx Performance Count Parameters */ 287 u32 fmbm_tccn; /* Tx Cycle Counter */ 288 u32 fmbm_ttuc; /* Tx Tasks Utilization Counter */ 289 u32 fmbm_ttcquc; /* Tx Transmit conf Q util Counter */ 290 u32 fmbm_tduc; /* Tx DMA Utilization Counter */ 291 u32 fmbm_tfuc; /* Tx FIFO Utilization Counter */ 292 u32 reserved029c[16]; /* (0x29C-0x2FF) */ 293 u32 fmbm_tdcfg[0x3]; /* Tx Debug Configuration */ 294 u32 fmbm_tgpr; /* Tx General Purpose Register */ 295 u32 reserved0310[0x3a]; /* (0x310-0x3FF) */ 296 }; 297 298 /* BMI port register map */ 299 union fman_port_bmi_regs { 300 struct fman_port_rx_bmi_regs rx; 301 struct fman_port_tx_bmi_regs tx; 302 }; 303 304 /* QMI port register map */ 305 struct fman_port_qmi_regs { 306 u32 fmqm_pnc; /* PortID n Configuration Register */ 307 u32 fmqm_pns; /* PortID n Status Register */ 308 u32 fmqm_pnts; /* PortID n Task Status Register */ 309 u32 reserved00c[4]; /* 0xn00C - 0xn01B */ 310 u32 fmqm_pnen; /* PortID n Enqueue NIA Register */ 311 u32 fmqm_pnetfc; /* PortID n Enq Total Frame Counter */ 312 u32 reserved024[2]; /* 0xn024 - 0x02B */ 313 u32 fmqm_pndn; /* PortID n Dequeue NIA Register */ 314 u32 fmqm_pndc; /* PortID n Dequeue Config Register */ 315 u32 fmqm_pndtfc; /* PortID n Dequeue tot Frame cntr */ 316 u32 fmqm_pndfdc; /* PortID n Dequeue FQID Dflt Cntr */ 317 u32 fmqm_pndcc; /* PortID n Dequeue Confirm Counter */ 318 }; 319 320 /* QMI dequeue prefetch modes */ 321 enum fman_port_deq_prefetch { 322 FMAN_PORT_DEQ_NO_PREFETCH, /* No prefetch mode */ 323 FMAN_PORT_DEQ_PART_PREFETCH, /* Partial prefetch mode */ 324 FMAN_PORT_DEQ_FULL_PREFETCH /* Full prefetch mode */ 325 }; 326 327 /* A structure for defining FM port resources */ 328 struct fman_port_rsrc { 329 u32 num; /* Committed required resource */ 330 u32 extra; /* Extra (not committed) required resource */ 331 }; 332 333 enum fman_port_dma_swap { 334 FMAN_PORT_DMA_NO_SWAP, /* No swap, transfer data as is */ 335 FMAN_PORT_DMA_SWAP_LE, 336 /* The transferred data should be swapped in PPC Little Endian mode */ 337 FMAN_PORT_DMA_SWAP_BE 338 /* The transferred data should be swapped in Big Endian mode */ 339 }; 340 341 /* Default port color */ 342 enum fman_port_color { 343 FMAN_PORT_COLOR_GREEN, /* Default port color is green */ 344 FMAN_PORT_COLOR_YELLOW, /* Default port color is yellow */ 345 FMAN_PORT_COLOR_RED, /* Default port color is red */ 346 FMAN_PORT_COLOR_OVERRIDE /* Ignore color */ 347 }; 348 349 /* QMI dequeue from the SP channel - types */ 350 enum fman_port_deq_type { 351 FMAN_PORT_DEQ_BY_PRI, 352 /* Priority precedence and Intra-Class scheduling */ 353 FMAN_PORT_DEQ_ACTIVE_FQ, 354 /* Active FQ precedence and Intra-Class scheduling */ 355 FMAN_PORT_DEQ_ACTIVE_FQ_NO_ICS 356 /* Active FQ precedence and override Intra-Class scheduling */ 357 }; 358 359 /* External buffer pools configuration */ 360 struct fman_port_bpools { 361 u8 count; /* Num of pools to set up */ 362 bool counters_enable; /* Enable allocate counters */ 363 u8 grp_bp_depleted_num; 364 /* Number of depleted pools - if reached the BMI indicates 365 * the MAC to send a pause frame 366 */ 367 struct { 368 u8 bpid; /* BM pool ID */ 369 u16 size; 370 /* Pool's size - must be in ascending order */ 371 bool is_backup; 372 /* If this is a backup pool */ 373 bool grp_bp_depleted; 374 /* Consider this buffer in multiple pools depletion criteria */ 375 bool single_bp_depleted; 376 /* Consider this buffer in single pool depletion criteria */ 377 } bpool[FMAN_PORT_MAX_EXT_POOLS_NUM]; 378 }; 379 380 struct fman_port_cfg { 381 u32 dflt_fqid; 382 u32 err_fqid; 383 u8 deq_sp; 384 bool deq_high_priority; 385 enum fman_port_deq_type deq_type; 386 enum fman_port_deq_prefetch deq_prefetch_option; 387 u16 deq_byte_cnt; 388 u8 cheksum_last_bytes_ignore; 389 u8 rx_cut_end_bytes; 390 struct fman_buf_pool_depletion buf_pool_depletion; 391 struct fman_ext_pools ext_buf_pools; 392 u32 tx_fifo_min_level; 393 u32 tx_fifo_low_comf_level; 394 u32 rx_pri_elevation; 395 u32 rx_fifo_thr; 396 struct fman_sp_buf_margins buf_margins; 397 u32 int_buf_start_margin; 398 struct fman_sp_int_context_data_copy int_context; 399 u32 discard_mask; 400 u32 err_mask; 401 struct fman_buffer_prefix_content buffer_prefix_content; 402 bool dont_release_buf; 403 404 u8 rx_fd_bits; 405 u32 tx_fifo_deq_pipeline_depth; 406 bool errata_A006320; 407 bool excessive_threshold_register; 408 bool fmbm_tfne_has_features; 409 410 enum fman_port_dma_swap dma_swap_data; 411 enum fman_port_color color; 412 }; 413 414 struct fman_port_rx_pools_params { 415 u8 num_of_pools; 416 u16 second_largest_buf_size; 417 u16 largest_buf_size; 418 }; 419 420 struct fman_port_dts_params { 421 void __iomem *base_addr; /* FMan port virtual memory */ 422 enum fman_port_type type; /* Port type */ 423 u16 speed; /* Port speed */ 424 u8 id; /* HW Port Id */ 425 u32 qman_channel_id; /* QMan channel id (non RX only) */ 426 struct fman *fman; /* FMan Handle */ 427 }; 428 429 struct fman_port { 430 void *fm; 431 struct device *dev; 432 struct fman_rev_info rev_info; 433 u8 port_id; 434 enum fman_port_type port_type; 435 u16 port_speed; 436 437 union fman_port_bmi_regs __iomem *bmi_regs; 438 struct fman_port_qmi_regs __iomem *qmi_regs; 439 440 struct fman_sp_buffer_offsets buffer_offsets; 441 442 u8 internal_buf_offset; 443 struct fman_ext_pools ext_buf_pools; 444 445 u16 max_frame_length; 446 struct fman_port_rsrc open_dmas; 447 struct fman_port_rsrc tasks; 448 struct fman_port_rsrc fifo_bufs; 449 struct fman_port_rx_pools_params rx_pools_params; 450 451 struct fman_port_cfg *cfg; 452 struct fman_port_dts_params dts_params; 453 454 u8 ext_pools_num; 455 u32 max_port_fifo_size; 456 u32 max_num_of_ext_pools; 457 u32 max_num_of_sub_portals; 458 u32 bm_max_num_of_pools; 459 }; 460 461 static int init_bmi_rx(struct fman_port *port) 462 { 463 struct fman_port_rx_bmi_regs __iomem *regs = &port->bmi_regs->rx; 464 struct fman_port_cfg *cfg = port->cfg; 465 u32 tmp; 466 467 /* DMA attributes */ 468 tmp = (u32)cfg->dma_swap_data << BMI_DMA_ATTR_SWP_SHIFT; 469 /* Enable write optimization */ 470 tmp |= BMI_DMA_ATTR_WRITE_OPTIMIZE; 471 iowrite32be(tmp, ®s->fmbm_rda); 472 473 /* Rx FIFO parameters */ 474 tmp = (cfg->rx_pri_elevation / PORT_BMI_FIFO_UNITS - 1) << 475 BMI_RX_FIFO_PRI_ELEVATION_SHIFT; 476 tmp |= cfg->rx_fifo_thr / PORT_BMI_FIFO_UNITS - 1; 477 iowrite32be(tmp, ®s->fmbm_rfp); 478 479 if (cfg->excessive_threshold_register) 480 /* always allow access to the extra resources */ 481 iowrite32be(BMI_RX_FIFO_THRESHOLD_ETHE, ®s->fmbm_reth); 482 483 /* Frame end data */ 484 tmp = (cfg->cheksum_last_bytes_ignore & BMI_FRAME_END_CS_IGNORE_MASK) << 485 BMI_FRAME_END_CS_IGNORE_SHIFT; 486 tmp |= (cfg->rx_cut_end_bytes & BMI_RX_FRAME_END_CUT_MASK) << 487 BMI_RX_FRAME_END_CUT_SHIFT; 488 if (cfg->errata_A006320) 489 tmp &= 0xffe0ffff; 490 iowrite32be(tmp, ®s->fmbm_rfed); 491 492 /* Internal context parameters */ 493 tmp = ((cfg->int_context.ext_buf_offset / PORT_IC_OFFSET_UNITS) & 494 BMI_IC_TO_EXT_MASK) << BMI_IC_TO_EXT_SHIFT; 495 tmp |= ((cfg->int_context.int_context_offset / PORT_IC_OFFSET_UNITS) & 496 BMI_IC_FROM_INT_MASK) << BMI_IC_FROM_INT_SHIFT; 497 tmp |= (cfg->int_context.size / PORT_IC_OFFSET_UNITS) & 498 BMI_IC_SIZE_MASK; 499 iowrite32be(tmp, ®s->fmbm_ricp); 500 501 /* Internal buffer offset */ 502 tmp = ((cfg->int_buf_start_margin / PORT_IC_OFFSET_UNITS) & 503 BMI_INT_BUF_MARG_MASK) << BMI_INT_BUF_MARG_SHIFT; 504 iowrite32be(tmp, ®s->fmbm_rim); 505 506 /* External buffer margins */ 507 tmp = (cfg->buf_margins.start_margins & BMI_EXT_BUF_MARG_START_MASK) << 508 BMI_EXT_BUF_MARG_START_SHIFT; 509 tmp |= cfg->buf_margins.end_margins & BMI_EXT_BUF_MARG_END_MASK; 510 iowrite32be(tmp, ®s->fmbm_rebm); 511 512 /* Frame attributes */ 513 tmp = BMI_CMD_RX_MR_DEF; 514 tmp |= BMI_CMD_ATTR_ORDER; 515 tmp |= (u32)cfg->color << BMI_CMD_ATTR_COLOR_SHIFT; 516 /* Synchronization request */ 517 tmp |= BMI_CMD_ATTR_SYNC; 518 519 iowrite32be(tmp, ®s->fmbm_rfca); 520 521 /* NIA */ 522 tmp = (u32)cfg->rx_fd_bits << BMI_NEXT_ENG_FD_BITS_SHIFT; 523 524 tmp |= NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME; 525 iowrite32be(tmp, ®s->fmbm_rfne); 526 527 /* Enqueue NIA */ 528 iowrite32be(NIA_ENG_QMI_ENQ | NIA_ORDER_RESTOR, ®s->fmbm_rfene); 529 530 /* Default/error queues */ 531 iowrite32be((cfg->dflt_fqid & DFLT_FQ_ID), ®s->fmbm_rfqid); 532 iowrite32be((cfg->err_fqid & DFLT_FQ_ID), ®s->fmbm_refqid); 533 534 /* Discard/error masks */ 535 iowrite32be(cfg->discard_mask, ®s->fmbm_rfsdm); 536 iowrite32be(cfg->err_mask, ®s->fmbm_rfsem); 537 538 return 0; 539 } 540 541 static int init_bmi_tx(struct fman_port *port) 542 { 543 struct fman_port_tx_bmi_regs __iomem *regs = &port->bmi_regs->tx; 544 struct fman_port_cfg *cfg = port->cfg; 545 u32 tmp; 546 547 /* Tx Configuration register */ 548 tmp = 0; 549 iowrite32be(tmp, ®s->fmbm_tcfg); 550 551 /* DMA attributes */ 552 tmp = (u32)cfg->dma_swap_data << BMI_DMA_ATTR_SWP_SHIFT; 553 iowrite32be(tmp, ®s->fmbm_tda); 554 555 /* Tx FIFO parameters */ 556 tmp = (cfg->tx_fifo_min_level / PORT_BMI_FIFO_UNITS) << 557 BMI_TX_FIFO_MIN_FILL_SHIFT; 558 tmp |= ((cfg->tx_fifo_deq_pipeline_depth - 1) & 559 BMI_FIFO_PIPELINE_DEPTH_MASK) << BMI_FIFO_PIPELINE_DEPTH_SHIFT; 560 tmp |= (cfg->tx_fifo_low_comf_level / PORT_BMI_FIFO_UNITS) - 1; 561 iowrite32be(tmp, ®s->fmbm_tfp); 562 563 /* Frame end data */ 564 tmp = (cfg->cheksum_last_bytes_ignore & BMI_FRAME_END_CS_IGNORE_MASK) << 565 BMI_FRAME_END_CS_IGNORE_SHIFT; 566 iowrite32be(tmp, ®s->fmbm_tfed); 567 568 /* Internal context parameters */ 569 tmp = ((cfg->int_context.ext_buf_offset / PORT_IC_OFFSET_UNITS) & 570 BMI_IC_TO_EXT_MASK) << BMI_IC_TO_EXT_SHIFT; 571 tmp |= ((cfg->int_context.int_context_offset / PORT_IC_OFFSET_UNITS) & 572 BMI_IC_FROM_INT_MASK) << BMI_IC_FROM_INT_SHIFT; 573 tmp |= (cfg->int_context.size / PORT_IC_OFFSET_UNITS) & 574 BMI_IC_SIZE_MASK; 575 iowrite32be(tmp, ®s->fmbm_ticp); 576 577 /* Frame attributes */ 578 tmp = BMI_CMD_TX_MR_DEF; 579 tmp |= BMI_CMD_ATTR_ORDER; 580 tmp |= (u32)cfg->color << BMI_CMD_ATTR_COLOR_SHIFT; 581 iowrite32be(tmp, ®s->fmbm_tfca); 582 583 /* Dequeue NIA + enqueue NIA */ 584 iowrite32be(NIA_ENG_QMI_DEQ, ®s->fmbm_tfdne); 585 iowrite32be(NIA_ENG_QMI_ENQ | NIA_ORDER_RESTOR, ®s->fmbm_tfene); 586 if (cfg->fmbm_tfne_has_features) 587 iowrite32be(!cfg->dflt_fqid ? 588 BMI_EBD_EN | NIA_BMI_AC_FETCH_ALL_FRAME : 589 NIA_BMI_AC_FETCH_ALL_FRAME, ®s->fmbm_tfne); 590 if (!cfg->dflt_fqid && cfg->dont_release_buf) { 591 iowrite32be(DFLT_FQ_ID, ®s->fmbm_tcfqid); 592 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE, 593 ®s->fmbm_tfene); 594 if (cfg->fmbm_tfne_has_features) 595 iowrite32be(ioread32be(®s->fmbm_tfne) & ~BMI_EBD_EN, 596 ®s->fmbm_tfne); 597 } 598 599 /* Confirmation/error queues */ 600 if (cfg->dflt_fqid || !cfg->dont_release_buf) 601 iowrite32be(cfg->dflt_fqid & DFLT_FQ_ID, ®s->fmbm_tcfqid); 602 iowrite32be((cfg->err_fqid & DFLT_FQ_ID), ®s->fmbm_tefqid); 603 604 return 0; 605 } 606 607 static int init_qmi(struct fman_port *port) 608 { 609 struct fman_port_qmi_regs __iomem *regs = port->qmi_regs; 610 struct fman_port_cfg *cfg = port->cfg; 611 u32 tmp; 612 613 /* Rx port configuration */ 614 if (port->port_type == FMAN_PORT_TYPE_RX) { 615 /* Enqueue NIA */ 616 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_RELEASE, ®s->fmqm_pnen); 617 return 0; 618 } 619 620 /* Continue with Tx port configuration */ 621 if (port->port_type == FMAN_PORT_TYPE_TX) { 622 /* Enqueue NIA */ 623 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE, 624 ®s->fmqm_pnen); 625 /* Dequeue NIA */ 626 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX, ®s->fmqm_pndn); 627 } 628 629 /* Dequeue Configuration register */ 630 tmp = 0; 631 if (cfg->deq_high_priority) 632 tmp |= QMI_DEQ_CFG_PRI; 633 634 switch (cfg->deq_type) { 635 case FMAN_PORT_DEQ_BY_PRI: 636 tmp |= QMI_DEQ_CFG_TYPE1; 637 break; 638 case FMAN_PORT_DEQ_ACTIVE_FQ: 639 tmp |= QMI_DEQ_CFG_TYPE2; 640 break; 641 case FMAN_PORT_DEQ_ACTIVE_FQ_NO_ICS: 642 tmp |= QMI_DEQ_CFG_TYPE3; 643 break; 644 default: 645 return -EINVAL; 646 } 647 648 switch (cfg->deq_prefetch_option) { 649 case FMAN_PORT_DEQ_NO_PREFETCH: 650 break; 651 case FMAN_PORT_DEQ_PART_PREFETCH: 652 tmp |= QMI_DEQ_CFG_PREFETCH_PARTIAL; 653 break; 654 case FMAN_PORT_DEQ_FULL_PREFETCH: 655 tmp |= QMI_DEQ_CFG_PREFETCH_FULL; 656 break; 657 default: 658 return -EINVAL; 659 } 660 661 tmp |= (cfg->deq_sp & QMI_DEQ_CFG_SP_MASK) << QMI_DEQ_CFG_SP_SHIFT; 662 tmp |= cfg->deq_byte_cnt; 663 iowrite32be(tmp, ®s->fmqm_pndc); 664 665 return 0; 666 } 667 668 static int init(struct fman_port *port) 669 { 670 int err; 671 672 /* Init BMI registers */ 673 switch (port->port_type) { 674 case FMAN_PORT_TYPE_RX: 675 err = init_bmi_rx(port); 676 break; 677 case FMAN_PORT_TYPE_TX: 678 err = init_bmi_tx(port); 679 break; 680 default: 681 return -EINVAL; 682 } 683 684 if (err) 685 return err; 686 687 /* Init QMI registers */ 688 err = init_qmi(port); 689 return err; 690 691 return 0; 692 } 693 694 static int set_bpools(const struct fman_port *port, 695 const struct fman_port_bpools *bp) 696 { 697 u32 __iomem *bp_reg, *bp_depl_reg; 698 u32 tmp; 699 u8 i, max_bp_num; 700 bool grp_depl_used = false, rx_port; 701 702 switch (port->port_type) { 703 case FMAN_PORT_TYPE_RX: 704 max_bp_num = port->ext_pools_num; 705 rx_port = true; 706 bp_reg = port->bmi_regs->rx.fmbm_ebmpi; 707 bp_depl_reg = &port->bmi_regs->rx.fmbm_mpd; 708 break; 709 default: 710 return -EINVAL; 711 } 712 713 if (rx_port) { 714 /* Check buffers are provided in ascending order */ 715 for (i = 0; (i < (bp->count - 1) && 716 (i < FMAN_PORT_MAX_EXT_POOLS_NUM - 1)); i++) { 717 if (bp->bpool[i].size > bp->bpool[i + 1].size) 718 return -EINVAL; 719 } 720 } 721 722 /* Set up external buffers pools */ 723 for (i = 0; i < bp->count; i++) { 724 tmp = BMI_EXT_BUF_POOL_VALID; 725 tmp |= ((u32)bp->bpool[i].bpid << 726 BMI_EXT_BUF_POOL_ID_SHIFT) & BMI_EXT_BUF_POOL_ID_MASK; 727 728 if (rx_port) { 729 if (bp->counters_enable) 730 tmp |= BMI_EXT_BUF_POOL_EN_COUNTER; 731 732 if (bp->bpool[i].is_backup) 733 tmp |= BMI_EXT_BUF_POOL_BACKUP; 734 735 tmp |= (u32)bp->bpool[i].size; 736 } 737 738 iowrite32be(tmp, &bp_reg[i]); 739 } 740 741 /* Clear unused pools */ 742 for (i = bp->count; i < max_bp_num; i++) 743 iowrite32be(0, &bp_reg[i]); 744 745 /* Pools depletion */ 746 tmp = 0; 747 for (i = 0; i < FMAN_PORT_MAX_EXT_POOLS_NUM; i++) { 748 if (bp->bpool[i].grp_bp_depleted) { 749 grp_depl_used = true; 750 tmp |= 0x80000000 >> i; 751 } 752 753 if (bp->bpool[i].single_bp_depleted) 754 tmp |= 0x80 >> i; 755 } 756 757 if (grp_depl_used) 758 tmp |= ((u32)bp->grp_bp_depleted_num - 1) << 759 BMI_POOL_DEP_NUM_OF_POOLS_SHIFT; 760 761 iowrite32be(tmp, bp_depl_reg); 762 return 0; 763 } 764 765 static bool is_init_done(struct fman_port_cfg *cfg) 766 { 767 /* Checks if FMan port driver parameters were initialized */ 768 if (!cfg) 769 return true; 770 771 return false; 772 } 773 774 static int verify_size_of_fifo(struct fman_port *port) 775 { 776 u32 min_fifo_size_required = 0, opt_fifo_size_for_b2b = 0; 777 778 /* TX Ports */ 779 if (port->port_type == FMAN_PORT_TYPE_TX) { 780 min_fifo_size_required = (u32) 781 (roundup(port->max_frame_length, 782 FMAN_BMI_FIFO_UNITS) + (3 * FMAN_BMI_FIFO_UNITS)); 783 784 min_fifo_size_required += 785 port->cfg->tx_fifo_deq_pipeline_depth * 786 FMAN_BMI_FIFO_UNITS; 787 788 opt_fifo_size_for_b2b = min_fifo_size_required; 789 790 /* Add some margin for back-to-back capability to improve 791 * performance, allows the hardware to pipeline new frame dma 792 * while the previous frame not yet transmitted. 793 */ 794 if (port->port_speed == 10000) 795 opt_fifo_size_for_b2b += 3 * FMAN_BMI_FIFO_UNITS; 796 else 797 opt_fifo_size_for_b2b += 2 * FMAN_BMI_FIFO_UNITS; 798 } 799 800 /* RX Ports */ 801 else if (port->port_type == FMAN_PORT_TYPE_RX) { 802 if (port->rev_info.major >= 6) 803 min_fifo_size_required = (u32) 804 (roundup(port->max_frame_length, 805 FMAN_BMI_FIFO_UNITS) + 806 (5 * FMAN_BMI_FIFO_UNITS)); 807 /* 4 according to spec + 1 for FOF>0 */ 808 else 809 min_fifo_size_required = (u32) 810 (roundup(min(port->max_frame_length, 811 port->rx_pools_params.largest_buf_size), 812 FMAN_BMI_FIFO_UNITS) + 813 (7 * FMAN_BMI_FIFO_UNITS)); 814 815 opt_fifo_size_for_b2b = min_fifo_size_required; 816 817 /* Add some margin for back-to-back capability to improve 818 * performance,allows the hardware to pipeline new frame dma 819 * while the previous frame not yet transmitted. 820 */ 821 if (port->port_speed == 10000) 822 opt_fifo_size_for_b2b += 8 * FMAN_BMI_FIFO_UNITS; 823 else 824 opt_fifo_size_for_b2b += 3 * FMAN_BMI_FIFO_UNITS; 825 } 826 827 WARN_ON(min_fifo_size_required <= 0); 828 WARN_ON(opt_fifo_size_for_b2b < min_fifo_size_required); 829 830 /* Verify the size */ 831 if (port->fifo_bufs.num < min_fifo_size_required) 832 dev_dbg(port->dev, "%s: FIFO size should be enlarged to %d bytes\n", 833 __func__, min_fifo_size_required); 834 else if (port->fifo_bufs.num < opt_fifo_size_for_b2b) 835 dev_dbg(port->dev, "%s: For b2b processing,FIFO may be enlarged to %d bytes\n", 836 __func__, opt_fifo_size_for_b2b); 837 838 return 0; 839 } 840 841 static int set_ext_buffer_pools(struct fman_port *port) 842 { 843 struct fman_ext_pools *ext_buf_pools = &port->cfg->ext_buf_pools; 844 struct fman_buf_pool_depletion *buf_pool_depletion = 845 &port->cfg->buf_pool_depletion; 846 u8 ordered_array[FMAN_PORT_MAX_EXT_POOLS_NUM]; 847 u16 sizes_array[BM_MAX_NUM_OF_POOLS]; 848 int i = 0, j = 0, err; 849 struct fman_port_bpools bpools; 850 851 memset(&ordered_array, 0, sizeof(u8) * FMAN_PORT_MAX_EXT_POOLS_NUM); 852 memset(&sizes_array, 0, sizeof(u16) * BM_MAX_NUM_OF_POOLS); 853 memcpy(&port->ext_buf_pools, ext_buf_pools, 854 sizeof(struct fman_ext_pools)); 855 856 fman_sp_set_buf_pools_in_asc_order_of_buf_sizes(ext_buf_pools, 857 ordered_array, 858 sizes_array); 859 860 memset(&bpools, 0, sizeof(struct fman_port_bpools)); 861 bpools.count = ext_buf_pools->num_of_pools_used; 862 bpools.counters_enable = true; 863 for (i = 0; i < ext_buf_pools->num_of_pools_used; i++) { 864 bpools.bpool[i].bpid = ordered_array[i]; 865 bpools.bpool[i].size = sizes_array[ordered_array[i]]; 866 } 867 868 /* save pools parameters for later use */ 869 port->rx_pools_params.num_of_pools = ext_buf_pools->num_of_pools_used; 870 port->rx_pools_params.largest_buf_size = 871 sizes_array[ordered_array[ext_buf_pools->num_of_pools_used - 1]]; 872 port->rx_pools_params.second_largest_buf_size = 873 sizes_array[ordered_array[ext_buf_pools->num_of_pools_used - 2]]; 874 875 /* FMBM_RMPD reg. - pool depletion */ 876 if (buf_pool_depletion->pools_grp_mode_enable) { 877 bpools.grp_bp_depleted_num = buf_pool_depletion->num_of_pools; 878 for (i = 0; i < port->bm_max_num_of_pools; i++) { 879 if (buf_pool_depletion->pools_to_consider[i]) { 880 for (j = 0; j < ext_buf_pools-> 881 num_of_pools_used; j++) { 882 if (i == ordered_array[j]) { 883 bpools.bpool[j]. 884 grp_bp_depleted = true; 885 break; 886 } 887 } 888 } 889 } 890 } 891 892 if (buf_pool_depletion->single_pool_mode_enable) { 893 for (i = 0; i < port->bm_max_num_of_pools; i++) { 894 if (buf_pool_depletion-> 895 pools_to_consider_for_single_mode[i]) { 896 for (j = 0; j < ext_buf_pools-> 897 num_of_pools_used; j++) { 898 if (i == ordered_array[j]) { 899 bpools.bpool[j]. 900 single_bp_depleted = true; 901 break; 902 } 903 } 904 } 905 } 906 } 907 908 err = set_bpools(port, &bpools); 909 if (err != 0) { 910 dev_err(port->dev, "%s: set_bpools() failed\n", __func__); 911 return -EINVAL; 912 } 913 914 return 0; 915 } 916 917 static int init_low_level_driver(struct fman_port *port) 918 { 919 struct fman_port_cfg *cfg = port->cfg; 920 u32 tmp_val; 921 922 switch (port->port_type) { 923 case FMAN_PORT_TYPE_RX: 924 cfg->err_mask = (RX_ERRS_TO_ENQ & ~cfg->discard_mask); 925 break; 926 default: 927 break; 928 } 929 930 tmp_val = (u32)((port->internal_buf_offset % OFFSET_UNITS) ? 931 (port->internal_buf_offset / OFFSET_UNITS + 1) : 932 (port->internal_buf_offset / OFFSET_UNITS)); 933 port->internal_buf_offset = (u8)(tmp_val * OFFSET_UNITS); 934 port->cfg->int_buf_start_margin = port->internal_buf_offset; 935 936 if (init(port) != 0) { 937 dev_err(port->dev, "%s: fman port initialization failed\n", 938 __func__); 939 return -ENODEV; 940 } 941 942 /* The code bellow is a trick so the FM will not release the buffer 943 * to BM nor will try to enqueue the frame to QM 944 */ 945 if (port->port_type == FMAN_PORT_TYPE_TX) { 946 if (!cfg->dflt_fqid && cfg->dont_release_buf) { 947 /* override fmbm_tcfqid 0 with a false non-0 value. 948 * This will force FM to act according to tfene. 949 * Otherwise, if fmbm_tcfqid is 0 the FM will release 950 * buffers to BM regardless of fmbm_tfene 951 */ 952 iowrite32be(0xFFFFFF, &port->bmi_regs->tx.fmbm_tcfqid); 953 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE, 954 &port->bmi_regs->tx.fmbm_tfene); 955 } 956 } 957 958 return 0; 959 } 960 961 static int fill_soc_specific_params(struct fman_port *port) 962 { 963 u32 bmi_max_fifo_size; 964 965 bmi_max_fifo_size = fman_get_bmi_max_fifo_size(port->fm); 966 port->max_port_fifo_size = MAX_PORT_FIFO_SIZE(bmi_max_fifo_size); 967 port->bm_max_num_of_pools = 64; 968 969 /* P4080 - Major 2 970 * P2041/P3041/P5020/P5040 - Major 3 971 * Tx/Bx - Major 6 972 */ 973 switch (port->rev_info.major) { 974 case 2: 975 case 3: 976 port->max_num_of_ext_pools = 4; 977 port->max_num_of_sub_portals = 12; 978 break; 979 980 case 6: 981 port->max_num_of_ext_pools = 8; 982 port->max_num_of_sub_portals = 16; 983 break; 984 985 default: 986 dev_err(port->dev, "%s: Unsupported FMan version\n", __func__); 987 return -EINVAL; 988 } 989 990 return 0; 991 } 992 993 static int get_dflt_fifo_deq_pipeline_depth(u8 major, enum fman_port_type type, 994 u16 speed) 995 { 996 switch (type) { 997 case FMAN_PORT_TYPE_RX: 998 case FMAN_PORT_TYPE_TX: 999 switch (speed) { 1000 case 10000: 1001 return 4; 1002 case 1000: 1003 if (major >= 6) 1004 return 2; 1005 else 1006 return 1; 1007 default: 1008 return 0; 1009 } 1010 default: 1011 return 0; 1012 } 1013 } 1014 1015 static int get_dflt_num_of_tasks(u8 major, enum fman_port_type type, 1016 u16 speed) 1017 { 1018 switch (type) { 1019 case FMAN_PORT_TYPE_RX: 1020 case FMAN_PORT_TYPE_TX: 1021 switch (speed) { 1022 case 10000: 1023 return 16; 1024 case 1000: 1025 if (major >= 6) 1026 return 4; 1027 else 1028 return 3; 1029 default: 1030 return 0; 1031 } 1032 default: 1033 return 0; 1034 } 1035 } 1036 1037 static int get_dflt_extra_num_of_tasks(u8 major, enum fman_port_type type, 1038 u16 speed) 1039 { 1040 switch (type) { 1041 case FMAN_PORT_TYPE_RX: 1042 /* FMan V3 */ 1043 if (major >= 6) 1044 return 0; 1045 1046 /* FMan V2 */ 1047 if (speed == 10000) 1048 return 8; 1049 else 1050 return 2; 1051 case FMAN_PORT_TYPE_TX: 1052 default: 1053 return 0; 1054 } 1055 } 1056 1057 static int get_dflt_num_of_open_dmas(u8 major, enum fman_port_type type, 1058 u16 speed) 1059 { 1060 int val; 1061 1062 if (major >= 6) { 1063 switch (type) { 1064 case FMAN_PORT_TYPE_TX: 1065 if (speed == 10000) 1066 val = 12; 1067 else 1068 val = 3; 1069 break; 1070 case FMAN_PORT_TYPE_RX: 1071 if (speed == 10000) 1072 val = 8; 1073 else 1074 val = 2; 1075 break; 1076 default: 1077 return 0; 1078 } 1079 } else { 1080 switch (type) { 1081 case FMAN_PORT_TYPE_TX: 1082 case FMAN_PORT_TYPE_RX: 1083 if (speed == 10000) 1084 val = 8; 1085 else 1086 val = 1; 1087 break; 1088 default: 1089 val = 0; 1090 } 1091 } 1092 1093 return val; 1094 } 1095 1096 static int get_dflt_extra_num_of_open_dmas(u8 major, enum fman_port_type type, 1097 u16 speed) 1098 { 1099 /* FMan V3 */ 1100 if (major >= 6) 1101 return 0; 1102 1103 /* FMan V2 */ 1104 switch (type) { 1105 case FMAN_PORT_TYPE_RX: 1106 case FMAN_PORT_TYPE_TX: 1107 if (speed == 10000) 1108 return 8; 1109 else 1110 return 1; 1111 default: 1112 return 0; 1113 } 1114 } 1115 1116 static int get_dflt_num_of_fifo_bufs(u8 major, enum fman_port_type type, 1117 u16 speed) 1118 { 1119 int val; 1120 1121 if (major >= 6) { 1122 switch (type) { 1123 case FMAN_PORT_TYPE_TX: 1124 if (speed == 10000) 1125 val = 64; 1126 else 1127 val = 50; 1128 break; 1129 case FMAN_PORT_TYPE_RX: 1130 if (speed == 10000) 1131 val = 96; 1132 else 1133 val = 50; 1134 break; 1135 default: 1136 val = 0; 1137 } 1138 } else { 1139 switch (type) { 1140 case FMAN_PORT_TYPE_TX: 1141 if (speed == 10000) 1142 val = 48; 1143 else 1144 val = 44; 1145 break; 1146 case FMAN_PORT_TYPE_RX: 1147 if (speed == 10000) 1148 val = 48; 1149 else 1150 val = 45; 1151 break; 1152 default: 1153 val = 0; 1154 } 1155 } 1156 1157 return val; 1158 } 1159 1160 static void set_dflt_cfg(struct fman_port *port, 1161 struct fman_port_params *port_params) 1162 { 1163 struct fman_port_cfg *cfg = port->cfg; 1164 1165 cfg->dma_swap_data = FMAN_PORT_DMA_NO_SWAP; 1166 cfg->color = FMAN_PORT_COLOR_GREEN; 1167 cfg->rx_cut_end_bytes = DFLT_PORT_CUT_BYTES_FROM_END; 1168 cfg->rx_pri_elevation = BMI_PRIORITY_ELEVATION_LEVEL; 1169 cfg->rx_fifo_thr = BMI_FIFO_THRESHOLD; 1170 cfg->tx_fifo_low_comf_level = (5 * 1024); 1171 cfg->deq_type = FMAN_PORT_DEQ_BY_PRI; 1172 cfg->deq_prefetch_option = FMAN_PORT_DEQ_FULL_PREFETCH; 1173 cfg->tx_fifo_deq_pipeline_depth = 1174 BMI_DEQUEUE_PIPELINE_DEPTH(port->port_type, port->port_speed); 1175 cfg->deq_byte_cnt = QMI_BYTE_COUNT_LEVEL_CONTROL(port->port_type); 1176 1177 cfg->rx_pri_elevation = 1178 DFLT_PORT_RX_FIFO_PRI_ELEVATION_LEV(port->max_port_fifo_size); 1179 port->cfg->rx_fifo_thr = 1180 DFLT_PORT_RX_FIFO_THRESHOLD(port->rev_info.major, 1181 port->max_port_fifo_size); 1182 1183 if ((port->rev_info.major == 6) && 1184 ((port->rev_info.minor == 0) || (port->rev_info.minor == 3))) 1185 cfg->errata_A006320 = true; 1186 1187 /* Excessive Threshold register - exists for pre-FMv3 chips only */ 1188 if (port->rev_info.major < 6) 1189 cfg->excessive_threshold_register = true; 1190 else 1191 cfg->fmbm_tfne_has_features = true; 1192 1193 cfg->buffer_prefix_content.data_align = 1194 DFLT_PORT_BUFFER_PREFIX_CONTEXT_DATA_ALIGN; 1195 } 1196 1197 static void set_rx_dflt_cfg(struct fman_port *port, 1198 struct fman_port_params *port_params) 1199 { 1200 port->cfg->discard_mask = DFLT_PORT_ERRORS_TO_DISCARD; 1201 1202 memcpy(&port->cfg->ext_buf_pools, 1203 &port_params->specific_params.rx_params.ext_buf_pools, 1204 sizeof(struct fman_ext_pools)); 1205 port->cfg->err_fqid = 1206 port_params->specific_params.rx_params.err_fqid; 1207 port->cfg->dflt_fqid = 1208 port_params->specific_params.rx_params.dflt_fqid; 1209 } 1210 1211 static void set_tx_dflt_cfg(struct fman_port *port, 1212 struct fman_port_params *port_params, 1213 struct fman_port_dts_params *dts_params) 1214 { 1215 port->cfg->tx_fifo_deq_pipeline_depth = 1216 get_dflt_fifo_deq_pipeline_depth(port->rev_info.major, 1217 port->port_type, 1218 port->port_speed); 1219 port->cfg->err_fqid = 1220 port_params->specific_params.non_rx_params.err_fqid; 1221 port->cfg->deq_sp = 1222 (u8)(dts_params->qman_channel_id & QMI_DEQ_CFG_SUBPORTAL_MASK); 1223 port->cfg->dflt_fqid = 1224 port_params->specific_params.non_rx_params.dflt_fqid; 1225 port->cfg->deq_high_priority = true; 1226 } 1227 1228 /** 1229 * fman_port_config 1230 * @port: Pointer to the port structure 1231 * @params: Pointer to data structure of parameters 1232 * 1233 * Creates a descriptor for the FM PORT module. 1234 * The routine returns a pointer to the FM PORT object. 1235 * This descriptor must be passed as first parameter to all other FM PORT 1236 * function calls. 1237 * No actual initialization or configuration of FM hardware is done by this 1238 * routine. 1239 * 1240 * Return: 0 on success; Error code otherwise. 1241 */ 1242 int fman_port_config(struct fman_port *port, struct fman_port_params *params) 1243 { 1244 void __iomem *base_addr = port->dts_params.base_addr; 1245 int err; 1246 1247 /* Allocate the FM driver's parameters structure */ 1248 port->cfg = kzalloc(sizeof(*port->cfg), GFP_KERNEL); 1249 if (!port->cfg) 1250 goto err_params; 1251 1252 /* Initialize FM port parameters which will be kept by the driver */ 1253 port->port_type = port->dts_params.type; 1254 port->port_speed = port->dts_params.speed; 1255 port->port_id = port->dts_params.id; 1256 port->fm = port->dts_params.fman; 1257 port->ext_pools_num = (u8)8; 1258 1259 /* get FM revision */ 1260 fman_get_revision(port->fm, &port->rev_info); 1261 1262 err = fill_soc_specific_params(port); 1263 if (err) 1264 goto err_port_cfg; 1265 1266 switch (port->port_type) { 1267 case FMAN_PORT_TYPE_RX: 1268 set_rx_dflt_cfg(port, params); 1269 case FMAN_PORT_TYPE_TX: 1270 set_tx_dflt_cfg(port, params, &port->dts_params); 1271 default: 1272 set_dflt_cfg(port, params); 1273 } 1274 1275 /* Continue with other parameters */ 1276 /* set memory map pointers */ 1277 port->bmi_regs = base_addr + BMI_PORT_REGS_OFFSET; 1278 port->qmi_regs = base_addr + QMI_PORT_REGS_OFFSET; 1279 1280 port->max_frame_length = DFLT_PORT_MAX_FRAME_LENGTH; 1281 /* resource distribution. */ 1282 1283 port->fifo_bufs.num = 1284 get_dflt_num_of_fifo_bufs(port->rev_info.major, port->port_type, 1285 port->port_speed) * FMAN_BMI_FIFO_UNITS; 1286 port->fifo_bufs.extra = 1287 DFLT_PORT_EXTRA_NUM_OF_FIFO_BUFS * FMAN_BMI_FIFO_UNITS; 1288 1289 port->open_dmas.num = 1290 get_dflt_num_of_open_dmas(port->rev_info.major, 1291 port->port_type, port->port_speed); 1292 port->open_dmas.extra = 1293 get_dflt_extra_num_of_open_dmas(port->rev_info.major, 1294 port->port_type, port->port_speed); 1295 port->tasks.num = 1296 get_dflt_num_of_tasks(port->rev_info.major, 1297 port->port_type, port->port_speed); 1298 port->tasks.extra = 1299 get_dflt_extra_num_of_tasks(port->rev_info.major, 1300 port->port_type, port->port_speed); 1301 1302 /* FM_HEAVY_TRAFFIC_SEQUENCER_HANG_ERRATA_FMAN_A006981 errata 1303 * workaround 1304 */ 1305 if ((port->rev_info.major == 6) && (port->rev_info.minor == 0) && 1306 (((port->port_type == FMAN_PORT_TYPE_TX) && 1307 (port->port_speed == 1000)))) { 1308 port->open_dmas.num = 16; 1309 port->open_dmas.extra = 0; 1310 } 1311 1312 if (port->rev_info.major >= 6 && 1313 port->port_type == FMAN_PORT_TYPE_TX && 1314 port->port_speed == 1000) { 1315 /* FM_WRONG_RESET_VALUES_ERRATA_FMAN_A005127 Errata 1316 * workaround 1317 */ 1318 if (port->rev_info.major >= 6) { 1319 u32 reg; 1320 1321 reg = 0x00001013; 1322 iowrite32be(reg, &port->bmi_regs->tx.fmbm_tfp); 1323 } 1324 } 1325 1326 return 0; 1327 1328 err_port_cfg: 1329 kfree(port->cfg); 1330 err_params: 1331 kfree(port); 1332 return -EINVAL; 1333 } 1334 EXPORT_SYMBOL(fman_port_config); 1335 1336 /** 1337 * fman_port_init 1338 * port: A pointer to a FM Port module. 1339 * Initializes the FM PORT module by defining the software structure and 1340 * configuring the hardware registers. 1341 * 1342 * Return: 0 on success; Error code otherwise. 1343 */ 1344 int fman_port_init(struct fman_port *port) 1345 { 1346 struct fman_port_cfg *cfg; 1347 int err; 1348 struct fman_port_init_params params; 1349 1350 if (is_init_done(port->cfg)) 1351 return -EINVAL; 1352 1353 err = fman_sp_build_buffer_struct(&port->cfg->int_context, 1354 &port->cfg->buffer_prefix_content, 1355 &port->cfg->buf_margins, 1356 &port->buffer_offsets, 1357 &port->internal_buf_offset); 1358 if (err) 1359 return err; 1360 1361 cfg = port->cfg; 1362 1363 if (port->port_type == FMAN_PORT_TYPE_RX) { 1364 /* Call the external Buffer routine which also checks fifo 1365 * size and updates it if necessary 1366 */ 1367 /* define external buffer pools and pool depletion */ 1368 err = set_ext_buffer_pools(port); 1369 if (err) 1370 return err; 1371 /* check if the largest external buffer pool is large enough */ 1372 if (cfg->buf_margins.start_margins + MIN_EXT_BUF_SIZE + 1373 cfg->buf_margins.end_margins > 1374 port->rx_pools_params.largest_buf_size) { 1375 dev_err(port->dev, "%s: buf_margins.start_margins (%d) + minimum buf size (64) + buf_margins.end_margins (%d) is larger than maximum external buffer size (%d)\n", 1376 __func__, cfg->buf_margins.start_margins, 1377 cfg->buf_margins.end_margins, 1378 port->rx_pools_params.largest_buf_size); 1379 return -EINVAL; 1380 } 1381 } 1382 1383 /* Call FM module routine for communicating parameters */ 1384 memset(¶ms, 0, sizeof(params)); 1385 params.port_id = port->port_id; 1386 params.port_type = port->port_type; 1387 params.port_speed = port->port_speed; 1388 params.num_of_tasks = (u8)port->tasks.num; 1389 params.num_of_extra_tasks = (u8)port->tasks.extra; 1390 params.num_of_open_dmas = (u8)port->open_dmas.num; 1391 params.num_of_extra_open_dmas = (u8)port->open_dmas.extra; 1392 1393 if (port->fifo_bufs.num) { 1394 err = verify_size_of_fifo(port); 1395 if (err) 1396 return err; 1397 } 1398 params.size_of_fifo = port->fifo_bufs.num; 1399 params.extra_size_of_fifo = port->fifo_bufs.extra; 1400 params.deq_pipeline_depth = port->cfg->tx_fifo_deq_pipeline_depth; 1401 params.max_frame_length = port->max_frame_length; 1402 1403 err = fman_set_port_params(port->fm, ¶ms); 1404 if (err) 1405 return err; 1406 1407 err = init_low_level_driver(port); 1408 if (err) 1409 return err; 1410 1411 kfree(port->cfg); 1412 port->cfg = NULL; 1413 1414 return 0; 1415 } 1416 EXPORT_SYMBOL(fman_port_init); 1417 1418 /** 1419 * fman_port_cfg_buf_prefix_content 1420 * @port A pointer to a FM Port module. 1421 * @buffer_prefix_content A structure of parameters describing 1422 * the structure of the buffer. 1423 * Out parameter: 1424 * Start margin - offset of data from 1425 * start of external buffer. 1426 * Defines the structure, size and content of the application buffer. 1427 * The prefix, in Tx ports, if 'pass_prs_result', the application should set 1428 * a value to their offsets in the prefix of the FM will save the first 1429 * 'priv_data_size', than, depending on 'pass_prs_result' and 1430 * 'pass_time_stamp', copy parse result and timeStamp, and the packet itself 1431 * (in this order), to the application buffer, and to offset. 1432 * Calling this routine changes the buffer margins definitions in the internal 1433 * driver data base from its default configuration: 1434 * Data size: [DEFAULT_PORT_BUFFER_PREFIX_CONTENT_PRIV_DATA_SIZE] 1435 * Pass Parser result: [DEFAULT_PORT_BUFFER_PREFIX_CONTENT_PASS_PRS_RESULT]. 1436 * Pass timestamp: [DEFAULT_PORT_BUFFER_PREFIX_CONTENT_PASS_TIME_STAMP]. 1437 * May be used for all ports 1438 * 1439 * Allowed only following fman_port_config() and before fman_port_init(). 1440 * 1441 * Return: 0 on success; Error code otherwise. 1442 */ 1443 int fman_port_cfg_buf_prefix_content(struct fman_port *port, 1444 struct fman_buffer_prefix_content * 1445 buffer_prefix_content) 1446 { 1447 if (is_init_done(port->cfg)) 1448 return -EINVAL; 1449 1450 memcpy(&port->cfg->buffer_prefix_content, 1451 buffer_prefix_content, 1452 sizeof(struct fman_buffer_prefix_content)); 1453 /* if data_align was not initialized by user, 1454 * we return to driver's default 1455 */ 1456 if (!port->cfg->buffer_prefix_content.data_align) 1457 port->cfg->buffer_prefix_content.data_align = 1458 DFLT_PORT_BUFFER_PREFIX_CONTEXT_DATA_ALIGN; 1459 1460 return 0; 1461 } 1462 EXPORT_SYMBOL(fman_port_cfg_buf_prefix_content); 1463 1464 /** 1465 * fman_port_disable 1466 * port: A pointer to a FM Port module. 1467 * 1468 * Gracefully disable an FM port. The port will not start new tasks after all 1469 * tasks associated with the port are terminated. 1470 * 1471 * This is a blocking routine, it returns after port is gracefully stopped, 1472 * i.e. the port will not except new frames, but it will finish all frames 1473 * or tasks which were already began. 1474 * Allowed only following fman_port_init(). 1475 * 1476 * Return: 0 on success; Error code otherwise. 1477 */ 1478 int fman_port_disable(struct fman_port *port) 1479 { 1480 u32 __iomem *bmi_cfg_reg, *bmi_status_reg; 1481 u32 tmp; 1482 bool rx_port, failure = false; 1483 int count; 1484 1485 if (!is_init_done(port->cfg)) 1486 return -EINVAL; 1487 1488 switch (port->port_type) { 1489 case FMAN_PORT_TYPE_RX: 1490 bmi_cfg_reg = &port->bmi_regs->rx.fmbm_rcfg; 1491 bmi_status_reg = &port->bmi_regs->rx.fmbm_rst; 1492 rx_port = true; 1493 break; 1494 case FMAN_PORT_TYPE_TX: 1495 bmi_cfg_reg = &port->bmi_regs->tx.fmbm_tcfg; 1496 bmi_status_reg = &port->bmi_regs->tx.fmbm_tst; 1497 rx_port = false; 1498 break; 1499 default: 1500 return -EINVAL; 1501 } 1502 1503 /* Disable QMI */ 1504 if (!rx_port) { 1505 tmp = ioread32be(&port->qmi_regs->fmqm_pnc) & ~QMI_PORT_CFG_EN; 1506 iowrite32be(tmp, &port->qmi_regs->fmqm_pnc); 1507 1508 /* Wait for QMI to finish FD handling */ 1509 count = 100; 1510 do { 1511 udelay(10); 1512 tmp = ioread32be(&port->qmi_regs->fmqm_pns); 1513 } while ((tmp & QMI_PORT_STATUS_DEQ_FD_BSY) && --count); 1514 1515 if (count == 0) { 1516 /* Timeout */ 1517 failure = true; 1518 } 1519 } 1520 1521 /* Disable BMI */ 1522 tmp = ioread32be(bmi_cfg_reg) & ~BMI_PORT_CFG_EN; 1523 iowrite32be(tmp, bmi_cfg_reg); 1524 1525 /* Wait for graceful stop end */ 1526 count = 500; 1527 do { 1528 udelay(10); 1529 tmp = ioread32be(bmi_status_reg); 1530 } while ((tmp & BMI_PORT_STATUS_BSY) && --count); 1531 1532 if (count == 0) { 1533 /* Timeout */ 1534 failure = true; 1535 } 1536 1537 if (failure) 1538 dev_dbg(port->dev, "%s: FMan Port[%d]: BMI or QMI is Busy. Port forced down\n", 1539 __func__, port->port_id); 1540 1541 return 0; 1542 } 1543 EXPORT_SYMBOL(fman_port_disable); 1544 1545 /** 1546 * fman_port_enable 1547 * port: A pointer to a FM Port module. 1548 * 1549 * A runtime routine provided to allow disable/enable of port. 1550 * 1551 * Allowed only following fman_port_init(). 1552 * 1553 * Return: 0 on success; Error code otherwise. 1554 */ 1555 int fman_port_enable(struct fman_port *port) 1556 { 1557 u32 __iomem *bmi_cfg_reg; 1558 u32 tmp; 1559 bool rx_port; 1560 1561 if (!is_init_done(port->cfg)) 1562 return -EINVAL; 1563 1564 switch (port->port_type) { 1565 case FMAN_PORT_TYPE_RX: 1566 bmi_cfg_reg = &port->bmi_regs->rx.fmbm_rcfg; 1567 rx_port = true; 1568 break; 1569 case FMAN_PORT_TYPE_TX: 1570 bmi_cfg_reg = &port->bmi_regs->tx.fmbm_tcfg; 1571 rx_port = false; 1572 break; 1573 default: 1574 return -EINVAL; 1575 } 1576 1577 /* Enable QMI */ 1578 if (!rx_port) { 1579 tmp = ioread32be(&port->qmi_regs->fmqm_pnc) | QMI_PORT_CFG_EN; 1580 iowrite32be(tmp, &port->qmi_regs->fmqm_pnc); 1581 } 1582 1583 /* Enable BMI */ 1584 tmp = ioread32be(bmi_cfg_reg) | BMI_PORT_CFG_EN; 1585 iowrite32be(tmp, bmi_cfg_reg); 1586 1587 return 0; 1588 } 1589 EXPORT_SYMBOL(fman_port_enable); 1590 1591 /** 1592 * fman_port_bind 1593 * dev: FMan Port OF device pointer 1594 * 1595 * Bind to a specific FMan Port. 1596 * 1597 * Allowed only after the port was created. 1598 * 1599 * Return: A pointer to the FMan port device. 1600 */ 1601 struct fman_port *fman_port_bind(struct device *dev) 1602 { 1603 return (struct fman_port *)(dev_get_drvdata(get_device(dev))); 1604 } 1605 EXPORT_SYMBOL(fman_port_bind); 1606 1607 /** 1608 * fman_port_get_qman_channel_id 1609 * port: Pointer to the FMan port devuce 1610 * 1611 * Get the QMan channel ID for the specific port 1612 * 1613 * Return: QMan channel ID 1614 */ 1615 u32 fman_port_get_qman_channel_id(struct fman_port *port) 1616 { 1617 return port->dts_params.qman_channel_id; 1618 } 1619 EXPORT_SYMBOL(fman_port_get_qman_channel_id); 1620 1621 static int fman_port_probe(struct platform_device *of_dev) 1622 { 1623 struct fman_port *port; 1624 struct fman *fman; 1625 struct device_node *fm_node, *port_node; 1626 struct resource res; 1627 struct resource *dev_res; 1628 u32 val; 1629 int err = 0, lenp; 1630 enum fman_port_type port_type; 1631 u16 port_speed; 1632 u8 port_id; 1633 1634 port = kzalloc(sizeof(*port), GFP_KERNEL); 1635 if (!port) 1636 return -ENOMEM; 1637 1638 port->dev = &of_dev->dev; 1639 1640 port_node = of_node_get(of_dev->dev.of_node); 1641 1642 /* Get the FM node */ 1643 fm_node = of_get_parent(port_node); 1644 if (!fm_node) { 1645 dev_err(port->dev, "%s: of_get_parent() failed\n", __func__); 1646 err = -ENODEV; 1647 goto return_err; 1648 } 1649 1650 fman = dev_get_drvdata(&of_find_device_by_node(fm_node)->dev); 1651 of_node_put(fm_node); 1652 if (!fman) { 1653 err = -EINVAL; 1654 goto return_err; 1655 } 1656 1657 err = of_property_read_u32(port_node, "cell-index", &val); 1658 if (err) { 1659 dev_err(port->dev, "%s: reading cell-index for %s failed\n", 1660 __func__, port_node->full_name); 1661 err = -EINVAL; 1662 goto return_err; 1663 } 1664 port_id = (u8)val; 1665 port->dts_params.id = port_id; 1666 1667 if (of_device_is_compatible(port_node, "fsl,fman-v3-port-tx")) { 1668 port_type = FMAN_PORT_TYPE_TX; 1669 port_speed = 1000; 1670 if (of_find_property(port_node, "fsl,fman-10g-port", &lenp)) 1671 port_speed = 10000; 1672 1673 } else if (of_device_is_compatible(port_node, "fsl,fman-v2-port-tx")) { 1674 if (port_id >= TX_10G_PORT_BASE) 1675 port_speed = 10000; 1676 else 1677 port_speed = 1000; 1678 port_type = FMAN_PORT_TYPE_TX; 1679 1680 } else if (of_device_is_compatible(port_node, "fsl,fman-v3-port-rx")) { 1681 port_type = FMAN_PORT_TYPE_RX; 1682 port_speed = 1000; 1683 if (of_find_property(port_node, "fsl,fman-10g-port", &lenp)) 1684 port_speed = 10000; 1685 1686 } else if (of_device_is_compatible(port_node, "fsl,fman-v2-port-rx")) { 1687 if (port_id >= RX_10G_PORT_BASE) 1688 port_speed = 10000; 1689 else 1690 port_speed = 1000; 1691 port_type = FMAN_PORT_TYPE_RX; 1692 1693 } else { 1694 dev_err(port->dev, "%s: Illegal port type\n", __func__); 1695 err = -EINVAL; 1696 goto return_err; 1697 } 1698 1699 port->dts_params.type = port_type; 1700 port->dts_params.speed = port_speed; 1701 1702 if (port_type == FMAN_PORT_TYPE_TX) { 1703 u32 qman_channel_id; 1704 1705 qman_channel_id = fman_get_qman_channel_id(fman, port_id); 1706 if (qman_channel_id == 0) { 1707 dev_err(port->dev, "%s: incorrect qman-channel-id\n", 1708 __func__); 1709 err = -EINVAL; 1710 goto return_err; 1711 } 1712 port->dts_params.qman_channel_id = qman_channel_id; 1713 } 1714 1715 err = of_address_to_resource(port_node, 0, &res); 1716 if (err < 0) { 1717 dev_err(port->dev, "%s: of_address_to_resource() failed\n", 1718 __func__); 1719 err = -ENOMEM; 1720 goto return_err; 1721 } 1722 1723 port->dts_params.fman = fman; 1724 1725 of_node_put(port_node); 1726 1727 dev_res = __devm_request_region(port->dev, &res, res.start, 1728 resource_size(&res), "fman-port"); 1729 if (!dev_res) { 1730 dev_err(port->dev, "%s: __devm_request_region() failed\n", 1731 __func__); 1732 err = -EINVAL; 1733 goto free_port; 1734 } 1735 1736 port->dts_params.base_addr = devm_ioremap(port->dev, res.start, 1737 resource_size(&res)); 1738 if (!port->dts_params.base_addr) 1739 dev_err(port->dev, "%s: devm_ioremap() failed\n", __func__); 1740 1741 dev_set_drvdata(&of_dev->dev, port); 1742 1743 return 0; 1744 1745 return_err: 1746 of_node_put(port_node); 1747 free_port: 1748 kfree(port); 1749 return err; 1750 } 1751 1752 static const struct of_device_id fman_port_match[] = { 1753 {.compatible = "fsl,fman-v3-port-rx"}, 1754 {.compatible = "fsl,fman-v2-port-rx"}, 1755 {.compatible = "fsl,fman-v3-port-tx"}, 1756 {.compatible = "fsl,fman-v2-port-tx"}, 1757 {} 1758 }; 1759 1760 MODULE_DEVICE_TABLE(of, fman_port_match); 1761 1762 static struct platform_driver fman_port_driver = { 1763 .driver = { 1764 .name = "fsl-fman-port", 1765 .of_match_table = fman_port_match, 1766 }, 1767 .probe = fman_port_probe, 1768 }; 1769 1770 static int __init fman_port_load(void) 1771 { 1772 int err; 1773 1774 pr_debug("FSL DPAA FMan driver\n"); 1775 1776 err = platform_driver_register(&fman_port_driver); 1777 if (err < 0) 1778 pr_err("Error, platform_driver_register() = %d\n", err); 1779 1780 return err; 1781 } 1782 module_init(fman_port_load); 1783 1784 static void __exit fman_port_unload(void) 1785 { 1786 platform_driver_unregister(&fman_port_driver); 1787 } 1788 module_exit(fman_port_unload); 1789 1790 MODULE_LICENSE("Dual BSD/GPL"); 1791 MODULE_DESCRIPTION("Freescale DPAA Frame Manager Port driver"); 1792