1 /* 2 * Copyright 2008-2015 Freescale Semiconductor Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * 16 * ALTERNATIVELY, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL") as published by the Free Software 18 * Foundation, either version 2 of that License or (at your option) any 19 * later version. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 34 35 #include "fman_memac.h" 36 #include "fman.h" 37 38 #include <linux/slab.h> 39 #include <linux/io.h> 40 #include <linux/phy.h> 41 #include <linux/phy_fixed.h> 42 #include <linux/of_mdio.h> 43 44 /* PCS registers */ 45 #define MDIO_SGMII_CR 0x00 46 #define MDIO_SGMII_DEV_ABIL_SGMII 0x04 47 #define MDIO_SGMII_LINK_TMR_L 0x12 48 #define MDIO_SGMII_LINK_TMR_H 0x13 49 #define MDIO_SGMII_IF_MODE 0x14 50 51 /* SGMII Control defines */ 52 #define SGMII_CR_AN_EN 0x1000 53 #define SGMII_CR_RESTART_AN 0x0200 54 #define SGMII_CR_FD 0x0100 55 #define SGMII_CR_SPEED_SEL1_1G 0x0040 56 #define SGMII_CR_DEF_VAL (SGMII_CR_AN_EN | SGMII_CR_FD | \ 57 SGMII_CR_SPEED_SEL1_1G) 58 59 /* SGMII Device Ability for SGMII defines */ 60 #define MDIO_SGMII_DEV_ABIL_SGMII_MODE 0x4001 61 #define MDIO_SGMII_DEV_ABIL_BASEX_MODE 0x01A0 62 63 /* Link timer define */ 64 #define LINK_TMR_L 0xa120 65 #define LINK_TMR_H 0x0007 66 #define LINK_TMR_L_BASEX 0xaf08 67 #define LINK_TMR_H_BASEX 0x002f 68 69 /* SGMII IF Mode defines */ 70 #define IF_MODE_USE_SGMII_AN 0x0002 71 #define IF_MODE_SGMII_EN 0x0001 72 #define IF_MODE_SGMII_SPEED_100M 0x0004 73 #define IF_MODE_SGMII_SPEED_1G 0x0008 74 #define IF_MODE_SGMII_DUPLEX_HALF 0x0010 75 76 /* Num of additional exact match MAC adr regs */ 77 #define MEMAC_NUM_OF_PADDRS 7 78 79 /* Control and Configuration Register (COMMAND_CONFIG) */ 80 #define CMD_CFG_REG_LOWP_RXETY 0x01000000 /* 07 Rx low power indication */ 81 #define CMD_CFG_TX_LOWP_ENA 0x00800000 /* 08 Tx Low Power Idle Enable */ 82 #define CMD_CFG_PFC_MODE 0x00080000 /* 12 Enable PFC */ 83 #define CMD_CFG_NO_LEN_CHK 0x00020000 /* 14 Payload length check disable */ 84 #define CMD_CFG_SW_RESET 0x00001000 /* 19 S/W Reset, self clearing bit */ 85 #define CMD_CFG_TX_PAD_EN 0x00000800 /* 20 Enable Tx padding of frames */ 86 #define CMD_CFG_PAUSE_IGNORE 0x00000100 /* 23 Ignore Pause frame quanta */ 87 #define CMD_CFG_CRC_FWD 0x00000040 /* 25 Terminate/frwd CRC of frames */ 88 #define CMD_CFG_PAD_EN 0x00000020 /* 26 Frame padding removal */ 89 #define CMD_CFG_PROMIS_EN 0x00000010 /* 27 Promiscuous operation enable */ 90 #define CMD_CFG_RX_EN 0x00000002 /* 30 MAC receive path enable */ 91 #define CMD_CFG_TX_EN 0x00000001 /* 31 MAC transmit path enable */ 92 93 /* Transmit FIFO Sections Register (TX_FIFO_SECTIONS) */ 94 #define TX_FIFO_SECTIONS_TX_EMPTY_MASK 0xFFFF0000 95 #define TX_FIFO_SECTIONS_TX_AVAIL_MASK 0x0000FFFF 96 #define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G 0x00400000 97 #define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G 0x00100000 98 #define TX_FIFO_SECTIONS_TX_AVAIL_10G 0x00000019 99 #define TX_FIFO_SECTIONS_TX_AVAIL_1G 0x00000020 100 #define TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G 0x00000060 101 102 #define GET_TX_EMPTY_DEFAULT_VALUE(_val) \ 103 do { \ 104 _val &= ~TX_FIFO_SECTIONS_TX_EMPTY_MASK; \ 105 ((_val == TX_FIFO_SECTIONS_TX_AVAIL_10G) ? \ 106 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G) :\ 107 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G));\ 108 } while (0) 109 110 /* Interface Mode Register (IF_MODE) */ 111 112 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */ 113 #define IF_MODE_10G 0x00000000 /* 30-31 10G interface */ 114 #define IF_MODE_MII 0x00000001 /* 30-31 MII interface */ 115 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */ 116 #define IF_MODE_RGMII 0x00000004 117 #define IF_MODE_RGMII_AUTO 0x00008000 118 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */ 119 #define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */ 120 #define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */ 121 #define IF_MODE_RGMII_SP_MASK 0x00006000 /* Setsp mask bits */ 122 #define IF_MODE_RGMII_FD 0x00001000 /* Full duplex RGMII */ 123 #define IF_MODE_HD 0x00000040 /* Half duplex operation */ 124 125 /* Hash table Control Register (HASHTABLE_CTRL) */ 126 #define HASH_CTRL_MCAST_EN 0x00000100 127 /* 26-31 Hash table address code */ 128 #define HASH_CTRL_ADDR_MASK 0x0000003F 129 /* MAC mcast indication */ 130 #define GROUP_ADDRESS 0x0000010000000000LL 131 #define HASH_TABLE_SIZE 64 /* Hash tbl size */ 132 133 /* Interrupt Mask Register (IMASK) */ 134 #define MEMAC_IMASK_MGI 0x40000000 /* 1 Magic pkt detect indication */ 135 #define MEMAC_IMASK_TSECC_ER 0x20000000 /* 2 Timestamp FIFO ECC error evnt */ 136 #define MEMAC_IMASK_TECC_ER 0x02000000 /* 6 Transmit frame ECC error evnt */ 137 #define MEMAC_IMASK_RECC_ER 0x01000000 /* 7 Receive frame ECC error evnt */ 138 139 #define MEMAC_ALL_ERRS_IMASK \ 140 ((u32)(MEMAC_IMASK_TSECC_ER | \ 141 MEMAC_IMASK_TECC_ER | \ 142 MEMAC_IMASK_RECC_ER | \ 143 MEMAC_IMASK_MGI)) 144 145 #define MEMAC_IEVNT_PCS 0x80000000 /* PCS (XG). Link sync (G) */ 146 #define MEMAC_IEVNT_AN 0x40000000 /* Auto-negotiation */ 147 #define MEMAC_IEVNT_LT 0x20000000 /* Link Training/New page */ 148 #define MEMAC_IEVNT_MGI 0x00004000 /* Magic pkt detection */ 149 #define MEMAC_IEVNT_TS_ECC_ER 0x00002000 /* Timestamp FIFO ECC error*/ 150 #define MEMAC_IEVNT_RX_FIFO_OVFL 0x00001000 /* Rx FIFO overflow */ 151 #define MEMAC_IEVNT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */ 152 #define MEMAC_IEVNT_TX_FIFO_OVFL 0x00000400 /* Tx FIFO overflow */ 153 #define MEMAC_IEVNT_TX_ECC_ER 0x00000200 /* Tx frame ECC error */ 154 #define MEMAC_IEVNT_RX_ECC_ER 0x00000100 /* Rx frame ECC error */ 155 #define MEMAC_IEVNT_LI_FAULT 0x00000080 /* Link Interruption flt */ 156 #define MEMAC_IEVNT_RX_EMPTY 0x00000040 /* Rx FIFO empty */ 157 #define MEMAC_IEVNT_TX_EMPTY 0x00000020 /* Tx FIFO empty */ 158 #define MEMAC_IEVNT_RX_LOWP 0x00000010 /* Low Power Idle */ 159 #define MEMAC_IEVNT_PHY_LOS 0x00000004 /* Phy loss of signal */ 160 #define MEMAC_IEVNT_REM_FAULT 0x00000002 /* Remote fault (XGMII) */ 161 #define MEMAC_IEVNT_LOC_FAULT 0x00000001 /* Local fault (XGMII) */ 162 163 #define DEFAULT_PAUSE_QUANTA 0xf000 164 #define DEFAULT_FRAME_LENGTH 0x600 165 #define DEFAULT_TX_IPG_LENGTH 12 166 167 #define CLXY_PAUSE_QUANTA_CLX_PQNT 0x0000FFFF 168 #define CLXY_PAUSE_QUANTA_CLY_PQNT 0xFFFF0000 169 #define CLXY_PAUSE_THRESH_CLX_QTH 0x0000FFFF 170 #define CLXY_PAUSE_THRESH_CLY_QTH 0xFFFF0000 171 172 struct mac_addr { 173 /* Lower 32 bits of 48-bit MAC address */ 174 u32 mac_addr_l; 175 /* Upper 16 bits of 48-bit MAC address */ 176 u32 mac_addr_u; 177 }; 178 179 /* memory map */ 180 struct memac_regs { 181 u32 res0000[2]; /* General Control and Status */ 182 u32 command_config; /* 0x008 Ctrl and cfg */ 183 struct mac_addr mac_addr0; /* 0x00C-0x010 MAC_ADDR_0...1 */ 184 u32 maxfrm; /* 0x014 Max frame length */ 185 u32 res0018[1]; 186 u32 rx_fifo_sections; /* Receive FIFO configuration reg */ 187 u32 tx_fifo_sections; /* Transmit FIFO configuration reg */ 188 u32 res0024[2]; 189 u32 hashtable_ctrl; /* 0x02C Hash table control */ 190 u32 res0030[4]; 191 u32 ievent; /* 0x040 Interrupt event */ 192 u32 tx_ipg_length; /* 0x044 Transmitter inter-packet-gap */ 193 u32 res0048; 194 u32 imask; /* 0x04C Interrupt mask */ 195 u32 res0050; 196 u32 pause_quanta[4]; /* 0x054 Pause quanta */ 197 u32 pause_thresh[4]; /* 0x064 Pause quanta threshold */ 198 u32 rx_pause_status; /* 0x074 Receive pause status */ 199 u32 res0078[2]; 200 struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS];/* 0x80-0x0B4 mac padr */ 201 u32 lpwake_timer; /* 0x0B8 Low Power Wakeup Timer */ 202 u32 sleep_timer; /* 0x0BC Transmit EEE Low Power Timer */ 203 u32 res00c0[8]; 204 u32 statn_config; /* 0x0E0 Statistics configuration */ 205 u32 res00e4[7]; 206 /* Rx Statistics Counter */ 207 u32 reoct_l; 208 u32 reoct_u; 209 u32 roct_l; 210 u32 roct_u; 211 u32 raln_l; 212 u32 raln_u; 213 u32 rxpf_l; 214 u32 rxpf_u; 215 u32 rfrm_l; 216 u32 rfrm_u; 217 u32 rfcs_l; 218 u32 rfcs_u; 219 u32 rvlan_l; 220 u32 rvlan_u; 221 u32 rerr_l; 222 u32 rerr_u; 223 u32 ruca_l; 224 u32 ruca_u; 225 u32 rmca_l; 226 u32 rmca_u; 227 u32 rbca_l; 228 u32 rbca_u; 229 u32 rdrp_l; 230 u32 rdrp_u; 231 u32 rpkt_l; 232 u32 rpkt_u; 233 u32 rund_l; 234 u32 rund_u; 235 u32 r64_l; 236 u32 r64_u; 237 u32 r127_l; 238 u32 r127_u; 239 u32 r255_l; 240 u32 r255_u; 241 u32 r511_l; 242 u32 r511_u; 243 u32 r1023_l; 244 u32 r1023_u; 245 u32 r1518_l; 246 u32 r1518_u; 247 u32 r1519x_l; 248 u32 r1519x_u; 249 u32 rovr_l; 250 u32 rovr_u; 251 u32 rjbr_l; 252 u32 rjbr_u; 253 u32 rfrg_l; 254 u32 rfrg_u; 255 u32 rcnp_l; 256 u32 rcnp_u; 257 u32 rdrntp_l; 258 u32 rdrntp_u; 259 u32 res01d0[12]; 260 /* Tx Statistics Counter */ 261 u32 teoct_l; 262 u32 teoct_u; 263 u32 toct_l; 264 u32 toct_u; 265 u32 res0210[2]; 266 u32 txpf_l; 267 u32 txpf_u; 268 u32 tfrm_l; 269 u32 tfrm_u; 270 u32 tfcs_l; 271 u32 tfcs_u; 272 u32 tvlan_l; 273 u32 tvlan_u; 274 u32 terr_l; 275 u32 terr_u; 276 u32 tuca_l; 277 u32 tuca_u; 278 u32 tmca_l; 279 u32 tmca_u; 280 u32 tbca_l; 281 u32 tbca_u; 282 u32 res0258[2]; 283 u32 tpkt_l; 284 u32 tpkt_u; 285 u32 tund_l; 286 u32 tund_u; 287 u32 t64_l; 288 u32 t64_u; 289 u32 t127_l; 290 u32 t127_u; 291 u32 t255_l; 292 u32 t255_u; 293 u32 t511_l; 294 u32 t511_u; 295 u32 t1023_l; 296 u32 t1023_u; 297 u32 t1518_l; 298 u32 t1518_u; 299 u32 t1519x_l; 300 u32 t1519x_u; 301 u32 res02a8[6]; 302 u32 tcnp_l; 303 u32 tcnp_u; 304 u32 res02c8[14]; 305 /* Line Interface Control */ 306 u32 if_mode; /* 0x300 Interface Mode Control */ 307 u32 if_status; /* 0x304 Interface Status */ 308 u32 res0308[14]; 309 /* HiGig/2 */ 310 u32 hg_config; /* 0x340 Control and cfg */ 311 u32 res0344[3]; 312 u32 hg_pause_quanta; /* 0x350 Pause quanta */ 313 u32 res0354[3]; 314 u32 hg_pause_thresh; /* 0x360 Pause quanta threshold */ 315 u32 res0364[3]; 316 u32 hgrx_pause_status; /* 0x370 Receive pause status */ 317 u32 hg_fifos_status; /* 0x374 fifos status */ 318 u32 rhm; /* 0x378 rx messages counter */ 319 u32 thm; /* 0x37C tx messages counter */ 320 }; 321 322 struct memac_cfg { 323 bool reset_on_init; 324 bool pause_ignore; 325 bool promiscuous_mode_enable; 326 struct fixed_phy_status *fixed_link; 327 u16 max_frame_length; 328 u16 pause_quanta; 329 u32 tx_ipg_length; 330 }; 331 332 struct fman_mac { 333 /* Pointer to MAC memory mapped registers */ 334 struct memac_regs __iomem *regs; 335 /* MAC address of device */ 336 u64 addr; 337 /* Ethernet physical interface */ 338 phy_interface_t phy_if; 339 u16 max_speed; 340 void *dev_id; /* device cookie used by the exception cbs */ 341 fman_mac_exception_cb *exception_cb; 342 fman_mac_exception_cb *event_cb; 343 /* Pointer to driver's global address hash table */ 344 struct eth_hash_t *multicast_addr_hash; 345 /* Pointer to driver's individual address hash table */ 346 struct eth_hash_t *unicast_addr_hash; 347 u8 mac_id; 348 u32 exceptions; 349 struct memac_cfg *memac_drv_param; 350 void *fm; 351 struct fman_rev_info fm_rev_info; 352 bool basex_if; 353 struct phy_device *pcsphy; 354 bool allmulti_enabled; 355 }; 356 357 static void add_addr_in_paddr(struct memac_regs __iomem *regs, const u8 *adr, 358 u8 paddr_num) 359 { 360 u32 tmp0, tmp1; 361 362 tmp0 = (u32)(adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24); 363 tmp1 = (u32)(adr[4] | adr[5] << 8); 364 365 if (paddr_num == 0) { 366 iowrite32be(tmp0, ®s->mac_addr0.mac_addr_l); 367 iowrite32be(tmp1, ®s->mac_addr0.mac_addr_u); 368 } else { 369 iowrite32be(tmp0, ®s->mac_addr[paddr_num - 1].mac_addr_l); 370 iowrite32be(tmp1, ®s->mac_addr[paddr_num - 1].mac_addr_u); 371 } 372 } 373 374 static int reset(struct memac_regs __iomem *regs) 375 { 376 u32 tmp; 377 int count; 378 379 tmp = ioread32be(®s->command_config); 380 381 tmp |= CMD_CFG_SW_RESET; 382 383 iowrite32be(tmp, ®s->command_config); 384 385 count = 100; 386 do { 387 udelay(1); 388 } while ((ioread32be(®s->command_config) & CMD_CFG_SW_RESET) && 389 --count); 390 391 if (count == 0) 392 return -EBUSY; 393 394 return 0; 395 } 396 397 static void set_exception(struct memac_regs __iomem *regs, u32 val, 398 bool enable) 399 { 400 u32 tmp; 401 402 tmp = ioread32be(®s->imask); 403 if (enable) 404 tmp |= val; 405 else 406 tmp &= ~val; 407 408 iowrite32be(tmp, ®s->imask); 409 } 410 411 static int init(struct memac_regs __iomem *regs, struct memac_cfg *cfg, 412 phy_interface_t phy_if, u16 speed, bool slow_10g_if, 413 u32 exceptions) 414 { 415 u32 tmp; 416 417 /* Config */ 418 tmp = 0; 419 if (cfg->promiscuous_mode_enable) 420 tmp |= CMD_CFG_PROMIS_EN; 421 if (cfg->pause_ignore) 422 tmp |= CMD_CFG_PAUSE_IGNORE; 423 424 /* Payload length check disable */ 425 tmp |= CMD_CFG_NO_LEN_CHK; 426 /* Enable padding of frames in transmit direction */ 427 tmp |= CMD_CFG_TX_PAD_EN; 428 429 tmp |= CMD_CFG_CRC_FWD; 430 431 iowrite32be(tmp, ®s->command_config); 432 433 /* Max Frame Length */ 434 iowrite32be((u32)cfg->max_frame_length, ®s->maxfrm); 435 436 /* Pause Time */ 437 iowrite32be((u32)cfg->pause_quanta, ®s->pause_quanta[0]); 438 iowrite32be((u32)0, ®s->pause_thresh[0]); 439 440 /* IF_MODE */ 441 tmp = 0; 442 switch (phy_if) { 443 case PHY_INTERFACE_MODE_XGMII: 444 tmp |= IF_MODE_10G; 445 break; 446 case PHY_INTERFACE_MODE_MII: 447 tmp |= IF_MODE_MII; 448 break; 449 default: 450 tmp |= IF_MODE_GMII; 451 if (phy_if == PHY_INTERFACE_MODE_RGMII || 452 phy_if == PHY_INTERFACE_MODE_RGMII_ID || 453 phy_if == PHY_INTERFACE_MODE_RGMII_RXID || 454 phy_if == PHY_INTERFACE_MODE_RGMII_TXID) 455 tmp |= IF_MODE_RGMII | IF_MODE_RGMII_AUTO; 456 } 457 iowrite32be(tmp, ®s->if_mode); 458 459 /* TX_FIFO_SECTIONS */ 460 tmp = 0; 461 if (phy_if == PHY_INTERFACE_MODE_XGMII) { 462 if (slow_10g_if) { 463 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G | 464 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G); 465 } else { 466 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_10G | 467 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G); 468 } 469 } else { 470 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_1G | 471 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G); 472 } 473 iowrite32be(tmp, ®s->tx_fifo_sections); 474 475 /* clear all pending events and set-up interrupts */ 476 iowrite32be(0xffffffff, ®s->ievent); 477 set_exception(regs, exceptions, true); 478 479 return 0; 480 } 481 482 static void set_dflts(struct memac_cfg *cfg) 483 { 484 cfg->reset_on_init = false; 485 cfg->promiscuous_mode_enable = false; 486 cfg->pause_ignore = false; 487 cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH; 488 cfg->max_frame_length = DEFAULT_FRAME_LENGTH; 489 cfg->pause_quanta = DEFAULT_PAUSE_QUANTA; 490 } 491 492 static u32 get_mac_addr_hash_code(u64 eth_addr) 493 { 494 u64 mask1, mask2; 495 u32 xor_val = 0; 496 u8 i, j; 497 498 for (i = 0; i < 6; i++) { 499 mask1 = eth_addr & (u64)0x01; 500 eth_addr >>= 1; 501 502 for (j = 0; j < 7; j++) { 503 mask2 = eth_addr & (u64)0x01; 504 mask1 ^= mask2; 505 eth_addr >>= 1; 506 } 507 508 xor_val |= (mask1 << (5 - i)); 509 } 510 511 return xor_val; 512 } 513 514 static void setup_sgmii_internal_phy(struct fman_mac *memac, 515 struct fixed_phy_status *fixed_link) 516 { 517 u16 tmp_reg16; 518 519 if (WARN_ON(!memac->pcsphy)) 520 return; 521 522 /* SGMII mode */ 523 tmp_reg16 = IF_MODE_SGMII_EN; 524 if (!fixed_link) 525 /* AN enable */ 526 tmp_reg16 |= IF_MODE_USE_SGMII_AN; 527 else { 528 switch (fixed_link->speed) { 529 case 10: 530 /* For 10M: IF_MODE[SPEED_10M] = 0 */ 531 break; 532 case 100: 533 tmp_reg16 |= IF_MODE_SGMII_SPEED_100M; 534 break; 535 case 1000: 536 default: 537 tmp_reg16 |= IF_MODE_SGMII_SPEED_1G; 538 break; 539 } 540 if (!fixed_link->duplex) 541 tmp_reg16 |= IF_MODE_SGMII_DUPLEX_HALF; 542 } 543 phy_write(memac->pcsphy, MDIO_SGMII_IF_MODE, tmp_reg16); 544 545 /* Device ability according to SGMII specification */ 546 tmp_reg16 = MDIO_SGMII_DEV_ABIL_SGMII_MODE; 547 phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16); 548 549 /* Adjust link timer for SGMII - 550 * According to Cisco SGMII specification the timer should be 1.6 ms. 551 * The link_timer register is configured in units of the clock. 552 * - When running as 1G SGMII, Serdes clock is 125 MHz, so 553 * unit = 1 / (125*10^6 Hz) = 8 ns. 554 * 1.6 ms in units of 8 ns = 1.6ms / 8ns = 2*10^5 = 0x30d40 555 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so 556 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns. 557 * 1.6 ms in units of 3.2 ns = 1.6ms / 3.2ns = 5*10^5 = 0x7a120. 558 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII, 559 * we always set up here a value of 2.5 SGMII. 560 */ 561 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H); 562 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L); 563 564 if (!fixed_link) 565 /* Restart AN */ 566 tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN; 567 else 568 /* AN disabled */ 569 tmp_reg16 = SGMII_CR_DEF_VAL & ~SGMII_CR_AN_EN; 570 phy_write(memac->pcsphy, 0x0, tmp_reg16); 571 } 572 573 static void setup_sgmii_internal_phy_base_x(struct fman_mac *memac) 574 { 575 u16 tmp_reg16; 576 577 /* AN Device capability */ 578 tmp_reg16 = MDIO_SGMII_DEV_ABIL_BASEX_MODE; 579 phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16); 580 581 /* Adjust link timer for SGMII - 582 * For Serdes 1000BaseX auto-negotiation the timer should be 10 ms. 583 * The link_timer register is configured in units of the clock. 584 * - When running as 1G SGMII, Serdes clock is 125 MHz, so 585 * unit = 1 / (125*10^6 Hz) = 8 ns. 586 * 10 ms in units of 8 ns = 10ms / 8ns = 1250000 = 0x1312d0 587 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so 588 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns. 589 * 10 ms in units of 3.2 ns = 10ms / 3.2ns = 3125000 = 0x2faf08. 590 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII, 591 * we always set up here a value of 2.5 SGMII. 592 */ 593 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H_BASEX); 594 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L_BASEX); 595 596 /* Restart AN */ 597 tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN; 598 phy_write(memac->pcsphy, 0x0, tmp_reg16); 599 } 600 601 static int check_init_parameters(struct fman_mac *memac) 602 { 603 if (!memac->exception_cb) { 604 pr_err("Uninitialized exception handler\n"); 605 return -EINVAL; 606 } 607 if (!memac->event_cb) { 608 pr_warn("Uninitialize event handler\n"); 609 return -EINVAL; 610 } 611 612 return 0; 613 } 614 615 static int get_exception_flag(enum fman_mac_exceptions exception) 616 { 617 u32 bit_mask; 618 619 switch (exception) { 620 case FM_MAC_EX_10G_TX_ECC_ER: 621 bit_mask = MEMAC_IMASK_TECC_ER; 622 break; 623 case FM_MAC_EX_10G_RX_ECC_ER: 624 bit_mask = MEMAC_IMASK_RECC_ER; 625 break; 626 case FM_MAC_EX_TS_FIFO_ECC_ERR: 627 bit_mask = MEMAC_IMASK_TSECC_ER; 628 break; 629 case FM_MAC_EX_MAGIC_PACKET_INDICATION: 630 bit_mask = MEMAC_IMASK_MGI; 631 break; 632 default: 633 bit_mask = 0; 634 break; 635 } 636 637 return bit_mask; 638 } 639 640 static void memac_err_exception(void *handle) 641 { 642 struct fman_mac *memac = (struct fman_mac *)handle; 643 struct memac_regs __iomem *regs = memac->regs; 644 u32 event, imask; 645 646 event = ioread32be(®s->ievent); 647 imask = ioread32be(®s->imask); 648 649 /* Imask include both error and notification/event bits. 650 * Leaving only error bits enabled by imask. 651 * The imask error bits are shifted by 16 bits offset from 652 * their corresponding location in the ievent - hence the >> 16 653 */ 654 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16); 655 656 iowrite32be(event, ®s->ievent); 657 658 if (event & MEMAC_IEVNT_TS_ECC_ER) 659 memac->exception_cb(memac->dev_id, FM_MAC_EX_TS_FIFO_ECC_ERR); 660 if (event & MEMAC_IEVNT_TX_ECC_ER) 661 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_TX_ECC_ER); 662 if (event & MEMAC_IEVNT_RX_ECC_ER) 663 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_RX_ECC_ER); 664 } 665 666 static void memac_exception(void *handle) 667 { 668 struct fman_mac *memac = (struct fman_mac *)handle; 669 struct memac_regs __iomem *regs = memac->regs; 670 u32 event, imask; 671 672 event = ioread32be(®s->ievent); 673 imask = ioread32be(®s->imask); 674 675 /* Imask include both error and notification/event bits. 676 * Leaving only error bits enabled by imask. 677 * The imask error bits are shifted by 16 bits offset from 678 * their corresponding location in the ievent - hence the >> 16 679 */ 680 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16); 681 682 iowrite32be(event, ®s->ievent); 683 684 if (event & MEMAC_IEVNT_MGI) 685 memac->exception_cb(memac->dev_id, 686 FM_MAC_EX_MAGIC_PACKET_INDICATION); 687 } 688 689 static void free_init_resources(struct fman_mac *memac) 690 { 691 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 692 FMAN_INTR_TYPE_ERR); 693 694 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 695 FMAN_INTR_TYPE_NORMAL); 696 697 /* release the driver's group hash table */ 698 free_hash_table(memac->multicast_addr_hash); 699 memac->multicast_addr_hash = NULL; 700 701 /* release the driver's individual hash table */ 702 free_hash_table(memac->unicast_addr_hash); 703 memac->unicast_addr_hash = NULL; 704 } 705 706 static bool is_init_done(struct memac_cfg *memac_drv_params) 707 { 708 /* Checks if mEMAC driver parameters were initialized */ 709 if (!memac_drv_params) 710 return true; 711 712 return false; 713 } 714 715 int memac_enable(struct fman_mac *memac, enum comm_mode mode) 716 { 717 struct memac_regs __iomem *regs = memac->regs; 718 u32 tmp; 719 720 if (!is_init_done(memac->memac_drv_param)) 721 return -EINVAL; 722 723 tmp = ioread32be(®s->command_config); 724 if (mode & COMM_MODE_RX) 725 tmp |= CMD_CFG_RX_EN; 726 if (mode & COMM_MODE_TX) 727 tmp |= CMD_CFG_TX_EN; 728 729 iowrite32be(tmp, ®s->command_config); 730 731 return 0; 732 } 733 734 int memac_disable(struct fman_mac *memac, enum comm_mode mode) 735 { 736 struct memac_regs __iomem *regs = memac->regs; 737 u32 tmp; 738 739 if (!is_init_done(memac->memac_drv_param)) 740 return -EINVAL; 741 742 tmp = ioread32be(®s->command_config); 743 if (mode & COMM_MODE_RX) 744 tmp &= ~CMD_CFG_RX_EN; 745 if (mode & COMM_MODE_TX) 746 tmp &= ~CMD_CFG_TX_EN; 747 748 iowrite32be(tmp, ®s->command_config); 749 750 return 0; 751 } 752 753 int memac_set_promiscuous(struct fman_mac *memac, bool new_val) 754 { 755 struct memac_regs __iomem *regs = memac->regs; 756 u32 tmp; 757 758 if (!is_init_done(memac->memac_drv_param)) 759 return -EINVAL; 760 761 tmp = ioread32be(®s->command_config); 762 if (new_val) 763 tmp |= CMD_CFG_PROMIS_EN; 764 else 765 tmp &= ~CMD_CFG_PROMIS_EN; 766 767 iowrite32be(tmp, ®s->command_config); 768 769 return 0; 770 } 771 772 int memac_adjust_link(struct fman_mac *memac, u16 speed) 773 { 774 struct memac_regs __iomem *regs = memac->regs; 775 u32 tmp; 776 777 if (!is_init_done(memac->memac_drv_param)) 778 return -EINVAL; 779 780 tmp = ioread32be(®s->if_mode); 781 782 /* Set full duplex */ 783 tmp &= ~IF_MODE_HD; 784 785 if (phy_interface_mode_is_rgmii(memac->phy_if)) { 786 /* Configure RGMII in manual mode */ 787 tmp &= ~IF_MODE_RGMII_AUTO; 788 tmp &= ~IF_MODE_RGMII_SP_MASK; 789 /* Full duplex */ 790 tmp |= IF_MODE_RGMII_FD; 791 792 switch (speed) { 793 case SPEED_1000: 794 tmp |= IF_MODE_RGMII_1000; 795 break; 796 case SPEED_100: 797 tmp |= IF_MODE_RGMII_100; 798 break; 799 case SPEED_10: 800 tmp |= IF_MODE_RGMII_10; 801 break; 802 default: 803 break; 804 } 805 } 806 807 iowrite32be(tmp, ®s->if_mode); 808 809 return 0; 810 } 811 812 int memac_cfg_max_frame_len(struct fman_mac *memac, u16 new_val) 813 { 814 if (is_init_done(memac->memac_drv_param)) 815 return -EINVAL; 816 817 memac->memac_drv_param->max_frame_length = new_val; 818 819 return 0; 820 } 821 822 int memac_cfg_reset_on_init(struct fman_mac *memac, bool enable) 823 { 824 if (is_init_done(memac->memac_drv_param)) 825 return -EINVAL; 826 827 memac->memac_drv_param->reset_on_init = enable; 828 829 return 0; 830 } 831 832 int memac_cfg_fixed_link(struct fman_mac *memac, 833 struct fixed_phy_status *fixed_link) 834 { 835 if (is_init_done(memac->memac_drv_param)) 836 return -EINVAL; 837 838 memac->memac_drv_param->fixed_link = fixed_link; 839 840 return 0; 841 } 842 843 int memac_set_tx_pause_frames(struct fman_mac *memac, u8 priority, 844 u16 pause_time, u16 thresh_time) 845 { 846 struct memac_regs __iomem *regs = memac->regs; 847 u32 tmp; 848 849 if (!is_init_done(memac->memac_drv_param)) 850 return -EINVAL; 851 852 tmp = ioread32be(®s->tx_fifo_sections); 853 854 GET_TX_EMPTY_DEFAULT_VALUE(tmp); 855 iowrite32be(tmp, ®s->tx_fifo_sections); 856 857 tmp = ioread32be(®s->command_config); 858 tmp &= ~CMD_CFG_PFC_MODE; 859 860 iowrite32be(tmp, ®s->command_config); 861 862 tmp = ioread32be(®s->pause_quanta[priority / 2]); 863 if (priority % 2) 864 tmp &= CLXY_PAUSE_QUANTA_CLX_PQNT; 865 else 866 tmp &= CLXY_PAUSE_QUANTA_CLY_PQNT; 867 tmp |= ((u32)pause_time << (16 * (priority % 2))); 868 iowrite32be(tmp, ®s->pause_quanta[priority / 2]); 869 870 tmp = ioread32be(®s->pause_thresh[priority / 2]); 871 if (priority % 2) 872 tmp &= CLXY_PAUSE_THRESH_CLX_QTH; 873 else 874 tmp &= CLXY_PAUSE_THRESH_CLY_QTH; 875 tmp |= ((u32)thresh_time << (16 * (priority % 2))); 876 iowrite32be(tmp, ®s->pause_thresh[priority / 2]); 877 878 return 0; 879 } 880 881 int memac_accept_rx_pause_frames(struct fman_mac *memac, bool en) 882 { 883 struct memac_regs __iomem *regs = memac->regs; 884 u32 tmp; 885 886 if (!is_init_done(memac->memac_drv_param)) 887 return -EINVAL; 888 889 tmp = ioread32be(®s->command_config); 890 if (en) 891 tmp &= ~CMD_CFG_PAUSE_IGNORE; 892 else 893 tmp |= CMD_CFG_PAUSE_IGNORE; 894 895 iowrite32be(tmp, ®s->command_config); 896 897 return 0; 898 } 899 900 int memac_modify_mac_address(struct fman_mac *memac, const enet_addr_t *enet_addr) 901 { 902 if (!is_init_done(memac->memac_drv_param)) 903 return -EINVAL; 904 905 add_addr_in_paddr(memac->regs, (const u8 *)(*enet_addr), 0); 906 907 return 0; 908 } 909 910 int memac_add_hash_mac_address(struct fman_mac *memac, enet_addr_t *eth_addr) 911 { 912 struct memac_regs __iomem *regs = memac->regs; 913 struct eth_hash_entry *hash_entry; 914 u32 hash; 915 u64 addr; 916 917 if (!is_init_done(memac->memac_drv_param)) 918 return -EINVAL; 919 920 addr = ENET_ADDR_TO_UINT64(*eth_addr); 921 922 if (!(addr & GROUP_ADDRESS)) { 923 /* Unicast addresses not supported in hash */ 924 pr_err("Unicast Address\n"); 925 return -EINVAL; 926 } 927 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK; 928 929 /* Create element to be added to the driver hash table */ 930 hash_entry = kmalloc(sizeof(*hash_entry), GFP_ATOMIC); 931 if (!hash_entry) 932 return -ENOMEM; 933 hash_entry->addr = addr; 934 INIT_LIST_HEAD(&hash_entry->node); 935 936 list_add_tail(&hash_entry->node, 937 &memac->multicast_addr_hash->lsts[hash]); 938 iowrite32be(hash | HASH_CTRL_MCAST_EN, ®s->hashtable_ctrl); 939 940 return 0; 941 } 942 943 int memac_set_allmulti(struct fman_mac *memac, bool enable) 944 { 945 u32 entry; 946 struct memac_regs __iomem *regs = memac->regs; 947 948 if (!is_init_done(memac->memac_drv_param)) 949 return -EINVAL; 950 951 if (enable) { 952 for (entry = 0; entry < HASH_TABLE_SIZE; entry++) 953 iowrite32be(entry | HASH_CTRL_MCAST_EN, 954 ®s->hashtable_ctrl); 955 } else { 956 for (entry = 0; entry < HASH_TABLE_SIZE; entry++) 957 iowrite32be(entry & ~HASH_CTRL_MCAST_EN, 958 ®s->hashtable_ctrl); 959 } 960 961 memac->allmulti_enabled = enable; 962 963 return 0; 964 } 965 966 int memac_set_tstamp(struct fman_mac *memac, bool enable) 967 { 968 return 0; /* Always enabled. */ 969 } 970 971 int memac_del_hash_mac_address(struct fman_mac *memac, enet_addr_t *eth_addr) 972 { 973 struct memac_regs __iomem *regs = memac->regs; 974 struct eth_hash_entry *hash_entry = NULL; 975 struct list_head *pos; 976 u32 hash; 977 u64 addr; 978 979 if (!is_init_done(memac->memac_drv_param)) 980 return -EINVAL; 981 982 addr = ENET_ADDR_TO_UINT64(*eth_addr); 983 984 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK; 985 986 list_for_each(pos, &memac->multicast_addr_hash->lsts[hash]) { 987 hash_entry = ETH_HASH_ENTRY_OBJ(pos); 988 if (hash_entry && hash_entry->addr == addr) { 989 list_del_init(&hash_entry->node); 990 kfree(hash_entry); 991 break; 992 } 993 } 994 995 if (!memac->allmulti_enabled) { 996 if (list_empty(&memac->multicast_addr_hash->lsts[hash])) 997 iowrite32be(hash & ~HASH_CTRL_MCAST_EN, 998 ®s->hashtable_ctrl); 999 } 1000 1001 return 0; 1002 } 1003 1004 int memac_set_exception(struct fman_mac *memac, 1005 enum fman_mac_exceptions exception, bool enable) 1006 { 1007 u32 bit_mask = 0; 1008 1009 if (!is_init_done(memac->memac_drv_param)) 1010 return -EINVAL; 1011 1012 bit_mask = get_exception_flag(exception); 1013 if (bit_mask) { 1014 if (enable) 1015 memac->exceptions |= bit_mask; 1016 else 1017 memac->exceptions &= ~bit_mask; 1018 } else { 1019 pr_err("Undefined exception\n"); 1020 return -EINVAL; 1021 } 1022 set_exception(memac->regs, bit_mask, enable); 1023 1024 return 0; 1025 } 1026 1027 int memac_init(struct fman_mac *memac) 1028 { 1029 struct memac_cfg *memac_drv_param; 1030 u8 i; 1031 enet_addr_t eth_addr; 1032 bool slow_10g_if = false; 1033 struct fixed_phy_status *fixed_link; 1034 int err; 1035 u32 reg32 = 0; 1036 1037 if (is_init_done(memac->memac_drv_param)) 1038 return -EINVAL; 1039 1040 err = check_init_parameters(memac); 1041 if (err) 1042 return err; 1043 1044 memac_drv_param = memac->memac_drv_param; 1045 1046 if (memac->fm_rev_info.major == 6 && memac->fm_rev_info.minor == 4) 1047 slow_10g_if = true; 1048 1049 /* First, reset the MAC if desired. */ 1050 if (memac_drv_param->reset_on_init) { 1051 err = reset(memac->regs); 1052 if (err) { 1053 pr_err("mEMAC reset failed\n"); 1054 return err; 1055 } 1056 } 1057 1058 /* MAC Address */ 1059 if (memac->addr != 0) { 1060 MAKE_ENET_ADDR_FROM_UINT64(memac->addr, eth_addr); 1061 add_addr_in_paddr(memac->regs, (const u8 *)eth_addr, 0); 1062 } 1063 1064 fixed_link = memac_drv_param->fixed_link; 1065 1066 init(memac->regs, memac->memac_drv_param, memac->phy_if, 1067 memac->max_speed, slow_10g_if, memac->exceptions); 1068 1069 /* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 errata workaround 1070 * Exists only in FMan 6.0 and 6.3. 1071 */ 1072 if ((memac->fm_rev_info.major == 6) && 1073 ((memac->fm_rev_info.minor == 0) || 1074 (memac->fm_rev_info.minor == 3))) { 1075 /* MAC strips CRC from received frames - this workaround 1076 * should decrease the likelihood of bug appearance 1077 */ 1078 reg32 = ioread32be(&memac->regs->command_config); 1079 reg32 &= ~CMD_CFG_CRC_FWD; 1080 iowrite32be(reg32, &memac->regs->command_config); 1081 } 1082 1083 if (memac->phy_if == PHY_INTERFACE_MODE_SGMII) { 1084 /* Configure internal SGMII PHY */ 1085 if (memac->basex_if) 1086 setup_sgmii_internal_phy_base_x(memac); 1087 else 1088 setup_sgmii_internal_phy(memac, fixed_link); 1089 } else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII) { 1090 /* Configure 4 internal SGMII PHYs */ 1091 for (i = 0; i < 4; i++) { 1092 u8 qsmgii_phy_addr, phy_addr; 1093 /* QSGMII PHY address occupies 3 upper bits of 5-bit 1094 * phy_address; the lower 2 bits are used to extend 1095 * register address space and access each one of 4 1096 * ports inside QSGMII. 1097 */ 1098 phy_addr = memac->pcsphy->mdio.addr; 1099 qsmgii_phy_addr = (u8)((phy_addr << 2) | i); 1100 memac->pcsphy->mdio.addr = qsmgii_phy_addr; 1101 if (memac->basex_if) 1102 setup_sgmii_internal_phy_base_x(memac); 1103 else 1104 setup_sgmii_internal_phy(memac, fixed_link); 1105 1106 memac->pcsphy->mdio.addr = phy_addr; 1107 } 1108 } 1109 1110 /* Max Frame Length */ 1111 err = fman_set_mac_max_frame(memac->fm, memac->mac_id, 1112 memac_drv_param->max_frame_length); 1113 if (err) { 1114 pr_err("settings Mac max frame length is FAILED\n"); 1115 return err; 1116 } 1117 1118 memac->multicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE); 1119 if (!memac->multicast_addr_hash) { 1120 free_init_resources(memac); 1121 pr_err("allocation hash table is FAILED\n"); 1122 return -ENOMEM; 1123 } 1124 1125 memac->unicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE); 1126 if (!memac->unicast_addr_hash) { 1127 free_init_resources(memac); 1128 pr_err("allocation hash table is FAILED\n"); 1129 return -ENOMEM; 1130 } 1131 1132 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 1133 FMAN_INTR_TYPE_ERR, memac_err_exception, memac); 1134 1135 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 1136 FMAN_INTR_TYPE_NORMAL, memac_exception, memac); 1137 1138 kfree(memac_drv_param); 1139 memac->memac_drv_param = NULL; 1140 1141 return 0; 1142 } 1143 1144 int memac_free(struct fman_mac *memac) 1145 { 1146 free_init_resources(memac); 1147 1148 if (memac->pcsphy) 1149 put_device(&memac->pcsphy->mdio.dev); 1150 1151 kfree(memac->memac_drv_param); 1152 kfree(memac); 1153 1154 return 0; 1155 } 1156 1157 struct fman_mac *memac_config(struct fman_mac_params *params) 1158 { 1159 struct fman_mac *memac; 1160 struct memac_cfg *memac_drv_param; 1161 void __iomem *base_addr; 1162 1163 base_addr = params->base_addr; 1164 /* allocate memory for the m_emac data structure */ 1165 memac = kzalloc(sizeof(*memac), GFP_KERNEL); 1166 if (!memac) 1167 return NULL; 1168 1169 /* allocate memory for the m_emac driver parameters data structure */ 1170 memac_drv_param = kzalloc(sizeof(*memac_drv_param), GFP_KERNEL); 1171 if (!memac_drv_param) { 1172 memac_free(memac); 1173 return NULL; 1174 } 1175 1176 /* Plant parameter structure pointer */ 1177 memac->memac_drv_param = memac_drv_param; 1178 1179 set_dflts(memac_drv_param); 1180 1181 memac->addr = ENET_ADDR_TO_UINT64(params->addr); 1182 1183 memac->regs = base_addr; 1184 memac->max_speed = params->max_speed; 1185 memac->phy_if = params->phy_if; 1186 memac->mac_id = params->mac_id; 1187 memac->exceptions = (MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER | 1188 MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI); 1189 memac->exception_cb = params->exception_cb; 1190 memac->event_cb = params->event_cb; 1191 memac->dev_id = params->dev_id; 1192 memac->fm = params->fm; 1193 memac->basex_if = params->basex_if; 1194 1195 /* Save FMan revision */ 1196 fman_get_revision(memac->fm, &memac->fm_rev_info); 1197 1198 if (memac->phy_if == PHY_INTERFACE_MODE_SGMII || 1199 memac->phy_if == PHY_INTERFACE_MODE_QSGMII) { 1200 if (!params->internal_phy_node) { 1201 pr_err("PCS PHY node is not available\n"); 1202 memac_free(memac); 1203 return NULL; 1204 } 1205 1206 memac->pcsphy = of_phy_find_device(params->internal_phy_node); 1207 if (!memac->pcsphy) { 1208 pr_err("of_phy_find_device (PCS PHY) failed\n"); 1209 memac_free(memac); 1210 return NULL; 1211 } 1212 } 1213 1214 return memac; 1215 } 1216