1 /* 2 * Copyright 2008-2015 Freescale Semiconductor Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * 16 * ALTERNATIVELY, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL") as published by the Free Software 18 * Foundation, either version 2 of that License or (at your option) any 19 * later version. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 34 35 #include "fman_memac.h" 36 #include "fman.h" 37 38 #include <linux/slab.h> 39 #include <linux/io.h> 40 #include <linux/phy.h> 41 #include <linux/of_mdio.h> 42 43 /* PCS registers */ 44 #define MDIO_SGMII_CR 0x00 45 #define MDIO_SGMII_DEV_ABIL_SGMII 0x04 46 #define MDIO_SGMII_LINK_TMR_L 0x12 47 #define MDIO_SGMII_LINK_TMR_H 0x13 48 #define MDIO_SGMII_IF_MODE 0x14 49 50 /* SGMII Control defines */ 51 #define SGMII_CR_AN_EN 0x1000 52 #define SGMII_CR_RESTART_AN 0x0200 53 #define SGMII_CR_FD 0x0100 54 #define SGMII_CR_SPEED_SEL1_1G 0x0040 55 #define SGMII_CR_DEF_VAL (SGMII_CR_AN_EN | SGMII_CR_FD | \ 56 SGMII_CR_SPEED_SEL1_1G) 57 58 /* SGMII Device Ability for SGMII defines */ 59 #define MDIO_SGMII_DEV_ABIL_SGMII_MODE 0x4001 60 #define MDIO_SGMII_DEV_ABIL_BASEX_MODE 0x01A0 61 62 /* Link timer define */ 63 #define LINK_TMR_L 0xa120 64 #define LINK_TMR_H 0x0007 65 #define LINK_TMR_L_BASEX 0xaf08 66 #define LINK_TMR_H_BASEX 0x002f 67 68 /* SGMII IF Mode defines */ 69 #define IF_MODE_USE_SGMII_AN 0x0002 70 #define IF_MODE_SGMII_EN 0x0001 71 #define IF_MODE_SGMII_SPEED_100M 0x0004 72 #define IF_MODE_SGMII_SPEED_1G 0x0008 73 #define IF_MODE_SGMII_DUPLEX_HALF 0x0010 74 75 /* Num of additional exact match MAC adr regs */ 76 #define MEMAC_NUM_OF_PADDRS 7 77 78 /* Control and Configuration Register (COMMAND_CONFIG) */ 79 #define CMD_CFG_REG_LOWP_RXETY 0x01000000 /* 07 Rx low power indication */ 80 #define CMD_CFG_TX_LOWP_ENA 0x00800000 /* 08 Tx Low Power Idle Enable */ 81 #define CMD_CFG_PFC_MODE 0x00080000 /* 12 Enable PFC */ 82 #define CMD_CFG_NO_LEN_CHK 0x00020000 /* 14 Payload length check disable */ 83 #define CMD_CFG_SW_RESET 0x00001000 /* 19 S/W Reset, self clearing bit */ 84 #define CMD_CFG_TX_PAD_EN 0x00000800 /* 20 Enable Tx padding of frames */ 85 #define CMD_CFG_PAUSE_IGNORE 0x00000100 /* 23 Ignore Pause frame quanta */ 86 #define CMD_CFG_CRC_FWD 0x00000040 /* 25 Terminate/frwd CRC of frames */ 87 #define CMD_CFG_PAD_EN 0x00000020 /* 26 Frame padding removal */ 88 #define CMD_CFG_PROMIS_EN 0x00000010 /* 27 Promiscuous operation enable */ 89 #define CMD_CFG_RX_EN 0x00000002 /* 30 MAC receive path enable */ 90 #define CMD_CFG_TX_EN 0x00000001 /* 31 MAC transmit path enable */ 91 92 /* Transmit FIFO Sections Register (TX_FIFO_SECTIONS) */ 93 #define TX_FIFO_SECTIONS_TX_EMPTY_MASK 0xFFFF0000 94 #define TX_FIFO_SECTIONS_TX_AVAIL_MASK 0x0000FFFF 95 #define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G 0x00400000 96 #define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G 0x00100000 97 #define TX_FIFO_SECTIONS_TX_AVAIL_10G 0x00000019 98 #define TX_FIFO_SECTIONS_TX_AVAIL_1G 0x00000020 99 #define TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G 0x00000060 100 101 #define GET_TX_EMPTY_DEFAULT_VALUE(_val) \ 102 do { \ 103 _val &= ~TX_FIFO_SECTIONS_TX_EMPTY_MASK; \ 104 ((_val == TX_FIFO_SECTIONS_TX_AVAIL_10G) ? \ 105 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G) :\ 106 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G));\ 107 } while (0) 108 109 /* Interface Mode Register (IF_MODE) */ 110 111 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */ 112 #define IF_MODE_XGMII 0x00000000 /* 30-31 XGMII (10G) interface */ 113 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */ 114 #define IF_MODE_RGMII 0x00000004 115 #define IF_MODE_RGMII_AUTO 0x00008000 116 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */ 117 #define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */ 118 #define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */ 119 #define IF_MODE_RGMII_SP_MASK 0x00006000 /* Setsp mask bits */ 120 #define IF_MODE_RGMII_FD 0x00001000 /* Full duplex RGMII */ 121 #define IF_MODE_HD 0x00000040 /* Half duplex operation */ 122 123 /* Hash table Control Register (HASHTABLE_CTRL) */ 124 #define HASH_CTRL_MCAST_EN 0x00000100 125 /* 26-31 Hash table address code */ 126 #define HASH_CTRL_ADDR_MASK 0x0000003F 127 /* MAC mcast indication */ 128 #define GROUP_ADDRESS 0x0000010000000000LL 129 #define HASH_TABLE_SIZE 64 /* Hash tbl size */ 130 131 /* Interrupt Mask Register (IMASK) */ 132 #define MEMAC_IMASK_MGI 0x40000000 /* 1 Magic pkt detect indication */ 133 #define MEMAC_IMASK_TSECC_ER 0x20000000 /* 2 Timestamp FIFO ECC error evnt */ 134 #define MEMAC_IMASK_TECC_ER 0x02000000 /* 6 Transmit frame ECC error evnt */ 135 #define MEMAC_IMASK_RECC_ER 0x01000000 /* 7 Receive frame ECC error evnt */ 136 137 #define MEMAC_ALL_ERRS_IMASK \ 138 ((u32)(MEMAC_IMASK_TSECC_ER | \ 139 MEMAC_IMASK_TECC_ER | \ 140 MEMAC_IMASK_RECC_ER | \ 141 MEMAC_IMASK_MGI)) 142 143 #define MEMAC_IEVNT_PCS 0x80000000 /* PCS (XG). Link sync (G) */ 144 #define MEMAC_IEVNT_AN 0x40000000 /* Auto-negotiation */ 145 #define MEMAC_IEVNT_LT 0x20000000 /* Link Training/New page */ 146 #define MEMAC_IEVNT_MGI 0x00004000 /* Magic pkt detection */ 147 #define MEMAC_IEVNT_TS_ECC_ER 0x00002000 /* Timestamp FIFO ECC error*/ 148 #define MEMAC_IEVNT_RX_FIFO_OVFL 0x00001000 /* Rx FIFO overflow */ 149 #define MEMAC_IEVNT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */ 150 #define MEMAC_IEVNT_TX_FIFO_OVFL 0x00000400 /* Tx FIFO overflow */ 151 #define MEMAC_IEVNT_TX_ECC_ER 0x00000200 /* Tx frame ECC error */ 152 #define MEMAC_IEVNT_RX_ECC_ER 0x00000100 /* Rx frame ECC error */ 153 #define MEMAC_IEVNT_LI_FAULT 0x00000080 /* Link Interruption flt */ 154 #define MEMAC_IEVNT_RX_EMPTY 0x00000040 /* Rx FIFO empty */ 155 #define MEMAC_IEVNT_TX_EMPTY 0x00000020 /* Tx FIFO empty */ 156 #define MEMAC_IEVNT_RX_LOWP 0x00000010 /* Low Power Idle */ 157 #define MEMAC_IEVNT_PHY_LOS 0x00000004 /* Phy loss of signal */ 158 #define MEMAC_IEVNT_REM_FAULT 0x00000002 /* Remote fault (XGMII) */ 159 #define MEMAC_IEVNT_LOC_FAULT 0x00000001 /* Local fault (XGMII) */ 160 161 #define DEFAULT_PAUSE_QUANTA 0xf000 162 #define DEFAULT_FRAME_LENGTH 0x600 163 #define DEFAULT_TX_IPG_LENGTH 12 164 165 #define CLXY_PAUSE_QUANTA_CLX_PQNT 0x0000FFFF 166 #define CLXY_PAUSE_QUANTA_CLY_PQNT 0xFFFF0000 167 #define CLXY_PAUSE_THRESH_CLX_QTH 0x0000FFFF 168 #define CLXY_PAUSE_THRESH_CLY_QTH 0xFFFF0000 169 170 struct mac_addr { 171 /* Lower 32 bits of 48-bit MAC address */ 172 u32 mac_addr_l; 173 /* Upper 16 bits of 48-bit MAC address */ 174 u32 mac_addr_u; 175 }; 176 177 /* memory map */ 178 struct memac_regs { 179 u32 res0000[2]; /* General Control and Status */ 180 u32 command_config; /* 0x008 Ctrl and cfg */ 181 struct mac_addr mac_addr0; /* 0x00C-0x010 MAC_ADDR_0...1 */ 182 u32 maxfrm; /* 0x014 Max frame length */ 183 u32 res0018[1]; 184 u32 rx_fifo_sections; /* Receive FIFO configuration reg */ 185 u32 tx_fifo_sections; /* Transmit FIFO configuration reg */ 186 u32 res0024[2]; 187 u32 hashtable_ctrl; /* 0x02C Hash table control */ 188 u32 res0030[4]; 189 u32 ievent; /* 0x040 Interrupt event */ 190 u32 tx_ipg_length; /* 0x044 Transmitter inter-packet-gap */ 191 u32 res0048; 192 u32 imask; /* 0x04C Interrupt mask */ 193 u32 res0050; 194 u32 pause_quanta[4]; /* 0x054 Pause quanta */ 195 u32 pause_thresh[4]; /* 0x064 Pause quanta threshold */ 196 u32 rx_pause_status; /* 0x074 Receive pause status */ 197 u32 res0078[2]; 198 struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS];/* 0x80-0x0B4 mac padr */ 199 u32 lpwake_timer; /* 0x0B8 Low Power Wakeup Timer */ 200 u32 sleep_timer; /* 0x0BC Transmit EEE Low Power Timer */ 201 u32 res00c0[8]; 202 u32 statn_config; /* 0x0E0 Statistics configuration */ 203 u32 res00e4[7]; 204 /* Rx Statistics Counter */ 205 u32 reoct_l; 206 u32 reoct_u; 207 u32 roct_l; 208 u32 roct_u; 209 u32 raln_l; 210 u32 raln_u; 211 u32 rxpf_l; 212 u32 rxpf_u; 213 u32 rfrm_l; 214 u32 rfrm_u; 215 u32 rfcs_l; 216 u32 rfcs_u; 217 u32 rvlan_l; 218 u32 rvlan_u; 219 u32 rerr_l; 220 u32 rerr_u; 221 u32 ruca_l; 222 u32 ruca_u; 223 u32 rmca_l; 224 u32 rmca_u; 225 u32 rbca_l; 226 u32 rbca_u; 227 u32 rdrp_l; 228 u32 rdrp_u; 229 u32 rpkt_l; 230 u32 rpkt_u; 231 u32 rund_l; 232 u32 rund_u; 233 u32 r64_l; 234 u32 r64_u; 235 u32 r127_l; 236 u32 r127_u; 237 u32 r255_l; 238 u32 r255_u; 239 u32 r511_l; 240 u32 r511_u; 241 u32 r1023_l; 242 u32 r1023_u; 243 u32 r1518_l; 244 u32 r1518_u; 245 u32 r1519x_l; 246 u32 r1519x_u; 247 u32 rovr_l; 248 u32 rovr_u; 249 u32 rjbr_l; 250 u32 rjbr_u; 251 u32 rfrg_l; 252 u32 rfrg_u; 253 u32 rcnp_l; 254 u32 rcnp_u; 255 u32 rdrntp_l; 256 u32 rdrntp_u; 257 u32 res01d0[12]; 258 /* Tx Statistics Counter */ 259 u32 teoct_l; 260 u32 teoct_u; 261 u32 toct_l; 262 u32 toct_u; 263 u32 res0210[2]; 264 u32 txpf_l; 265 u32 txpf_u; 266 u32 tfrm_l; 267 u32 tfrm_u; 268 u32 tfcs_l; 269 u32 tfcs_u; 270 u32 tvlan_l; 271 u32 tvlan_u; 272 u32 terr_l; 273 u32 terr_u; 274 u32 tuca_l; 275 u32 tuca_u; 276 u32 tmca_l; 277 u32 tmca_u; 278 u32 tbca_l; 279 u32 tbca_u; 280 u32 res0258[2]; 281 u32 tpkt_l; 282 u32 tpkt_u; 283 u32 tund_l; 284 u32 tund_u; 285 u32 t64_l; 286 u32 t64_u; 287 u32 t127_l; 288 u32 t127_u; 289 u32 t255_l; 290 u32 t255_u; 291 u32 t511_l; 292 u32 t511_u; 293 u32 t1023_l; 294 u32 t1023_u; 295 u32 t1518_l; 296 u32 t1518_u; 297 u32 t1519x_l; 298 u32 t1519x_u; 299 u32 res02a8[6]; 300 u32 tcnp_l; 301 u32 tcnp_u; 302 u32 res02c8[14]; 303 /* Line Interface Control */ 304 u32 if_mode; /* 0x300 Interface Mode Control */ 305 u32 if_status; /* 0x304 Interface Status */ 306 u32 res0308[14]; 307 /* HiGig/2 */ 308 u32 hg_config; /* 0x340 Control and cfg */ 309 u32 res0344[3]; 310 u32 hg_pause_quanta; /* 0x350 Pause quanta */ 311 u32 res0354[3]; 312 u32 hg_pause_thresh; /* 0x360 Pause quanta threshold */ 313 u32 res0364[3]; 314 u32 hgrx_pause_status; /* 0x370 Receive pause status */ 315 u32 hg_fifos_status; /* 0x374 fifos status */ 316 u32 rhm; /* 0x378 rx messages counter */ 317 u32 thm; /* 0x37C tx messages counter */ 318 }; 319 320 struct memac_cfg { 321 bool reset_on_init; 322 bool pause_ignore; 323 bool promiscuous_mode_enable; 324 struct fixed_phy_status *fixed_link; 325 u16 max_frame_length; 326 u16 pause_quanta; 327 u32 tx_ipg_length; 328 }; 329 330 struct fman_mac { 331 /* Pointer to MAC memory mapped registers */ 332 struct memac_regs __iomem *regs; 333 /* MAC address of device */ 334 u64 addr; 335 /* Ethernet physical interface */ 336 phy_interface_t phy_if; 337 u16 max_speed; 338 void *dev_id; /* device cookie used by the exception cbs */ 339 fman_mac_exception_cb *exception_cb; 340 fman_mac_exception_cb *event_cb; 341 /* Pointer to driver's global address hash table */ 342 struct eth_hash_t *multicast_addr_hash; 343 /* Pointer to driver's individual address hash table */ 344 struct eth_hash_t *unicast_addr_hash; 345 u8 mac_id; 346 u32 exceptions; 347 struct memac_cfg *memac_drv_param; 348 void *fm; 349 struct fman_rev_info fm_rev_info; 350 bool basex_if; 351 struct phy_device *pcsphy; 352 }; 353 354 static void add_addr_in_paddr(struct memac_regs __iomem *regs, u8 *adr, 355 u8 paddr_num) 356 { 357 u32 tmp0, tmp1; 358 359 tmp0 = (u32)(adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24); 360 tmp1 = (u32)(adr[4] | adr[5] << 8); 361 362 if (paddr_num == 0) { 363 iowrite32be(tmp0, ®s->mac_addr0.mac_addr_l); 364 iowrite32be(tmp1, ®s->mac_addr0.mac_addr_u); 365 } else { 366 iowrite32be(tmp0, ®s->mac_addr[paddr_num - 1].mac_addr_l); 367 iowrite32be(tmp1, ®s->mac_addr[paddr_num - 1].mac_addr_u); 368 } 369 } 370 371 static int reset(struct memac_regs __iomem *regs) 372 { 373 u32 tmp; 374 int count; 375 376 tmp = ioread32be(®s->command_config); 377 378 tmp |= CMD_CFG_SW_RESET; 379 380 iowrite32be(tmp, ®s->command_config); 381 382 count = 100; 383 do { 384 udelay(1); 385 } while ((ioread32be(®s->command_config) & CMD_CFG_SW_RESET) && 386 --count); 387 388 if (count == 0) 389 return -EBUSY; 390 391 return 0; 392 } 393 394 static void set_exception(struct memac_regs __iomem *regs, u32 val, 395 bool enable) 396 { 397 u32 tmp; 398 399 tmp = ioread32be(®s->imask); 400 if (enable) 401 tmp |= val; 402 else 403 tmp &= ~val; 404 405 iowrite32be(tmp, ®s->imask); 406 } 407 408 static int init(struct memac_regs __iomem *regs, struct memac_cfg *cfg, 409 phy_interface_t phy_if, u16 speed, bool slow_10g_if, 410 u32 exceptions) 411 { 412 u32 tmp; 413 414 /* Config */ 415 tmp = 0; 416 if (cfg->promiscuous_mode_enable) 417 tmp |= CMD_CFG_PROMIS_EN; 418 if (cfg->pause_ignore) 419 tmp |= CMD_CFG_PAUSE_IGNORE; 420 421 /* Payload length check disable */ 422 tmp |= CMD_CFG_NO_LEN_CHK; 423 /* Enable padding of frames in transmit direction */ 424 tmp |= CMD_CFG_TX_PAD_EN; 425 426 tmp |= CMD_CFG_CRC_FWD; 427 428 iowrite32be(tmp, ®s->command_config); 429 430 /* Max Frame Length */ 431 iowrite32be((u32)cfg->max_frame_length, ®s->maxfrm); 432 433 /* Pause Time */ 434 iowrite32be((u32)cfg->pause_quanta, ®s->pause_quanta[0]); 435 iowrite32be((u32)0, ®s->pause_thresh[0]); 436 437 /* IF_MODE */ 438 tmp = 0; 439 switch (phy_if) { 440 case PHY_INTERFACE_MODE_XGMII: 441 tmp |= IF_MODE_XGMII; 442 break; 443 default: 444 tmp |= IF_MODE_GMII; 445 if (phy_if == PHY_INTERFACE_MODE_RGMII) 446 tmp |= IF_MODE_RGMII | IF_MODE_RGMII_AUTO; 447 } 448 iowrite32be(tmp, ®s->if_mode); 449 450 /* TX_FIFO_SECTIONS */ 451 tmp = 0; 452 if (phy_if == PHY_INTERFACE_MODE_XGMII) { 453 if (slow_10g_if) { 454 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G | 455 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G); 456 } else { 457 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_10G | 458 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G); 459 } 460 } else { 461 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_1G | 462 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G); 463 } 464 iowrite32be(tmp, ®s->tx_fifo_sections); 465 466 /* clear all pending events and set-up interrupts */ 467 iowrite32be(0xffffffff, ®s->ievent); 468 set_exception(regs, exceptions, true); 469 470 return 0; 471 } 472 473 static void set_dflts(struct memac_cfg *cfg) 474 { 475 cfg->reset_on_init = false; 476 cfg->promiscuous_mode_enable = false; 477 cfg->pause_ignore = false; 478 cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH; 479 cfg->max_frame_length = DEFAULT_FRAME_LENGTH; 480 cfg->pause_quanta = DEFAULT_PAUSE_QUANTA; 481 } 482 483 static u32 get_mac_addr_hash_code(u64 eth_addr) 484 { 485 u64 mask1, mask2; 486 u32 xor_val = 0; 487 u8 i, j; 488 489 for (i = 0; i < 6; i++) { 490 mask1 = eth_addr & (u64)0x01; 491 eth_addr >>= 1; 492 493 for (j = 0; j < 7; j++) { 494 mask2 = eth_addr & (u64)0x01; 495 mask1 ^= mask2; 496 eth_addr >>= 1; 497 } 498 499 xor_val |= (mask1 << (5 - i)); 500 } 501 502 return xor_val; 503 } 504 505 static void setup_sgmii_internal_phy(struct fman_mac *memac, 506 struct fixed_phy_status *fixed_link) 507 { 508 u16 tmp_reg16; 509 510 /* SGMII mode */ 511 tmp_reg16 = IF_MODE_SGMII_EN; 512 if (!fixed_link) 513 /* AN enable */ 514 tmp_reg16 |= IF_MODE_USE_SGMII_AN; 515 else { 516 switch (fixed_link->speed) { 517 case 10: 518 /* For 10M: IF_MODE[SPEED_10M] = 0 */ 519 break; 520 case 100: 521 tmp_reg16 |= IF_MODE_SGMII_SPEED_100M; 522 break; 523 case 1000: /* fallthrough */ 524 default: 525 tmp_reg16 |= IF_MODE_SGMII_SPEED_1G; 526 break; 527 } 528 if (!fixed_link->duplex) 529 tmp_reg16 |= IF_MODE_SGMII_DUPLEX_HALF; 530 } 531 phy_write(memac->pcsphy, MDIO_SGMII_IF_MODE, tmp_reg16); 532 533 /* Device ability according to SGMII specification */ 534 tmp_reg16 = MDIO_SGMII_DEV_ABIL_SGMII_MODE; 535 phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16); 536 537 /* Adjust link timer for SGMII - 538 * According to Cisco SGMII specification the timer should be 1.6 ms. 539 * The link_timer register is configured in units of the clock. 540 * - When running as 1G SGMII, Serdes clock is 125 MHz, so 541 * unit = 1 / (125*10^6 Hz) = 8 ns. 542 * 1.6 ms in units of 8 ns = 1.6ms / 8ns = 2*10^5 = 0x30d40 543 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so 544 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns. 545 * 1.6 ms in units of 3.2 ns = 1.6ms / 3.2ns = 5*10^5 = 0x7a120. 546 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII, 547 * we always set up here a value of 2.5 SGMII. 548 */ 549 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H); 550 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L); 551 552 if (!fixed_link) 553 /* Restart AN */ 554 tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN; 555 else 556 /* AN disabled */ 557 tmp_reg16 = SGMII_CR_DEF_VAL & ~SGMII_CR_AN_EN; 558 phy_write(memac->pcsphy, 0x0, tmp_reg16); 559 } 560 561 static void setup_sgmii_internal_phy_base_x(struct fman_mac *memac) 562 { 563 u16 tmp_reg16; 564 565 /* AN Device capability */ 566 tmp_reg16 = MDIO_SGMII_DEV_ABIL_BASEX_MODE; 567 phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16); 568 569 /* Adjust link timer for SGMII - 570 * For Serdes 1000BaseX auto-negotiation the timer should be 10 ms. 571 * The link_timer register is configured in units of the clock. 572 * - When running as 1G SGMII, Serdes clock is 125 MHz, so 573 * unit = 1 / (125*10^6 Hz) = 8 ns. 574 * 10 ms in units of 8 ns = 10ms / 8ns = 1250000 = 0x1312d0 575 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so 576 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns. 577 * 10 ms in units of 3.2 ns = 10ms / 3.2ns = 3125000 = 0x2faf08. 578 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII, 579 * we always set up here a value of 2.5 SGMII. 580 */ 581 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H_BASEX); 582 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L_BASEX); 583 584 /* Restart AN */ 585 tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN; 586 phy_write(memac->pcsphy, 0x0, tmp_reg16); 587 } 588 589 static int check_init_parameters(struct fman_mac *memac) 590 { 591 if (memac->addr == 0) { 592 pr_err("Ethernet MAC must have a valid MAC address\n"); 593 return -EINVAL; 594 } 595 if (!memac->exception_cb) { 596 pr_err("Uninitialized exception handler\n"); 597 return -EINVAL; 598 } 599 if (!memac->event_cb) { 600 pr_warn("Uninitialize event handler\n"); 601 return -EINVAL; 602 } 603 604 return 0; 605 } 606 607 static int get_exception_flag(enum fman_mac_exceptions exception) 608 { 609 u32 bit_mask; 610 611 switch (exception) { 612 case FM_MAC_EX_10G_TX_ECC_ER: 613 bit_mask = MEMAC_IMASK_TECC_ER; 614 break; 615 case FM_MAC_EX_10G_RX_ECC_ER: 616 bit_mask = MEMAC_IMASK_RECC_ER; 617 break; 618 case FM_MAC_EX_TS_FIFO_ECC_ERR: 619 bit_mask = MEMAC_IMASK_TSECC_ER; 620 break; 621 case FM_MAC_EX_MAGIC_PACKET_INDICATION: 622 bit_mask = MEMAC_IMASK_MGI; 623 break; 624 default: 625 bit_mask = 0; 626 break; 627 } 628 629 return bit_mask; 630 } 631 632 static void memac_err_exception(void *handle) 633 { 634 struct fman_mac *memac = (struct fman_mac *)handle; 635 struct memac_regs __iomem *regs = memac->regs; 636 u32 event, imask; 637 638 event = ioread32be(®s->ievent); 639 imask = ioread32be(®s->imask); 640 641 /* Imask include both error and notification/event bits. 642 * Leaving only error bits enabled by imask. 643 * The imask error bits are shifted by 16 bits offset from 644 * their corresponding location in the ievent - hence the >> 16 645 */ 646 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16); 647 648 iowrite32be(event, ®s->ievent); 649 650 if (event & MEMAC_IEVNT_TS_ECC_ER) 651 memac->exception_cb(memac->dev_id, FM_MAC_EX_TS_FIFO_ECC_ERR); 652 if (event & MEMAC_IEVNT_TX_ECC_ER) 653 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_TX_ECC_ER); 654 if (event & MEMAC_IEVNT_RX_ECC_ER) 655 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_RX_ECC_ER); 656 } 657 658 static void memac_exception(void *handle) 659 { 660 struct fman_mac *memac = (struct fman_mac *)handle; 661 struct memac_regs __iomem *regs = memac->regs; 662 u32 event, imask; 663 664 event = ioread32be(®s->ievent); 665 imask = ioread32be(®s->imask); 666 667 /* Imask include both error and notification/event bits. 668 * Leaving only error bits enabled by imask. 669 * The imask error bits are shifted by 16 bits offset from 670 * their corresponding location in the ievent - hence the >> 16 671 */ 672 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16); 673 674 iowrite32be(event, ®s->ievent); 675 676 if (event & MEMAC_IEVNT_MGI) 677 memac->exception_cb(memac->dev_id, 678 FM_MAC_EX_MAGIC_PACKET_INDICATION); 679 } 680 681 static void free_init_resources(struct fman_mac *memac) 682 { 683 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 684 FMAN_INTR_TYPE_ERR); 685 686 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 687 FMAN_INTR_TYPE_NORMAL); 688 689 /* release the driver's group hash table */ 690 free_hash_table(memac->multicast_addr_hash); 691 memac->multicast_addr_hash = NULL; 692 693 /* release the driver's individual hash table */ 694 free_hash_table(memac->unicast_addr_hash); 695 memac->unicast_addr_hash = NULL; 696 } 697 698 static bool is_init_done(struct memac_cfg *memac_drv_params) 699 { 700 /* Checks if mEMAC driver parameters were initialized */ 701 if (!memac_drv_params) 702 return true; 703 704 return false; 705 } 706 707 int memac_enable(struct fman_mac *memac, enum comm_mode mode) 708 { 709 struct memac_regs __iomem *regs = memac->regs; 710 u32 tmp; 711 712 if (!is_init_done(memac->memac_drv_param)) 713 return -EINVAL; 714 715 tmp = ioread32be(®s->command_config); 716 if (mode & COMM_MODE_RX) 717 tmp |= CMD_CFG_RX_EN; 718 if (mode & COMM_MODE_TX) 719 tmp |= CMD_CFG_TX_EN; 720 721 iowrite32be(tmp, ®s->command_config); 722 723 return 0; 724 } 725 726 int memac_disable(struct fman_mac *memac, enum comm_mode mode) 727 { 728 struct memac_regs __iomem *regs = memac->regs; 729 u32 tmp; 730 731 if (!is_init_done(memac->memac_drv_param)) 732 return -EINVAL; 733 734 tmp = ioread32be(®s->command_config); 735 if (mode & COMM_MODE_RX) 736 tmp &= ~CMD_CFG_RX_EN; 737 if (mode & COMM_MODE_TX) 738 tmp &= ~CMD_CFG_TX_EN; 739 740 iowrite32be(tmp, ®s->command_config); 741 742 return 0; 743 } 744 745 int memac_set_promiscuous(struct fman_mac *memac, bool new_val) 746 { 747 struct memac_regs __iomem *regs = memac->regs; 748 u32 tmp; 749 750 if (!is_init_done(memac->memac_drv_param)) 751 return -EINVAL; 752 753 tmp = ioread32be(®s->command_config); 754 if (new_val) 755 tmp |= CMD_CFG_PROMIS_EN; 756 else 757 tmp &= ~CMD_CFG_PROMIS_EN; 758 759 iowrite32be(tmp, ®s->command_config); 760 761 return 0; 762 } 763 764 int memac_adjust_link(struct fman_mac *memac, u16 speed) 765 { 766 struct memac_regs __iomem *regs = memac->regs; 767 u32 tmp; 768 769 if (!is_init_done(memac->memac_drv_param)) 770 return -EINVAL; 771 772 tmp = ioread32be(®s->if_mode); 773 774 /* Set full duplex */ 775 tmp &= ~IF_MODE_HD; 776 777 if (memac->phy_if == PHY_INTERFACE_MODE_RGMII) { 778 /* Configure RGMII in manual mode */ 779 tmp &= ~IF_MODE_RGMII_AUTO; 780 tmp &= ~IF_MODE_RGMII_SP_MASK; 781 /* Full duplex */ 782 tmp |= IF_MODE_RGMII_FD; 783 784 switch (speed) { 785 case SPEED_1000: 786 tmp |= IF_MODE_RGMII_1000; 787 break; 788 case SPEED_100: 789 tmp |= IF_MODE_RGMII_100; 790 break; 791 case SPEED_10: 792 tmp |= IF_MODE_RGMII_10; 793 break; 794 default: 795 break; 796 } 797 } 798 799 iowrite32be(tmp, ®s->if_mode); 800 801 return 0; 802 } 803 804 int memac_cfg_max_frame_len(struct fman_mac *memac, u16 new_val) 805 { 806 if (is_init_done(memac->memac_drv_param)) 807 return -EINVAL; 808 809 memac->memac_drv_param->max_frame_length = new_val; 810 811 return 0; 812 } 813 814 int memac_cfg_reset_on_init(struct fman_mac *memac, bool enable) 815 { 816 if (is_init_done(memac->memac_drv_param)) 817 return -EINVAL; 818 819 memac->memac_drv_param->reset_on_init = enable; 820 821 return 0; 822 } 823 824 int memac_cfg_fixed_link(struct fman_mac *memac, 825 struct fixed_phy_status *fixed_link) 826 { 827 if (is_init_done(memac->memac_drv_param)) 828 return -EINVAL; 829 830 memac->memac_drv_param->fixed_link = fixed_link; 831 832 return 0; 833 } 834 835 int memac_set_tx_pause_frames(struct fman_mac *memac, u8 priority, 836 u16 pause_time, u16 thresh_time) 837 { 838 struct memac_regs __iomem *regs = memac->regs; 839 u32 tmp; 840 841 if (!is_init_done(memac->memac_drv_param)) 842 return -EINVAL; 843 844 tmp = ioread32be(®s->tx_fifo_sections); 845 846 GET_TX_EMPTY_DEFAULT_VALUE(tmp); 847 iowrite32be(tmp, ®s->tx_fifo_sections); 848 849 tmp = ioread32be(®s->command_config); 850 tmp &= ~CMD_CFG_PFC_MODE; 851 priority = 0; 852 853 iowrite32be(tmp, ®s->command_config); 854 855 tmp = ioread32be(®s->pause_quanta[priority / 2]); 856 if (priority % 2) 857 tmp &= CLXY_PAUSE_QUANTA_CLX_PQNT; 858 else 859 tmp &= CLXY_PAUSE_QUANTA_CLY_PQNT; 860 tmp |= ((u32)pause_time << (16 * (priority % 2))); 861 iowrite32be(tmp, ®s->pause_quanta[priority / 2]); 862 863 tmp = ioread32be(®s->pause_thresh[priority / 2]); 864 if (priority % 2) 865 tmp &= CLXY_PAUSE_THRESH_CLX_QTH; 866 else 867 tmp &= CLXY_PAUSE_THRESH_CLY_QTH; 868 tmp |= ((u32)thresh_time << (16 * (priority % 2))); 869 iowrite32be(tmp, ®s->pause_thresh[priority / 2]); 870 871 return 0; 872 } 873 874 int memac_accept_rx_pause_frames(struct fman_mac *memac, bool en) 875 { 876 struct memac_regs __iomem *regs = memac->regs; 877 u32 tmp; 878 879 if (!is_init_done(memac->memac_drv_param)) 880 return -EINVAL; 881 882 tmp = ioread32be(®s->command_config); 883 if (en) 884 tmp &= ~CMD_CFG_PAUSE_IGNORE; 885 else 886 tmp |= CMD_CFG_PAUSE_IGNORE; 887 888 iowrite32be(tmp, ®s->command_config); 889 890 return 0; 891 } 892 893 int memac_modify_mac_address(struct fman_mac *memac, enet_addr_t *enet_addr) 894 { 895 if (!is_init_done(memac->memac_drv_param)) 896 return -EINVAL; 897 898 add_addr_in_paddr(memac->regs, (u8 *)(*enet_addr), 0); 899 900 return 0; 901 } 902 903 int memac_add_hash_mac_address(struct fman_mac *memac, enet_addr_t *eth_addr) 904 { 905 struct memac_regs __iomem *regs = memac->regs; 906 struct eth_hash_entry *hash_entry; 907 u32 hash; 908 u64 addr; 909 910 if (!is_init_done(memac->memac_drv_param)) 911 return -EINVAL; 912 913 addr = ENET_ADDR_TO_UINT64(*eth_addr); 914 915 if (!(addr & GROUP_ADDRESS)) { 916 /* Unicast addresses not supported in hash */ 917 pr_err("Unicast Address\n"); 918 return -EINVAL; 919 } 920 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK; 921 922 /* Create element to be added to the driver hash table */ 923 hash_entry = kmalloc(sizeof(*hash_entry), GFP_KERNEL); 924 if (!hash_entry) 925 return -ENOMEM; 926 hash_entry->addr = addr; 927 INIT_LIST_HEAD(&hash_entry->node); 928 929 list_add_tail(&hash_entry->node, 930 &memac->multicast_addr_hash->lsts[hash]); 931 iowrite32be(hash | HASH_CTRL_MCAST_EN, ®s->hashtable_ctrl); 932 933 return 0; 934 } 935 936 int memac_del_hash_mac_address(struct fman_mac *memac, enet_addr_t *eth_addr) 937 { 938 struct memac_regs __iomem *regs = memac->regs; 939 struct eth_hash_entry *hash_entry = NULL; 940 struct list_head *pos; 941 u32 hash; 942 u64 addr; 943 944 if (!is_init_done(memac->memac_drv_param)) 945 return -EINVAL; 946 947 addr = ENET_ADDR_TO_UINT64(*eth_addr); 948 949 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK; 950 951 list_for_each(pos, &memac->multicast_addr_hash->lsts[hash]) { 952 hash_entry = ETH_HASH_ENTRY_OBJ(pos); 953 if (hash_entry->addr == addr) { 954 list_del_init(&hash_entry->node); 955 kfree(hash_entry); 956 break; 957 } 958 } 959 if (list_empty(&memac->multicast_addr_hash->lsts[hash])) 960 iowrite32be(hash & ~HASH_CTRL_MCAST_EN, ®s->hashtable_ctrl); 961 962 return 0; 963 } 964 965 int memac_set_exception(struct fman_mac *memac, 966 enum fman_mac_exceptions exception, bool enable) 967 { 968 u32 bit_mask = 0; 969 970 if (!is_init_done(memac->memac_drv_param)) 971 return -EINVAL; 972 973 bit_mask = get_exception_flag(exception); 974 if (bit_mask) { 975 if (enable) 976 memac->exceptions |= bit_mask; 977 else 978 memac->exceptions &= ~bit_mask; 979 } else { 980 pr_err("Undefined exception\n"); 981 return -EINVAL; 982 } 983 set_exception(memac->regs, bit_mask, enable); 984 985 return 0; 986 } 987 988 int memac_init(struct fman_mac *memac) 989 { 990 struct memac_cfg *memac_drv_param; 991 u8 i; 992 enet_addr_t eth_addr; 993 bool slow_10g_if = false; 994 struct fixed_phy_status *fixed_link; 995 int err; 996 u32 reg32 = 0; 997 998 if (is_init_done(memac->memac_drv_param)) 999 return -EINVAL; 1000 1001 err = check_init_parameters(memac); 1002 if (err) 1003 return err; 1004 1005 memac_drv_param = memac->memac_drv_param; 1006 1007 if (memac->fm_rev_info.major == 6 && memac->fm_rev_info.minor == 4) 1008 slow_10g_if = true; 1009 1010 /* First, reset the MAC if desired. */ 1011 if (memac_drv_param->reset_on_init) { 1012 err = reset(memac->regs); 1013 if (err) { 1014 pr_err("mEMAC reset failed\n"); 1015 return err; 1016 } 1017 } 1018 1019 /* MAC Address */ 1020 MAKE_ENET_ADDR_FROM_UINT64(memac->addr, eth_addr); 1021 add_addr_in_paddr(memac->regs, (u8 *)eth_addr, 0); 1022 1023 fixed_link = memac_drv_param->fixed_link; 1024 1025 init(memac->regs, memac->memac_drv_param, memac->phy_if, 1026 memac->max_speed, slow_10g_if, memac->exceptions); 1027 1028 /* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 errata workaround 1029 * Exists only in FMan 6.0 and 6.3. 1030 */ 1031 if ((memac->fm_rev_info.major == 6) && 1032 ((memac->fm_rev_info.minor == 0) || 1033 (memac->fm_rev_info.minor == 3))) { 1034 /* MAC strips CRC from received frames - this workaround 1035 * should decrease the likelihood of bug appearance 1036 */ 1037 reg32 = ioread32be(&memac->regs->command_config); 1038 reg32 &= ~CMD_CFG_CRC_FWD; 1039 iowrite32be(reg32, &memac->regs->command_config); 1040 } 1041 1042 if (memac->phy_if == PHY_INTERFACE_MODE_SGMII) { 1043 /* Configure internal SGMII PHY */ 1044 if (memac->basex_if) 1045 setup_sgmii_internal_phy_base_x(memac); 1046 else 1047 setup_sgmii_internal_phy(memac, fixed_link); 1048 } else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII) { 1049 /* Configure 4 internal SGMII PHYs */ 1050 for (i = 0; i < 4; i++) { 1051 u8 qsmgii_phy_addr, phy_addr; 1052 /* QSGMII PHY address occupies 3 upper bits of 5-bit 1053 * phy_address; the lower 2 bits are used to extend 1054 * register address space and access each one of 4 1055 * ports inside QSGMII. 1056 */ 1057 phy_addr = memac->pcsphy->mdio.addr; 1058 qsmgii_phy_addr = (u8)((phy_addr << 2) | i); 1059 memac->pcsphy->mdio.addr = qsmgii_phy_addr; 1060 if (memac->basex_if) 1061 setup_sgmii_internal_phy_base_x(memac); 1062 else 1063 setup_sgmii_internal_phy(memac, fixed_link); 1064 1065 memac->pcsphy->mdio.addr = phy_addr; 1066 } 1067 } 1068 1069 /* Max Frame Length */ 1070 err = fman_set_mac_max_frame(memac->fm, memac->mac_id, 1071 memac_drv_param->max_frame_length); 1072 if (err) { 1073 pr_err("settings Mac max frame length is FAILED\n"); 1074 return err; 1075 } 1076 1077 memac->multicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE); 1078 if (!memac->multicast_addr_hash) { 1079 free_init_resources(memac); 1080 pr_err("allocation hash table is FAILED\n"); 1081 return -ENOMEM; 1082 } 1083 1084 memac->unicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE); 1085 if (!memac->unicast_addr_hash) { 1086 free_init_resources(memac); 1087 pr_err("allocation hash table is FAILED\n"); 1088 return -ENOMEM; 1089 } 1090 1091 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 1092 FMAN_INTR_TYPE_ERR, memac_err_exception, memac); 1093 1094 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, 1095 FMAN_INTR_TYPE_NORMAL, memac_exception, memac); 1096 1097 kfree(memac_drv_param); 1098 memac->memac_drv_param = NULL; 1099 1100 return 0; 1101 } 1102 1103 int memac_free(struct fman_mac *memac) 1104 { 1105 free_init_resources(memac); 1106 1107 kfree(memac->memac_drv_param); 1108 kfree(memac); 1109 1110 return 0; 1111 } 1112 1113 struct fman_mac *memac_config(struct fman_mac_params *params) 1114 { 1115 struct fman_mac *memac; 1116 struct memac_cfg *memac_drv_param; 1117 void __iomem *base_addr; 1118 1119 base_addr = params->base_addr; 1120 /* allocate memory for the m_emac data structure */ 1121 memac = kzalloc(sizeof(*memac), GFP_KERNEL); 1122 if (!memac) 1123 return NULL; 1124 1125 /* allocate memory for the m_emac driver parameters data structure */ 1126 memac_drv_param = kzalloc(sizeof(*memac_drv_param), GFP_KERNEL); 1127 if (!memac_drv_param) { 1128 memac_free(memac); 1129 return NULL; 1130 } 1131 1132 /* Plant parameter structure pointer */ 1133 memac->memac_drv_param = memac_drv_param; 1134 1135 set_dflts(memac_drv_param); 1136 1137 memac->addr = ENET_ADDR_TO_UINT64(params->addr); 1138 1139 memac->regs = base_addr; 1140 memac->max_speed = params->max_speed; 1141 memac->phy_if = params->phy_if; 1142 memac->mac_id = params->mac_id; 1143 memac->exceptions = (MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER | 1144 MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI); 1145 memac->exception_cb = params->exception_cb; 1146 memac->event_cb = params->event_cb; 1147 memac->dev_id = params->dev_id; 1148 memac->fm = params->fm; 1149 memac->basex_if = params->basex_if; 1150 1151 /* Save FMan revision */ 1152 fman_get_revision(memac->fm, &memac->fm_rev_info); 1153 1154 if (memac->phy_if == PHY_INTERFACE_MODE_SGMII) { 1155 if (!params->internal_phy_node) { 1156 pr_err("PCS PHY node is not available\n"); 1157 memac_free(memac); 1158 return NULL; 1159 } 1160 1161 memac->pcsphy = of_phy_find_device(params->internal_phy_node); 1162 if (!memac->pcsphy) { 1163 pr_err("of_phy_find_device (PCS PHY) failed\n"); 1164 memac_free(memac); 1165 return NULL; 1166 } 1167 } 1168 1169 return memac; 1170 } 1171