1# SPDX-License-Identifier: GPL-2.0-only 2config FSL_FMAN 3 tristate "FMan support" 4 depends on FSL_SOC || ARCH_LAYERSCAPE || COMPILE_TEST 5 select GENERIC_ALLOCATOR 6 select PHYLINK 7 select PCS 8 select PCS_LYNX 9 select CRC32 10 default n 11 help 12 Freescale Data-Path Acceleration Architecture Frame Manager 13 (FMan) support 14 15config DPAA_ERRATUM_A050385 16 bool 17 depends on ARM64 && FSL_DPAA 18 default y 19 help 20 DPAA FMan erratum A050385 software workaround implementation: 21 align buffers, data start, SG fragment length to avoid FMan DMA 22 splits. 23 FMAN DMA read or writes under heavy traffic load may cause FMAN 24 internal resource leak thus stopping further packet processing. 25 The FMAN internal queue can overflow when FMAN splits single 26 read or write transactions into multiple smaller transactions 27 such that more than 17 AXI transactions are in flight from FMAN 28 to interconnect. When the FMAN internal queue overflows, it can 29 stall further packet processing. The issue can occur with any 30 one of the following three conditions: 31 1. FMAN AXI transaction crosses 4K address boundary (Errata 32 A010022) 33 2. FMAN DMA address for an AXI transaction is not 16 byte 34 aligned, i.e. the last 4 bits of an address are non-zero 35 3. Scatter Gather (SG) frames have more than one SG buffer in 36 the SG list and any one of the buffers, except the last 37 buffer in the SG list has data size that is not a multiple 38 of 16 bytes, i.e., other than 16, 32, 48, 64, etc. 39 With any one of the above three conditions present, there is 40 likelihood of stalled FMAN packet processing, especially under 41 stress with multiple ports injecting line-rate traffic. 42