1 /* 2 * Fast Ethernet Controller (ENET) PTP driver for MX6x. 3 * 4 * Copyright (C) 2012 Freescale Semiconductor, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program; if not, write to the Free Software Foundation, Inc., 17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 */ 19 20 #include <linux/module.h> 21 #include <linux/kernel.h> 22 #include <linux/string.h> 23 #include <linux/ptrace.h> 24 #include <linux/errno.h> 25 #include <linux/ioport.h> 26 #include <linux/slab.h> 27 #include <linux/interrupt.h> 28 #include <linux/pci.h> 29 #include <linux/init.h> 30 #include <linux/delay.h> 31 #include <linux/netdevice.h> 32 #include <linux/etherdevice.h> 33 #include <linux/skbuff.h> 34 #include <linux/spinlock.h> 35 #include <linux/workqueue.h> 36 #include <linux/bitops.h> 37 #include <linux/io.h> 38 #include <linux/irq.h> 39 #include <linux/clk.h> 40 #include <linux/platform_device.h> 41 #include <linux/phy.h> 42 #include <linux/fec.h> 43 #include <linux/of.h> 44 #include <linux/of_device.h> 45 #include <linux/of_gpio.h> 46 #include <linux/of_net.h> 47 48 #include "fec.h" 49 50 /* FEC 1588 register bits */ 51 #define FEC_T_CTRL_SLAVE 0x00002000 52 #define FEC_T_CTRL_CAPTURE 0x00000800 53 #define FEC_T_CTRL_RESTART 0x00000200 54 #define FEC_T_CTRL_PERIOD_RST 0x00000030 55 #define FEC_T_CTRL_PERIOD_EN 0x00000010 56 #define FEC_T_CTRL_ENABLE 0x00000001 57 58 #define FEC_T_INC_MASK 0x0000007f 59 #define FEC_T_INC_OFFSET 0 60 #define FEC_T_INC_CORR_MASK 0x00007f00 61 #define FEC_T_INC_CORR_OFFSET 8 62 63 #define FEC_ATIME_CTRL 0x400 64 #define FEC_ATIME 0x404 65 #define FEC_ATIME_EVT_OFFSET 0x408 66 #define FEC_ATIME_EVT_PERIOD 0x40c 67 #define FEC_ATIME_CORR 0x410 68 #define FEC_ATIME_INC 0x414 69 #define FEC_TS_TIMESTAMP 0x418 70 71 #define FEC_CC_MULT (1 << 31) 72 /** 73 * fec_ptp_read - read raw cycle counter (to be used by time counter) 74 * @cc: the cyclecounter structure 75 * 76 * this function reads the cyclecounter registers and is called by the 77 * cyclecounter structure used to construct a ns counter from the 78 * arbitrary fixed point registers 79 */ 80 static cycle_t fec_ptp_read(const struct cyclecounter *cc) 81 { 82 struct fec_enet_private *fep = 83 container_of(cc, struct fec_enet_private, cc); 84 u32 tempval; 85 86 tempval = readl(fep->hwp + FEC_ATIME_CTRL); 87 tempval |= FEC_T_CTRL_CAPTURE; 88 writel(tempval, fep->hwp + FEC_ATIME_CTRL); 89 90 return readl(fep->hwp + FEC_ATIME); 91 } 92 93 /** 94 * fec_ptp_start_cyclecounter - create the cycle counter from hw 95 * @ndev: network device 96 * 97 * this function initializes the timecounter and cyclecounter 98 * structures for use in generated a ns counter from the arbitrary 99 * fixed point cycles registers in the hardware. 100 */ 101 void fec_ptp_start_cyclecounter(struct net_device *ndev) 102 { 103 struct fec_enet_private *fep = netdev_priv(ndev); 104 unsigned long flags; 105 int inc; 106 107 inc = 1000000000 / clk_get_rate(fep->clk_ptp); 108 109 /* grab the ptp lock */ 110 spin_lock_irqsave(&fep->tmreg_lock, flags); 111 112 /* 1ns counter */ 113 writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC); 114 115 /* use free running count */ 116 writel(0, fep->hwp + FEC_ATIME_EVT_PERIOD); 117 118 writel(FEC_T_CTRL_ENABLE, fep->hwp + FEC_ATIME_CTRL); 119 120 memset(&fep->cc, 0, sizeof(fep->cc)); 121 fep->cc.read = fec_ptp_read; 122 fep->cc.mask = CLOCKSOURCE_MASK(32); 123 fep->cc.shift = 31; 124 fep->cc.mult = FEC_CC_MULT; 125 126 /* reset the ns time counter */ 127 timecounter_init(&fep->tc, &fep->cc, ktime_to_ns(ktime_get_real())); 128 129 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 130 } 131 132 /** 133 * fec_ptp_adjfreq - adjust ptp cycle frequency 134 * @ptp: the ptp clock structure 135 * @ppb: parts per billion adjustment from base 136 * 137 * Adjust the frequency of the ptp cycle counter by the 138 * indicated ppb from the base frequency. 139 * 140 * Because ENET hardware frequency adjust is complex, 141 * using software method to do that. 142 */ 143 static int fec_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 144 { 145 u64 diff; 146 unsigned long flags; 147 int neg_adj = 0; 148 u32 mult = FEC_CC_MULT; 149 150 struct fec_enet_private *fep = 151 container_of(ptp, struct fec_enet_private, ptp_caps); 152 153 if (ppb < 0) { 154 ppb = -ppb; 155 neg_adj = 1; 156 } 157 158 diff = mult; 159 diff *= ppb; 160 diff = div_u64(diff, 1000000000ULL); 161 162 spin_lock_irqsave(&fep->tmreg_lock, flags); 163 /* 164 * dummy read to set cycle_last in tc to now. 165 * So use adjusted mult to calculate when next call 166 * timercounter_read. 167 */ 168 timecounter_read(&fep->tc); 169 170 fep->cc.mult = neg_adj ? mult - diff : mult + diff; 171 172 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 173 174 return 0; 175 } 176 177 /** 178 * fec_ptp_adjtime 179 * @ptp: the ptp clock structure 180 * @delta: offset to adjust the cycle counter by 181 * 182 * adjust the timer by resetting the timecounter structure. 183 */ 184 static int fec_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 185 { 186 struct fec_enet_private *fep = 187 container_of(ptp, struct fec_enet_private, ptp_caps); 188 unsigned long flags; 189 u64 now; 190 191 spin_lock_irqsave(&fep->tmreg_lock, flags); 192 193 now = timecounter_read(&fep->tc); 194 now += delta; 195 196 /* reset the timecounter */ 197 timecounter_init(&fep->tc, &fep->cc, now); 198 199 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 200 201 return 0; 202 } 203 204 /** 205 * fec_ptp_gettime 206 * @ptp: the ptp clock structure 207 * @ts: timespec structure to hold the current time value 208 * 209 * read the timecounter and return the correct value on ns, 210 * after converting it into a struct timespec. 211 */ 212 static int fec_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts) 213 { 214 struct fec_enet_private *adapter = 215 container_of(ptp, struct fec_enet_private, ptp_caps); 216 u64 ns; 217 u32 remainder; 218 unsigned long flags; 219 220 spin_lock_irqsave(&adapter->tmreg_lock, flags); 221 ns = timecounter_read(&adapter->tc); 222 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 223 224 ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder); 225 ts->tv_nsec = remainder; 226 227 return 0; 228 } 229 230 /** 231 * fec_ptp_settime 232 * @ptp: the ptp clock structure 233 * @ts: the timespec containing the new time for the cycle counter 234 * 235 * reset the timecounter to use a new base value instead of the kernel 236 * wall timer value. 237 */ 238 static int fec_ptp_settime(struct ptp_clock_info *ptp, 239 const struct timespec *ts) 240 { 241 struct fec_enet_private *fep = 242 container_of(ptp, struct fec_enet_private, ptp_caps); 243 244 u64 ns; 245 unsigned long flags; 246 247 ns = ts->tv_sec * 1000000000ULL; 248 ns += ts->tv_nsec; 249 250 spin_lock_irqsave(&fep->tmreg_lock, flags); 251 timecounter_init(&fep->tc, &fep->cc, ns); 252 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 253 return 0; 254 } 255 256 /** 257 * fec_ptp_enable 258 * @ptp: the ptp clock structure 259 * @rq: the requested feature to change 260 * @on: whether to enable or disable the feature 261 * 262 */ 263 static int fec_ptp_enable(struct ptp_clock_info *ptp, 264 struct ptp_clock_request *rq, int on) 265 { 266 return -EOPNOTSUPP; 267 } 268 269 /** 270 * fec_ptp_hwtstamp_ioctl - control hardware time stamping 271 * @ndev: pointer to net_device 272 * @ifreq: ioctl data 273 * @cmd: particular ioctl requested 274 */ 275 int fec_ptp_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) 276 { 277 struct fec_enet_private *fep = netdev_priv(ndev); 278 279 struct hwtstamp_config config; 280 281 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 282 return -EFAULT; 283 284 /* reserved for future extensions */ 285 if (config.flags) 286 return -EINVAL; 287 288 switch (config.tx_type) { 289 case HWTSTAMP_TX_OFF: 290 fep->hwts_tx_en = 0; 291 break; 292 case HWTSTAMP_TX_ON: 293 fep->hwts_tx_en = 1; 294 break; 295 default: 296 return -ERANGE; 297 } 298 299 switch (config.rx_filter) { 300 case HWTSTAMP_FILTER_NONE: 301 if (fep->hwts_rx_en) 302 fep->hwts_rx_en = 0; 303 config.rx_filter = HWTSTAMP_FILTER_NONE; 304 break; 305 306 default: 307 /* 308 * register RXMTRL must be set in order to do V1 packets, 309 * therefore it is not possible to time stamp both V1 Sync and 310 * Delay_Req messages and hardware does not support 311 * timestamping all packets => return error 312 */ 313 fep->hwts_rx_en = 1; 314 config.rx_filter = HWTSTAMP_FILTER_ALL; 315 break; 316 } 317 318 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 319 -EFAULT : 0; 320 } 321 322 /** 323 * fec_time_keep - call timecounter_read every second to avoid timer overrun 324 * because ENET just support 32bit counter, will timeout in 4s 325 */ 326 static void fec_time_keep(unsigned long _data) 327 { 328 struct fec_enet_private *fep = (struct fec_enet_private *)_data; 329 u64 ns; 330 unsigned long flags; 331 332 spin_lock_irqsave(&fep->tmreg_lock, flags); 333 ns = timecounter_read(&fep->tc); 334 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 335 336 mod_timer(&fep->time_keep, jiffies + HZ); 337 } 338 339 /** 340 * fec_ptp_init 341 * @ndev: The FEC network adapter 342 * 343 * This function performs the required steps for enabling ptp 344 * support. If ptp support has already been loaded it simply calls the 345 * cyclecounter init routine and exits. 346 */ 347 348 void fec_ptp_init(struct net_device *ndev, struct platform_device *pdev) 349 { 350 struct fec_enet_private *fep = netdev_priv(ndev); 351 352 fep->ptp_caps.owner = THIS_MODULE; 353 snprintf(fep->ptp_caps.name, 16, "fec ptp"); 354 355 fep->ptp_caps.max_adj = 250000000; 356 fep->ptp_caps.n_alarm = 0; 357 fep->ptp_caps.n_ext_ts = 0; 358 fep->ptp_caps.n_per_out = 0; 359 fep->ptp_caps.pps = 0; 360 fep->ptp_caps.adjfreq = fec_ptp_adjfreq; 361 fep->ptp_caps.adjtime = fec_ptp_adjtime; 362 fep->ptp_caps.gettime = fec_ptp_gettime; 363 fep->ptp_caps.settime = fec_ptp_settime; 364 fep->ptp_caps.enable = fec_ptp_enable; 365 366 spin_lock_init(&fep->tmreg_lock); 367 368 fec_ptp_start_cyclecounter(ndev); 369 370 init_timer(&fep->time_keep); 371 fep->time_keep.data = (unsigned long)fep; 372 fep->time_keep.function = fec_time_keep; 373 fep->time_keep.expires = jiffies + HZ; 374 add_timer(&fep->time_keep); 375 376 fep->ptp_clock = ptp_clock_register(&fep->ptp_caps, &pdev->dev); 377 if (IS_ERR(fep->ptp_clock)) { 378 fep->ptp_clock = NULL; 379 pr_err("ptp_clock_register failed\n"); 380 } else { 381 pr_info("registered PHC device on %s\n", ndev->name); 382 } 383 } 384