1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/bitops.h> 26 #include <linux/bpf.h> 27 #include <linux/bpf_trace.h> 28 #include <linux/cacheflush.h> 29 #include <linux/clk.h> 30 #include <linux/crc32.h> 31 #include <linux/delay.h> 32 #include <linux/errno.h> 33 #include <linux/etherdevice.h> 34 #include <linux/fec.h> 35 #include <linux/filter.h> 36 #include <linux/gpio/consumer.h> 37 #include <linux/icmp.h> 38 #include <linux/if_vlan.h> 39 #include <linux/in.h> 40 #include <linux/interrupt.h> 41 #include <linux/io.h> 42 #include <linux/ioport.h> 43 #include <linux/ip.h> 44 #include <linux/irq.h> 45 #include <linux/kernel.h> 46 #include <linux/mdio.h> 47 #include <linux/mfd/syscon.h> 48 #include <linux/module.h> 49 #include <linux/netdevice.h> 50 #include <linux/of.h> 51 #include <linux/of_mdio.h> 52 #include <linux/of_net.h> 53 #include <linux/phy.h> 54 #include <linux/pinctrl/consumer.h> 55 #include <linux/platform_device.h> 56 #include <linux/pm_runtime.h> 57 #include <linux/prefetch.h> 58 #include <linux/property.h> 59 #include <linux/ptrace.h> 60 #include <linux/regmap.h> 61 #include <linux/regulator/consumer.h> 62 #include <linux/skbuff.h> 63 #include <linux/slab.h> 64 #include <linux/spinlock.h> 65 #include <linux/string.h> 66 #include <linux/tcp.h> 67 #include <linux/udp.h> 68 #include <linux/workqueue.h> 69 #include <net/ip.h> 70 #include <net/page_pool/helpers.h> 71 #include <net/selftests.h> 72 #include <net/tso.h> 73 #include <soc/imx/cpuidle.h> 74 75 #include "fec.h" 76 77 static void set_multicast_list(struct net_device *ndev); 78 static void fec_enet_itr_coal_set(struct net_device *ndev); 79 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 80 int cpu, struct xdp_buff *xdp, 81 u32 dma_sync_len); 82 83 #define DRIVER_NAME "fec" 84 85 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 86 87 #define FEC_ENET_RSEM_V 0x84 88 #define FEC_ENET_RSFL_V 16 89 #define FEC_ENET_RAEM_V 0x8 90 #define FEC_ENET_RAFL_V 0x8 91 #define FEC_ENET_OPD_V 0xFFF0 92 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 93 94 #define FEC_ENET_XDP_PASS 0 95 #define FEC_ENET_XDP_CONSUMED BIT(0) 96 #define FEC_ENET_XDP_TX BIT(1) 97 #define FEC_ENET_XDP_REDIR BIT(2) 98 99 struct fec_devinfo { 100 u32 quirks; 101 }; 102 103 static const struct fec_devinfo fec_imx25_info = { 104 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 105 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_HAS_MDIO_C45, 106 }; 107 108 static const struct fec_devinfo fec_imx27_info = { 109 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG | 110 FEC_QUIRK_HAS_MDIO_C45, 111 }; 112 113 static const struct fec_devinfo fec_imx28_info = { 114 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 115 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 116 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 117 FEC_QUIRK_NO_HARD_RESET | FEC_QUIRK_HAS_MDIO_C45, 118 }; 119 120 static const struct fec_devinfo fec_imx6q_info = { 121 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 122 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 123 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 124 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII | 125 FEC_QUIRK_HAS_PMQOS | FEC_QUIRK_HAS_MDIO_C45, 126 }; 127 128 static const struct fec_devinfo fec_mvf600_info = { 129 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC | 130 FEC_QUIRK_HAS_MDIO_C45, 131 }; 132 133 static const struct fec_devinfo fec_imx6sx_info = { 134 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 135 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 136 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 137 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 138 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 139 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 140 FEC_QUIRK_HAS_MDIO_C45, 141 }; 142 143 static const struct fec_devinfo fec_imx6ul_info = { 144 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 145 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 146 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 147 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 148 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII | 149 FEC_QUIRK_HAS_MDIO_C45, 150 }; 151 152 static const struct fec_devinfo fec_imx8mq_info = { 153 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 154 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 155 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 156 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 157 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 158 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 159 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2 | 160 FEC_QUIRK_HAS_MDIO_C45, 161 }; 162 163 static const struct fec_devinfo fec_imx8qm_info = { 164 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 165 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 166 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 167 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 168 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 169 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 170 FEC_QUIRK_DELAYED_CLKS_SUPPORT | FEC_QUIRK_HAS_MDIO_C45 | 171 FEC_QUIRK_JUMBO_FRAME, 172 }; 173 174 static const struct fec_devinfo fec_s32v234_info = { 175 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 176 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 177 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 178 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 179 FEC_QUIRK_HAS_MDIO_C45, 180 }; 181 182 static struct platform_device_id fec_devtype[] = { 183 { 184 /* keep it for coldfire */ 185 .name = DRIVER_NAME, 186 .driver_data = 0, 187 }, { 188 /* sentinel */ 189 } 190 }; 191 MODULE_DEVICE_TABLE(platform, fec_devtype); 192 193 static const struct of_device_id fec_dt_ids[] = { 194 { .compatible = "fsl,imx25-fec", .data = &fec_imx25_info, }, 195 { .compatible = "fsl,imx27-fec", .data = &fec_imx27_info, }, 196 { .compatible = "fsl,imx28-fec", .data = &fec_imx28_info, }, 197 { .compatible = "fsl,imx6q-fec", .data = &fec_imx6q_info, }, 198 { .compatible = "fsl,mvf600-fec", .data = &fec_mvf600_info, }, 199 { .compatible = "fsl,imx6sx-fec", .data = &fec_imx6sx_info, }, 200 { .compatible = "fsl,imx6ul-fec", .data = &fec_imx6ul_info, }, 201 { .compatible = "fsl,imx8mq-fec", .data = &fec_imx8mq_info, }, 202 { .compatible = "fsl,imx8qm-fec", .data = &fec_imx8qm_info, }, 203 { .compatible = "fsl,s32v234-fec", .data = &fec_s32v234_info, }, 204 { /* sentinel */ } 205 }; 206 MODULE_DEVICE_TABLE(of, fec_dt_ids); 207 208 static unsigned char macaddr[ETH_ALEN]; 209 module_param_array(macaddr, byte, NULL, 0); 210 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 211 212 #if defined(CONFIG_M5272) 213 /* 214 * Some hardware gets it MAC address out of local flash memory. 215 * if this is non-zero then assume it is the address to get MAC from. 216 */ 217 #if defined(CONFIG_NETtel) 218 #define FEC_FLASHMAC 0xf0006006 219 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 220 #define FEC_FLASHMAC 0xf0006000 221 #elif defined(CONFIG_CANCam) 222 #define FEC_FLASHMAC 0xf0020000 223 #elif defined (CONFIG_M5272C3) 224 #define FEC_FLASHMAC (0xffe04000 + 4) 225 #elif defined(CONFIG_MOD5272) 226 #define FEC_FLASHMAC 0xffc0406b 227 #else 228 #define FEC_FLASHMAC 0 229 #endif 230 #endif /* CONFIG_M5272 */ 231 232 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 233 * 234 * 2048 byte skbufs are allocated. However, alignment requirements 235 * varies between FEC variants. Worst case is 64, so round down by 64. 236 */ 237 #define MAX_JUMBO_BUF_SIZE (round_down(16384 - FEC_DRV_RESERVE_SPACE - 64, 64)) 238 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 239 #define PKT_MINBUF_SIZE 64 240 241 /* FEC receive acceleration */ 242 #define FEC_RACC_IPDIS BIT(1) 243 #define FEC_RACC_PRODIS BIT(2) 244 #define FEC_RACC_SHIFT16 BIT(7) 245 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 246 247 /* MIB Control Register */ 248 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 249 250 /* 251 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 252 * size bits. Other FEC hardware does not, so we need to take that into 253 * account when setting it. 254 */ 255 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 256 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 257 defined(CONFIG_ARM64) 258 #define OPT_ARCH_HAS_MAX_FL 1 259 #else 260 #define OPT_ARCH_HAS_MAX_FL 0 261 #endif 262 263 /* FEC MII MMFR bits definition */ 264 #define FEC_MMFR_ST (1 << 30) 265 #define FEC_MMFR_ST_C45 (0) 266 #define FEC_MMFR_OP_READ (2 << 28) 267 #define FEC_MMFR_OP_READ_C45 (3 << 28) 268 #define FEC_MMFR_OP_WRITE (1 << 28) 269 #define FEC_MMFR_OP_ADDR_WRITE (0) 270 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 271 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 272 #define FEC_MMFR_TA (2 << 16) 273 #define FEC_MMFR_DATA(v) (v & 0xffff) 274 /* FEC ECR bits definition */ 275 #define FEC_ECR_RESET BIT(0) 276 #define FEC_ECR_ETHEREN BIT(1) 277 #define FEC_ECR_MAGICEN BIT(2) 278 #define FEC_ECR_SLEEP BIT(3) 279 #define FEC_ECR_EN1588 BIT(4) 280 #define FEC_ECR_SPEED BIT(5) 281 #define FEC_ECR_BYTESWP BIT(8) 282 /* FEC RCR bits definition */ 283 #define FEC_RCR_LOOP BIT(0) 284 #define FEC_RCR_DRT BIT(1) 285 #define FEC_RCR_MII BIT(2) 286 #define FEC_RCR_PROMISC BIT(3) 287 #define FEC_RCR_BC_REJ BIT(4) 288 #define FEC_RCR_FLOWCTL BIT(5) 289 #define FEC_RCR_RGMII BIT(6) 290 #define FEC_RCR_RMII BIT(8) 291 #define FEC_RCR_10BASET BIT(9) 292 #define FEC_RCR_NLC BIT(30) 293 /* TX WMARK bits */ 294 #define FEC_TXWMRK_STRFWD BIT(8) 295 296 #define FEC_MII_TIMEOUT 30000 /* us */ 297 298 /* Transmitter timeout */ 299 #define TX_TIMEOUT (2 * HZ) 300 301 #define FEC_PAUSE_FLAG_AUTONEG 0x1 302 #define FEC_PAUSE_FLAG_ENABLE 0x2 303 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 304 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 305 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 306 307 /* Max number of allowed TCP segments for software TSO */ 308 #define FEC_MAX_TSO_SEGS 100 309 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 310 311 #define IS_TSO_HEADER(txq, addr) \ 312 ((addr >= txq->tso_hdrs_dma) && \ 313 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 314 315 static int mii_cnt; 316 317 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 318 struct bufdesc_prop *bd) 319 { 320 return (bdp >= bd->last) ? bd->base 321 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 322 } 323 324 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 325 struct bufdesc_prop *bd) 326 { 327 return (bdp <= bd->base) ? bd->last 328 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 329 } 330 331 static int fec_enet_get_bd_index(struct bufdesc *bdp, 332 struct bufdesc_prop *bd) 333 { 334 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 335 } 336 337 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 338 { 339 int entries; 340 341 entries = (((const char *)txq->dirty_tx - 342 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 343 344 return entries >= 0 ? entries : entries + txq->bd.ring_size; 345 } 346 347 static void swap_buffer(void *bufaddr, int len) 348 { 349 int i; 350 unsigned int *buf = bufaddr; 351 352 for (i = 0; i < len; i += 4, buf++) 353 swab32s(buf); 354 } 355 356 static void fec_dump(struct net_device *ndev) 357 { 358 struct fec_enet_private *fep = netdev_priv(ndev); 359 struct bufdesc *bdp; 360 struct fec_enet_priv_tx_q *txq; 361 int index = 0; 362 363 netdev_info(ndev, "TX ring dump\n"); 364 pr_info("Nr SC addr len SKB\n"); 365 366 txq = fep->tx_queue[0]; 367 bdp = txq->bd.base; 368 369 do { 370 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 371 index, 372 bdp == txq->bd.cur ? 'S' : ' ', 373 bdp == txq->dirty_tx ? 'H' : ' ', 374 fec16_to_cpu(bdp->cbd_sc), 375 fec32_to_cpu(bdp->cbd_bufaddr), 376 fec16_to_cpu(bdp->cbd_datlen), 377 txq->tx_buf[index].buf_p); 378 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 379 index++; 380 } while (bdp != txq->bd.base); 381 } 382 383 /* 384 * Coldfire does not support DMA coherent allocations, and has historically used 385 * a band-aid with a manual flush in fec_enet_rx_queue. 386 */ 387 #if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA) 388 static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, 389 gfp_t gfp) 390 { 391 return dma_alloc_noncoherent(dev, size, handle, DMA_BIDIRECTIONAL, gfp); 392 } 393 394 static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr, 395 dma_addr_t handle) 396 { 397 dma_free_noncoherent(dev, size, cpu_addr, handle, DMA_BIDIRECTIONAL); 398 } 399 #else /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */ 400 static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, 401 gfp_t gfp) 402 { 403 return dma_alloc_coherent(dev, size, handle, gfp); 404 } 405 406 static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr, 407 dma_addr_t handle) 408 { 409 dma_free_coherent(dev, size, cpu_addr, handle); 410 } 411 #endif /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */ 412 413 struct fec_dma_devres { 414 size_t size; 415 void *vaddr; 416 dma_addr_t dma_handle; 417 }; 418 419 static void fec_dmam_release(struct device *dev, void *res) 420 { 421 struct fec_dma_devres *this = res; 422 423 fec_dma_free(dev, this->size, this->vaddr, this->dma_handle); 424 } 425 426 static void *fec_dmam_alloc(struct device *dev, size_t size, dma_addr_t *handle, 427 gfp_t gfp) 428 { 429 struct fec_dma_devres *dr; 430 void *vaddr; 431 432 dr = devres_alloc(fec_dmam_release, sizeof(*dr), gfp); 433 if (!dr) 434 return NULL; 435 vaddr = fec_dma_alloc(dev, size, handle, gfp); 436 if (!vaddr) { 437 devres_free(dr); 438 return NULL; 439 } 440 dr->vaddr = vaddr; 441 dr->dma_handle = *handle; 442 dr->size = size; 443 devres_add(dev, dr); 444 return vaddr; 445 } 446 447 static inline bool is_ipv4_pkt(struct sk_buff *skb) 448 { 449 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 450 } 451 452 static int 453 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 454 { 455 /* Only run for packets requiring a checksum. */ 456 if (skb->ip_summed != CHECKSUM_PARTIAL) 457 return 0; 458 459 if (unlikely(skb_cow_head(skb, 0))) 460 return -1; 461 462 if (is_ipv4_pkt(skb)) 463 ip_hdr(skb)->check = 0; 464 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 465 466 return 0; 467 } 468 469 static int 470 fec_enet_create_page_pool(struct fec_enet_private *fep, 471 struct fec_enet_priv_rx_q *rxq, int size) 472 { 473 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 474 struct page_pool_params pp_params = { 475 .order = fep->pagepool_order, 476 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 477 .pool_size = size, 478 .nid = dev_to_node(&fep->pdev->dev), 479 .dev = &fep->pdev->dev, 480 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 481 .offset = FEC_ENET_XDP_HEADROOM, 482 .max_len = fep->rx_frame_size, 483 }; 484 int err; 485 486 rxq->page_pool = page_pool_create(&pp_params); 487 if (IS_ERR(rxq->page_pool)) { 488 err = PTR_ERR(rxq->page_pool); 489 rxq->page_pool = NULL; 490 return err; 491 } 492 493 err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0); 494 if (err < 0) 495 goto err_free_pp; 496 497 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 498 rxq->page_pool); 499 if (err) 500 goto err_unregister_rxq; 501 502 return 0; 503 504 err_unregister_rxq: 505 xdp_rxq_info_unreg(&rxq->xdp_rxq); 506 err_free_pp: 507 page_pool_destroy(rxq->page_pool); 508 rxq->page_pool = NULL; 509 return err; 510 } 511 512 static struct bufdesc * 513 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 514 struct sk_buff *skb, 515 struct net_device *ndev) 516 { 517 struct fec_enet_private *fep = netdev_priv(ndev); 518 struct bufdesc *bdp = txq->bd.cur; 519 struct bufdesc_ex *ebdp; 520 int nr_frags = skb_shinfo(skb)->nr_frags; 521 int frag, frag_len; 522 unsigned short status; 523 unsigned int estatus = 0; 524 skb_frag_t *this_frag; 525 unsigned int index; 526 void *bufaddr; 527 dma_addr_t addr; 528 int i; 529 530 for (frag = 0; frag < nr_frags; frag++) { 531 this_frag = &skb_shinfo(skb)->frags[frag]; 532 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 533 ebdp = (struct bufdesc_ex *)bdp; 534 535 status = fec16_to_cpu(bdp->cbd_sc); 536 status &= ~BD_ENET_TX_STATS; 537 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 538 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 539 540 /* Handle the last BD specially */ 541 if (frag == nr_frags - 1) { 542 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 543 if (fep->bufdesc_ex) { 544 estatus |= BD_ENET_TX_INT; 545 if (unlikely(skb_shinfo(skb)->tx_flags & 546 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 547 estatus |= BD_ENET_TX_TS; 548 } 549 } 550 551 if (fep->bufdesc_ex) { 552 if (fep->quirks & FEC_QUIRK_HAS_AVB) 553 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 554 if (skb->ip_summed == CHECKSUM_PARTIAL) 555 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 556 557 ebdp->cbd_bdu = 0; 558 ebdp->cbd_esc = cpu_to_fec32(estatus); 559 } 560 561 bufaddr = skb_frag_address(this_frag); 562 563 index = fec_enet_get_bd_index(bdp, &txq->bd); 564 if (((unsigned long) bufaddr) & fep->tx_align || 565 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 566 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 567 bufaddr = txq->tx_bounce[index]; 568 569 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 570 swap_buffer(bufaddr, frag_len); 571 } 572 573 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 574 DMA_TO_DEVICE); 575 if (dma_mapping_error(&fep->pdev->dev, addr)) { 576 if (net_ratelimit()) 577 netdev_err(ndev, "Tx DMA memory map failed\n"); 578 goto dma_mapping_error; 579 } 580 581 bdp->cbd_bufaddr = cpu_to_fec32(addr); 582 bdp->cbd_datlen = cpu_to_fec16(frag_len); 583 /* Make sure the updates to rest of the descriptor are 584 * performed before transferring ownership. 585 */ 586 wmb(); 587 bdp->cbd_sc = cpu_to_fec16(status); 588 } 589 590 return bdp; 591 dma_mapping_error: 592 bdp = txq->bd.cur; 593 for (i = 0; i < frag; i++) { 594 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 595 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 596 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 597 } 598 return ERR_PTR(-ENOMEM); 599 } 600 601 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 602 struct sk_buff *skb, struct net_device *ndev) 603 { 604 struct fec_enet_private *fep = netdev_priv(ndev); 605 int nr_frags = skb_shinfo(skb)->nr_frags; 606 struct bufdesc *bdp, *last_bdp; 607 void *bufaddr; 608 dma_addr_t addr; 609 unsigned short status; 610 unsigned short buflen; 611 unsigned int estatus = 0; 612 unsigned int index; 613 int entries_free; 614 615 entries_free = fec_enet_get_free_txdesc_num(txq); 616 if (entries_free < MAX_SKB_FRAGS + 1) { 617 dev_kfree_skb_any(skb); 618 if (net_ratelimit()) 619 netdev_err(ndev, "NOT enough BD for SG!\n"); 620 return NETDEV_TX_OK; 621 } 622 623 /* Protocol checksum off-load for TCP and UDP. */ 624 if (fec_enet_clear_csum(skb, ndev)) { 625 dev_kfree_skb_any(skb); 626 return NETDEV_TX_OK; 627 } 628 629 /* Fill in a Tx ring entry */ 630 bdp = txq->bd.cur; 631 last_bdp = bdp; 632 status = fec16_to_cpu(bdp->cbd_sc); 633 status &= ~BD_ENET_TX_STATS; 634 635 /* Set buffer length and buffer pointer */ 636 bufaddr = skb->data; 637 buflen = skb_headlen(skb); 638 639 index = fec_enet_get_bd_index(bdp, &txq->bd); 640 if (((unsigned long) bufaddr) & fep->tx_align || 641 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 642 memcpy(txq->tx_bounce[index], skb->data, buflen); 643 bufaddr = txq->tx_bounce[index]; 644 645 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 646 swap_buffer(bufaddr, buflen); 647 } 648 649 /* Push the data cache so the CPM does not get stale memory data. */ 650 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 651 if (dma_mapping_error(&fep->pdev->dev, addr)) { 652 dev_kfree_skb_any(skb); 653 if (net_ratelimit()) 654 netdev_err(ndev, "Tx DMA memory map failed\n"); 655 return NETDEV_TX_OK; 656 } 657 658 if (nr_frags) { 659 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 660 if (IS_ERR(last_bdp)) { 661 dma_unmap_single(&fep->pdev->dev, addr, 662 buflen, DMA_TO_DEVICE); 663 dev_kfree_skb_any(skb); 664 return NETDEV_TX_OK; 665 } 666 } else { 667 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 668 if (fep->bufdesc_ex) { 669 estatus = BD_ENET_TX_INT; 670 if (unlikely(skb_shinfo(skb)->tx_flags & 671 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 672 estatus |= BD_ENET_TX_TS; 673 } 674 } 675 bdp->cbd_bufaddr = cpu_to_fec32(addr); 676 bdp->cbd_datlen = cpu_to_fec16(buflen); 677 678 if (fep->bufdesc_ex) { 679 680 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 681 682 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 683 fep->hwts_tx_en)) 684 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 685 686 if (fep->quirks & FEC_QUIRK_HAS_AVB) 687 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 688 689 if (skb->ip_summed == CHECKSUM_PARTIAL) 690 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 691 692 ebdp->cbd_bdu = 0; 693 ebdp->cbd_esc = cpu_to_fec32(estatus); 694 } 695 696 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 697 /* Save skb pointer */ 698 txq->tx_buf[index].buf_p = skb; 699 700 /* Make sure the updates to rest of the descriptor are performed before 701 * transferring ownership. 702 */ 703 wmb(); 704 705 /* Send it on its way. Tell FEC it's ready, interrupt when done, 706 * it's the last BD of the frame, and to put the CRC on the end. 707 */ 708 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 709 bdp->cbd_sc = cpu_to_fec16(status); 710 711 /* If this was the last BD in the ring, start at the beginning again. */ 712 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 713 714 skb_tx_timestamp(skb); 715 716 /* Make sure the update to bdp is performed before txq->bd.cur. */ 717 wmb(); 718 txq->bd.cur = bdp; 719 720 /* Trigger transmission start */ 721 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 722 !readl(txq->bd.reg_desc_active) || 723 !readl(txq->bd.reg_desc_active) || 724 !readl(txq->bd.reg_desc_active) || 725 !readl(txq->bd.reg_desc_active)) 726 writel(0, txq->bd.reg_desc_active); 727 728 return 0; 729 } 730 731 static int 732 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 733 struct net_device *ndev, 734 struct bufdesc *bdp, int index, char *data, 735 int size, bool last_tcp, bool is_last) 736 { 737 struct fec_enet_private *fep = netdev_priv(ndev); 738 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 739 unsigned short status; 740 unsigned int estatus = 0; 741 dma_addr_t addr; 742 743 status = fec16_to_cpu(bdp->cbd_sc); 744 status &= ~BD_ENET_TX_STATS; 745 746 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 747 748 if (((unsigned long) data) & fep->tx_align || 749 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 750 memcpy(txq->tx_bounce[index], data, size); 751 data = txq->tx_bounce[index]; 752 753 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 754 swap_buffer(data, size); 755 } 756 757 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 758 if (dma_mapping_error(&fep->pdev->dev, addr)) { 759 dev_kfree_skb_any(skb); 760 if (net_ratelimit()) 761 netdev_err(ndev, "Tx DMA memory map failed\n"); 762 return NETDEV_TX_OK; 763 } 764 765 bdp->cbd_datlen = cpu_to_fec16(size); 766 bdp->cbd_bufaddr = cpu_to_fec32(addr); 767 768 if (fep->bufdesc_ex) { 769 if (fep->quirks & FEC_QUIRK_HAS_AVB) 770 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 771 if (skb->ip_summed == CHECKSUM_PARTIAL) 772 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 773 ebdp->cbd_bdu = 0; 774 ebdp->cbd_esc = cpu_to_fec32(estatus); 775 } 776 777 /* Handle the last BD specially */ 778 if (last_tcp) 779 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 780 if (is_last) { 781 status |= BD_ENET_TX_INTR; 782 if (fep->bufdesc_ex) 783 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 784 } 785 786 bdp->cbd_sc = cpu_to_fec16(status); 787 788 return 0; 789 } 790 791 static int 792 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 793 struct sk_buff *skb, struct net_device *ndev, 794 struct bufdesc *bdp, int index) 795 { 796 struct fec_enet_private *fep = netdev_priv(ndev); 797 int hdr_len = skb_tcp_all_headers(skb); 798 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 799 void *bufaddr; 800 unsigned long dmabuf; 801 unsigned short status; 802 unsigned int estatus = 0; 803 804 status = fec16_to_cpu(bdp->cbd_sc); 805 status &= ~BD_ENET_TX_STATS; 806 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 807 808 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 809 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 810 if (((unsigned long)bufaddr) & fep->tx_align || 811 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 812 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 813 bufaddr = txq->tx_bounce[index]; 814 815 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 816 swap_buffer(bufaddr, hdr_len); 817 818 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 819 hdr_len, DMA_TO_DEVICE); 820 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 821 dev_kfree_skb_any(skb); 822 if (net_ratelimit()) 823 netdev_err(ndev, "Tx DMA memory map failed\n"); 824 return NETDEV_TX_OK; 825 } 826 } 827 828 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 829 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 830 831 if (fep->bufdesc_ex) { 832 if (fep->quirks & FEC_QUIRK_HAS_AVB) 833 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 834 if (skb->ip_summed == CHECKSUM_PARTIAL) 835 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 836 ebdp->cbd_bdu = 0; 837 ebdp->cbd_esc = cpu_to_fec32(estatus); 838 } 839 840 bdp->cbd_sc = cpu_to_fec16(status); 841 842 return 0; 843 } 844 845 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 846 struct sk_buff *skb, 847 struct net_device *ndev) 848 { 849 struct fec_enet_private *fep = netdev_priv(ndev); 850 int hdr_len, total_len, data_left; 851 struct bufdesc *bdp = txq->bd.cur; 852 struct bufdesc *tmp_bdp; 853 struct bufdesc_ex *ebdp; 854 struct tso_t tso; 855 unsigned int index = 0; 856 int ret; 857 858 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 859 dev_kfree_skb_any(skb); 860 if (net_ratelimit()) 861 netdev_err(ndev, "NOT enough BD for TSO!\n"); 862 return NETDEV_TX_OK; 863 } 864 865 /* Protocol checksum off-load for TCP and UDP. */ 866 if (fec_enet_clear_csum(skb, ndev)) { 867 dev_kfree_skb_any(skb); 868 return NETDEV_TX_OK; 869 } 870 871 /* Initialize the TSO handler, and prepare the first payload */ 872 hdr_len = tso_start(skb, &tso); 873 874 total_len = skb->len - hdr_len; 875 while (total_len > 0) { 876 char *hdr; 877 878 index = fec_enet_get_bd_index(bdp, &txq->bd); 879 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 880 total_len -= data_left; 881 882 /* prepare packet headers: MAC + IP + TCP */ 883 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 884 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 885 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 886 if (ret) 887 goto err_release; 888 889 while (data_left > 0) { 890 int size; 891 892 size = min_t(int, tso.size, data_left); 893 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 894 index = fec_enet_get_bd_index(bdp, &txq->bd); 895 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 896 bdp, index, 897 tso.data, size, 898 size == data_left, 899 total_len == 0); 900 if (ret) 901 goto err_release; 902 903 data_left -= size; 904 tso_build_data(skb, &tso, size); 905 } 906 907 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 908 } 909 910 /* Save skb pointer */ 911 txq->tx_buf[index].buf_p = skb; 912 913 skb_tx_timestamp(skb); 914 txq->bd.cur = bdp; 915 916 /* Trigger transmission start */ 917 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 918 !readl(txq->bd.reg_desc_active) || 919 !readl(txq->bd.reg_desc_active) || 920 !readl(txq->bd.reg_desc_active) || 921 !readl(txq->bd.reg_desc_active)) 922 writel(0, txq->bd.reg_desc_active); 923 924 return 0; 925 926 err_release: 927 /* Release all used data descriptors for TSO */ 928 tmp_bdp = txq->bd.cur; 929 930 while (tmp_bdp != bdp) { 931 /* Unmap data buffers */ 932 if (tmp_bdp->cbd_bufaddr && 933 !IS_TSO_HEADER(txq, fec32_to_cpu(tmp_bdp->cbd_bufaddr))) 934 dma_unmap_single(&fep->pdev->dev, 935 fec32_to_cpu(tmp_bdp->cbd_bufaddr), 936 fec16_to_cpu(tmp_bdp->cbd_datlen), 937 DMA_TO_DEVICE); 938 939 /* Clear standard buffer descriptor fields */ 940 tmp_bdp->cbd_sc = 0; 941 tmp_bdp->cbd_datlen = 0; 942 tmp_bdp->cbd_bufaddr = 0; 943 944 /* Handle extended descriptor if enabled */ 945 if (fep->bufdesc_ex) { 946 ebdp = (struct bufdesc_ex *)tmp_bdp; 947 ebdp->cbd_esc = 0; 948 } 949 950 tmp_bdp = fec_enet_get_nextdesc(tmp_bdp, &txq->bd); 951 } 952 953 dev_kfree_skb_any(skb); 954 955 return ret; 956 } 957 958 static netdev_tx_t 959 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 960 { 961 struct fec_enet_private *fep = netdev_priv(ndev); 962 int entries_free; 963 unsigned short queue; 964 struct fec_enet_priv_tx_q *txq; 965 struct netdev_queue *nq; 966 int ret; 967 968 queue = skb_get_queue_mapping(skb); 969 txq = fep->tx_queue[queue]; 970 nq = netdev_get_tx_queue(ndev, queue); 971 972 if (skb_is_gso(skb)) 973 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 974 else 975 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 976 if (ret) 977 return ret; 978 979 entries_free = fec_enet_get_free_txdesc_num(txq); 980 if (entries_free <= txq->tx_stop_threshold) 981 netif_tx_stop_queue(nq); 982 983 return NETDEV_TX_OK; 984 } 985 986 /* Init RX & TX buffer descriptors 987 */ 988 static void fec_enet_bd_init(struct net_device *dev) 989 { 990 struct fec_enet_private *fep = netdev_priv(dev); 991 struct fec_enet_priv_tx_q *txq; 992 struct fec_enet_priv_rx_q *rxq; 993 struct bufdesc *bdp; 994 unsigned int i; 995 unsigned int q; 996 997 for (q = 0; q < fep->num_rx_queues; q++) { 998 /* Initialize the receive buffer descriptors. */ 999 rxq = fep->rx_queue[q]; 1000 bdp = rxq->bd.base; 1001 1002 for (i = 0; i < rxq->bd.ring_size; i++) { 1003 1004 /* Initialize the BD for every fragment in the page. */ 1005 if (bdp->cbd_bufaddr) 1006 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 1007 else 1008 bdp->cbd_sc = cpu_to_fec16(0); 1009 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1010 } 1011 1012 /* Set the last buffer to wrap */ 1013 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 1014 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 1015 1016 rxq->bd.cur = rxq->bd.base; 1017 } 1018 1019 for (q = 0; q < fep->num_tx_queues; q++) { 1020 /* ...and the same for transmit */ 1021 txq = fep->tx_queue[q]; 1022 bdp = txq->bd.base; 1023 txq->bd.cur = bdp; 1024 1025 for (i = 0; i < txq->bd.ring_size; i++) { 1026 /* Initialize the BD for every fragment in the page. */ 1027 bdp->cbd_sc = cpu_to_fec16(0); 1028 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 1029 if (bdp->cbd_bufaddr && 1030 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1031 dma_unmap_single(&fep->pdev->dev, 1032 fec32_to_cpu(bdp->cbd_bufaddr), 1033 fec16_to_cpu(bdp->cbd_datlen), 1034 DMA_TO_DEVICE); 1035 if (txq->tx_buf[i].buf_p) 1036 dev_kfree_skb_any(txq->tx_buf[i].buf_p); 1037 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 1038 if (bdp->cbd_bufaddr) 1039 dma_unmap_single(&fep->pdev->dev, 1040 fec32_to_cpu(bdp->cbd_bufaddr), 1041 fec16_to_cpu(bdp->cbd_datlen), 1042 DMA_TO_DEVICE); 1043 1044 if (txq->tx_buf[i].buf_p) 1045 xdp_return_frame(txq->tx_buf[i].buf_p); 1046 } else { 1047 struct page *page = txq->tx_buf[i].buf_p; 1048 1049 if (page) 1050 page_pool_put_page(pp_page_to_nmdesc(page)->pp, 1051 page, 0, 1052 false); 1053 } 1054 1055 txq->tx_buf[i].buf_p = NULL; 1056 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1057 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 1058 bdp->cbd_bufaddr = cpu_to_fec32(0); 1059 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1060 } 1061 1062 /* Set the last buffer to wrap */ 1063 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 1064 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 1065 txq->dirty_tx = bdp; 1066 } 1067 } 1068 1069 static void fec_enet_active_rxring(struct net_device *ndev) 1070 { 1071 struct fec_enet_private *fep = netdev_priv(ndev); 1072 int i; 1073 1074 for (i = 0; i < fep->num_rx_queues; i++) 1075 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 1076 } 1077 1078 static void fec_enet_enable_ring(struct net_device *ndev) 1079 { 1080 struct fec_enet_private *fep = netdev_priv(ndev); 1081 struct fec_enet_priv_tx_q *txq; 1082 struct fec_enet_priv_rx_q *rxq; 1083 int i; 1084 1085 for (i = 0; i < fep->num_rx_queues; i++) { 1086 rxq = fep->rx_queue[i]; 1087 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 1088 writel(fep->max_buf_size, fep->hwp + FEC_R_BUFF_SIZE(i)); 1089 1090 /* enable DMA1/2 */ 1091 if (i) 1092 writel(RCMR_MATCHEN | RCMR_CMP(i), 1093 fep->hwp + FEC_RCMR(i)); 1094 } 1095 1096 for (i = 0; i < fep->num_tx_queues; i++) { 1097 txq = fep->tx_queue[i]; 1098 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 1099 1100 /* enable DMA1/2 */ 1101 if (i) 1102 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 1103 fep->hwp + FEC_DMA_CFG(i)); 1104 } 1105 } 1106 1107 /* Whack a reset. We should wait for this. 1108 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1109 * instead of reset MAC itself. 1110 */ 1111 static void fec_ctrl_reset(struct fec_enet_private *fep, bool allow_wol) 1112 { 1113 u32 val; 1114 1115 if (!allow_wol || !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1116 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || 1117 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 1118 writel(0, fep->hwp + FEC_ECNTRL); 1119 } else { 1120 writel(FEC_ECR_RESET, fep->hwp + FEC_ECNTRL); 1121 udelay(10); 1122 } 1123 } else { 1124 val = readl(fep->hwp + FEC_ECNTRL); 1125 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1126 writel(val, fep->hwp + FEC_ECNTRL); 1127 } 1128 } 1129 1130 static void fec_set_hw_mac_addr(struct net_device *ndev) 1131 { 1132 struct fec_enet_private *fep = netdev_priv(ndev); 1133 1134 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 1135 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 1136 fep->hwp + FEC_ADDR_LOW); 1137 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 1138 fep->hwp + FEC_ADDR_HIGH); 1139 } 1140 1141 /* 1142 * This function is called to start or restart the FEC during a link 1143 * change, transmit timeout, or to reconfigure the FEC. The network 1144 * packet processing for this device must be stopped before this call. 1145 */ 1146 static void 1147 fec_restart(struct net_device *ndev) 1148 { 1149 struct fec_enet_private *fep = netdev_priv(ndev); 1150 u32 ecntl = FEC_ECR_ETHEREN; 1151 u32 rcntl = FEC_RCR_MII; 1152 1153 if (OPT_ARCH_HAS_MAX_FL) 1154 rcntl |= (fep->netdev->mtu + ETH_HLEN + ETH_FCS_LEN) << 16; 1155 1156 if (fep->bufdesc_ex) 1157 fec_ptp_save_state(fep); 1158 1159 fec_ctrl_reset(fep, false); 1160 1161 /* 1162 * enet-mac reset will reset mac address registers too, 1163 * so need to reconfigure it. 1164 */ 1165 fec_set_hw_mac_addr(ndev); 1166 1167 /* Clear any outstanding interrupt, except MDIO. */ 1168 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 1169 1170 fec_enet_bd_init(ndev); 1171 1172 fec_enet_enable_ring(ndev); 1173 1174 /* Enable MII mode */ 1175 if (fep->full_duplex == DUPLEX_FULL) { 1176 /* FD enable */ 1177 writel(0x04, fep->hwp + FEC_X_CNTRL); 1178 } else { 1179 /* No Rcv on Xmit */ 1180 rcntl |= FEC_RCR_DRT; 1181 writel(0x0, fep->hwp + FEC_X_CNTRL); 1182 } 1183 1184 /* Set MII speed */ 1185 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1186 1187 #if !defined(CONFIG_M5272) 1188 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1189 u32 val = readl(fep->hwp + FEC_RACC); 1190 1191 /* align IP header */ 1192 val |= FEC_RACC_SHIFT16; 1193 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1194 /* set RX checksum */ 1195 val |= FEC_RACC_OPTIONS; 1196 else 1197 val &= ~FEC_RACC_OPTIONS; 1198 writel(val, fep->hwp + FEC_RACC); 1199 writel(min(fep->rx_frame_size, fep->max_buf_size), fep->hwp + FEC_FTRL); 1200 } 1201 #endif 1202 1203 /* 1204 * The phy interface and speed need to get configured 1205 * differently on enet-mac. 1206 */ 1207 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1208 /* Enable flow control and length check */ 1209 rcntl |= FEC_RCR_NLC | FEC_RCR_FLOWCTL; 1210 1211 /* RGMII, RMII or MII */ 1212 if (phy_interface_mode_is_rgmii(fep->phy_interface)) 1213 rcntl |= FEC_RCR_RGMII; 1214 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1215 rcntl |= FEC_RCR_RMII; 1216 else 1217 rcntl &= ~FEC_RCR_RMII; 1218 1219 /* 1G, 100M or 10M */ 1220 if (ndev->phydev) { 1221 if (ndev->phydev->speed == SPEED_1000) 1222 ecntl |= FEC_ECR_SPEED; 1223 else if (ndev->phydev->speed == SPEED_100) 1224 rcntl &= ~FEC_RCR_10BASET; 1225 else 1226 rcntl |= FEC_RCR_10BASET; 1227 } 1228 } else { 1229 #ifdef FEC_MIIGSK_ENR 1230 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1231 u32 cfgr; 1232 /* disable the gasket and wait */ 1233 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1234 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1235 udelay(1); 1236 1237 /* 1238 * configure the gasket: 1239 * RMII, 50 MHz, no loopback, no echo 1240 * MII, 25 MHz, no loopback, no echo 1241 */ 1242 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1243 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1244 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1245 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1246 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1247 1248 /* re-enable the gasket */ 1249 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1250 } 1251 #endif 1252 } 1253 1254 #if !defined(CONFIG_M5272) 1255 /* enable pause frame*/ 1256 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1257 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1258 ndev->phydev && ndev->phydev->pause)) { 1259 rcntl |= FEC_RCR_FLOWCTL; 1260 1261 /* set FIFO threshold parameter to reduce overrun */ 1262 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1263 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1264 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1265 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1266 1267 /* OPD */ 1268 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1269 } else { 1270 rcntl &= ~FEC_RCR_FLOWCTL; 1271 } 1272 #endif /* !defined(CONFIG_M5272) */ 1273 1274 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1275 1276 /* Setup multicast filter. */ 1277 set_multicast_list(ndev); 1278 #ifndef CONFIG_M5272 1279 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1280 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1281 #endif 1282 1283 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1284 /* enable ENET endian swap */ 1285 ecntl |= FEC_ECR_BYTESWP; 1286 1287 /* When Jumbo Frame is enabled, the FIFO may not be large enough 1288 * to hold an entire frame. In such cases, if the MTU exceeds 1289 * (PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN), configure the interface 1290 * to operate in cut-through mode, triggered by the FIFO threshold. 1291 * Otherwise, enable the ENET store-and-forward mode. 1292 */ 1293 if ((fep->quirks & FEC_QUIRK_JUMBO_FRAME) && 1294 (ndev->mtu > (PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN))) 1295 writel(0xF, fep->hwp + FEC_X_WMRK); 1296 else 1297 writel(FEC_TXWMRK_STRFWD, fep->hwp + FEC_X_WMRK); 1298 } 1299 1300 if (fep->bufdesc_ex) 1301 ecntl |= FEC_ECR_EN1588; 1302 1303 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1304 fep->rgmii_txc_dly) 1305 ecntl |= FEC_ENET_TXC_DLY; 1306 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1307 fep->rgmii_rxc_dly) 1308 ecntl |= FEC_ENET_RXC_DLY; 1309 1310 #ifndef CONFIG_M5272 1311 /* Enable the MIB statistic event counters */ 1312 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1313 #endif 1314 1315 /* And last, enable the transmit and receive processing */ 1316 writel(ecntl, fep->hwp + FEC_ECNTRL); 1317 fec_enet_active_rxring(ndev); 1318 1319 if (fep->bufdesc_ex) { 1320 fec_ptp_start_cyclecounter(ndev); 1321 fec_ptp_restore_state(fep); 1322 } 1323 1324 /* Enable interrupts we wish to service */ 1325 if (fep->link) 1326 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1327 else 1328 writel(0, fep->hwp + FEC_IMASK); 1329 1330 /* Init the interrupt coalescing */ 1331 if (fep->quirks & FEC_QUIRK_HAS_COALESCE) 1332 fec_enet_itr_coal_set(ndev); 1333 } 1334 1335 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep) 1336 { 1337 if (!(of_machine_is_compatible("fsl,imx8qm") || 1338 of_machine_is_compatible("fsl,imx8qxp") || 1339 of_machine_is_compatible("fsl,imx8dxl"))) 1340 return 0; 1341 1342 return imx_scu_get_handle(&fep->ipc_handle); 1343 } 1344 1345 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled) 1346 { 1347 struct device_node *np = fep->pdev->dev.of_node; 1348 u32 rsrc_id, val; 1349 int idx; 1350 1351 if (!np || !fep->ipc_handle) 1352 return; 1353 1354 idx = of_alias_get_id(np, "ethernet"); 1355 if (idx < 0) 1356 idx = 0; 1357 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0; 1358 1359 val = enabled ? 1 : 0; 1360 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val); 1361 } 1362 1363 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1364 { 1365 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1366 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1367 1368 if (stop_gpr->gpr) { 1369 if (enabled) 1370 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1371 BIT(stop_gpr->bit), 1372 BIT(stop_gpr->bit)); 1373 else 1374 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1375 BIT(stop_gpr->bit), 0); 1376 } else if (pdata && pdata->sleep_mode_enable) { 1377 pdata->sleep_mode_enable(enabled); 1378 } else { 1379 fec_enet_ipg_stop_set(fep, enabled); 1380 } 1381 } 1382 1383 static void fec_irqs_disable(struct net_device *ndev) 1384 { 1385 struct fec_enet_private *fep = netdev_priv(ndev); 1386 1387 writel(0, fep->hwp + FEC_IMASK); 1388 } 1389 1390 static void fec_irqs_disable_except_wakeup(struct net_device *ndev) 1391 { 1392 struct fec_enet_private *fep = netdev_priv(ndev); 1393 1394 writel(0, fep->hwp + FEC_IMASK); 1395 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1396 } 1397 1398 static void 1399 fec_stop(struct net_device *ndev) 1400 { 1401 struct fec_enet_private *fep = netdev_priv(ndev); 1402 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & FEC_RCR_RMII; 1403 u32 val; 1404 1405 /* We cannot expect a graceful transmit stop without link !!! */ 1406 if (fep->link) { 1407 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1408 udelay(10); 1409 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1410 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1411 } 1412 1413 if (fep->bufdesc_ex) 1414 fec_ptp_save_state(fep); 1415 1416 fec_ctrl_reset(fep, true); 1417 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1418 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1419 1420 /* We have to keep ENET enabled to have MII interrupt stay working */ 1421 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1422 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1423 writel(FEC_ECR_ETHEREN, fep->hwp + FEC_ECNTRL); 1424 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1425 } 1426 1427 if (fep->bufdesc_ex) { 1428 val = readl(fep->hwp + FEC_ECNTRL); 1429 val |= FEC_ECR_EN1588; 1430 writel(val, fep->hwp + FEC_ECNTRL); 1431 1432 fec_ptp_start_cyclecounter(ndev); 1433 fec_ptp_restore_state(fep); 1434 } 1435 } 1436 1437 static void 1438 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1439 { 1440 struct fec_enet_private *fep = netdev_priv(ndev); 1441 1442 fec_dump(ndev); 1443 1444 ndev->stats.tx_errors++; 1445 1446 schedule_work(&fep->tx_timeout_work); 1447 } 1448 1449 static void fec_enet_timeout_work(struct work_struct *work) 1450 { 1451 struct fec_enet_private *fep = 1452 container_of(work, struct fec_enet_private, tx_timeout_work); 1453 struct net_device *ndev = fep->netdev; 1454 1455 rtnl_lock(); 1456 if (netif_device_present(ndev) || netif_running(ndev)) { 1457 napi_disable(&fep->napi); 1458 netif_tx_lock_bh(ndev); 1459 fec_restart(ndev); 1460 netif_tx_wake_all_queues(ndev); 1461 netif_tx_unlock_bh(ndev); 1462 napi_enable(&fep->napi); 1463 } 1464 rtnl_unlock(); 1465 } 1466 1467 static void 1468 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1469 struct skb_shared_hwtstamps *hwtstamps) 1470 { 1471 unsigned long flags; 1472 u64 ns; 1473 1474 spin_lock_irqsave(&fep->tmreg_lock, flags); 1475 ns = timecounter_cyc2time(&fep->tc, ts); 1476 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1477 1478 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1479 hwtstamps->hwtstamp = ns_to_ktime(ns); 1480 } 1481 1482 static void 1483 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id, int budget) 1484 { 1485 struct fec_enet_private *fep; 1486 struct xdp_frame *xdpf; 1487 struct bufdesc *bdp; 1488 unsigned short status; 1489 struct sk_buff *skb; 1490 struct fec_enet_priv_tx_q *txq; 1491 struct netdev_queue *nq; 1492 int index = 0; 1493 int entries_free; 1494 struct page *page; 1495 int frame_len; 1496 1497 fep = netdev_priv(ndev); 1498 1499 txq = fep->tx_queue[queue_id]; 1500 /* get next bdp of dirty_tx */ 1501 nq = netdev_get_tx_queue(ndev, queue_id); 1502 bdp = txq->dirty_tx; 1503 1504 /* get next bdp of dirty_tx */ 1505 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1506 1507 while (bdp != READ_ONCE(txq->bd.cur)) { 1508 /* Order the load of bd.cur and cbd_sc */ 1509 rmb(); 1510 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1511 if (status & BD_ENET_TX_READY) 1512 break; 1513 1514 index = fec_enet_get_bd_index(bdp, &txq->bd); 1515 1516 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1517 skb = txq->tx_buf[index].buf_p; 1518 if (bdp->cbd_bufaddr && 1519 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1520 dma_unmap_single(&fep->pdev->dev, 1521 fec32_to_cpu(bdp->cbd_bufaddr), 1522 fec16_to_cpu(bdp->cbd_datlen), 1523 DMA_TO_DEVICE); 1524 bdp->cbd_bufaddr = cpu_to_fec32(0); 1525 if (!skb) 1526 goto tx_buf_done; 1527 } else { 1528 /* Tx processing cannot call any XDP (or page pool) APIs if 1529 * the "budget" is 0. Because NAPI is called with budget of 1530 * 0 (such as netpoll) indicates we may be in an IRQ context, 1531 * however, we can't use the page pool from IRQ context. 1532 */ 1533 if (unlikely(!budget)) 1534 break; 1535 1536 if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1537 xdpf = txq->tx_buf[index].buf_p; 1538 if (bdp->cbd_bufaddr) 1539 dma_unmap_single(&fep->pdev->dev, 1540 fec32_to_cpu(bdp->cbd_bufaddr), 1541 fec16_to_cpu(bdp->cbd_datlen), 1542 DMA_TO_DEVICE); 1543 } else { 1544 page = txq->tx_buf[index].buf_p; 1545 } 1546 1547 bdp->cbd_bufaddr = cpu_to_fec32(0); 1548 if (unlikely(!txq->tx_buf[index].buf_p)) { 1549 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1550 goto tx_buf_done; 1551 } 1552 1553 frame_len = fec16_to_cpu(bdp->cbd_datlen); 1554 } 1555 1556 /* Check for errors. */ 1557 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1558 BD_ENET_TX_RL | BD_ENET_TX_UN | 1559 BD_ENET_TX_CSL)) { 1560 ndev->stats.tx_errors++; 1561 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1562 ndev->stats.tx_heartbeat_errors++; 1563 if (status & BD_ENET_TX_LC) /* Late collision */ 1564 ndev->stats.tx_window_errors++; 1565 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1566 ndev->stats.tx_aborted_errors++; 1567 if (status & BD_ENET_TX_UN) /* Underrun */ 1568 ndev->stats.tx_fifo_errors++; 1569 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1570 ndev->stats.tx_carrier_errors++; 1571 } else { 1572 ndev->stats.tx_packets++; 1573 1574 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) 1575 ndev->stats.tx_bytes += skb->len; 1576 else 1577 ndev->stats.tx_bytes += frame_len; 1578 } 1579 1580 /* Deferred means some collisions occurred during transmit, 1581 * but we eventually sent the packet OK. 1582 */ 1583 if (status & BD_ENET_TX_DEF) 1584 ndev->stats.collisions++; 1585 1586 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1587 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1588 * are to time stamp the packet, so we still need to check time 1589 * stamping enabled flag. 1590 */ 1591 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1592 fep->hwts_tx_en) && fep->bufdesc_ex) { 1593 struct skb_shared_hwtstamps shhwtstamps; 1594 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1595 1596 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1597 skb_tstamp_tx(skb, &shhwtstamps); 1598 } 1599 1600 /* Free the sk buffer associated with this last transmit */ 1601 napi_consume_skb(skb, budget); 1602 } else if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1603 xdp_return_frame_rx_napi(xdpf); 1604 } else { /* recycle pages of XDP_TX frames */ 1605 /* The dma_sync_size = 0 as XDP_TX has already synced DMA for_device */ 1606 page_pool_put_page(pp_page_to_nmdesc(page)->pp, page, 1607 0, true); 1608 } 1609 1610 txq->tx_buf[index].buf_p = NULL; 1611 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1612 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1613 1614 tx_buf_done: 1615 /* Make sure the update to bdp and tx_buf are performed 1616 * before dirty_tx 1617 */ 1618 wmb(); 1619 txq->dirty_tx = bdp; 1620 1621 /* Update pointer to next buffer descriptor to be transmitted */ 1622 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1623 1624 /* Since we have freed up a buffer, the ring is no longer full 1625 */ 1626 if (netif_tx_queue_stopped(nq)) { 1627 entries_free = fec_enet_get_free_txdesc_num(txq); 1628 if (entries_free >= txq->tx_wake_threshold) 1629 netif_tx_wake_queue(nq); 1630 } 1631 } 1632 1633 /* ERR006358: Keep the transmitter going */ 1634 if (bdp != txq->bd.cur && 1635 readl(txq->bd.reg_desc_active) == 0) 1636 writel(0, txq->bd.reg_desc_active); 1637 } 1638 1639 static void fec_enet_tx(struct net_device *ndev, int budget) 1640 { 1641 struct fec_enet_private *fep = netdev_priv(ndev); 1642 int i; 1643 1644 /* Make sure that AVB queues are processed first. */ 1645 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1646 fec_enet_tx_queue(ndev, i, budget); 1647 } 1648 1649 static int fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq, 1650 struct bufdesc *bdp, int index) 1651 { 1652 struct page *new_page; 1653 dma_addr_t phys_addr; 1654 1655 new_page = page_pool_dev_alloc_pages(rxq->page_pool); 1656 if (unlikely(!new_page)) 1657 return -ENOMEM; 1658 1659 rxq->rx_skb_info[index].page = new_page; 1660 rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM; 1661 phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM; 1662 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 1663 1664 return 0; 1665 } 1666 1667 static u32 1668 fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog, 1669 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int cpu) 1670 { 1671 unsigned int sync, len = xdp->data_end - xdp->data; 1672 u32 ret = FEC_ENET_XDP_PASS; 1673 struct page *page; 1674 int err; 1675 u32 act; 1676 1677 act = bpf_prog_run_xdp(prog, xdp); 1678 1679 /* Due xdp_adjust_tail and xdp_adjust_head: DMA sync for_device cover 1680 * max len CPU touch 1681 */ 1682 sync = xdp->data_end - xdp->data; 1683 sync = max(sync, len); 1684 1685 switch (act) { 1686 case XDP_PASS: 1687 rxq->stats[RX_XDP_PASS]++; 1688 ret = FEC_ENET_XDP_PASS; 1689 break; 1690 1691 case XDP_REDIRECT: 1692 rxq->stats[RX_XDP_REDIRECT]++; 1693 err = xdp_do_redirect(fep->netdev, xdp, prog); 1694 if (unlikely(err)) 1695 goto xdp_err; 1696 1697 ret = FEC_ENET_XDP_REDIR; 1698 break; 1699 1700 case XDP_TX: 1701 rxq->stats[RX_XDP_TX]++; 1702 err = fec_enet_xdp_tx_xmit(fep, cpu, xdp, sync); 1703 if (unlikely(err)) { 1704 rxq->stats[RX_XDP_TX_ERRORS]++; 1705 goto xdp_err; 1706 } 1707 1708 ret = FEC_ENET_XDP_TX; 1709 break; 1710 1711 default: 1712 bpf_warn_invalid_xdp_action(fep->netdev, prog, act); 1713 fallthrough; 1714 1715 case XDP_ABORTED: 1716 fallthrough; /* handle aborts by dropping packet */ 1717 1718 case XDP_DROP: 1719 rxq->stats[RX_XDP_DROP]++; 1720 xdp_err: 1721 ret = FEC_ENET_XDP_CONSUMED; 1722 page = virt_to_head_page(xdp->data); 1723 page_pool_put_page(rxq->page_pool, page, sync, true); 1724 if (act != XDP_DROP) 1725 trace_xdp_exception(fep->netdev, prog, act); 1726 break; 1727 } 1728 1729 return ret; 1730 } 1731 1732 static void fec_enet_rx_vlan(const struct net_device *ndev, struct sk_buff *skb) 1733 { 1734 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX) { 1735 const struct vlan_ethhdr *vlan_header = skb_vlan_eth_hdr(skb); 1736 const u16 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1737 1738 /* Push and remove the vlan tag */ 1739 1740 memmove(skb->data + VLAN_HLEN, skb->data, ETH_ALEN * 2); 1741 skb_pull(skb, VLAN_HLEN); 1742 __vlan_hwaccel_put_tag(skb, 1743 htons(ETH_P_8021Q), 1744 vlan_tag); 1745 } 1746 } 1747 1748 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1749 * When we update through the ring, if the next incoming buffer has 1750 * not been given to the system, we just set the empty indicator, 1751 * effectively tossing the packet. 1752 */ 1753 static int 1754 fec_enet_rx_queue(struct net_device *ndev, u16 queue_id, int budget) 1755 { 1756 struct fec_enet_private *fep = netdev_priv(ndev); 1757 struct fec_enet_priv_rx_q *rxq; 1758 struct bufdesc *bdp; 1759 unsigned short status; 1760 struct sk_buff *skb; 1761 ushort pkt_len; 1762 int pkt_received = 0; 1763 struct bufdesc_ex *ebdp = NULL; 1764 int index = 0; 1765 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1766 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 1767 u32 ret, xdp_result = FEC_ENET_XDP_PASS; 1768 u32 data_start = FEC_ENET_XDP_HEADROOM; 1769 int cpu = smp_processor_id(); 1770 struct xdp_buff xdp; 1771 struct page *page; 1772 __fec32 cbd_bufaddr; 1773 u32 sub_len = 4; 1774 1775 #if !defined(CONFIG_M5272) 1776 /*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of 1777 * FEC_RACC_SHIFT16 is set by default in the probe function. 1778 */ 1779 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1780 data_start += 2; 1781 sub_len += 2; 1782 } 1783 #endif 1784 1785 #if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA) 1786 /* 1787 * Hacky flush of all caches instead of using the DMA API for the TSO 1788 * headers. 1789 */ 1790 flush_cache_all(); 1791 #endif 1792 rxq = fep->rx_queue[queue_id]; 1793 1794 /* First, grab all of the stats for the incoming packet. 1795 * These get messed up if we get called due to a busy condition. 1796 */ 1797 bdp = rxq->bd.cur; 1798 xdp_init_buff(&xdp, PAGE_SIZE << fep->pagepool_order, &rxq->xdp_rxq); 1799 1800 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1801 1802 if (pkt_received >= budget) 1803 break; 1804 pkt_received++; 1805 1806 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT); 1807 1808 /* Check for errors. */ 1809 status ^= BD_ENET_RX_LAST; 1810 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1811 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1812 BD_ENET_RX_CL)) { 1813 ndev->stats.rx_errors++; 1814 if (status & BD_ENET_RX_OV) { 1815 /* FIFO overrun */ 1816 ndev->stats.rx_fifo_errors++; 1817 goto rx_processing_done; 1818 } 1819 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1820 | BD_ENET_RX_LAST)) { 1821 /* Frame too long or too short. */ 1822 ndev->stats.rx_length_errors++; 1823 if (status & BD_ENET_RX_LAST) 1824 netdev_err(ndev, "rcv is not +last\n"); 1825 } 1826 if (status & BD_ENET_RX_CR) /* CRC Error */ 1827 ndev->stats.rx_crc_errors++; 1828 /* Report late collisions as a frame error. */ 1829 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1830 ndev->stats.rx_frame_errors++; 1831 goto rx_processing_done; 1832 } 1833 1834 /* Process the incoming frame. */ 1835 ndev->stats.rx_packets++; 1836 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1837 ndev->stats.rx_bytes += pkt_len; 1838 1839 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1840 page = rxq->rx_skb_info[index].page; 1841 cbd_bufaddr = bdp->cbd_bufaddr; 1842 if (fec_enet_update_cbd(rxq, bdp, index)) { 1843 ndev->stats.rx_dropped++; 1844 goto rx_processing_done; 1845 } 1846 1847 dma_sync_single_for_cpu(&fep->pdev->dev, 1848 fec32_to_cpu(cbd_bufaddr), 1849 pkt_len, 1850 DMA_FROM_DEVICE); 1851 prefetch(page_address(page)); 1852 1853 if (xdp_prog) { 1854 xdp_buff_clear_frags_flag(&xdp); 1855 /* subtract 16bit shift and FCS */ 1856 xdp_prepare_buff(&xdp, page_address(page), 1857 data_start, pkt_len - sub_len, false); 1858 ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, cpu); 1859 xdp_result |= ret; 1860 if (ret != FEC_ENET_XDP_PASS) 1861 goto rx_processing_done; 1862 } 1863 1864 /* The packet length includes FCS, but we don't want to 1865 * include that when passing upstream as it messes up 1866 * bridging applications. 1867 */ 1868 skb = build_skb(page_address(page), 1869 PAGE_SIZE << fep->pagepool_order); 1870 if (unlikely(!skb)) { 1871 page_pool_recycle_direct(rxq->page_pool, page); 1872 ndev->stats.rx_dropped++; 1873 1874 netdev_err_once(ndev, "build_skb failed!\n"); 1875 goto rx_processing_done; 1876 } 1877 1878 skb_reserve(skb, data_start); 1879 skb_put(skb, pkt_len - sub_len); 1880 skb_mark_for_recycle(skb); 1881 1882 if (unlikely(need_swap)) { 1883 u8 *data; 1884 1885 data = page_address(page) + FEC_ENET_XDP_HEADROOM; 1886 swap_buffer(data, pkt_len); 1887 } 1888 1889 /* Extract the enhanced buffer descriptor */ 1890 ebdp = NULL; 1891 if (fep->bufdesc_ex) 1892 ebdp = (struct bufdesc_ex *)bdp; 1893 1894 /* If this is a VLAN packet remove the VLAN Tag */ 1895 if (fep->bufdesc_ex && 1896 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) 1897 fec_enet_rx_vlan(ndev, skb); 1898 1899 skb->protocol = eth_type_trans(skb, ndev); 1900 1901 /* Get receive timestamp from the skb */ 1902 if (fep->hwts_rx_en && fep->bufdesc_ex) 1903 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1904 skb_hwtstamps(skb)); 1905 1906 if (fep->bufdesc_ex && 1907 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1908 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1909 /* don't check it */ 1910 skb->ip_summed = CHECKSUM_UNNECESSARY; 1911 } else { 1912 skb_checksum_none_assert(skb); 1913 } 1914 } 1915 1916 skb_record_rx_queue(skb, queue_id); 1917 napi_gro_receive(&fep->napi, skb); 1918 1919 rx_processing_done: 1920 /* Clear the status flags for this buffer */ 1921 status &= ~BD_ENET_RX_STATS; 1922 1923 /* Mark the buffer empty */ 1924 status |= BD_ENET_RX_EMPTY; 1925 1926 if (fep->bufdesc_ex) { 1927 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1928 1929 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1930 ebdp->cbd_prot = 0; 1931 ebdp->cbd_bdu = 0; 1932 } 1933 /* Make sure the updates to rest of the descriptor are 1934 * performed before transferring ownership. 1935 */ 1936 wmb(); 1937 bdp->cbd_sc = cpu_to_fec16(status); 1938 1939 /* Update BD pointer to next entry */ 1940 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1941 1942 /* Doing this here will keep the FEC running while we process 1943 * incoming frames. On a heavily loaded network, we should be 1944 * able to keep up at the expense of system resources. 1945 */ 1946 writel(0, rxq->bd.reg_desc_active); 1947 } 1948 rxq->bd.cur = bdp; 1949 1950 if (xdp_result & FEC_ENET_XDP_REDIR) 1951 xdp_do_flush(); 1952 1953 return pkt_received; 1954 } 1955 1956 static int fec_enet_rx(struct net_device *ndev, int budget) 1957 { 1958 struct fec_enet_private *fep = netdev_priv(ndev); 1959 int i, done = 0; 1960 1961 /* Make sure that AVB queues are processed first. */ 1962 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1963 done += fec_enet_rx_queue(ndev, i, budget - done); 1964 1965 return done; 1966 } 1967 1968 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1969 { 1970 uint int_events; 1971 1972 int_events = readl(fep->hwp + FEC_IEVENT); 1973 1974 /* Don't clear MDIO events, we poll for those */ 1975 int_events &= ~FEC_ENET_MII; 1976 1977 writel(int_events, fep->hwp + FEC_IEVENT); 1978 1979 return int_events != 0; 1980 } 1981 1982 static irqreturn_t 1983 fec_enet_interrupt(int irq, void *dev_id) 1984 { 1985 struct net_device *ndev = dev_id; 1986 struct fec_enet_private *fep = netdev_priv(ndev); 1987 irqreturn_t ret = IRQ_NONE; 1988 1989 if (fec_enet_collect_events(fep) && fep->link) { 1990 ret = IRQ_HANDLED; 1991 1992 if (napi_schedule_prep(&fep->napi)) { 1993 /* Disable interrupts */ 1994 writel(0, fep->hwp + FEC_IMASK); 1995 __napi_schedule(&fep->napi); 1996 } 1997 } 1998 1999 return ret; 2000 } 2001 2002 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 2003 { 2004 struct net_device *ndev = napi->dev; 2005 struct fec_enet_private *fep = netdev_priv(ndev); 2006 int done = 0; 2007 2008 do { 2009 done += fec_enet_rx(ndev, budget - done); 2010 fec_enet_tx(ndev, budget); 2011 } while ((done < budget) && fec_enet_collect_events(fep)); 2012 2013 if (done < budget) { 2014 napi_complete_done(napi, done); 2015 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 2016 } 2017 2018 return done; 2019 } 2020 2021 /* ------------------------------------------------------------------------- */ 2022 static int fec_get_mac(struct net_device *ndev) 2023 { 2024 struct fec_enet_private *fep = netdev_priv(ndev); 2025 unsigned char *iap, tmpaddr[ETH_ALEN]; 2026 int ret; 2027 2028 /* 2029 * try to get mac address in following order: 2030 * 2031 * 1) module parameter via kernel command line in form 2032 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 2033 */ 2034 iap = macaddr; 2035 2036 /* 2037 * 2) from device tree data 2038 */ 2039 if (!is_valid_ether_addr(iap)) { 2040 struct device_node *np = fep->pdev->dev.of_node; 2041 if (np) { 2042 ret = of_get_mac_address(np, tmpaddr); 2043 if (!ret) 2044 iap = tmpaddr; 2045 else if (ret == -EPROBE_DEFER) 2046 return ret; 2047 } 2048 } 2049 2050 /* 2051 * 3) from flash or fuse (via platform data) 2052 */ 2053 if (!is_valid_ether_addr(iap)) { 2054 #ifdef CONFIG_M5272 2055 if (FEC_FLASHMAC) 2056 iap = (unsigned char *)FEC_FLASHMAC; 2057 #else 2058 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 2059 2060 if (pdata) 2061 iap = (unsigned char *)&pdata->mac; 2062 #endif 2063 } 2064 2065 /* 2066 * 4) FEC mac registers set by bootloader 2067 */ 2068 if (!is_valid_ether_addr(iap)) { 2069 *((__be32 *) &tmpaddr[0]) = 2070 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 2071 *((__be16 *) &tmpaddr[4]) = 2072 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 2073 iap = &tmpaddr[0]; 2074 } 2075 2076 /* 2077 * 5) random mac address 2078 */ 2079 if (!is_valid_ether_addr(iap)) { 2080 /* Report it and use a random ethernet address instead */ 2081 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 2082 eth_hw_addr_random(ndev); 2083 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 2084 ndev->dev_addr); 2085 return 0; 2086 } 2087 2088 /* Adjust MAC if using macaddr */ 2089 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0); 2090 2091 return 0; 2092 } 2093 2094 /* ------------------------------------------------------------------------- */ 2095 2096 /* 2097 * Phy section 2098 */ 2099 2100 /* LPI Sleep Ts count base on tx clk (clk_ref). 2101 * The lpi sleep cnt value = X us / (cycle_ns). 2102 */ 2103 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) 2104 { 2105 struct fec_enet_private *fep = netdev_priv(ndev); 2106 2107 return us * (fep->clk_ref_rate / 1000) / 1000; 2108 } 2109 2110 static int fec_enet_eee_mode_set(struct net_device *ndev, u32 lpi_timer, 2111 bool enable) 2112 { 2113 struct fec_enet_private *fep = netdev_priv(ndev); 2114 unsigned int sleep_cycle, wake_cycle; 2115 2116 if (enable) { 2117 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, lpi_timer); 2118 wake_cycle = sleep_cycle; 2119 } else { 2120 sleep_cycle = 0; 2121 wake_cycle = 0; 2122 } 2123 2124 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); 2125 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); 2126 2127 return 0; 2128 } 2129 2130 static void fec_enet_adjust_link(struct net_device *ndev) 2131 { 2132 struct fec_enet_private *fep = netdev_priv(ndev); 2133 struct phy_device *phy_dev = ndev->phydev; 2134 int status_change = 0; 2135 2136 /* 2137 * If the netdev is down, or is going down, we're not interested 2138 * in link state events, so just mark our idea of the link as down 2139 * and ignore the event. 2140 */ 2141 if (!netif_running(ndev) || !netif_device_present(ndev)) { 2142 fep->link = 0; 2143 } else if (phy_dev->link) { 2144 if (!fep->link) { 2145 fep->link = phy_dev->link; 2146 status_change = 1; 2147 } 2148 2149 if (fep->full_duplex != phy_dev->duplex) { 2150 fep->full_duplex = phy_dev->duplex; 2151 status_change = 1; 2152 } 2153 2154 if (phy_dev->speed != fep->speed) { 2155 fep->speed = phy_dev->speed; 2156 status_change = 1; 2157 } 2158 2159 /* if any of the above changed restart the FEC */ 2160 if (status_change) { 2161 netif_stop_queue(ndev); 2162 napi_disable(&fep->napi); 2163 netif_tx_lock_bh(ndev); 2164 fec_restart(ndev); 2165 netif_tx_wake_all_queues(ndev); 2166 netif_tx_unlock_bh(ndev); 2167 napi_enable(&fep->napi); 2168 } 2169 if (fep->quirks & FEC_QUIRK_HAS_EEE) 2170 fec_enet_eee_mode_set(ndev, 2171 phy_dev->eee_cfg.tx_lpi_timer, 2172 phy_dev->enable_tx_lpi); 2173 } else { 2174 if (fep->link) { 2175 netif_stop_queue(ndev); 2176 napi_disable(&fep->napi); 2177 netif_tx_lock_bh(ndev); 2178 fec_stop(ndev); 2179 netif_tx_unlock_bh(ndev); 2180 napi_enable(&fep->napi); 2181 fep->link = phy_dev->link; 2182 status_change = 1; 2183 } 2184 } 2185 2186 if (status_change) 2187 phy_print_status(phy_dev); 2188 } 2189 2190 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 2191 { 2192 uint ievent; 2193 int ret; 2194 2195 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 2196 ievent & FEC_ENET_MII, 2, 30000); 2197 2198 if (!ret) 2199 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2200 2201 return ret; 2202 } 2203 2204 static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) 2205 { 2206 struct fec_enet_private *fep = bus->priv; 2207 struct device *dev = &fep->pdev->dev; 2208 int ret = 0, frame_start, frame_addr, frame_op; 2209 2210 ret = pm_runtime_resume_and_get(dev); 2211 if (ret < 0) 2212 return ret; 2213 2214 /* C22 read */ 2215 frame_op = FEC_MMFR_OP_READ; 2216 frame_start = FEC_MMFR_ST; 2217 frame_addr = regnum; 2218 2219 /* start a read op */ 2220 writel(frame_start | frame_op | 2221 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2222 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2223 2224 /* wait for end of transfer */ 2225 ret = fec_enet_mdio_wait(fep); 2226 if (ret) { 2227 netdev_err(fep->netdev, "MDIO read timeout\n"); 2228 goto out; 2229 } 2230 2231 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2232 2233 out: 2234 pm_runtime_mark_last_busy(dev); 2235 pm_runtime_put_autosuspend(dev); 2236 2237 return ret; 2238 } 2239 2240 static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id, 2241 int devad, int regnum) 2242 { 2243 struct fec_enet_private *fep = bus->priv; 2244 struct device *dev = &fep->pdev->dev; 2245 int ret = 0, frame_start, frame_op; 2246 2247 ret = pm_runtime_resume_and_get(dev); 2248 if (ret < 0) 2249 return ret; 2250 2251 frame_start = FEC_MMFR_ST_C45; 2252 2253 /* write address */ 2254 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2255 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2256 FEC_MMFR_TA | (regnum & 0xFFFF), 2257 fep->hwp + FEC_MII_DATA); 2258 2259 /* wait for end of transfer */ 2260 ret = fec_enet_mdio_wait(fep); 2261 if (ret) { 2262 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2263 goto out; 2264 } 2265 2266 frame_op = FEC_MMFR_OP_READ_C45; 2267 2268 /* start a read op */ 2269 writel(frame_start | frame_op | 2270 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2271 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2272 2273 /* wait for end of transfer */ 2274 ret = fec_enet_mdio_wait(fep); 2275 if (ret) { 2276 netdev_err(fep->netdev, "MDIO read timeout\n"); 2277 goto out; 2278 } 2279 2280 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2281 2282 out: 2283 pm_runtime_mark_last_busy(dev); 2284 pm_runtime_put_autosuspend(dev); 2285 2286 return ret; 2287 } 2288 2289 static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, 2290 u16 value) 2291 { 2292 struct fec_enet_private *fep = bus->priv; 2293 struct device *dev = &fep->pdev->dev; 2294 int ret, frame_start, frame_addr; 2295 2296 ret = pm_runtime_resume_and_get(dev); 2297 if (ret < 0) 2298 return ret; 2299 2300 /* C22 write */ 2301 frame_start = FEC_MMFR_ST; 2302 frame_addr = regnum; 2303 2304 /* start a write op */ 2305 writel(frame_start | FEC_MMFR_OP_WRITE | 2306 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2307 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2308 fep->hwp + FEC_MII_DATA); 2309 2310 /* wait for end of transfer */ 2311 ret = fec_enet_mdio_wait(fep); 2312 if (ret) 2313 netdev_err(fep->netdev, "MDIO write timeout\n"); 2314 2315 pm_runtime_mark_last_busy(dev); 2316 pm_runtime_put_autosuspend(dev); 2317 2318 return ret; 2319 } 2320 2321 static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id, 2322 int devad, int regnum, u16 value) 2323 { 2324 struct fec_enet_private *fep = bus->priv; 2325 struct device *dev = &fep->pdev->dev; 2326 int ret, frame_start; 2327 2328 ret = pm_runtime_resume_and_get(dev); 2329 if (ret < 0) 2330 return ret; 2331 2332 frame_start = FEC_MMFR_ST_C45; 2333 2334 /* write address */ 2335 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2336 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2337 FEC_MMFR_TA | (regnum & 0xFFFF), 2338 fep->hwp + FEC_MII_DATA); 2339 2340 /* wait for end of transfer */ 2341 ret = fec_enet_mdio_wait(fep); 2342 if (ret) { 2343 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2344 goto out; 2345 } 2346 2347 /* start a write op */ 2348 writel(frame_start | FEC_MMFR_OP_WRITE | 2349 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2350 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2351 fep->hwp + FEC_MII_DATA); 2352 2353 /* wait for end of transfer */ 2354 ret = fec_enet_mdio_wait(fep); 2355 if (ret) 2356 netdev_err(fep->netdev, "MDIO write timeout\n"); 2357 2358 out: 2359 pm_runtime_mark_last_busy(dev); 2360 pm_runtime_put_autosuspend(dev); 2361 2362 return ret; 2363 } 2364 2365 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 2366 { 2367 struct fec_enet_private *fep = netdev_priv(ndev); 2368 struct phy_device *phy_dev = ndev->phydev; 2369 2370 if (phy_dev) { 2371 phy_reset_after_clk_enable(phy_dev); 2372 } else if (fep->phy_node) { 2373 /* 2374 * If the PHY still is not bound to the MAC, but there is 2375 * OF PHY node and a matching PHY device instance already, 2376 * use the OF PHY node to obtain the PHY device instance, 2377 * and then use that PHY device instance when triggering 2378 * the PHY reset. 2379 */ 2380 phy_dev = of_phy_find_device(fep->phy_node); 2381 phy_reset_after_clk_enable(phy_dev); 2382 if (phy_dev) 2383 put_device(&phy_dev->mdio.dev); 2384 } 2385 } 2386 2387 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 2388 { 2389 struct fec_enet_private *fep = netdev_priv(ndev); 2390 int ret; 2391 2392 if (enable) { 2393 ret = clk_prepare_enable(fep->clk_enet_out); 2394 if (ret) 2395 return ret; 2396 2397 if (fep->clk_ptp) { 2398 mutex_lock(&fep->ptp_clk_mutex); 2399 ret = clk_prepare_enable(fep->clk_ptp); 2400 if (ret) { 2401 mutex_unlock(&fep->ptp_clk_mutex); 2402 goto failed_clk_ptp; 2403 } else { 2404 fep->ptp_clk_on = true; 2405 } 2406 mutex_unlock(&fep->ptp_clk_mutex); 2407 } 2408 2409 ret = clk_prepare_enable(fep->clk_ref); 2410 if (ret) 2411 goto failed_clk_ref; 2412 2413 ret = clk_prepare_enable(fep->clk_2x_txclk); 2414 if (ret) 2415 goto failed_clk_2x_txclk; 2416 2417 fec_enet_phy_reset_after_clk_enable(ndev); 2418 } else { 2419 clk_disable_unprepare(fep->clk_enet_out); 2420 if (fep->clk_ptp) { 2421 mutex_lock(&fep->ptp_clk_mutex); 2422 clk_disable_unprepare(fep->clk_ptp); 2423 fep->ptp_clk_on = false; 2424 mutex_unlock(&fep->ptp_clk_mutex); 2425 } 2426 clk_disable_unprepare(fep->clk_ref); 2427 clk_disable_unprepare(fep->clk_2x_txclk); 2428 } 2429 2430 return 0; 2431 2432 failed_clk_2x_txclk: 2433 if (fep->clk_ref) 2434 clk_disable_unprepare(fep->clk_ref); 2435 failed_clk_ref: 2436 if (fep->clk_ptp) { 2437 mutex_lock(&fep->ptp_clk_mutex); 2438 clk_disable_unprepare(fep->clk_ptp); 2439 fep->ptp_clk_on = false; 2440 mutex_unlock(&fep->ptp_clk_mutex); 2441 } 2442 failed_clk_ptp: 2443 clk_disable_unprepare(fep->clk_enet_out); 2444 2445 return ret; 2446 } 2447 2448 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep, 2449 struct device_node *np) 2450 { 2451 u32 rgmii_tx_delay, rgmii_rx_delay; 2452 2453 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ 2454 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { 2455 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) { 2456 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); 2457 return -EINVAL; 2458 } else if (rgmii_tx_delay == 2000) { 2459 fep->rgmii_txc_dly = true; 2460 } 2461 } 2462 2463 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */ 2464 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { 2465 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) { 2466 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); 2467 return -EINVAL; 2468 } else if (rgmii_rx_delay == 2000) { 2469 fep->rgmii_rxc_dly = true; 2470 } 2471 } 2472 2473 return 0; 2474 } 2475 2476 static int fec_enet_mii_probe(struct net_device *ndev) 2477 { 2478 struct fec_enet_private *fep = netdev_priv(ndev); 2479 struct phy_device *phy_dev = NULL; 2480 char mdio_bus_id[MII_BUS_ID_SIZE]; 2481 char phy_name[MII_BUS_ID_SIZE + 3]; 2482 int phy_id; 2483 int dev_id = fep->dev_id; 2484 2485 if (fep->phy_node) { 2486 phy_dev = of_phy_connect(ndev, fep->phy_node, 2487 &fec_enet_adjust_link, 0, 2488 fep->phy_interface); 2489 if (!phy_dev) { 2490 netdev_err(ndev, "Unable to connect to phy\n"); 2491 return -ENODEV; 2492 } 2493 } else { 2494 /* check for attached phy */ 2495 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2496 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2497 continue; 2498 if (dev_id--) 2499 continue; 2500 strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2501 break; 2502 } 2503 2504 if (phy_id >= PHY_MAX_ADDR) { 2505 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2506 strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2507 phy_id = 0; 2508 } 2509 2510 snprintf(phy_name, sizeof(phy_name), 2511 PHY_ID_FMT, mdio_bus_id, phy_id); 2512 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2513 fep->phy_interface); 2514 } 2515 2516 if (IS_ERR(phy_dev)) { 2517 netdev_err(ndev, "could not attach to PHY\n"); 2518 return PTR_ERR(phy_dev); 2519 } 2520 2521 /* mask with MAC supported features */ 2522 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2523 phy_set_max_speed(phy_dev, 1000); 2524 phy_remove_link_mode(phy_dev, 2525 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2526 #if !defined(CONFIG_M5272) 2527 phy_support_sym_pause(phy_dev); 2528 #endif 2529 } 2530 else 2531 phy_set_max_speed(phy_dev, 100); 2532 2533 if (fep->quirks & FEC_QUIRK_HAS_EEE) 2534 phy_support_eee(phy_dev); 2535 2536 fep->link = 0; 2537 fep->full_duplex = 0; 2538 2539 phy_attached_info(phy_dev); 2540 2541 return 0; 2542 } 2543 2544 static int fec_enet_mii_init(struct platform_device *pdev) 2545 { 2546 static struct mii_bus *fec0_mii_bus; 2547 struct net_device *ndev = platform_get_drvdata(pdev); 2548 struct fec_enet_private *fep = netdev_priv(ndev); 2549 bool suppress_preamble = false; 2550 struct phy_device *phydev; 2551 struct device_node *node; 2552 int err = -ENXIO; 2553 u32 mii_speed, holdtime; 2554 u32 bus_freq; 2555 int addr; 2556 2557 /* 2558 * The i.MX28 dual fec interfaces are not equal. 2559 * Here are the differences: 2560 * 2561 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2562 * - fec0 acts as the 1588 time master while fec1 is slave 2563 * - external phys can only be configured by fec0 2564 * 2565 * That is to say fec1 can not work independently. It only works 2566 * when fec0 is working. The reason behind this design is that the 2567 * second interface is added primarily for Switch mode. 2568 * 2569 * Because of the last point above, both phys are attached on fec0 2570 * mdio interface in board design, and need to be configured by 2571 * fec0 mii_bus. 2572 */ 2573 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2574 /* fec1 uses fec0 mii_bus */ 2575 if (mii_cnt && fec0_mii_bus) { 2576 fep->mii_bus = fec0_mii_bus; 2577 mii_cnt++; 2578 return 0; 2579 } 2580 return -ENOENT; 2581 } 2582 2583 bus_freq = 2500000; /* 2.5MHz by default */ 2584 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2585 if (node) { 2586 of_property_read_u32(node, "clock-frequency", &bus_freq); 2587 suppress_preamble = of_property_read_bool(node, 2588 "suppress-preamble"); 2589 } 2590 2591 /* 2592 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2593 * 2594 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2595 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2596 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2597 * document. 2598 */ 2599 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2600 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2601 mii_speed--; 2602 if (mii_speed > 63) { 2603 dev_err(&pdev->dev, 2604 "fec clock (%lu) too fast to get right mii speed\n", 2605 clk_get_rate(fep->clk_ipg)); 2606 err = -EINVAL; 2607 goto err_out; 2608 } 2609 2610 /* 2611 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2612 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2613 * versions are RAZ there, so just ignore the difference and write the 2614 * register always. 2615 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2616 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2617 * output. 2618 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2619 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2620 * holdtime cannot result in a value greater than 3. 2621 */ 2622 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2623 2624 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2625 2626 if (suppress_preamble) 2627 fep->phy_speed |= BIT(7); 2628 2629 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2630 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2631 * MII event generation condition: 2632 * - writing MSCR: 2633 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2634 * mscr_reg_data_in[7:0] != 0 2635 * - writing MMFR: 2636 * - mscr[7:0]_not_zero 2637 */ 2638 writel(0, fep->hwp + FEC_MII_DATA); 2639 } 2640 2641 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2642 2643 /* Clear any pending transaction complete indication */ 2644 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2645 2646 fep->mii_bus = mdiobus_alloc(); 2647 if (fep->mii_bus == NULL) { 2648 err = -ENOMEM; 2649 goto err_out; 2650 } 2651 2652 fep->mii_bus->name = "fec_enet_mii_bus"; 2653 fep->mii_bus->read = fec_enet_mdio_read_c22; 2654 fep->mii_bus->write = fec_enet_mdio_write_c22; 2655 if (fep->quirks & FEC_QUIRK_HAS_MDIO_C45) { 2656 fep->mii_bus->read_c45 = fec_enet_mdio_read_c45; 2657 fep->mii_bus->write_c45 = fec_enet_mdio_write_c45; 2658 } 2659 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2660 pdev->name, fep->dev_id + 1); 2661 fep->mii_bus->priv = fep; 2662 fep->mii_bus->parent = &pdev->dev; 2663 2664 err = of_mdiobus_register(fep->mii_bus, node); 2665 if (err) 2666 goto err_out_free_mdiobus; 2667 of_node_put(node); 2668 2669 /* find all the PHY devices on the bus and set mac_managed_pm to true */ 2670 for (addr = 0; addr < PHY_MAX_ADDR; addr++) { 2671 phydev = mdiobus_get_phy(fep->mii_bus, addr); 2672 if (phydev) 2673 phydev->mac_managed_pm = true; 2674 } 2675 2676 mii_cnt++; 2677 2678 /* save fec0 mii_bus */ 2679 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2680 fec0_mii_bus = fep->mii_bus; 2681 2682 return 0; 2683 2684 err_out_free_mdiobus: 2685 mdiobus_free(fep->mii_bus); 2686 err_out: 2687 of_node_put(node); 2688 return err; 2689 } 2690 2691 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2692 { 2693 if (--mii_cnt == 0) { 2694 mdiobus_unregister(fep->mii_bus); 2695 mdiobus_free(fep->mii_bus); 2696 } 2697 } 2698 2699 static void fec_enet_get_drvinfo(struct net_device *ndev, 2700 struct ethtool_drvinfo *info) 2701 { 2702 struct fec_enet_private *fep = netdev_priv(ndev); 2703 2704 strscpy(info->driver, fep->pdev->dev.driver->name, 2705 sizeof(info->driver)); 2706 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2707 } 2708 2709 static int fec_enet_get_regs_len(struct net_device *ndev) 2710 { 2711 struct fec_enet_private *fep = netdev_priv(ndev); 2712 struct resource *r; 2713 int s = 0; 2714 2715 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2716 if (r) 2717 s = resource_size(r); 2718 2719 return s; 2720 } 2721 2722 /* List of registers that can be safety be read to dump them with ethtool */ 2723 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2724 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2725 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2726 static __u32 fec_enet_register_version = 2; 2727 static u32 fec_enet_register_offset[] = { 2728 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2729 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2730 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2731 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2732 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2733 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2734 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2735 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2736 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2737 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2738 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2739 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2740 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2741 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2742 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2743 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2744 RMON_T_P_GTE2048, RMON_T_OCTETS, 2745 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2746 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2747 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2748 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2749 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2750 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2751 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2752 RMON_R_P_GTE2048, RMON_R_OCTETS, 2753 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2754 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2755 }; 2756 /* for i.MX6ul */ 2757 static u32 fec_enet_register_offset_6ul[] = { 2758 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2759 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2760 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0, 2761 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, 2762 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0, 2763 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2764 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, 2765 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2766 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2767 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2768 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2769 RMON_T_P_GTE2048, RMON_T_OCTETS, 2770 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2771 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2772 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2773 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2774 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2775 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2776 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2777 RMON_R_P_GTE2048, RMON_R_OCTETS, 2778 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2779 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2780 }; 2781 #else 2782 static __u32 fec_enet_register_version = 1; 2783 static u32 fec_enet_register_offset[] = { 2784 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2785 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2786 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2787 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2788 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2789 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2790 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2791 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2792 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2793 }; 2794 #endif 2795 2796 static void fec_enet_get_regs(struct net_device *ndev, 2797 struct ethtool_regs *regs, void *regbuf) 2798 { 2799 struct fec_enet_private *fep = netdev_priv(ndev); 2800 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2801 struct device *dev = &fep->pdev->dev; 2802 u32 *buf = (u32 *)regbuf; 2803 u32 i, off; 2804 int ret; 2805 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2806 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2807 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2808 u32 *reg_list; 2809 u32 reg_cnt; 2810 2811 if (!of_machine_is_compatible("fsl,imx6ul")) { 2812 reg_list = fec_enet_register_offset; 2813 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2814 } else { 2815 reg_list = fec_enet_register_offset_6ul; 2816 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul); 2817 } 2818 #else 2819 /* coldfire */ 2820 static u32 *reg_list = fec_enet_register_offset; 2821 static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2822 #endif 2823 ret = pm_runtime_resume_and_get(dev); 2824 if (ret < 0) 2825 return; 2826 2827 regs->version = fec_enet_register_version; 2828 2829 memset(buf, 0, regs->len); 2830 2831 for (i = 0; i < reg_cnt; i++) { 2832 off = reg_list[i]; 2833 2834 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2835 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2836 continue; 2837 2838 off >>= 2; 2839 buf[off] = readl(&theregs[off]); 2840 } 2841 2842 pm_runtime_mark_last_busy(dev); 2843 pm_runtime_put_autosuspend(dev); 2844 } 2845 2846 static int fec_enet_get_ts_info(struct net_device *ndev, 2847 struct kernel_ethtool_ts_info *info) 2848 { 2849 struct fec_enet_private *fep = netdev_priv(ndev); 2850 2851 if (fep->bufdesc_ex) { 2852 2853 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2854 SOF_TIMESTAMPING_TX_HARDWARE | 2855 SOF_TIMESTAMPING_RX_HARDWARE | 2856 SOF_TIMESTAMPING_RAW_HARDWARE; 2857 if (fep->ptp_clock) 2858 info->phc_index = ptp_clock_index(fep->ptp_clock); 2859 2860 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2861 (1 << HWTSTAMP_TX_ON); 2862 2863 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2864 (1 << HWTSTAMP_FILTER_ALL); 2865 return 0; 2866 } else { 2867 return ethtool_op_get_ts_info(ndev, info); 2868 } 2869 } 2870 2871 #if !defined(CONFIG_M5272) 2872 2873 static void fec_enet_get_pauseparam(struct net_device *ndev, 2874 struct ethtool_pauseparam *pause) 2875 { 2876 struct fec_enet_private *fep = netdev_priv(ndev); 2877 2878 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2879 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2880 pause->rx_pause = pause->tx_pause; 2881 } 2882 2883 static int fec_enet_set_pauseparam(struct net_device *ndev, 2884 struct ethtool_pauseparam *pause) 2885 { 2886 struct fec_enet_private *fep = netdev_priv(ndev); 2887 2888 if (!ndev->phydev) 2889 return -ENODEV; 2890 2891 if (pause->tx_pause != pause->rx_pause) { 2892 netdev_info(ndev, 2893 "hardware only support enable/disable both tx and rx"); 2894 return -EINVAL; 2895 } 2896 2897 fep->pause_flag = 0; 2898 2899 /* tx pause must be same as rx pause */ 2900 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2901 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2902 2903 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2904 pause->autoneg); 2905 2906 if (pause->autoneg) { 2907 if (netif_running(ndev)) 2908 fec_stop(ndev); 2909 phy_start_aneg(ndev->phydev); 2910 } 2911 if (netif_running(ndev)) { 2912 napi_disable(&fep->napi); 2913 netif_tx_lock_bh(ndev); 2914 fec_restart(ndev); 2915 netif_tx_wake_all_queues(ndev); 2916 netif_tx_unlock_bh(ndev); 2917 napi_enable(&fep->napi); 2918 } 2919 2920 return 0; 2921 } 2922 2923 static const struct fec_stat { 2924 char name[ETH_GSTRING_LEN]; 2925 u16 offset; 2926 } fec_stats[] = { 2927 /* RMON TX */ 2928 { "tx_dropped", RMON_T_DROP }, 2929 { "tx_packets", RMON_T_PACKETS }, 2930 { "tx_broadcast", RMON_T_BC_PKT }, 2931 { "tx_multicast", RMON_T_MC_PKT }, 2932 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2933 { "tx_undersize", RMON_T_UNDERSIZE }, 2934 { "tx_oversize", RMON_T_OVERSIZE }, 2935 { "tx_fragment", RMON_T_FRAG }, 2936 { "tx_jabber", RMON_T_JAB }, 2937 { "tx_collision", RMON_T_COL }, 2938 { "tx_64byte", RMON_T_P64 }, 2939 { "tx_65to127byte", RMON_T_P65TO127 }, 2940 { "tx_128to255byte", RMON_T_P128TO255 }, 2941 { "tx_256to511byte", RMON_T_P256TO511 }, 2942 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2943 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2944 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2945 { "tx_octets", RMON_T_OCTETS }, 2946 2947 /* IEEE TX */ 2948 { "IEEE_tx_drop", IEEE_T_DROP }, 2949 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2950 { "IEEE_tx_1col", IEEE_T_1COL }, 2951 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2952 { "IEEE_tx_def", IEEE_T_DEF }, 2953 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2954 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2955 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2956 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2957 { "IEEE_tx_sqe", IEEE_T_SQE }, 2958 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2959 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2960 2961 /* RMON RX */ 2962 { "rx_packets", RMON_R_PACKETS }, 2963 { "rx_broadcast", RMON_R_BC_PKT }, 2964 { "rx_multicast", RMON_R_MC_PKT }, 2965 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2966 { "rx_undersize", RMON_R_UNDERSIZE }, 2967 { "rx_oversize", RMON_R_OVERSIZE }, 2968 { "rx_fragment", RMON_R_FRAG }, 2969 { "rx_jabber", RMON_R_JAB }, 2970 { "rx_64byte", RMON_R_P64 }, 2971 { "rx_65to127byte", RMON_R_P65TO127 }, 2972 { "rx_128to255byte", RMON_R_P128TO255 }, 2973 { "rx_256to511byte", RMON_R_P256TO511 }, 2974 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2975 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2976 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2977 { "rx_octets", RMON_R_OCTETS }, 2978 2979 /* IEEE RX */ 2980 { "IEEE_rx_drop", IEEE_R_DROP }, 2981 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2982 { "IEEE_rx_crc", IEEE_R_CRC }, 2983 { "IEEE_rx_align", IEEE_R_ALIGN }, 2984 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2985 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2986 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2987 }; 2988 2989 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2990 2991 static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = { 2992 "rx_xdp_redirect", /* RX_XDP_REDIRECT = 0, */ 2993 "rx_xdp_pass", /* RX_XDP_PASS, */ 2994 "rx_xdp_drop", /* RX_XDP_DROP, */ 2995 "rx_xdp_tx", /* RX_XDP_TX, */ 2996 "rx_xdp_tx_errors", /* RX_XDP_TX_ERRORS, */ 2997 "tx_xdp_xmit", /* TX_XDP_XMIT, */ 2998 "tx_xdp_xmit_errors", /* TX_XDP_XMIT_ERRORS, */ 2999 }; 3000 3001 static void fec_enet_update_ethtool_stats(struct net_device *dev) 3002 { 3003 struct fec_enet_private *fep = netdev_priv(dev); 3004 int i; 3005 3006 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 3007 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 3008 } 3009 3010 static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data) 3011 { 3012 u64 xdp_stats[XDP_STATS_TOTAL] = { 0 }; 3013 struct fec_enet_priv_rx_q *rxq; 3014 int i, j; 3015 3016 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 3017 rxq = fep->rx_queue[i]; 3018 3019 for (j = 0; j < XDP_STATS_TOTAL; j++) 3020 xdp_stats[j] += rxq->stats[j]; 3021 } 3022 3023 memcpy(data, xdp_stats, sizeof(xdp_stats)); 3024 } 3025 3026 static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data) 3027 { 3028 #ifdef CONFIG_PAGE_POOL_STATS 3029 struct page_pool_stats stats = {}; 3030 struct fec_enet_priv_rx_q *rxq; 3031 int i; 3032 3033 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 3034 rxq = fep->rx_queue[i]; 3035 3036 if (!rxq->page_pool) 3037 continue; 3038 3039 page_pool_get_stats(rxq->page_pool, &stats); 3040 } 3041 3042 page_pool_ethtool_stats_get(data, &stats); 3043 #endif 3044 } 3045 3046 static void fec_enet_get_ethtool_stats(struct net_device *dev, 3047 struct ethtool_stats *stats, u64 *data) 3048 { 3049 struct fec_enet_private *fep = netdev_priv(dev); 3050 3051 if (netif_running(dev)) 3052 fec_enet_update_ethtool_stats(dev); 3053 3054 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 3055 data += FEC_STATS_SIZE / sizeof(u64); 3056 3057 fec_enet_get_xdp_stats(fep, data); 3058 data += XDP_STATS_TOTAL; 3059 3060 fec_enet_page_pool_stats(fep, data); 3061 } 3062 3063 static void fec_enet_get_strings(struct net_device *netdev, 3064 u32 stringset, u8 *data) 3065 { 3066 int i; 3067 switch (stringset) { 3068 case ETH_SS_STATS: 3069 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) { 3070 ethtool_puts(&data, fec_stats[i].name); 3071 } 3072 for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) { 3073 ethtool_puts(&data, fec_xdp_stat_strs[i]); 3074 } 3075 page_pool_ethtool_stats_get_strings(data); 3076 3077 break; 3078 case ETH_SS_TEST: 3079 net_selftest_get_strings(data); 3080 break; 3081 } 3082 } 3083 3084 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 3085 { 3086 int count; 3087 3088 switch (sset) { 3089 case ETH_SS_STATS: 3090 count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL; 3091 count += page_pool_ethtool_stats_get_count(); 3092 return count; 3093 3094 case ETH_SS_TEST: 3095 return net_selftest_get_count(); 3096 default: 3097 return -EOPNOTSUPP; 3098 } 3099 } 3100 3101 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 3102 { 3103 struct fec_enet_private *fep = netdev_priv(dev); 3104 struct fec_enet_priv_rx_q *rxq; 3105 int i, j; 3106 3107 /* Disable MIB statistics counters */ 3108 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 3109 3110 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 3111 writel(0, fep->hwp + fec_stats[i].offset); 3112 3113 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 3114 rxq = fep->rx_queue[i]; 3115 for (j = 0; j < XDP_STATS_TOTAL; j++) 3116 rxq->stats[j] = 0; 3117 } 3118 3119 /* Don't disable MIB statistics counters */ 3120 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 3121 } 3122 3123 #else /* !defined(CONFIG_M5272) */ 3124 #define FEC_STATS_SIZE 0 3125 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 3126 { 3127 } 3128 3129 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 3130 { 3131 } 3132 #endif /* !defined(CONFIG_M5272) */ 3133 3134 /* ITR clock source is enet system clock (clk_ahb). 3135 * TCTT unit is cycle_ns * 64 cycle 3136 * So, the ICTT value = X us / (cycle_ns * 64) 3137 */ 3138 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 3139 { 3140 struct fec_enet_private *fep = netdev_priv(ndev); 3141 3142 return us * (fep->itr_clk_rate / 64000) / 1000; 3143 } 3144 3145 /* Set threshold for interrupt coalescing */ 3146 static void fec_enet_itr_coal_set(struct net_device *ndev) 3147 { 3148 struct fec_enet_private *fep = netdev_priv(ndev); 3149 u32 rx_itr = 0, tx_itr = 0; 3150 int rx_ictt, tx_ictt; 3151 3152 rx_ictt = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); 3153 tx_ictt = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); 3154 3155 if (rx_ictt > 0 && fep->rx_pkts_itr > 1) { 3156 /* Enable with enet system clock as Interrupt Coalescing timer Clock Source */ 3157 rx_itr = FEC_ITR_EN | FEC_ITR_CLK_SEL; 3158 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 3159 rx_itr |= FEC_ITR_ICTT(rx_ictt); 3160 } 3161 3162 if (tx_ictt > 0 && fep->tx_pkts_itr > 1) { 3163 /* Enable with enet system clock as Interrupt Coalescing timer Clock Source */ 3164 tx_itr = FEC_ITR_EN | FEC_ITR_CLK_SEL; 3165 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 3166 tx_itr |= FEC_ITR_ICTT(tx_ictt); 3167 } 3168 3169 writel(tx_itr, fep->hwp + FEC_TXIC0); 3170 writel(rx_itr, fep->hwp + FEC_RXIC0); 3171 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 3172 writel(tx_itr, fep->hwp + FEC_TXIC1); 3173 writel(rx_itr, fep->hwp + FEC_RXIC1); 3174 writel(tx_itr, fep->hwp + FEC_TXIC2); 3175 writel(rx_itr, fep->hwp + FEC_RXIC2); 3176 } 3177 } 3178 3179 static int fec_enet_get_coalesce(struct net_device *ndev, 3180 struct ethtool_coalesce *ec, 3181 struct kernel_ethtool_coalesce *kernel_coal, 3182 struct netlink_ext_ack *extack) 3183 { 3184 struct fec_enet_private *fep = netdev_priv(ndev); 3185 3186 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3187 return -EOPNOTSUPP; 3188 3189 ec->rx_coalesce_usecs = fep->rx_time_itr; 3190 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 3191 3192 ec->tx_coalesce_usecs = fep->tx_time_itr; 3193 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 3194 3195 return 0; 3196 } 3197 3198 static int fec_enet_set_coalesce(struct net_device *ndev, 3199 struct ethtool_coalesce *ec, 3200 struct kernel_ethtool_coalesce *kernel_coal, 3201 struct netlink_ext_ack *extack) 3202 { 3203 struct fec_enet_private *fep = netdev_priv(ndev); 3204 struct device *dev = &fep->pdev->dev; 3205 unsigned int cycle; 3206 3207 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3208 return -EOPNOTSUPP; 3209 3210 if (ec->rx_max_coalesced_frames > 255) { 3211 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 3212 return -EINVAL; 3213 } 3214 3215 if (ec->tx_max_coalesced_frames > 255) { 3216 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 3217 return -EINVAL; 3218 } 3219 3220 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 3221 if (cycle > 0xFFFF) { 3222 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 3223 return -EINVAL; 3224 } 3225 3226 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 3227 if (cycle > 0xFFFF) { 3228 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 3229 return -EINVAL; 3230 } 3231 3232 fep->rx_time_itr = ec->rx_coalesce_usecs; 3233 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 3234 3235 fep->tx_time_itr = ec->tx_coalesce_usecs; 3236 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 3237 3238 fec_enet_itr_coal_set(ndev); 3239 3240 return 0; 3241 } 3242 3243 static int 3244 fec_enet_get_eee(struct net_device *ndev, struct ethtool_keee *edata) 3245 { 3246 struct fec_enet_private *fep = netdev_priv(ndev); 3247 3248 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3249 return -EOPNOTSUPP; 3250 3251 if (!netif_running(ndev)) 3252 return -ENETDOWN; 3253 3254 return phy_ethtool_get_eee(ndev->phydev, edata); 3255 } 3256 3257 static int 3258 fec_enet_set_eee(struct net_device *ndev, struct ethtool_keee *edata) 3259 { 3260 struct fec_enet_private *fep = netdev_priv(ndev); 3261 3262 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3263 return -EOPNOTSUPP; 3264 3265 if (!netif_running(ndev)) 3266 return -ENETDOWN; 3267 3268 return phy_ethtool_set_eee(ndev->phydev, edata); 3269 } 3270 3271 static void 3272 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3273 { 3274 struct fec_enet_private *fep = netdev_priv(ndev); 3275 3276 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 3277 wol->supported = WAKE_MAGIC; 3278 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 3279 } else { 3280 wol->supported = wol->wolopts = 0; 3281 } 3282 } 3283 3284 static int 3285 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3286 { 3287 struct fec_enet_private *fep = netdev_priv(ndev); 3288 3289 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 3290 return -EINVAL; 3291 3292 if (wol->wolopts & ~WAKE_MAGIC) 3293 return -EINVAL; 3294 3295 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 3296 if (device_may_wakeup(&ndev->dev)) 3297 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 3298 else 3299 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 3300 3301 return 0; 3302 } 3303 3304 static const struct ethtool_ops fec_enet_ethtool_ops = { 3305 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3306 ETHTOOL_COALESCE_MAX_FRAMES, 3307 .get_drvinfo = fec_enet_get_drvinfo, 3308 .get_regs_len = fec_enet_get_regs_len, 3309 .get_regs = fec_enet_get_regs, 3310 .nway_reset = phy_ethtool_nway_reset, 3311 .get_link = ethtool_op_get_link, 3312 .get_coalesce = fec_enet_get_coalesce, 3313 .set_coalesce = fec_enet_set_coalesce, 3314 #ifndef CONFIG_M5272 3315 .get_pauseparam = fec_enet_get_pauseparam, 3316 .set_pauseparam = fec_enet_set_pauseparam, 3317 .get_strings = fec_enet_get_strings, 3318 .get_ethtool_stats = fec_enet_get_ethtool_stats, 3319 .get_sset_count = fec_enet_get_sset_count, 3320 #endif 3321 .get_ts_info = fec_enet_get_ts_info, 3322 .get_wol = fec_enet_get_wol, 3323 .set_wol = fec_enet_set_wol, 3324 .get_eee = fec_enet_get_eee, 3325 .set_eee = fec_enet_set_eee, 3326 .get_link_ksettings = phy_ethtool_get_link_ksettings, 3327 .set_link_ksettings = phy_ethtool_set_link_ksettings, 3328 .self_test = net_selftest, 3329 }; 3330 3331 static void fec_enet_free_buffers(struct net_device *ndev) 3332 { 3333 struct fec_enet_private *fep = netdev_priv(ndev); 3334 unsigned int i; 3335 struct fec_enet_priv_tx_q *txq; 3336 struct fec_enet_priv_rx_q *rxq; 3337 unsigned int q; 3338 3339 for (q = 0; q < fep->num_rx_queues; q++) { 3340 rxq = fep->rx_queue[q]; 3341 for (i = 0; i < rxq->bd.ring_size; i++) 3342 page_pool_put_full_page(rxq->page_pool, rxq->rx_skb_info[i].page, false); 3343 3344 for (i = 0; i < XDP_STATS_TOTAL; i++) 3345 rxq->stats[i] = 0; 3346 3347 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 3348 xdp_rxq_info_unreg(&rxq->xdp_rxq); 3349 page_pool_destroy(rxq->page_pool); 3350 rxq->page_pool = NULL; 3351 } 3352 3353 for (q = 0; q < fep->num_tx_queues; q++) { 3354 txq = fep->tx_queue[q]; 3355 for (i = 0; i < txq->bd.ring_size; i++) { 3356 kfree(txq->tx_bounce[i]); 3357 txq->tx_bounce[i] = NULL; 3358 3359 if (!txq->tx_buf[i].buf_p) { 3360 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3361 continue; 3362 } 3363 3364 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 3365 dev_kfree_skb(txq->tx_buf[i].buf_p); 3366 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 3367 xdp_return_frame(txq->tx_buf[i].buf_p); 3368 } else { 3369 struct page *page = txq->tx_buf[i].buf_p; 3370 3371 page_pool_put_page(pp_page_to_nmdesc(page)->pp, 3372 page, 0, false); 3373 } 3374 3375 txq->tx_buf[i].buf_p = NULL; 3376 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3377 } 3378 } 3379 } 3380 3381 static void fec_enet_free_queue(struct net_device *ndev) 3382 { 3383 struct fec_enet_private *fep = netdev_priv(ndev); 3384 int i; 3385 struct fec_enet_priv_tx_q *txq; 3386 3387 for (i = 0; i < fep->num_tx_queues; i++) 3388 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 3389 txq = fep->tx_queue[i]; 3390 fec_dma_free(&fep->pdev->dev, 3391 txq->bd.ring_size * TSO_HEADER_SIZE, 3392 txq->tso_hdrs, txq->tso_hdrs_dma); 3393 } 3394 3395 for (i = 0; i < fep->num_rx_queues; i++) 3396 kfree(fep->rx_queue[i]); 3397 for (i = 0; i < fep->num_tx_queues; i++) 3398 kfree(fep->tx_queue[i]); 3399 } 3400 3401 static int fec_enet_alloc_queue(struct net_device *ndev) 3402 { 3403 struct fec_enet_private *fep = netdev_priv(ndev); 3404 int i; 3405 int ret = 0; 3406 struct fec_enet_priv_tx_q *txq; 3407 3408 for (i = 0; i < fep->num_tx_queues; i++) { 3409 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 3410 if (!txq) { 3411 ret = -ENOMEM; 3412 goto alloc_failed; 3413 } 3414 3415 fep->tx_queue[i] = txq; 3416 txq->bd.ring_size = TX_RING_SIZE; 3417 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 3418 3419 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 3420 txq->tx_wake_threshold = FEC_MAX_SKB_DESCS + 2 * MAX_SKB_FRAGS; 3421 3422 txq->tso_hdrs = fec_dma_alloc(&fep->pdev->dev, 3423 txq->bd.ring_size * TSO_HEADER_SIZE, 3424 &txq->tso_hdrs_dma, GFP_KERNEL); 3425 if (!txq->tso_hdrs) { 3426 ret = -ENOMEM; 3427 goto alloc_failed; 3428 } 3429 } 3430 3431 for (i = 0; i < fep->num_rx_queues; i++) { 3432 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 3433 GFP_KERNEL); 3434 if (!fep->rx_queue[i]) { 3435 ret = -ENOMEM; 3436 goto alloc_failed; 3437 } 3438 3439 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 3440 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 3441 } 3442 return ret; 3443 3444 alloc_failed: 3445 fec_enet_free_queue(ndev); 3446 return ret; 3447 } 3448 3449 static int 3450 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 3451 { 3452 struct fec_enet_private *fep = netdev_priv(ndev); 3453 struct fec_enet_priv_rx_q *rxq; 3454 dma_addr_t phys_addr; 3455 struct bufdesc *bdp; 3456 struct page *page; 3457 int i, err; 3458 3459 rxq = fep->rx_queue[queue]; 3460 bdp = rxq->bd.base; 3461 3462 err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size); 3463 if (err < 0) { 3464 netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err); 3465 return err; 3466 } 3467 3468 for (i = 0; i < rxq->bd.ring_size; i++) { 3469 page = page_pool_dev_alloc_pages(rxq->page_pool); 3470 if (!page) 3471 goto err_alloc; 3472 3473 phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM; 3474 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 3475 3476 rxq->rx_skb_info[i].page = page; 3477 rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM; 3478 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3479 3480 if (fep->bufdesc_ex) { 3481 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3482 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 3483 } 3484 3485 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3486 } 3487 3488 /* Set the last buffer to wrap. */ 3489 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3490 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3491 return 0; 3492 3493 err_alloc: 3494 fec_enet_free_buffers(ndev); 3495 return -ENOMEM; 3496 } 3497 3498 static int 3499 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 3500 { 3501 struct fec_enet_private *fep = netdev_priv(ndev); 3502 unsigned int i; 3503 struct bufdesc *bdp; 3504 struct fec_enet_priv_tx_q *txq; 3505 3506 txq = fep->tx_queue[queue]; 3507 bdp = txq->bd.base; 3508 for (i = 0; i < txq->bd.ring_size; i++) { 3509 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 3510 if (!txq->tx_bounce[i]) 3511 goto err_alloc; 3512 3513 bdp->cbd_sc = cpu_to_fec16(0); 3514 bdp->cbd_bufaddr = cpu_to_fec32(0); 3515 3516 if (fep->bufdesc_ex) { 3517 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3518 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 3519 } 3520 3521 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3522 } 3523 3524 /* Set the last buffer to wrap. */ 3525 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3526 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3527 3528 return 0; 3529 3530 err_alloc: 3531 fec_enet_free_buffers(ndev); 3532 return -ENOMEM; 3533 } 3534 3535 static int fec_enet_alloc_buffers(struct net_device *ndev) 3536 { 3537 struct fec_enet_private *fep = netdev_priv(ndev); 3538 unsigned int i; 3539 3540 for (i = 0; i < fep->num_rx_queues; i++) 3541 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3542 return -ENOMEM; 3543 3544 for (i = 0; i < fep->num_tx_queues; i++) 3545 if (fec_enet_alloc_txq_buffers(ndev, i)) 3546 return -ENOMEM; 3547 return 0; 3548 } 3549 3550 static int 3551 fec_enet_open(struct net_device *ndev) 3552 { 3553 struct fec_enet_private *fep = netdev_priv(ndev); 3554 int ret; 3555 bool reset_again; 3556 3557 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3558 if (ret < 0) 3559 return ret; 3560 3561 pinctrl_pm_select_default_state(&fep->pdev->dev); 3562 ret = fec_enet_clk_enable(ndev, true); 3563 if (ret) 3564 goto clk_enable; 3565 3566 /* During the first fec_enet_open call the PHY isn't probed at this 3567 * point. Therefore the phy_reset_after_clk_enable() call within 3568 * fec_enet_clk_enable() fails. As we need this reset in order to be 3569 * sure the PHY is working correctly we check if we need to reset again 3570 * later when the PHY is probed 3571 */ 3572 if (ndev->phydev && ndev->phydev->drv) 3573 reset_again = false; 3574 else 3575 reset_again = true; 3576 3577 /* I should reset the ring buffers here, but I don't yet know 3578 * a simple way to do that. 3579 */ 3580 3581 ret = fec_enet_alloc_buffers(ndev); 3582 if (ret) 3583 goto err_enet_alloc; 3584 3585 /* Init MAC prior to mii bus probe */ 3586 fec_restart(ndev); 3587 3588 /* Call phy_reset_after_clk_enable() again if it failed during 3589 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3590 */ 3591 if (reset_again) 3592 fec_enet_phy_reset_after_clk_enable(ndev); 3593 3594 /* Probe and connect to PHY when open the interface */ 3595 ret = fec_enet_mii_probe(ndev); 3596 if (ret) 3597 goto err_enet_mii_probe; 3598 3599 if (fep->quirks & FEC_QUIRK_ERR006687) 3600 imx6q_cpuidle_fec_irqs_used(); 3601 3602 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3603 cpu_latency_qos_add_request(&fep->pm_qos_req, 0); 3604 3605 napi_enable(&fep->napi); 3606 phy_start(ndev->phydev); 3607 netif_tx_start_all_queues(ndev); 3608 3609 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3610 FEC_WOL_FLAG_ENABLE); 3611 3612 return 0; 3613 3614 err_enet_mii_probe: 3615 fec_enet_free_buffers(ndev); 3616 err_enet_alloc: 3617 fec_enet_clk_enable(ndev, false); 3618 clk_enable: 3619 pm_runtime_mark_last_busy(&fep->pdev->dev); 3620 pm_runtime_put_autosuspend(&fep->pdev->dev); 3621 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3622 return ret; 3623 } 3624 3625 static int 3626 fec_enet_close(struct net_device *ndev) 3627 { 3628 struct fec_enet_private *fep = netdev_priv(ndev); 3629 3630 phy_stop(ndev->phydev); 3631 3632 if (netif_device_present(ndev)) { 3633 napi_disable(&fep->napi); 3634 netif_tx_disable(ndev); 3635 fec_stop(ndev); 3636 } 3637 3638 phy_disconnect(ndev->phydev); 3639 3640 if (fep->quirks & FEC_QUIRK_ERR006687) 3641 imx6q_cpuidle_fec_irqs_unused(); 3642 3643 fec_enet_update_ethtool_stats(ndev); 3644 3645 fec_enet_clk_enable(ndev, false); 3646 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3647 cpu_latency_qos_remove_request(&fep->pm_qos_req); 3648 3649 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3650 pm_runtime_mark_last_busy(&fep->pdev->dev); 3651 pm_runtime_put_autosuspend(&fep->pdev->dev); 3652 3653 fec_enet_free_buffers(ndev); 3654 3655 return 0; 3656 } 3657 3658 /* Set or clear the multicast filter for this adaptor. 3659 * Skeleton taken from sunlance driver. 3660 * The CPM Ethernet implementation allows Multicast as well as individual 3661 * MAC address filtering. Some of the drivers check to make sure it is 3662 * a group multicast address, and discard those that are not. I guess I 3663 * will do the same for now, but just remove the test if you want 3664 * individual filtering as well (do the upper net layers want or support 3665 * this kind of feature?). 3666 */ 3667 3668 #define FEC_HASH_BITS 6 /* #bits in hash */ 3669 3670 static void set_multicast_list(struct net_device *ndev) 3671 { 3672 struct fec_enet_private *fep = netdev_priv(ndev); 3673 struct netdev_hw_addr *ha; 3674 unsigned int crc, tmp; 3675 unsigned char hash; 3676 unsigned int hash_high = 0, hash_low = 0; 3677 3678 if (ndev->flags & IFF_PROMISC) { 3679 tmp = readl(fep->hwp + FEC_R_CNTRL); 3680 tmp |= 0x8; 3681 writel(tmp, fep->hwp + FEC_R_CNTRL); 3682 return; 3683 } 3684 3685 tmp = readl(fep->hwp + FEC_R_CNTRL); 3686 tmp &= ~0x8; 3687 writel(tmp, fep->hwp + FEC_R_CNTRL); 3688 3689 if (ndev->flags & IFF_ALLMULTI) { 3690 /* Catch all multicast addresses, so set the 3691 * filter to all 1's 3692 */ 3693 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3694 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3695 3696 return; 3697 } 3698 3699 /* Add the addresses in hash register */ 3700 netdev_for_each_mc_addr(ha, ndev) { 3701 /* calculate crc32 value of mac address */ 3702 crc = ether_crc_le(ndev->addr_len, ha->addr); 3703 3704 /* only upper 6 bits (FEC_HASH_BITS) are used 3705 * which point to specific bit in the hash registers 3706 */ 3707 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3708 3709 if (hash > 31) 3710 hash_high |= 1 << (hash - 32); 3711 else 3712 hash_low |= 1 << hash; 3713 } 3714 3715 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3716 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3717 } 3718 3719 /* Set a MAC change in hardware. */ 3720 static int 3721 fec_set_mac_address(struct net_device *ndev, void *p) 3722 { 3723 struct sockaddr *addr = p; 3724 3725 if (addr) { 3726 if (!is_valid_ether_addr(addr->sa_data)) 3727 return -EADDRNOTAVAIL; 3728 eth_hw_addr_set(ndev, addr->sa_data); 3729 } 3730 3731 /* Add netif status check here to avoid system hang in below case: 3732 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3733 * After ethx down, fec all clocks are gated off and then register 3734 * access causes system hang. 3735 */ 3736 if (!netif_running(ndev)) 3737 return 0; 3738 3739 fec_set_hw_mac_addr(ndev); 3740 3741 return 0; 3742 } 3743 3744 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3745 netdev_features_t features) 3746 { 3747 struct fec_enet_private *fep = netdev_priv(netdev); 3748 netdev_features_t changed = features ^ netdev->features; 3749 3750 netdev->features = features; 3751 3752 /* Receive checksum has been changed */ 3753 if (changed & NETIF_F_RXCSUM) { 3754 if (features & NETIF_F_RXCSUM) 3755 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3756 else 3757 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3758 } 3759 } 3760 3761 static int fec_set_features(struct net_device *netdev, 3762 netdev_features_t features) 3763 { 3764 struct fec_enet_private *fep = netdev_priv(netdev); 3765 netdev_features_t changed = features ^ netdev->features; 3766 3767 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3768 napi_disable(&fep->napi); 3769 netif_tx_lock_bh(netdev); 3770 fec_stop(netdev); 3771 fec_enet_set_netdev_features(netdev, features); 3772 fec_restart(netdev); 3773 netif_tx_wake_all_queues(netdev); 3774 netif_tx_unlock_bh(netdev); 3775 napi_enable(&fep->napi); 3776 } else { 3777 fec_enet_set_netdev_features(netdev, features); 3778 } 3779 3780 return 0; 3781 } 3782 3783 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3784 struct net_device *sb_dev) 3785 { 3786 struct fec_enet_private *fep = netdev_priv(ndev); 3787 u16 vlan_tag = 0; 3788 3789 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3790 return netdev_pick_tx(ndev, skb, NULL); 3791 3792 /* VLAN is present in the payload.*/ 3793 if (eth_type_vlan(skb->protocol)) { 3794 struct vlan_ethhdr *vhdr = skb_vlan_eth_hdr(skb); 3795 3796 vlan_tag = ntohs(vhdr->h_vlan_TCI); 3797 /* VLAN is present in the skb but not yet pushed in the payload.*/ 3798 } else if (skb_vlan_tag_present(skb)) { 3799 vlan_tag = skb->vlan_tci; 3800 } else { 3801 return vlan_tag; 3802 } 3803 3804 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3805 } 3806 3807 static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf) 3808 { 3809 struct fec_enet_private *fep = netdev_priv(dev); 3810 bool is_run = netif_running(dev); 3811 struct bpf_prog *old_prog; 3812 3813 switch (bpf->command) { 3814 case XDP_SETUP_PROG: 3815 /* No need to support the SoCs that require to 3816 * do the frame swap because the performance wouldn't be 3817 * better than the skb mode. 3818 */ 3819 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 3820 return -EOPNOTSUPP; 3821 3822 if (!bpf->prog) 3823 xdp_features_clear_redirect_target(dev); 3824 3825 if (is_run) { 3826 napi_disable(&fep->napi); 3827 netif_tx_disable(dev); 3828 } 3829 3830 old_prog = xchg(&fep->xdp_prog, bpf->prog); 3831 if (old_prog) 3832 bpf_prog_put(old_prog); 3833 3834 fec_restart(dev); 3835 3836 if (is_run) { 3837 napi_enable(&fep->napi); 3838 netif_tx_start_all_queues(dev); 3839 } 3840 3841 if (bpf->prog) 3842 xdp_features_set_redirect_target(dev, false); 3843 3844 return 0; 3845 3846 case XDP_SETUP_XSK_POOL: 3847 return -EOPNOTSUPP; 3848 3849 default: 3850 return -EOPNOTSUPP; 3851 } 3852 } 3853 3854 static int 3855 fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index) 3856 { 3857 if (unlikely(index < 0)) 3858 return 0; 3859 3860 return (index % fep->num_tx_queues); 3861 } 3862 3863 static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep, 3864 struct fec_enet_priv_tx_q *txq, 3865 void *frame, u32 dma_sync_len, 3866 bool ndo_xmit) 3867 { 3868 unsigned int index, status, estatus; 3869 struct bufdesc *bdp; 3870 dma_addr_t dma_addr; 3871 int entries_free; 3872 u16 frame_len; 3873 3874 entries_free = fec_enet_get_free_txdesc_num(txq); 3875 if (entries_free < MAX_SKB_FRAGS + 1) { 3876 netdev_err_once(fep->netdev, "NOT enough BD for SG!\n"); 3877 return -EBUSY; 3878 } 3879 3880 /* Fill in a Tx ring entry */ 3881 bdp = txq->bd.cur; 3882 status = fec16_to_cpu(bdp->cbd_sc); 3883 status &= ~BD_ENET_TX_STATS; 3884 3885 index = fec_enet_get_bd_index(bdp, &txq->bd); 3886 3887 if (ndo_xmit) { 3888 struct xdp_frame *xdpf = frame; 3889 3890 dma_addr = dma_map_single(&fep->pdev->dev, xdpf->data, 3891 xdpf->len, DMA_TO_DEVICE); 3892 if (dma_mapping_error(&fep->pdev->dev, dma_addr)) 3893 return -ENOMEM; 3894 3895 frame_len = xdpf->len; 3896 txq->tx_buf[index].buf_p = xdpf; 3897 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_NDO; 3898 } else { 3899 struct xdp_buff *xdpb = frame; 3900 struct page *page; 3901 3902 page = virt_to_page(xdpb->data); 3903 dma_addr = page_pool_get_dma_addr(page) + 3904 (xdpb->data - xdpb->data_hard_start); 3905 dma_sync_single_for_device(&fep->pdev->dev, dma_addr, 3906 dma_sync_len, DMA_BIDIRECTIONAL); 3907 frame_len = xdpb->data_end - xdpb->data; 3908 txq->tx_buf[index].buf_p = page; 3909 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_TX; 3910 } 3911 3912 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 3913 if (fep->bufdesc_ex) 3914 estatus = BD_ENET_TX_INT; 3915 3916 bdp->cbd_bufaddr = cpu_to_fec32(dma_addr); 3917 bdp->cbd_datlen = cpu_to_fec16(frame_len); 3918 3919 if (fep->bufdesc_ex) { 3920 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3921 3922 if (fep->quirks & FEC_QUIRK_HAS_AVB) 3923 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 3924 3925 ebdp->cbd_bdu = 0; 3926 ebdp->cbd_esc = cpu_to_fec32(estatus); 3927 } 3928 3929 /* Make sure the updates to rest of the descriptor are performed before 3930 * transferring ownership. 3931 */ 3932 dma_wmb(); 3933 3934 /* Send it on its way. Tell FEC it's ready, interrupt when done, 3935 * it's the last BD of the frame, and to put the CRC on the end. 3936 */ 3937 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 3938 bdp->cbd_sc = cpu_to_fec16(status); 3939 3940 /* If this was the last BD in the ring, start at the beginning again. */ 3941 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3942 3943 /* Make sure the update to bdp are performed before txq->bd.cur. */ 3944 dma_wmb(); 3945 3946 txq->bd.cur = bdp; 3947 3948 /* Trigger transmission start */ 3949 writel(0, txq->bd.reg_desc_active); 3950 3951 return 0; 3952 } 3953 3954 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 3955 int cpu, struct xdp_buff *xdp, 3956 u32 dma_sync_len) 3957 { 3958 struct fec_enet_priv_tx_q *txq; 3959 struct netdev_queue *nq; 3960 int queue, ret; 3961 3962 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3963 txq = fep->tx_queue[queue]; 3964 nq = netdev_get_tx_queue(fep->netdev, queue); 3965 3966 __netif_tx_lock(nq, cpu); 3967 3968 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3969 txq_trans_cond_update(nq); 3970 ret = fec_enet_txq_xmit_frame(fep, txq, xdp, dma_sync_len, false); 3971 3972 __netif_tx_unlock(nq); 3973 3974 return ret; 3975 } 3976 3977 static int fec_enet_xdp_xmit(struct net_device *dev, 3978 int num_frames, 3979 struct xdp_frame **frames, 3980 u32 flags) 3981 { 3982 struct fec_enet_private *fep = netdev_priv(dev); 3983 struct fec_enet_priv_tx_q *txq; 3984 int cpu = smp_processor_id(); 3985 unsigned int sent_frames = 0; 3986 struct netdev_queue *nq; 3987 unsigned int queue; 3988 int i; 3989 3990 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3991 txq = fep->tx_queue[queue]; 3992 nq = netdev_get_tx_queue(fep->netdev, queue); 3993 3994 __netif_tx_lock(nq, cpu); 3995 3996 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3997 txq_trans_cond_update(nq); 3998 for (i = 0; i < num_frames; i++) { 3999 if (fec_enet_txq_xmit_frame(fep, txq, frames[i], 0, true) < 0) 4000 break; 4001 sent_frames++; 4002 } 4003 4004 __netif_tx_unlock(nq); 4005 4006 return sent_frames; 4007 } 4008 4009 static int fec_hwtstamp_get(struct net_device *ndev, 4010 struct kernel_hwtstamp_config *config) 4011 { 4012 struct fec_enet_private *fep = netdev_priv(ndev); 4013 4014 if (!netif_running(ndev)) 4015 return -EINVAL; 4016 4017 if (!fep->bufdesc_ex) 4018 return -EOPNOTSUPP; 4019 4020 fec_ptp_get(ndev, config); 4021 4022 return 0; 4023 } 4024 4025 static int fec_hwtstamp_set(struct net_device *ndev, 4026 struct kernel_hwtstamp_config *config, 4027 struct netlink_ext_ack *extack) 4028 { 4029 struct fec_enet_private *fep = netdev_priv(ndev); 4030 4031 if (!netif_running(ndev)) 4032 return -EINVAL; 4033 4034 if (!fep->bufdesc_ex) 4035 return -EOPNOTSUPP; 4036 4037 return fec_ptp_set(ndev, config, extack); 4038 } 4039 4040 static int fec_change_mtu(struct net_device *ndev, int new_mtu) 4041 { 4042 struct fec_enet_private *fep = netdev_priv(ndev); 4043 int order; 4044 4045 if (netif_running(ndev)) 4046 return -EBUSY; 4047 4048 order = get_order(new_mtu + ETH_HLEN + ETH_FCS_LEN 4049 + FEC_DRV_RESERVE_SPACE); 4050 fep->rx_frame_size = (PAGE_SIZE << order) - FEC_DRV_RESERVE_SPACE; 4051 fep->pagepool_order = order; 4052 WRITE_ONCE(ndev->mtu, new_mtu); 4053 4054 return 0; 4055 } 4056 4057 static const struct net_device_ops fec_netdev_ops = { 4058 .ndo_open = fec_enet_open, 4059 .ndo_stop = fec_enet_close, 4060 .ndo_start_xmit = fec_enet_start_xmit, 4061 .ndo_select_queue = fec_enet_select_queue, 4062 .ndo_set_rx_mode = set_multicast_list, 4063 .ndo_validate_addr = eth_validate_addr, 4064 .ndo_tx_timeout = fec_timeout, 4065 .ndo_set_mac_address = fec_set_mac_address, 4066 .ndo_change_mtu = fec_change_mtu, 4067 .ndo_eth_ioctl = phy_do_ioctl_running, 4068 .ndo_set_features = fec_set_features, 4069 .ndo_bpf = fec_enet_bpf, 4070 .ndo_xdp_xmit = fec_enet_xdp_xmit, 4071 .ndo_hwtstamp_get = fec_hwtstamp_get, 4072 .ndo_hwtstamp_set = fec_hwtstamp_set, 4073 }; 4074 4075 static const unsigned short offset_des_active_rxq[] = { 4076 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 4077 }; 4078 4079 static const unsigned short offset_des_active_txq[] = { 4080 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 4081 }; 4082 4083 /* 4084 * XXX: We need to clean up on failure exits here. 4085 * 4086 */ 4087 static int fec_enet_init(struct net_device *ndev) 4088 { 4089 struct fec_enet_private *fep = netdev_priv(ndev); 4090 struct bufdesc *cbd_base; 4091 dma_addr_t bd_dma; 4092 int bd_size; 4093 unsigned int i; 4094 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 4095 sizeof(struct bufdesc); 4096 unsigned dsize_log2 = __fls(dsize); 4097 int ret; 4098 4099 WARN_ON(dsize != (1 << dsize_log2)); 4100 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 4101 fep->rx_align = 0xf; 4102 fep->tx_align = 0xf; 4103 #else 4104 fep->rx_align = 0x3; 4105 fep->tx_align = 0x3; 4106 #endif 4107 fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4108 fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4109 fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT; 4110 fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT; 4111 4112 /* Check mask of the streaming and coherent API */ 4113 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 4114 if (ret < 0) { 4115 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 4116 return ret; 4117 } 4118 4119 ret = fec_enet_alloc_queue(ndev); 4120 if (ret) 4121 return ret; 4122 4123 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 4124 4125 /* Allocate memory for buffer descriptors. */ 4126 cbd_base = fec_dmam_alloc(&fep->pdev->dev, bd_size, &bd_dma, 4127 GFP_KERNEL); 4128 if (!cbd_base) { 4129 ret = -ENOMEM; 4130 goto free_queue_mem; 4131 } 4132 4133 /* Get the Ethernet address */ 4134 ret = fec_get_mac(ndev); 4135 if (ret) 4136 goto free_queue_mem; 4137 4138 /* Set receive and transmit descriptor base. */ 4139 for (i = 0; i < fep->num_rx_queues; i++) { 4140 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 4141 unsigned size = dsize * rxq->bd.ring_size; 4142 4143 rxq->bd.qid = i; 4144 rxq->bd.base = cbd_base; 4145 rxq->bd.cur = cbd_base; 4146 rxq->bd.dma = bd_dma; 4147 rxq->bd.dsize = dsize; 4148 rxq->bd.dsize_log2 = dsize_log2; 4149 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 4150 bd_dma += size; 4151 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4152 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4153 } 4154 4155 for (i = 0; i < fep->num_tx_queues; i++) { 4156 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 4157 unsigned size = dsize * txq->bd.ring_size; 4158 4159 txq->bd.qid = i; 4160 txq->bd.base = cbd_base; 4161 txq->bd.cur = cbd_base; 4162 txq->bd.dma = bd_dma; 4163 txq->bd.dsize = dsize; 4164 txq->bd.dsize_log2 = dsize_log2; 4165 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 4166 bd_dma += size; 4167 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4168 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4169 } 4170 4171 4172 /* The FEC Ethernet specific entries in the device structure */ 4173 ndev->watchdog_timeo = TX_TIMEOUT; 4174 ndev->netdev_ops = &fec_netdev_ops; 4175 ndev->ethtool_ops = &fec_enet_ethtool_ops; 4176 4177 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 4178 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi); 4179 4180 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 4181 /* enable hw VLAN support */ 4182 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 4183 4184 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 4185 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS); 4186 4187 /* enable hw accelerator */ 4188 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 4189 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 4190 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 4191 } 4192 4193 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 4194 fep->tx_align = 0; 4195 fep->rx_align = 0x3f; 4196 } 4197 4198 ndev->hw_features = ndev->features; 4199 4200 if (!(fep->quirks & FEC_QUIRK_SWAP_FRAME)) 4201 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 4202 NETDEV_XDP_ACT_REDIRECT; 4203 4204 fec_restart(ndev); 4205 4206 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 4207 fec_enet_clear_ethtool_stats(ndev); 4208 else 4209 fec_enet_update_ethtool_stats(ndev); 4210 4211 return 0; 4212 4213 free_queue_mem: 4214 fec_enet_free_queue(ndev); 4215 return ret; 4216 } 4217 4218 static void fec_enet_deinit(struct net_device *ndev) 4219 { 4220 struct fec_enet_private *fep = netdev_priv(ndev); 4221 4222 netif_napi_del(&fep->napi); 4223 fec_enet_free_queue(ndev); 4224 } 4225 4226 #ifdef CONFIG_OF 4227 static int fec_reset_phy(struct platform_device *pdev) 4228 { 4229 struct gpio_desc *phy_reset; 4230 int msec = 1, phy_post_delay = 0; 4231 struct device_node *np = pdev->dev.of_node; 4232 int err; 4233 4234 if (!np) 4235 return 0; 4236 4237 err = of_property_read_u32(np, "phy-reset-duration", &msec); 4238 /* A sane reset duration should not be longer than 1s */ 4239 if (!err && msec > 1000) 4240 msec = 1; 4241 4242 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 4243 /* valid reset duration should be less than 1s */ 4244 if (!err && phy_post_delay > 1000) 4245 return -EINVAL; 4246 4247 phy_reset = devm_gpiod_get_optional(&pdev->dev, "phy-reset", 4248 GPIOD_OUT_HIGH); 4249 if (IS_ERR(phy_reset)) 4250 return dev_err_probe(&pdev->dev, PTR_ERR(phy_reset), 4251 "failed to get phy-reset-gpios\n"); 4252 4253 if (!phy_reset) 4254 return 0; 4255 4256 if (msec > 20) 4257 msleep(msec); 4258 else 4259 usleep_range(msec * 1000, msec * 1000 + 1000); 4260 4261 gpiod_set_value_cansleep(phy_reset, 0); 4262 4263 if (!phy_post_delay) 4264 return 0; 4265 4266 if (phy_post_delay > 20) 4267 msleep(phy_post_delay); 4268 else 4269 usleep_range(phy_post_delay * 1000, 4270 phy_post_delay * 1000 + 1000); 4271 4272 return 0; 4273 } 4274 #else /* CONFIG_OF */ 4275 static int fec_reset_phy(struct platform_device *pdev) 4276 { 4277 /* 4278 * In case of platform probe, the reset has been done 4279 * by machine code. 4280 */ 4281 return 0; 4282 } 4283 #endif /* CONFIG_OF */ 4284 4285 static void 4286 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 4287 { 4288 struct device_node *np = pdev->dev.of_node; 4289 4290 *num_tx = *num_rx = 1; 4291 4292 if (!np || !of_device_is_available(np)) 4293 return; 4294 4295 /* parse the num of tx and rx queues */ 4296 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 4297 4298 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 4299 4300 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 4301 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 4302 *num_tx); 4303 *num_tx = 1; 4304 return; 4305 } 4306 4307 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 4308 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 4309 *num_rx); 4310 *num_rx = 1; 4311 return; 4312 } 4313 4314 } 4315 4316 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 4317 { 4318 int irq_cnt = platform_irq_count(pdev); 4319 4320 if (irq_cnt > FEC_IRQ_NUM) 4321 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 4322 else if (irq_cnt == 2) 4323 irq_cnt = 1; /* last for pps */ 4324 else if (irq_cnt <= 0) 4325 irq_cnt = 1; /* At least 1 irq is needed */ 4326 return irq_cnt; 4327 } 4328 4329 static void fec_enet_get_wakeup_irq(struct platform_device *pdev) 4330 { 4331 struct net_device *ndev = platform_get_drvdata(pdev); 4332 struct fec_enet_private *fep = netdev_priv(ndev); 4333 4334 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) 4335 fep->wake_irq = fep->irq[2]; 4336 else 4337 fep->wake_irq = fep->irq[0]; 4338 } 4339 4340 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 4341 struct device_node *np) 4342 { 4343 struct device_node *gpr_np; 4344 u32 out_val[3]; 4345 int ret = 0; 4346 4347 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 4348 if (!gpr_np) 4349 return 0; 4350 4351 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 4352 ARRAY_SIZE(out_val)); 4353 if (ret) { 4354 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 4355 goto out; 4356 } 4357 4358 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 4359 if (IS_ERR(fep->stop_gpr.gpr)) { 4360 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 4361 ret = PTR_ERR(fep->stop_gpr.gpr); 4362 fep->stop_gpr.gpr = NULL; 4363 goto out; 4364 } 4365 4366 fep->stop_gpr.reg = out_val[1]; 4367 fep->stop_gpr.bit = out_val[2]; 4368 4369 out: 4370 of_node_put(gpr_np); 4371 4372 return ret; 4373 } 4374 4375 static int 4376 fec_probe(struct platform_device *pdev) 4377 { 4378 struct fec_enet_private *fep; 4379 struct fec_platform_data *pdata; 4380 phy_interface_t interface; 4381 struct net_device *ndev; 4382 int i, irq, ret = 0; 4383 static int dev_id; 4384 struct device_node *np = pdev->dev.of_node, *phy_node; 4385 int num_tx_qs; 4386 int num_rx_qs; 4387 char irq_name[8]; 4388 int irq_cnt; 4389 const struct fec_devinfo *dev_info; 4390 4391 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 4392 4393 /* Init network device */ 4394 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 4395 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 4396 if (!ndev) 4397 return -ENOMEM; 4398 4399 SET_NETDEV_DEV(ndev, &pdev->dev); 4400 4401 /* setup board info structure */ 4402 fep = netdev_priv(ndev); 4403 4404 dev_info = device_get_match_data(&pdev->dev); 4405 if (!dev_info) 4406 dev_info = (const struct fec_devinfo *)pdev->id_entry->driver_data; 4407 if (dev_info) 4408 fep->quirks = dev_info->quirks; 4409 4410 fep->netdev = ndev; 4411 fep->num_rx_queues = num_rx_qs; 4412 fep->num_tx_queues = num_tx_qs; 4413 4414 #if !defined(CONFIG_M5272) 4415 /* default enable pause frame auto negotiation */ 4416 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 4417 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 4418 #endif 4419 4420 /* Select default pin state */ 4421 pinctrl_pm_select_default_state(&pdev->dev); 4422 4423 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 4424 if (IS_ERR(fep->hwp)) { 4425 ret = PTR_ERR(fep->hwp); 4426 goto failed_ioremap; 4427 } 4428 4429 fep->pdev = pdev; 4430 fep->dev_id = dev_id++; 4431 4432 platform_set_drvdata(pdev, ndev); 4433 4434 if ((of_machine_is_compatible("fsl,imx6q") || 4435 of_machine_is_compatible("fsl,imx6dl")) && 4436 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 4437 fep->quirks |= FEC_QUIRK_ERR006687; 4438 4439 ret = fec_enet_ipc_handle_init(fep); 4440 if (ret) 4441 goto failed_ipc_init; 4442 4443 if (of_property_read_bool(np, "fsl,magic-packet")) 4444 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 4445 4446 ret = fec_enet_init_stop_mode(fep, np); 4447 if (ret) 4448 goto failed_stop_mode; 4449 4450 phy_node = of_parse_phandle(np, "phy-handle", 0); 4451 if (!phy_node && of_phy_is_fixed_link(np)) { 4452 ret = of_phy_register_fixed_link(np); 4453 if (ret < 0) { 4454 dev_err(&pdev->dev, 4455 "broken fixed-link specification\n"); 4456 goto failed_phy; 4457 } 4458 phy_node = of_node_get(np); 4459 } 4460 fep->phy_node = phy_node; 4461 4462 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 4463 if (ret) { 4464 pdata = dev_get_platdata(&pdev->dev); 4465 if (pdata) 4466 fep->phy_interface = pdata->phy; 4467 else 4468 fep->phy_interface = PHY_INTERFACE_MODE_MII; 4469 } else { 4470 fep->phy_interface = interface; 4471 } 4472 4473 ret = fec_enet_parse_rgmii_delay(fep, np); 4474 if (ret) 4475 goto failed_rgmii_delay; 4476 4477 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 4478 if (IS_ERR(fep->clk_ipg)) { 4479 ret = PTR_ERR(fep->clk_ipg); 4480 goto failed_clk; 4481 } 4482 4483 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 4484 if (IS_ERR(fep->clk_ahb)) { 4485 ret = PTR_ERR(fep->clk_ahb); 4486 goto failed_clk; 4487 } 4488 4489 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 4490 4491 /* enet_out is optional, depends on board */ 4492 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out"); 4493 if (IS_ERR(fep->clk_enet_out)) { 4494 ret = PTR_ERR(fep->clk_enet_out); 4495 goto failed_clk; 4496 } 4497 4498 fep->ptp_clk_on = false; 4499 mutex_init(&fep->ptp_clk_mutex); 4500 4501 /* clk_ref is optional, depends on board */ 4502 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref"); 4503 if (IS_ERR(fep->clk_ref)) { 4504 ret = PTR_ERR(fep->clk_ref); 4505 goto failed_clk; 4506 } 4507 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); 4508 4509 /* clk_2x_txclk is optional, depends on board */ 4510 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { 4511 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); 4512 if (IS_ERR(fep->clk_2x_txclk)) 4513 fep->clk_2x_txclk = NULL; 4514 } 4515 4516 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 4517 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 4518 if (IS_ERR(fep->clk_ptp)) { 4519 fep->clk_ptp = NULL; 4520 fep->bufdesc_ex = false; 4521 } 4522 4523 ret = fec_enet_clk_enable(ndev, true); 4524 if (ret) 4525 goto failed_clk; 4526 4527 ret = clk_prepare_enable(fep->clk_ipg); 4528 if (ret) 4529 goto failed_clk_ipg; 4530 ret = clk_prepare_enable(fep->clk_ahb); 4531 if (ret) 4532 goto failed_clk_ahb; 4533 4534 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 4535 if (!IS_ERR(fep->reg_phy)) { 4536 ret = regulator_enable(fep->reg_phy); 4537 if (ret) { 4538 dev_err(&pdev->dev, 4539 "Failed to enable phy regulator: %d\n", ret); 4540 goto failed_regulator; 4541 } 4542 } else { 4543 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 4544 ret = -EPROBE_DEFER; 4545 goto failed_regulator; 4546 } 4547 fep->reg_phy = NULL; 4548 } 4549 4550 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 4551 pm_runtime_use_autosuspend(&pdev->dev); 4552 pm_runtime_get_noresume(&pdev->dev); 4553 pm_runtime_set_active(&pdev->dev); 4554 pm_runtime_enable(&pdev->dev); 4555 4556 ret = fec_reset_phy(pdev); 4557 if (ret) 4558 goto failed_reset; 4559 4560 irq_cnt = fec_enet_get_irq_cnt(pdev); 4561 if (fep->bufdesc_ex) 4562 fec_ptp_init(pdev, irq_cnt); 4563 4564 ret = fec_enet_init(ndev); 4565 if (ret) 4566 goto failed_init; 4567 4568 for (i = 0; i < irq_cnt; i++) { 4569 snprintf(irq_name, sizeof(irq_name), "int%d", i); 4570 irq = platform_get_irq_byname_optional(pdev, irq_name); 4571 if (irq < 0) 4572 irq = platform_get_irq(pdev, i); 4573 if (irq < 0) { 4574 ret = irq; 4575 goto failed_irq; 4576 } 4577 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 4578 0, pdev->name, ndev); 4579 if (ret) 4580 goto failed_irq; 4581 4582 fep->irq[i] = irq; 4583 } 4584 4585 /* Decide which interrupt line is wakeup capable */ 4586 fec_enet_get_wakeup_irq(pdev); 4587 4588 ret = fec_enet_mii_init(pdev); 4589 if (ret) 4590 goto failed_mii_init; 4591 4592 /* Carrier starts down, phylib will bring it up */ 4593 netif_carrier_off(ndev); 4594 fec_enet_clk_enable(ndev, false); 4595 pinctrl_pm_select_sleep_state(&pdev->dev); 4596 4597 fep->pagepool_order = 0; 4598 fep->rx_frame_size = FEC_ENET_RX_FRSIZE; 4599 4600 if (fep->quirks & FEC_QUIRK_JUMBO_FRAME) 4601 fep->max_buf_size = MAX_JUMBO_BUF_SIZE; 4602 else 4603 fep->max_buf_size = PKT_MAXBUF_SIZE; 4604 4605 ndev->max_mtu = fep->max_buf_size - ETH_HLEN - ETH_FCS_LEN; 4606 4607 ret = register_netdev(ndev); 4608 if (ret) 4609 goto failed_register; 4610 4611 device_init_wakeup(&ndev->dev, fep->wol_flag & 4612 FEC_WOL_HAS_MAGIC_PACKET); 4613 4614 if (fep->bufdesc_ex && fep->ptp_clock) 4615 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 4616 4617 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 4618 4619 pm_runtime_mark_last_busy(&pdev->dev); 4620 pm_runtime_put_autosuspend(&pdev->dev); 4621 4622 return 0; 4623 4624 failed_register: 4625 fec_enet_mii_remove(fep); 4626 failed_mii_init: 4627 failed_irq: 4628 fec_enet_deinit(ndev); 4629 failed_init: 4630 fec_ptp_stop(pdev); 4631 failed_reset: 4632 pm_runtime_put_noidle(&pdev->dev); 4633 pm_runtime_disable(&pdev->dev); 4634 if (fep->reg_phy) 4635 regulator_disable(fep->reg_phy); 4636 failed_regulator: 4637 clk_disable_unprepare(fep->clk_ahb); 4638 failed_clk_ahb: 4639 clk_disable_unprepare(fep->clk_ipg); 4640 failed_clk_ipg: 4641 fec_enet_clk_enable(ndev, false); 4642 failed_clk: 4643 failed_rgmii_delay: 4644 if (of_phy_is_fixed_link(np)) 4645 of_phy_deregister_fixed_link(np); 4646 of_node_put(phy_node); 4647 failed_stop_mode: 4648 failed_ipc_init: 4649 failed_phy: 4650 dev_id--; 4651 failed_ioremap: 4652 free_netdev(ndev); 4653 4654 return ret; 4655 } 4656 4657 static void 4658 fec_drv_remove(struct platform_device *pdev) 4659 { 4660 struct net_device *ndev = platform_get_drvdata(pdev); 4661 struct fec_enet_private *fep = netdev_priv(ndev); 4662 struct device_node *np = pdev->dev.of_node; 4663 int ret; 4664 4665 ret = pm_runtime_get_sync(&pdev->dev); 4666 if (ret < 0) 4667 dev_err(&pdev->dev, 4668 "Failed to resume device in remove callback (%pe)\n", 4669 ERR_PTR(ret)); 4670 4671 cancel_work_sync(&fep->tx_timeout_work); 4672 fec_ptp_stop(pdev); 4673 unregister_netdev(ndev); 4674 fec_enet_mii_remove(fep); 4675 if (fep->reg_phy) 4676 regulator_disable(fep->reg_phy); 4677 4678 if (of_phy_is_fixed_link(np)) 4679 of_phy_deregister_fixed_link(np); 4680 of_node_put(fep->phy_node); 4681 4682 /* After pm_runtime_get_sync() failed, the clks are still off, so skip 4683 * disabling them again. 4684 */ 4685 if (ret >= 0) { 4686 clk_disable_unprepare(fep->clk_ahb); 4687 clk_disable_unprepare(fep->clk_ipg); 4688 } 4689 pm_runtime_put_noidle(&pdev->dev); 4690 pm_runtime_disable(&pdev->dev); 4691 4692 fec_enet_deinit(ndev); 4693 free_netdev(ndev); 4694 } 4695 4696 static int fec_suspend(struct device *dev) 4697 { 4698 struct net_device *ndev = dev_get_drvdata(dev); 4699 struct fec_enet_private *fep = netdev_priv(ndev); 4700 int ret; 4701 4702 rtnl_lock(); 4703 if (netif_running(ndev)) { 4704 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 4705 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 4706 phy_stop(ndev->phydev); 4707 napi_disable(&fep->napi); 4708 netif_tx_lock_bh(ndev); 4709 netif_device_detach(ndev); 4710 netif_tx_unlock_bh(ndev); 4711 fec_stop(ndev); 4712 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4713 fec_irqs_disable(ndev); 4714 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 4715 } else { 4716 fec_irqs_disable_except_wakeup(ndev); 4717 if (fep->wake_irq > 0) { 4718 disable_irq(fep->wake_irq); 4719 enable_irq_wake(fep->wake_irq); 4720 } 4721 fec_enet_stop_mode(fep, true); 4722 } 4723 /* It's safe to disable clocks since interrupts are masked */ 4724 fec_enet_clk_enable(ndev, false); 4725 4726 fep->rpm_active = !pm_runtime_status_suspended(dev); 4727 if (fep->rpm_active) { 4728 ret = pm_runtime_force_suspend(dev); 4729 if (ret < 0) { 4730 rtnl_unlock(); 4731 return ret; 4732 } 4733 } 4734 } 4735 rtnl_unlock(); 4736 4737 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4738 regulator_disable(fep->reg_phy); 4739 4740 /* SOC supply clock to phy, when clock is disabled, phy link down 4741 * SOC control phy regulator, when regulator is disabled, phy link down 4742 */ 4743 if (fep->clk_enet_out || fep->reg_phy) 4744 fep->link = 0; 4745 4746 return 0; 4747 } 4748 4749 static int fec_resume(struct device *dev) 4750 { 4751 struct net_device *ndev = dev_get_drvdata(dev); 4752 struct fec_enet_private *fep = netdev_priv(ndev); 4753 int ret; 4754 int val; 4755 4756 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4757 ret = regulator_enable(fep->reg_phy); 4758 if (ret) 4759 return ret; 4760 } 4761 4762 rtnl_lock(); 4763 if (netif_running(ndev)) { 4764 if (fep->rpm_active) 4765 pm_runtime_force_resume(dev); 4766 4767 ret = fec_enet_clk_enable(ndev, true); 4768 if (ret) { 4769 rtnl_unlock(); 4770 goto failed_clk; 4771 } 4772 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 4773 fec_enet_stop_mode(fep, false); 4774 if (fep->wake_irq) { 4775 disable_irq_wake(fep->wake_irq); 4776 enable_irq(fep->wake_irq); 4777 } 4778 4779 val = readl(fep->hwp + FEC_ECNTRL); 4780 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 4781 writel(val, fep->hwp + FEC_ECNTRL); 4782 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 4783 } else { 4784 pinctrl_pm_select_default_state(&fep->pdev->dev); 4785 } 4786 fec_restart(ndev); 4787 netif_tx_lock_bh(ndev); 4788 netif_device_attach(ndev); 4789 netif_tx_unlock_bh(ndev); 4790 napi_enable(&fep->napi); 4791 phy_init_hw(ndev->phydev); 4792 phy_start(ndev->phydev); 4793 } 4794 rtnl_unlock(); 4795 4796 return 0; 4797 4798 failed_clk: 4799 if (fep->reg_phy) 4800 regulator_disable(fep->reg_phy); 4801 return ret; 4802 } 4803 4804 static int fec_runtime_suspend(struct device *dev) 4805 { 4806 struct net_device *ndev = dev_get_drvdata(dev); 4807 struct fec_enet_private *fep = netdev_priv(ndev); 4808 4809 clk_disable_unprepare(fep->clk_ahb); 4810 clk_disable_unprepare(fep->clk_ipg); 4811 4812 return 0; 4813 } 4814 4815 static int fec_runtime_resume(struct device *dev) 4816 { 4817 struct net_device *ndev = dev_get_drvdata(dev); 4818 struct fec_enet_private *fep = netdev_priv(ndev); 4819 int ret; 4820 4821 ret = clk_prepare_enable(fep->clk_ahb); 4822 if (ret) 4823 return ret; 4824 ret = clk_prepare_enable(fep->clk_ipg); 4825 if (ret) 4826 goto failed_clk_ipg; 4827 4828 return 0; 4829 4830 failed_clk_ipg: 4831 clk_disable_unprepare(fep->clk_ahb); 4832 return ret; 4833 } 4834 4835 static const struct dev_pm_ops fec_pm_ops = { 4836 SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 4837 RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 4838 }; 4839 4840 static struct platform_driver fec_driver = { 4841 .driver = { 4842 .name = DRIVER_NAME, 4843 .pm = pm_ptr(&fec_pm_ops), 4844 .of_match_table = fec_dt_ids, 4845 .suppress_bind_attrs = true, 4846 }, 4847 .id_table = fec_devtype, 4848 .probe = fec_probe, 4849 .remove = fec_drv_remove, 4850 }; 4851 4852 module_platform_driver(fec_driver); 4853 4854 MODULE_DESCRIPTION("NXP Fast Ethernet Controller (FEC) driver"); 4855 MODULE_LICENSE("GPL"); 4856