1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/page_pool/helpers.h> 42 #include <net/selftests.h> 43 #include <net/tso.h> 44 #include <linux/tcp.h> 45 #include <linux/udp.h> 46 #include <linux/icmp.h> 47 #include <linux/spinlock.h> 48 #include <linux/workqueue.h> 49 #include <linux/bitops.h> 50 #include <linux/io.h> 51 #include <linux/irq.h> 52 #include <linux/clk.h> 53 #include <linux/crc32.h> 54 #include <linux/platform_device.h> 55 #include <linux/property.h> 56 #include <linux/mdio.h> 57 #include <linux/phy.h> 58 #include <linux/fec.h> 59 #include <linux/of.h> 60 #include <linux/of_mdio.h> 61 #include <linux/of_net.h> 62 #include <linux/regulator/consumer.h> 63 #include <linux/if_vlan.h> 64 #include <linux/pinctrl/consumer.h> 65 #include <linux/gpio/consumer.h> 66 #include <linux/prefetch.h> 67 #include <linux/mfd/syscon.h> 68 #include <linux/regmap.h> 69 #include <soc/imx/cpuidle.h> 70 #include <linux/filter.h> 71 #include <linux/bpf.h> 72 #include <linux/bpf_trace.h> 73 74 #include <asm/cacheflush.h> 75 76 #include "fec.h" 77 78 static void set_multicast_list(struct net_device *ndev); 79 static void fec_enet_itr_coal_set(struct net_device *ndev); 80 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 81 int cpu, struct xdp_buff *xdp, 82 u32 dma_sync_len); 83 84 #define DRIVER_NAME "fec" 85 86 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 87 88 #define FEC_ENET_RSEM_V 0x84 89 #define FEC_ENET_RSFL_V 16 90 #define FEC_ENET_RAEM_V 0x8 91 #define FEC_ENET_RAFL_V 0x8 92 #define FEC_ENET_OPD_V 0xFFF0 93 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 94 95 #define FEC_ENET_XDP_PASS 0 96 #define FEC_ENET_XDP_CONSUMED BIT(0) 97 #define FEC_ENET_XDP_TX BIT(1) 98 #define FEC_ENET_XDP_REDIR BIT(2) 99 100 struct fec_devinfo { 101 u32 quirks; 102 }; 103 104 static const struct fec_devinfo fec_imx25_info = { 105 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 106 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_HAS_MDIO_C45, 107 }; 108 109 static const struct fec_devinfo fec_imx27_info = { 110 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG | 111 FEC_QUIRK_HAS_MDIO_C45, 112 }; 113 114 static const struct fec_devinfo fec_imx28_info = { 115 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 116 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 117 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 118 FEC_QUIRK_NO_HARD_RESET | FEC_QUIRK_HAS_MDIO_C45, 119 }; 120 121 static const struct fec_devinfo fec_imx6q_info = { 122 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 125 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII | 126 FEC_QUIRK_HAS_PMQOS | FEC_QUIRK_HAS_MDIO_C45, 127 }; 128 129 static const struct fec_devinfo fec_mvf600_info = { 130 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC | 131 FEC_QUIRK_HAS_MDIO_C45, 132 }; 133 134 static const struct fec_devinfo fec_imx6x_info = { 135 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 136 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 137 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 138 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 139 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 140 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 141 FEC_QUIRK_HAS_MDIO_C45, 142 }; 143 144 static const struct fec_devinfo fec_imx6ul_info = { 145 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 146 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 147 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 148 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 149 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII | 150 FEC_QUIRK_HAS_MDIO_C45, 151 }; 152 153 static const struct fec_devinfo fec_imx8mq_info = { 154 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 155 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 156 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 157 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 158 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 159 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 160 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2 | 161 FEC_QUIRK_HAS_MDIO_C45, 162 }; 163 164 static const struct fec_devinfo fec_imx8qm_info = { 165 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 166 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 167 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 168 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 169 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 170 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 171 FEC_QUIRK_DELAYED_CLKS_SUPPORT | FEC_QUIRK_HAS_MDIO_C45, 172 }; 173 174 static const struct fec_devinfo fec_s32v234_info = { 175 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 176 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 177 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 178 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 179 FEC_QUIRK_HAS_MDIO_C45, 180 }; 181 182 static struct platform_device_id fec_devtype[] = { 183 { 184 /* keep it for coldfire */ 185 .name = DRIVER_NAME, 186 .driver_data = 0, 187 }, { 188 /* sentinel */ 189 } 190 }; 191 MODULE_DEVICE_TABLE(platform, fec_devtype); 192 193 static const struct of_device_id fec_dt_ids[] = { 194 { .compatible = "fsl,imx25-fec", .data = &fec_imx25_info, }, 195 { .compatible = "fsl,imx27-fec", .data = &fec_imx27_info, }, 196 { .compatible = "fsl,imx28-fec", .data = &fec_imx28_info, }, 197 { .compatible = "fsl,imx6q-fec", .data = &fec_imx6q_info, }, 198 { .compatible = "fsl,mvf600-fec", .data = &fec_mvf600_info, }, 199 { .compatible = "fsl,imx6sx-fec", .data = &fec_imx6x_info, }, 200 { .compatible = "fsl,imx6ul-fec", .data = &fec_imx6ul_info, }, 201 { .compatible = "fsl,imx8mq-fec", .data = &fec_imx8mq_info, }, 202 { .compatible = "fsl,imx8qm-fec", .data = &fec_imx8qm_info, }, 203 { .compatible = "fsl,s32v234-fec", .data = &fec_s32v234_info, }, 204 { /* sentinel */ } 205 }; 206 MODULE_DEVICE_TABLE(of, fec_dt_ids); 207 208 static unsigned char macaddr[ETH_ALEN]; 209 module_param_array(macaddr, byte, NULL, 0); 210 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 211 212 #if defined(CONFIG_M5272) 213 /* 214 * Some hardware gets it MAC address out of local flash memory. 215 * if this is non-zero then assume it is the address to get MAC from. 216 */ 217 #if defined(CONFIG_NETtel) 218 #define FEC_FLASHMAC 0xf0006006 219 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 220 #define FEC_FLASHMAC 0xf0006000 221 #elif defined(CONFIG_CANCam) 222 #define FEC_FLASHMAC 0xf0020000 223 #elif defined (CONFIG_M5272C3) 224 #define FEC_FLASHMAC (0xffe04000 + 4) 225 #elif defined(CONFIG_MOD5272) 226 #define FEC_FLASHMAC 0xffc0406b 227 #else 228 #define FEC_FLASHMAC 0 229 #endif 230 #endif /* CONFIG_M5272 */ 231 232 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 233 * 234 * 2048 byte skbufs are allocated. However, alignment requirements 235 * varies between FEC variants. Worst case is 64, so round down by 64. 236 */ 237 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 238 #define PKT_MINBUF_SIZE 64 239 240 /* FEC receive acceleration */ 241 #define FEC_RACC_IPDIS BIT(1) 242 #define FEC_RACC_PRODIS BIT(2) 243 #define FEC_RACC_SHIFT16 BIT(7) 244 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 245 246 /* MIB Control Register */ 247 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 248 249 /* 250 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 251 * size bits. Other FEC hardware does not, so we need to take that into 252 * account when setting it. 253 */ 254 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 255 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 256 defined(CONFIG_ARM64) 257 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 258 #else 259 #define OPT_FRAME_SIZE 0 260 #endif 261 262 /* FEC MII MMFR bits definition */ 263 #define FEC_MMFR_ST (1 << 30) 264 #define FEC_MMFR_ST_C45 (0) 265 #define FEC_MMFR_OP_READ (2 << 28) 266 #define FEC_MMFR_OP_READ_C45 (3 << 28) 267 #define FEC_MMFR_OP_WRITE (1 << 28) 268 #define FEC_MMFR_OP_ADDR_WRITE (0) 269 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 270 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 271 #define FEC_MMFR_TA (2 << 16) 272 #define FEC_MMFR_DATA(v) (v & 0xffff) 273 /* FEC ECR bits definition */ 274 #define FEC_ECR_RESET BIT(0) 275 #define FEC_ECR_ETHEREN BIT(1) 276 #define FEC_ECR_MAGICEN BIT(2) 277 #define FEC_ECR_SLEEP BIT(3) 278 #define FEC_ECR_EN1588 BIT(4) 279 #define FEC_ECR_BYTESWP BIT(8) 280 /* FEC RCR bits definition */ 281 #define FEC_RCR_LOOP BIT(0) 282 #define FEC_RCR_HALFDPX BIT(1) 283 #define FEC_RCR_MII BIT(2) 284 #define FEC_RCR_PROMISC BIT(3) 285 #define FEC_RCR_BC_REJ BIT(4) 286 #define FEC_RCR_FLOWCTL BIT(5) 287 #define FEC_RCR_RMII BIT(8) 288 #define FEC_RCR_10BASET BIT(9) 289 /* TX WMARK bits */ 290 #define FEC_TXWMRK_STRFWD BIT(8) 291 292 #define FEC_MII_TIMEOUT 30000 /* us */ 293 294 /* Transmitter timeout */ 295 #define TX_TIMEOUT (2 * HZ) 296 297 #define FEC_PAUSE_FLAG_AUTONEG 0x1 298 #define FEC_PAUSE_FLAG_ENABLE 0x2 299 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 300 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 301 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 302 303 /* Max number of allowed TCP segments for software TSO */ 304 #define FEC_MAX_TSO_SEGS 100 305 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 306 307 #define IS_TSO_HEADER(txq, addr) \ 308 ((addr >= txq->tso_hdrs_dma) && \ 309 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 310 311 static int mii_cnt; 312 313 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 314 struct bufdesc_prop *bd) 315 { 316 return (bdp >= bd->last) ? bd->base 317 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 318 } 319 320 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 321 struct bufdesc_prop *bd) 322 { 323 return (bdp <= bd->base) ? bd->last 324 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 325 } 326 327 static int fec_enet_get_bd_index(struct bufdesc *bdp, 328 struct bufdesc_prop *bd) 329 { 330 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 331 } 332 333 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 334 { 335 int entries; 336 337 entries = (((const char *)txq->dirty_tx - 338 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 339 340 return entries >= 0 ? entries : entries + txq->bd.ring_size; 341 } 342 343 static void swap_buffer(void *bufaddr, int len) 344 { 345 int i; 346 unsigned int *buf = bufaddr; 347 348 for (i = 0; i < len; i += 4, buf++) 349 swab32s(buf); 350 } 351 352 static void fec_dump(struct net_device *ndev) 353 { 354 struct fec_enet_private *fep = netdev_priv(ndev); 355 struct bufdesc *bdp; 356 struct fec_enet_priv_tx_q *txq; 357 int index = 0; 358 359 netdev_info(ndev, "TX ring dump\n"); 360 pr_info("Nr SC addr len SKB\n"); 361 362 txq = fep->tx_queue[0]; 363 bdp = txq->bd.base; 364 365 do { 366 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 367 index, 368 bdp == txq->bd.cur ? 'S' : ' ', 369 bdp == txq->dirty_tx ? 'H' : ' ', 370 fec16_to_cpu(bdp->cbd_sc), 371 fec32_to_cpu(bdp->cbd_bufaddr), 372 fec16_to_cpu(bdp->cbd_datlen), 373 txq->tx_buf[index].buf_p); 374 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 375 index++; 376 } while (bdp != txq->bd.base); 377 } 378 379 /* 380 * Coldfire does not support DMA coherent allocations, and has historically used 381 * a band-aid with a manual flush in fec_enet_rx_queue. 382 */ 383 #if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA) 384 static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, 385 gfp_t gfp) 386 { 387 return dma_alloc_noncoherent(dev, size, handle, DMA_BIDIRECTIONAL, gfp); 388 } 389 390 static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr, 391 dma_addr_t handle) 392 { 393 dma_free_noncoherent(dev, size, cpu_addr, handle, DMA_BIDIRECTIONAL); 394 } 395 #else /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */ 396 static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, 397 gfp_t gfp) 398 { 399 return dma_alloc_coherent(dev, size, handle, gfp); 400 } 401 402 static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr, 403 dma_addr_t handle) 404 { 405 dma_free_coherent(dev, size, cpu_addr, handle); 406 } 407 #endif /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */ 408 409 struct fec_dma_devres { 410 size_t size; 411 void *vaddr; 412 dma_addr_t dma_handle; 413 }; 414 415 static void fec_dmam_release(struct device *dev, void *res) 416 { 417 struct fec_dma_devres *this = res; 418 419 fec_dma_free(dev, this->size, this->vaddr, this->dma_handle); 420 } 421 422 static void *fec_dmam_alloc(struct device *dev, size_t size, dma_addr_t *handle, 423 gfp_t gfp) 424 { 425 struct fec_dma_devres *dr; 426 void *vaddr; 427 428 dr = devres_alloc(fec_dmam_release, sizeof(*dr), gfp); 429 if (!dr) 430 return NULL; 431 vaddr = fec_dma_alloc(dev, size, handle, gfp); 432 if (!vaddr) { 433 devres_free(dr); 434 return NULL; 435 } 436 dr->vaddr = vaddr; 437 dr->dma_handle = *handle; 438 dr->size = size; 439 devres_add(dev, dr); 440 return vaddr; 441 } 442 443 static inline bool is_ipv4_pkt(struct sk_buff *skb) 444 { 445 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 446 } 447 448 static int 449 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 450 { 451 /* Only run for packets requiring a checksum. */ 452 if (skb->ip_summed != CHECKSUM_PARTIAL) 453 return 0; 454 455 if (unlikely(skb_cow_head(skb, 0))) 456 return -1; 457 458 if (is_ipv4_pkt(skb)) 459 ip_hdr(skb)->check = 0; 460 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 461 462 return 0; 463 } 464 465 static int 466 fec_enet_create_page_pool(struct fec_enet_private *fep, 467 struct fec_enet_priv_rx_q *rxq, int size) 468 { 469 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 470 struct page_pool_params pp_params = { 471 .order = 0, 472 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 473 .pool_size = size, 474 .nid = dev_to_node(&fep->pdev->dev), 475 .dev = &fep->pdev->dev, 476 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 477 .offset = FEC_ENET_XDP_HEADROOM, 478 .max_len = FEC_ENET_RX_FRSIZE, 479 }; 480 int err; 481 482 rxq->page_pool = page_pool_create(&pp_params); 483 if (IS_ERR(rxq->page_pool)) { 484 err = PTR_ERR(rxq->page_pool); 485 rxq->page_pool = NULL; 486 return err; 487 } 488 489 err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0); 490 if (err < 0) 491 goto err_free_pp; 492 493 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 494 rxq->page_pool); 495 if (err) 496 goto err_unregister_rxq; 497 498 return 0; 499 500 err_unregister_rxq: 501 xdp_rxq_info_unreg(&rxq->xdp_rxq); 502 err_free_pp: 503 page_pool_destroy(rxq->page_pool); 504 rxq->page_pool = NULL; 505 return err; 506 } 507 508 static struct bufdesc * 509 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 510 struct sk_buff *skb, 511 struct net_device *ndev) 512 { 513 struct fec_enet_private *fep = netdev_priv(ndev); 514 struct bufdesc *bdp = txq->bd.cur; 515 struct bufdesc_ex *ebdp; 516 int nr_frags = skb_shinfo(skb)->nr_frags; 517 int frag, frag_len; 518 unsigned short status; 519 unsigned int estatus = 0; 520 skb_frag_t *this_frag; 521 unsigned int index; 522 void *bufaddr; 523 dma_addr_t addr; 524 int i; 525 526 for (frag = 0; frag < nr_frags; frag++) { 527 this_frag = &skb_shinfo(skb)->frags[frag]; 528 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 529 ebdp = (struct bufdesc_ex *)bdp; 530 531 status = fec16_to_cpu(bdp->cbd_sc); 532 status &= ~BD_ENET_TX_STATS; 533 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 534 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 535 536 /* Handle the last BD specially */ 537 if (frag == nr_frags - 1) { 538 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 539 if (fep->bufdesc_ex) { 540 estatus |= BD_ENET_TX_INT; 541 if (unlikely(skb_shinfo(skb)->tx_flags & 542 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 543 estatus |= BD_ENET_TX_TS; 544 } 545 } 546 547 if (fep->bufdesc_ex) { 548 if (fep->quirks & FEC_QUIRK_HAS_AVB) 549 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 550 if (skb->ip_summed == CHECKSUM_PARTIAL) 551 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 552 553 ebdp->cbd_bdu = 0; 554 ebdp->cbd_esc = cpu_to_fec32(estatus); 555 } 556 557 bufaddr = skb_frag_address(this_frag); 558 559 index = fec_enet_get_bd_index(bdp, &txq->bd); 560 if (((unsigned long) bufaddr) & fep->tx_align || 561 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 562 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 563 bufaddr = txq->tx_bounce[index]; 564 565 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 566 swap_buffer(bufaddr, frag_len); 567 } 568 569 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 570 DMA_TO_DEVICE); 571 if (dma_mapping_error(&fep->pdev->dev, addr)) { 572 if (net_ratelimit()) 573 netdev_err(ndev, "Tx DMA memory map failed\n"); 574 goto dma_mapping_error; 575 } 576 577 bdp->cbd_bufaddr = cpu_to_fec32(addr); 578 bdp->cbd_datlen = cpu_to_fec16(frag_len); 579 /* Make sure the updates to rest of the descriptor are 580 * performed before transferring ownership. 581 */ 582 wmb(); 583 bdp->cbd_sc = cpu_to_fec16(status); 584 } 585 586 return bdp; 587 dma_mapping_error: 588 bdp = txq->bd.cur; 589 for (i = 0; i < frag; i++) { 590 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 591 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 592 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 593 } 594 return ERR_PTR(-ENOMEM); 595 } 596 597 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 598 struct sk_buff *skb, struct net_device *ndev) 599 { 600 struct fec_enet_private *fep = netdev_priv(ndev); 601 int nr_frags = skb_shinfo(skb)->nr_frags; 602 struct bufdesc *bdp, *last_bdp; 603 void *bufaddr; 604 dma_addr_t addr; 605 unsigned short status; 606 unsigned short buflen; 607 unsigned int estatus = 0; 608 unsigned int index; 609 int entries_free; 610 611 entries_free = fec_enet_get_free_txdesc_num(txq); 612 if (entries_free < MAX_SKB_FRAGS + 1) { 613 dev_kfree_skb_any(skb); 614 if (net_ratelimit()) 615 netdev_err(ndev, "NOT enough BD for SG!\n"); 616 return NETDEV_TX_OK; 617 } 618 619 /* Protocol checksum off-load for TCP and UDP. */ 620 if (fec_enet_clear_csum(skb, ndev)) { 621 dev_kfree_skb_any(skb); 622 return NETDEV_TX_OK; 623 } 624 625 /* Fill in a Tx ring entry */ 626 bdp = txq->bd.cur; 627 last_bdp = bdp; 628 status = fec16_to_cpu(bdp->cbd_sc); 629 status &= ~BD_ENET_TX_STATS; 630 631 /* Set buffer length and buffer pointer */ 632 bufaddr = skb->data; 633 buflen = skb_headlen(skb); 634 635 index = fec_enet_get_bd_index(bdp, &txq->bd); 636 if (((unsigned long) bufaddr) & fep->tx_align || 637 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 638 memcpy(txq->tx_bounce[index], skb->data, buflen); 639 bufaddr = txq->tx_bounce[index]; 640 641 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 642 swap_buffer(bufaddr, buflen); 643 } 644 645 /* Push the data cache so the CPM does not get stale memory data. */ 646 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 647 if (dma_mapping_error(&fep->pdev->dev, addr)) { 648 dev_kfree_skb_any(skb); 649 if (net_ratelimit()) 650 netdev_err(ndev, "Tx DMA memory map failed\n"); 651 return NETDEV_TX_OK; 652 } 653 654 if (nr_frags) { 655 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 656 if (IS_ERR(last_bdp)) { 657 dma_unmap_single(&fep->pdev->dev, addr, 658 buflen, DMA_TO_DEVICE); 659 dev_kfree_skb_any(skb); 660 return NETDEV_TX_OK; 661 } 662 } else { 663 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 664 if (fep->bufdesc_ex) { 665 estatus = BD_ENET_TX_INT; 666 if (unlikely(skb_shinfo(skb)->tx_flags & 667 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 668 estatus |= BD_ENET_TX_TS; 669 } 670 } 671 bdp->cbd_bufaddr = cpu_to_fec32(addr); 672 bdp->cbd_datlen = cpu_to_fec16(buflen); 673 674 if (fep->bufdesc_ex) { 675 676 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 677 678 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 679 fep->hwts_tx_en)) 680 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 681 682 if (fep->quirks & FEC_QUIRK_HAS_AVB) 683 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 684 685 if (skb->ip_summed == CHECKSUM_PARTIAL) 686 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 687 688 ebdp->cbd_bdu = 0; 689 ebdp->cbd_esc = cpu_to_fec32(estatus); 690 } 691 692 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 693 /* Save skb pointer */ 694 txq->tx_buf[index].buf_p = skb; 695 696 /* Make sure the updates to rest of the descriptor are performed before 697 * transferring ownership. 698 */ 699 wmb(); 700 701 /* Send it on its way. Tell FEC it's ready, interrupt when done, 702 * it's the last BD of the frame, and to put the CRC on the end. 703 */ 704 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 705 bdp->cbd_sc = cpu_to_fec16(status); 706 707 /* If this was the last BD in the ring, start at the beginning again. */ 708 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 709 710 skb_tx_timestamp(skb); 711 712 /* Make sure the update to bdp is performed before txq->bd.cur. */ 713 wmb(); 714 txq->bd.cur = bdp; 715 716 /* Trigger transmission start */ 717 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 718 !readl(txq->bd.reg_desc_active) || 719 !readl(txq->bd.reg_desc_active) || 720 !readl(txq->bd.reg_desc_active) || 721 !readl(txq->bd.reg_desc_active)) 722 writel(0, txq->bd.reg_desc_active); 723 724 return 0; 725 } 726 727 static int 728 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 729 struct net_device *ndev, 730 struct bufdesc *bdp, int index, char *data, 731 int size, bool last_tcp, bool is_last) 732 { 733 struct fec_enet_private *fep = netdev_priv(ndev); 734 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 735 unsigned short status; 736 unsigned int estatus = 0; 737 dma_addr_t addr; 738 739 status = fec16_to_cpu(bdp->cbd_sc); 740 status &= ~BD_ENET_TX_STATS; 741 742 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 743 744 if (((unsigned long) data) & fep->tx_align || 745 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 746 memcpy(txq->tx_bounce[index], data, size); 747 data = txq->tx_bounce[index]; 748 749 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 750 swap_buffer(data, size); 751 } 752 753 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 754 if (dma_mapping_error(&fep->pdev->dev, addr)) { 755 dev_kfree_skb_any(skb); 756 if (net_ratelimit()) 757 netdev_err(ndev, "Tx DMA memory map failed\n"); 758 return NETDEV_TX_OK; 759 } 760 761 bdp->cbd_datlen = cpu_to_fec16(size); 762 bdp->cbd_bufaddr = cpu_to_fec32(addr); 763 764 if (fep->bufdesc_ex) { 765 if (fep->quirks & FEC_QUIRK_HAS_AVB) 766 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 767 if (skb->ip_summed == CHECKSUM_PARTIAL) 768 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 769 ebdp->cbd_bdu = 0; 770 ebdp->cbd_esc = cpu_to_fec32(estatus); 771 } 772 773 /* Handle the last BD specially */ 774 if (last_tcp) 775 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 776 if (is_last) { 777 status |= BD_ENET_TX_INTR; 778 if (fep->bufdesc_ex) 779 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 780 } 781 782 bdp->cbd_sc = cpu_to_fec16(status); 783 784 return 0; 785 } 786 787 static int 788 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 789 struct sk_buff *skb, struct net_device *ndev, 790 struct bufdesc *bdp, int index) 791 { 792 struct fec_enet_private *fep = netdev_priv(ndev); 793 int hdr_len = skb_tcp_all_headers(skb); 794 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 795 void *bufaddr; 796 unsigned long dmabuf; 797 unsigned short status; 798 unsigned int estatus = 0; 799 800 status = fec16_to_cpu(bdp->cbd_sc); 801 status &= ~BD_ENET_TX_STATS; 802 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 803 804 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 805 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 806 if (((unsigned long)bufaddr) & fep->tx_align || 807 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 808 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 809 bufaddr = txq->tx_bounce[index]; 810 811 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 812 swap_buffer(bufaddr, hdr_len); 813 814 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 815 hdr_len, DMA_TO_DEVICE); 816 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 817 dev_kfree_skb_any(skb); 818 if (net_ratelimit()) 819 netdev_err(ndev, "Tx DMA memory map failed\n"); 820 return NETDEV_TX_OK; 821 } 822 } 823 824 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 825 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 826 827 if (fep->bufdesc_ex) { 828 if (fep->quirks & FEC_QUIRK_HAS_AVB) 829 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 830 if (skb->ip_summed == CHECKSUM_PARTIAL) 831 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 832 ebdp->cbd_bdu = 0; 833 ebdp->cbd_esc = cpu_to_fec32(estatus); 834 } 835 836 bdp->cbd_sc = cpu_to_fec16(status); 837 838 return 0; 839 } 840 841 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 842 struct sk_buff *skb, 843 struct net_device *ndev) 844 { 845 struct fec_enet_private *fep = netdev_priv(ndev); 846 int hdr_len, total_len, data_left; 847 struct bufdesc *bdp = txq->bd.cur; 848 struct bufdesc *tmp_bdp; 849 struct bufdesc_ex *ebdp; 850 struct tso_t tso; 851 unsigned int index = 0; 852 int ret; 853 854 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 855 dev_kfree_skb_any(skb); 856 if (net_ratelimit()) 857 netdev_err(ndev, "NOT enough BD for TSO!\n"); 858 return NETDEV_TX_OK; 859 } 860 861 /* Protocol checksum off-load for TCP and UDP. */ 862 if (fec_enet_clear_csum(skb, ndev)) { 863 dev_kfree_skb_any(skb); 864 return NETDEV_TX_OK; 865 } 866 867 /* Initialize the TSO handler, and prepare the first payload */ 868 hdr_len = tso_start(skb, &tso); 869 870 total_len = skb->len - hdr_len; 871 while (total_len > 0) { 872 char *hdr; 873 874 index = fec_enet_get_bd_index(bdp, &txq->bd); 875 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 876 total_len -= data_left; 877 878 /* prepare packet headers: MAC + IP + TCP */ 879 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 880 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 881 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 882 if (ret) 883 goto err_release; 884 885 while (data_left > 0) { 886 int size; 887 888 size = min_t(int, tso.size, data_left); 889 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 890 index = fec_enet_get_bd_index(bdp, &txq->bd); 891 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 892 bdp, index, 893 tso.data, size, 894 size == data_left, 895 total_len == 0); 896 if (ret) 897 goto err_release; 898 899 data_left -= size; 900 tso_build_data(skb, &tso, size); 901 } 902 903 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 904 } 905 906 /* Save skb pointer */ 907 txq->tx_buf[index].buf_p = skb; 908 909 skb_tx_timestamp(skb); 910 txq->bd.cur = bdp; 911 912 /* Trigger transmission start */ 913 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 914 !readl(txq->bd.reg_desc_active) || 915 !readl(txq->bd.reg_desc_active) || 916 !readl(txq->bd.reg_desc_active) || 917 !readl(txq->bd.reg_desc_active)) 918 writel(0, txq->bd.reg_desc_active); 919 920 return 0; 921 922 err_release: 923 /* Release all used data descriptors for TSO */ 924 tmp_bdp = txq->bd.cur; 925 926 while (tmp_bdp != bdp) { 927 /* Unmap data buffers */ 928 if (tmp_bdp->cbd_bufaddr && 929 !IS_TSO_HEADER(txq, fec32_to_cpu(tmp_bdp->cbd_bufaddr))) 930 dma_unmap_single(&fep->pdev->dev, 931 fec32_to_cpu(tmp_bdp->cbd_bufaddr), 932 fec16_to_cpu(tmp_bdp->cbd_datlen), 933 DMA_TO_DEVICE); 934 935 /* Clear standard buffer descriptor fields */ 936 tmp_bdp->cbd_sc = 0; 937 tmp_bdp->cbd_datlen = 0; 938 tmp_bdp->cbd_bufaddr = 0; 939 940 /* Handle extended descriptor if enabled */ 941 if (fep->bufdesc_ex) { 942 ebdp = (struct bufdesc_ex *)tmp_bdp; 943 ebdp->cbd_esc = 0; 944 } 945 946 tmp_bdp = fec_enet_get_nextdesc(tmp_bdp, &txq->bd); 947 } 948 949 dev_kfree_skb_any(skb); 950 951 return ret; 952 } 953 954 static netdev_tx_t 955 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 956 { 957 struct fec_enet_private *fep = netdev_priv(ndev); 958 int entries_free; 959 unsigned short queue; 960 struct fec_enet_priv_tx_q *txq; 961 struct netdev_queue *nq; 962 int ret; 963 964 queue = skb_get_queue_mapping(skb); 965 txq = fep->tx_queue[queue]; 966 nq = netdev_get_tx_queue(ndev, queue); 967 968 if (skb_is_gso(skb)) 969 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 970 else 971 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 972 if (ret) 973 return ret; 974 975 entries_free = fec_enet_get_free_txdesc_num(txq); 976 if (entries_free <= txq->tx_stop_threshold) 977 netif_tx_stop_queue(nq); 978 979 return NETDEV_TX_OK; 980 } 981 982 /* Init RX & TX buffer descriptors 983 */ 984 static void fec_enet_bd_init(struct net_device *dev) 985 { 986 struct fec_enet_private *fep = netdev_priv(dev); 987 struct fec_enet_priv_tx_q *txq; 988 struct fec_enet_priv_rx_q *rxq; 989 struct bufdesc *bdp; 990 unsigned int i; 991 unsigned int q; 992 993 for (q = 0; q < fep->num_rx_queues; q++) { 994 /* Initialize the receive buffer descriptors. */ 995 rxq = fep->rx_queue[q]; 996 bdp = rxq->bd.base; 997 998 for (i = 0; i < rxq->bd.ring_size; i++) { 999 1000 /* Initialize the BD for every fragment in the page. */ 1001 if (bdp->cbd_bufaddr) 1002 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 1003 else 1004 bdp->cbd_sc = cpu_to_fec16(0); 1005 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1006 } 1007 1008 /* Set the last buffer to wrap */ 1009 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 1010 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 1011 1012 rxq->bd.cur = rxq->bd.base; 1013 } 1014 1015 for (q = 0; q < fep->num_tx_queues; q++) { 1016 /* ...and the same for transmit */ 1017 txq = fep->tx_queue[q]; 1018 bdp = txq->bd.base; 1019 txq->bd.cur = bdp; 1020 1021 for (i = 0; i < txq->bd.ring_size; i++) { 1022 /* Initialize the BD for every fragment in the page. */ 1023 bdp->cbd_sc = cpu_to_fec16(0); 1024 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 1025 if (bdp->cbd_bufaddr && 1026 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1027 dma_unmap_single(&fep->pdev->dev, 1028 fec32_to_cpu(bdp->cbd_bufaddr), 1029 fec16_to_cpu(bdp->cbd_datlen), 1030 DMA_TO_DEVICE); 1031 if (txq->tx_buf[i].buf_p) 1032 dev_kfree_skb_any(txq->tx_buf[i].buf_p); 1033 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 1034 if (bdp->cbd_bufaddr) 1035 dma_unmap_single(&fep->pdev->dev, 1036 fec32_to_cpu(bdp->cbd_bufaddr), 1037 fec16_to_cpu(bdp->cbd_datlen), 1038 DMA_TO_DEVICE); 1039 1040 if (txq->tx_buf[i].buf_p) 1041 xdp_return_frame(txq->tx_buf[i].buf_p); 1042 } else { 1043 struct page *page = txq->tx_buf[i].buf_p; 1044 1045 if (page) 1046 page_pool_put_page(page->pp, page, 0, false); 1047 } 1048 1049 txq->tx_buf[i].buf_p = NULL; 1050 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1051 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 1052 bdp->cbd_bufaddr = cpu_to_fec32(0); 1053 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1054 } 1055 1056 /* Set the last buffer to wrap */ 1057 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 1058 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 1059 txq->dirty_tx = bdp; 1060 } 1061 } 1062 1063 static void fec_enet_active_rxring(struct net_device *ndev) 1064 { 1065 struct fec_enet_private *fep = netdev_priv(ndev); 1066 int i; 1067 1068 for (i = 0; i < fep->num_rx_queues; i++) 1069 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 1070 } 1071 1072 static void fec_enet_enable_ring(struct net_device *ndev) 1073 { 1074 struct fec_enet_private *fep = netdev_priv(ndev); 1075 struct fec_enet_priv_tx_q *txq; 1076 struct fec_enet_priv_rx_q *rxq; 1077 int i; 1078 1079 for (i = 0; i < fep->num_rx_queues; i++) { 1080 rxq = fep->rx_queue[i]; 1081 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 1082 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 1083 1084 /* enable DMA1/2 */ 1085 if (i) 1086 writel(RCMR_MATCHEN | RCMR_CMP(i), 1087 fep->hwp + FEC_RCMR(i)); 1088 } 1089 1090 for (i = 0; i < fep->num_tx_queues; i++) { 1091 txq = fep->tx_queue[i]; 1092 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 1093 1094 /* enable DMA1/2 */ 1095 if (i) 1096 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 1097 fep->hwp + FEC_DMA_CFG(i)); 1098 } 1099 } 1100 1101 /* Whack a reset. We should wait for this. 1102 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1103 * instead of reset MAC itself. 1104 */ 1105 static void fec_ctrl_reset(struct fec_enet_private *fep, bool allow_wol) 1106 { 1107 u32 val; 1108 1109 if (!allow_wol || !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1110 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || 1111 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 1112 writel(0, fep->hwp + FEC_ECNTRL); 1113 } else { 1114 writel(FEC_ECR_RESET, fep->hwp + FEC_ECNTRL); 1115 udelay(10); 1116 } 1117 } else { 1118 val = readl(fep->hwp + FEC_ECNTRL); 1119 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1120 writel(val, fep->hwp + FEC_ECNTRL); 1121 } 1122 } 1123 1124 /* 1125 * This function is called to start or restart the FEC during a link 1126 * change, transmit timeout, or to reconfigure the FEC. The network 1127 * packet processing for this device must be stopped before this call. 1128 */ 1129 static void 1130 fec_restart(struct net_device *ndev) 1131 { 1132 struct fec_enet_private *fep = netdev_priv(ndev); 1133 u32 temp_mac[2]; 1134 u32 rcntl = OPT_FRAME_SIZE | 0x04; 1135 u32 ecntl = FEC_ECR_ETHEREN; 1136 1137 if (fep->bufdesc_ex) 1138 fec_ptp_save_state(fep); 1139 1140 fec_ctrl_reset(fep, false); 1141 1142 /* 1143 * enet-mac reset will reset mac address registers too, 1144 * so need to reconfigure it. 1145 */ 1146 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 1147 writel((__force u32)cpu_to_be32(temp_mac[0]), 1148 fep->hwp + FEC_ADDR_LOW); 1149 writel((__force u32)cpu_to_be32(temp_mac[1]), 1150 fep->hwp + FEC_ADDR_HIGH); 1151 1152 /* Clear any outstanding interrupt, except MDIO. */ 1153 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 1154 1155 fec_enet_bd_init(ndev); 1156 1157 fec_enet_enable_ring(ndev); 1158 1159 /* Enable MII mode */ 1160 if (fep->full_duplex == DUPLEX_FULL) { 1161 /* FD enable */ 1162 writel(0x04, fep->hwp + FEC_X_CNTRL); 1163 } else { 1164 /* No Rcv on Xmit */ 1165 rcntl |= 0x02; 1166 writel(0x0, fep->hwp + FEC_X_CNTRL); 1167 } 1168 1169 /* Set MII speed */ 1170 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1171 1172 #if !defined(CONFIG_M5272) 1173 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1174 u32 val = readl(fep->hwp + FEC_RACC); 1175 1176 /* align IP header */ 1177 val |= FEC_RACC_SHIFT16; 1178 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1179 /* set RX checksum */ 1180 val |= FEC_RACC_OPTIONS; 1181 else 1182 val &= ~FEC_RACC_OPTIONS; 1183 writel(val, fep->hwp + FEC_RACC); 1184 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1185 } 1186 #endif 1187 1188 /* 1189 * The phy interface and speed need to get configured 1190 * differently on enet-mac. 1191 */ 1192 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1193 /* Enable flow control and length check */ 1194 rcntl |= 0x40000000 | 0x00000020; 1195 1196 /* RGMII, RMII or MII */ 1197 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1198 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1199 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1200 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1201 rcntl |= (1 << 6); 1202 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1203 rcntl |= FEC_RCR_RMII; 1204 else 1205 rcntl &= ~FEC_RCR_RMII; 1206 1207 /* 1G, 100M or 10M */ 1208 if (ndev->phydev) { 1209 if (ndev->phydev->speed == SPEED_1000) 1210 ecntl |= (1 << 5); 1211 else if (ndev->phydev->speed == SPEED_100) 1212 rcntl &= ~FEC_RCR_10BASET; 1213 else 1214 rcntl |= FEC_RCR_10BASET; 1215 } 1216 } else { 1217 #ifdef FEC_MIIGSK_ENR 1218 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1219 u32 cfgr; 1220 /* disable the gasket and wait */ 1221 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1222 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1223 udelay(1); 1224 1225 /* 1226 * configure the gasket: 1227 * RMII, 50 MHz, no loopback, no echo 1228 * MII, 25 MHz, no loopback, no echo 1229 */ 1230 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1231 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1232 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1233 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1234 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1235 1236 /* re-enable the gasket */ 1237 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1238 } 1239 #endif 1240 } 1241 1242 #if !defined(CONFIG_M5272) 1243 /* enable pause frame*/ 1244 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1245 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1246 ndev->phydev && ndev->phydev->pause)) { 1247 rcntl |= FEC_RCR_FLOWCTL; 1248 1249 /* set FIFO threshold parameter to reduce overrun */ 1250 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1251 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1252 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1253 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1254 1255 /* OPD */ 1256 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1257 } else { 1258 rcntl &= ~FEC_RCR_FLOWCTL; 1259 } 1260 #endif /* !defined(CONFIG_M5272) */ 1261 1262 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1263 1264 /* Setup multicast filter. */ 1265 set_multicast_list(ndev); 1266 #ifndef CONFIG_M5272 1267 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1268 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1269 #endif 1270 1271 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1272 /* enable ENET endian swap */ 1273 ecntl |= FEC_ECR_BYTESWP; 1274 /* enable ENET store and forward mode */ 1275 writel(FEC_TXWMRK_STRFWD, fep->hwp + FEC_X_WMRK); 1276 } 1277 1278 if (fep->bufdesc_ex) 1279 ecntl |= FEC_ECR_EN1588; 1280 1281 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1282 fep->rgmii_txc_dly) 1283 ecntl |= FEC_ENET_TXC_DLY; 1284 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1285 fep->rgmii_rxc_dly) 1286 ecntl |= FEC_ENET_RXC_DLY; 1287 1288 #ifndef CONFIG_M5272 1289 /* Enable the MIB statistic event counters */ 1290 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1291 #endif 1292 1293 /* And last, enable the transmit and receive processing */ 1294 writel(ecntl, fep->hwp + FEC_ECNTRL); 1295 fec_enet_active_rxring(ndev); 1296 1297 if (fep->bufdesc_ex) { 1298 fec_ptp_start_cyclecounter(ndev); 1299 fec_ptp_restore_state(fep); 1300 } 1301 1302 /* Enable interrupts we wish to service */ 1303 if (fep->link) 1304 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1305 else 1306 writel(0, fep->hwp + FEC_IMASK); 1307 1308 /* Init the interrupt coalescing */ 1309 if (fep->quirks & FEC_QUIRK_HAS_COALESCE) 1310 fec_enet_itr_coal_set(ndev); 1311 } 1312 1313 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep) 1314 { 1315 if (!(of_machine_is_compatible("fsl,imx8qm") || 1316 of_machine_is_compatible("fsl,imx8qxp") || 1317 of_machine_is_compatible("fsl,imx8dxl"))) 1318 return 0; 1319 1320 return imx_scu_get_handle(&fep->ipc_handle); 1321 } 1322 1323 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled) 1324 { 1325 struct device_node *np = fep->pdev->dev.of_node; 1326 u32 rsrc_id, val; 1327 int idx; 1328 1329 if (!np || !fep->ipc_handle) 1330 return; 1331 1332 idx = of_alias_get_id(np, "ethernet"); 1333 if (idx < 0) 1334 idx = 0; 1335 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0; 1336 1337 val = enabled ? 1 : 0; 1338 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val); 1339 } 1340 1341 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1342 { 1343 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1344 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1345 1346 if (stop_gpr->gpr) { 1347 if (enabled) 1348 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1349 BIT(stop_gpr->bit), 1350 BIT(stop_gpr->bit)); 1351 else 1352 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1353 BIT(stop_gpr->bit), 0); 1354 } else if (pdata && pdata->sleep_mode_enable) { 1355 pdata->sleep_mode_enable(enabled); 1356 } else { 1357 fec_enet_ipg_stop_set(fep, enabled); 1358 } 1359 } 1360 1361 static void fec_irqs_disable(struct net_device *ndev) 1362 { 1363 struct fec_enet_private *fep = netdev_priv(ndev); 1364 1365 writel(0, fep->hwp + FEC_IMASK); 1366 } 1367 1368 static void fec_irqs_disable_except_wakeup(struct net_device *ndev) 1369 { 1370 struct fec_enet_private *fep = netdev_priv(ndev); 1371 1372 writel(0, fep->hwp + FEC_IMASK); 1373 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1374 } 1375 1376 static void 1377 fec_stop(struct net_device *ndev) 1378 { 1379 struct fec_enet_private *fep = netdev_priv(ndev); 1380 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & FEC_RCR_RMII; 1381 u32 val; 1382 1383 /* We cannot expect a graceful transmit stop without link !!! */ 1384 if (fep->link) { 1385 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1386 udelay(10); 1387 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1388 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1389 } 1390 1391 if (fep->bufdesc_ex) 1392 fec_ptp_save_state(fep); 1393 1394 fec_ctrl_reset(fep, true); 1395 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1396 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1397 1398 /* We have to keep ENET enabled to have MII interrupt stay working */ 1399 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1400 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1401 writel(FEC_ECR_ETHEREN, fep->hwp + FEC_ECNTRL); 1402 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1403 } 1404 1405 if (fep->bufdesc_ex) { 1406 val = readl(fep->hwp + FEC_ECNTRL); 1407 val |= FEC_ECR_EN1588; 1408 writel(val, fep->hwp + FEC_ECNTRL); 1409 1410 fec_ptp_start_cyclecounter(ndev); 1411 fec_ptp_restore_state(fep); 1412 } 1413 } 1414 1415 static void 1416 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1417 { 1418 struct fec_enet_private *fep = netdev_priv(ndev); 1419 1420 fec_dump(ndev); 1421 1422 ndev->stats.tx_errors++; 1423 1424 schedule_work(&fep->tx_timeout_work); 1425 } 1426 1427 static void fec_enet_timeout_work(struct work_struct *work) 1428 { 1429 struct fec_enet_private *fep = 1430 container_of(work, struct fec_enet_private, tx_timeout_work); 1431 struct net_device *ndev = fep->netdev; 1432 1433 rtnl_lock(); 1434 if (netif_device_present(ndev) || netif_running(ndev)) { 1435 napi_disable(&fep->napi); 1436 netif_tx_lock_bh(ndev); 1437 fec_restart(ndev); 1438 netif_tx_wake_all_queues(ndev); 1439 netif_tx_unlock_bh(ndev); 1440 napi_enable(&fep->napi); 1441 } 1442 rtnl_unlock(); 1443 } 1444 1445 static void 1446 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1447 struct skb_shared_hwtstamps *hwtstamps) 1448 { 1449 unsigned long flags; 1450 u64 ns; 1451 1452 spin_lock_irqsave(&fep->tmreg_lock, flags); 1453 ns = timecounter_cyc2time(&fep->tc, ts); 1454 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1455 1456 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1457 hwtstamps->hwtstamp = ns_to_ktime(ns); 1458 } 1459 1460 static void 1461 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id, int budget) 1462 { 1463 struct fec_enet_private *fep; 1464 struct xdp_frame *xdpf; 1465 struct bufdesc *bdp; 1466 unsigned short status; 1467 struct sk_buff *skb; 1468 struct fec_enet_priv_tx_q *txq; 1469 struct netdev_queue *nq; 1470 int index = 0; 1471 int entries_free; 1472 struct page *page; 1473 int frame_len; 1474 1475 fep = netdev_priv(ndev); 1476 1477 txq = fep->tx_queue[queue_id]; 1478 /* get next bdp of dirty_tx */ 1479 nq = netdev_get_tx_queue(ndev, queue_id); 1480 bdp = txq->dirty_tx; 1481 1482 /* get next bdp of dirty_tx */ 1483 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1484 1485 while (bdp != READ_ONCE(txq->bd.cur)) { 1486 /* Order the load of bd.cur and cbd_sc */ 1487 rmb(); 1488 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1489 if (status & BD_ENET_TX_READY) 1490 break; 1491 1492 index = fec_enet_get_bd_index(bdp, &txq->bd); 1493 1494 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1495 skb = txq->tx_buf[index].buf_p; 1496 if (bdp->cbd_bufaddr && 1497 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1498 dma_unmap_single(&fep->pdev->dev, 1499 fec32_to_cpu(bdp->cbd_bufaddr), 1500 fec16_to_cpu(bdp->cbd_datlen), 1501 DMA_TO_DEVICE); 1502 bdp->cbd_bufaddr = cpu_to_fec32(0); 1503 if (!skb) 1504 goto tx_buf_done; 1505 } else { 1506 /* Tx processing cannot call any XDP (or page pool) APIs if 1507 * the "budget" is 0. Because NAPI is called with budget of 1508 * 0 (such as netpoll) indicates we may be in an IRQ context, 1509 * however, we can't use the page pool from IRQ context. 1510 */ 1511 if (unlikely(!budget)) 1512 break; 1513 1514 if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1515 xdpf = txq->tx_buf[index].buf_p; 1516 if (bdp->cbd_bufaddr) 1517 dma_unmap_single(&fep->pdev->dev, 1518 fec32_to_cpu(bdp->cbd_bufaddr), 1519 fec16_to_cpu(bdp->cbd_datlen), 1520 DMA_TO_DEVICE); 1521 } else { 1522 page = txq->tx_buf[index].buf_p; 1523 } 1524 1525 bdp->cbd_bufaddr = cpu_to_fec32(0); 1526 if (unlikely(!txq->tx_buf[index].buf_p)) { 1527 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1528 goto tx_buf_done; 1529 } 1530 1531 frame_len = fec16_to_cpu(bdp->cbd_datlen); 1532 } 1533 1534 /* Check for errors. */ 1535 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1536 BD_ENET_TX_RL | BD_ENET_TX_UN | 1537 BD_ENET_TX_CSL)) { 1538 ndev->stats.tx_errors++; 1539 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1540 ndev->stats.tx_heartbeat_errors++; 1541 if (status & BD_ENET_TX_LC) /* Late collision */ 1542 ndev->stats.tx_window_errors++; 1543 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1544 ndev->stats.tx_aborted_errors++; 1545 if (status & BD_ENET_TX_UN) /* Underrun */ 1546 ndev->stats.tx_fifo_errors++; 1547 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1548 ndev->stats.tx_carrier_errors++; 1549 } else { 1550 ndev->stats.tx_packets++; 1551 1552 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) 1553 ndev->stats.tx_bytes += skb->len; 1554 else 1555 ndev->stats.tx_bytes += frame_len; 1556 } 1557 1558 /* Deferred means some collisions occurred during transmit, 1559 * but we eventually sent the packet OK. 1560 */ 1561 if (status & BD_ENET_TX_DEF) 1562 ndev->stats.collisions++; 1563 1564 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1565 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1566 * are to time stamp the packet, so we still need to check time 1567 * stamping enabled flag. 1568 */ 1569 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1570 fep->hwts_tx_en) && fep->bufdesc_ex) { 1571 struct skb_shared_hwtstamps shhwtstamps; 1572 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1573 1574 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1575 skb_tstamp_tx(skb, &shhwtstamps); 1576 } 1577 1578 /* Free the sk buffer associated with this last transmit */ 1579 napi_consume_skb(skb, budget); 1580 } else if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1581 xdp_return_frame_rx_napi(xdpf); 1582 } else { /* recycle pages of XDP_TX frames */ 1583 /* The dma_sync_size = 0 as XDP_TX has already synced DMA for_device */ 1584 page_pool_put_page(page->pp, page, 0, true); 1585 } 1586 1587 txq->tx_buf[index].buf_p = NULL; 1588 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1589 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1590 1591 tx_buf_done: 1592 /* Make sure the update to bdp and tx_buf are performed 1593 * before dirty_tx 1594 */ 1595 wmb(); 1596 txq->dirty_tx = bdp; 1597 1598 /* Update pointer to next buffer descriptor to be transmitted */ 1599 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1600 1601 /* Since we have freed up a buffer, the ring is no longer full 1602 */ 1603 if (netif_tx_queue_stopped(nq)) { 1604 entries_free = fec_enet_get_free_txdesc_num(txq); 1605 if (entries_free >= txq->tx_wake_threshold) 1606 netif_tx_wake_queue(nq); 1607 } 1608 } 1609 1610 /* ERR006358: Keep the transmitter going */ 1611 if (bdp != txq->bd.cur && 1612 readl(txq->bd.reg_desc_active) == 0) 1613 writel(0, txq->bd.reg_desc_active); 1614 } 1615 1616 static void fec_enet_tx(struct net_device *ndev, int budget) 1617 { 1618 struct fec_enet_private *fep = netdev_priv(ndev); 1619 int i; 1620 1621 /* Make sure that AVB queues are processed first. */ 1622 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1623 fec_enet_tx_queue(ndev, i, budget); 1624 } 1625 1626 static int fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq, 1627 struct bufdesc *bdp, int index) 1628 { 1629 struct page *new_page; 1630 dma_addr_t phys_addr; 1631 1632 new_page = page_pool_dev_alloc_pages(rxq->page_pool); 1633 if (unlikely(!new_page)) 1634 return -ENOMEM; 1635 1636 rxq->rx_skb_info[index].page = new_page; 1637 rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM; 1638 phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM; 1639 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 1640 1641 return 0; 1642 } 1643 1644 static u32 1645 fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog, 1646 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int cpu) 1647 { 1648 unsigned int sync, len = xdp->data_end - xdp->data; 1649 u32 ret = FEC_ENET_XDP_PASS; 1650 struct page *page; 1651 int err; 1652 u32 act; 1653 1654 act = bpf_prog_run_xdp(prog, xdp); 1655 1656 /* Due xdp_adjust_tail and xdp_adjust_head: DMA sync for_device cover 1657 * max len CPU touch 1658 */ 1659 sync = xdp->data_end - xdp->data; 1660 sync = max(sync, len); 1661 1662 switch (act) { 1663 case XDP_PASS: 1664 rxq->stats[RX_XDP_PASS]++; 1665 ret = FEC_ENET_XDP_PASS; 1666 break; 1667 1668 case XDP_REDIRECT: 1669 rxq->stats[RX_XDP_REDIRECT]++; 1670 err = xdp_do_redirect(fep->netdev, xdp, prog); 1671 if (unlikely(err)) 1672 goto xdp_err; 1673 1674 ret = FEC_ENET_XDP_REDIR; 1675 break; 1676 1677 case XDP_TX: 1678 rxq->stats[RX_XDP_TX]++; 1679 err = fec_enet_xdp_tx_xmit(fep, cpu, xdp, sync); 1680 if (unlikely(err)) { 1681 rxq->stats[RX_XDP_TX_ERRORS]++; 1682 goto xdp_err; 1683 } 1684 1685 ret = FEC_ENET_XDP_TX; 1686 break; 1687 1688 default: 1689 bpf_warn_invalid_xdp_action(fep->netdev, prog, act); 1690 fallthrough; 1691 1692 case XDP_ABORTED: 1693 fallthrough; /* handle aborts by dropping packet */ 1694 1695 case XDP_DROP: 1696 rxq->stats[RX_XDP_DROP]++; 1697 xdp_err: 1698 ret = FEC_ENET_XDP_CONSUMED; 1699 page = virt_to_head_page(xdp->data); 1700 page_pool_put_page(rxq->page_pool, page, sync, true); 1701 if (act != XDP_DROP) 1702 trace_xdp_exception(fep->netdev, prog, act); 1703 break; 1704 } 1705 1706 return ret; 1707 } 1708 1709 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1710 * When we update through the ring, if the next incoming buffer has 1711 * not been given to the system, we just set the empty indicator, 1712 * effectively tossing the packet. 1713 */ 1714 static int 1715 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1716 { 1717 struct fec_enet_private *fep = netdev_priv(ndev); 1718 struct fec_enet_priv_rx_q *rxq; 1719 struct bufdesc *bdp; 1720 unsigned short status; 1721 struct sk_buff *skb; 1722 ushort pkt_len; 1723 __u8 *data; 1724 int pkt_received = 0; 1725 struct bufdesc_ex *ebdp = NULL; 1726 bool vlan_packet_rcvd = false; 1727 u16 vlan_tag; 1728 int index = 0; 1729 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1730 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 1731 u32 ret, xdp_result = FEC_ENET_XDP_PASS; 1732 u32 data_start = FEC_ENET_XDP_HEADROOM; 1733 int cpu = smp_processor_id(); 1734 struct xdp_buff xdp; 1735 struct page *page; 1736 __fec32 cbd_bufaddr; 1737 u32 sub_len = 4; 1738 1739 #if !defined(CONFIG_M5272) 1740 /*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of 1741 * FEC_RACC_SHIFT16 is set by default in the probe function. 1742 */ 1743 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1744 data_start += 2; 1745 sub_len += 2; 1746 } 1747 #endif 1748 1749 #if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA) 1750 /* 1751 * Hacky flush of all caches instead of using the DMA API for the TSO 1752 * headers. 1753 */ 1754 flush_cache_all(); 1755 #endif 1756 rxq = fep->rx_queue[queue_id]; 1757 1758 /* First, grab all of the stats for the incoming packet. 1759 * These get messed up if we get called due to a busy condition. 1760 */ 1761 bdp = rxq->bd.cur; 1762 xdp_init_buff(&xdp, PAGE_SIZE, &rxq->xdp_rxq); 1763 1764 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1765 1766 if (pkt_received >= budget) 1767 break; 1768 pkt_received++; 1769 1770 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT); 1771 1772 /* Check for errors. */ 1773 status ^= BD_ENET_RX_LAST; 1774 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1775 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1776 BD_ENET_RX_CL)) { 1777 ndev->stats.rx_errors++; 1778 if (status & BD_ENET_RX_OV) { 1779 /* FIFO overrun */ 1780 ndev->stats.rx_fifo_errors++; 1781 goto rx_processing_done; 1782 } 1783 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1784 | BD_ENET_RX_LAST)) { 1785 /* Frame too long or too short. */ 1786 ndev->stats.rx_length_errors++; 1787 if (status & BD_ENET_RX_LAST) 1788 netdev_err(ndev, "rcv is not +last\n"); 1789 } 1790 if (status & BD_ENET_RX_CR) /* CRC Error */ 1791 ndev->stats.rx_crc_errors++; 1792 /* Report late collisions as a frame error. */ 1793 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1794 ndev->stats.rx_frame_errors++; 1795 goto rx_processing_done; 1796 } 1797 1798 /* Process the incoming frame. */ 1799 ndev->stats.rx_packets++; 1800 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1801 ndev->stats.rx_bytes += pkt_len; 1802 1803 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1804 page = rxq->rx_skb_info[index].page; 1805 cbd_bufaddr = bdp->cbd_bufaddr; 1806 if (fec_enet_update_cbd(rxq, bdp, index)) { 1807 ndev->stats.rx_dropped++; 1808 goto rx_processing_done; 1809 } 1810 1811 dma_sync_single_for_cpu(&fep->pdev->dev, 1812 fec32_to_cpu(cbd_bufaddr), 1813 pkt_len, 1814 DMA_FROM_DEVICE); 1815 prefetch(page_address(page)); 1816 1817 if (xdp_prog) { 1818 xdp_buff_clear_frags_flag(&xdp); 1819 /* subtract 16bit shift and FCS */ 1820 xdp_prepare_buff(&xdp, page_address(page), 1821 data_start, pkt_len - sub_len, false); 1822 ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, cpu); 1823 xdp_result |= ret; 1824 if (ret != FEC_ENET_XDP_PASS) 1825 goto rx_processing_done; 1826 } 1827 1828 /* The packet length includes FCS, but we don't want to 1829 * include that when passing upstream as it messes up 1830 * bridging applications. 1831 */ 1832 skb = build_skb(page_address(page), PAGE_SIZE); 1833 if (unlikely(!skb)) { 1834 page_pool_recycle_direct(rxq->page_pool, page); 1835 ndev->stats.rx_dropped++; 1836 1837 netdev_err_once(ndev, "build_skb failed!\n"); 1838 goto rx_processing_done; 1839 } 1840 1841 skb_reserve(skb, data_start); 1842 skb_put(skb, pkt_len - sub_len); 1843 skb_mark_for_recycle(skb); 1844 1845 if (unlikely(need_swap)) { 1846 data = page_address(page) + FEC_ENET_XDP_HEADROOM; 1847 swap_buffer(data, pkt_len); 1848 } 1849 data = skb->data; 1850 1851 /* Extract the enhanced buffer descriptor */ 1852 ebdp = NULL; 1853 if (fep->bufdesc_ex) 1854 ebdp = (struct bufdesc_ex *)bdp; 1855 1856 /* If this is a VLAN packet remove the VLAN Tag */ 1857 vlan_packet_rcvd = false; 1858 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1859 fep->bufdesc_ex && 1860 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1861 /* Push and remove the vlan tag */ 1862 struct vlan_hdr *vlan_header = 1863 (struct vlan_hdr *) (data + ETH_HLEN); 1864 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1865 1866 vlan_packet_rcvd = true; 1867 1868 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1869 skb_pull(skb, VLAN_HLEN); 1870 } 1871 1872 skb->protocol = eth_type_trans(skb, ndev); 1873 1874 /* Get receive timestamp from the skb */ 1875 if (fep->hwts_rx_en && fep->bufdesc_ex) 1876 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1877 skb_hwtstamps(skb)); 1878 1879 if (fep->bufdesc_ex && 1880 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1881 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1882 /* don't check it */ 1883 skb->ip_summed = CHECKSUM_UNNECESSARY; 1884 } else { 1885 skb_checksum_none_assert(skb); 1886 } 1887 } 1888 1889 /* Handle received VLAN packets */ 1890 if (vlan_packet_rcvd) 1891 __vlan_hwaccel_put_tag(skb, 1892 htons(ETH_P_8021Q), 1893 vlan_tag); 1894 1895 skb_record_rx_queue(skb, queue_id); 1896 napi_gro_receive(&fep->napi, skb); 1897 1898 rx_processing_done: 1899 /* Clear the status flags for this buffer */ 1900 status &= ~BD_ENET_RX_STATS; 1901 1902 /* Mark the buffer empty */ 1903 status |= BD_ENET_RX_EMPTY; 1904 1905 if (fep->bufdesc_ex) { 1906 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1907 1908 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1909 ebdp->cbd_prot = 0; 1910 ebdp->cbd_bdu = 0; 1911 } 1912 /* Make sure the updates to rest of the descriptor are 1913 * performed before transferring ownership. 1914 */ 1915 wmb(); 1916 bdp->cbd_sc = cpu_to_fec16(status); 1917 1918 /* Update BD pointer to next entry */ 1919 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1920 1921 /* Doing this here will keep the FEC running while we process 1922 * incoming frames. On a heavily loaded network, we should be 1923 * able to keep up at the expense of system resources. 1924 */ 1925 writel(0, rxq->bd.reg_desc_active); 1926 } 1927 rxq->bd.cur = bdp; 1928 1929 if (xdp_result & FEC_ENET_XDP_REDIR) 1930 xdp_do_flush(); 1931 1932 return pkt_received; 1933 } 1934 1935 static int fec_enet_rx(struct net_device *ndev, int budget) 1936 { 1937 struct fec_enet_private *fep = netdev_priv(ndev); 1938 int i, done = 0; 1939 1940 /* Make sure that AVB queues are processed first. */ 1941 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1942 done += fec_enet_rx_queue(ndev, budget - done, i); 1943 1944 return done; 1945 } 1946 1947 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1948 { 1949 uint int_events; 1950 1951 int_events = readl(fep->hwp + FEC_IEVENT); 1952 1953 /* Don't clear MDIO events, we poll for those */ 1954 int_events &= ~FEC_ENET_MII; 1955 1956 writel(int_events, fep->hwp + FEC_IEVENT); 1957 1958 return int_events != 0; 1959 } 1960 1961 static irqreturn_t 1962 fec_enet_interrupt(int irq, void *dev_id) 1963 { 1964 struct net_device *ndev = dev_id; 1965 struct fec_enet_private *fep = netdev_priv(ndev); 1966 irqreturn_t ret = IRQ_NONE; 1967 1968 if (fec_enet_collect_events(fep) && fep->link) { 1969 ret = IRQ_HANDLED; 1970 1971 if (napi_schedule_prep(&fep->napi)) { 1972 /* Disable interrupts */ 1973 writel(0, fep->hwp + FEC_IMASK); 1974 __napi_schedule(&fep->napi); 1975 } 1976 } 1977 1978 return ret; 1979 } 1980 1981 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1982 { 1983 struct net_device *ndev = napi->dev; 1984 struct fec_enet_private *fep = netdev_priv(ndev); 1985 int done = 0; 1986 1987 do { 1988 done += fec_enet_rx(ndev, budget - done); 1989 fec_enet_tx(ndev, budget); 1990 } while ((done < budget) && fec_enet_collect_events(fep)); 1991 1992 if (done < budget) { 1993 napi_complete_done(napi, done); 1994 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1995 } 1996 1997 return done; 1998 } 1999 2000 /* ------------------------------------------------------------------------- */ 2001 static int fec_get_mac(struct net_device *ndev) 2002 { 2003 struct fec_enet_private *fep = netdev_priv(ndev); 2004 unsigned char *iap, tmpaddr[ETH_ALEN]; 2005 int ret; 2006 2007 /* 2008 * try to get mac address in following order: 2009 * 2010 * 1) module parameter via kernel command line in form 2011 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 2012 */ 2013 iap = macaddr; 2014 2015 /* 2016 * 2) from device tree data 2017 */ 2018 if (!is_valid_ether_addr(iap)) { 2019 struct device_node *np = fep->pdev->dev.of_node; 2020 if (np) { 2021 ret = of_get_mac_address(np, tmpaddr); 2022 if (!ret) 2023 iap = tmpaddr; 2024 else if (ret == -EPROBE_DEFER) 2025 return ret; 2026 } 2027 } 2028 2029 /* 2030 * 3) from flash or fuse (via platform data) 2031 */ 2032 if (!is_valid_ether_addr(iap)) { 2033 #ifdef CONFIG_M5272 2034 if (FEC_FLASHMAC) 2035 iap = (unsigned char *)FEC_FLASHMAC; 2036 #else 2037 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 2038 2039 if (pdata) 2040 iap = (unsigned char *)&pdata->mac; 2041 #endif 2042 } 2043 2044 /* 2045 * 4) FEC mac registers set by bootloader 2046 */ 2047 if (!is_valid_ether_addr(iap)) { 2048 *((__be32 *) &tmpaddr[0]) = 2049 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 2050 *((__be16 *) &tmpaddr[4]) = 2051 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 2052 iap = &tmpaddr[0]; 2053 } 2054 2055 /* 2056 * 5) random mac address 2057 */ 2058 if (!is_valid_ether_addr(iap)) { 2059 /* Report it and use a random ethernet address instead */ 2060 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 2061 eth_hw_addr_random(ndev); 2062 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 2063 ndev->dev_addr); 2064 return 0; 2065 } 2066 2067 /* Adjust MAC if using macaddr */ 2068 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0); 2069 2070 return 0; 2071 } 2072 2073 /* ------------------------------------------------------------------------- */ 2074 2075 /* 2076 * Phy section 2077 */ 2078 2079 /* LPI Sleep Ts count base on tx clk (clk_ref). 2080 * The lpi sleep cnt value = X us / (cycle_ns). 2081 */ 2082 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) 2083 { 2084 struct fec_enet_private *fep = netdev_priv(ndev); 2085 2086 return us * (fep->clk_ref_rate / 1000) / 1000; 2087 } 2088 2089 static int fec_enet_eee_mode_set(struct net_device *ndev, u32 lpi_timer, 2090 bool enable) 2091 { 2092 struct fec_enet_private *fep = netdev_priv(ndev); 2093 unsigned int sleep_cycle, wake_cycle; 2094 2095 if (enable) { 2096 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, lpi_timer); 2097 wake_cycle = sleep_cycle; 2098 } else { 2099 sleep_cycle = 0; 2100 wake_cycle = 0; 2101 } 2102 2103 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); 2104 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); 2105 2106 return 0; 2107 } 2108 2109 static void fec_enet_adjust_link(struct net_device *ndev) 2110 { 2111 struct fec_enet_private *fep = netdev_priv(ndev); 2112 struct phy_device *phy_dev = ndev->phydev; 2113 int status_change = 0; 2114 2115 /* 2116 * If the netdev is down, or is going down, we're not interested 2117 * in link state events, so just mark our idea of the link as down 2118 * and ignore the event. 2119 */ 2120 if (!netif_running(ndev) || !netif_device_present(ndev)) { 2121 fep->link = 0; 2122 } else if (phy_dev->link) { 2123 if (!fep->link) { 2124 fep->link = phy_dev->link; 2125 status_change = 1; 2126 } 2127 2128 if (fep->full_duplex != phy_dev->duplex) { 2129 fep->full_duplex = phy_dev->duplex; 2130 status_change = 1; 2131 } 2132 2133 if (phy_dev->speed != fep->speed) { 2134 fep->speed = phy_dev->speed; 2135 status_change = 1; 2136 } 2137 2138 /* if any of the above changed restart the FEC */ 2139 if (status_change) { 2140 netif_stop_queue(ndev); 2141 napi_disable(&fep->napi); 2142 netif_tx_lock_bh(ndev); 2143 fec_restart(ndev); 2144 netif_tx_wake_all_queues(ndev); 2145 netif_tx_unlock_bh(ndev); 2146 napi_enable(&fep->napi); 2147 } 2148 if (fep->quirks & FEC_QUIRK_HAS_EEE) 2149 fec_enet_eee_mode_set(ndev, 2150 phy_dev->eee_cfg.tx_lpi_timer, 2151 phy_dev->enable_tx_lpi); 2152 } else { 2153 if (fep->link) { 2154 netif_stop_queue(ndev); 2155 napi_disable(&fep->napi); 2156 netif_tx_lock_bh(ndev); 2157 fec_stop(ndev); 2158 netif_tx_unlock_bh(ndev); 2159 napi_enable(&fep->napi); 2160 fep->link = phy_dev->link; 2161 status_change = 1; 2162 } 2163 } 2164 2165 if (status_change) 2166 phy_print_status(phy_dev); 2167 } 2168 2169 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 2170 { 2171 uint ievent; 2172 int ret; 2173 2174 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 2175 ievent & FEC_ENET_MII, 2, 30000); 2176 2177 if (!ret) 2178 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2179 2180 return ret; 2181 } 2182 2183 static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) 2184 { 2185 struct fec_enet_private *fep = bus->priv; 2186 struct device *dev = &fep->pdev->dev; 2187 int ret = 0, frame_start, frame_addr, frame_op; 2188 2189 ret = pm_runtime_resume_and_get(dev); 2190 if (ret < 0) 2191 return ret; 2192 2193 /* C22 read */ 2194 frame_op = FEC_MMFR_OP_READ; 2195 frame_start = FEC_MMFR_ST; 2196 frame_addr = regnum; 2197 2198 /* start a read op */ 2199 writel(frame_start | frame_op | 2200 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2201 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2202 2203 /* wait for end of transfer */ 2204 ret = fec_enet_mdio_wait(fep); 2205 if (ret) { 2206 netdev_err(fep->netdev, "MDIO read timeout\n"); 2207 goto out; 2208 } 2209 2210 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2211 2212 out: 2213 pm_runtime_mark_last_busy(dev); 2214 pm_runtime_put_autosuspend(dev); 2215 2216 return ret; 2217 } 2218 2219 static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id, 2220 int devad, int regnum) 2221 { 2222 struct fec_enet_private *fep = bus->priv; 2223 struct device *dev = &fep->pdev->dev; 2224 int ret = 0, frame_start, frame_op; 2225 2226 ret = pm_runtime_resume_and_get(dev); 2227 if (ret < 0) 2228 return ret; 2229 2230 frame_start = FEC_MMFR_ST_C45; 2231 2232 /* write address */ 2233 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2234 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2235 FEC_MMFR_TA | (regnum & 0xFFFF), 2236 fep->hwp + FEC_MII_DATA); 2237 2238 /* wait for end of transfer */ 2239 ret = fec_enet_mdio_wait(fep); 2240 if (ret) { 2241 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2242 goto out; 2243 } 2244 2245 frame_op = FEC_MMFR_OP_READ_C45; 2246 2247 /* start a read op */ 2248 writel(frame_start | frame_op | 2249 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2250 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2251 2252 /* wait for end of transfer */ 2253 ret = fec_enet_mdio_wait(fep); 2254 if (ret) { 2255 netdev_err(fep->netdev, "MDIO read timeout\n"); 2256 goto out; 2257 } 2258 2259 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2260 2261 out: 2262 pm_runtime_mark_last_busy(dev); 2263 pm_runtime_put_autosuspend(dev); 2264 2265 return ret; 2266 } 2267 2268 static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, 2269 u16 value) 2270 { 2271 struct fec_enet_private *fep = bus->priv; 2272 struct device *dev = &fep->pdev->dev; 2273 int ret, frame_start, frame_addr; 2274 2275 ret = pm_runtime_resume_and_get(dev); 2276 if (ret < 0) 2277 return ret; 2278 2279 /* C22 write */ 2280 frame_start = FEC_MMFR_ST; 2281 frame_addr = regnum; 2282 2283 /* start a write op */ 2284 writel(frame_start | FEC_MMFR_OP_WRITE | 2285 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2286 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2287 fep->hwp + FEC_MII_DATA); 2288 2289 /* wait for end of transfer */ 2290 ret = fec_enet_mdio_wait(fep); 2291 if (ret) 2292 netdev_err(fep->netdev, "MDIO write timeout\n"); 2293 2294 pm_runtime_mark_last_busy(dev); 2295 pm_runtime_put_autosuspend(dev); 2296 2297 return ret; 2298 } 2299 2300 static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id, 2301 int devad, int regnum, u16 value) 2302 { 2303 struct fec_enet_private *fep = bus->priv; 2304 struct device *dev = &fep->pdev->dev; 2305 int ret, frame_start; 2306 2307 ret = pm_runtime_resume_and_get(dev); 2308 if (ret < 0) 2309 return ret; 2310 2311 frame_start = FEC_MMFR_ST_C45; 2312 2313 /* write address */ 2314 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2315 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2316 FEC_MMFR_TA | (regnum & 0xFFFF), 2317 fep->hwp + FEC_MII_DATA); 2318 2319 /* wait for end of transfer */ 2320 ret = fec_enet_mdio_wait(fep); 2321 if (ret) { 2322 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2323 goto out; 2324 } 2325 2326 /* start a write op */ 2327 writel(frame_start | FEC_MMFR_OP_WRITE | 2328 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2329 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2330 fep->hwp + FEC_MII_DATA); 2331 2332 /* wait for end of transfer */ 2333 ret = fec_enet_mdio_wait(fep); 2334 if (ret) 2335 netdev_err(fep->netdev, "MDIO write timeout\n"); 2336 2337 out: 2338 pm_runtime_mark_last_busy(dev); 2339 pm_runtime_put_autosuspend(dev); 2340 2341 return ret; 2342 } 2343 2344 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 2345 { 2346 struct fec_enet_private *fep = netdev_priv(ndev); 2347 struct phy_device *phy_dev = ndev->phydev; 2348 2349 if (phy_dev) { 2350 phy_reset_after_clk_enable(phy_dev); 2351 } else if (fep->phy_node) { 2352 /* 2353 * If the PHY still is not bound to the MAC, but there is 2354 * OF PHY node and a matching PHY device instance already, 2355 * use the OF PHY node to obtain the PHY device instance, 2356 * and then use that PHY device instance when triggering 2357 * the PHY reset. 2358 */ 2359 phy_dev = of_phy_find_device(fep->phy_node); 2360 phy_reset_after_clk_enable(phy_dev); 2361 put_device(&phy_dev->mdio.dev); 2362 } 2363 } 2364 2365 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 2366 { 2367 struct fec_enet_private *fep = netdev_priv(ndev); 2368 int ret; 2369 2370 if (enable) { 2371 ret = clk_prepare_enable(fep->clk_enet_out); 2372 if (ret) 2373 return ret; 2374 2375 if (fep->clk_ptp) { 2376 mutex_lock(&fep->ptp_clk_mutex); 2377 ret = clk_prepare_enable(fep->clk_ptp); 2378 if (ret) { 2379 mutex_unlock(&fep->ptp_clk_mutex); 2380 goto failed_clk_ptp; 2381 } else { 2382 fep->ptp_clk_on = true; 2383 } 2384 mutex_unlock(&fep->ptp_clk_mutex); 2385 } 2386 2387 ret = clk_prepare_enable(fep->clk_ref); 2388 if (ret) 2389 goto failed_clk_ref; 2390 2391 ret = clk_prepare_enable(fep->clk_2x_txclk); 2392 if (ret) 2393 goto failed_clk_2x_txclk; 2394 2395 fec_enet_phy_reset_after_clk_enable(ndev); 2396 } else { 2397 clk_disable_unprepare(fep->clk_enet_out); 2398 if (fep->clk_ptp) { 2399 mutex_lock(&fep->ptp_clk_mutex); 2400 clk_disable_unprepare(fep->clk_ptp); 2401 fep->ptp_clk_on = false; 2402 mutex_unlock(&fep->ptp_clk_mutex); 2403 } 2404 clk_disable_unprepare(fep->clk_ref); 2405 clk_disable_unprepare(fep->clk_2x_txclk); 2406 } 2407 2408 return 0; 2409 2410 failed_clk_2x_txclk: 2411 if (fep->clk_ref) 2412 clk_disable_unprepare(fep->clk_ref); 2413 failed_clk_ref: 2414 if (fep->clk_ptp) { 2415 mutex_lock(&fep->ptp_clk_mutex); 2416 clk_disable_unprepare(fep->clk_ptp); 2417 fep->ptp_clk_on = false; 2418 mutex_unlock(&fep->ptp_clk_mutex); 2419 } 2420 failed_clk_ptp: 2421 clk_disable_unprepare(fep->clk_enet_out); 2422 2423 return ret; 2424 } 2425 2426 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep, 2427 struct device_node *np) 2428 { 2429 u32 rgmii_tx_delay, rgmii_rx_delay; 2430 2431 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ 2432 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { 2433 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) { 2434 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); 2435 return -EINVAL; 2436 } else if (rgmii_tx_delay == 2000) { 2437 fep->rgmii_txc_dly = true; 2438 } 2439 } 2440 2441 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */ 2442 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { 2443 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) { 2444 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); 2445 return -EINVAL; 2446 } else if (rgmii_rx_delay == 2000) { 2447 fep->rgmii_rxc_dly = true; 2448 } 2449 } 2450 2451 return 0; 2452 } 2453 2454 static int fec_enet_mii_probe(struct net_device *ndev) 2455 { 2456 struct fec_enet_private *fep = netdev_priv(ndev); 2457 struct phy_device *phy_dev = NULL; 2458 char mdio_bus_id[MII_BUS_ID_SIZE]; 2459 char phy_name[MII_BUS_ID_SIZE + 3]; 2460 int phy_id; 2461 int dev_id = fep->dev_id; 2462 2463 if (fep->phy_node) { 2464 phy_dev = of_phy_connect(ndev, fep->phy_node, 2465 &fec_enet_adjust_link, 0, 2466 fep->phy_interface); 2467 if (!phy_dev) { 2468 netdev_err(ndev, "Unable to connect to phy\n"); 2469 return -ENODEV; 2470 } 2471 } else { 2472 /* check for attached phy */ 2473 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2474 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2475 continue; 2476 if (dev_id--) 2477 continue; 2478 strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2479 break; 2480 } 2481 2482 if (phy_id >= PHY_MAX_ADDR) { 2483 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2484 strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2485 phy_id = 0; 2486 } 2487 2488 snprintf(phy_name, sizeof(phy_name), 2489 PHY_ID_FMT, mdio_bus_id, phy_id); 2490 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2491 fep->phy_interface); 2492 } 2493 2494 if (IS_ERR(phy_dev)) { 2495 netdev_err(ndev, "could not attach to PHY\n"); 2496 return PTR_ERR(phy_dev); 2497 } 2498 2499 /* mask with MAC supported features */ 2500 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2501 phy_set_max_speed(phy_dev, 1000); 2502 phy_remove_link_mode(phy_dev, 2503 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2504 #if !defined(CONFIG_M5272) 2505 phy_support_sym_pause(phy_dev); 2506 #endif 2507 } 2508 else 2509 phy_set_max_speed(phy_dev, 100); 2510 2511 if (fep->quirks & FEC_QUIRK_HAS_EEE) 2512 phy_support_eee(phy_dev); 2513 2514 fep->link = 0; 2515 fep->full_duplex = 0; 2516 2517 phy_attached_info(phy_dev); 2518 2519 return 0; 2520 } 2521 2522 static int fec_enet_mii_init(struct platform_device *pdev) 2523 { 2524 static struct mii_bus *fec0_mii_bus; 2525 struct net_device *ndev = platform_get_drvdata(pdev); 2526 struct fec_enet_private *fep = netdev_priv(ndev); 2527 bool suppress_preamble = false; 2528 struct phy_device *phydev; 2529 struct device_node *node; 2530 int err = -ENXIO; 2531 u32 mii_speed, holdtime; 2532 u32 bus_freq; 2533 int addr; 2534 2535 /* 2536 * The i.MX28 dual fec interfaces are not equal. 2537 * Here are the differences: 2538 * 2539 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2540 * - fec0 acts as the 1588 time master while fec1 is slave 2541 * - external phys can only be configured by fec0 2542 * 2543 * That is to say fec1 can not work independently. It only works 2544 * when fec0 is working. The reason behind this design is that the 2545 * second interface is added primarily for Switch mode. 2546 * 2547 * Because of the last point above, both phys are attached on fec0 2548 * mdio interface in board design, and need to be configured by 2549 * fec0 mii_bus. 2550 */ 2551 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2552 /* fec1 uses fec0 mii_bus */ 2553 if (mii_cnt && fec0_mii_bus) { 2554 fep->mii_bus = fec0_mii_bus; 2555 mii_cnt++; 2556 return 0; 2557 } 2558 return -ENOENT; 2559 } 2560 2561 bus_freq = 2500000; /* 2.5MHz by default */ 2562 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2563 if (node) { 2564 of_property_read_u32(node, "clock-frequency", &bus_freq); 2565 suppress_preamble = of_property_read_bool(node, 2566 "suppress-preamble"); 2567 } 2568 2569 /* 2570 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2571 * 2572 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2573 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2574 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2575 * document. 2576 */ 2577 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2578 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2579 mii_speed--; 2580 if (mii_speed > 63) { 2581 dev_err(&pdev->dev, 2582 "fec clock (%lu) too fast to get right mii speed\n", 2583 clk_get_rate(fep->clk_ipg)); 2584 err = -EINVAL; 2585 goto err_out; 2586 } 2587 2588 /* 2589 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2590 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2591 * versions are RAZ there, so just ignore the difference and write the 2592 * register always. 2593 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2594 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2595 * output. 2596 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2597 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2598 * holdtime cannot result in a value greater than 3. 2599 */ 2600 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2601 2602 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2603 2604 if (suppress_preamble) 2605 fep->phy_speed |= BIT(7); 2606 2607 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2608 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2609 * MII event generation condition: 2610 * - writing MSCR: 2611 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2612 * mscr_reg_data_in[7:0] != 0 2613 * - writing MMFR: 2614 * - mscr[7:0]_not_zero 2615 */ 2616 writel(0, fep->hwp + FEC_MII_DATA); 2617 } 2618 2619 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2620 2621 /* Clear any pending transaction complete indication */ 2622 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2623 2624 fep->mii_bus = mdiobus_alloc(); 2625 if (fep->mii_bus == NULL) { 2626 err = -ENOMEM; 2627 goto err_out; 2628 } 2629 2630 fep->mii_bus->name = "fec_enet_mii_bus"; 2631 fep->mii_bus->read = fec_enet_mdio_read_c22; 2632 fep->mii_bus->write = fec_enet_mdio_write_c22; 2633 if (fep->quirks & FEC_QUIRK_HAS_MDIO_C45) { 2634 fep->mii_bus->read_c45 = fec_enet_mdio_read_c45; 2635 fep->mii_bus->write_c45 = fec_enet_mdio_write_c45; 2636 } 2637 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2638 pdev->name, fep->dev_id + 1); 2639 fep->mii_bus->priv = fep; 2640 fep->mii_bus->parent = &pdev->dev; 2641 2642 err = of_mdiobus_register(fep->mii_bus, node); 2643 if (err) 2644 goto err_out_free_mdiobus; 2645 of_node_put(node); 2646 2647 /* find all the PHY devices on the bus and set mac_managed_pm to true */ 2648 for (addr = 0; addr < PHY_MAX_ADDR; addr++) { 2649 phydev = mdiobus_get_phy(fep->mii_bus, addr); 2650 if (phydev) 2651 phydev->mac_managed_pm = true; 2652 } 2653 2654 mii_cnt++; 2655 2656 /* save fec0 mii_bus */ 2657 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2658 fec0_mii_bus = fep->mii_bus; 2659 2660 return 0; 2661 2662 err_out_free_mdiobus: 2663 mdiobus_free(fep->mii_bus); 2664 err_out: 2665 of_node_put(node); 2666 return err; 2667 } 2668 2669 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2670 { 2671 if (--mii_cnt == 0) { 2672 mdiobus_unregister(fep->mii_bus); 2673 mdiobus_free(fep->mii_bus); 2674 } 2675 } 2676 2677 static void fec_enet_get_drvinfo(struct net_device *ndev, 2678 struct ethtool_drvinfo *info) 2679 { 2680 struct fec_enet_private *fep = netdev_priv(ndev); 2681 2682 strscpy(info->driver, fep->pdev->dev.driver->name, 2683 sizeof(info->driver)); 2684 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2685 } 2686 2687 static int fec_enet_get_regs_len(struct net_device *ndev) 2688 { 2689 struct fec_enet_private *fep = netdev_priv(ndev); 2690 struct resource *r; 2691 int s = 0; 2692 2693 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2694 if (r) 2695 s = resource_size(r); 2696 2697 return s; 2698 } 2699 2700 /* List of registers that can be safety be read to dump them with ethtool */ 2701 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2702 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2703 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2704 static __u32 fec_enet_register_version = 2; 2705 static u32 fec_enet_register_offset[] = { 2706 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2707 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2708 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2709 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2710 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2711 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2712 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2713 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2714 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2715 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2716 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2717 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2718 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2719 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2720 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2721 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2722 RMON_T_P_GTE2048, RMON_T_OCTETS, 2723 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2724 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2725 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2726 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2727 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2728 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2729 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2730 RMON_R_P_GTE2048, RMON_R_OCTETS, 2731 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2732 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2733 }; 2734 /* for i.MX6ul */ 2735 static u32 fec_enet_register_offset_6ul[] = { 2736 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2737 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2738 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0, 2739 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, 2740 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0, 2741 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2742 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, 2743 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2744 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2745 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2746 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2747 RMON_T_P_GTE2048, RMON_T_OCTETS, 2748 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2749 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2750 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2751 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2752 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2753 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2754 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2755 RMON_R_P_GTE2048, RMON_R_OCTETS, 2756 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2757 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2758 }; 2759 #else 2760 static __u32 fec_enet_register_version = 1; 2761 static u32 fec_enet_register_offset[] = { 2762 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2763 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2764 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2765 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2766 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2767 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2768 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2769 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2770 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2771 }; 2772 #endif 2773 2774 static void fec_enet_get_regs(struct net_device *ndev, 2775 struct ethtool_regs *regs, void *regbuf) 2776 { 2777 struct fec_enet_private *fep = netdev_priv(ndev); 2778 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2779 struct device *dev = &fep->pdev->dev; 2780 u32 *buf = (u32 *)regbuf; 2781 u32 i, off; 2782 int ret; 2783 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2784 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2785 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2786 u32 *reg_list; 2787 u32 reg_cnt; 2788 2789 if (!of_machine_is_compatible("fsl,imx6ul")) { 2790 reg_list = fec_enet_register_offset; 2791 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2792 } else { 2793 reg_list = fec_enet_register_offset_6ul; 2794 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul); 2795 } 2796 #else 2797 /* coldfire */ 2798 static u32 *reg_list = fec_enet_register_offset; 2799 static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2800 #endif 2801 ret = pm_runtime_resume_and_get(dev); 2802 if (ret < 0) 2803 return; 2804 2805 regs->version = fec_enet_register_version; 2806 2807 memset(buf, 0, regs->len); 2808 2809 for (i = 0; i < reg_cnt; i++) { 2810 off = reg_list[i]; 2811 2812 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2813 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2814 continue; 2815 2816 off >>= 2; 2817 buf[off] = readl(&theregs[off]); 2818 } 2819 2820 pm_runtime_mark_last_busy(dev); 2821 pm_runtime_put_autosuspend(dev); 2822 } 2823 2824 static int fec_enet_get_ts_info(struct net_device *ndev, 2825 struct kernel_ethtool_ts_info *info) 2826 { 2827 struct fec_enet_private *fep = netdev_priv(ndev); 2828 2829 if (fep->bufdesc_ex) { 2830 2831 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2832 SOF_TIMESTAMPING_TX_HARDWARE | 2833 SOF_TIMESTAMPING_RX_HARDWARE | 2834 SOF_TIMESTAMPING_RAW_HARDWARE; 2835 if (fep->ptp_clock) 2836 info->phc_index = ptp_clock_index(fep->ptp_clock); 2837 2838 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2839 (1 << HWTSTAMP_TX_ON); 2840 2841 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2842 (1 << HWTSTAMP_FILTER_ALL); 2843 return 0; 2844 } else { 2845 return ethtool_op_get_ts_info(ndev, info); 2846 } 2847 } 2848 2849 #if !defined(CONFIG_M5272) 2850 2851 static void fec_enet_get_pauseparam(struct net_device *ndev, 2852 struct ethtool_pauseparam *pause) 2853 { 2854 struct fec_enet_private *fep = netdev_priv(ndev); 2855 2856 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2857 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2858 pause->rx_pause = pause->tx_pause; 2859 } 2860 2861 static int fec_enet_set_pauseparam(struct net_device *ndev, 2862 struct ethtool_pauseparam *pause) 2863 { 2864 struct fec_enet_private *fep = netdev_priv(ndev); 2865 2866 if (!ndev->phydev) 2867 return -ENODEV; 2868 2869 if (pause->tx_pause != pause->rx_pause) { 2870 netdev_info(ndev, 2871 "hardware only support enable/disable both tx and rx"); 2872 return -EINVAL; 2873 } 2874 2875 fep->pause_flag = 0; 2876 2877 /* tx pause must be same as rx pause */ 2878 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2879 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2880 2881 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2882 pause->autoneg); 2883 2884 if (pause->autoneg) { 2885 if (netif_running(ndev)) 2886 fec_stop(ndev); 2887 phy_start_aneg(ndev->phydev); 2888 } 2889 if (netif_running(ndev)) { 2890 napi_disable(&fep->napi); 2891 netif_tx_lock_bh(ndev); 2892 fec_restart(ndev); 2893 netif_tx_wake_all_queues(ndev); 2894 netif_tx_unlock_bh(ndev); 2895 napi_enable(&fep->napi); 2896 } 2897 2898 return 0; 2899 } 2900 2901 static const struct fec_stat { 2902 char name[ETH_GSTRING_LEN]; 2903 u16 offset; 2904 } fec_stats[] = { 2905 /* RMON TX */ 2906 { "tx_dropped", RMON_T_DROP }, 2907 { "tx_packets", RMON_T_PACKETS }, 2908 { "tx_broadcast", RMON_T_BC_PKT }, 2909 { "tx_multicast", RMON_T_MC_PKT }, 2910 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2911 { "tx_undersize", RMON_T_UNDERSIZE }, 2912 { "tx_oversize", RMON_T_OVERSIZE }, 2913 { "tx_fragment", RMON_T_FRAG }, 2914 { "tx_jabber", RMON_T_JAB }, 2915 { "tx_collision", RMON_T_COL }, 2916 { "tx_64byte", RMON_T_P64 }, 2917 { "tx_65to127byte", RMON_T_P65TO127 }, 2918 { "tx_128to255byte", RMON_T_P128TO255 }, 2919 { "tx_256to511byte", RMON_T_P256TO511 }, 2920 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2921 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2922 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2923 { "tx_octets", RMON_T_OCTETS }, 2924 2925 /* IEEE TX */ 2926 { "IEEE_tx_drop", IEEE_T_DROP }, 2927 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2928 { "IEEE_tx_1col", IEEE_T_1COL }, 2929 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2930 { "IEEE_tx_def", IEEE_T_DEF }, 2931 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2932 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2933 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2934 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2935 { "IEEE_tx_sqe", IEEE_T_SQE }, 2936 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2937 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2938 2939 /* RMON RX */ 2940 { "rx_packets", RMON_R_PACKETS }, 2941 { "rx_broadcast", RMON_R_BC_PKT }, 2942 { "rx_multicast", RMON_R_MC_PKT }, 2943 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2944 { "rx_undersize", RMON_R_UNDERSIZE }, 2945 { "rx_oversize", RMON_R_OVERSIZE }, 2946 { "rx_fragment", RMON_R_FRAG }, 2947 { "rx_jabber", RMON_R_JAB }, 2948 { "rx_64byte", RMON_R_P64 }, 2949 { "rx_65to127byte", RMON_R_P65TO127 }, 2950 { "rx_128to255byte", RMON_R_P128TO255 }, 2951 { "rx_256to511byte", RMON_R_P256TO511 }, 2952 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2953 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2954 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2955 { "rx_octets", RMON_R_OCTETS }, 2956 2957 /* IEEE RX */ 2958 { "IEEE_rx_drop", IEEE_R_DROP }, 2959 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2960 { "IEEE_rx_crc", IEEE_R_CRC }, 2961 { "IEEE_rx_align", IEEE_R_ALIGN }, 2962 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2963 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2964 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2965 }; 2966 2967 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2968 2969 static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = { 2970 "rx_xdp_redirect", /* RX_XDP_REDIRECT = 0, */ 2971 "rx_xdp_pass", /* RX_XDP_PASS, */ 2972 "rx_xdp_drop", /* RX_XDP_DROP, */ 2973 "rx_xdp_tx", /* RX_XDP_TX, */ 2974 "rx_xdp_tx_errors", /* RX_XDP_TX_ERRORS, */ 2975 "tx_xdp_xmit", /* TX_XDP_XMIT, */ 2976 "tx_xdp_xmit_errors", /* TX_XDP_XMIT_ERRORS, */ 2977 }; 2978 2979 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2980 { 2981 struct fec_enet_private *fep = netdev_priv(dev); 2982 int i; 2983 2984 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2985 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2986 } 2987 2988 static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data) 2989 { 2990 u64 xdp_stats[XDP_STATS_TOTAL] = { 0 }; 2991 struct fec_enet_priv_rx_q *rxq; 2992 int i, j; 2993 2994 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2995 rxq = fep->rx_queue[i]; 2996 2997 for (j = 0; j < XDP_STATS_TOTAL; j++) 2998 xdp_stats[j] += rxq->stats[j]; 2999 } 3000 3001 memcpy(data, xdp_stats, sizeof(xdp_stats)); 3002 } 3003 3004 static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data) 3005 { 3006 #ifdef CONFIG_PAGE_POOL_STATS 3007 struct page_pool_stats stats = {}; 3008 struct fec_enet_priv_rx_q *rxq; 3009 int i; 3010 3011 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 3012 rxq = fep->rx_queue[i]; 3013 3014 if (!rxq->page_pool) 3015 continue; 3016 3017 page_pool_get_stats(rxq->page_pool, &stats); 3018 } 3019 3020 page_pool_ethtool_stats_get(data, &stats); 3021 #endif 3022 } 3023 3024 static void fec_enet_get_ethtool_stats(struct net_device *dev, 3025 struct ethtool_stats *stats, u64 *data) 3026 { 3027 struct fec_enet_private *fep = netdev_priv(dev); 3028 3029 if (netif_running(dev)) 3030 fec_enet_update_ethtool_stats(dev); 3031 3032 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 3033 data += FEC_STATS_SIZE / sizeof(u64); 3034 3035 fec_enet_get_xdp_stats(fep, data); 3036 data += XDP_STATS_TOTAL; 3037 3038 fec_enet_page_pool_stats(fep, data); 3039 } 3040 3041 static void fec_enet_get_strings(struct net_device *netdev, 3042 u32 stringset, u8 *data) 3043 { 3044 int i; 3045 switch (stringset) { 3046 case ETH_SS_STATS: 3047 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) { 3048 ethtool_puts(&data, fec_stats[i].name); 3049 } 3050 for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) { 3051 ethtool_puts(&data, fec_xdp_stat_strs[i]); 3052 } 3053 page_pool_ethtool_stats_get_strings(data); 3054 3055 break; 3056 case ETH_SS_TEST: 3057 net_selftest_get_strings(data); 3058 break; 3059 } 3060 } 3061 3062 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 3063 { 3064 int count; 3065 3066 switch (sset) { 3067 case ETH_SS_STATS: 3068 count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL; 3069 count += page_pool_ethtool_stats_get_count(); 3070 return count; 3071 3072 case ETH_SS_TEST: 3073 return net_selftest_get_count(); 3074 default: 3075 return -EOPNOTSUPP; 3076 } 3077 } 3078 3079 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 3080 { 3081 struct fec_enet_private *fep = netdev_priv(dev); 3082 struct fec_enet_priv_rx_q *rxq; 3083 int i, j; 3084 3085 /* Disable MIB statistics counters */ 3086 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 3087 3088 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 3089 writel(0, fep->hwp + fec_stats[i].offset); 3090 3091 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 3092 rxq = fep->rx_queue[i]; 3093 for (j = 0; j < XDP_STATS_TOTAL; j++) 3094 rxq->stats[j] = 0; 3095 } 3096 3097 /* Don't disable MIB statistics counters */ 3098 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 3099 } 3100 3101 #else /* !defined(CONFIG_M5272) */ 3102 #define FEC_STATS_SIZE 0 3103 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 3104 { 3105 } 3106 3107 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 3108 { 3109 } 3110 #endif /* !defined(CONFIG_M5272) */ 3111 3112 /* ITR clock source is enet system clock (clk_ahb). 3113 * TCTT unit is cycle_ns * 64 cycle 3114 * So, the ICTT value = X us / (cycle_ns * 64) 3115 */ 3116 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 3117 { 3118 struct fec_enet_private *fep = netdev_priv(ndev); 3119 3120 return us * (fep->itr_clk_rate / 64000) / 1000; 3121 } 3122 3123 /* Set threshold for interrupt coalescing */ 3124 static void fec_enet_itr_coal_set(struct net_device *ndev) 3125 { 3126 struct fec_enet_private *fep = netdev_priv(ndev); 3127 int rx_itr, tx_itr; 3128 3129 /* Must be greater than zero to avoid unpredictable behavior */ 3130 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 3131 !fep->tx_time_itr || !fep->tx_pkts_itr) 3132 return; 3133 3134 /* Select enet system clock as Interrupt Coalescing 3135 * timer Clock Source 3136 */ 3137 rx_itr = FEC_ITR_CLK_SEL; 3138 tx_itr = FEC_ITR_CLK_SEL; 3139 3140 /* set ICFT and ICTT */ 3141 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 3142 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 3143 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 3144 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 3145 3146 rx_itr |= FEC_ITR_EN; 3147 tx_itr |= FEC_ITR_EN; 3148 3149 writel(tx_itr, fep->hwp + FEC_TXIC0); 3150 writel(rx_itr, fep->hwp + FEC_RXIC0); 3151 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 3152 writel(tx_itr, fep->hwp + FEC_TXIC1); 3153 writel(rx_itr, fep->hwp + FEC_RXIC1); 3154 writel(tx_itr, fep->hwp + FEC_TXIC2); 3155 writel(rx_itr, fep->hwp + FEC_RXIC2); 3156 } 3157 } 3158 3159 static int fec_enet_get_coalesce(struct net_device *ndev, 3160 struct ethtool_coalesce *ec, 3161 struct kernel_ethtool_coalesce *kernel_coal, 3162 struct netlink_ext_ack *extack) 3163 { 3164 struct fec_enet_private *fep = netdev_priv(ndev); 3165 3166 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3167 return -EOPNOTSUPP; 3168 3169 ec->rx_coalesce_usecs = fep->rx_time_itr; 3170 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 3171 3172 ec->tx_coalesce_usecs = fep->tx_time_itr; 3173 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 3174 3175 return 0; 3176 } 3177 3178 static int fec_enet_set_coalesce(struct net_device *ndev, 3179 struct ethtool_coalesce *ec, 3180 struct kernel_ethtool_coalesce *kernel_coal, 3181 struct netlink_ext_ack *extack) 3182 { 3183 struct fec_enet_private *fep = netdev_priv(ndev); 3184 struct device *dev = &fep->pdev->dev; 3185 unsigned int cycle; 3186 3187 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3188 return -EOPNOTSUPP; 3189 3190 if (ec->rx_max_coalesced_frames > 255) { 3191 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 3192 return -EINVAL; 3193 } 3194 3195 if (ec->tx_max_coalesced_frames > 255) { 3196 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 3197 return -EINVAL; 3198 } 3199 3200 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 3201 if (cycle > 0xFFFF) { 3202 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 3203 return -EINVAL; 3204 } 3205 3206 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 3207 if (cycle > 0xFFFF) { 3208 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 3209 return -EINVAL; 3210 } 3211 3212 fep->rx_time_itr = ec->rx_coalesce_usecs; 3213 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 3214 3215 fep->tx_time_itr = ec->tx_coalesce_usecs; 3216 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 3217 3218 fec_enet_itr_coal_set(ndev); 3219 3220 return 0; 3221 } 3222 3223 static int 3224 fec_enet_get_eee(struct net_device *ndev, struct ethtool_keee *edata) 3225 { 3226 struct fec_enet_private *fep = netdev_priv(ndev); 3227 3228 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3229 return -EOPNOTSUPP; 3230 3231 if (!netif_running(ndev)) 3232 return -ENETDOWN; 3233 3234 return phy_ethtool_get_eee(ndev->phydev, edata); 3235 } 3236 3237 static int 3238 fec_enet_set_eee(struct net_device *ndev, struct ethtool_keee *edata) 3239 { 3240 struct fec_enet_private *fep = netdev_priv(ndev); 3241 3242 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3243 return -EOPNOTSUPP; 3244 3245 if (!netif_running(ndev)) 3246 return -ENETDOWN; 3247 3248 return phy_ethtool_set_eee(ndev->phydev, edata); 3249 } 3250 3251 static void 3252 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3253 { 3254 struct fec_enet_private *fep = netdev_priv(ndev); 3255 3256 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 3257 wol->supported = WAKE_MAGIC; 3258 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 3259 } else { 3260 wol->supported = wol->wolopts = 0; 3261 } 3262 } 3263 3264 static int 3265 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3266 { 3267 struct fec_enet_private *fep = netdev_priv(ndev); 3268 3269 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 3270 return -EINVAL; 3271 3272 if (wol->wolopts & ~WAKE_MAGIC) 3273 return -EINVAL; 3274 3275 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 3276 if (device_may_wakeup(&ndev->dev)) 3277 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 3278 else 3279 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 3280 3281 return 0; 3282 } 3283 3284 static const struct ethtool_ops fec_enet_ethtool_ops = { 3285 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3286 ETHTOOL_COALESCE_MAX_FRAMES, 3287 .get_drvinfo = fec_enet_get_drvinfo, 3288 .get_regs_len = fec_enet_get_regs_len, 3289 .get_regs = fec_enet_get_regs, 3290 .nway_reset = phy_ethtool_nway_reset, 3291 .get_link = ethtool_op_get_link, 3292 .get_coalesce = fec_enet_get_coalesce, 3293 .set_coalesce = fec_enet_set_coalesce, 3294 #ifndef CONFIG_M5272 3295 .get_pauseparam = fec_enet_get_pauseparam, 3296 .set_pauseparam = fec_enet_set_pauseparam, 3297 .get_strings = fec_enet_get_strings, 3298 .get_ethtool_stats = fec_enet_get_ethtool_stats, 3299 .get_sset_count = fec_enet_get_sset_count, 3300 #endif 3301 .get_ts_info = fec_enet_get_ts_info, 3302 .get_wol = fec_enet_get_wol, 3303 .set_wol = fec_enet_set_wol, 3304 .get_eee = fec_enet_get_eee, 3305 .set_eee = fec_enet_set_eee, 3306 .get_link_ksettings = phy_ethtool_get_link_ksettings, 3307 .set_link_ksettings = phy_ethtool_set_link_ksettings, 3308 .self_test = net_selftest, 3309 }; 3310 3311 static void fec_enet_free_buffers(struct net_device *ndev) 3312 { 3313 struct fec_enet_private *fep = netdev_priv(ndev); 3314 unsigned int i; 3315 struct fec_enet_priv_tx_q *txq; 3316 struct fec_enet_priv_rx_q *rxq; 3317 unsigned int q; 3318 3319 for (q = 0; q < fep->num_rx_queues; q++) { 3320 rxq = fep->rx_queue[q]; 3321 for (i = 0; i < rxq->bd.ring_size; i++) 3322 page_pool_put_full_page(rxq->page_pool, rxq->rx_skb_info[i].page, false); 3323 3324 for (i = 0; i < XDP_STATS_TOTAL; i++) 3325 rxq->stats[i] = 0; 3326 3327 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 3328 xdp_rxq_info_unreg(&rxq->xdp_rxq); 3329 page_pool_destroy(rxq->page_pool); 3330 rxq->page_pool = NULL; 3331 } 3332 3333 for (q = 0; q < fep->num_tx_queues; q++) { 3334 txq = fep->tx_queue[q]; 3335 for (i = 0; i < txq->bd.ring_size; i++) { 3336 kfree(txq->tx_bounce[i]); 3337 txq->tx_bounce[i] = NULL; 3338 3339 if (!txq->tx_buf[i].buf_p) { 3340 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3341 continue; 3342 } 3343 3344 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 3345 dev_kfree_skb(txq->tx_buf[i].buf_p); 3346 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 3347 xdp_return_frame(txq->tx_buf[i].buf_p); 3348 } else { 3349 struct page *page = txq->tx_buf[i].buf_p; 3350 3351 page_pool_put_page(page->pp, page, 0, false); 3352 } 3353 3354 txq->tx_buf[i].buf_p = NULL; 3355 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3356 } 3357 } 3358 } 3359 3360 static void fec_enet_free_queue(struct net_device *ndev) 3361 { 3362 struct fec_enet_private *fep = netdev_priv(ndev); 3363 int i; 3364 struct fec_enet_priv_tx_q *txq; 3365 3366 for (i = 0; i < fep->num_tx_queues; i++) 3367 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 3368 txq = fep->tx_queue[i]; 3369 fec_dma_free(&fep->pdev->dev, 3370 txq->bd.ring_size * TSO_HEADER_SIZE, 3371 txq->tso_hdrs, txq->tso_hdrs_dma); 3372 } 3373 3374 for (i = 0; i < fep->num_rx_queues; i++) 3375 kfree(fep->rx_queue[i]); 3376 for (i = 0; i < fep->num_tx_queues; i++) 3377 kfree(fep->tx_queue[i]); 3378 } 3379 3380 static int fec_enet_alloc_queue(struct net_device *ndev) 3381 { 3382 struct fec_enet_private *fep = netdev_priv(ndev); 3383 int i; 3384 int ret = 0; 3385 struct fec_enet_priv_tx_q *txq; 3386 3387 for (i = 0; i < fep->num_tx_queues; i++) { 3388 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 3389 if (!txq) { 3390 ret = -ENOMEM; 3391 goto alloc_failed; 3392 } 3393 3394 fep->tx_queue[i] = txq; 3395 txq->bd.ring_size = TX_RING_SIZE; 3396 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 3397 3398 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 3399 txq->tx_wake_threshold = FEC_MAX_SKB_DESCS + 2 * MAX_SKB_FRAGS; 3400 3401 txq->tso_hdrs = fec_dma_alloc(&fep->pdev->dev, 3402 txq->bd.ring_size * TSO_HEADER_SIZE, 3403 &txq->tso_hdrs_dma, GFP_KERNEL); 3404 if (!txq->tso_hdrs) { 3405 ret = -ENOMEM; 3406 goto alloc_failed; 3407 } 3408 } 3409 3410 for (i = 0; i < fep->num_rx_queues; i++) { 3411 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 3412 GFP_KERNEL); 3413 if (!fep->rx_queue[i]) { 3414 ret = -ENOMEM; 3415 goto alloc_failed; 3416 } 3417 3418 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 3419 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 3420 } 3421 return ret; 3422 3423 alloc_failed: 3424 fec_enet_free_queue(ndev); 3425 return ret; 3426 } 3427 3428 static int 3429 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 3430 { 3431 struct fec_enet_private *fep = netdev_priv(ndev); 3432 struct fec_enet_priv_rx_q *rxq; 3433 dma_addr_t phys_addr; 3434 struct bufdesc *bdp; 3435 struct page *page; 3436 int i, err; 3437 3438 rxq = fep->rx_queue[queue]; 3439 bdp = rxq->bd.base; 3440 3441 err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size); 3442 if (err < 0) { 3443 netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err); 3444 return err; 3445 } 3446 3447 for (i = 0; i < rxq->bd.ring_size; i++) { 3448 page = page_pool_dev_alloc_pages(rxq->page_pool); 3449 if (!page) 3450 goto err_alloc; 3451 3452 phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM; 3453 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 3454 3455 rxq->rx_skb_info[i].page = page; 3456 rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM; 3457 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3458 3459 if (fep->bufdesc_ex) { 3460 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3461 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 3462 } 3463 3464 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3465 } 3466 3467 /* Set the last buffer to wrap. */ 3468 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3469 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3470 return 0; 3471 3472 err_alloc: 3473 fec_enet_free_buffers(ndev); 3474 return -ENOMEM; 3475 } 3476 3477 static int 3478 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 3479 { 3480 struct fec_enet_private *fep = netdev_priv(ndev); 3481 unsigned int i; 3482 struct bufdesc *bdp; 3483 struct fec_enet_priv_tx_q *txq; 3484 3485 txq = fep->tx_queue[queue]; 3486 bdp = txq->bd.base; 3487 for (i = 0; i < txq->bd.ring_size; i++) { 3488 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 3489 if (!txq->tx_bounce[i]) 3490 goto err_alloc; 3491 3492 bdp->cbd_sc = cpu_to_fec16(0); 3493 bdp->cbd_bufaddr = cpu_to_fec32(0); 3494 3495 if (fep->bufdesc_ex) { 3496 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3497 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 3498 } 3499 3500 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3501 } 3502 3503 /* Set the last buffer to wrap. */ 3504 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3505 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3506 3507 return 0; 3508 3509 err_alloc: 3510 fec_enet_free_buffers(ndev); 3511 return -ENOMEM; 3512 } 3513 3514 static int fec_enet_alloc_buffers(struct net_device *ndev) 3515 { 3516 struct fec_enet_private *fep = netdev_priv(ndev); 3517 unsigned int i; 3518 3519 for (i = 0; i < fep->num_rx_queues; i++) 3520 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3521 return -ENOMEM; 3522 3523 for (i = 0; i < fep->num_tx_queues; i++) 3524 if (fec_enet_alloc_txq_buffers(ndev, i)) 3525 return -ENOMEM; 3526 return 0; 3527 } 3528 3529 static int 3530 fec_enet_open(struct net_device *ndev) 3531 { 3532 struct fec_enet_private *fep = netdev_priv(ndev); 3533 int ret; 3534 bool reset_again; 3535 3536 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3537 if (ret < 0) 3538 return ret; 3539 3540 pinctrl_pm_select_default_state(&fep->pdev->dev); 3541 ret = fec_enet_clk_enable(ndev, true); 3542 if (ret) 3543 goto clk_enable; 3544 3545 /* During the first fec_enet_open call the PHY isn't probed at this 3546 * point. Therefore the phy_reset_after_clk_enable() call within 3547 * fec_enet_clk_enable() fails. As we need this reset in order to be 3548 * sure the PHY is working correctly we check if we need to reset again 3549 * later when the PHY is probed 3550 */ 3551 if (ndev->phydev && ndev->phydev->drv) 3552 reset_again = false; 3553 else 3554 reset_again = true; 3555 3556 /* I should reset the ring buffers here, but I don't yet know 3557 * a simple way to do that. 3558 */ 3559 3560 ret = fec_enet_alloc_buffers(ndev); 3561 if (ret) 3562 goto err_enet_alloc; 3563 3564 /* Init MAC prior to mii bus probe */ 3565 fec_restart(ndev); 3566 3567 /* Call phy_reset_after_clk_enable() again if it failed during 3568 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3569 */ 3570 if (reset_again) 3571 fec_enet_phy_reset_after_clk_enable(ndev); 3572 3573 /* Probe and connect to PHY when open the interface */ 3574 ret = fec_enet_mii_probe(ndev); 3575 if (ret) 3576 goto err_enet_mii_probe; 3577 3578 if (fep->quirks & FEC_QUIRK_ERR006687) 3579 imx6q_cpuidle_fec_irqs_used(); 3580 3581 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3582 cpu_latency_qos_add_request(&fep->pm_qos_req, 0); 3583 3584 napi_enable(&fep->napi); 3585 phy_start(ndev->phydev); 3586 netif_tx_start_all_queues(ndev); 3587 3588 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3589 FEC_WOL_FLAG_ENABLE); 3590 3591 return 0; 3592 3593 err_enet_mii_probe: 3594 fec_enet_free_buffers(ndev); 3595 err_enet_alloc: 3596 fec_enet_clk_enable(ndev, false); 3597 clk_enable: 3598 pm_runtime_mark_last_busy(&fep->pdev->dev); 3599 pm_runtime_put_autosuspend(&fep->pdev->dev); 3600 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3601 return ret; 3602 } 3603 3604 static int 3605 fec_enet_close(struct net_device *ndev) 3606 { 3607 struct fec_enet_private *fep = netdev_priv(ndev); 3608 3609 phy_stop(ndev->phydev); 3610 3611 if (netif_device_present(ndev)) { 3612 napi_disable(&fep->napi); 3613 netif_tx_disable(ndev); 3614 fec_stop(ndev); 3615 } 3616 3617 phy_disconnect(ndev->phydev); 3618 3619 if (fep->quirks & FEC_QUIRK_ERR006687) 3620 imx6q_cpuidle_fec_irqs_unused(); 3621 3622 fec_enet_update_ethtool_stats(ndev); 3623 3624 fec_enet_clk_enable(ndev, false); 3625 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3626 cpu_latency_qos_remove_request(&fep->pm_qos_req); 3627 3628 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3629 pm_runtime_mark_last_busy(&fep->pdev->dev); 3630 pm_runtime_put_autosuspend(&fep->pdev->dev); 3631 3632 fec_enet_free_buffers(ndev); 3633 3634 return 0; 3635 } 3636 3637 /* Set or clear the multicast filter for this adaptor. 3638 * Skeleton taken from sunlance driver. 3639 * The CPM Ethernet implementation allows Multicast as well as individual 3640 * MAC address filtering. Some of the drivers check to make sure it is 3641 * a group multicast address, and discard those that are not. I guess I 3642 * will do the same for now, but just remove the test if you want 3643 * individual filtering as well (do the upper net layers want or support 3644 * this kind of feature?). 3645 */ 3646 3647 #define FEC_HASH_BITS 6 /* #bits in hash */ 3648 3649 static void set_multicast_list(struct net_device *ndev) 3650 { 3651 struct fec_enet_private *fep = netdev_priv(ndev); 3652 struct netdev_hw_addr *ha; 3653 unsigned int crc, tmp; 3654 unsigned char hash; 3655 unsigned int hash_high = 0, hash_low = 0; 3656 3657 if (ndev->flags & IFF_PROMISC) { 3658 tmp = readl(fep->hwp + FEC_R_CNTRL); 3659 tmp |= 0x8; 3660 writel(tmp, fep->hwp + FEC_R_CNTRL); 3661 return; 3662 } 3663 3664 tmp = readl(fep->hwp + FEC_R_CNTRL); 3665 tmp &= ~0x8; 3666 writel(tmp, fep->hwp + FEC_R_CNTRL); 3667 3668 if (ndev->flags & IFF_ALLMULTI) { 3669 /* Catch all multicast addresses, so set the 3670 * filter to all 1's 3671 */ 3672 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3673 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3674 3675 return; 3676 } 3677 3678 /* Add the addresses in hash register */ 3679 netdev_for_each_mc_addr(ha, ndev) { 3680 /* calculate crc32 value of mac address */ 3681 crc = ether_crc_le(ndev->addr_len, ha->addr); 3682 3683 /* only upper 6 bits (FEC_HASH_BITS) are used 3684 * which point to specific bit in the hash registers 3685 */ 3686 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3687 3688 if (hash > 31) 3689 hash_high |= 1 << (hash - 32); 3690 else 3691 hash_low |= 1 << hash; 3692 } 3693 3694 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3695 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3696 } 3697 3698 /* Set a MAC change in hardware. */ 3699 static int 3700 fec_set_mac_address(struct net_device *ndev, void *p) 3701 { 3702 struct fec_enet_private *fep = netdev_priv(ndev); 3703 struct sockaddr *addr = p; 3704 3705 if (addr) { 3706 if (!is_valid_ether_addr(addr->sa_data)) 3707 return -EADDRNOTAVAIL; 3708 eth_hw_addr_set(ndev, addr->sa_data); 3709 } 3710 3711 /* Add netif status check here to avoid system hang in below case: 3712 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3713 * After ethx down, fec all clocks are gated off and then register 3714 * access causes system hang. 3715 */ 3716 if (!netif_running(ndev)) 3717 return 0; 3718 3719 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3720 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3721 fep->hwp + FEC_ADDR_LOW); 3722 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3723 fep->hwp + FEC_ADDR_HIGH); 3724 return 0; 3725 } 3726 3727 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3728 netdev_features_t features) 3729 { 3730 struct fec_enet_private *fep = netdev_priv(netdev); 3731 netdev_features_t changed = features ^ netdev->features; 3732 3733 netdev->features = features; 3734 3735 /* Receive checksum has been changed */ 3736 if (changed & NETIF_F_RXCSUM) { 3737 if (features & NETIF_F_RXCSUM) 3738 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3739 else 3740 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3741 } 3742 } 3743 3744 static int fec_set_features(struct net_device *netdev, 3745 netdev_features_t features) 3746 { 3747 struct fec_enet_private *fep = netdev_priv(netdev); 3748 netdev_features_t changed = features ^ netdev->features; 3749 3750 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3751 napi_disable(&fep->napi); 3752 netif_tx_lock_bh(netdev); 3753 fec_stop(netdev); 3754 fec_enet_set_netdev_features(netdev, features); 3755 fec_restart(netdev); 3756 netif_tx_wake_all_queues(netdev); 3757 netif_tx_unlock_bh(netdev); 3758 napi_enable(&fep->napi); 3759 } else { 3760 fec_enet_set_netdev_features(netdev, features); 3761 } 3762 3763 return 0; 3764 } 3765 3766 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3767 struct net_device *sb_dev) 3768 { 3769 struct fec_enet_private *fep = netdev_priv(ndev); 3770 u16 vlan_tag = 0; 3771 3772 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3773 return netdev_pick_tx(ndev, skb, NULL); 3774 3775 /* VLAN is present in the payload.*/ 3776 if (eth_type_vlan(skb->protocol)) { 3777 struct vlan_ethhdr *vhdr = skb_vlan_eth_hdr(skb); 3778 3779 vlan_tag = ntohs(vhdr->h_vlan_TCI); 3780 /* VLAN is present in the skb but not yet pushed in the payload.*/ 3781 } else if (skb_vlan_tag_present(skb)) { 3782 vlan_tag = skb->vlan_tci; 3783 } else { 3784 return vlan_tag; 3785 } 3786 3787 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3788 } 3789 3790 static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf) 3791 { 3792 struct fec_enet_private *fep = netdev_priv(dev); 3793 bool is_run = netif_running(dev); 3794 struct bpf_prog *old_prog; 3795 3796 switch (bpf->command) { 3797 case XDP_SETUP_PROG: 3798 /* No need to support the SoCs that require to 3799 * do the frame swap because the performance wouldn't be 3800 * better than the skb mode. 3801 */ 3802 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 3803 return -EOPNOTSUPP; 3804 3805 if (!bpf->prog) 3806 xdp_features_clear_redirect_target(dev); 3807 3808 if (is_run) { 3809 napi_disable(&fep->napi); 3810 netif_tx_disable(dev); 3811 } 3812 3813 old_prog = xchg(&fep->xdp_prog, bpf->prog); 3814 if (old_prog) 3815 bpf_prog_put(old_prog); 3816 3817 fec_restart(dev); 3818 3819 if (is_run) { 3820 napi_enable(&fep->napi); 3821 netif_tx_start_all_queues(dev); 3822 } 3823 3824 if (bpf->prog) 3825 xdp_features_set_redirect_target(dev, false); 3826 3827 return 0; 3828 3829 case XDP_SETUP_XSK_POOL: 3830 return -EOPNOTSUPP; 3831 3832 default: 3833 return -EOPNOTSUPP; 3834 } 3835 } 3836 3837 static int 3838 fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index) 3839 { 3840 if (unlikely(index < 0)) 3841 return 0; 3842 3843 return (index % fep->num_tx_queues); 3844 } 3845 3846 static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep, 3847 struct fec_enet_priv_tx_q *txq, 3848 void *frame, u32 dma_sync_len, 3849 bool ndo_xmit) 3850 { 3851 unsigned int index, status, estatus; 3852 struct bufdesc *bdp; 3853 dma_addr_t dma_addr; 3854 int entries_free; 3855 u16 frame_len; 3856 3857 entries_free = fec_enet_get_free_txdesc_num(txq); 3858 if (entries_free < MAX_SKB_FRAGS + 1) { 3859 netdev_err_once(fep->netdev, "NOT enough BD for SG!\n"); 3860 return -EBUSY; 3861 } 3862 3863 /* Fill in a Tx ring entry */ 3864 bdp = txq->bd.cur; 3865 status = fec16_to_cpu(bdp->cbd_sc); 3866 status &= ~BD_ENET_TX_STATS; 3867 3868 index = fec_enet_get_bd_index(bdp, &txq->bd); 3869 3870 if (ndo_xmit) { 3871 struct xdp_frame *xdpf = frame; 3872 3873 dma_addr = dma_map_single(&fep->pdev->dev, xdpf->data, 3874 xdpf->len, DMA_TO_DEVICE); 3875 if (dma_mapping_error(&fep->pdev->dev, dma_addr)) 3876 return -ENOMEM; 3877 3878 frame_len = xdpf->len; 3879 txq->tx_buf[index].buf_p = xdpf; 3880 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_NDO; 3881 } else { 3882 struct xdp_buff *xdpb = frame; 3883 struct page *page; 3884 3885 page = virt_to_page(xdpb->data); 3886 dma_addr = page_pool_get_dma_addr(page) + 3887 (xdpb->data - xdpb->data_hard_start); 3888 dma_sync_single_for_device(&fep->pdev->dev, dma_addr, 3889 dma_sync_len, DMA_BIDIRECTIONAL); 3890 frame_len = xdpb->data_end - xdpb->data; 3891 txq->tx_buf[index].buf_p = page; 3892 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_TX; 3893 } 3894 3895 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 3896 if (fep->bufdesc_ex) 3897 estatus = BD_ENET_TX_INT; 3898 3899 bdp->cbd_bufaddr = cpu_to_fec32(dma_addr); 3900 bdp->cbd_datlen = cpu_to_fec16(frame_len); 3901 3902 if (fep->bufdesc_ex) { 3903 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3904 3905 if (fep->quirks & FEC_QUIRK_HAS_AVB) 3906 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 3907 3908 ebdp->cbd_bdu = 0; 3909 ebdp->cbd_esc = cpu_to_fec32(estatus); 3910 } 3911 3912 /* Make sure the updates to rest of the descriptor are performed before 3913 * transferring ownership. 3914 */ 3915 dma_wmb(); 3916 3917 /* Send it on its way. Tell FEC it's ready, interrupt when done, 3918 * it's the last BD of the frame, and to put the CRC on the end. 3919 */ 3920 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 3921 bdp->cbd_sc = cpu_to_fec16(status); 3922 3923 /* If this was the last BD in the ring, start at the beginning again. */ 3924 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3925 3926 /* Make sure the update to bdp are performed before txq->bd.cur. */ 3927 dma_wmb(); 3928 3929 txq->bd.cur = bdp; 3930 3931 /* Trigger transmission start */ 3932 writel(0, txq->bd.reg_desc_active); 3933 3934 return 0; 3935 } 3936 3937 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 3938 int cpu, struct xdp_buff *xdp, 3939 u32 dma_sync_len) 3940 { 3941 struct fec_enet_priv_tx_q *txq; 3942 struct netdev_queue *nq; 3943 int queue, ret; 3944 3945 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3946 txq = fep->tx_queue[queue]; 3947 nq = netdev_get_tx_queue(fep->netdev, queue); 3948 3949 __netif_tx_lock(nq, cpu); 3950 3951 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3952 txq_trans_cond_update(nq); 3953 ret = fec_enet_txq_xmit_frame(fep, txq, xdp, dma_sync_len, false); 3954 3955 __netif_tx_unlock(nq); 3956 3957 return ret; 3958 } 3959 3960 static int fec_enet_xdp_xmit(struct net_device *dev, 3961 int num_frames, 3962 struct xdp_frame **frames, 3963 u32 flags) 3964 { 3965 struct fec_enet_private *fep = netdev_priv(dev); 3966 struct fec_enet_priv_tx_q *txq; 3967 int cpu = smp_processor_id(); 3968 unsigned int sent_frames = 0; 3969 struct netdev_queue *nq; 3970 unsigned int queue; 3971 int i; 3972 3973 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3974 txq = fep->tx_queue[queue]; 3975 nq = netdev_get_tx_queue(fep->netdev, queue); 3976 3977 __netif_tx_lock(nq, cpu); 3978 3979 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3980 txq_trans_cond_update(nq); 3981 for (i = 0; i < num_frames; i++) { 3982 if (fec_enet_txq_xmit_frame(fep, txq, frames[i], 0, true) < 0) 3983 break; 3984 sent_frames++; 3985 } 3986 3987 __netif_tx_unlock(nq); 3988 3989 return sent_frames; 3990 } 3991 3992 static int fec_hwtstamp_get(struct net_device *ndev, 3993 struct kernel_hwtstamp_config *config) 3994 { 3995 struct fec_enet_private *fep = netdev_priv(ndev); 3996 3997 if (!netif_running(ndev)) 3998 return -EINVAL; 3999 4000 if (!fep->bufdesc_ex) 4001 return -EOPNOTSUPP; 4002 4003 fec_ptp_get(ndev, config); 4004 4005 return 0; 4006 } 4007 4008 static int fec_hwtstamp_set(struct net_device *ndev, 4009 struct kernel_hwtstamp_config *config, 4010 struct netlink_ext_ack *extack) 4011 { 4012 struct fec_enet_private *fep = netdev_priv(ndev); 4013 4014 if (!netif_running(ndev)) 4015 return -EINVAL; 4016 4017 if (!fep->bufdesc_ex) 4018 return -EOPNOTSUPP; 4019 4020 return fec_ptp_set(ndev, config, extack); 4021 } 4022 4023 static const struct net_device_ops fec_netdev_ops = { 4024 .ndo_open = fec_enet_open, 4025 .ndo_stop = fec_enet_close, 4026 .ndo_start_xmit = fec_enet_start_xmit, 4027 .ndo_select_queue = fec_enet_select_queue, 4028 .ndo_set_rx_mode = set_multicast_list, 4029 .ndo_validate_addr = eth_validate_addr, 4030 .ndo_tx_timeout = fec_timeout, 4031 .ndo_set_mac_address = fec_set_mac_address, 4032 .ndo_eth_ioctl = phy_do_ioctl_running, 4033 .ndo_set_features = fec_set_features, 4034 .ndo_bpf = fec_enet_bpf, 4035 .ndo_xdp_xmit = fec_enet_xdp_xmit, 4036 .ndo_hwtstamp_get = fec_hwtstamp_get, 4037 .ndo_hwtstamp_set = fec_hwtstamp_set, 4038 }; 4039 4040 static const unsigned short offset_des_active_rxq[] = { 4041 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 4042 }; 4043 4044 static const unsigned short offset_des_active_txq[] = { 4045 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 4046 }; 4047 4048 /* 4049 * XXX: We need to clean up on failure exits here. 4050 * 4051 */ 4052 static int fec_enet_init(struct net_device *ndev) 4053 { 4054 struct fec_enet_private *fep = netdev_priv(ndev); 4055 struct bufdesc *cbd_base; 4056 dma_addr_t bd_dma; 4057 int bd_size; 4058 unsigned int i; 4059 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 4060 sizeof(struct bufdesc); 4061 unsigned dsize_log2 = __fls(dsize); 4062 int ret; 4063 4064 WARN_ON(dsize != (1 << dsize_log2)); 4065 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 4066 fep->rx_align = 0xf; 4067 fep->tx_align = 0xf; 4068 #else 4069 fep->rx_align = 0x3; 4070 fep->tx_align = 0x3; 4071 #endif 4072 fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4073 fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4074 fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT; 4075 fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT; 4076 4077 /* Check mask of the streaming and coherent API */ 4078 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 4079 if (ret < 0) { 4080 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 4081 return ret; 4082 } 4083 4084 ret = fec_enet_alloc_queue(ndev); 4085 if (ret) 4086 return ret; 4087 4088 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 4089 4090 /* Allocate memory for buffer descriptors. */ 4091 cbd_base = fec_dmam_alloc(&fep->pdev->dev, bd_size, &bd_dma, 4092 GFP_KERNEL); 4093 if (!cbd_base) { 4094 ret = -ENOMEM; 4095 goto free_queue_mem; 4096 } 4097 4098 /* Get the Ethernet address */ 4099 ret = fec_get_mac(ndev); 4100 if (ret) 4101 goto free_queue_mem; 4102 4103 /* Set receive and transmit descriptor base. */ 4104 for (i = 0; i < fep->num_rx_queues; i++) { 4105 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 4106 unsigned size = dsize * rxq->bd.ring_size; 4107 4108 rxq->bd.qid = i; 4109 rxq->bd.base = cbd_base; 4110 rxq->bd.cur = cbd_base; 4111 rxq->bd.dma = bd_dma; 4112 rxq->bd.dsize = dsize; 4113 rxq->bd.dsize_log2 = dsize_log2; 4114 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 4115 bd_dma += size; 4116 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4117 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4118 } 4119 4120 for (i = 0; i < fep->num_tx_queues; i++) { 4121 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 4122 unsigned size = dsize * txq->bd.ring_size; 4123 4124 txq->bd.qid = i; 4125 txq->bd.base = cbd_base; 4126 txq->bd.cur = cbd_base; 4127 txq->bd.dma = bd_dma; 4128 txq->bd.dsize = dsize; 4129 txq->bd.dsize_log2 = dsize_log2; 4130 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 4131 bd_dma += size; 4132 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4133 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4134 } 4135 4136 4137 /* The FEC Ethernet specific entries in the device structure */ 4138 ndev->watchdog_timeo = TX_TIMEOUT; 4139 ndev->netdev_ops = &fec_netdev_ops; 4140 ndev->ethtool_ops = &fec_enet_ethtool_ops; 4141 4142 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 4143 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi); 4144 4145 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 4146 /* enable hw VLAN support */ 4147 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 4148 4149 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 4150 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS); 4151 4152 /* enable hw accelerator */ 4153 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 4154 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 4155 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 4156 } 4157 4158 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 4159 fep->tx_align = 0; 4160 fep->rx_align = 0x3f; 4161 } 4162 4163 ndev->hw_features = ndev->features; 4164 4165 if (!(fep->quirks & FEC_QUIRK_SWAP_FRAME)) 4166 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 4167 NETDEV_XDP_ACT_REDIRECT; 4168 4169 fec_restart(ndev); 4170 4171 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 4172 fec_enet_clear_ethtool_stats(ndev); 4173 else 4174 fec_enet_update_ethtool_stats(ndev); 4175 4176 return 0; 4177 4178 free_queue_mem: 4179 fec_enet_free_queue(ndev); 4180 return ret; 4181 } 4182 4183 static void fec_enet_deinit(struct net_device *ndev) 4184 { 4185 struct fec_enet_private *fep = netdev_priv(ndev); 4186 4187 netif_napi_del(&fep->napi); 4188 fec_enet_free_queue(ndev); 4189 } 4190 4191 #ifdef CONFIG_OF 4192 static int fec_reset_phy(struct platform_device *pdev) 4193 { 4194 struct gpio_desc *phy_reset; 4195 int msec = 1, phy_post_delay = 0; 4196 struct device_node *np = pdev->dev.of_node; 4197 int err; 4198 4199 if (!np) 4200 return 0; 4201 4202 err = of_property_read_u32(np, "phy-reset-duration", &msec); 4203 /* A sane reset duration should not be longer than 1s */ 4204 if (!err && msec > 1000) 4205 msec = 1; 4206 4207 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 4208 /* valid reset duration should be less than 1s */ 4209 if (!err && phy_post_delay > 1000) 4210 return -EINVAL; 4211 4212 phy_reset = devm_gpiod_get_optional(&pdev->dev, "phy-reset", 4213 GPIOD_OUT_HIGH); 4214 if (IS_ERR(phy_reset)) 4215 return dev_err_probe(&pdev->dev, PTR_ERR(phy_reset), 4216 "failed to get phy-reset-gpios\n"); 4217 4218 if (!phy_reset) 4219 return 0; 4220 4221 if (msec > 20) 4222 msleep(msec); 4223 else 4224 usleep_range(msec * 1000, msec * 1000 + 1000); 4225 4226 gpiod_set_value_cansleep(phy_reset, 0); 4227 4228 if (!phy_post_delay) 4229 return 0; 4230 4231 if (phy_post_delay > 20) 4232 msleep(phy_post_delay); 4233 else 4234 usleep_range(phy_post_delay * 1000, 4235 phy_post_delay * 1000 + 1000); 4236 4237 return 0; 4238 } 4239 #else /* CONFIG_OF */ 4240 static int fec_reset_phy(struct platform_device *pdev) 4241 { 4242 /* 4243 * In case of platform probe, the reset has been done 4244 * by machine code. 4245 */ 4246 return 0; 4247 } 4248 #endif /* CONFIG_OF */ 4249 4250 static void 4251 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 4252 { 4253 struct device_node *np = pdev->dev.of_node; 4254 4255 *num_tx = *num_rx = 1; 4256 4257 if (!np || !of_device_is_available(np)) 4258 return; 4259 4260 /* parse the num of tx and rx queues */ 4261 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 4262 4263 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 4264 4265 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 4266 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 4267 *num_tx); 4268 *num_tx = 1; 4269 return; 4270 } 4271 4272 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 4273 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 4274 *num_rx); 4275 *num_rx = 1; 4276 return; 4277 } 4278 4279 } 4280 4281 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 4282 { 4283 int irq_cnt = platform_irq_count(pdev); 4284 4285 if (irq_cnt > FEC_IRQ_NUM) 4286 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 4287 else if (irq_cnt == 2) 4288 irq_cnt = 1; /* last for pps */ 4289 else if (irq_cnt <= 0) 4290 irq_cnt = 1; /* At least 1 irq is needed */ 4291 return irq_cnt; 4292 } 4293 4294 static void fec_enet_get_wakeup_irq(struct platform_device *pdev) 4295 { 4296 struct net_device *ndev = platform_get_drvdata(pdev); 4297 struct fec_enet_private *fep = netdev_priv(ndev); 4298 4299 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) 4300 fep->wake_irq = fep->irq[2]; 4301 else 4302 fep->wake_irq = fep->irq[0]; 4303 } 4304 4305 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 4306 struct device_node *np) 4307 { 4308 struct device_node *gpr_np; 4309 u32 out_val[3]; 4310 int ret = 0; 4311 4312 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 4313 if (!gpr_np) 4314 return 0; 4315 4316 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 4317 ARRAY_SIZE(out_val)); 4318 if (ret) { 4319 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 4320 goto out; 4321 } 4322 4323 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 4324 if (IS_ERR(fep->stop_gpr.gpr)) { 4325 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 4326 ret = PTR_ERR(fep->stop_gpr.gpr); 4327 fep->stop_gpr.gpr = NULL; 4328 goto out; 4329 } 4330 4331 fep->stop_gpr.reg = out_val[1]; 4332 fep->stop_gpr.bit = out_val[2]; 4333 4334 out: 4335 of_node_put(gpr_np); 4336 4337 return ret; 4338 } 4339 4340 static int 4341 fec_probe(struct platform_device *pdev) 4342 { 4343 struct fec_enet_private *fep; 4344 struct fec_platform_data *pdata; 4345 phy_interface_t interface; 4346 struct net_device *ndev; 4347 int i, irq, ret = 0; 4348 static int dev_id; 4349 struct device_node *np = pdev->dev.of_node, *phy_node; 4350 int num_tx_qs; 4351 int num_rx_qs; 4352 char irq_name[8]; 4353 int irq_cnt; 4354 const struct fec_devinfo *dev_info; 4355 4356 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 4357 4358 /* Init network device */ 4359 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 4360 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 4361 if (!ndev) 4362 return -ENOMEM; 4363 4364 SET_NETDEV_DEV(ndev, &pdev->dev); 4365 4366 /* setup board info structure */ 4367 fep = netdev_priv(ndev); 4368 4369 dev_info = device_get_match_data(&pdev->dev); 4370 if (!dev_info) 4371 dev_info = (const struct fec_devinfo *)pdev->id_entry->driver_data; 4372 if (dev_info) 4373 fep->quirks = dev_info->quirks; 4374 4375 fep->netdev = ndev; 4376 fep->num_rx_queues = num_rx_qs; 4377 fep->num_tx_queues = num_tx_qs; 4378 4379 #if !defined(CONFIG_M5272) 4380 /* default enable pause frame auto negotiation */ 4381 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 4382 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 4383 #endif 4384 4385 /* Select default pin state */ 4386 pinctrl_pm_select_default_state(&pdev->dev); 4387 4388 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 4389 if (IS_ERR(fep->hwp)) { 4390 ret = PTR_ERR(fep->hwp); 4391 goto failed_ioremap; 4392 } 4393 4394 fep->pdev = pdev; 4395 fep->dev_id = dev_id++; 4396 4397 platform_set_drvdata(pdev, ndev); 4398 4399 if ((of_machine_is_compatible("fsl,imx6q") || 4400 of_machine_is_compatible("fsl,imx6dl")) && 4401 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 4402 fep->quirks |= FEC_QUIRK_ERR006687; 4403 4404 ret = fec_enet_ipc_handle_init(fep); 4405 if (ret) 4406 goto failed_ipc_init; 4407 4408 if (of_property_read_bool(np, "fsl,magic-packet")) 4409 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 4410 4411 ret = fec_enet_init_stop_mode(fep, np); 4412 if (ret) 4413 goto failed_stop_mode; 4414 4415 phy_node = of_parse_phandle(np, "phy-handle", 0); 4416 if (!phy_node && of_phy_is_fixed_link(np)) { 4417 ret = of_phy_register_fixed_link(np); 4418 if (ret < 0) { 4419 dev_err(&pdev->dev, 4420 "broken fixed-link specification\n"); 4421 goto failed_phy; 4422 } 4423 phy_node = of_node_get(np); 4424 } 4425 fep->phy_node = phy_node; 4426 4427 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 4428 if (ret) { 4429 pdata = dev_get_platdata(&pdev->dev); 4430 if (pdata) 4431 fep->phy_interface = pdata->phy; 4432 else 4433 fep->phy_interface = PHY_INTERFACE_MODE_MII; 4434 } else { 4435 fep->phy_interface = interface; 4436 } 4437 4438 ret = fec_enet_parse_rgmii_delay(fep, np); 4439 if (ret) 4440 goto failed_rgmii_delay; 4441 4442 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 4443 if (IS_ERR(fep->clk_ipg)) { 4444 ret = PTR_ERR(fep->clk_ipg); 4445 goto failed_clk; 4446 } 4447 4448 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 4449 if (IS_ERR(fep->clk_ahb)) { 4450 ret = PTR_ERR(fep->clk_ahb); 4451 goto failed_clk; 4452 } 4453 4454 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 4455 4456 /* enet_out is optional, depends on board */ 4457 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out"); 4458 if (IS_ERR(fep->clk_enet_out)) { 4459 ret = PTR_ERR(fep->clk_enet_out); 4460 goto failed_clk; 4461 } 4462 4463 fep->ptp_clk_on = false; 4464 mutex_init(&fep->ptp_clk_mutex); 4465 4466 /* clk_ref is optional, depends on board */ 4467 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref"); 4468 if (IS_ERR(fep->clk_ref)) { 4469 ret = PTR_ERR(fep->clk_ref); 4470 goto failed_clk; 4471 } 4472 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); 4473 4474 /* clk_2x_txclk is optional, depends on board */ 4475 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { 4476 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); 4477 if (IS_ERR(fep->clk_2x_txclk)) 4478 fep->clk_2x_txclk = NULL; 4479 } 4480 4481 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 4482 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 4483 if (IS_ERR(fep->clk_ptp)) { 4484 fep->clk_ptp = NULL; 4485 fep->bufdesc_ex = false; 4486 } 4487 4488 ret = fec_enet_clk_enable(ndev, true); 4489 if (ret) 4490 goto failed_clk; 4491 4492 ret = clk_prepare_enable(fep->clk_ipg); 4493 if (ret) 4494 goto failed_clk_ipg; 4495 ret = clk_prepare_enable(fep->clk_ahb); 4496 if (ret) 4497 goto failed_clk_ahb; 4498 4499 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 4500 if (!IS_ERR(fep->reg_phy)) { 4501 ret = regulator_enable(fep->reg_phy); 4502 if (ret) { 4503 dev_err(&pdev->dev, 4504 "Failed to enable phy regulator: %d\n", ret); 4505 goto failed_regulator; 4506 } 4507 } else { 4508 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 4509 ret = -EPROBE_DEFER; 4510 goto failed_regulator; 4511 } 4512 fep->reg_phy = NULL; 4513 } 4514 4515 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 4516 pm_runtime_use_autosuspend(&pdev->dev); 4517 pm_runtime_get_noresume(&pdev->dev); 4518 pm_runtime_set_active(&pdev->dev); 4519 pm_runtime_enable(&pdev->dev); 4520 4521 ret = fec_reset_phy(pdev); 4522 if (ret) 4523 goto failed_reset; 4524 4525 irq_cnt = fec_enet_get_irq_cnt(pdev); 4526 if (fep->bufdesc_ex) 4527 fec_ptp_init(pdev, irq_cnt); 4528 4529 ret = fec_enet_init(ndev); 4530 if (ret) 4531 goto failed_init; 4532 4533 for (i = 0; i < irq_cnt; i++) { 4534 snprintf(irq_name, sizeof(irq_name), "int%d", i); 4535 irq = platform_get_irq_byname_optional(pdev, irq_name); 4536 if (irq < 0) 4537 irq = platform_get_irq(pdev, i); 4538 if (irq < 0) { 4539 ret = irq; 4540 goto failed_irq; 4541 } 4542 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 4543 0, pdev->name, ndev); 4544 if (ret) 4545 goto failed_irq; 4546 4547 fep->irq[i] = irq; 4548 } 4549 4550 /* Decide which interrupt line is wakeup capable */ 4551 fec_enet_get_wakeup_irq(pdev); 4552 4553 ret = fec_enet_mii_init(pdev); 4554 if (ret) 4555 goto failed_mii_init; 4556 4557 /* Carrier starts down, phylib will bring it up */ 4558 netif_carrier_off(ndev); 4559 fec_enet_clk_enable(ndev, false); 4560 pinctrl_pm_select_sleep_state(&pdev->dev); 4561 4562 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN; 4563 4564 ret = register_netdev(ndev); 4565 if (ret) 4566 goto failed_register; 4567 4568 device_init_wakeup(&ndev->dev, fep->wol_flag & 4569 FEC_WOL_HAS_MAGIC_PACKET); 4570 4571 if (fep->bufdesc_ex && fep->ptp_clock) 4572 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 4573 4574 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 4575 4576 pm_runtime_mark_last_busy(&pdev->dev); 4577 pm_runtime_put_autosuspend(&pdev->dev); 4578 4579 return 0; 4580 4581 failed_register: 4582 fec_enet_mii_remove(fep); 4583 failed_mii_init: 4584 failed_irq: 4585 fec_enet_deinit(ndev); 4586 failed_init: 4587 fec_ptp_stop(pdev); 4588 failed_reset: 4589 pm_runtime_put_noidle(&pdev->dev); 4590 pm_runtime_disable(&pdev->dev); 4591 if (fep->reg_phy) 4592 regulator_disable(fep->reg_phy); 4593 failed_regulator: 4594 clk_disable_unprepare(fep->clk_ahb); 4595 failed_clk_ahb: 4596 clk_disable_unprepare(fep->clk_ipg); 4597 failed_clk_ipg: 4598 fec_enet_clk_enable(ndev, false); 4599 failed_clk: 4600 failed_rgmii_delay: 4601 if (of_phy_is_fixed_link(np)) 4602 of_phy_deregister_fixed_link(np); 4603 of_node_put(phy_node); 4604 failed_stop_mode: 4605 failed_ipc_init: 4606 failed_phy: 4607 dev_id--; 4608 failed_ioremap: 4609 free_netdev(ndev); 4610 4611 return ret; 4612 } 4613 4614 static void 4615 fec_drv_remove(struct platform_device *pdev) 4616 { 4617 struct net_device *ndev = platform_get_drvdata(pdev); 4618 struct fec_enet_private *fep = netdev_priv(ndev); 4619 struct device_node *np = pdev->dev.of_node; 4620 int ret; 4621 4622 ret = pm_runtime_get_sync(&pdev->dev); 4623 if (ret < 0) 4624 dev_err(&pdev->dev, 4625 "Failed to resume device in remove callback (%pe)\n", 4626 ERR_PTR(ret)); 4627 4628 cancel_work_sync(&fep->tx_timeout_work); 4629 fec_ptp_stop(pdev); 4630 unregister_netdev(ndev); 4631 fec_enet_mii_remove(fep); 4632 if (fep->reg_phy) 4633 regulator_disable(fep->reg_phy); 4634 4635 if (of_phy_is_fixed_link(np)) 4636 of_phy_deregister_fixed_link(np); 4637 of_node_put(fep->phy_node); 4638 4639 /* After pm_runtime_get_sync() failed, the clks are still off, so skip 4640 * disabling them again. 4641 */ 4642 if (ret >= 0) { 4643 clk_disable_unprepare(fep->clk_ahb); 4644 clk_disable_unprepare(fep->clk_ipg); 4645 } 4646 pm_runtime_put_noidle(&pdev->dev); 4647 pm_runtime_disable(&pdev->dev); 4648 4649 fec_enet_deinit(ndev); 4650 free_netdev(ndev); 4651 } 4652 4653 static int fec_suspend(struct device *dev) 4654 { 4655 struct net_device *ndev = dev_get_drvdata(dev); 4656 struct fec_enet_private *fep = netdev_priv(ndev); 4657 int ret; 4658 4659 rtnl_lock(); 4660 if (netif_running(ndev)) { 4661 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 4662 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 4663 phy_stop(ndev->phydev); 4664 napi_disable(&fep->napi); 4665 netif_tx_lock_bh(ndev); 4666 netif_device_detach(ndev); 4667 netif_tx_unlock_bh(ndev); 4668 fec_stop(ndev); 4669 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4670 fec_irqs_disable(ndev); 4671 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 4672 } else { 4673 fec_irqs_disable_except_wakeup(ndev); 4674 if (fep->wake_irq > 0) { 4675 disable_irq(fep->wake_irq); 4676 enable_irq_wake(fep->wake_irq); 4677 } 4678 fec_enet_stop_mode(fep, true); 4679 } 4680 /* It's safe to disable clocks since interrupts are masked */ 4681 fec_enet_clk_enable(ndev, false); 4682 4683 fep->rpm_active = !pm_runtime_status_suspended(dev); 4684 if (fep->rpm_active) { 4685 ret = pm_runtime_force_suspend(dev); 4686 if (ret < 0) { 4687 rtnl_unlock(); 4688 return ret; 4689 } 4690 } 4691 } 4692 rtnl_unlock(); 4693 4694 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4695 regulator_disable(fep->reg_phy); 4696 4697 /* SOC supply clock to phy, when clock is disabled, phy link down 4698 * SOC control phy regulator, when regulator is disabled, phy link down 4699 */ 4700 if (fep->clk_enet_out || fep->reg_phy) 4701 fep->link = 0; 4702 4703 return 0; 4704 } 4705 4706 static int fec_resume(struct device *dev) 4707 { 4708 struct net_device *ndev = dev_get_drvdata(dev); 4709 struct fec_enet_private *fep = netdev_priv(ndev); 4710 int ret; 4711 int val; 4712 4713 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4714 ret = regulator_enable(fep->reg_phy); 4715 if (ret) 4716 return ret; 4717 } 4718 4719 rtnl_lock(); 4720 if (netif_running(ndev)) { 4721 if (fep->rpm_active) 4722 pm_runtime_force_resume(dev); 4723 4724 ret = fec_enet_clk_enable(ndev, true); 4725 if (ret) { 4726 rtnl_unlock(); 4727 goto failed_clk; 4728 } 4729 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 4730 fec_enet_stop_mode(fep, false); 4731 if (fep->wake_irq) { 4732 disable_irq_wake(fep->wake_irq); 4733 enable_irq(fep->wake_irq); 4734 } 4735 4736 val = readl(fep->hwp + FEC_ECNTRL); 4737 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 4738 writel(val, fep->hwp + FEC_ECNTRL); 4739 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 4740 } else { 4741 pinctrl_pm_select_default_state(&fep->pdev->dev); 4742 } 4743 fec_restart(ndev); 4744 netif_tx_lock_bh(ndev); 4745 netif_device_attach(ndev); 4746 netif_tx_unlock_bh(ndev); 4747 napi_enable(&fep->napi); 4748 phy_init_hw(ndev->phydev); 4749 phy_start(ndev->phydev); 4750 } 4751 rtnl_unlock(); 4752 4753 return 0; 4754 4755 failed_clk: 4756 if (fep->reg_phy) 4757 regulator_disable(fep->reg_phy); 4758 return ret; 4759 } 4760 4761 static int fec_runtime_suspend(struct device *dev) 4762 { 4763 struct net_device *ndev = dev_get_drvdata(dev); 4764 struct fec_enet_private *fep = netdev_priv(ndev); 4765 4766 clk_disable_unprepare(fep->clk_ahb); 4767 clk_disable_unprepare(fep->clk_ipg); 4768 4769 return 0; 4770 } 4771 4772 static int fec_runtime_resume(struct device *dev) 4773 { 4774 struct net_device *ndev = dev_get_drvdata(dev); 4775 struct fec_enet_private *fep = netdev_priv(ndev); 4776 int ret; 4777 4778 ret = clk_prepare_enable(fep->clk_ahb); 4779 if (ret) 4780 return ret; 4781 ret = clk_prepare_enable(fep->clk_ipg); 4782 if (ret) 4783 goto failed_clk_ipg; 4784 4785 return 0; 4786 4787 failed_clk_ipg: 4788 clk_disable_unprepare(fep->clk_ahb); 4789 return ret; 4790 } 4791 4792 static const struct dev_pm_ops fec_pm_ops = { 4793 SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 4794 RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 4795 }; 4796 4797 static struct platform_driver fec_driver = { 4798 .driver = { 4799 .name = DRIVER_NAME, 4800 .pm = pm_ptr(&fec_pm_ops), 4801 .of_match_table = fec_dt_ids, 4802 .suppress_bind_attrs = true, 4803 }, 4804 .id_table = fec_devtype, 4805 .probe = fec_probe, 4806 .remove = fec_drv_remove, 4807 }; 4808 4809 module_platform_driver(fec_driver); 4810 4811 MODULE_DESCRIPTION("NXP Fast Ethernet Controller (FEC) driver"); 4812 MODULE_LICENSE("GPL"); 4813