1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/bitops.h> 26 #include <linux/bpf.h> 27 #include <linux/bpf_trace.h> 28 #include <linux/cacheflush.h> 29 #include <linux/clk.h> 30 #include <linux/crc32.h> 31 #include <linux/delay.h> 32 #include <linux/errno.h> 33 #include <linux/etherdevice.h> 34 #include <linux/fec.h> 35 #include <linux/filter.h> 36 #include <linux/gpio/consumer.h> 37 #include <linux/icmp.h> 38 #include <linux/if_vlan.h> 39 #include <linux/in.h> 40 #include <linux/interrupt.h> 41 #include <linux/io.h> 42 #include <linux/ioport.h> 43 #include <linux/ip.h> 44 #include <linux/irq.h> 45 #include <linux/kernel.h> 46 #include <linux/mdio.h> 47 #include <linux/mfd/syscon.h> 48 #include <linux/module.h> 49 #include <linux/netdevice.h> 50 #include <linux/of.h> 51 #include <linux/of_mdio.h> 52 #include <linux/of_net.h> 53 #include <linux/phy.h> 54 #include <linux/pinctrl/consumer.h> 55 #include <linux/phy_fixed.h> 56 #include <linux/platform_device.h> 57 #include <linux/pm_runtime.h> 58 #include <linux/prefetch.h> 59 #include <linux/property.h> 60 #include <linux/ptrace.h> 61 #include <linux/regmap.h> 62 #include <linux/regulator/consumer.h> 63 #include <linux/skbuff.h> 64 #include <linux/slab.h> 65 #include <linux/spinlock.h> 66 #include <linux/string.h> 67 #include <linux/tcp.h> 68 #include <linux/udp.h> 69 #include <linux/workqueue.h> 70 #include <net/ip.h> 71 #include <net/page_pool/helpers.h> 72 #include <net/selftests.h> 73 #include <net/tso.h> 74 #include <soc/imx/cpuidle.h> 75 76 #include "fec.h" 77 78 static void set_multicast_list(struct net_device *ndev); 79 static void fec_enet_itr_coal_set(struct net_device *ndev); 80 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 81 int cpu, struct xdp_buff *xdp, 82 u32 dma_sync_len); 83 84 #define DRIVER_NAME "fec" 85 86 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 87 88 #define FEC_ENET_RSEM_V 0x84 89 #define FEC_ENET_RSFL_V 16 90 #define FEC_ENET_RAEM_V 0x8 91 #define FEC_ENET_RAFL_V 0x8 92 #define FEC_ENET_OPD_V 0xFFF0 93 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 94 95 #define FEC_ENET_XDP_PASS 0 96 #define FEC_ENET_XDP_CONSUMED BIT(0) 97 #define FEC_ENET_XDP_TX BIT(1) 98 #define FEC_ENET_XDP_REDIR BIT(2) 99 100 struct fec_devinfo { 101 u32 quirks; 102 }; 103 104 static const struct fec_devinfo fec_imx25_info = { 105 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 106 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_HAS_MDIO_C45, 107 }; 108 109 static const struct fec_devinfo fec_imx27_info = { 110 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG | 111 FEC_QUIRK_HAS_MDIO_C45, 112 }; 113 114 static const struct fec_devinfo fec_imx28_info = { 115 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 116 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 117 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 118 FEC_QUIRK_NO_HARD_RESET | FEC_QUIRK_HAS_MDIO_C45, 119 }; 120 121 static const struct fec_devinfo fec_imx6q_info = { 122 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 125 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII | 126 FEC_QUIRK_HAS_PMQOS | FEC_QUIRK_HAS_MDIO_C45, 127 }; 128 129 static const struct fec_devinfo fec_mvf600_info = { 130 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC | 131 FEC_QUIRK_HAS_MDIO_C45, 132 }; 133 134 static const struct fec_devinfo fec_imx6sx_info = { 135 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 136 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 137 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 138 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 139 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 140 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 141 FEC_QUIRK_HAS_MDIO_C45, 142 }; 143 144 static const struct fec_devinfo fec_imx6ul_info = { 145 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 146 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 147 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 148 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 149 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII | 150 FEC_QUIRK_HAS_MDIO_C45, 151 }; 152 153 static const struct fec_devinfo fec_imx8mq_info = { 154 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 155 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 156 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 157 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 158 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 159 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 160 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2 | 161 FEC_QUIRK_HAS_MDIO_C45, 162 }; 163 164 static const struct fec_devinfo fec_imx8qm_info = { 165 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 166 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 167 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 168 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 169 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 170 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 171 FEC_QUIRK_DELAYED_CLKS_SUPPORT | FEC_QUIRK_HAS_MDIO_C45 | 172 FEC_QUIRK_JUMBO_FRAME, 173 }; 174 175 static const struct fec_devinfo fec_s32v234_info = { 176 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 177 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 178 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 179 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 180 FEC_QUIRK_HAS_MDIO_C45, 181 }; 182 183 static struct platform_device_id fec_devtype[] = { 184 { 185 /* keep it for coldfire */ 186 .name = DRIVER_NAME, 187 .driver_data = 0, 188 }, { 189 /* sentinel */ 190 } 191 }; 192 MODULE_DEVICE_TABLE(platform, fec_devtype); 193 194 static const struct of_device_id fec_dt_ids[] = { 195 { .compatible = "fsl,imx25-fec", .data = &fec_imx25_info, }, 196 { .compatible = "fsl,imx27-fec", .data = &fec_imx27_info, }, 197 { .compatible = "fsl,imx28-fec", .data = &fec_imx28_info, }, 198 { .compatible = "fsl,imx6q-fec", .data = &fec_imx6q_info, }, 199 { .compatible = "fsl,mvf600-fec", .data = &fec_mvf600_info, }, 200 { .compatible = "fsl,imx6sx-fec", .data = &fec_imx6sx_info, }, 201 { .compatible = "fsl,imx6ul-fec", .data = &fec_imx6ul_info, }, 202 { .compatible = "fsl,imx8mq-fec", .data = &fec_imx8mq_info, }, 203 { .compatible = "fsl,imx8qm-fec", .data = &fec_imx8qm_info, }, 204 { .compatible = "fsl,s32v234-fec", .data = &fec_s32v234_info, }, 205 { /* sentinel */ } 206 }; 207 MODULE_DEVICE_TABLE(of, fec_dt_ids); 208 209 static unsigned char macaddr[ETH_ALEN]; 210 module_param_array(macaddr, byte, NULL, 0); 211 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 212 213 #if defined(CONFIG_M5272) 214 /* 215 * Some hardware gets it MAC address out of local flash memory. 216 * if this is non-zero then assume it is the address to get MAC from. 217 */ 218 #if defined(CONFIG_NETtel) 219 #define FEC_FLASHMAC 0xf0006006 220 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 221 #define FEC_FLASHMAC 0xf0006000 222 #elif defined(CONFIG_CANCam) 223 #define FEC_FLASHMAC 0xf0020000 224 #elif defined (CONFIG_M5272C3) 225 #define FEC_FLASHMAC (0xffe04000 + 4) 226 #elif defined(CONFIG_MOD5272) 227 #define FEC_FLASHMAC 0xffc0406b 228 #else 229 #define FEC_FLASHMAC 0 230 #endif 231 #endif /* CONFIG_M5272 */ 232 233 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 234 * 235 * 2048 byte skbufs are allocated. However, alignment requirements 236 * varies between FEC variants. Worst case is 64, so round down by 64. 237 */ 238 #define MAX_JUMBO_BUF_SIZE (round_down(16384 - FEC_DRV_RESERVE_SPACE - 64, 64)) 239 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 240 #define PKT_MINBUF_SIZE 64 241 242 /* FEC receive acceleration */ 243 #define FEC_RACC_IPDIS BIT(1) 244 #define FEC_RACC_PRODIS BIT(2) 245 #define FEC_RACC_SHIFT16 BIT(7) 246 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 247 248 /* MIB Control Register */ 249 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 250 251 /* 252 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 253 * size bits. Other FEC hardware does not, so we need to take that into 254 * account when setting it. 255 */ 256 #ifndef CONFIG_M5272 257 #define OPT_ARCH_HAS_MAX_FL 1 258 #else 259 #define OPT_ARCH_HAS_MAX_FL 0 260 #endif 261 262 /* FEC MII MMFR bits definition */ 263 #define FEC_MMFR_ST (1 << 30) 264 #define FEC_MMFR_ST_C45 (0) 265 #define FEC_MMFR_OP_READ (2 << 28) 266 #define FEC_MMFR_OP_READ_C45 (3 << 28) 267 #define FEC_MMFR_OP_WRITE (1 << 28) 268 #define FEC_MMFR_OP_ADDR_WRITE (0) 269 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 270 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 271 #define FEC_MMFR_TA (2 << 16) 272 #define FEC_MMFR_DATA(v) (v & 0xffff) 273 /* FEC ECR bits definition */ 274 #define FEC_ECR_RESET BIT(0) 275 #define FEC_ECR_ETHEREN BIT(1) 276 #define FEC_ECR_MAGICEN BIT(2) 277 #define FEC_ECR_SLEEP BIT(3) 278 #define FEC_ECR_EN1588 BIT(4) 279 #define FEC_ECR_SPEED BIT(5) 280 #define FEC_ECR_BYTESWP BIT(8) 281 /* FEC RCR bits definition */ 282 #define FEC_RCR_LOOP BIT(0) 283 #define FEC_RCR_DRT BIT(1) 284 #define FEC_RCR_MII BIT(2) 285 #define FEC_RCR_PROMISC BIT(3) 286 #define FEC_RCR_BC_REJ BIT(4) 287 #define FEC_RCR_FLOWCTL BIT(5) 288 #define FEC_RCR_RGMII BIT(6) 289 #define FEC_RCR_RMII BIT(8) 290 #define FEC_RCR_10BASET BIT(9) 291 #define FEC_RCR_NLC BIT(30) 292 /* TX WMARK bits */ 293 #define FEC_TXWMRK_STRFWD BIT(8) 294 295 #define FEC_MII_TIMEOUT 30000 /* us */ 296 297 /* Transmitter timeout */ 298 #define TX_TIMEOUT (2 * HZ) 299 300 #define FEC_PAUSE_FLAG_AUTONEG 0x1 301 #define FEC_PAUSE_FLAG_ENABLE 0x2 302 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 303 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 304 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 305 306 /* Max number of allowed TCP segments for software TSO */ 307 #define FEC_MAX_TSO_SEGS 100 308 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 309 310 #define IS_TSO_HEADER(txq, addr) \ 311 ((addr >= txq->tso_hdrs_dma) && \ 312 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 313 314 static int mii_cnt; 315 316 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 317 struct bufdesc_prop *bd) 318 { 319 return (bdp >= bd->last) ? bd->base 320 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 321 } 322 323 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 324 struct bufdesc_prop *bd) 325 { 326 return (bdp <= bd->base) ? bd->last 327 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 328 } 329 330 static int fec_enet_get_bd_index(struct bufdesc *bdp, 331 struct bufdesc_prop *bd) 332 { 333 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 334 } 335 336 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 337 { 338 int entries; 339 340 entries = (((const char *)txq->dirty_tx - 341 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 342 343 return entries >= 0 ? entries : entries + txq->bd.ring_size; 344 } 345 346 static void swap_buffer(void *bufaddr, int len) 347 { 348 int i; 349 unsigned int *buf = bufaddr; 350 351 for (i = 0; i < len; i += 4, buf++) 352 swab32s(buf); 353 } 354 355 static void fec_dump(struct net_device *ndev) 356 { 357 struct fec_enet_private *fep = netdev_priv(ndev); 358 struct bufdesc *bdp; 359 struct fec_enet_priv_tx_q *txq; 360 int index = 0; 361 362 netdev_info(ndev, "TX ring dump\n"); 363 pr_info("Nr SC addr len SKB\n"); 364 365 txq = fep->tx_queue[0]; 366 bdp = txq->bd.base; 367 368 do { 369 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 370 index, 371 bdp == txq->bd.cur ? 'S' : ' ', 372 bdp == txq->dirty_tx ? 'H' : ' ', 373 fec16_to_cpu(bdp->cbd_sc), 374 fec32_to_cpu(bdp->cbd_bufaddr), 375 fec16_to_cpu(bdp->cbd_datlen), 376 txq->tx_buf[index].buf_p); 377 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 378 index++; 379 } while (bdp != txq->bd.base); 380 } 381 382 /* 383 * Coldfire does not support DMA coherent allocations, and has historically used 384 * a band-aid with a manual flush in fec_enet_rx_queue. 385 */ 386 #if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA) 387 static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, 388 gfp_t gfp) 389 { 390 return dma_alloc_noncoherent(dev, size, handle, DMA_BIDIRECTIONAL, gfp); 391 } 392 393 static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr, 394 dma_addr_t handle) 395 { 396 dma_free_noncoherent(dev, size, cpu_addr, handle, DMA_BIDIRECTIONAL); 397 } 398 #else /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */ 399 static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, 400 gfp_t gfp) 401 { 402 return dma_alloc_coherent(dev, size, handle, gfp); 403 } 404 405 static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr, 406 dma_addr_t handle) 407 { 408 dma_free_coherent(dev, size, cpu_addr, handle); 409 } 410 #endif /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */ 411 412 struct fec_dma_devres { 413 size_t size; 414 void *vaddr; 415 dma_addr_t dma_handle; 416 }; 417 418 static void fec_dmam_release(struct device *dev, void *res) 419 { 420 struct fec_dma_devres *this = res; 421 422 fec_dma_free(dev, this->size, this->vaddr, this->dma_handle); 423 } 424 425 static void *fec_dmam_alloc(struct device *dev, size_t size, dma_addr_t *handle, 426 gfp_t gfp) 427 { 428 struct fec_dma_devres *dr; 429 void *vaddr; 430 431 dr = devres_alloc(fec_dmam_release, sizeof(*dr), gfp); 432 if (!dr) 433 return NULL; 434 vaddr = fec_dma_alloc(dev, size, handle, gfp); 435 if (!vaddr) { 436 devres_free(dr); 437 return NULL; 438 } 439 dr->vaddr = vaddr; 440 dr->dma_handle = *handle; 441 dr->size = size; 442 devres_add(dev, dr); 443 return vaddr; 444 } 445 446 static inline bool is_ipv4_pkt(struct sk_buff *skb) 447 { 448 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 449 } 450 451 static int 452 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 453 { 454 /* Only run for packets requiring a checksum. */ 455 if (skb->ip_summed != CHECKSUM_PARTIAL) 456 return 0; 457 458 if (unlikely(skb_cow_head(skb, 0))) 459 return -1; 460 461 if (is_ipv4_pkt(skb)) 462 ip_hdr(skb)->check = 0; 463 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 464 465 return 0; 466 } 467 468 static int 469 fec_enet_create_page_pool(struct fec_enet_private *fep, 470 struct fec_enet_priv_rx_q *rxq, int size) 471 { 472 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 473 struct page_pool_params pp_params = { 474 .order = fep->pagepool_order, 475 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 476 .pool_size = size, 477 .nid = dev_to_node(&fep->pdev->dev), 478 .dev = &fep->pdev->dev, 479 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 480 .offset = FEC_ENET_XDP_HEADROOM, 481 .max_len = fep->rx_frame_size, 482 }; 483 int err; 484 485 rxq->page_pool = page_pool_create(&pp_params); 486 if (IS_ERR(rxq->page_pool)) { 487 err = PTR_ERR(rxq->page_pool); 488 rxq->page_pool = NULL; 489 return err; 490 } 491 492 err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0); 493 if (err < 0) 494 goto err_free_pp; 495 496 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 497 rxq->page_pool); 498 if (err) 499 goto err_unregister_rxq; 500 501 return 0; 502 503 err_unregister_rxq: 504 xdp_rxq_info_unreg(&rxq->xdp_rxq); 505 err_free_pp: 506 page_pool_destroy(rxq->page_pool); 507 rxq->page_pool = NULL; 508 return err; 509 } 510 511 static struct bufdesc * 512 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 513 struct sk_buff *skb, 514 struct net_device *ndev) 515 { 516 struct fec_enet_private *fep = netdev_priv(ndev); 517 struct bufdesc *bdp = txq->bd.cur; 518 struct bufdesc_ex *ebdp; 519 int nr_frags = skb_shinfo(skb)->nr_frags; 520 int frag, frag_len; 521 unsigned short status; 522 unsigned int estatus = 0; 523 skb_frag_t *this_frag; 524 unsigned int index; 525 void *bufaddr; 526 dma_addr_t addr; 527 int i; 528 529 for (frag = 0; frag < nr_frags; frag++) { 530 this_frag = &skb_shinfo(skb)->frags[frag]; 531 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 532 ebdp = (struct bufdesc_ex *)bdp; 533 534 status = fec16_to_cpu(bdp->cbd_sc); 535 status &= ~BD_ENET_TX_STATS; 536 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 537 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 538 539 /* Handle the last BD specially */ 540 if (frag == nr_frags - 1) { 541 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 542 if (fep->bufdesc_ex) { 543 estatus |= BD_ENET_TX_INT; 544 if (unlikely(skb_shinfo(skb)->tx_flags & 545 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 546 estatus |= BD_ENET_TX_TS; 547 } 548 } 549 550 if (fep->bufdesc_ex) { 551 if (fep->quirks & FEC_QUIRK_HAS_AVB) 552 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 553 if (skb->ip_summed == CHECKSUM_PARTIAL) 554 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 555 556 ebdp->cbd_bdu = 0; 557 ebdp->cbd_esc = cpu_to_fec32(estatus); 558 } 559 560 bufaddr = skb_frag_address(this_frag); 561 562 index = fec_enet_get_bd_index(bdp, &txq->bd); 563 if (((unsigned long) bufaddr) & fep->tx_align || 564 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 565 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 566 bufaddr = txq->tx_bounce[index]; 567 568 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 569 swap_buffer(bufaddr, frag_len); 570 } 571 572 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 573 DMA_TO_DEVICE); 574 if (dma_mapping_error(&fep->pdev->dev, addr)) { 575 if (net_ratelimit()) 576 netdev_err(ndev, "Tx DMA memory map failed\n"); 577 goto dma_mapping_error; 578 } 579 580 bdp->cbd_bufaddr = cpu_to_fec32(addr); 581 bdp->cbd_datlen = cpu_to_fec16(frag_len); 582 /* Make sure the updates to rest of the descriptor are 583 * performed before transferring ownership. 584 */ 585 wmb(); 586 bdp->cbd_sc = cpu_to_fec16(status); 587 } 588 589 return bdp; 590 dma_mapping_error: 591 bdp = txq->bd.cur; 592 for (i = 0; i < frag; i++) { 593 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 594 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 595 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 596 } 597 return ERR_PTR(-ENOMEM); 598 } 599 600 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 601 struct sk_buff *skb, struct net_device *ndev) 602 { 603 struct fec_enet_private *fep = netdev_priv(ndev); 604 int nr_frags = skb_shinfo(skb)->nr_frags; 605 struct bufdesc *bdp, *last_bdp; 606 void *bufaddr; 607 dma_addr_t addr; 608 unsigned short status; 609 unsigned short buflen; 610 unsigned int estatus = 0; 611 unsigned int index; 612 int entries_free; 613 614 entries_free = fec_enet_get_free_txdesc_num(txq); 615 if (entries_free < MAX_SKB_FRAGS + 1) { 616 dev_kfree_skb_any(skb); 617 if (net_ratelimit()) 618 netdev_err(ndev, "NOT enough BD for SG!\n"); 619 return NETDEV_TX_OK; 620 } 621 622 /* Protocol checksum off-load for TCP and UDP. */ 623 if (fec_enet_clear_csum(skb, ndev)) { 624 dev_kfree_skb_any(skb); 625 return NETDEV_TX_OK; 626 } 627 628 /* Fill in a Tx ring entry */ 629 bdp = txq->bd.cur; 630 last_bdp = bdp; 631 status = fec16_to_cpu(bdp->cbd_sc); 632 status &= ~BD_ENET_TX_STATS; 633 634 /* Set buffer length and buffer pointer */ 635 bufaddr = skb->data; 636 buflen = skb_headlen(skb); 637 638 index = fec_enet_get_bd_index(bdp, &txq->bd); 639 if (((unsigned long) bufaddr) & fep->tx_align || 640 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 641 memcpy(txq->tx_bounce[index], skb->data, buflen); 642 bufaddr = txq->tx_bounce[index]; 643 644 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 645 swap_buffer(bufaddr, buflen); 646 } 647 648 /* Push the data cache so the CPM does not get stale memory data. */ 649 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 650 if (dma_mapping_error(&fep->pdev->dev, addr)) { 651 dev_kfree_skb_any(skb); 652 if (net_ratelimit()) 653 netdev_err(ndev, "Tx DMA memory map failed\n"); 654 return NETDEV_TX_OK; 655 } 656 657 if (nr_frags) { 658 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 659 if (IS_ERR(last_bdp)) { 660 dma_unmap_single(&fep->pdev->dev, addr, 661 buflen, DMA_TO_DEVICE); 662 dev_kfree_skb_any(skb); 663 return NETDEV_TX_OK; 664 } 665 } else { 666 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 667 if (fep->bufdesc_ex) { 668 estatus = BD_ENET_TX_INT; 669 if (unlikely(skb_shinfo(skb)->tx_flags & 670 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 671 estatus |= BD_ENET_TX_TS; 672 } 673 } 674 bdp->cbd_bufaddr = cpu_to_fec32(addr); 675 bdp->cbd_datlen = cpu_to_fec16(buflen); 676 677 if (fep->bufdesc_ex) { 678 679 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 680 681 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 682 fep->hwts_tx_en)) 683 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 684 685 if (fep->quirks & FEC_QUIRK_HAS_AVB) 686 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 687 688 if (skb->ip_summed == CHECKSUM_PARTIAL) 689 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 690 691 ebdp->cbd_bdu = 0; 692 ebdp->cbd_esc = cpu_to_fec32(estatus); 693 } 694 695 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 696 /* Save skb pointer */ 697 txq->tx_buf[index].buf_p = skb; 698 699 /* Make sure the updates to rest of the descriptor are performed before 700 * transferring ownership. 701 */ 702 wmb(); 703 704 /* Send it on its way. Tell FEC it's ready, interrupt when done, 705 * it's the last BD of the frame, and to put the CRC on the end. 706 */ 707 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 708 bdp->cbd_sc = cpu_to_fec16(status); 709 710 /* If this was the last BD in the ring, start at the beginning again. */ 711 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 712 713 skb_tx_timestamp(skb); 714 715 /* Make sure the update to bdp is performed before txq->bd.cur. */ 716 wmb(); 717 txq->bd.cur = bdp; 718 719 /* Trigger transmission start */ 720 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 721 !readl(txq->bd.reg_desc_active) || 722 !readl(txq->bd.reg_desc_active) || 723 !readl(txq->bd.reg_desc_active) || 724 !readl(txq->bd.reg_desc_active)) 725 writel(0, txq->bd.reg_desc_active); 726 727 return 0; 728 } 729 730 static int 731 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 732 struct net_device *ndev, 733 struct bufdesc *bdp, int index, char *data, 734 int size, bool last_tcp, bool is_last) 735 { 736 struct fec_enet_private *fep = netdev_priv(ndev); 737 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 738 unsigned short status; 739 unsigned int estatus = 0; 740 dma_addr_t addr; 741 742 status = fec16_to_cpu(bdp->cbd_sc); 743 status &= ~BD_ENET_TX_STATS; 744 745 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 746 747 if (((unsigned long) data) & fep->tx_align || 748 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 749 memcpy(txq->tx_bounce[index], data, size); 750 data = txq->tx_bounce[index]; 751 752 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 753 swap_buffer(data, size); 754 } 755 756 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 757 if (dma_mapping_error(&fep->pdev->dev, addr)) { 758 dev_kfree_skb_any(skb); 759 if (net_ratelimit()) 760 netdev_err(ndev, "Tx DMA memory map failed\n"); 761 return NETDEV_TX_OK; 762 } 763 764 bdp->cbd_datlen = cpu_to_fec16(size); 765 bdp->cbd_bufaddr = cpu_to_fec32(addr); 766 767 if (fep->bufdesc_ex) { 768 if (fep->quirks & FEC_QUIRK_HAS_AVB) 769 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 770 if (skb->ip_summed == CHECKSUM_PARTIAL) 771 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 772 ebdp->cbd_bdu = 0; 773 ebdp->cbd_esc = cpu_to_fec32(estatus); 774 } 775 776 /* Handle the last BD specially */ 777 if (last_tcp) 778 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 779 if (is_last) { 780 status |= BD_ENET_TX_INTR; 781 if (fep->bufdesc_ex) 782 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 783 } 784 785 bdp->cbd_sc = cpu_to_fec16(status); 786 787 return 0; 788 } 789 790 static int 791 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 792 struct sk_buff *skb, struct net_device *ndev, 793 struct bufdesc *bdp, int index) 794 { 795 struct fec_enet_private *fep = netdev_priv(ndev); 796 int hdr_len = skb_tcp_all_headers(skb); 797 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 798 void *bufaddr; 799 unsigned long dmabuf; 800 unsigned short status; 801 unsigned int estatus = 0; 802 803 status = fec16_to_cpu(bdp->cbd_sc); 804 status &= ~BD_ENET_TX_STATS; 805 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 806 807 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 808 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 809 if (((unsigned long)bufaddr) & fep->tx_align || 810 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 811 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 812 bufaddr = txq->tx_bounce[index]; 813 814 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 815 swap_buffer(bufaddr, hdr_len); 816 817 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 818 hdr_len, DMA_TO_DEVICE); 819 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 820 dev_kfree_skb_any(skb); 821 if (net_ratelimit()) 822 netdev_err(ndev, "Tx DMA memory map failed\n"); 823 return NETDEV_TX_OK; 824 } 825 } 826 827 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 828 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 829 830 if (fep->bufdesc_ex) { 831 if (fep->quirks & FEC_QUIRK_HAS_AVB) 832 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 833 if (skb->ip_summed == CHECKSUM_PARTIAL) 834 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 835 ebdp->cbd_bdu = 0; 836 ebdp->cbd_esc = cpu_to_fec32(estatus); 837 } 838 839 bdp->cbd_sc = cpu_to_fec16(status); 840 841 return 0; 842 } 843 844 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 845 struct sk_buff *skb, 846 struct net_device *ndev) 847 { 848 struct fec_enet_private *fep = netdev_priv(ndev); 849 int hdr_len, total_len, data_left; 850 struct bufdesc *bdp = txq->bd.cur; 851 struct bufdesc *tmp_bdp; 852 struct bufdesc_ex *ebdp; 853 struct tso_t tso; 854 unsigned int index = 0; 855 int ret; 856 857 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 858 dev_kfree_skb_any(skb); 859 if (net_ratelimit()) 860 netdev_err(ndev, "NOT enough BD for TSO!\n"); 861 return NETDEV_TX_OK; 862 } 863 864 /* Protocol checksum off-load for TCP and UDP. */ 865 if (fec_enet_clear_csum(skb, ndev)) { 866 dev_kfree_skb_any(skb); 867 return NETDEV_TX_OK; 868 } 869 870 /* Initialize the TSO handler, and prepare the first payload */ 871 hdr_len = tso_start(skb, &tso); 872 873 total_len = skb->len - hdr_len; 874 while (total_len > 0) { 875 char *hdr; 876 877 index = fec_enet_get_bd_index(bdp, &txq->bd); 878 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 879 total_len -= data_left; 880 881 /* prepare packet headers: MAC + IP + TCP */ 882 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 883 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 884 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 885 if (ret) 886 goto err_release; 887 888 while (data_left > 0) { 889 int size; 890 891 size = min_t(int, tso.size, data_left); 892 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 893 index = fec_enet_get_bd_index(bdp, &txq->bd); 894 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 895 bdp, index, 896 tso.data, size, 897 size == data_left, 898 total_len == 0); 899 if (ret) 900 goto err_release; 901 902 data_left -= size; 903 tso_build_data(skb, &tso, size); 904 } 905 906 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 907 } 908 909 /* Save skb pointer */ 910 txq->tx_buf[index].buf_p = skb; 911 912 skb_tx_timestamp(skb); 913 txq->bd.cur = bdp; 914 915 /* Trigger transmission start */ 916 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 917 !readl(txq->bd.reg_desc_active) || 918 !readl(txq->bd.reg_desc_active) || 919 !readl(txq->bd.reg_desc_active) || 920 !readl(txq->bd.reg_desc_active)) 921 writel(0, txq->bd.reg_desc_active); 922 923 return 0; 924 925 err_release: 926 /* Release all used data descriptors for TSO */ 927 tmp_bdp = txq->bd.cur; 928 929 while (tmp_bdp != bdp) { 930 /* Unmap data buffers */ 931 if (tmp_bdp->cbd_bufaddr && 932 !IS_TSO_HEADER(txq, fec32_to_cpu(tmp_bdp->cbd_bufaddr))) 933 dma_unmap_single(&fep->pdev->dev, 934 fec32_to_cpu(tmp_bdp->cbd_bufaddr), 935 fec16_to_cpu(tmp_bdp->cbd_datlen), 936 DMA_TO_DEVICE); 937 938 /* Clear standard buffer descriptor fields */ 939 tmp_bdp->cbd_sc = 0; 940 tmp_bdp->cbd_datlen = 0; 941 tmp_bdp->cbd_bufaddr = 0; 942 943 /* Handle extended descriptor if enabled */ 944 if (fep->bufdesc_ex) { 945 ebdp = (struct bufdesc_ex *)tmp_bdp; 946 ebdp->cbd_esc = 0; 947 } 948 949 tmp_bdp = fec_enet_get_nextdesc(tmp_bdp, &txq->bd); 950 } 951 952 dev_kfree_skb_any(skb); 953 954 return ret; 955 } 956 957 static netdev_tx_t 958 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 959 { 960 struct fec_enet_private *fep = netdev_priv(ndev); 961 int entries_free; 962 unsigned short queue; 963 struct fec_enet_priv_tx_q *txq; 964 struct netdev_queue *nq; 965 int ret; 966 967 queue = skb_get_queue_mapping(skb); 968 txq = fep->tx_queue[queue]; 969 nq = netdev_get_tx_queue(ndev, queue); 970 971 if (skb_is_gso(skb)) 972 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 973 else 974 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 975 if (ret) 976 return ret; 977 978 entries_free = fec_enet_get_free_txdesc_num(txq); 979 if (entries_free <= txq->tx_stop_threshold) 980 netif_tx_stop_queue(nq); 981 982 return NETDEV_TX_OK; 983 } 984 985 /* Init RX & TX buffer descriptors 986 */ 987 static void fec_enet_bd_init(struct net_device *dev) 988 { 989 struct fec_enet_private *fep = netdev_priv(dev); 990 struct fec_enet_priv_tx_q *txq; 991 struct fec_enet_priv_rx_q *rxq; 992 struct bufdesc *bdp; 993 unsigned int i; 994 unsigned int q; 995 996 for (q = 0; q < fep->num_rx_queues; q++) { 997 /* Initialize the receive buffer descriptors. */ 998 rxq = fep->rx_queue[q]; 999 bdp = rxq->bd.base; 1000 1001 for (i = 0; i < rxq->bd.ring_size; i++) { 1002 1003 /* Initialize the BD for every fragment in the page. */ 1004 if (bdp->cbd_bufaddr) 1005 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 1006 else 1007 bdp->cbd_sc = cpu_to_fec16(0); 1008 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1009 } 1010 1011 /* Set the last buffer to wrap */ 1012 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 1013 bdp->cbd_sc |= cpu_to_fec16(BD_ENET_RX_WRAP); 1014 1015 rxq->bd.cur = rxq->bd.base; 1016 } 1017 1018 for (q = 0; q < fep->num_tx_queues; q++) { 1019 /* ...and the same for transmit */ 1020 txq = fep->tx_queue[q]; 1021 bdp = txq->bd.base; 1022 txq->bd.cur = bdp; 1023 1024 for (i = 0; i < txq->bd.ring_size; i++) { 1025 /* Initialize the BD for every fragment in the page. */ 1026 bdp->cbd_sc = cpu_to_fec16(0); 1027 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 1028 if (bdp->cbd_bufaddr && 1029 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1030 dma_unmap_single(&fep->pdev->dev, 1031 fec32_to_cpu(bdp->cbd_bufaddr), 1032 fec16_to_cpu(bdp->cbd_datlen), 1033 DMA_TO_DEVICE); 1034 if (txq->tx_buf[i].buf_p) 1035 dev_kfree_skb_any(txq->tx_buf[i].buf_p); 1036 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 1037 if (bdp->cbd_bufaddr) 1038 dma_unmap_single(&fep->pdev->dev, 1039 fec32_to_cpu(bdp->cbd_bufaddr), 1040 fec16_to_cpu(bdp->cbd_datlen), 1041 DMA_TO_DEVICE); 1042 1043 if (txq->tx_buf[i].buf_p) 1044 xdp_return_frame(txq->tx_buf[i].buf_p); 1045 } else { 1046 struct page *page = txq->tx_buf[i].buf_p; 1047 1048 if (page) 1049 page_pool_put_page(pp_page_to_nmdesc(page)->pp, 1050 page, 0, 1051 false); 1052 } 1053 1054 txq->tx_buf[i].buf_p = NULL; 1055 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1056 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 1057 bdp->cbd_bufaddr = cpu_to_fec32(0); 1058 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1059 } 1060 1061 /* Set the last buffer to wrap */ 1062 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 1063 bdp->cbd_sc |= cpu_to_fec16(BD_ENET_TX_WRAP); 1064 txq->dirty_tx = bdp; 1065 } 1066 } 1067 1068 static void fec_enet_active_rxring(struct net_device *ndev) 1069 { 1070 struct fec_enet_private *fep = netdev_priv(ndev); 1071 int i; 1072 1073 for (i = 0; i < fep->num_rx_queues; i++) 1074 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 1075 } 1076 1077 static void fec_enet_enable_ring(struct net_device *ndev) 1078 { 1079 struct fec_enet_private *fep = netdev_priv(ndev); 1080 struct fec_enet_priv_tx_q *txq; 1081 struct fec_enet_priv_rx_q *rxq; 1082 int i; 1083 1084 for (i = 0; i < fep->num_rx_queues; i++) { 1085 rxq = fep->rx_queue[i]; 1086 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 1087 writel(fep->max_buf_size, fep->hwp + FEC_R_BUFF_SIZE(i)); 1088 1089 /* enable DMA1/2 */ 1090 if (i) 1091 writel(RCMR_MATCHEN | RCMR_CMP(i), 1092 fep->hwp + FEC_RCMR(i)); 1093 } 1094 1095 for (i = 0; i < fep->num_tx_queues; i++) { 1096 txq = fep->tx_queue[i]; 1097 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 1098 1099 /* enable DMA1/2 */ 1100 if (i) 1101 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 1102 fep->hwp + FEC_DMA_CFG(i)); 1103 } 1104 } 1105 1106 /* Whack a reset. We should wait for this. 1107 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1108 * instead of reset MAC itself. 1109 */ 1110 static void fec_ctrl_reset(struct fec_enet_private *fep, bool allow_wol) 1111 { 1112 u32 val; 1113 1114 if (!allow_wol || !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1115 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || 1116 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 1117 writel(0, fep->hwp + FEC_ECNTRL); 1118 } else { 1119 writel(FEC_ECR_RESET, fep->hwp + FEC_ECNTRL); 1120 udelay(10); 1121 } 1122 } else { 1123 val = readl(fep->hwp + FEC_ECNTRL); 1124 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1125 writel(val, fep->hwp + FEC_ECNTRL); 1126 } 1127 } 1128 1129 static void fec_set_hw_mac_addr(struct net_device *ndev) 1130 { 1131 struct fec_enet_private *fep = netdev_priv(ndev); 1132 1133 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 1134 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 1135 fep->hwp + FEC_ADDR_LOW); 1136 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 1137 fep->hwp + FEC_ADDR_HIGH); 1138 } 1139 1140 /* 1141 * This function is called to start or restart the FEC during a link 1142 * change, transmit timeout, or to reconfigure the FEC. The network 1143 * packet processing for this device must be stopped before this call. 1144 */ 1145 static void 1146 fec_restart(struct net_device *ndev) 1147 { 1148 struct fec_enet_private *fep = netdev_priv(ndev); 1149 u32 ecntl = FEC_ECR_ETHEREN; 1150 u32 rcntl = FEC_RCR_MII; 1151 1152 if (OPT_ARCH_HAS_MAX_FL) 1153 rcntl |= (fep->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN) << 16; 1154 1155 if (fep->bufdesc_ex) 1156 fec_ptp_save_state(fep); 1157 1158 fec_ctrl_reset(fep, false); 1159 1160 /* 1161 * enet-mac reset will reset mac address registers too, 1162 * so need to reconfigure it. 1163 */ 1164 fec_set_hw_mac_addr(ndev); 1165 1166 /* Clear any outstanding interrupt, except MDIO. */ 1167 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 1168 1169 fec_enet_bd_init(ndev); 1170 1171 fec_enet_enable_ring(ndev); 1172 1173 /* Enable MII mode */ 1174 if (fep->full_duplex == DUPLEX_FULL) { 1175 /* FD enable */ 1176 writel(0x04, fep->hwp + FEC_X_CNTRL); 1177 } else { 1178 /* No Rcv on Xmit */ 1179 rcntl |= FEC_RCR_DRT; 1180 writel(0x0, fep->hwp + FEC_X_CNTRL); 1181 } 1182 1183 /* Set MII speed */ 1184 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1185 1186 #if !defined(CONFIG_M5272) 1187 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1188 u32 val = readl(fep->hwp + FEC_RACC); 1189 1190 /* align IP header */ 1191 val |= FEC_RACC_SHIFT16; 1192 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1193 /* set RX checksum */ 1194 val |= FEC_RACC_OPTIONS; 1195 else 1196 val &= ~FEC_RACC_OPTIONS; 1197 writel(val, fep->hwp + FEC_RACC); 1198 writel(min(fep->rx_frame_size, fep->max_buf_size), fep->hwp + FEC_FTRL); 1199 } 1200 #endif 1201 1202 /* 1203 * The phy interface and speed need to get configured 1204 * differently on enet-mac. 1205 */ 1206 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1207 /* Enable flow control and length check */ 1208 rcntl |= FEC_RCR_NLC | FEC_RCR_FLOWCTL; 1209 1210 /* RGMII, RMII or MII */ 1211 if (phy_interface_mode_is_rgmii(fep->phy_interface)) 1212 rcntl |= FEC_RCR_RGMII; 1213 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1214 rcntl |= FEC_RCR_RMII; 1215 else 1216 rcntl &= ~FEC_RCR_RMII; 1217 1218 /* 1G, 100M or 10M */ 1219 if (ndev->phydev) { 1220 if (ndev->phydev->speed == SPEED_1000) 1221 ecntl |= FEC_ECR_SPEED; 1222 else if (ndev->phydev->speed == SPEED_100) 1223 rcntl &= ~FEC_RCR_10BASET; 1224 else 1225 rcntl |= FEC_RCR_10BASET; 1226 } 1227 } else { 1228 #ifdef FEC_MIIGSK_ENR 1229 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1230 u32 cfgr; 1231 /* disable the gasket and wait */ 1232 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1233 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1234 udelay(1); 1235 1236 /* 1237 * configure the gasket: 1238 * RMII, 50 MHz, no loopback, no echo 1239 * MII, 25 MHz, no loopback, no echo 1240 */ 1241 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1242 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1243 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1244 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1245 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1246 1247 /* re-enable the gasket */ 1248 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1249 } 1250 #endif 1251 } 1252 1253 #if !defined(CONFIG_M5272) 1254 /* enable pause frame*/ 1255 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1256 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1257 ndev->phydev && ndev->phydev->pause)) { 1258 rcntl |= FEC_RCR_FLOWCTL; 1259 1260 /* set FIFO threshold parameter to reduce overrun */ 1261 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1262 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1263 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1264 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1265 1266 /* OPD */ 1267 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1268 } else { 1269 rcntl &= ~FEC_RCR_FLOWCTL; 1270 } 1271 #endif /* !defined(CONFIG_M5272) */ 1272 1273 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1274 1275 /* Setup multicast filter. */ 1276 set_multicast_list(ndev); 1277 #ifndef CONFIG_M5272 1278 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1279 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1280 #endif 1281 1282 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1283 /* enable ENET endian swap */ 1284 ecntl |= FEC_ECR_BYTESWP; 1285 1286 /* When Jumbo Frame is enabled, the FIFO may not be large enough 1287 * to hold an entire frame. In such cases, if the MTU exceeds 1288 * (PKT_MAXBUF_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN), configure 1289 * the interface to operate in cut-through mode, triggered by 1290 * the FIFO threshold. 1291 * Otherwise, enable the ENET store-and-forward mode. 1292 */ 1293 if ((fep->quirks & FEC_QUIRK_JUMBO_FRAME) && 1294 (ndev->mtu > (PKT_MAXBUF_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN))) 1295 writel(0xF, fep->hwp + FEC_X_WMRK); 1296 else 1297 writel(FEC_TXWMRK_STRFWD, fep->hwp + FEC_X_WMRK); 1298 } 1299 1300 if (fep->bufdesc_ex) 1301 ecntl |= FEC_ECR_EN1588; 1302 1303 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1304 fep->rgmii_txc_dly) 1305 ecntl |= FEC_ENET_TXC_DLY; 1306 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1307 fep->rgmii_rxc_dly) 1308 ecntl |= FEC_ENET_RXC_DLY; 1309 1310 #ifndef CONFIG_M5272 1311 /* Enable the MIB statistic event counters */ 1312 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1313 #endif 1314 1315 /* And last, enable the transmit and receive processing */ 1316 writel(ecntl, fep->hwp + FEC_ECNTRL); 1317 fec_enet_active_rxring(ndev); 1318 1319 if (fep->bufdesc_ex) { 1320 fec_ptp_start_cyclecounter(ndev); 1321 fec_ptp_restore_state(fep); 1322 } 1323 1324 /* Enable interrupts we wish to service */ 1325 if (fep->link) 1326 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1327 else 1328 writel(0, fep->hwp + FEC_IMASK); 1329 1330 /* Init the interrupt coalescing */ 1331 if (fep->quirks & FEC_QUIRK_HAS_COALESCE) 1332 fec_enet_itr_coal_set(ndev); 1333 } 1334 1335 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep) 1336 { 1337 if (!(of_machine_is_compatible("fsl,imx8qm") || 1338 of_machine_is_compatible("fsl,imx8qp") || 1339 of_machine_is_compatible("fsl,imx8qxp") || 1340 of_machine_is_compatible("fsl,imx8dx") || 1341 of_machine_is_compatible("fsl,imx8dxl"))) 1342 return 0; 1343 1344 return imx_scu_get_handle(&fep->ipc_handle); 1345 } 1346 1347 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled) 1348 { 1349 struct device_node *np = fep->pdev->dev.of_node; 1350 u32 rsrc_id, val; 1351 int idx; 1352 1353 if (!np || !fep->ipc_handle) 1354 return; 1355 1356 idx = of_alias_get_id(np, "ethernet"); 1357 if (idx < 0) 1358 idx = 0; 1359 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0; 1360 1361 val = enabled ? 1 : 0; 1362 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val); 1363 } 1364 1365 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1366 { 1367 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1368 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1369 1370 if (stop_gpr->gpr) { 1371 if (enabled) 1372 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1373 BIT(stop_gpr->bit), 1374 BIT(stop_gpr->bit)); 1375 else 1376 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1377 BIT(stop_gpr->bit), 0); 1378 } else if (pdata && pdata->sleep_mode_enable) { 1379 pdata->sleep_mode_enable(enabled); 1380 } else { 1381 fec_enet_ipg_stop_set(fep, enabled); 1382 } 1383 } 1384 1385 static void fec_irqs_disable(struct net_device *ndev) 1386 { 1387 struct fec_enet_private *fep = netdev_priv(ndev); 1388 1389 writel(0, fep->hwp + FEC_IMASK); 1390 } 1391 1392 static void fec_irqs_disable_except_wakeup(struct net_device *ndev) 1393 { 1394 struct fec_enet_private *fep = netdev_priv(ndev); 1395 1396 writel(0, fep->hwp + FEC_IMASK); 1397 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1398 } 1399 1400 static void 1401 fec_stop(struct net_device *ndev) 1402 { 1403 struct fec_enet_private *fep = netdev_priv(ndev); 1404 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & FEC_RCR_RMII; 1405 u32 val; 1406 1407 /* We cannot expect a graceful transmit stop without link !!! */ 1408 if (fep->link) { 1409 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1410 udelay(10); 1411 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1412 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1413 } 1414 1415 if (fep->bufdesc_ex) 1416 fec_ptp_save_state(fep); 1417 1418 fec_ctrl_reset(fep, true); 1419 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1420 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1421 1422 /* We have to keep ENET enabled to have MII interrupt stay working */ 1423 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1424 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1425 writel(FEC_ECR_ETHEREN, fep->hwp + FEC_ECNTRL); 1426 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1427 } 1428 1429 if (fep->bufdesc_ex) { 1430 val = readl(fep->hwp + FEC_ECNTRL); 1431 val |= FEC_ECR_EN1588; 1432 writel(val, fep->hwp + FEC_ECNTRL); 1433 1434 fec_ptp_start_cyclecounter(ndev); 1435 fec_ptp_restore_state(fep); 1436 } 1437 } 1438 1439 static void 1440 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1441 { 1442 struct fec_enet_private *fep = netdev_priv(ndev); 1443 1444 fec_dump(ndev); 1445 1446 ndev->stats.tx_errors++; 1447 1448 schedule_work(&fep->tx_timeout_work); 1449 } 1450 1451 static void fec_enet_timeout_work(struct work_struct *work) 1452 { 1453 struct fec_enet_private *fep = 1454 container_of(work, struct fec_enet_private, tx_timeout_work); 1455 struct net_device *ndev = fep->netdev; 1456 1457 rtnl_lock(); 1458 if (netif_device_present(ndev) || netif_running(ndev)) { 1459 napi_disable(&fep->napi); 1460 netif_tx_lock_bh(ndev); 1461 fec_restart(ndev); 1462 netif_tx_wake_all_queues(ndev); 1463 netif_tx_unlock_bh(ndev); 1464 napi_enable(&fep->napi); 1465 } 1466 rtnl_unlock(); 1467 } 1468 1469 static void 1470 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1471 struct skb_shared_hwtstamps *hwtstamps) 1472 { 1473 unsigned long flags; 1474 u64 ns; 1475 1476 spin_lock_irqsave(&fep->tmreg_lock, flags); 1477 ns = timecounter_cyc2time(&fep->tc, ts); 1478 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1479 1480 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1481 hwtstamps->hwtstamp = ns_to_ktime(ns); 1482 } 1483 1484 static void 1485 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id, int budget) 1486 { 1487 struct fec_enet_private *fep; 1488 struct xdp_frame *xdpf; 1489 struct bufdesc *bdp; 1490 unsigned short status; 1491 struct sk_buff *skb; 1492 struct fec_enet_priv_tx_q *txq; 1493 struct netdev_queue *nq; 1494 int index = 0; 1495 int entries_free; 1496 struct page *page; 1497 int frame_len; 1498 1499 fep = netdev_priv(ndev); 1500 1501 txq = fep->tx_queue[queue_id]; 1502 /* get next bdp of dirty_tx */ 1503 nq = netdev_get_tx_queue(ndev, queue_id); 1504 bdp = txq->dirty_tx; 1505 1506 /* get next bdp of dirty_tx */ 1507 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1508 1509 while (bdp != READ_ONCE(txq->bd.cur)) { 1510 /* Order the load of bd.cur and cbd_sc */ 1511 rmb(); 1512 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1513 if (status & BD_ENET_TX_READY) 1514 break; 1515 1516 index = fec_enet_get_bd_index(bdp, &txq->bd); 1517 1518 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1519 skb = txq->tx_buf[index].buf_p; 1520 if (bdp->cbd_bufaddr && 1521 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1522 dma_unmap_single(&fep->pdev->dev, 1523 fec32_to_cpu(bdp->cbd_bufaddr), 1524 fec16_to_cpu(bdp->cbd_datlen), 1525 DMA_TO_DEVICE); 1526 bdp->cbd_bufaddr = cpu_to_fec32(0); 1527 if (!skb) 1528 goto tx_buf_done; 1529 } else { 1530 /* Tx processing cannot call any XDP (or page pool) APIs if 1531 * the "budget" is 0. Because NAPI is called with budget of 1532 * 0 (such as netpoll) indicates we may be in an IRQ context, 1533 * however, we can't use the page pool from IRQ context. 1534 */ 1535 if (unlikely(!budget)) 1536 break; 1537 1538 if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1539 xdpf = txq->tx_buf[index].buf_p; 1540 if (bdp->cbd_bufaddr) 1541 dma_unmap_single(&fep->pdev->dev, 1542 fec32_to_cpu(bdp->cbd_bufaddr), 1543 fec16_to_cpu(bdp->cbd_datlen), 1544 DMA_TO_DEVICE); 1545 } else { 1546 page = txq->tx_buf[index].buf_p; 1547 } 1548 1549 bdp->cbd_bufaddr = cpu_to_fec32(0); 1550 if (unlikely(!txq->tx_buf[index].buf_p)) { 1551 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1552 goto tx_buf_done; 1553 } 1554 1555 frame_len = fec16_to_cpu(bdp->cbd_datlen); 1556 } 1557 1558 /* Check for errors. */ 1559 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1560 BD_ENET_TX_RL | BD_ENET_TX_UN | 1561 BD_ENET_TX_CSL)) { 1562 ndev->stats.tx_errors++; 1563 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1564 ndev->stats.tx_heartbeat_errors++; 1565 if (status & BD_ENET_TX_LC) /* Late collision */ 1566 ndev->stats.tx_window_errors++; 1567 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1568 ndev->stats.tx_aborted_errors++; 1569 if (status & BD_ENET_TX_UN) /* Underrun */ 1570 ndev->stats.tx_fifo_errors++; 1571 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1572 ndev->stats.tx_carrier_errors++; 1573 } else { 1574 ndev->stats.tx_packets++; 1575 1576 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) 1577 ndev->stats.tx_bytes += skb->len; 1578 else 1579 ndev->stats.tx_bytes += frame_len; 1580 } 1581 1582 /* Deferred means some collisions occurred during transmit, 1583 * but we eventually sent the packet OK. 1584 */ 1585 if (status & BD_ENET_TX_DEF) 1586 ndev->stats.collisions++; 1587 1588 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1589 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1590 * are to time stamp the packet, so we still need to check time 1591 * stamping enabled flag. 1592 */ 1593 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1594 fep->hwts_tx_en) && fep->bufdesc_ex) { 1595 struct skb_shared_hwtstamps shhwtstamps; 1596 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1597 1598 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1599 skb_tstamp_tx(skb, &shhwtstamps); 1600 } 1601 1602 /* Free the sk buffer associated with this last transmit */ 1603 napi_consume_skb(skb, budget); 1604 } else if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1605 xdp_return_frame_rx_napi(xdpf); 1606 } else { /* recycle pages of XDP_TX frames */ 1607 /* The dma_sync_size = 0 as XDP_TX has already synced DMA for_device */ 1608 page_pool_put_page(pp_page_to_nmdesc(page)->pp, page, 1609 0, true); 1610 } 1611 1612 txq->tx_buf[index].buf_p = NULL; 1613 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1614 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1615 1616 tx_buf_done: 1617 /* Make sure the update to bdp and tx_buf are performed 1618 * before dirty_tx 1619 */ 1620 wmb(); 1621 txq->dirty_tx = bdp; 1622 1623 /* Update pointer to next buffer descriptor to be transmitted */ 1624 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1625 1626 /* Since we have freed up a buffer, the ring is no longer full 1627 */ 1628 if (netif_tx_queue_stopped(nq)) { 1629 entries_free = fec_enet_get_free_txdesc_num(txq); 1630 if (entries_free >= txq->tx_wake_threshold) 1631 netif_tx_wake_queue(nq); 1632 } 1633 } 1634 1635 /* ERR006358: Keep the transmitter going */ 1636 if (bdp != txq->bd.cur && 1637 readl(txq->bd.reg_desc_active) == 0) 1638 writel(0, txq->bd.reg_desc_active); 1639 } 1640 1641 static void fec_enet_tx(struct net_device *ndev, int budget) 1642 { 1643 struct fec_enet_private *fep = netdev_priv(ndev); 1644 int i; 1645 1646 /* Make sure that AVB queues are processed first. */ 1647 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1648 fec_enet_tx_queue(ndev, i, budget); 1649 } 1650 1651 static int fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq, 1652 struct bufdesc *bdp, int index) 1653 { 1654 struct page *new_page; 1655 dma_addr_t phys_addr; 1656 1657 new_page = page_pool_dev_alloc_pages(rxq->page_pool); 1658 if (unlikely(!new_page)) 1659 return -ENOMEM; 1660 1661 rxq->rx_buf[index] = new_page; 1662 phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM; 1663 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 1664 1665 return 0; 1666 } 1667 1668 static u32 1669 fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog, 1670 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int cpu) 1671 { 1672 unsigned int sync, len = xdp->data_end - xdp->data; 1673 u32 ret = FEC_ENET_XDP_PASS; 1674 struct page *page; 1675 int err; 1676 u32 act; 1677 1678 act = bpf_prog_run_xdp(prog, xdp); 1679 1680 /* Due xdp_adjust_tail and xdp_adjust_head: DMA sync for_device cover 1681 * max len CPU touch 1682 */ 1683 sync = xdp->data_end - xdp->data; 1684 sync = max(sync, len); 1685 1686 switch (act) { 1687 case XDP_PASS: 1688 rxq->stats[RX_XDP_PASS]++; 1689 ret = FEC_ENET_XDP_PASS; 1690 break; 1691 1692 case XDP_REDIRECT: 1693 rxq->stats[RX_XDP_REDIRECT]++; 1694 err = xdp_do_redirect(fep->netdev, xdp, prog); 1695 if (unlikely(err)) 1696 goto xdp_err; 1697 1698 ret = FEC_ENET_XDP_REDIR; 1699 break; 1700 1701 case XDP_TX: 1702 rxq->stats[RX_XDP_TX]++; 1703 err = fec_enet_xdp_tx_xmit(fep, cpu, xdp, sync); 1704 if (unlikely(err)) { 1705 rxq->stats[RX_XDP_TX_ERRORS]++; 1706 goto xdp_err; 1707 } 1708 1709 ret = FEC_ENET_XDP_TX; 1710 break; 1711 1712 default: 1713 bpf_warn_invalid_xdp_action(fep->netdev, prog, act); 1714 fallthrough; 1715 1716 case XDP_ABORTED: 1717 fallthrough; /* handle aborts by dropping packet */ 1718 1719 case XDP_DROP: 1720 rxq->stats[RX_XDP_DROP]++; 1721 xdp_err: 1722 ret = FEC_ENET_XDP_CONSUMED; 1723 page = virt_to_head_page(xdp->data); 1724 page_pool_put_page(rxq->page_pool, page, sync, true); 1725 if (act != XDP_DROP) 1726 trace_xdp_exception(fep->netdev, prog, act); 1727 break; 1728 } 1729 1730 return ret; 1731 } 1732 1733 static void fec_enet_rx_vlan(const struct net_device *ndev, struct sk_buff *skb) 1734 { 1735 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX) { 1736 const struct vlan_ethhdr *vlan_header = skb_vlan_eth_hdr(skb); 1737 const u16 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1738 1739 /* Push and remove the vlan tag */ 1740 1741 memmove(skb->data + VLAN_HLEN, skb->data, ETH_ALEN * 2); 1742 skb_pull(skb, VLAN_HLEN); 1743 __vlan_hwaccel_put_tag(skb, 1744 htons(ETH_P_8021Q), 1745 vlan_tag); 1746 } 1747 } 1748 1749 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1750 * When we update through the ring, if the next incoming buffer has 1751 * not been given to the system, we just set the empty indicator, 1752 * effectively tossing the packet. 1753 */ 1754 static int 1755 fec_enet_rx_queue(struct net_device *ndev, u16 queue_id, int budget) 1756 { 1757 struct fec_enet_private *fep = netdev_priv(ndev); 1758 struct fec_enet_priv_rx_q *rxq; 1759 struct bufdesc *bdp; 1760 unsigned short status; 1761 struct sk_buff *skb; 1762 ushort pkt_len; 1763 int pkt_received = 0; 1764 struct bufdesc_ex *ebdp = NULL; 1765 int index = 0; 1766 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1767 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 1768 u32 ret, xdp_result = FEC_ENET_XDP_PASS; 1769 u32 data_start = FEC_ENET_XDP_HEADROOM; 1770 int cpu = smp_processor_id(); 1771 struct xdp_buff xdp; 1772 struct page *page; 1773 __fec32 cbd_bufaddr; 1774 u32 sub_len = 4; 1775 1776 /*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of 1777 * FEC_RACC_SHIFT16 is set by default in the probe function. 1778 */ 1779 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1780 data_start += 2; 1781 sub_len += 2; 1782 } 1783 1784 #if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA) 1785 /* 1786 * Hacky flush of all caches instead of using the DMA API for the TSO 1787 * headers. 1788 */ 1789 flush_cache_all(); 1790 #endif 1791 rxq = fep->rx_queue[queue_id]; 1792 1793 /* First, grab all of the stats for the incoming packet. 1794 * These get messed up if we get called due to a busy condition. 1795 */ 1796 bdp = rxq->bd.cur; 1797 xdp_init_buff(&xdp, PAGE_SIZE << fep->pagepool_order, &rxq->xdp_rxq); 1798 1799 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1800 1801 if (pkt_received >= budget) 1802 break; 1803 pkt_received++; 1804 1805 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT); 1806 1807 /* Check for errors. */ 1808 status ^= BD_ENET_RX_LAST; 1809 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1810 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1811 BD_ENET_RX_CL)) { 1812 ndev->stats.rx_errors++; 1813 if (status & BD_ENET_RX_OV) { 1814 /* FIFO overrun */ 1815 ndev->stats.rx_fifo_errors++; 1816 goto rx_processing_done; 1817 } 1818 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1819 | BD_ENET_RX_LAST)) { 1820 /* Frame too long or too short. */ 1821 ndev->stats.rx_length_errors++; 1822 if (status & BD_ENET_RX_LAST) 1823 netdev_err(ndev, "rcv is not +last\n"); 1824 } 1825 if (status & BD_ENET_RX_CR) /* CRC Error */ 1826 ndev->stats.rx_crc_errors++; 1827 /* Report late collisions as a frame error. */ 1828 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1829 ndev->stats.rx_frame_errors++; 1830 goto rx_processing_done; 1831 } 1832 1833 /* Process the incoming frame. */ 1834 ndev->stats.rx_packets++; 1835 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1836 ndev->stats.rx_bytes += pkt_len; 1837 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1838 ndev->stats.rx_bytes -= 2; 1839 1840 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1841 page = rxq->rx_buf[index]; 1842 cbd_bufaddr = bdp->cbd_bufaddr; 1843 if (fec_enet_update_cbd(rxq, bdp, index)) { 1844 ndev->stats.rx_dropped++; 1845 goto rx_processing_done; 1846 } 1847 1848 dma_sync_single_for_cpu(&fep->pdev->dev, 1849 fec32_to_cpu(cbd_bufaddr), 1850 pkt_len, 1851 DMA_FROM_DEVICE); 1852 prefetch(page_address(page)); 1853 1854 if (xdp_prog) { 1855 xdp_buff_clear_frags_flag(&xdp); 1856 /* subtract 16bit shift and FCS */ 1857 xdp_prepare_buff(&xdp, page_address(page), 1858 data_start, pkt_len - sub_len, false); 1859 ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, cpu); 1860 xdp_result |= ret; 1861 if (ret != FEC_ENET_XDP_PASS) 1862 goto rx_processing_done; 1863 } 1864 1865 /* The packet length includes FCS, but we don't want to 1866 * include that when passing upstream as it messes up 1867 * bridging applications. 1868 */ 1869 skb = build_skb(page_address(page), 1870 PAGE_SIZE << fep->pagepool_order); 1871 if (unlikely(!skb)) { 1872 page_pool_recycle_direct(rxq->page_pool, page); 1873 ndev->stats.rx_dropped++; 1874 1875 netdev_err_once(ndev, "build_skb failed!\n"); 1876 goto rx_processing_done; 1877 } 1878 1879 skb_reserve(skb, data_start); 1880 skb_put(skb, pkt_len - sub_len); 1881 skb_mark_for_recycle(skb); 1882 1883 if (unlikely(need_swap)) { 1884 u8 *data; 1885 1886 data = page_address(page) + FEC_ENET_XDP_HEADROOM; 1887 swap_buffer(data, pkt_len); 1888 } 1889 1890 /* Extract the enhanced buffer descriptor */ 1891 ebdp = NULL; 1892 if (fep->bufdesc_ex) 1893 ebdp = (struct bufdesc_ex *)bdp; 1894 1895 /* If this is a VLAN packet remove the VLAN Tag */ 1896 if (fep->bufdesc_ex && 1897 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) 1898 fec_enet_rx_vlan(ndev, skb); 1899 1900 skb->protocol = eth_type_trans(skb, ndev); 1901 1902 /* Get receive timestamp from the skb */ 1903 if (fep->hwts_rx_en && fep->bufdesc_ex) 1904 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1905 skb_hwtstamps(skb)); 1906 1907 if (fep->bufdesc_ex && 1908 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1909 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1910 /* don't check it */ 1911 skb->ip_summed = CHECKSUM_UNNECESSARY; 1912 } else { 1913 skb_checksum_none_assert(skb); 1914 } 1915 } 1916 1917 skb_record_rx_queue(skb, queue_id); 1918 napi_gro_receive(&fep->napi, skb); 1919 1920 rx_processing_done: 1921 /* Clear the status flags for this buffer */ 1922 status &= ~BD_ENET_RX_STATS; 1923 1924 /* Mark the buffer empty */ 1925 status |= BD_ENET_RX_EMPTY; 1926 1927 if (fep->bufdesc_ex) { 1928 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1929 1930 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1931 ebdp->cbd_prot = 0; 1932 ebdp->cbd_bdu = 0; 1933 } 1934 /* Make sure the updates to rest of the descriptor are 1935 * performed before transferring ownership. 1936 */ 1937 wmb(); 1938 bdp->cbd_sc = cpu_to_fec16(status); 1939 1940 /* Update BD pointer to next entry */ 1941 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1942 1943 /* Doing this here will keep the FEC running while we process 1944 * incoming frames. On a heavily loaded network, we should be 1945 * able to keep up at the expense of system resources. 1946 */ 1947 writel(0, rxq->bd.reg_desc_active); 1948 } 1949 rxq->bd.cur = bdp; 1950 1951 if (xdp_result & FEC_ENET_XDP_REDIR) 1952 xdp_do_flush(); 1953 1954 return pkt_received; 1955 } 1956 1957 static int fec_enet_rx(struct net_device *ndev, int budget) 1958 { 1959 struct fec_enet_private *fep = netdev_priv(ndev); 1960 int i, done = 0; 1961 1962 /* Make sure that AVB queues are processed first. */ 1963 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1964 done += fec_enet_rx_queue(ndev, i, budget - done); 1965 1966 return done; 1967 } 1968 1969 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1970 { 1971 uint int_events; 1972 1973 int_events = readl(fep->hwp + FEC_IEVENT); 1974 1975 /* Don't clear MDIO events, we poll for those */ 1976 int_events &= ~FEC_ENET_MII; 1977 1978 writel(int_events, fep->hwp + FEC_IEVENT); 1979 1980 return int_events != 0; 1981 } 1982 1983 static irqreturn_t 1984 fec_enet_interrupt(int irq, void *dev_id) 1985 { 1986 struct net_device *ndev = dev_id; 1987 struct fec_enet_private *fep = netdev_priv(ndev); 1988 irqreturn_t ret = IRQ_NONE; 1989 1990 if (fec_enet_collect_events(fep) && fep->link) { 1991 ret = IRQ_HANDLED; 1992 1993 if (napi_schedule_prep(&fep->napi)) { 1994 /* Disable interrupts */ 1995 writel(0, fep->hwp + FEC_IMASK); 1996 __napi_schedule(&fep->napi); 1997 } 1998 } 1999 2000 return ret; 2001 } 2002 2003 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 2004 { 2005 struct net_device *ndev = napi->dev; 2006 struct fec_enet_private *fep = netdev_priv(ndev); 2007 int done = 0; 2008 2009 do { 2010 done += fec_enet_rx(ndev, budget - done); 2011 fec_enet_tx(ndev, budget); 2012 } while ((done < budget) && fec_enet_collect_events(fep)); 2013 2014 if (done < budget) { 2015 napi_complete_done(napi, done); 2016 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 2017 } 2018 2019 return done; 2020 } 2021 2022 /* ------------------------------------------------------------------------- */ 2023 static int fec_get_mac(struct net_device *ndev) 2024 { 2025 struct fec_enet_private *fep = netdev_priv(ndev); 2026 unsigned char *iap, tmpaddr[ETH_ALEN]; 2027 int ret; 2028 2029 /* 2030 * try to get mac address in following order: 2031 * 2032 * 1) module parameter via kernel command line in form 2033 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 2034 */ 2035 iap = macaddr; 2036 2037 /* 2038 * 2) from device tree data 2039 */ 2040 if (!is_valid_ether_addr(iap)) { 2041 struct device_node *np = fep->pdev->dev.of_node; 2042 if (np) { 2043 ret = of_get_mac_address(np, tmpaddr); 2044 if (!ret) 2045 iap = tmpaddr; 2046 else if (ret == -EPROBE_DEFER) 2047 return ret; 2048 } 2049 } 2050 2051 /* 2052 * 3) from flash or fuse (via platform data) 2053 */ 2054 if (!is_valid_ether_addr(iap)) { 2055 #ifdef CONFIG_M5272 2056 if (FEC_FLASHMAC) 2057 iap = (unsigned char *)FEC_FLASHMAC; 2058 #else 2059 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 2060 2061 if (pdata) 2062 iap = (unsigned char *)&pdata->mac; 2063 #endif 2064 } 2065 2066 /* 2067 * 4) FEC mac registers set by bootloader 2068 */ 2069 if (!is_valid_ether_addr(iap)) { 2070 *((__be32 *) &tmpaddr[0]) = 2071 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 2072 *((__be16 *) &tmpaddr[4]) = 2073 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 2074 iap = &tmpaddr[0]; 2075 } 2076 2077 /* 2078 * 5) random mac address 2079 */ 2080 if (!is_valid_ether_addr(iap)) { 2081 /* Report it and use a random ethernet address instead */ 2082 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 2083 eth_hw_addr_random(ndev); 2084 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 2085 ndev->dev_addr); 2086 return 0; 2087 } 2088 2089 /* Adjust MAC if using macaddr */ 2090 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0); 2091 2092 return 0; 2093 } 2094 2095 /* ------------------------------------------------------------------------- */ 2096 2097 /* 2098 * Phy section 2099 */ 2100 2101 /* LPI Sleep Ts count base on tx clk (clk_ref). 2102 * The lpi sleep cnt value = X us / (cycle_ns). 2103 */ 2104 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) 2105 { 2106 struct fec_enet_private *fep = netdev_priv(ndev); 2107 2108 return us * (fep->clk_ref_rate / 1000) / 1000; 2109 } 2110 2111 static int fec_enet_eee_mode_set(struct net_device *ndev, u32 lpi_timer, 2112 bool enable) 2113 { 2114 struct fec_enet_private *fep = netdev_priv(ndev); 2115 unsigned int sleep_cycle, wake_cycle; 2116 2117 if (enable) { 2118 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, lpi_timer); 2119 wake_cycle = sleep_cycle; 2120 } else { 2121 sleep_cycle = 0; 2122 wake_cycle = 0; 2123 } 2124 2125 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); 2126 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); 2127 2128 return 0; 2129 } 2130 2131 static void fec_enet_adjust_link(struct net_device *ndev) 2132 { 2133 struct fec_enet_private *fep = netdev_priv(ndev); 2134 struct phy_device *phy_dev = ndev->phydev; 2135 int status_change = 0; 2136 2137 /* 2138 * If the netdev is down, or is going down, we're not interested 2139 * in link state events, so just mark our idea of the link as down 2140 * and ignore the event. 2141 */ 2142 if (!netif_running(ndev) || !netif_device_present(ndev)) { 2143 fep->link = 0; 2144 } else if (phy_dev->link) { 2145 if (!fep->link) { 2146 fep->link = phy_dev->link; 2147 status_change = 1; 2148 } 2149 2150 if (fep->full_duplex != phy_dev->duplex) { 2151 fep->full_duplex = phy_dev->duplex; 2152 status_change = 1; 2153 } 2154 2155 if (phy_dev->speed != fep->speed) { 2156 fep->speed = phy_dev->speed; 2157 status_change = 1; 2158 } 2159 2160 /* if any of the above changed restart the FEC */ 2161 if (status_change) { 2162 netif_stop_queue(ndev); 2163 napi_disable(&fep->napi); 2164 netif_tx_lock_bh(ndev); 2165 fec_restart(ndev); 2166 netif_tx_wake_all_queues(ndev); 2167 netif_tx_unlock_bh(ndev); 2168 napi_enable(&fep->napi); 2169 } 2170 if (fep->quirks & FEC_QUIRK_HAS_EEE) 2171 fec_enet_eee_mode_set(ndev, 2172 phy_dev->eee_cfg.tx_lpi_timer, 2173 phy_dev->enable_tx_lpi); 2174 } else { 2175 if (fep->link) { 2176 netif_stop_queue(ndev); 2177 napi_disable(&fep->napi); 2178 netif_tx_lock_bh(ndev); 2179 fec_stop(ndev); 2180 netif_tx_unlock_bh(ndev); 2181 napi_enable(&fep->napi); 2182 fep->link = phy_dev->link; 2183 status_change = 1; 2184 } 2185 } 2186 2187 if (status_change) 2188 phy_print_status(phy_dev); 2189 } 2190 2191 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 2192 { 2193 uint ievent; 2194 int ret; 2195 2196 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 2197 ievent & FEC_ENET_MII, 2, 30000); 2198 2199 if (!ret) 2200 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2201 2202 return ret; 2203 } 2204 2205 static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) 2206 { 2207 struct fec_enet_private *fep = bus->priv; 2208 struct device *dev = &fep->pdev->dev; 2209 int ret = 0, frame_start, frame_addr, frame_op; 2210 2211 ret = pm_runtime_resume_and_get(dev); 2212 if (ret < 0) 2213 return ret; 2214 2215 /* C22 read */ 2216 frame_op = FEC_MMFR_OP_READ; 2217 frame_start = FEC_MMFR_ST; 2218 frame_addr = regnum; 2219 2220 /* start a read op */ 2221 writel(frame_start | frame_op | 2222 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2223 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2224 2225 /* wait for end of transfer */ 2226 ret = fec_enet_mdio_wait(fep); 2227 if (ret) { 2228 netdev_err(fep->netdev, "MDIO read timeout\n"); 2229 goto out; 2230 } 2231 2232 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2233 2234 out: 2235 pm_runtime_put_autosuspend(dev); 2236 2237 return ret; 2238 } 2239 2240 static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id, 2241 int devad, int regnum) 2242 { 2243 struct fec_enet_private *fep = bus->priv; 2244 struct device *dev = &fep->pdev->dev; 2245 int ret = 0, frame_start, frame_op; 2246 2247 ret = pm_runtime_resume_and_get(dev); 2248 if (ret < 0) 2249 return ret; 2250 2251 frame_start = FEC_MMFR_ST_C45; 2252 2253 /* write address */ 2254 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2255 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2256 FEC_MMFR_TA | (regnum & 0xFFFF), 2257 fep->hwp + FEC_MII_DATA); 2258 2259 /* wait for end of transfer */ 2260 ret = fec_enet_mdio_wait(fep); 2261 if (ret) { 2262 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2263 goto out; 2264 } 2265 2266 frame_op = FEC_MMFR_OP_READ_C45; 2267 2268 /* start a read op */ 2269 writel(frame_start | frame_op | 2270 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2271 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2272 2273 /* wait for end of transfer */ 2274 ret = fec_enet_mdio_wait(fep); 2275 if (ret) { 2276 netdev_err(fep->netdev, "MDIO read timeout\n"); 2277 goto out; 2278 } 2279 2280 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2281 2282 out: 2283 pm_runtime_put_autosuspend(dev); 2284 2285 return ret; 2286 } 2287 2288 static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, 2289 u16 value) 2290 { 2291 struct fec_enet_private *fep = bus->priv; 2292 struct device *dev = &fep->pdev->dev; 2293 int ret, frame_start, frame_addr; 2294 2295 ret = pm_runtime_resume_and_get(dev); 2296 if (ret < 0) 2297 return ret; 2298 2299 /* C22 write */ 2300 frame_start = FEC_MMFR_ST; 2301 frame_addr = regnum; 2302 2303 /* start a write op */ 2304 writel(frame_start | FEC_MMFR_OP_WRITE | 2305 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2306 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2307 fep->hwp + FEC_MII_DATA); 2308 2309 /* wait for end of transfer */ 2310 ret = fec_enet_mdio_wait(fep); 2311 if (ret) 2312 netdev_err(fep->netdev, "MDIO write timeout\n"); 2313 2314 pm_runtime_put_autosuspend(dev); 2315 2316 return ret; 2317 } 2318 2319 static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id, 2320 int devad, int regnum, u16 value) 2321 { 2322 struct fec_enet_private *fep = bus->priv; 2323 struct device *dev = &fep->pdev->dev; 2324 int ret, frame_start; 2325 2326 ret = pm_runtime_resume_and_get(dev); 2327 if (ret < 0) 2328 return ret; 2329 2330 frame_start = FEC_MMFR_ST_C45; 2331 2332 /* write address */ 2333 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2334 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2335 FEC_MMFR_TA | (regnum & 0xFFFF), 2336 fep->hwp + FEC_MII_DATA); 2337 2338 /* wait for end of transfer */ 2339 ret = fec_enet_mdio_wait(fep); 2340 if (ret) { 2341 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2342 goto out; 2343 } 2344 2345 /* start a write op */ 2346 writel(frame_start | FEC_MMFR_OP_WRITE | 2347 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2348 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2349 fep->hwp + FEC_MII_DATA); 2350 2351 /* wait for end of transfer */ 2352 ret = fec_enet_mdio_wait(fep); 2353 if (ret) 2354 netdev_err(fep->netdev, "MDIO write timeout\n"); 2355 2356 out: 2357 pm_runtime_put_autosuspend(dev); 2358 2359 return ret; 2360 } 2361 2362 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 2363 { 2364 struct fec_enet_private *fep = netdev_priv(ndev); 2365 struct phy_device *phy_dev = ndev->phydev; 2366 2367 if (phy_dev) { 2368 phy_reset_after_clk_enable(phy_dev); 2369 } else if (fep->phy_node) { 2370 /* 2371 * If the PHY still is not bound to the MAC, but there is 2372 * OF PHY node and a matching PHY device instance already, 2373 * use the OF PHY node to obtain the PHY device instance, 2374 * and then use that PHY device instance when triggering 2375 * the PHY reset. 2376 */ 2377 phy_dev = of_phy_find_device(fep->phy_node); 2378 phy_reset_after_clk_enable(phy_dev); 2379 if (phy_dev) 2380 put_device(&phy_dev->mdio.dev); 2381 } 2382 } 2383 2384 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 2385 { 2386 struct fec_enet_private *fep = netdev_priv(ndev); 2387 int ret; 2388 2389 if (enable) { 2390 ret = clk_prepare_enable(fep->clk_enet_out); 2391 if (ret) 2392 return ret; 2393 2394 if (fep->clk_ptp) { 2395 mutex_lock(&fep->ptp_clk_mutex); 2396 ret = clk_prepare_enable(fep->clk_ptp); 2397 if (ret) { 2398 mutex_unlock(&fep->ptp_clk_mutex); 2399 goto failed_clk_ptp; 2400 } else { 2401 fep->ptp_clk_on = true; 2402 } 2403 mutex_unlock(&fep->ptp_clk_mutex); 2404 } 2405 2406 ret = clk_prepare_enable(fep->clk_ref); 2407 if (ret) 2408 goto failed_clk_ref; 2409 2410 ret = clk_prepare_enable(fep->clk_2x_txclk); 2411 if (ret) 2412 goto failed_clk_2x_txclk; 2413 2414 fec_enet_phy_reset_after_clk_enable(ndev); 2415 } else { 2416 clk_disable_unprepare(fep->clk_enet_out); 2417 if (fep->clk_ptp) { 2418 mutex_lock(&fep->ptp_clk_mutex); 2419 clk_disable_unprepare(fep->clk_ptp); 2420 fep->ptp_clk_on = false; 2421 mutex_unlock(&fep->ptp_clk_mutex); 2422 } 2423 clk_disable_unprepare(fep->clk_ref); 2424 clk_disable_unprepare(fep->clk_2x_txclk); 2425 } 2426 2427 return 0; 2428 2429 failed_clk_2x_txclk: 2430 if (fep->clk_ref) 2431 clk_disable_unprepare(fep->clk_ref); 2432 failed_clk_ref: 2433 if (fep->clk_ptp) { 2434 mutex_lock(&fep->ptp_clk_mutex); 2435 clk_disable_unprepare(fep->clk_ptp); 2436 fep->ptp_clk_on = false; 2437 mutex_unlock(&fep->ptp_clk_mutex); 2438 } 2439 failed_clk_ptp: 2440 clk_disable_unprepare(fep->clk_enet_out); 2441 2442 return ret; 2443 } 2444 2445 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep, 2446 struct device_node *np) 2447 { 2448 u32 rgmii_tx_delay, rgmii_rx_delay; 2449 2450 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ 2451 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { 2452 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) { 2453 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); 2454 return -EINVAL; 2455 } else if (rgmii_tx_delay == 2000) { 2456 fep->rgmii_txc_dly = true; 2457 } 2458 } 2459 2460 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */ 2461 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { 2462 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) { 2463 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); 2464 return -EINVAL; 2465 } else if (rgmii_rx_delay == 2000) { 2466 fep->rgmii_rxc_dly = true; 2467 } 2468 } 2469 2470 return 0; 2471 } 2472 2473 static int fec_enet_mii_probe(struct net_device *ndev) 2474 { 2475 struct fec_enet_private *fep = netdev_priv(ndev); 2476 struct phy_device *phy_dev; 2477 int ret; 2478 2479 if (fep->phy_node) { 2480 phy_dev = of_phy_connect(ndev, fep->phy_node, 2481 &fec_enet_adjust_link, 0, 2482 fep->phy_interface); 2483 if (!phy_dev) { 2484 netdev_err(ndev, "Unable to connect to phy\n"); 2485 return -ENODEV; 2486 } 2487 } else { 2488 /* check for attached phy */ 2489 phy_dev = phy_find_first(fep->mii_bus); 2490 if (fep->dev_id && phy_dev) 2491 phy_dev = phy_find_next(fep->mii_bus, phy_dev); 2492 2493 if (!phy_dev) { 2494 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2495 phy_dev = fixed_phy_register_100fd(); 2496 if (IS_ERR(phy_dev)) { 2497 netdev_err(ndev, "could not register fixed PHY\n"); 2498 return PTR_ERR(phy_dev); 2499 } 2500 } 2501 2502 ret = phy_connect_direct(ndev, phy_dev, &fec_enet_adjust_link, 2503 fep->phy_interface); 2504 if (ret) { 2505 if (phy_is_pseudo_fixed_link(phy_dev)) 2506 fixed_phy_unregister(phy_dev); 2507 netdev_err(ndev, "could not attach to PHY\n"); 2508 return ret; 2509 } 2510 2511 } 2512 2513 /* mask with MAC supported features */ 2514 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2515 phy_set_max_speed(phy_dev, 1000); 2516 phy_remove_link_mode(phy_dev, 2517 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2518 phy_support_sym_pause(phy_dev); 2519 } 2520 else 2521 phy_set_max_speed(phy_dev, 100); 2522 2523 if (fep->quirks & FEC_QUIRK_HAS_EEE) 2524 phy_support_eee(phy_dev); 2525 2526 fep->link = 0; 2527 fep->full_duplex = 0; 2528 2529 phy_attached_info(phy_dev); 2530 2531 return 0; 2532 } 2533 2534 static int fec_enet_mii_init(struct platform_device *pdev) 2535 { 2536 static struct mii_bus *fec0_mii_bus; 2537 struct net_device *ndev = platform_get_drvdata(pdev); 2538 struct fec_enet_private *fep = netdev_priv(ndev); 2539 bool suppress_preamble = false; 2540 struct phy_device *phydev; 2541 struct device_node *node; 2542 int err = -ENXIO; 2543 u32 mii_speed, holdtime; 2544 u32 bus_freq; 2545 2546 /* 2547 * The i.MX28 dual fec interfaces are not equal. 2548 * Here are the differences: 2549 * 2550 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2551 * - fec0 acts as the 1588 time master while fec1 is slave 2552 * - external phys can only be configured by fec0 2553 * 2554 * That is to say fec1 can not work independently. It only works 2555 * when fec0 is working. The reason behind this design is that the 2556 * second interface is added primarily for Switch mode. 2557 * 2558 * Because of the last point above, both phys are attached on fec0 2559 * mdio interface in board design, and need to be configured by 2560 * fec0 mii_bus. 2561 */ 2562 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2563 /* fec1 uses fec0 mii_bus */ 2564 if (mii_cnt && fec0_mii_bus) { 2565 fep->mii_bus = fec0_mii_bus; 2566 mii_cnt++; 2567 return 0; 2568 } 2569 return -ENOENT; 2570 } 2571 2572 bus_freq = 2500000; /* 2.5MHz by default */ 2573 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2574 if (node) { 2575 of_property_read_u32(node, "clock-frequency", &bus_freq); 2576 suppress_preamble = of_property_read_bool(node, 2577 "suppress-preamble"); 2578 } 2579 2580 /* 2581 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2582 * 2583 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2584 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2585 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2586 * document. 2587 */ 2588 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2589 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2590 mii_speed--; 2591 if (mii_speed > 63) { 2592 dev_err(&pdev->dev, 2593 "fec clock (%lu) too fast to get right mii speed\n", 2594 clk_get_rate(fep->clk_ipg)); 2595 err = -EINVAL; 2596 goto err_out; 2597 } 2598 2599 /* 2600 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2601 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2602 * versions are RAZ there, so just ignore the difference and write the 2603 * register always. 2604 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2605 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2606 * output. 2607 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2608 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2609 * holdtime cannot result in a value greater than 3. 2610 */ 2611 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2612 2613 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2614 2615 if (suppress_preamble) 2616 fep->phy_speed |= BIT(7); 2617 2618 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2619 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2620 * MII event generation condition: 2621 * - writing MSCR: 2622 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2623 * mscr_reg_data_in[7:0] != 0 2624 * - writing MMFR: 2625 * - mscr[7:0]_not_zero 2626 */ 2627 writel(0, fep->hwp + FEC_MII_DATA); 2628 } 2629 2630 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2631 2632 /* Clear any pending transaction complete indication */ 2633 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2634 2635 fep->mii_bus = mdiobus_alloc(); 2636 if (fep->mii_bus == NULL) { 2637 err = -ENOMEM; 2638 goto err_out; 2639 } 2640 2641 fep->mii_bus->name = "fec_enet_mii_bus"; 2642 fep->mii_bus->read = fec_enet_mdio_read_c22; 2643 fep->mii_bus->write = fec_enet_mdio_write_c22; 2644 if (fep->quirks & FEC_QUIRK_HAS_MDIO_C45) { 2645 fep->mii_bus->read_c45 = fec_enet_mdio_read_c45; 2646 fep->mii_bus->write_c45 = fec_enet_mdio_write_c45; 2647 } 2648 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2649 pdev->name, fep->dev_id + 1); 2650 fep->mii_bus->priv = fep; 2651 fep->mii_bus->parent = &pdev->dev; 2652 2653 err = of_mdiobus_register(fep->mii_bus, node); 2654 if (err) 2655 goto err_out_free_mdiobus; 2656 of_node_put(node); 2657 2658 /* find all the PHY devices on the bus and set mac_managed_pm to true */ 2659 mdiobus_for_each_phy(fep->mii_bus, phydev) 2660 phydev->mac_managed_pm = true; 2661 2662 mii_cnt++; 2663 2664 /* save fec0 mii_bus */ 2665 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2666 fec0_mii_bus = fep->mii_bus; 2667 2668 return 0; 2669 2670 err_out_free_mdiobus: 2671 mdiobus_free(fep->mii_bus); 2672 err_out: 2673 of_node_put(node); 2674 return err; 2675 } 2676 2677 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2678 { 2679 if (--mii_cnt == 0) { 2680 mdiobus_unregister(fep->mii_bus); 2681 mdiobus_free(fep->mii_bus); 2682 } 2683 } 2684 2685 static void fec_enet_get_drvinfo(struct net_device *ndev, 2686 struct ethtool_drvinfo *info) 2687 { 2688 struct fec_enet_private *fep = netdev_priv(ndev); 2689 2690 strscpy(info->driver, fep->pdev->dev.driver->name, 2691 sizeof(info->driver)); 2692 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2693 } 2694 2695 static int fec_enet_get_regs_len(struct net_device *ndev) 2696 { 2697 struct fec_enet_private *fep = netdev_priv(ndev); 2698 struct resource *r; 2699 int s = 0; 2700 2701 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2702 if (r) 2703 s = resource_size(r); 2704 2705 return s; 2706 } 2707 2708 /* List of registers that can be safety be read to dump them with ethtool */ 2709 #if !defined(CONFIG_M5272) || defined(CONFIG_COMPILE_TEST) 2710 static __u32 fec_enet_register_version = 2; 2711 static u32 fec_enet_register_offset[] = { 2712 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2713 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2714 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2715 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2716 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2717 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2718 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2719 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2720 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2721 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2722 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2723 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2724 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2725 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2726 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2727 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2728 RMON_T_P_GTE2048, RMON_T_OCTETS, 2729 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2730 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2731 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2732 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2733 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2734 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2735 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2736 RMON_R_P_GTE2048, RMON_R_OCTETS, 2737 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2738 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2739 }; 2740 /* for i.MX6ul */ 2741 static u32 fec_enet_register_offset_6ul[] = { 2742 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2743 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2744 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0, 2745 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, 2746 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0, 2747 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2748 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, 2749 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2750 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2751 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2752 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2753 RMON_T_P_GTE2048, RMON_T_OCTETS, 2754 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2755 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2756 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2757 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2758 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2759 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2760 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2761 RMON_R_P_GTE2048, RMON_R_OCTETS, 2762 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2763 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2764 }; 2765 #else 2766 static __u32 fec_enet_register_version = 1; 2767 static u32 fec_enet_register_offset[] = { 2768 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2769 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2770 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2771 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2772 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2773 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2774 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2775 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2776 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2777 }; 2778 #endif 2779 2780 static void fec_enet_get_regs(struct net_device *ndev, 2781 struct ethtool_regs *regs, void *regbuf) 2782 { 2783 u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2784 struct fec_enet_private *fep = netdev_priv(ndev); 2785 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2786 u32 *reg_list = fec_enet_register_offset; 2787 struct device *dev = &fep->pdev->dev; 2788 u32 *buf = (u32 *)regbuf; 2789 u32 i, off; 2790 int ret; 2791 2792 #if !defined(CONFIG_M5272) || defined(CONFIG_COMPILE_TEST) 2793 if (of_machine_is_compatible("fsl,imx6ul")) { 2794 reg_list = fec_enet_register_offset_6ul; 2795 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul); 2796 } 2797 #endif 2798 2799 ret = pm_runtime_resume_and_get(dev); 2800 if (ret < 0) 2801 return; 2802 2803 regs->version = fec_enet_register_version; 2804 2805 memset(buf, 0, regs->len); 2806 2807 for (i = 0; i < reg_cnt; i++) { 2808 off = reg_list[i]; 2809 2810 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2811 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2812 continue; 2813 2814 off >>= 2; 2815 buf[off] = readl(&theregs[off]); 2816 } 2817 2818 pm_runtime_put_autosuspend(dev); 2819 } 2820 2821 static int fec_enet_get_ts_info(struct net_device *ndev, 2822 struct kernel_ethtool_ts_info *info) 2823 { 2824 struct fec_enet_private *fep = netdev_priv(ndev); 2825 2826 if (fep->bufdesc_ex) { 2827 2828 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2829 SOF_TIMESTAMPING_TX_HARDWARE | 2830 SOF_TIMESTAMPING_RX_HARDWARE | 2831 SOF_TIMESTAMPING_RAW_HARDWARE; 2832 if (fep->ptp_clock) 2833 info->phc_index = ptp_clock_index(fep->ptp_clock); 2834 2835 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2836 (1 << HWTSTAMP_TX_ON); 2837 2838 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2839 (1 << HWTSTAMP_FILTER_ALL); 2840 return 0; 2841 } else { 2842 return ethtool_op_get_ts_info(ndev, info); 2843 } 2844 } 2845 2846 #if !defined(CONFIG_M5272) 2847 2848 static void fec_enet_get_pauseparam(struct net_device *ndev, 2849 struct ethtool_pauseparam *pause) 2850 { 2851 struct fec_enet_private *fep = netdev_priv(ndev); 2852 2853 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2854 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2855 pause->rx_pause = pause->tx_pause; 2856 } 2857 2858 static int fec_enet_set_pauseparam(struct net_device *ndev, 2859 struct ethtool_pauseparam *pause) 2860 { 2861 struct fec_enet_private *fep = netdev_priv(ndev); 2862 2863 if (!ndev->phydev) 2864 return -ENODEV; 2865 2866 if (pause->tx_pause != pause->rx_pause) { 2867 netdev_info(ndev, 2868 "hardware only support enable/disable both tx and rx"); 2869 return -EINVAL; 2870 } 2871 2872 fep->pause_flag = 0; 2873 2874 /* tx pause must be same as rx pause */ 2875 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2876 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2877 2878 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2879 pause->autoneg); 2880 2881 if (pause->autoneg) { 2882 if (netif_running(ndev)) 2883 fec_stop(ndev); 2884 phy_start_aneg(ndev->phydev); 2885 } 2886 if (netif_running(ndev)) { 2887 napi_disable(&fep->napi); 2888 netif_tx_lock_bh(ndev); 2889 fec_restart(ndev); 2890 netif_tx_wake_all_queues(ndev); 2891 netif_tx_unlock_bh(ndev); 2892 napi_enable(&fep->napi); 2893 } 2894 2895 return 0; 2896 } 2897 2898 static const struct fec_stat { 2899 char name[ETH_GSTRING_LEN]; 2900 u16 offset; 2901 } fec_stats[] = { 2902 /* RMON TX */ 2903 { "tx_dropped", RMON_T_DROP }, 2904 { "tx_packets", RMON_T_PACKETS }, 2905 { "tx_broadcast", RMON_T_BC_PKT }, 2906 { "tx_multicast", RMON_T_MC_PKT }, 2907 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2908 { "tx_undersize", RMON_T_UNDERSIZE }, 2909 { "tx_oversize", RMON_T_OVERSIZE }, 2910 { "tx_fragment", RMON_T_FRAG }, 2911 { "tx_jabber", RMON_T_JAB }, 2912 { "tx_collision", RMON_T_COL }, 2913 { "tx_64byte", RMON_T_P64 }, 2914 { "tx_65to127byte", RMON_T_P65TO127 }, 2915 { "tx_128to255byte", RMON_T_P128TO255 }, 2916 { "tx_256to511byte", RMON_T_P256TO511 }, 2917 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2918 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2919 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2920 { "tx_octets", RMON_T_OCTETS }, 2921 2922 /* IEEE TX */ 2923 { "IEEE_tx_drop", IEEE_T_DROP }, 2924 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2925 { "IEEE_tx_1col", IEEE_T_1COL }, 2926 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2927 { "IEEE_tx_def", IEEE_T_DEF }, 2928 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2929 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2930 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2931 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2932 { "IEEE_tx_sqe", IEEE_T_SQE }, 2933 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2934 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2935 2936 /* RMON RX */ 2937 { "rx_packets", RMON_R_PACKETS }, 2938 { "rx_broadcast", RMON_R_BC_PKT }, 2939 { "rx_multicast", RMON_R_MC_PKT }, 2940 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2941 { "rx_undersize", RMON_R_UNDERSIZE }, 2942 { "rx_oversize", RMON_R_OVERSIZE }, 2943 { "rx_fragment", RMON_R_FRAG }, 2944 { "rx_jabber", RMON_R_JAB }, 2945 { "rx_64byte", RMON_R_P64 }, 2946 { "rx_65to127byte", RMON_R_P65TO127 }, 2947 { "rx_128to255byte", RMON_R_P128TO255 }, 2948 { "rx_256to511byte", RMON_R_P256TO511 }, 2949 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2950 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2951 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2952 { "rx_octets", RMON_R_OCTETS }, 2953 2954 /* IEEE RX */ 2955 { "IEEE_rx_drop", IEEE_R_DROP }, 2956 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2957 { "IEEE_rx_crc", IEEE_R_CRC }, 2958 { "IEEE_rx_align", IEEE_R_ALIGN }, 2959 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2960 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2961 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2962 }; 2963 2964 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2965 2966 static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = { 2967 "rx_xdp_redirect", /* RX_XDP_REDIRECT = 0, */ 2968 "rx_xdp_pass", /* RX_XDP_PASS, */ 2969 "rx_xdp_drop", /* RX_XDP_DROP, */ 2970 "rx_xdp_tx", /* RX_XDP_TX, */ 2971 "rx_xdp_tx_errors", /* RX_XDP_TX_ERRORS, */ 2972 "tx_xdp_xmit", /* TX_XDP_XMIT, */ 2973 "tx_xdp_xmit_errors", /* TX_XDP_XMIT_ERRORS, */ 2974 }; 2975 2976 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2977 { 2978 struct fec_enet_private *fep = netdev_priv(dev); 2979 int i; 2980 2981 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2982 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2983 } 2984 2985 static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data) 2986 { 2987 u64 xdp_stats[XDP_STATS_TOTAL] = { 0 }; 2988 struct fec_enet_priv_rx_q *rxq; 2989 int i, j; 2990 2991 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2992 rxq = fep->rx_queue[i]; 2993 2994 for (j = 0; j < XDP_STATS_TOTAL; j++) 2995 xdp_stats[j] += rxq->stats[j]; 2996 } 2997 2998 memcpy(data, xdp_stats, sizeof(xdp_stats)); 2999 } 3000 3001 static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data) 3002 { 3003 #ifdef CONFIG_PAGE_POOL_STATS 3004 struct page_pool_stats stats = {}; 3005 struct fec_enet_priv_rx_q *rxq; 3006 int i; 3007 3008 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 3009 rxq = fep->rx_queue[i]; 3010 3011 if (!rxq->page_pool) 3012 continue; 3013 3014 page_pool_get_stats(rxq->page_pool, &stats); 3015 } 3016 3017 page_pool_ethtool_stats_get(data, &stats); 3018 #endif 3019 } 3020 3021 static void fec_enet_get_ethtool_stats(struct net_device *dev, 3022 struct ethtool_stats *stats, u64 *data) 3023 { 3024 struct fec_enet_private *fep = netdev_priv(dev); 3025 3026 if (netif_running(dev)) 3027 fec_enet_update_ethtool_stats(dev); 3028 3029 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 3030 data += FEC_STATS_SIZE / sizeof(u64); 3031 3032 fec_enet_get_xdp_stats(fep, data); 3033 data += XDP_STATS_TOTAL; 3034 3035 fec_enet_page_pool_stats(fep, data); 3036 } 3037 3038 static void fec_enet_get_strings(struct net_device *netdev, 3039 u32 stringset, u8 *data) 3040 { 3041 int i; 3042 switch (stringset) { 3043 case ETH_SS_STATS: 3044 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) { 3045 ethtool_puts(&data, fec_stats[i].name); 3046 } 3047 for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) { 3048 ethtool_puts(&data, fec_xdp_stat_strs[i]); 3049 } 3050 page_pool_ethtool_stats_get_strings(data); 3051 3052 break; 3053 case ETH_SS_TEST: 3054 net_selftest_get_strings(data); 3055 break; 3056 } 3057 } 3058 3059 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 3060 { 3061 int count; 3062 3063 switch (sset) { 3064 case ETH_SS_STATS: 3065 count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL; 3066 count += page_pool_ethtool_stats_get_count(); 3067 return count; 3068 3069 case ETH_SS_TEST: 3070 return net_selftest_get_count(); 3071 default: 3072 return -EOPNOTSUPP; 3073 } 3074 } 3075 3076 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 3077 { 3078 struct fec_enet_private *fep = netdev_priv(dev); 3079 struct fec_enet_priv_rx_q *rxq; 3080 int i, j; 3081 3082 /* Disable MIB statistics counters */ 3083 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 3084 3085 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 3086 writel(0, fep->hwp + fec_stats[i].offset); 3087 3088 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 3089 rxq = fep->rx_queue[i]; 3090 for (j = 0; j < XDP_STATS_TOTAL; j++) 3091 rxq->stats[j] = 0; 3092 } 3093 3094 /* Don't disable MIB statistics counters */ 3095 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 3096 } 3097 3098 #else /* !defined(CONFIG_M5272) */ 3099 #define FEC_STATS_SIZE 0 3100 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 3101 { 3102 } 3103 3104 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 3105 { 3106 } 3107 #endif /* !defined(CONFIG_M5272) */ 3108 3109 /* ITR clock source is enet system clock (clk_ahb). 3110 * TCTT unit is cycle_ns * 64 cycle 3111 * So, the ICTT value = X us / (cycle_ns * 64) 3112 */ 3113 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 3114 { 3115 struct fec_enet_private *fep = netdev_priv(ndev); 3116 3117 return us * (fep->itr_clk_rate / 64000) / 1000; 3118 } 3119 3120 /* Set threshold for interrupt coalescing */ 3121 static void fec_enet_itr_coal_set(struct net_device *ndev) 3122 { 3123 struct fec_enet_private *fep = netdev_priv(ndev); 3124 u32 rx_itr = 0, tx_itr = 0; 3125 int rx_ictt, tx_ictt; 3126 3127 rx_ictt = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); 3128 tx_ictt = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); 3129 3130 if (rx_ictt > 0 && fep->rx_pkts_itr > 1) { 3131 /* Enable with enet system clock as Interrupt Coalescing timer Clock Source */ 3132 rx_itr = FEC_ITR_EN | FEC_ITR_CLK_SEL; 3133 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 3134 rx_itr |= FEC_ITR_ICTT(rx_ictt); 3135 } 3136 3137 if (tx_ictt > 0 && fep->tx_pkts_itr > 1) { 3138 /* Enable with enet system clock as Interrupt Coalescing timer Clock Source */ 3139 tx_itr = FEC_ITR_EN | FEC_ITR_CLK_SEL; 3140 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 3141 tx_itr |= FEC_ITR_ICTT(tx_ictt); 3142 } 3143 3144 writel(tx_itr, fep->hwp + FEC_TXIC0); 3145 writel(rx_itr, fep->hwp + FEC_RXIC0); 3146 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 3147 writel(tx_itr, fep->hwp + FEC_TXIC1); 3148 writel(rx_itr, fep->hwp + FEC_RXIC1); 3149 writel(tx_itr, fep->hwp + FEC_TXIC2); 3150 writel(rx_itr, fep->hwp + FEC_RXIC2); 3151 } 3152 } 3153 3154 static int fec_enet_get_coalesce(struct net_device *ndev, 3155 struct ethtool_coalesce *ec, 3156 struct kernel_ethtool_coalesce *kernel_coal, 3157 struct netlink_ext_ack *extack) 3158 { 3159 struct fec_enet_private *fep = netdev_priv(ndev); 3160 3161 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3162 return -EOPNOTSUPP; 3163 3164 ec->rx_coalesce_usecs = fep->rx_time_itr; 3165 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 3166 3167 ec->tx_coalesce_usecs = fep->tx_time_itr; 3168 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 3169 3170 return 0; 3171 } 3172 3173 static int fec_enet_set_coalesce(struct net_device *ndev, 3174 struct ethtool_coalesce *ec, 3175 struct kernel_ethtool_coalesce *kernel_coal, 3176 struct netlink_ext_ack *extack) 3177 { 3178 struct fec_enet_private *fep = netdev_priv(ndev); 3179 struct device *dev = &fep->pdev->dev; 3180 unsigned int cycle; 3181 3182 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3183 return -EOPNOTSUPP; 3184 3185 if (ec->rx_max_coalesced_frames > 255) { 3186 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 3187 return -EINVAL; 3188 } 3189 3190 if (ec->tx_max_coalesced_frames > 255) { 3191 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 3192 return -EINVAL; 3193 } 3194 3195 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 3196 if (cycle > 0xFFFF) { 3197 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 3198 return -EINVAL; 3199 } 3200 3201 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 3202 if (cycle > 0xFFFF) { 3203 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 3204 return -EINVAL; 3205 } 3206 3207 fep->rx_time_itr = ec->rx_coalesce_usecs; 3208 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 3209 3210 fep->tx_time_itr = ec->tx_coalesce_usecs; 3211 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 3212 3213 fec_enet_itr_coal_set(ndev); 3214 3215 return 0; 3216 } 3217 3218 static int 3219 fec_enet_get_eee(struct net_device *ndev, struct ethtool_keee *edata) 3220 { 3221 struct fec_enet_private *fep = netdev_priv(ndev); 3222 3223 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3224 return -EOPNOTSUPP; 3225 3226 if (!netif_running(ndev)) 3227 return -ENETDOWN; 3228 3229 return phy_ethtool_get_eee(ndev->phydev, edata); 3230 } 3231 3232 static int 3233 fec_enet_set_eee(struct net_device *ndev, struct ethtool_keee *edata) 3234 { 3235 struct fec_enet_private *fep = netdev_priv(ndev); 3236 3237 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3238 return -EOPNOTSUPP; 3239 3240 if (!netif_running(ndev)) 3241 return -ENETDOWN; 3242 3243 return phy_ethtool_set_eee(ndev->phydev, edata); 3244 } 3245 3246 static void 3247 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3248 { 3249 struct fec_enet_private *fep = netdev_priv(ndev); 3250 3251 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 3252 wol->supported = WAKE_MAGIC; 3253 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 3254 } else { 3255 wol->supported = wol->wolopts = 0; 3256 } 3257 } 3258 3259 static int 3260 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3261 { 3262 struct fec_enet_private *fep = netdev_priv(ndev); 3263 3264 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 3265 return -EINVAL; 3266 3267 if (wol->wolopts & ~WAKE_MAGIC) 3268 return -EINVAL; 3269 3270 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 3271 if (device_may_wakeup(&ndev->dev)) 3272 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 3273 else 3274 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 3275 3276 return 0; 3277 } 3278 3279 static const struct ethtool_ops fec_enet_ethtool_ops = { 3280 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3281 ETHTOOL_COALESCE_MAX_FRAMES, 3282 .get_drvinfo = fec_enet_get_drvinfo, 3283 .get_regs_len = fec_enet_get_regs_len, 3284 .get_regs = fec_enet_get_regs, 3285 .nway_reset = phy_ethtool_nway_reset, 3286 .get_link = ethtool_op_get_link, 3287 .get_coalesce = fec_enet_get_coalesce, 3288 .set_coalesce = fec_enet_set_coalesce, 3289 #ifndef CONFIG_M5272 3290 .get_pauseparam = fec_enet_get_pauseparam, 3291 .set_pauseparam = fec_enet_set_pauseparam, 3292 .get_strings = fec_enet_get_strings, 3293 .get_ethtool_stats = fec_enet_get_ethtool_stats, 3294 .get_sset_count = fec_enet_get_sset_count, 3295 #endif 3296 .get_ts_info = fec_enet_get_ts_info, 3297 .get_wol = fec_enet_get_wol, 3298 .set_wol = fec_enet_set_wol, 3299 .get_eee = fec_enet_get_eee, 3300 .set_eee = fec_enet_set_eee, 3301 .get_link_ksettings = phy_ethtool_get_link_ksettings, 3302 .set_link_ksettings = phy_ethtool_set_link_ksettings, 3303 .self_test = net_selftest, 3304 }; 3305 3306 static void fec_enet_free_buffers(struct net_device *ndev) 3307 { 3308 struct fec_enet_private *fep = netdev_priv(ndev); 3309 unsigned int i; 3310 struct fec_enet_priv_tx_q *txq; 3311 struct fec_enet_priv_rx_q *rxq; 3312 unsigned int q; 3313 3314 for (q = 0; q < fep->num_rx_queues; q++) { 3315 rxq = fep->rx_queue[q]; 3316 for (i = 0; i < rxq->bd.ring_size; i++) 3317 page_pool_put_full_page(rxq->page_pool, rxq->rx_buf[i], 3318 false); 3319 3320 for (i = 0; i < XDP_STATS_TOTAL; i++) 3321 rxq->stats[i] = 0; 3322 3323 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 3324 xdp_rxq_info_unreg(&rxq->xdp_rxq); 3325 page_pool_destroy(rxq->page_pool); 3326 rxq->page_pool = NULL; 3327 } 3328 3329 for (q = 0; q < fep->num_tx_queues; q++) { 3330 txq = fep->tx_queue[q]; 3331 for (i = 0; i < txq->bd.ring_size; i++) { 3332 kfree(txq->tx_bounce[i]); 3333 txq->tx_bounce[i] = NULL; 3334 3335 if (!txq->tx_buf[i].buf_p) { 3336 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3337 continue; 3338 } 3339 3340 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 3341 dev_kfree_skb(txq->tx_buf[i].buf_p); 3342 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 3343 xdp_return_frame(txq->tx_buf[i].buf_p); 3344 } else { 3345 struct page *page = txq->tx_buf[i].buf_p; 3346 3347 page_pool_put_page(pp_page_to_nmdesc(page)->pp, 3348 page, 0, false); 3349 } 3350 3351 txq->tx_buf[i].buf_p = NULL; 3352 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3353 } 3354 } 3355 } 3356 3357 static void fec_enet_free_queue(struct net_device *ndev) 3358 { 3359 struct fec_enet_private *fep = netdev_priv(ndev); 3360 int i; 3361 struct fec_enet_priv_tx_q *txq; 3362 3363 for (i = 0; i < fep->num_tx_queues; i++) 3364 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 3365 txq = fep->tx_queue[i]; 3366 fec_dma_free(&fep->pdev->dev, 3367 txq->bd.ring_size * TSO_HEADER_SIZE, 3368 txq->tso_hdrs, txq->tso_hdrs_dma); 3369 } 3370 3371 for (i = 0; i < fep->num_rx_queues; i++) 3372 kfree(fep->rx_queue[i]); 3373 for (i = 0; i < fep->num_tx_queues; i++) 3374 kfree(fep->tx_queue[i]); 3375 } 3376 3377 static int fec_enet_alloc_queue(struct net_device *ndev) 3378 { 3379 struct fec_enet_private *fep = netdev_priv(ndev); 3380 int i; 3381 int ret = 0; 3382 struct fec_enet_priv_tx_q *txq; 3383 3384 for (i = 0; i < fep->num_tx_queues; i++) { 3385 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 3386 if (!txq) { 3387 ret = -ENOMEM; 3388 goto alloc_failed; 3389 } 3390 3391 fep->tx_queue[i] = txq; 3392 txq->bd.ring_size = TX_RING_SIZE; 3393 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 3394 3395 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 3396 txq->tx_wake_threshold = FEC_MAX_SKB_DESCS + 2 * MAX_SKB_FRAGS; 3397 3398 txq->tso_hdrs = fec_dma_alloc(&fep->pdev->dev, 3399 txq->bd.ring_size * TSO_HEADER_SIZE, 3400 &txq->tso_hdrs_dma, GFP_KERNEL); 3401 if (!txq->tso_hdrs) { 3402 ret = -ENOMEM; 3403 goto alloc_failed; 3404 } 3405 } 3406 3407 for (i = 0; i < fep->num_rx_queues; i++) { 3408 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 3409 GFP_KERNEL); 3410 if (!fep->rx_queue[i]) { 3411 ret = -ENOMEM; 3412 goto alloc_failed; 3413 } 3414 3415 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 3416 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 3417 } 3418 return ret; 3419 3420 alloc_failed: 3421 fec_enet_free_queue(ndev); 3422 return ret; 3423 } 3424 3425 static int 3426 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 3427 { 3428 struct fec_enet_private *fep = netdev_priv(ndev); 3429 struct fec_enet_priv_rx_q *rxq; 3430 dma_addr_t phys_addr; 3431 struct bufdesc *bdp; 3432 struct page *page; 3433 int i, err; 3434 3435 rxq = fep->rx_queue[queue]; 3436 bdp = rxq->bd.base; 3437 3438 err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size); 3439 if (err < 0) { 3440 netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err); 3441 return err; 3442 } 3443 3444 /* Some platforms require the RX buffer must be 64 bytes alignment. 3445 * Some platforms require 16 bytes alignment. And some platforms 3446 * require 4 bytes alignment. But since the page pool have been 3447 * introduced into the driver, the address of RX buffer is always 3448 * the page address plus FEC_ENET_XDP_HEADROOM, and 3449 * FEC_ENET_XDP_HEADROOM is 256 bytes. Therefore, this address can 3450 * satisfy all platforms. To prevent future modifications to 3451 * FEC_ENET_XDP_HEADROOM from ignoring this hardware limitation, a 3452 * BUILD_BUG_ON() test has been added, which ensures that 3453 * FEC_ENET_XDP_HEADROOM provides the required alignment. 3454 */ 3455 BUILD_BUG_ON(FEC_ENET_XDP_HEADROOM & 0x3f); 3456 3457 for (i = 0; i < rxq->bd.ring_size; i++) { 3458 page = page_pool_dev_alloc_pages(rxq->page_pool); 3459 if (!page) 3460 goto err_alloc; 3461 3462 phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM; 3463 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 3464 3465 rxq->rx_buf[i] = page; 3466 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3467 3468 if (fep->bufdesc_ex) { 3469 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3470 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 3471 } 3472 3473 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3474 } 3475 3476 /* Set the last buffer to wrap. */ 3477 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3478 bdp->cbd_sc |= cpu_to_fec16(BD_ENET_RX_WRAP); 3479 return 0; 3480 3481 err_alloc: 3482 fec_enet_free_buffers(ndev); 3483 return -ENOMEM; 3484 } 3485 3486 static int 3487 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 3488 { 3489 struct fec_enet_private *fep = netdev_priv(ndev); 3490 unsigned int i; 3491 struct bufdesc *bdp; 3492 struct fec_enet_priv_tx_q *txq; 3493 3494 txq = fep->tx_queue[queue]; 3495 bdp = txq->bd.base; 3496 for (i = 0; i < txq->bd.ring_size; i++) { 3497 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 3498 if (!txq->tx_bounce[i]) 3499 goto err_alloc; 3500 3501 bdp->cbd_sc = cpu_to_fec16(0); 3502 bdp->cbd_bufaddr = cpu_to_fec32(0); 3503 3504 if (fep->bufdesc_ex) { 3505 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3506 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 3507 } 3508 3509 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3510 } 3511 3512 /* Set the last buffer to wrap. */ 3513 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3514 bdp->cbd_sc |= cpu_to_fec16(BD_ENET_TX_WRAP); 3515 3516 return 0; 3517 3518 err_alloc: 3519 fec_enet_free_buffers(ndev); 3520 return -ENOMEM; 3521 } 3522 3523 static int fec_enet_alloc_buffers(struct net_device *ndev) 3524 { 3525 struct fec_enet_private *fep = netdev_priv(ndev); 3526 unsigned int i; 3527 3528 for (i = 0; i < fep->num_rx_queues; i++) 3529 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3530 return -ENOMEM; 3531 3532 for (i = 0; i < fep->num_tx_queues; i++) 3533 if (fec_enet_alloc_txq_buffers(ndev, i)) 3534 return -ENOMEM; 3535 return 0; 3536 } 3537 3538 static int 3539 fec_enet_open(struct net_device *ndev) 3540 { 3541 struct fec_enet_private *fep = netdev_priv(ndev); 3542 int ret; 3543 bool reset_again; 3544 3545 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3546 if (ret < 0) 3547 return ret; 3548 3549 pinctrl_pm_select_default_state(&fep->pdev->dev); 3550 ret = fec_enet_clk_enable(ndev, true); 3551 if (ret) 3552 goto clk_enable; 3553 3554 /* During the first fec_enet_open call the PHY isn't probed at this 3555 * point. Therefore the phy_reset_after_clk_enable() call within 3556 * fec_enet_clk_enable() fails. As we need this reset in order to be 3557 * sure the PHY is working correctly we check if we need to reset again 3558 * later when the PHY is probed 3559 */ 3560 if (ndev->phydev && ndev->phydev->drv) 3561 reset_again = false; 3562 else 3563 reset_again = true; 3564 3565 /* I should reset the ring buffers here, but I don't yet know 3566 * a simple way to do that. 3567 */ 3568 3569 ret = fec_enet_alloc_buffers(ndev); 3570 if (ret) 3571 goto err_enet_alloc; 3572 3573 /* Init MAC prior to mii bus probe */ 3574 fec_restart(ndev); 3575 3576 /* Call phy_reset_after_clk_enable() again if it failed during 3577 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3578 */ 3579 if (reset_again) 3580 fec_enet_phy_reset_after_clk_enable(ndev); 3581 3582 /* Probe and connect to PHY when open the interface */ 3583 ret = fec_enet_mii_probe(ndev); 3584 if (ret) 3585 goto err_enet_mii_probe; 3586 3587 if (fep->quirks & FEC_QUIRK_ERR006687) 3588 imx6q_cpuidle_fec_irqs_used(); 3589 3590 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3591 cpu_latency_qos_add_request(&fep->pm_qos_req, 0); 3592 3593 napi_enable(&fep->napi); 3594 phy_start(ndev->phydev); 3595 netif_tx_start_all_queues(ndev); 3596 3597 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3598 FEC_WOL_FLAG_ENABLE); 3599 3600 return 0; 3601 3602 err_enet_mii_probe: 3603 fec_enet_free_buffers(ndev); 3604 err_enet_alloc: 3605 fec_enet_clk_enable(ndev, false); 3606 clk_enable: 3607 pm_runtime_put_autosuspend(&fep->pdev->dev); 3608 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3609 return ret; 3610 } 3611 3612 static int 3613 fec_enet_close(struct net_device *ndev) 3614 { 3615 struct fec_enet_private *fep = netdev_priv(ndev); 3616 struct phy_device *phy_dev = ndev->phydev; 3617 3618 phy_stop(phy_dev); 3619 3620 if (netif_device_present(ndev)) { 3621 napi_disable(&fep->napi); 3622 netif_tx_disable(ndev); 3623 fec_stop(ndev); 3624 } 3625 3626 phy_disconnect(phy_dev); 3627 3628 if (!fep->phy_node && phy_is_pseudo_fixed_link(phy_dev)) 3629 fixed_phy_unregister(phy_dev); 3630 3631 if (fep->quirks & FEC_QUIRK_ERR006687) 3632 imx6q_cpuidle_fec_irqs_unused(); 3633 3634 fec_enet_update_ethtool_stats(ndev); 3635 3636 fec_enet_clk_enable(ndev, false); 3637 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3638 cpu_latency_qos_remove_request(&fep->pm_qos_req); 3639 3640 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3641 pm_runtime_put_autosuspend(&fep->pdev->dev); 3642 3643 fec_enet_free_buffers(ndev); 3644 3645 return 0; 3646 } 3647 3648 /* Set or clear the multicast filter for this adaptor. 3649 * Skeleton taken from sunlance driver. 3650 * The CPM Ethernet implementation allows Multicast as well as individual 3651 * MAC address filtering. Some of the drivers check to make sure it is 3652 * a group multicast address, and discard those that are not. I guess I 3653 * will do the same for now, but just remove the test if you want 3654 * individual filtering as well (do the upper net layers want or support 3655 * this kind of feature?). 3656 */ 3657 3658 #define FEC_HASH_BITS 6 /* #bits in hash */ 3659 3660 static void set_multicast_list(struct net_device *ndev) 3661 { 3662 struct fec_enet_private *fep = netdev_priv(ndev); 3663 struct netdev_hw_addr *ha; 3664 unsigned int crc, tmp; 3665 unsigned char hash; 3666 unsigned int hash_high = 0, hash_low = 0; 3667 3668 if (ndev->flags & IFF_PROMISC) { 3669 tmp = readl(fep->hwp + FEC_R_CNTRL); 3670 tmp |= 0x8; 3671 writel(tmp, fep->hwp + FEC_R_CNTRL); 3672 return; 3673 } 3674 3675 tmp = readl(fep->hwp + FEC_R_CNTRL); 3676 tmp &= ~0x8; 3677 writel(tmp, fep->hwp + FEC_R_CNTRL); 3678 3679 if (ndev->flags & IFF_ALLMULTI) { 3680 /* Catch all multicast addresses, so set the 3681 * filter to all 1's 3682 */ 3683 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3684 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3685 3686 return; 3687 } 3688 3689 /* Add the addresses in hash register */ 3690 netdev_for_each_mc_addr(ha, ndev) { 3691 /* calculate crc32 value of mac address */ 3692 crc = ether_crc_le(ndev->addr_len, ha->addr); 3693 3694 /* only upper 6 bits (FEC_HASH_BITS) are used 3695 * which point to specific bit in the hash registers 3696 */ 3697 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3698 3699 if (hash > 31) 3700 hash_high |= 1 << (hash - 32); 3701 else 3702 hash_low |= 1 << hash; 3703 } 3704 3705 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3706 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3707 } 3708 3709 /* Set a MAC change in hardware. */ 3710 static int 3711 fec_set_mac_address(struct net_device *ndev, void *p) 3712 { 3713 struct sockaddr *addr = p; 3714 3715 if (addr) { 3716 if (!is_valid_ether_addr(addr->sa_data)) 3717 return -EADDRNOTAVAIL; 3718 eth_hw_addr_set(ndev, addr->sa_data); 3719 } 3720 3721 /* Add netif status check here to avoid system hang in below case: 3722 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3723 * After ethx down, fec all clocks are gated off and then register 3724 * access causes system hang. 3725 */ 3726 if (!netif_running(ndev)) 3727 return 0; 3728 3729 fec_set_hw_mac_addr(ndev); 3730 3731 return 0; 3732 } 3733 3734 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3735 netdev_features_t features) 3736 { 3737 struct fec_enet_private *fep = netdev_priv(netdev); 3738 netdev_features_t changed = features ^ netdev->features; 3739 3740 netdev->features = features; 3741 3742 /* Receive checksum has been changed */ 3743 if (changed & NETIF_F_RXCSUM) { 3744 if (features & NETIF_F_RXCSUM) 3745 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3746 else 3747 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3748 } 3749 } 3750 3751 static int fec_set_features(struct net_device *netdev, 3752 netdev_features_t features) 3753 { 3754 struct fec_enet_private *fep = netdev_priv(netdev); 3755 netdev_features_t changed = features ^ netdev->features; 3756 3757 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3758 napi_disable(&fep->napi); 3759 netif_tx_lock_bh(netdev); 3760 fec_stop(netdev); 3761 fec_enet_set_netdev_features(netdev, features); 3762 fec_restart(netdev); 3763 netif_tx_wake_all_queues(netdev); 3764 netif_tx_unlock_bh(netdev); 3765 napi_enable(&fep->napi); 3766 } else { 3767 fec_enet_set_netdev_features(netdev, features); 3768 } 3769 3770 return 0; 3771 } 3772 3773 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3774 struct net_device *sb_dev) 3775 { 3776 struct fec_enet_private *fep = netdev_priv(ndev); 3777 u16 vlan_tag = 0; 3778 3779 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3780 return netdev_pick_tx(ndev, skb, NULL); 3781 3782 /* VLAN is present in the payload.*/ 3783 if (eth_type_vlan(skb->protocol)) { 3784 struct vlan_ethhdr *vhdr = skb_vlan_eth_hdr(skb); 3785 3786 vlan_tag = ntohs(vhdr->h_vlan_TCI); 3787 /* VLAN is present in the skb but not yet pushed in the payload.*/ 3788 } else if (skb_vlan_tag_present(skb)) { 3789 vlan_tag = skb->vlan_tci; 3790 } else { 3791 return vlan_tag; 3792 } 3793 3794 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3795 } 3796 3797 static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf) 3798 { 3799 struct fec_enet_private *fep = netdev_priv(dev); 3800 bool is_run = netif_running(dev); 3801 struct bpf_prog *old_prog; 3802 3803 switch (bpf->command) { 3804 case XDP_SETUP_PROG: 3805 /* No need to support the SoCs that require to 3806 * do the frame swap because the performance wouldn't be 3807 * better than the skb mode. 3808 */ 3809 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 3810 return -EOPNOTSUPP; 3811 3812 if (!bpf->prog) 3813 xdp_features_clear_redirect_target(dev); 3814 3815 if (is_run) { 3816 napi_disable(&fep->napi); 3817 netif_tx_disable(dev); 3818 } 3819 3820 old_prog = xchg(&fep->xdp_prog, bpf->prog); 3821 if (old_prog) 3822 bpf_prog_put(old_prog); 3823 3824 fec_restart(dev); 3825 3826 if (is_run) { 3827 napi_enable(&fep->napi); 3828 netif_tx_start_all_queues(dev); 3829 } 3830 3831 if (bpf->prog) 3832 xdp_features_set_redirect_target(dev, false); 3833 3834 return 0; 3835 3836 case XDP_SETUP_XSK_POOL: 3837 return -EOPNOTSUPP; 3838 3839 default: 3840 return -EOPNOTSUPP; 3841 } 3842 } 3843 3844 static int 3845 fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index) 3846 { 3847 if (unlikely(index < 0)) 3848 return 0; 3849 3850 return (index % fep->num_tx_queues); 3851 } 3852 3853 static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep, 3854 struct fec_enet_priv_tx_q *txq, 3855 void *frame, u32 dma_sync_len, 3856 bool ndo_xmit) 3857 { 3858 unsigned int index, status, estatus; 3859 struct bufdesc *bdp; 3860 dma_addr_t dma_addr; 3861 int entries_free; 3862 u16 frame_len; 3863 3864 entries_free = fec_enet_get_free_txdesc_num(txq); 3865 if (entries_free < MAX_SKB_FRAGS + 1) { 3866 netdev_err_once(fep->netdev, "NOT enough BD for SG!\n"); 3867 return -EBUSY; 3868 } 3869 3870 /* Fill in a Tx ring entry */ 3871 bdp = txq->bd.cur; 3872 status = fec16_to_cpu(bdp->cbd_sc); 3873 status &= ~BD_ENET_TX_STATS; 3874 3875 index = fec_enet_get_bd_index(bdp, &txq->bd); 3876 3877 if (ndo_xmit) { 3878 struct xdp_frame *xdpf = frame; 3879 3880 dma_addr = dma_map_single(&fep->pdev->dev, xdpf->data, 3881 xdpf->len, DMA_TO_DEVICE); 3882 if (dma_mapping_error(&fep->pdev->dev, dma_addr)) 3883 return -ENOMEM; 3884 3885 frame_len = xdpf->len; 3886 txq->tx_buf[index].buf_p = xdpf; 3887 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_NDO; 3888 } else { 3889 struct xdp_buff *xdpb = frame; 3890 struct page *page; 3891 3892 page = virt_to_page(xdpb->data); 3893 dma_addr = page_pool_get_dma_addr(page) + 3894 (xdpb->data - xdpb->data_hard_start); 3895 dma_sync_single_for_device(&fep->pdev->dev, dma_addr, 3896 dma_sync_len, DMA_BIDIRECTIONAL); 3897 frame_len = xdpb->data_end - xdpb->data; 3898 txq->tx_buf[index].buf_p = page; 3899 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_TX; 3900 } 3901 3902 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 3903 if (fep->bufdesc_ex) 3904 estatus = BD_ENET_TX_INT; 3905 3906 bdp->cbd_bufaddr = cpu_to_fec32(dma_addr); 3907 bdp->cbd_datlen = cpu_to_fec16(frame_len); 3908 3909 if (fep->bufdesc_ex) { 3910 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3911 3912 if (fep->quirks & FEC_QUIRK_HAS_AVB) 3913 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 3914 3915 ebdp->cbd_bdu = 0; 3916 ebdp->cbd_esc = cpu_to_fec32(estatus); 3917 } 3918 3919 /* Make sure the updates to rest of the descriptor are performed before 3920 * transferring ownership. 3921 */ 3922 dma_wmb(); 3923 3924 /* Send it on its way. Tell FEC it's ready, interrupt when done, 3925 * it's the last BD of the frame, and to put the CRC on the end. 3926 */ 3927 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 3928 bdp->cbd_sc = cpu_to_fec16(status); 3929 3930 /* If this was the last BD in the ring, start at the beginning again. */ 3931 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3932 3933 /* Make sure the update to bdp are performed before txq->bd.cur. */ 3934 dma_wmb(); 3935 3936 txq->bd.cur = bdp; 3937 3938 /* Trigger transmission start */ 3939 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 3940 !readl(txq->bd.reg_desc_active) || 3941 !readl(txq->bd.reg_desc_active) || 3942 !readl(txq->bd.reg_desc_active) || 3943 !readl(txq->bd.reg_desc_active)) 3944 writel(0, txq->bd.reg_desc_active); 3945 3946 return 0; 3947 } 3948 3949 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 3950 int cpu, struct xdp_buff *xdp, 3951 u32 dma_sync_len) 3952 { 3953 struct fec_enet_priv_tx_q *txq; 3954 struct netdev_queue *nq; 3955 int queue, ret; 3956 3957 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3958 txq = fep->tx_queue[queue]; 3959 nq = netdev_get_tx_queue(fep->netdev, queue); 3960 3961 __netif_tx_lock(nq, cpu); 3962 3963 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3964 txq_trans_cond_update(nq); 3965 ret = fec_enet_txq_xmit_frame(fep, txq, xdp, dma_sync_len, false); 3966 3967 __netif_tx_unlock(nq); 3968 3969 return ret; 3970 } 3971 3972 static int fec_enet_xdp_xmit(struct net_device *dev, 3973 int num_frames, 3974 struct xdp_frame **frames, 3975 u32 flags) 3976 { 3977 struct fec_enet_private *fep = netdev_priv(dev); 3978 struct fec_enet_priv_tx_q *txq; 3979 int cpu = smp_processor_id(); 3980 unsigned int sent_frames = 0; 3981 struct netdev_queue *nq; 3982 unsigned int queue; 3983 int i; 3984 3985 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3986 txq = fep->tx_queue[queue]; 3987 nq = netdev_get_tx_queue(fep->netdev, queue); 3988 3989 __netif_tx_lock(nq, cpu); 3990 3991 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3992 txq_trans_cond_update(nq); 3993 for (i = 0; i < num_frames; i++) { 3994 if (fec_enet_txq_xmit_frame(fep, txq, frames[i], 0, true) < 0) 3995 break; 3996 sent_frames++; 3997 } 3998 3999 __netif_tx_unlock(nq); 4000 4001 return sent_frames; 4002 } 4003 4004 static int fec_hwtstamp_get(struct net_device *ndev, 4005 struct kernel_hwtstamp_config *config) 4006 { 4007 struct fec_enet_private *fep = netdev_priv(ndev); 4008 4009 if (!netif_running(ndev)) 4010 return -EINVAL; 4011 4012 if (!fep->bufdesc_ex) 4013 return -EOPNOTSUPP; 4014 4015 fec_ptp_get(ndev, config); 4016 4017 return 0; 4018 } 4019 4020 static int fec_hwtstamp_set(struct net_device *ndev, 4021 struct kernel_hwtstamp_config *config, 4022 struct netlink_ext_ack *extack) 4023 { 4024 struct fec_enet_private *fep = netdev_priv(ndev); 4025 4026 if (!netif_running(ndev)) 4027 return -EINVAL; 4028 4029 if (!fep->bufdesc_ex) 4030 return -EOPNOTSUPP; 4031 4032 return fec_ptp_set(ndev, config, extack); 4033 } 4034 4035 static int fec_change_mtu(struct net_device *ndev, int new_mtu) 4036 { 4037 struct fec_enet_private *fep = netdev_priv(ndev); 4038 int order; 4039 4040 if (netif_running(ndev)) 4041 return -EBUSY; 4042 4043 order = get_order(new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN 4044 + FEC_DRV_RESERVE_SPACE); 4045 fep->rx_frame_size = (PAGE_SIZE << order) - FEC_DRV_RESERVE_SPACE; 4046 fep->pagepool_order = order; 4047 WRITE_ONCE(ndev->mtu, new_mtu); 4048 4049 return 0; 4050 } 4051 4052 static const struct net_device_ops fec_netdev_ops = { 4053 .ndo_open = fec_enet_open, 4054 .ndo_stop = fec_enet_close, 4055 .ndo_start_xmit = fec_enet_start_xmit, 4056 .ndo_select_queue = fec_enet_select_queue, 4057 .ndo_set_rx_mode = set_multicast_list, 4058 .ndo_validate_addr = eth_validate_addr, 4059 .ndo_tx_timeout = fec_timeout, 4060 .ndo_set_mac_address = fec_set_mac_address, 4061 .ndo_change_mtu = fec_change_mtu, 4062 .ndo_eth_ioctl = phy_do_ioctl_running, 4063 .ndo_set_features = fec_set_features, 4064 .ndo_bpf = fec_enet_bpf, 4065 .ndo_xdp_xmit = fec_enet_xdp_xmit, 4066 .ndo_hwtstamp_get = fec_hwtstamp_get, 4067 .ndo_hwtstamp_set = fec_hwtstamp_set, 4068 }; 4069 4070 static const unsigned short offset_des_active_rxq[] = { 4071 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 4072 }; 4073 4074 static const unsigned short offset_des_active_txq[] = { 4075 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 4076 }; 4077 4078 /* 4079 * XXX: We need to clean up on failure exits here. 4080 * 4081 */ 4082 static int fec_enet_init(struct net_device *ndev) 4083 { 4084 struct fec_enet_private *fep = netdev_priv(ndev); 4085 struct bufdesc *cbd_base; 4086 dma_addr_t bd_dma; 4087 int bd_size; 4088 unsigned int i; 4089 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 4090 sizeof(struct bufdesc); 4091 unsigned dsize_log2 = __fls(dsize); 4092 int ret; 4093 4094 WARN_ON(dsize != (1 << dsize_log2)); 4095 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 4096 fep->tx_align = 0xf; 4097 #else 4098 fep->tx_align = 0x3; 4099 #endif 4100 fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4101 fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4102 fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT; 4103 fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT; 4104 4105 /* Check mask of the streaming and coherent API */ 4106 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 4107 if (ret < 0) { 4108 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 4109 return ret; 4110 } 4111 4112 ret = fec_enet_alloc_queue(ndev); 4113 if (ret) 4114 return ret; 4115 4116 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 4117 4118 /* Allocate memory for buffer descriptors. */ 4119 cbd_base = fec_dmam_alloc(&fep->pdev->dev, bd_size, &bd_dma, 4120 GFP_KERNEL); 4121 if (!cbd_base) { 4122 ret = -ENOMEM; 4123 goto free_queue_mem; 4124 } 4125 4126 /* Get the Ethernet address */ 4127 ret = fec_get_mac(ndev); 4128 if (ret) 4129 goto free_queue_mem; 4130 4131 /* Set receive and transmit descriptor base. */ 4132 for (i = 0; i < fep->num_rx_queues; i++) { 4133 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 4134 unsigned size = dsize * rxq->bd.ring_size; 4135 4136 rxq->bd.qid = i; 4137 rxq->bd.base = cbd_base; 4138 rxq->bd.cur = cbd_base; 4139 rxq->bd.dma = bd_dma; 4140 rxq->bd.dsize = dsize; 4141 rxq->bd.dsize_log2 = dsize_log2; 4142 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 4143 bd_dma += size; 4144 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4145 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4146 } 4147 4148 for (i = 0; i < fep->num_tx_queues; i++) { 4149 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 4150 unsigned size = dsize * txq->bd.ring_size; 4151 4152 txq->bd.qid = i; 4153 txq->bd.base = cbd_base; 4154 txq->bd.cur = cbd_base; 4155 txq->bd.dma = bd_dma; 4156 txq->bd.dsize = dsize; 4157 txq->bd.dsize_log2 = dsize_log2; 4158 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 4159 bd_dma += size; 4160 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4161 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4162 } 4163 4164 4165 /* The FEC Ethernet specific entries in the device structure */ 4166 ndev->watchdog_timeo = TX_TIMEOUT; 4167 ndev->netdev_ops = &fec_netdev_ops; 4168 ndev->ethtool_ops = &fec_enet_ethtool_ops; 4169 4170 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 4171 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi); 4172 4173 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 4174 /* enable hw VLAN support */ 4175 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 4176 4177 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 4178 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS); 4179 4180 /* enable hw accelerator */ 4181 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 4182 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 4183 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 4184 } 4185 4186 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) 4187 fep->tx_align = 0; 4188 4189 ndev->hw_features = ndev->features; 4190 4191 if (!(fep->quirks & FEC_QUIRK_SWAP_FRAME)) 4192 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 4193 NETDEV_XDP_ACT_REDIRECT; 4194 4195 fec_restart(ndev); 4196 4197 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 4198 fec_enet_clear_ethtool_stats(ndev); 4199 else 4200 fec_enet_update_ethtool_stats(ndev); 4201 4202 return 0; 4203 4204 free_queue_mem: 4205 fec_enet_free_queue(ndev); 4206 return ret; 4207 } 4208 4209 static void fec_enet_deinit(struct net_device *ndev) 4210 { 4211 struct fec_enet_private *fep = netdev_priv(ndev); 4212 4213 netif_napi_del(&fep->napi); 4214 fec_enet_free_queue(ndev); 4215 } 4216 4217 #ifdef CONFIG_OF 4218 static int fec_reset_phy(struct platform_device *pdev) 4219 { 4220 struct gpio_desc *phy_reset; 4221 int msec = 1, phy_post_delay = 0; 4222 struct device_node *np = pdev->dev.of_node; 4223 int err; 4224 4225 if (!np) 4226 return 0; 4227 4228 err = of_property_read_u32(np, "phy-reset-duration", &msec); 4229 /* A sane reset duration should not be longer than 1s */ 4230 if (!err && msec > 1000) 4231 msec = 1; 4232 4233 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 4234 /* valid reset duration should be less than 1s */ 4235 if (!err && phy_post_delay > 1000) 4236 return -EINVAL; 4237 4238 phy_reset = devm_gpiod_get_optional(&pdev->dev, "phy-reset", 4239 GPIOD_OUT_HIGH); 4240 if (IS_ERR(phy_reset)) 4241 return dev_err_probe(&pdev->dev, PTR_ERR(phy_reset), 4242 "failed to get phy-reset-gpios\n"); 4243 4244 if (!phy_reset) 4245 return 0; 4246 4247 if (msec > 20) 4248 msleep(msec); 4249 else 4250 usleep_range(msec * 1000, msec * 1000 + 1000); 4251 4252 gpiod_set_value_cansleep(phy_reset, 0); 4253 4254 if (!phy_post_delay) 4255 return 0; 4256 4257 if (phy_post_delay > 20) 4258 msleep(phy_post_delay); 4259 else 4260 usleep_range(phy_post_delay * 1000, 4261 phy_post_delay * 1000 + 1000); 4262 4263 return 0; 4264 } 4265 #else /* CONFIG_OF */ 4266 static int fec_reset_phy(struct platform_device *pdev) 4267 { 4268 /* 4269 * In case of platform probe, the reset has been done 4270 * by machine code. 4271 */ 4272 return 0; 4273 } 4274 #endif /* CONFIG_OF */ 4275 4276 static void 4277 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 4278 { 4279 struct device_node *np = pdev->dev.of_node; 4280 4281 *num_tx = *num_rx = 1; 4282 4283 if (!np || !of_device_is_available(np)) 4284 return; 4285 4286 /* parse the num of tx and rx queues */ 4287 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 4288 4289 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 4290 4291 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 4292 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 4293 *num_tx); 4294 *num_tx = 1; 4295 return; 4296 } 4297 4298 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 4299 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 4300 *num_rx); 4301 *num_rx = 1; 4302 return; 4303 } 4304 4305 } 4306 4307 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 4308 { 4309 int irq_cnt = platform_irq_count(pdev); 4310 4311 if (irq_cnt > FEC_IRQ_NUM) 4312 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 4313 else if (irq_cnt == 2) 4314 irq_cnt = 1; /* last for pps */ 4315 else if (irq_cnt <= 0) 4316 irq_cnt = 1; /* At least 1 irq is needed */ 4317 return irq_cnt; 4318 } 4319 4320 static void fec_enet_get_wakeup_irq(struct platform_device *pdev) 4321 { 4322 struct net_device *ndev = platform_get_drvdata(pdev); 4323 struct fec_enet_private *fep = netdev_priv(ndev); 4324 4325 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) 4326 fep->wake_irq = fep->irq[2]; 4327 else 4328 fep->wake_irq = fep->irq[0]; 4329 } 4330 4331 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 4332 struct device_node *np) 4333 { 4334 struct device_node *gpr_np; 4335 u32 out_val[3]; 4336 int ret = 0; 4337 4338 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 4339 if (!gpr_np) 4340 return 0; 4341 4342 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 4343 ARRAY_SIZE(out_val)); 4344 if (ret) { 4345 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 4346 goto out; 4347 } 4348 4349 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 4350 if (IS_ERR(fep->stop_gpr.gpr)) { 4351 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 4352 ret = PTR_ERR(fep->stop_gpr.gpr); 4353 fep->stop_gpr.gpr = NULL; 4354 goto out; 4355 } 4356 4357 fep->stop_gpr.reg = out_val[1]; 4358 fep->stop_gpr.bit = out_val[2]; 4359 4360 out: 4361 of_node_put(gpr_np); 4362 4363 return ret; 4364 } 4365 4366 static int 4367 fec_probe(struct platform_device *pdev) 4368 { 4369 struct fec_enet_private *fep; 4370 struct fec_platform_data *pdata; 4371 phy_interface_t interface; 4372 struct net_device *ndev; 4373 int i, irq, ret = 0; 4374 static int dev_id; 4375 struct device_node *np = pdev->dev.of_node, *phy_node; 4376 int num_tx_qs; 4377 int num_rx_qs; 4378 char irq_name[8]; 4379 int irq_cnt; 4380 const struct fec_devinfo *dev_info; 4381 4382 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 4383 4384 /* Init network device */ 4385 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 4386 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 4387 if (!ndev) 4388 return -ENOMEM; 4389 4390 SET_NETDEV_DEV(ndev, &pdev->dev); 4391 4392 /* setup board info structure */ 4393 fep = netdev_priv(ndev); 4394 4395 dev_info = device_get_match_data(&pdev->dev); 4396 if (!dev_info) 4397 dev_info = (const struct fec_devinfo *)pdev->id_entry->driver_data; 4398 if (dev_info) 4399 fep->quirks = dev_info->quirks; 4400 4401 fep->netdev = ndev; 4402 fep->num_rx_queues = num_rx_qs; 4403 fep->num_tx_queues = num_tx_qs; 4404 4405 /* default enable pause frame auto negotiation */ 4406 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 4407 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 4408 4409 /* Select default pin state */ 4410 pinctrl_pm_select_default_state(&pdev->dev); 4411 4412 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 4413 if (IS_ERR(fep->hwp)) { 4414 ret = PTR_ERR(fep->hwp); 4415 goto failed_ioremap; 4416 } 4417 4418 fep->pdev = pdev; 4419 fep->dev_id = dev_id++; 4420 4421 platform_set_drvdata(pdev, ndev); 4422 4423 if ((of_machine_is_compatible("fsl,imx6q") || 4424 of_machine_is_compatible("fsl,imx6dl")) && 4425 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 4426 fep->quirks |= FEC_QUIRK_ERR006687; 4427 4428 ret = fec_enet_ipc_handle_init(fep); 4429 if (ret) 4430 goto failed_ipc_init; 4431 4432 if (of_property_read_bool(np, "fsl,magic-packet")) 4433 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 4434 4435 ret = fec_enet_init_stop_mode(fep, np); 4436 if (ret) 4437 goto failed_stop_mode; 4438 4439 phy_node = of_parse_phandle(np, "phy-handle", 0); 4440 if (!phy_node && of_phy_is_fixed_link(np)) { 4441 ret = of_phy_register_fixed_link(np); 4442 if (ret < 0) { 4443 dev_err(&pdev->dev, 4444 "broken fixed-link specification\n"); 4445 goto failed_phy; 4446 } 4447 phy_node = of_node_get(np); 4448 } 4449 fep->phy_node = phy_node; 4450 4451 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 4452 if (ret) { 4453 pdata = dev_get_platdata(&pdev->dev); 4454 if (pdata) 4455 fep->phy_interface = pdata->phy; 4456 else 4457 fep->phy_interface = PHY_INTERFACE_MODE_MII; 4458 } else { 4459 fep->phy_interface = interface; 4460 } 4461 4462 ret = fec_enet_parse_rgmii_delay(fep, np); 4463 if (ret) 4464 goto failed_rgmii_delay; 4465 4466 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 4467 if (IS_ERR(fep->clk_ipg)) { 4468 ret = PTR_ERR(fep->clk_ipg); 4469 goto failed_clk; 4470 } 4471 4472 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 4473 if (IS_ERR(fep->clk_ahb)) { 4474 ret = PTR_ERR(fep->clk_ahb); 4475 goto failed_clk; 4476 } 4477 4478 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 4479 4480 /* enet_out is optional, depends on board */ 4481 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out"); 4482 if (IS_ERR(fep->clk_enet_out)) { 4483 ret = PTR_ERR(fep->clk_enet_out); 4484 goto failed_clk; 4485 } 4486 4487 fep->ptp_clk_on = false; 4488 mutex_init(&fep->ptp_clk_mutex); 4489 4490 /* clk_ref is optional, depends on board */ 4491 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref"); 4492 if (IS_ERR(fep->clk_ref)) { 4493 ret = PTR_ERR(fep->clk_ref); 4494 goto failed_clk; 4495 } 4496 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); 4497 4498 /* clk_2x_txclk is optional, depends on board */ 4499 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { 4500 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); 4501 if (IS_ERR(fep->clk_2x_txclk)) 4502 fep->clk_2x_txclk = NULL; 4503 } 4504 4505 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 4506 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 4507 if (IS_ERR(fep->clk_ptp)) { 4508 fep->clk_ptp = NULL; 4509 fep->bufdesc_ex = false; 4510 } 4511 4512 ret = fec_enet_clk_enable(ndev, true); 4513 if (ret) 4514 goto failed_clk; 4515 4516 ret = clk_prepare_enable(fep->clk_ipg); 4517 if (ret) 4518 goto failed_clk_ipg; 4519 ret = clk_prepare_enable(fep->clk_ahb); 4520 if (ret) 4521 goto failed_clk_ahb; 4522 4523 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 4524 if (!IS_ERR(fep->reg_phy)) { 4525 ret = regulator_enable(fep->reg_phy); 4526 if (ret) { 4527 dev_err(&pdev->dev, 4528 "Failed to enable phy regulator: %d\n", ret); 4529 goto failed_regulator; 4530 } 4531 } else { 4532 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 4533 ret = -EPROBE_DEFER; 4534 goto failed_regulator; 4535 } 4536 fep->reg_phy = NULL; 4537 } 4538 4539 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 4540 pm_runtime_use_autosuspend(&pdev->dev); 4541 pm_runtime_get_noresume(&pdev->dev); 4542 pm_runtime_set_active(&pdev->dev); 4543 pm_runtime_enable(&pdev->dev); 4544 4545 ret = fec_reset_phy(pdev); 4546 if (ret) 4547 goto failed_reset; 4548 4549 irq_cnt = fec_enet_get_irq_cnt(pdev); 4550 if (fep->bufdesc_ex) 4551 fec_ptp_init(pdev, irq_cnt); 4552 4553 ret = fec_enet_init(ndev); 4554 if (ret) 4555 goto failed_init; 4556 4557 for (i = 0; i < irq_cnt; i++) { 4558 snprintf(irq_name, sizeof(irq_name), "int%d", i); 4559 irq = platform_get_irq_byname_optional(pdev, irq_name); 4560 if (irq < 0) 4561 irq = platform_get_irq(pdev, i); 4562 if (irq < 0) { 4563 ret = irq; 4564 goto failed_irq; 4565 } 4566 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 4567 0, pdev->name, ndev); 4568 if (ret) 4569 goto failed_irq; 4570 4571 fep->irq[i] = irq; 4572 } 4573 4574 /* Decide which interrupt line is wakeup capable */ 4575 fec_enet_get_wakeup_irq(pdev); 4576 4577 ret = fec_enet_mii_init(pdev); 4578 if (ret) 4579 goto failed_mii_init; 4580 4581 /* Carrier starts down, phylib will bring it up */ 4582 netif_carrier_off(ndev); 4583 fec_enet_clk_enable(ndev, false); 4584 pinctrl_pm_select_sleep_state(&pdev->dev); 4585 4586 fep->pagepool_order = 0; 4587 fep->rx_frame_size = FEC_ENET_RX_FRSIZE; 4588 4589 if (fep->quirks & FEC_QUIRK_JUMBO_FRAME) 4590 fep->max_buf_size = MAX_JUMBO_BUF_SIZE; 4591 else 4592 fep->max_buf_size = PKT_MAXBUF_SIZE; 4593 4594 ndev->max_mtu = fep->max_buf_size - VLAN_ETH_HLEN - ETH_FCS_LEN; 4595 4596 ret = register_netdev(ndev); 4597 if (ret) 4598 goto failed_register; 4599 4600 device_init_wakeup(&ndev->dev, fep->wol_flag & 4601 FEC_WOL_HAS_MAGIC_PACKET); 4602 4603 if (fep->bufdesc_ex && fep->ptp_clock) 4604 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 4605 4606 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 4607 4608 pm_runtime_put_autosuspend(&pdev->dev); 4609 4610 return 0; 4611 4612 failed_register: 4613 fec_enet_mii_remove(fep); 4614 failed_mii_init: 4615 failed_irq: 4616 fec_enet_deinit(ndev); 4617 failed_init: 4618 fec_ptp_stop(pdev); 4619 failed_reset: 4620 pm_runtime_put_noidle(&pdev->dev); 4621 pm_runtime_disable(&pdev->dev); 4622 if (fep->reg_phy) 4623 regulator_disable(fep->reg_phy); 4624 failed_regulator: 4625 clk_disable_unprepare(fep->clk_ahb); 4626 failed_clk_ahb: 4627 clk_disable_unprepare(fep->clk_ipg); 4628 failed_clk_ipg: 4629 fec_enet_clk_enable(ndev, false); 4630 failed_clk: 4631 failed_rgmii_delay: 4632 if (of_phy_is_fixed_link(np)) 4633 of_phy_deregister_fixed_link(np); 4634 of_node_put(phy_node); 4635 failed_stop_mode: 4636 failed_ipc_init: 4637 failed_phy: 4638 dev_id--; 4639 failed_ioremap: 4640 free_netdev(ndev); 4641 4642 return ret; 4643 } 4644 4645 static void 4646 fec_drv_remove(struct platform_device *pdev) 4647 { 4648 struct net_device *ndev = platform_get_drvdata(pdev); 4649 struct fec_enet_private *fep = netdev_priv(ndev); 4650 struct device_node *np = pdev->dev.of_node; 4651 int ret; 4652 4653 ret = pm_runtime_get_sync(&pdev->dev); 4654 if (ret < 0) 4655 dev_err(&pdev->dev, 4656 "Failed to resume device in remove callback (%pe)\n", 4657 ERR_PTR(ret)); 4658 4659 cancel_work_sync(&fep->tx_timeout_work); 4660 fec_ptp_stop(pdev); 4661 unregister_netdev(ndev); 4662 fec_enet_mii_remove(fep); 4663 if (fep->reg_phy) 4664 regulator_disable(fep->reg_phy); 4665 4666 if (of_phy_is_fixed_link(np)) 4667 of_phy_deregister_fixed_link(np); 4668 of_node_put(fep->phy_node); 4669 4670 /* After pm_runtime_get_sync() failed, the clks are still off, so skip 4671 * disabling them again. 4672 */ 4673 if (ret >= 0) { 4674 clk_disable_unprepare(fep->clk_ahb); 4675 clk_disable_unprepare(fep->clk_ipg); 4676 } 4677 pm_runtime_put_noidle(&pdev->dev); 4678 pm_runtime_disable(&pdev->dev); 4679 4680 fec_enet_deinit(ndev); 4681 free_netdev(ndev); 4682 } 4683 4684 static int fec_suspend(struct device *dev) 4685 { 4686 struct net_device *ndev = dev_get_drvdata(dev); 4687 struct fec_enet_private *fep = netdev_priv(ndev); 4688 int ret; 4689 4690 rtnl_lock(); 4691 if (netif_running(ndev)) { 4692 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 4693 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 4694 phy_stop(ndev->phydev); 4695 napi_disable(&fep->napi); 4696 netif_tx_lock_bh(ndev); 4697 netif_device_detach(ndev); 4698 netif_tx_unlock_bh(ndev); 4699 fec_stop(ndev); 4700 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4701 fec_irqs_disable(ndev); 4702 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 4703 } else { 4704 fec_irqs_disable_except_wakeup(ndev); 4705 if (fep->wake_irq > 0) { 4706 disable_irq(fep->wake_irq); 4707 enable_irq_wake(fep->wake_irq); 4708 } 4709 fec_enet_stop_mode(fep, true); 4710 } 4711 /* It's safe to disable clocks since interrupts are masked */ 4712 fec_enet_clk_enable(ndev, false); 4713 4714 fep->rpm_active = !pm_runtime_status_suspended(dev); 4715 if (fep->rpm_active) { 4716 ret = pm_runtime_force_suspend(dev); 4717 if (ret < 0) { 4718 rtnl_unlock(); 4719 return ret; 4720 } 4721 } 4722 } 4723 rtnl_unlock(); 4724 4725 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4726 regulator_disable(fep->reg_phy); 4727 4728 /* SOC supply clock to phy, when clock is disabled, phy link down 4729 * SOC control phy regulator, when regulator is disabled, phy link down 4730 */ 4731 if (fep->clk_enet_out || fep->reg_phy) 4732 fep->link = 0; 4733 4734 return 0; 4735 } 4736 4737 static int fec_resume(struct device *dev) 4738 { 4739 struct net_device *ndev = dev_get_drvdata(dev); 4740 struct fec_enet_private *fep = netdev_priv(ndev); 4741 int ret; 4742 int val; 4743 4744 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4745 ret = regulator_enable(fep->reg_phy); 4746 if (ret) 4747 return ret; 4748 } 4749 4750 rtnl_lock(); 4751 if (netif_running(ndev)) { 4752 if (fep->rpm_active) 4753 pm_runtime_force_resume(dev); 4754 4755 ret = fec_enet_clk_enable(ndev, true); 4756 if (ret) { 4757 rtnl_unlock(); 4758 goto failed_clk; 4759 } 4760 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 4761 fec_enet_stop_mode(fep, false); 4762 if (fep->wake_irq) { 4763 disable_irq_wake(fep->wake_irq); 4764 enable_irq(fep->wake_irq); 4765 } 4766 4767 val = readl(fep->hwp + FEC_ECNTRL); 4768 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 4769 writel(val, fep->hwp + FEC_ECNTRL); 4770 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 4771 } else { 4772 pinctrl_pm_select_default_state(&fep->pdev->dev); 4773 } 4774 fec_restart(ndev); 4775 netif_tx_lock_bh(ndev); 4776 netif_device_attach(ndev); 4777 netif_tx_unlock_bh(ndev); 4778 napi_enable(&fep->napi); 4779 phy_init_hw(ndev->phydev); 4780 phy_start(ndev->phydev); 4781 } 4782 rtnl_unlock(); 4783 4784 return 0; 4785 4786 failed_clk: 4787 if (fep->reg_phy) 4788 regulator_disable(fep->reg_phy); 4789 return ret; 4790 } 4791 4792 static int fec_runtime_suspend(struct device *dev) 4793 { 4794 struct net_device *ndev = dev_get_drvdata(dev); 4795 struct fec_enet_private *fep = netdev_priv(ndev); 4796 4797 clk_disable_unprepare(fep->clk_ahb); 4798 clk_disable_unprepare(fep->clk_ipg); 4799 4800 return 0; 4801 } 4802 4803 static int fec_runtime_resume(struct device *dev) 4804 { 4805 struct net_device *ndev = dev_get_drvdata(dev); 4806 struct fec_enet_private *fep = netdev_priv(ndev); 4807 int ret; 4808 4809 ret = clk_prepare_enable(fep->clk_ahb); 4810 if (ret) 4811 return ret; 4812 ret = clk_prepare_enable(fep->clk_ipg); 4813 if (ret) 4814 goto failed_clk_ipg; 4815 4816 return 0; 4817 4818 failed_clk_ipg: 4819 clk_disable_unprepare(fep->clk_ahb); 4820 return ret; 4821 } 4822 4823 static const struct dev_pm_ops fec_pm_ops = { 4824 SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 4825 RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 4826 }; 4827 4828 static struct platform_driver fec_driver = { 4829 .driver = { 4830 .name = DRIVER_NAME, 4831 .pm = pm_ptr(&fec_pm_ops), 4832 .of_match_table = fec_dt_ids, 4833 .suppress_bind_attrs = true, 4834 }, 4835 .id_table = fec_devtype, 4836 .probe = fec_probe, 4837 .remove = fec_drv_remove, 4838 }; 4839 4840 module_platform_driver(fec_driver); 4841 4842 MODULE_DESCRIPTION("NXP Fast Ethernet Controller (FEC) driver"); 4843 MODULE_LICENSE("GPL"); 4844