1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/page_pool/helpers.h> 42 #include <net/selftests.h> 43 #include <net/tso.h> 44 #include <linux/tcp.h> 45 #include <linux/udp.h> 46 #include <linux/icmp.h> 47 #include <linux/spinlock.h> 48 #include <linux/workqueue.h> 49 #include <linux/bitops.h> 50 #include <linux/io.h> 51 #include <linux/irq.h> 52 #include <linux/clk.h> 53 #include <linux/crc32.h> 54 #include <linux/platform_device.h> 55 #include <linux/property.h> 56 #include <linux/mdio.h> 57 #include <linux/phy.h> 58 #include <linux/fec.h> 59 #include <linux/of.h> 60 #include <linux/of_mdio.h> 61 #include <linux/of_net.h> 62 #include <linux/regulator/consumer.h> 63 #include <linux/if_vlan.h> 64 #include <linux/pinctrl/consumer.h> 65 #include <linux/gpio/consumer.h> 66 #include <linux/prefetch.h> 67 #include <linux/mfd/syscon.h> 68 #include <linux/regmap.h> 69 #include <soc/imx/cpuidle.h> 70 #include <linux/filter.h> 71 #include <linux/bpf.h> 72 #include <linux/bpf_trace.h> 73 74 #include <asm/cacheflush.h> 75 76 #include "fec.h" 77 78 static void set_multicast_list(struct net_device *ndev); 79 static void fec_enet_itr_coal_set(struct net_device *ndev); 80 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 81 int cpu, struct xdp_buff *xdp, 82 u32 dma_sync_len); 83 84 #define DRIVER_NAME "fec" 85 86 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 87 88 #define FEC_ENET_RSEM_V 0x84 89 #define FEC_ENET_RSFL_V 16 90 #define FEC_ENET_RAEM_V 0x8 91 #define FEC_ENET_RAFL_V 0x8 92 #define FEC_ENET_OPD_V 0xFFF0 93 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 94 95 #define FEC_ENET_XDP_PASS 0 96 #define FEC_ENET_XDP_CONSUMED BIT(0) 97 #define FEC_ENET_XDP_TX BIT(1) 98 #define FEC_ENET_XDP_REDIR BIT(2) 99 100 struct fec_devinfo { 101 u32 quirks; 102 }; 103 104 static const struct fec_devinfo fec_imx25_info = { 105 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 106 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_HAS_MDIO_C45, 107 }; 108 109 static const struct fec_devinfo fec_imx27_info = { 110 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG | 111 FEC_QUIRK_HAS_MDIO_C45, 112 }; 113 114 static const struct fec_devinfo fec_imx28_info = { 115 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 116 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 117 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 118 FEC_QUIRK_NO_HARD_RESET | FEC_QUIRK_HAS_MDIO_C45, 119 }; 120 121 static const struct fec_devinfo fec_imx6q_info = { 122 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 125 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII | 126 FEC_QUIRK_HAS_PMQOS | FEC_QUIRK_HAS_MDIO_C45, 127 }; 128 129 static const struct fec_devinfo fec_mvf600_info = { 130 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC | 131 FEC_QUIRK_HAS_MDIO_C45, 132 }; 133 134 static const struct fec_devinfo fec_imx6x_info = { 135 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 136 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 137 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 138 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 139 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 140 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 141 FEC_QUIRK_HAS_MDIO_C45, 142 }; 143 144 static const struct fec_devinfo fec_imx6ul_info = { 145 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 146 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 147 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 148 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 149 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII | 150 FEC_QUIRK_HAS_MDIO_C45, 151 }; 152 153 static const struct fec_devinfo fec_imx8mq_info = { 154 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 155 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 156 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 157 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 158 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 159 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 160 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2 | 161 FEC_QUIRK_HAS_MDIO_C45, 162 }; 163 164 static const struct fec_devinfo fec_imx8qm_info = { 165 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 166 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 167 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 168 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 169 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 170 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 171 FEC_QUIRK_DELAYED_CLKS_SUPPORT | FEC_QUIRK_HAS_MDIO_C45, 172 }; 173 174 static const struct fec_devinfo fec_s32v234_info = { 175 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 176 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 177 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 178 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 179 FEC_QUIRK_HAS_MDIO_C45, 180 }; 181 182 static struct platform_device_id fec_devtype[] = { 183 { 184 /* keep it for coldfire */ 185 .name = DRIVER_NAME, 186 .driver_data = 0, 187 }, { 188 /* sentinel */ 189 } 190 }; 191 MODULE_DEVICE_TABLE(platform, fec_devtype); 192 193 static const struct of_device_id fec_dt_ids[] = { 194 { .compatible = "fsl,imx25-fec", .data = &fec_imx25_info, }, 195 { .compatible = "fsl,imx27-fec", .data = &fec_imx27_info, }, 196 { .compatible = "fsl,imx28-fec", .data = &fec_imx28_info, }, 197 { .compatible = "fsl,imx6q-fec", .data = &fec_imx6q_info, }, 198 { .compatible = "fsl,mvf600-fec", .data = &fec_mvf600_info, }, 199 { .compatible = "fsl,imx6sx-fec", .data = &fec_imx6x_info, }, 200 { .compatible = "fsl,imx6ul-fec", .data = &fec_imx6ul_info, }, 201 { .compatible = "fsl,imx8mq-fec", .data = &fec_imx8mq_info, }, 202 { .compatible = "fsl,imx8qm-fec", .data = &fec_imx8qm_info, }, 203 { .compatible = "fsl,s32v234-fec", .data = &fec_s32v234_info, }, 204 { /* sentinel */ } 205 }; 206 MODULE_DEVICE_TABLE(of, fec_dt_ids); 207 208 static unsigned char macaddr[ETH_ALEN]; 209 module_param_array(macaddr, byte, NULL, 0); 210 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 211 212 #if defined(CONFIG_M5272) 213 /* 214 * Some hardware gets it MAC address out of local flash memory. 215 * if this is non-zero then assume it is the address to get MAC from. 216 */ 217 #if defined(CONFIG_NETtel) 218 #define FEC_FLASHMAC 0xf0006006 219 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 220 #define FEC_FLASHMAC 0xf0006000 221 #elif defined(CONFIG_CANCam) 222 #define FEC_FLASHMAC 0xf0020000 223 #elif defined (CONFIG_M5272C3) 224 #define FEC_FLASHMAC (0xffe04000 + 4) 225 #elif defined(CONFIG_MOD5272) 226 #define FEC_FLASHMAC 0xffc0406b 227 #else 228 #define FEC_FLASHMAC 0 229 #endif 230 #endif /* CONFIG_M5272 */ 231 232 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 233 * 234 * 2048 byte skbufs are allocated. However, alignment requirements 235 * varies between FEC variants. Worst case is 64, so round down by 64. 236 */ 237 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 238 #define PKT_MINBUF_SIZE 64 239 240 /* FEC receive acceleration */ 241 #define FEC_RACC_IPDIS BIT(1) 242 #define FEC_RACC_PRODIS BIT(2) 243 #define FEC_RACC_SHIFT16 BIT(7) 244 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 245 246 /* MIB Control Register */ 247 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 248 249 /* 250 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 251 * size bits. Other FEC hardware does not, so we need to take that into 252 * account when setting it. 253 */ 254 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 255 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 256 defined(CONFIG_ARM64) 257 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 258 #else 259 #define OPT_FRAME_SIZE 0 260 #endif 261 262 /* FEC MII MMFR bits definition */ 263 #define FEC_MMFR_ST (1 << 30) 264 #define FEC_MMFR_ST_C45 (0) 265 #define FEC_MMFR_OP_READ (2 << 28) 266 #define FEC_MMFR_OP_READ_C45 (3 << 28) 267 #define FEC_MMFR_OP_WRITE (1 << 28) 268 #define FEC_MMFR_OP_ADDR_WRITE (0) 269 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 270 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 271 #define FEC_MMFR_TA (2 << 16) 272 #define FEC_MMFR_DATA(v) (v & 0xffff) 273 /* FEC ECR bits definition */ 274 #define FEC_ECR_RESET BIT(0) 275 #define FEC_ECR_ETHEREN BIT(1) 276 #define FEC_ECR_MAGICEN BIT(2) 277 #define FEC_ECR_SLEEP BIT(3) 278 #define FEC_ECR_EN1588 BIT(4) 279 #define FEC_ECR_BYTESWP BIT(8) 280 /* FEC RCR bits definition */ 281 #define FEC_RCR_LOOP BIT(0) 282 #define FEC_RCR_HALFDPX BIT(1) 283 #define FEC_RCR_MII BIT(2) 284 #define FEC_RCR_PROMISC BIT(3) 285 #define FEC_RCR_BC_REJ BIT(4) 286 #define FEC_RCR_FLOWCTL BIT(5) 287 #define FEC_RCR_RMII BIT(8) 288 #define FEC_RCR_10BASET BIT(9) 289 /* TX WMARK bits */ 290 #define FEC_TXWMRK_STRFWD BIT(8) 291 292 #define FEC_MII_TIMEOUT 30000 /* us */ 293 294 /* Transmitter timeout */ 295 #define TX_TIMEOUT (2 * HZ) 296 297 #define FEC_PAUSE_FLAG_AUTONEG 0x1 298 #define FEC_PAUSE_FLAG_ENABLE 0x2 299 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 300 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 301 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 302 303 /* Max number of allowed TCP segments for software TSO */ 304 #define FEC_MAX_TSO_SEGS 100 305 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 306 307 #define IS_TSO_HEADER(txq, addr) \ 308 ((addr >= txq->tso_hdrs_dma) && \ 309 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 310 311 static int mii_cnt; 312 313 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 314 struct bufdesc_prop *bd) 315 { 316 return (bdp >= bd->last) ? bd->base 317 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 318 } 319 320 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 321 struct bufdesc_prop *bd) 322 { 323 return (bdp <= bd->base) ? bd->last 324 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 325 } 326 327 static int fec_enet_get_bd_index(struct bufdesc *bdp, 328 struct bufdesc_prop *bd) 329 { 330 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 331 } 332 333 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 334 { 335 int entries; 336 337 entries = (((const char *)txq->dirty_tx - 338 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 339 340 return entries >= 0 ? entries : entries + txq->bd.ring_size; 341 } 342 343 static void swap_buffer(void *bufaddr, int len) 344 { 345 int i; 346 unsigned int *buf = bufaddr; 347 348 for (i = 0; i < len; i += 4, buf++) 349 swab32s(buf); 350 } 351 352 static void fec_dump(struct net_device *ndev) 353 { 354 struct fec_enet_private *fep = netdev_priv(ndev); 355 struct bufdesc *bdp; 356 struct fec_enet_priv_tx_q *txq; 357 int index = 0; 358 359 netdev_info(ndev, "TX ring dump\n"); 360 pr_info("Nr SC addr len SKB\n"); 361 362 txq = fep->tx_queue[0]; 363 bdp = txq->bd.base; 364 365 do { 366 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 367 index, 368 bdp == txq->bd.cur ? 'S' : ' ', 369 bdp == txq->dirty_tx ? 'H' : ' ', 370 fec16_to_cpu(bdp->cbd_sc), 371 fec32_to_cpu(bdp->cbd_bufaddr), 372 fec16_to_cpu(bdp->cbd_datlen), 373 txq->tx_buf[index].buf_p); 374 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 375 index++; 376 } while (bdp != txq->bd.base); 377 } 378 379 /* 380 * Coldfire does not support DMA coherent allocations, and has historically used 381 * a band-aid with a manual flush in fec_enet_rx_queue. 382 */ 383 #if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA) 384 static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, 385 gfp_t gfp) 386 { 387 return dma_alloc_noncoherent(dev, size, handle, DMA_BIDIRECTIONAL, gfp); 388 } 389 390 static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr, 391 dma_addr_t handle) 392 { 393 dma_free_noncoherent(dev, size, cpu_addr, handle, DMA_BIDIRECTIONAL); 394 } 395 #else /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */ 396 static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, 397 gfp_t gfp) 398 { 399 return dma_alloc_coherent(dev, size, handle, gfp); 400 } 401 402 static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr, 403 dma_addr_t handle) 404 { 405 dma_free_coherent(dev, size, cpu_addr, handle); 406 } 407 #endif /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */ 408 409 struct fec_dma_devres { 410 size_t size; 411 void *vaddr; 412 dma_addr_t dma_handle; 413 }; 414 415 static void fec_dmam_release(struct device *dev, void *res) 416 { 417 struct fec_dma_devres *this = res; 418 419 fec_dma_free(dev, this->size, this->vaddr, this->dma_handle); 420 } 421 422 static void *fec_dmam_alloc(struct device *dev, size_t size, dma_addr_t *handle, 423 gfp_t gfp) 424 { 425 struct fec_dma_devres *dr; 426 void *vaddr; 427 428 dr = devres_alloc(fec_dmam_release, sizeof(*dr), gfp); 429 if (!dr) 430 return NULL; 431 vaddr = fec_dma_alloc(dev, size, handle, gfp); 432 if (!vaddr) { 433 devres_free(dr); 434 return NULL; 435 } 436 dr->vaddr = vaddr; 437 dr->dma_handle = *handle; 438 dr->size = size; 439 devres_add(dev, dr); 440 return vaddr; 441 } 442 443 static inline bool is_ipv4_pkt(struct sk_buff *skb) 444 { 445 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 446 } 447 448 static int 449 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 450 { 451 /* Only run for packets requiring a checksum. */ 452 if (skb->ip_summed != CHECKSUM_PARTIAL) 453 return 0; 454 455 if (unlikely(skb_cow_head(skb, 0))) 456 return -1; 457 458 if (is_ipv4_pkt(skb)) 459 ip_hdr(skb)->check = 0; 460 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 461 462 return 0; 463 } 464 465 static int 466 fec_enet_create_page_pool(struct fec_enet_private *fep, 467 struct fec_enet_priv_rx_q *rxq, int size) 468 { 469 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 470 struct page_pool_params pp_params = { 471 .order = 0, 472 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 473 .pool_size = size, 474 .nid = dev_to_node(&fep->pdev->dev), 475 .dev = &fep->pdev->dev, 476 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 477 .offset = FEC_ENET_XDP_HEADROOM, 478 .max_len = FEC_ENET_RX_FRSIZE, 479 }; 480 int err; 481 482 rxq->page_pool = page_pool_create(&pp_params); 483 if (IS_ERR(rxq->page_pool)) { 484 err = PTR_ERR(rxq->page_pool); 485 rxq->page_pool = NULL; 486 return err; 487 } 488 489 err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0); 490 if (err < 0) 491 goto err_free_pp; 492 493 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 494 rxq->page_pool); 495 if (err) 496 goto err_unregister_rxq; 497 498 return 0; 499 500 err_unregister_rxq: 501 xdp_rxq_info_unreg(&rxq->xdp_rxq); 502 err_free_pp: 503 page_pool_destroy(rxq->page_pool); 504 rxq->page_pool = NULL; 505 return err; 506 } 507 508 static struct bufdesc * 509 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 510 struct sk_buff *skb, 511 struct net_device *ndev) 512 { 513 struct fec_enet_private *fep = netdev_priv(ndev); 514 struct bufdesc *bdp = txq->bd.cur; 515 struct bufdesc_ex *ebdp; 516 int nr_frags = skb_shinfo(skb)->nr_frags; 517 int frag, frag_len; 518 unsigned short status; 519 unsigned int estatus = 0; 520 skb_frag_t *this_frag; 521 unsigned int index; 522 void *bufaddr; 523 dma_addr_t addr; 524 int i; 525 526 for (frag = 0; frag < nr_frags; frag++) { 527 this_frag = &skb_shinfo(skb)->frags[frag]; 528 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 529 ebdp = (struct bufdesc_ex *)bdp; 530 531 status = fec16_to_cpu(bdp->cbd_sc); 532 status &= ~BD_ENET_TX_STATS; 533 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 534 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 535 536 /* Handle the last BD specially */ 537 if (frag == nr_frags - 1) { 538 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 539 if (fep->bufdesc_ex) { 540 estatus |= BD_ENET_TX_INT; 541 if (unlikely(skb_shinfo(skb)->tx_flags & 542 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 543 estatus |= BD_ENET_TX_TS; 544 } 545 } 546 547 if (fep->bufdesc_ex) { 548 if (fep->quirks & FEC_QUIRK_HAS_AVB) 549 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 550 if (skb->ip_summed == CHECKSUM_PARTIAL) 551 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 552 553 ebdp->cbd_bdu = 0; 554 ebdp->cbd_esc = cpu_to_fec32(estatus); 555 } 556 557 bufaddr = skb_frag_address(this_frag); 558 559 index = fec_enet_get_bd_index(bdp, &txq->bd); 560 if (((unsigned long) bufaddr) & fep->tx_align || 561 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 562 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 563 bufaddr = txq->tx_bounce[index]; 564 565 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 566 swap_buffer(bufaddr, frag_len); 567 } 568 569 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 570 DMA_TO_DEVICE); 571 if (dma_mapping_error(&fep->pdev->dev, addr)) { 572 if (net_ratelimit()) 573 netdev_err(ndev, "Tx DMA memory map failed\n"); 574 goto dma_mapping_error; 575 } 576 577 bdp->cbd_bufaddr = cpu_to_fec32(addr); 578 bdp->cbd_datlen = cpu_to_fec16(frag_len); 579 /* Make sure the updates to rest of the descriptor are 580 * performed before transferring ownership. 581 */ 582 wmb(); 583 bdp->cbd_sc = cpu_to_fec16(status); 584 } 585 586 return bdp; 587 dma_mapping_error: 588 bdp = txq->bd.cur; 589 for (i = 0; i < frag; i++) { 590 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 591 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 592 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 593 } 594 return ERR_PTR(-ENOMEM); 595 } 596 597 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 598 struct sk_buff *skb, struct net_device *ndev) 599 { 600 struct fec_enet_private *fep = netdev_priv(ndev); 601 int nr_frags = skb_shinfo(skb)->nr_frags; 602 struct bufdesc *bdp, *last_bdp; 603 void *bufaddr; 604 dma_addr_t addr; 605 unsigned short status; 606 unsigned short buflen; 607 unsigned int estatus = 0; 608 unsigned int index; 609 int entries_free; 610 611 entries_free = fec_enet_get_free_txdesc_num(txq); 612 if (entries_free < MAX_SKB_FRAGS + 1) { 613 dev_kfree_skb_any(skb); 614 if (net_ratelimit()) 615 netdev_err(ndev, "NOT enough BD for SG!\n"); 616 return NETDEV_TX_OK; 617 } 618 619 /* Protocol checksum off-load for TCP and UDP. */ 620 if (fec_enet_clear_csum(skb, ndev)) { 621 dev_kfree_skb_any(skb); 622 return NETDEV_TX_OK; 623 } 624 625 /* Fill in a Tx ring entry */ 626 bdp = txq->bd.cur; 627 last_bdp = bdp; 628 status = fec16_to_cpu(bdp->cbd_sc); 629 status &= ~BD_ENET_TX_STATS; 630 631 /* Set buffer length and buffer pointer */ 632 bufaddr = skb->data; 633 buflen = skb_headlen(skb); 634 635 index = fec_enet_get_bd_index(bdp, &txq->bd); 636 if (((unsigned long) bufaddr) & fep->tx_align || 637 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 638 memcpy(txq->tx_bounce[index], skb->data, buflen); 639 bufaddr = txq->tx_bounce[index]; 640 641 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 642 swap_buffer(bufaddr, buflen); 643 } 644 645 /* Push the data cache so the CPM does not get stale memory data. */ 646 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 647 if (dma_mapping_error(&fep->pdev->dev, addr)) { 648 dev_kfree_skb_any(skb); 649 if (net_ratelimit()) 650 netdev_err(ndev, "Tx DMA memory map failed\n"); 651 return NETDEV_TX_OK; 652 } 653 654 if (nr_frags) { 655 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 656 if (IS_ERR(last_bdp)) { 657 dma_unmap_single(&fep->pdev->dev, addr, 658 buflen, DMA_TO_DEVICE); 659 dev_kfree_skb_any(skb); 660 return NETDEV_TX_OK; 661 } 662 } else { 663 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 664 if (fep->bufdesc_ex) { 665 estatus = BD_ENET_TX_INT; 666 if (unlikely(skb_shinfo(skb)->tx_flags & 667 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 668 estatus |= BD_ENET_TX_TS; 669 } 670 } 671 bdp->cbd_bufaddr = cpu_to_fec32(addr); 672 bdp->cbd_datlen = cpu_to_fec16(buflen); 673 674 if (fep->bufdesc_ex) { 675 676 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 677 678 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 679 fep->hwts_tx_en)) 680 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 681 682 if (fep->quirks & FEC_QUIRK_HAS_AVB) 683 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 684 685 if (skb->ip_summed == CHECKSUM_PARTIAL) 686 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 687 688 ebdp->cbd_bdu = 0; 689 ebdp->cbd_esc = cpu_to_fec32(estatus); 690 } 691 692 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 693 /* Save skb pointer */ 694 txq->tx_buf[index].buf_p = skb; 695 696 /* Make sure the updates to rest of the descriptor are performed before 697 * transferring ownership. 698 */ 699 wmb(); 700 701 /* Send it on its way. Tell FEC it's ready, interrupt when done, 702 * it's the last BD of the frame, and to put the CRC on the end. 703 */ 704 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 705 bdp->cbd_sc = cpu_to_fec16(status); 706 707 /* If this was the last BD in the ring, start at the beginning again. */ 708 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 709 710 skb_tx_timestamp(skb); 711 712 /* Make sure the update to bdp is performed before txq->bd.cur. */ 713 wmb(); 714 txq->bd.cur = bdp; 715 716 /* Trigger transmission start */ 717 writel(0, txq->bd.reg_desc_active); 718 719 return 0; 720 } 721 722 static int 723 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 724 struct net_device *ndev, 725 struct bufdesc *bdp, int index, char *data, 726 int size, bool last_tcp, bool is_last) 727 { 728 struct fec_enet_private *fep = netdev_priv(ndev); 729 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 730 unsigned short status; 731 unsigned int estatus = 0; 732 dma_addr_t addr; 733 734 status = fec16_to_cpu(bdp->cbd_sc); 735 status &= ~BD_ENET_TX_STATS; 736 737 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 738 739 if (((unsigned long) data) & fep->tx_align || 740 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 741 memcpy(txq->tx_bounce[index], data, size); 742 data = txq->tx_bounce[index]; 743 744 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 745 swap_buffer(data, size); 746 } 747 748 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 749 if (dma_mapping_error(&fep->pdev->dev, addr)) { 750 dev_kfree_skb_any(skb); 751 if (net_ratelimit()) 752 netdev_err(ndev, "Tx DMA memory map failed\n"); 753 return NETDEV_TX_OK; 754 } 755 756 bdp->cbd_datlen = cpu_to_fec16(size); 757 bdp->cbd_bufaddr = cpu_to_fec32(addr); 758 759 if (fep->bufdesc_ex) { 760 if (fep->quirks & FEC_QUIRK_HAS_AVB) 761 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 762 if (skb->ip_summed == CHECKSUM_PARTIAL) 763 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 764 ebdp->cbd_bdu = 0; 765 ebdp->cbd_esc = cpu_to_fec32(estatus); 766 } 767 768 /* Handle the last BD specially */ 769 if (last_tcp) 770 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 771 if (is_last) { 772 status |= BD_ENET_TX_INTR; 773 if (fep->bufdesc_ex) 774 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 775 } 776 777 bdp->cbd_sc = cpu_to_fec16(status); 778 779 return 0; 780 } 781 782 static int 783 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 784 struct sk_buff *skb, struct net_device *ndev, 785 struct bufdesc *bdp, int index) 786 { 787 struct fec_enet_private *fep = netdev_priv(ndev); 788 int hdr_len = skb_tcp_all_headers(skb); 789 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 790 void *bufaddr; 791 unsigned long dmabuf; 792 unsigned short status; 793 unsigned int estatus = 0; 794 795 status = fec16_to_cpu(bdp->cbd_sc); 796 status &= ~BD_ENET_TX_STATS; 797 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 798 799 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 800 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 801 if (((unsigned long)bufaddr) & fep->tx_align || 802 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 803 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 804 bufaddr = txq->tx_bounce[index]; 805 806 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 807 swap_buffer(bufaddr, hdr_len); 808 809 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 810 hdr_len, DMA_TO_DEVICE); 811 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 812 dev_kfree_skb_any(skb); 813 if (net_ratelimit()) 814 netdev_err(ndev, "Tx DMA memory map failed\n"); 815 return NETDEV_TX_OK; 816 } 817 } 818 819 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 820 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 821 822 if (fep->bufdesc_ex) { 823 if (fep->quirks & FEC_QUIRK_HAS_AVB) 824 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 825 if (skb->ip_summed == CHECKSUM_PARTIAL) 826 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 827 ebdp->cbd_bdu = 0; 828 ebdp->cbd_esc = cpu_to_fec32(estatus); 829 } 830 831 bdp->cbd_sc = cpu_to_fec16(status); 832 833 return 0; 834 } 835 836 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 837 struct sk_buff *skb, 838 struct net_device *ndev) 839 { 840 struct fec_enet_private *fep = netdev_priv(ndev); 841 int hdr_len, total_len, data_left; 842 struct bufdesc *bdp = txq->bd.cur; 843 struct tso_t tso; 844 unsigned int index = 0; 845 int ret; 846 847 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 848 dev_kfree_skb_any(skb); 849 if (net_ratelimit()) 850 netdev_err(ndev, "NOT enough BD for TSO!\n"); 851 return NETDEV_TX_OK; 852 } 853 854 /* Protocol checksum off-load for TCP and UDP. */ 855 if (fec_enet_clear_csum(skb, ndev)) { 856 dev_kfree_skb_any(skb); 857 return NETDEV_TX_OK; 858 } 859 860 /* Initialize the TSO handler, and prepare the first payload */ 861 hdr_len = tso_start(skb, &tso); 862 863 total_len = skb->len - hdr_len; 864 while (total_len > 0) { 865 char *hdr; 866 867 index = fec_enet_get_bd_index(bdp, &txq->bd); 868 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 869 total_len -= data_left; 870 871 /* prepare packet headers: MAC + IP + TCP */ 872 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 873 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 874 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 875 if (ret) 876 goto err_release; 877 878 while (data_left > 0) { 879 int size; 880 881 size = min_t(int, tso.size, data_left); 882 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 883 index = fec_enet_get_bd_index(bdp, &txq->bd); 884 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 885 bdp, index, 886 tso.data, size, 887 size == data_left, 888 total_len == 0); 889 if (ret) 890 goto err_release; 891 892 data_left -= size; 893 tso_build_data(skb, &tso, size); 894 } 895 896 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 897 } 898 899 /* Save skb pointer */ 900 txq->tx_buf[index].buf_p = skb; 901 902 skb_tx_timestamp(skb); 903 txq->bd.cur = bdp; 904 905 /* Trigger transmission start */ 906 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 907 !readl(txq->bd.reg_desc_active) || 908 !readl(txq->bd.reg_desc_active) || 909 !readl(txq->bd.reg_desc_active) || 910 !readl(txq->bd.reg_desc_active)) 911 writel(0, txq->bd.reg_desc_active); 912 913 return 0; 914 915 err_release: 916 /* TODO: Release all used data descriptors for TSO */ 917 return ret; 918 } 919 920 static netdev_tx_t 921 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 922 { 923 struct fec_enet_private *fep = netdev_priv(ndev); 924 int entries_free; 925 unsigned short queue; 926 struct fec_enet_priv_tx_q *txq; 927 struct netdev_queue *nq; 928 int ret; 929 930 queue = skb_get_queue_mapping(skb); 931 txq = fep->tx_queue[queue]; 932 nq = netdev_get_tx_queue(ndev, queue); 933 934 if (skb_is_gso(skb)) 935 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 936 else 937 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 938 if (ret) 939 return ret; 940 941 entries_free = fec_enet_get_free_txdesc_num(txq); 942 if (entries_free <= txq->tx_stop_threshold) 943 netif_tx_stop_queue(nq); 944 945 return NETDEV_TX_OK; 946 } 947 948 /* Init RX & TX buffer descriptors 949 */ 950 static void fec_enet_bd_init(struct net_device *dev) 951 { 952 struct fec_enet_private *fep = netdev_priv(dev); 953 struct fec_enet_priv_tx_q *txq; 954 struct fec_enet_priv_rx_q *rxq; 955 struct bufdesc *bdp; 956 unsigned int i; 957 unsigned int q; 958 959 for (q = 0; q < fep->num_rx_queues; q++) { 960 /* Initialize the receive buffer descriptors. */ 961 rxq = fep->rx_queue[q]; 962 bdp = rxq->bd.base; 963 964 for (i = 0; i < rxq->bd.ring_size; i++) { 965 966 /* Initialize the BD for every fragment in the page. */ 967 if (bdp->cbd_bufaddr) 968 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 969 else 970 bdp->cbd_sc = cpu_to_fec16(0); 971 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 972 } 973 974 /* Set the last buffer to wrap */ 975 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 976 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 977 978 rxq->bd.cur = rxq->bd.base; 979 } 980 981 for (q = 0; q < fep->num_tx_queues; q++) { 982 /* ...and the same for transmit */ 983 txq = fep->tx_queue[q]; 984 bdp = txq->bd.base; 985 txq->bd.cur = bdp; 986 987 for (i = 0; i < txq->bd.ring_size; i++) { 988 /* Initialize the BD for every fragment in the page. */ 989 bdp->cbd_sc = cpu_to_fec16(0); 990 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 991 if (bdp->cbd_bufaddr && 992 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 993 dma_unmap_single(&fep->pdev->dev, 994 fec32_to_cpu(bdp->cbd_bufaddr), 995 fec16_to_cpu(bdp->cbd_datlen), 996 DMA_TO_DEVICE); 997 if (txq->tx_buf[i].buf_p) 998 dev_kfree_skb_any(txq->tx_buf[i].buf_p); 999 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 1000 if (bdp->cbd_bufaddr) 1001 dma_unmap_single(&fep->pdev->dev, 1002 fec32_to_cpu(bdp->cbd_bufaddr), 1003 fec16_to_cpu(bdp->cbd_datlen), 1004 DMA_TO_DEVICE); 1005 1006 if (txq->tx_buf[i].buf_p) 1007 xdp_return_frame(txq->tx_buf[i].buf_p); 1008 } else { 1009 struct page *page = txq->tx_buf[i].buf_p; 1010 1011 if (page) 1012 page_pool_put_page(page->pp, page, 0, false); 1013 } 1014 1015 txq->tx_buf[i].buf_p = NULL; 1016 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1017 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 1018 bdp->cbd_bufaddr = cpu_to_fec32(0); 1019 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1020 } 1021 1022 /* Set the last buffer to wrap */ 1023 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 1024 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 1025 txq->dirty_tx = bdp; 1026 } 1027 } 1028 1029 static void fec_enet_active_rxring(struct net_device *ndev) 1030 { 1031 struct fec_enet_private *fep = netdev_priv(ndev); 1032 int i; 1033 1034 for (i = 0; i < fep->num_rx_queues; i++) 1035 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 1036 } 1037 1038 static void fec_enet_enable_ring(struct net_device *ndev) 1039 { 1040 struct fec_enet_private *fep = netdev_priv(ndev); 1041 struct fec_enet_priv_tx_q *txq; 1042 struct fec_enet_priv_rx_q *rxq; 1043 int i; 1044 1045 for (i = 0; i < fep->num_rx_queues; i++) { 1046 rxq = fep->rx_queue[i]; 1047 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 1048 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 1049 1050 /* enable DMA1/2 */ 1051 if (i) 1052 writel(RCMR_MATCHEN | RCMR_CMP(i), 1053 fep->hwp + FEC_RCMR(i)); 1054 } 1055 1056 for (i = 0; i < fep->num_tx_queues; i++) { 1057 txq = fep->tx_queue[i]; 1058 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 1059 1060 /* enable DMA1/2 */ 1061 if (i) 1062 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 1063 fep->hwp + FEC_DMA_CFG(i)); 1064 } 1065 } 1066 1067 /* 1068 * This function is called to start or restart the FEC during a link 1069 * change, transmit timeout, or to reconfigure the FEC. The network 1070 * packet processing for this device must be stopped before this call. 1071 */ 1072 static void 1073 fec_restart(struct net_device *ndev) 1074 { 1075 struct fec_enet_private *fep = netdev_priv(ndev); 1076 u32 temp_mac[2]; 1077 u32 rcntl = OPT_FRAME_SIZE | 0x04; 1078 u32 ecntl = FEC_ECR_ETHEREN; 1079 1080 if (fep->bufdesc_ex) 1081 fec_ptp_save_state(fep); 1082 1083 /* Whack a reset. We should wait for this. 1084 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1085 * instead of reset MAC itself. 1086 */ 1087 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || 1088 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 1089 writel(0, fep->hwp + FEC_ECNTRL); 1090 } else { 1091 writel(1, fep->hwp + FEC_ECNTRL); 1092 udelay(10); 1093 } 1094 1095 /* 1096 * enet-mac reset will reset mac address registers too, 1097 * so need to reconfigure it. 1098 */ 1099 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 1100 writel((__force u32)cpu_to_be32(temp_mac[0]), 1101 fep->hwp + FEC_ADDR_LOW); 1102 writel((__force u32)cpu_to_be32(temp_mac[1]), 1103 fep->hwp + FEC_ADDR_HIGH); 1104 1105 /* Clear any outstanding interrupt, except MDIO. */ 1106 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 1107 1108 fec_enet_bd_init(ndev); 1109 1110 fec_enet_enable_ring(ndev); 1111 1112 /* Enable MII mode */ 1113 if (fep->full_duplex == DUPLEX_FULL) { 1114 /* FD enable */ 1115 writel(0x04, fep->hwp + FEC_X_CNTRL); 1116 } else { 1117 /* No Rcv on Xmit */ 1118 rcntl |= 0x02; 1119 writel(0x0, fep->hwp + FEC_X_CNTRL); 1120 } 1121 1122 /* Set MII speed */ 1123 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1124 1125 #if !defined(CONFIG_M5272) 1126 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1127 u32 val = readl(fep->hwp + FEC_RACC); 1128 1129 /* align IP header */ 1130 val |= FEC_RACC_SHIFT16; 1131 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1132 /* set RX checksum */ 1133 val |= FEC_RACC_OPTIONS; 1134 else 1135 val &= ~FEC_RACC_OPTIONS; 1136 writel(val, fep->hwp + FEC_RACC); 1137 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1138 } 1139 #endif 1140 1141 /* 1142 * The phy interface and speed need to get configured 1143 * differently on enet-mac. 1144 */ 1145 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1146 /* Enable flow control and length check */ 1147 rcntl |= 0x40000000 | 0x00000020; 1148 1149 /* RGMII, RMII or MII */ 1150 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1151 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1152 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1153 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1154 rcntl |= (1 << 6); 1155 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1156 rcntl |= FEC_RCR_RMII; 1157 else 1158 rcntl &= ~FEC_RCR_RMII; 1159 1160 /* 1G, 100M or 10M */ 1161 if (ndev->phydev) { 1162 if (ndev->phydev->speed == SPEED_1000) 1163 ecntl |= (1 << 5); 1164 else if (ndev->phydev->speed == SPEED_100) 1165 rcntl &= ~FEC_RCR_10BASET; 1166 else 1167 rcntl |= FEC_RCR_10BASET; 1168 } 1169 } else { 1170 #ifdef FEC_MIIGSK_ENR 1171 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1172 u32 cfgr; 1173 /* disable the gasket and wait */ 1174 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1175 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1176 udelay(1); 1177 1178 /* 1179 * configure the gasket: 1180 * RMII, 50 MHz, no loopback, no echo 1181 * MII, 25 MHz, no loopback, no echo 1182 */ 1183 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1184 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1185 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1186 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1187 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1188 1189 /* re-enable the gasket */ 1190 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1191 } 1192 #endif 1193 } 1194 1195 #if !defined(CONFIG_M5272) 1196 /* enable pause frame*/ 1197 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1198 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1199 ndev->phydev && ndev->phydev->pause)) { 1200 rcntl |= FEC_RCR_FLOWCTL; 1201 1202 /* set FIFO threshold parameter to reduce overrun */ 1203 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1204 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1205 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1206 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1207 1208 /* OPD */ 1209 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1210 } else { 1211 rcntl &= ~FEC_RCR_FLOWCTL; 1212 } 1213 #endif /* !defined(CONFIG_M5272) */ 1214 1215 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1216 1217 /* Setup multicast filter. */ 1218 set_multicast_list(ndev); 1219 #ifndef CONFIG_M5272 1220 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1221 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1222 #endif 1223 1224 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1225 /* enable ENET endian swap */ 1226 ecntl |= FEC_ECR_BYTESWP; 1227 /* enable ENET store and forward mode */ 1228 writel(FEC_TXWMRK_STRFWD, fep->hwp + FEC_X_WMRK); 1229 } 1230 1231 if (fep->bufdesc_ex) 1232 ecntl |= FEC_ECR_EN1588; 1233 1234 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1235 fep->rgmii_txc_dly) 1236 ecntl |= FEC_ENET_TXC_DLY; 1237 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1238 fep->rgmii_rxc_dly) 1239 ecntl |= FEC_ENET_RXC_DLY; 1240 1241 #ifndef CONFIG_M5272 1242 /* Enable the MIB statistic event counters */ 1243 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1244 #endif 1245 1246 /* And last, enable the transmit and receive processing */ 1247 writel(ecntl, fep->hwp + FEC_ECNTRL); 1248 fec_enet_active_rxring(ndev); 1249 1250 if (fep->bufdesc_ex) { 1251 fec_ptp_start_cyclecounter(ndev); 1252 fec_ptp_restore_state(fep); 1253 } 1254 1255 /* Enable interrupts we wish to service */ 1256 if (fep->link) 1257 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1258 else 1259 writel(0, fep->hwp + FEC_IMASK); 1260 1261 /* Init the interrupt coalescing */ 1262 if (fep->quirks & FEC_QUIRK_HAS_COALESCE) 1263 fec_enet_itr_coal_set(ndev); 1264 } 1265 1266 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep) 1267 { 1268 if (!(of_machine_is_compatible("fsl,imx8qm") || 1269 of_machine_is_compatible("fsl,imx8qxp") || 1270 of_machine_is_compatible("fsl,imx8dxl"))) 1271 return 0; 1272 1273 return imx_scu_get_handle(&fep->ipc_handle); 1274 } 1275 1276 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled) 1277 { 1278 struct device_node *np = fep->pdev->dev.of_node; 1279 u32 rsrc_id, val; 1280 int idx; 1281 1282 if (!np || !fep->ipc_handle) 1283 return; 1284 1285 idx = of_alias_get_id(np, "ethernet"); 1286 if (idx < 0) 1287 idx = 0; 1288 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0; 1289 1290 val = enabled ? 1 : 0; 1291 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val); 1292 } 1293 1294 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1295 { 1296 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1297 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1298 1299 if (stop_gpr->gpr) { 1300 if (enabled) 1301 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1302 BIT(stop_gpr->bit), 1303 BIT(stop_gpr->bit)); 1304 else 1305 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1306 BIT(stop_gpr->bit), 0); 1307 } else if (pdata && pdata->sleep_mode_enable) { 1308 pdata->sleep_mode_enable(enabled); 1309 } else { 1310 fec_enet_ipg_stop_set(fep, enabled); 1311 } 1312 } 1313 1314 static void fec_irqs_disable(struct net_device *ndev) 1315 { 1316 struct fec_enet_private *fep = netdev_priv(ndev); 1317 1318 writel(0, fep->hwp + FEC_IMASK); 1319 } 1320 1321 static void fec_irqs_disable_except_wakeup(struct net_device *ndev) 1322 { 1323 struct fec_enet_private *fep = netdev_priv(ndev); 1324 1325 writel(0, fep->hwp + FEC_IMASK); 1326 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1327 } 1328 1329 static void 1330 fec_stop(struct net_device *ndev) 1331 { 1332 struct fec_enet_private *fep = netdev_priv(ndev); 1333 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & FEC_RCR_RMII; 1334 u32 val; 1335 1336 /* We cannot expect a graceful transmit stop without link !!! */ 1337 if (fep->link) { 1338 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1339 udelay(10); 1340 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1341 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1342 } 1343 1344 if (fep->bufdesc_ex) 1345 fec_ptp_save_state(fep); 1346 1347 /* Whack a reset. We should wait for this. 1348 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1349 * instead of reset MAC itself. 1350 */ 1351 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1352 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 1353 writel(0, fep->hwp + FEC_ECNTRL); 1354 } else { 1355 writel(FEC_ECR_RESET, fep->hwp + FEC_ECNTRL); 1356 udelay(10); 1357 } 1358 } else { 1359 val = readl(fep->hwp + FEC_ECNTRL); 1360 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1361 writel(val, fep->hwp + FEC_ECNTRL); 1362 } 1363 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1364 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1365 1366 /* We have to keep ENET enabled to have MII interrupt stay working */ 1367 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1368 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1369 writel(FEC_ECR_ETHEREN, fep->hwp + FEC_ECNTRL); 1370 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1371 } 1372 1373 if (fep->bufdesc_ex) { 1374 val = readl(fep->hwp + FEC_ECNTRL); 1375 val |= FEC_ECR_EN1588; 1376 writel(val, fep->hwp + FEC_ECNTRL); 1377 1378 fec_ptp_start_cyclecounter(ndev); 1379 fec_ptp_restore_state(fep); 1380 } 1381 } 1382 1383 static void 1384 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1385 { 1386 struct fec_enet_private *fep = netdev_priv(ndev); 1387 1388 fec_dump(ndev); 1389 1390 ndev->stats.tx_errors++; 1391 1392 schedule_work(&fep->tx_timeout_work); 1393 } 1394 1395 static void fec_enet_timeout_work(struct work_struct *work) 1396 { 1397 struct fec_enet_private *fep = 1398 container_of(work, struct fec_enet_private, tx_timeout_work); 1399 struct net_device *ndev = fep->netdev; 1400 1401 rtnl_lock(); 1402 if (netif_device_present(ndev) || netif_running(ndev)) { 1403 napi_disable(&fep->napi); 1404 netif_tx_lock_bh(ndev); 1405 fec_restart(ndev); 1406 netif_tx_wake_all_queues(ndev); 1407 netif_tx_unlock_bh(ndev); 1408 napi_enable(&fep->napi); 1409 } 1410 rtnl_unlock(); 1411 } 1412 1413 static void 1414 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1415 struct skb_shared_hwtstamps *hwtstamps) 1416 { 1417 unsigned long flags; 1418 u64 ns; 1419 1420 spin_lock_irqsave(&fep->tmreg_lock, flags); 1421 ns = timecounter_cyc2time(&fep->tc, ts); 1422 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1423 1424 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1425 hwtstamps->hwtstamp = ns_to_ktime(ns); 1426 } 1427 1428 static void 1429 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id, int budget) 1430 { 1431 struct fec_enet_private *fep; 1432 struct xdp_frame *xdpf; 1433 struct bufdesc *bdp; 1434 unsigned short status; 1435 struct sk_buff *skb; 1436 struct fec_enet_priv_tx_q *txq; 1437 struct netdev_queue *nq; 1438 int index = 0; 1439 int entries_free; 1440 struct page *page; 1441 int frame_len; 1442 1443 fep = netdev_priv(ndev); 1444 1445 txq = fep->tx_queue[queue_id]; 1446 /* get next bdp of dirty_tx */ 1447 nq = netdev_get_tx_queue(ndev, queue_id); 1448 bdp = txq->dirty_tx; 1449 1450 /* get next bdp of dirty_tx */ 1451 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1452 1453 while (bdp != READ_ONCE(txq->bd.cur)) { 1454 /* Order the load of bd.cur and cbd_sc */ 1455 rmb(); 1456 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1457 if (status & BD_ENET_TX_READY) 1458 break; 1459 1460 index = fec_enet_get_bd_index(bdp, &txq->bd); 1461 1462 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1463 skb = txq->tx_buf[index].buf_p; 1464 if (bdp->cbd_bufaddr && 1465 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1466 dma_unmap_single(&fep->pdev->dev, 1467 fec32_to_cpu(bdp->cbd_bufaddr), 1468 fec16_to_cpu(bdp->cbd_datlen), 1469 DMA_TO_DEVICE); 1470 bdp->cbd_bufaddr = cpu_to_fec32(0); 1471 if (!skb) 1472 goto tx_buf_done; 1473 } else { 1474 /* Tx processing cannot call any XDP (or page pool) APIs if 1475 * the "budget" is 0. Because NAPI is called with budget of 1476 * 0 (such as netpoll) indicates we may be in an IRQ context, 1477 * however, we can't use the page pool from IRQ context. 1478 */ 1479 if (unlikely(!budget)) 1480 break; 1481 1482 if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1483 xdpf = txq->tx_buf[index].buf_p; 1484 if (bdp->cbd_bufaddr) 1485 dma_unmap_single(&fep->pdev->dev, 1486 fec32_to_cpu(bdp->cbd_bufaddr), 1487 fec16_to_cpu(bdp->cbd_datlen), 1488 DMA_TO_DEVICE); 1489 } else { 1490 page = txq->tx_buf[index].buf_p; 1491 } 1492 1493 bdp->cbd_bufaddr = cpu_to_fec32(0); 1494 if (unlikely(!txq->tx_buf[index].buf_p)) { 1495 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1496 goto tx_buf_done; 1497 } 1498 1499 frame_len = fec16_to_cpu(bdp->cbd_datlen); 1500 } 1501 1502 /* Check for errors. */ 1503 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1504 BD_ENET_TX_RL | BD_ENET_TX_UN | 1505 BD_ENET_TX_CSL)) { 1506 ndev->stats.tx_errors++; 1507 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1508 ndev->stats.tx_heartbeat_errors++; 1509 if (status & BD_ENET_TX_LC) /* Late collision */ 1510 ndev->stats.tx_window_errors++; 1511 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1512 ndev->stats.tx_aborted_errors++; 1513 if (status & BD_ENET_TX_UN) /* Underrun */ 1514 ndev->stats.tx_fifo_errors++; 1515 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1516 ndev->stats.tx_carrier_errors++; 1517 } else { 1518 ndev->stats.tx_packets++; 1519 1520 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) 1521 ndev->stats.tx_bytes += skb->len; 1522 else 1523 ndev->stats.tx_bytes += frame_len; 1524 } 1525 1526 /* Deferred means some collisions occurred during transmit, 1527 * but we eventually sent the packet OK. 1528 */ 1529 if (status & BD_ENET_TX_DEF) 1530 ndev->stats.collisions++; 1531 1532 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1533 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1534 * are to time stamp the packet, so we still need to check time 1535 * stamping enabled flag. 1536 */ 1537 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1538 fep->hwts_tx_en) && fep->bufdesc_ex) { 1539 struct skb_shared_hwtstamps shhwtstamps; 1540 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1541 1542 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1543 skb_tstamp_tx(skb, &shhwtstamps); 1544 } 1545 1546 /* Free the sk buffer associated with this last transmit */ 1547 napi_consume_skb(skb, budget); 1548 } else if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1549 xdp_return_frame_rx_napi(xdpf); 1550 } else { /* recycle pages of XDP_TX frames */ 1551 /* The dma_sync_size = 0 as XDP_TX has already synced DMA for_device */ 1552 page_pool_put_page(page->pp, page, 0, true); 1553 } 1554 1555 txq->tx_buf[index].buf_p = NULL; 1556 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1557 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1558 1559 tx_buf_done: 1560 /* Make sure the update to bdp and tx_buf are performed 1561 * before dirty_tx 1562 */ 1563 wmb(); 1564 txq->dirty_tx = bdp; 1565 1566 /* Update pointer to next buffer descriptor to be transmitted */ 1567 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1568 1569 /* Since we have freed up a buffer, the ring is no longer full 1570 */ 1571 if (netif_tx_queue_stopped(nq)) { 1572 entries_free = fec_enet_get_free_txdesc_num(txq); 1573 if (entries_free >= txq->tx_wake_threshold) 1574 netif_tx_wake_queue(nq); 1575 } 1576 } 1577 1578 /* ERR006358: Keep the transmitter going */ 1579 if (bdp != txq->bd.cur && 1580 readl(txq->bd.reg_desc_active) == 0) 1581 writel(0, txq->bd.reg_desc_active); 1582 } 1583 1584 static void fec_enet_tx(struct net_device *ndev, int budget) 1585 { 1586 struct fec_enet_private *fep = netdev_priv(ndev); 1587 int i; 1588 1589 /* Make sure that AVB queues are processed first. */ 1590 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1591 fec_enet_tx_queue(ndev, i, budget); 1592 } 1593 1594 static void fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq, 1595 struct bufdesc *bdp, int index) 1596 { 1597 struct page *new_page; 1598 dma_addr_t phys_addr; 1599 1600 new_page = page_pool_dev_alloc_pages(rxq->page_pool); 1601 WARN_ON(!new_page); 1602 rxq->rx_skb_info[index].page = new_page; 1603 1604 rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM; 1605 phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM; 1606 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 1607 } 1608 1609 static u32 1610 fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog, 1611 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int cpu) 1612 { 1613 unsigned int sync, len = xdp->data_end - xdp->data; 1614 u32 ret = FEC_ENET_XDP_PASS; 1615 struct page *page; 1616 int err; 1617 u32 act; 1618 1619 act = bpf_prog_run_xdp(prog, xdp); 1620 1621 /* Due xdp_adjust_tail and xdp_adjust_head: DMA sync for_device cover 1622 * max len CPU touch 1623 */ 1624 sync = xdp->data_end - xdp->data; 1625 sync = max(sync, len); 1626 1627 switch (act) { 1628 case XDP_PASS: 1629 rxq->stats[RX_XDP_PASS]++; 1630 ret = FEC_ENET_XDP_PASS; 1631 break; 1632 1633 case XDP_REDIRECT: 1634 rxq->stats[RX_XDP_REDIRECT]++; 1635 err = xdp_do_redirect(fep->netdev, xdp, prog); 1636 if (unlikely(err)) 1637 goto xdp_err; 1638 1639 ret = FEC_ENET_XDP_REDIR; 1640 break; 1641 1642 case XDP_TX: 1643 rxq->stats[RX_XDP_TX]++; 1644 err = fec_enet_xdp_tx_xmit(fep, cpu, xdp, sync); 1645 if (unlikely(err)) { 1646 rxq->stats[RX_XDP_TX_ERRORS]++; 1647 goto xdp_err; 1648 } 1649 1650 ret = FEC_ENET_XDP_TX; 1651 break; 1652 1653 default: 1654 bpf_warn_invalid_xdp_action(fep->netdev, prog, act); 1655 fallthrough; 1656 1657 case XDP_ABORTED: 1658 fallthrough; /* handle aborts by dropping packet */ 1659 1660 case XDP_DROP: 1661 rxq->stats[RX_XDP_DROP]++; 1662 xdp_err: 1663 ret = FEC_ENET_XDP_CONSUMED; 1664 page = virt_to_head_page(xdp->data); 1665 page_pool_put_page(rxq->page_pool, page, sync, true); 1666 if (act != XDP_DROP) 1667 trace_xdp_exception(fep->netdev, prog, act); 1668 break; 1669 } 1670 1671 return ret; 1672 } 1673 1674 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1675 * When we update through the ring, if the next incoming buffer has 1676 * not been given to the system, we just set the empty indicator, 1677 * effectively tossing the packet. 1678 */ 1679 static int 1680 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1681 { 1682 struct fec_enet_private *fep = netdev_priv(ndev); 1683 struct fec_enet_priv_rx_q *rxq; 1684 struct bufdesc *bdp; 1685 unsigned short status; 1686 struct sk_buff *skb; 1687 ushort pkt_len; 1688 __u8 *data; 1689 int pkt_received = 0; 1690 struct bufdesc_ex *ebdp = NULL; 1691 bool vlan_packet_rcvd = false; 1692 u16 vlan_tag; 1693 int index = 0; 1694 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1695 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 1696 u32 ret, xdp_result = FEC_ENET_XDP_PASS; 1697 u32 data_start = FEC_ENET_XDP_HEADROOM; 1698 int cpu = smp_processor_id(); 1699 struct xdp_buff xdp; 1700 struct page *page; 1701 u32 sub_len = 4; 1702 1703 #if !defined(CONFIG_M5272) 1704 /*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of 1705 * FEC_RACC_SHIFT16 is set by default in the probe function. 1706 */ 1707 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1708 data_start += 2; 1709 sub_len += 2; 1710 } 1711 #endif 1712 1713 #if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA) 1714 /* 1715 * Hacky flush of all caches instead of using the DMA API for the TSO 1716 * headers. 1717 */ 1718 flush_cache_all(); 1719 #endif 1720 rxq = fep->rx_queue[queue_id]; 1721 1722 /* First, grab all of the stats for the incoming packet. 1723 * These get messed up if we get called due to a busy condition. 1724 */ 1725 bdp = rxq->bd.cur; 1726 xdp_init_buff(&xdp, PAGE_SIZE, &rxq->xdp_rxq); 1727 1728 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1729 1730 if (pkt_received >= budget) 1731 break; 1732 pkt_received++; 1733 1734 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT); 1735 1736 /* Check for errors. */ 1737 status ^= BD_ENET_RX_LAST; 1738 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1739 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1740 BD_ENET_RX_CL)) { 1741 ndev->stats.rx_errors++; 1742 if (status & BD_ENET_RX_OV) { 1743 /* FIFO overrun */ 1744 ndev->stats.rx_fifo_errors++; 1745 goto rx_processing_done; 1746 } 1747 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1748 | BD_ENET_RX_LAST)) { 1749 /* Frame too long or too short. */ 1750 ndev->stats.rx_length_errors++; 1751 if (status & BD_ENET_RX_LAST) 1752 netdev_err(ndev, "rcv is not +last\n"); 1753 } 1754 if (status & BD_ENET_RX_CR) /* CRC Error */ 1755 ndev->stats.rx_crc_errors++; 1756 /* Report late collisions as a frame error. */ 1757 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1758 ndev->stats.rx_frame_errors++; 1759 goto rx_processing_done; 1760 } 1761 1762 /* Process the incoming frame. */ 1763 ndev->stats.rx_packets++; 1764 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1765 ndev->stats.rx_bytes += pkt_len; 1766 1767 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1768 page = rxq->rx_skb_info[index].page; 1769 dma_sync_single_for_cpu(&fep->pdev->dev, 1770 fec32_to_cpu(bdp->cbd_bufaddr), 1771 pkt_len, 1772 DMA_FROM_DEVICE); 1773 prefetch(page_address(page)); 1774 fec_enet_update_cbd(rxq, bdp, index); 1775 1776 if (xdp_prog) { 1777 xdp_buff_clear_frags_flag(&xdp); 1778 /* subtract 16bit shift and FCS */ 1779 xdp_prepare_buff(&xdp, page_address(page), 1780 data_start, pkt_len - sub_len, false); 1781 ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, cpu); 1782 xdp_result |= ret; 1783 if (ret != FEC_ENET_XDP_PASS) 1784 goto rx_processing_done; 1785 } 1786 1787 /* The packet length includes FCS, but we don't want to 1788 * include that when passing upstream as it messes up 1789 * bridging applications. 1790 */ 1791 skb = build_skb(page_address(page), PAGE_SIZE); 1792 if (unlikely(!skb)) { 1793 page_pool_recycle_direct(rxq->page_pool, page); 1794 ndev->stats.rx_dropped++; 1795 1796 netdev_err_once(ndev, "build_skb failed!\n"); 1797 goto rx_processing_done; 1798 } 1799 1800 skb_reserve(skb, data_start); 1801 skb_put(skb, pkt_len - sub_len); 1802 skb_mark_for_recycle(skb); 1803 1804 if (unlikely(need_swap)) { 1805 data = page_address(page) + FEC_ENET_XDP_HEADROOM; 1806 swap_buffer(data, pkt_len); 1807 } 1808 data = skb->data; 1809 1810 /* Extract the enhanced buffer descriptor */ 1811 ebdp = NULL; 1812 if (fep->bufdesc_ex) 1813 ebdp = (struct bufdesc_ex *)bdp; 1814 1815 /* If this is a VLAN packet remove the VLAN Tag */ 1816 vlan_packet_rcvd = false; 1817 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1818 fep->bufdesc_ex && 1819 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1820 /* Push and remove the vlan tag */ 1821 struct vlan_hdr *vlan_header = 1822 (struct vlan_hdr *) (data + ETH_HLEN); 1823 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1824 1825 vlan_packet_rcvd = true; 1826 1827 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1828 skb_pull(skb, VLAN_HLEN); 1829 } 1830 1831 skb->protocol = eth_type_trans(skb, ndev); 1832 1833 /* Get receive timestamp from the skb */ 1834 if (fep->hwts_rx_en && fep->bufdesc_ex) 1835 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1836 skb_hwtstamps(skb)); 1837 1838 if (fep->bufdesc_ex && 1839 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1840 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1841 /* don't check it */ 1842 skb->ip_summed = CHECKSUM_UNNECESSARY; 1843 } else { 1844 skb_checksum_none_assert(skb); 1845 } 1846 } 1847 1848 /* Handle received VLAN packets */ 1849 if (vlan_packet_rcvd) 1850 __vlan_hwaccel_put_tag(skb, 1851 htons(ETH_P_8021Q), 1852 vlan_tag); 1853 1854 skb_record_rx_queue(skb, queue_id); 1855 napi_gro_receive(&fep->napi, skb); 1856 1857 rx_processing_done: 1858 /* Clear the status flags for this buffer */ 1859 status &= ~BD_ENET_RX_STATS; 1860 1861 /* Mark the buffer empty */ 1862 status |= BD_ENET_RX_EMPTY; 1863 1864 if (fep->bufdesc_ex) { 1865 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1866 1867 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1868 ebdp->cbd_prot = 0; 1869 ebdp->cbd_bdu = 0; 1870 } 1871 /* Make sure the updates to rest of the descriptor are 1872 * performed before transferring ownership. 1873 */ 1874 wmb(); 1875 bdp->cbd_sc = cpu_to_fec16(status); 1876 1877 /* Update BD pointer to next entry */ 1878 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1879 1880 /* Doing this here will keep the FEC running while we process 1881 * incoming frames. On a heavily loaded network, we should be 1882 * able to keep up at the expense of system resources. 1883 */ 1884 writel(0, rxq->bd.reg_desc_active); 1885 } 1886 rxq->bd.cur = bdp; 1887 1888 if (xdp_result & FEC_ENET_XDP_REDIR) 1889 xdp_do_flush(); 1890 1891 return pkt_received; 1892 } 1893 1894 static int fec_enet_rx(struct net_device *ndev, int budget) 1895 { 1896 struct fec_enet_private *fep = netdev_priv(ndev); 1897 int i, done = 0; 1898 1899 /* Make sure that AVB queues are processed first. */ 1900 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1901 done += fec_enet_rx_queue(ndev, budget - done, i); 1902 1903 return done; 1904 } 1905 1906 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1907 { 1908 uint int_events; 1909 1910 int_events = readl(fep->hwp + FEC_IEVENT); 1911 1912 /* Don't clear MDIO events, we poll for those */ 1913 int_events &= ~FEC_ENET_MII; 1914 1915 writel(int_events, fep->hwp + FEC_IEVENT); 1916 1917 return int_events != 0; 1918 } 1919 1920 static irqreturn_t 1921 fec_enet_interrupt(int irq, void *dev_id) 1922 { 1923 struct net_device *ndev = dev_id; 1924 struct fec_enet_private *fep = netdev_priv(ndev); 1925 irqreturn_t ret = IRQ_NONE; 1926 1927 if (fec_enet_collect_events(fep) && fep->link) { 1928 ret = IRQ_HANDLED; 1929 1930 if (napi_schedule_prep(&fep->napi)) { 1931 /* Disable interrupts */ 1932 writel(0, fep->hwp + FEC_IMASK); 1933 __napi_schedule(&fep->napi); 1934 } 1935 } 1936 1937 return ret; 1938 } 1939 1940 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1941 { 1942 struct net_device *ndev = napi->dev; 1943 struct fec_enet_private *fep = netdev_priv(ndev); 1944 int done = 0; 1945 1946 do { 1947 done += fec_enet_rx(ndev, budget - done); 1948 fec_enet_tx(ndev, budget); 1949 } while ((done < budget) && fec_enet_collect_events(fep)); 1950 1951 if (done < budget) { 1952 napi_complete_done(napi, done); 1953 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1954 } 1955 1956 return done; 1957 } 1958 1959 /* ------------------------------------------------------------------------- */ 1960 static int fec_get_mac(struct net_device *ndev) 1961 { 1962 struct fec_enet_private *fep = netdev_priv(ndev); 1963 unsigned char *iap, tmpaddr[ETH_ALEN]; 1964 int ret; 1965 1966 /* 1967 * try to get mac address in following order: 1968 * 1969 * 1) module parameter via kernel command line in form 1970 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1971 */ 1972 iap = macaddr; 1973 1974 /* 1975 * 2) from device tree data 1976 */ 1977 if (!is_valid_ether_addr(iap)) { 1978 struct device_node *np = fep->pdev->dev.of_node; 1979 if (np) { 1980 ret = of_get_mac_address(np, tmpaddr); 1981 if (!ret) 1982 iap = tmpaddr; 1983 else if (ret == -EPROBE_DEFER) 1984 return ret; 1985 } 1986 } 1987 1988 /* 1989 * 3) from flash or fuse (via platform data) 1990 */ 1991 if (!is_valid_ether_addr(iap)) { 1992 #ifdef CONFIG_M5272 1993 if (FEC_FLASHMAC) 1994 iap = (unsigned char *)FEC_FLASHMAC; 1995 #else 1996 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1997 1998 if (pdata) 1999 iap = (unsigned char *)&pdata->mac; 2000 #endif 2001 } 2002 2003 /* 2004 * 4) FEC mac registers set by bootloader 2005 */ 2006 if (!is_valid_ether_addr(iap)) { 2007 *((__be32 *) &tmpaddr[0]) = 2008 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 2009 *((__be16 *) &tmpaddr[4]) = 2010 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 2011 iap = &tmpaddr[0]; 2012 } 2013 2014 /* 2015 * 5) random mac address 2016 */ 2017 if (!is_valid_ether_addr(iap)) { 2018 /* Report it and use a random ethernet address instead */ 2019 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 2020 eth_hw_addr_random(ndev); 2021 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 2022 ndev->dev_addr); 2023 return 0; 2024 } 2025 2026 /* Adjust MAC if using macaddr */ 2027 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0); 2028 2029 return 0; 2030 } 2031 2032 /* ------------------------------------------------------------------------- */ 2033 2034 /* 2035 * Phy section 2036 */ 2037 2038 /* LPI Sleep Ts count base on tx clk (clk_ref). 2039 * The lpi sleep cnt value = X us / (cycle_ns). 2040 */ 2041 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) 2042 { 2043 struct fec_enet_private *fep = netdev_priv(ndev); 2044 2045 return us * (fep->clk_ref_rate / 1000) / 1000; 2046 } 2047 2048 static int fec_enet_eee_mode_set(struct net_device *ndev, u32 lpi_timer, 2049 bool enable) 2050 { 2051 struct fec_enet_private *fep = netdev_priv(ndev); 2052 unsigned int sleep_cycle, wake_cycle; 2053 2054 if (enable) { 2055 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, lpi_timer); 2056 wake_cycle = sleep_cycle; 2057 } else { 2058 sleep_cycle = 0; 2059 wake_cycle = 0; 2060 } 2061 2062 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); 2063 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); 2064 2065 return 0; 2066 } 2067 2068 static void fec_enet_adjust_link(struct net_device *ndev) 2069 { 2070 struct fec_enet_private *fep = netdev_priv(ndev); 2071 struct phy_device *phy_dev = ndev->phydev; 2072 int status_change = 0; 2073 2074 /* 2075 * If the netdev is down, or is going down, we're not interested 2076 * in link state events, so just mark our idea of the link as down 2077 * and ignore the event. 2078 */ 2079 if (!netif_running(ndev) || !netif_device_present(ndev)) { 2080 fep->link = 0; 2081 } else if (phy_dev->link) { 2082 if (!fep->link) { 2083 fep->link = phy_dev->link; 2084 status_change = 1; 2085 } 2086 2087 if (fep->full_duplex != phy_dev->duplex) { 2088 fep->full_duplex = phy_dev->duplex; 2089 status_change = 1; 2090 } 2091 2092 if (phy_dev->speed != fep->speed) { 2093 fep->speed = phy_dev->speed; 2094 status_change = 1; 2095 } 2096 2097 /* if any of the above changed restart the FEC */ 2098 if (status_change) { 2099 netif_stop_queue(ndev); 2100 napi_disable(&fep->napi); 2101 netif_tx_lock_bh(ndev); 2102 fec_restart(ndev); 2103 netif_tx_wake_all_queues(ndev); 2104 netif_tx_unlock_bh(ndev); 2105 napi_enable(&fep->napi); 2106 } 2107 if (fep->quirks & FEC_QUIRK_HAS_EEE) 2108 fec_enet_eee_mode_set(ndev, 2109 phy_dev->eee_cfg.tx_lpi_timer, 2110 phy_dev->enable_tx_lpi); 2111 } else { 2112 if (fep->link) { 2113 netif_stop_queue(ndev); 2114 napi_disable(&fep->napi); 2115 netif_tx_lock_bh(ndev); 2116 fec_stop(ndev); 2117 netif_tx_unlock_bh(ndev); 2118 napi_enable(&fep->napi); 2119 fep->link = phy_dev->link; 2120 status_change = 1; 2121 } 2122 } 2123 2124 if (status_change) 2125 phy_print_status(phy_dev); 2126 } 2127 2128 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 2129 { 2130 uint ievent; 2131 int ret; 2132 2133 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 2134 ievent & FEC_ENET_MII, 2, 30000); 2135 2136 if (!ret) 2137 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2138 2139 return ret; 2140 } 2141 2142 static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) 2143 { 2144 struct fec_enet_private *fep = bus->priv; 2145 struct device *dev = &fep->pdev->dev; 2146 int ret = 0, frame_start, frame_addr, frame_op; 2147 2148 ret = pm_runtime_resume_and_get(dev); 2149 if (ret < 0) 2150 return ret; 2151 2152 /* C22 read */ 2153 frame_op = FEC_MMFR_OP_READ; 2154 frame_start = FEC_MMFR_ST; 2155 frame_addr = regnum; 2156 2157 /* start a read op */ 2158 writel(frame_start | frame_op | 2159 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2160 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2161 2162 /* wait for end of transfer */ 2163 ret = fec_enet_mdio_wait(fep); 2164 if (ret) { 2165 netdev_err(fep->netdev, "MDIO read timeout\n"); 2166 goto out; 2167 } 2168 2169 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2170 2171 out: 2172 pm_runtime_mark_last_busy(dev); 2173 pm_runtime_put_autosuspend(dev); 2174 2175 return ret; 2176 } 2177 2178 static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id, 2179 int devad, int regnum) 2180 { 2181 struct fec_enet_private *fep = bus->priv; 2182 struct device *dev = &fep->pdev->dev; 2183 int ret = 0, frame_start, frame_op; 2184 2185 ret = pm_runtime_resume_and_get(dev); 2186 if (ret < 0) 2187 return ret; 2188 2189 frame_start = FEC_MMFR_ST_C45; 2190 2191 /* write address */ 2192 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2193 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2194 FEC_MMFR_TA | (regnum & 0xFFFF), 2195 fep->hwp + FEC_MII_DATA); 2196 2197 /* wait for end of transfer */ 2198 ret = fec_enet_mdio_wait(fep); 2199 if (ret) { 2200 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2201 goto out; 2202 } 2203 2204 frame_op = FEC_MMFR_OP_READ_C45; 2205 2206 /* start a read op */ 2207 writel(frame_start | frame_op | 2208 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2209 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2210 2211 /* wait for end of transfer */ 2212 ret = fec_enet_mdio_wait(fep); 2213 if (ret) { 2214 netdev_err(fep->netdev, "MDIO read timeout\n"); 2215 goto out; 2216 } 2217 2218 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2219 2220 out: 2221 pm_runtime_mark_last_busy(dev); 2222 pm_runtime_put_autosuspend(dev); 2223 2224 return ret; 2225 } 2226 2227 static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, 2228 u16 value) 2229 { 2230 struct fec_enet_private *fep = bus->priv; 2231 struct device *dev = &fep->pdev->dev; 2232 int ret, frame_start, frame_addr; 2233 2234 ret = pm_runtime_resume_and_get(dev); 2235 if (ret < 0) 2236 return ret; 2237 2238 /* C22 write */ 2239 frame_start = FEC_MMFR_ST; 2240 frame_addr = regnum; 2241 2242 /* start a write op */ 2243 writel(frame_start | FEC_MMFR_OP_WRITE | 2244 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2245 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2246 fep->hwp + FEC_MII_DATA); 2247 2248 /* wait for end of transfer */ 2249 ret = fec_enet_mdio_wait(fep); 2250 if (ret) 2251 netdev_err(fep->netdev, "MDIO write timeout\n"); 2252 2253 pm_runtime_mark_last_busy(dev); 2254 pm_runtime_put_autosuspend(dev); 2255 2256 return ret; 2257 } 2258 2259 static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id, 2260 int devad, int regnum, u16 value) 2261 { 2262 struct fec_enet_private *fep = bus->priv; 2263 struct device *dev = &fep->pdev->dev; 2264 int ret, frame_start; 2265 2266 ret = pm_runtime_resume_and_get(dev); 2267 if (ret < 0) 2268 return ret; 2269 2270 frame_start = FEC_MMFR_ST_C45; 2271 2272 /* write address */ 2273 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2274 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2275 FEC_MMFR_TA | (regnum & 0xFFFF), 2276 fep->hwp + FEC_MII_DATA); 2277 2278 /* wait for end of transfer */ 2279 ret = fec_enet_mdio_wait(fep); 2280 if (ret) { 2281 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2282 goto out; 2283 } 2284 2285 /* start a write op */ 2286 writel(frame_start | FEC_MMFR_OP_WRITE | 2287 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2288 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2289 fep->hwp + FEC_MII_DATA); 2290 2291 /* wait for end of transfer */ 2292 ret = fec_enet_mdio_wait(fep); 2293 if (ret) 2294 netdev_err(fep->netdev, "MDIO write timeout\n"); 2295 2296 out: 2297 pm_runtime_mark_last_busy(dev); 2298 pm_runtime_put_autosuspend(dev); 2299 2300 return ret; 2301 } 2302 2303 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 2304 { 2305 struct fec_enet_private *fep = netdev_priv(ndev); 2306 struct phy_device *phy_dev = ndev->phydev; 2307 2308 if (phy_dev) { 2309 phy_reset_after_clk_enable(phy_dev); 2310 } else if (fep->phy_node) { 2311 /* 2312 * If the PHY still is not bound to the MAC, but there is 2313 * OF PHY node and a matching PHY device instance already, 2314 * use the OF PHY node to obtain the PHY device instance, 2315 * and then use that PHY device instance when triggering 2316 * the PHY reset. 2317 */ 2318 phy_dev = of_phy_find_device(fep->phy_node); 2319 phy_reset_after_clk_enable(phy_dev); 2320 put_device(&phy_dev->mdio.dev); 2321 } 2322 } 2323 2324 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 2325 { 2326 struct fec_enet_private *fep = netdev_priv(ndev); 2327 int ret; 2328 2329 if (enable) { 2330 ret = clk_prepare_enable(fep->clk_enet_out); 2331 if (ret) 2332 return ret; 2333 2334 if (fep->clk_ptp) { 2335 mutex_lock(&fep->ptp_clk_mutex); 2336 ret = clk_prepare_enable(fep->clk_ptp); 2337 if (ret) { 2338 mutex_unlock(&fep->ptp_clk_mutex); 2339 goto failed_clk_ptp; 2340 } else { 2341 fep->ptp_clk_on = true; 2342 } 2343 mutex_unlock(&fep->ptp_clk_mutex); 2344 } 2345 2346 ret = clk_prepare_enable(fep->clk_ref); 2347 if (ret) 2348 goto failed_clk_ref; 2349 2350 ret = clk_prepare_enable(fep->clk_2x_txclk); 2351 if (ret) 2352 goto failed_clk_2x_txclk; 2353 2354 fec_enet_phy_reset_after_clk_enable(ndev); 2355 } else { 2356 clk_disable_unprepare(fep->clk_enet_out); 2357 if (fep->clk_ptp) { 2358 mutex_lock(&fep->ptp_clk_mutex); 2359 clk_disable_unprepare(fep->clk_ptp); 2360 fep->ptp_clk_on = false; 2361 mutex_unlock(&fep->ptp_clk_mutex); 2362 } 2363 clk_disable_unprepare(fep->clk_ref); 2364 clk_disable_unprepare(fep->clk_2x_txclk); 2365 } 2366 2367 return 0; 2368 2369 failed_clk_2x_txclk: 2370 if (fep->clk_ref) 2371 clk_disable_unprepare(fep->clk_ref); 2372 failed_clk_ref: 2373 if (fep->clk_ptp) { 2374 mutex_lock(&fep->ptp_clk_mutex); 2375 clk_disable_unprepare(fep->clk_ptp); 2376 fep->ptp_clk_on = false; 2377 mutex_unlock(&fep->ptp_clk_mutex); 2378 } 2379 failed_clk_ptp: 2380 clk_disable_unprepare(fep->clk_enet_out); 2381 2382 return ret; 2383 } 2384 2385 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep, 2386 struct device_node *np) 2387 { 2388 u32 rgmii_tx_delay, rgmii_rx_delay; 2389 2390 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ 2391 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { 2392 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) { 2393 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); 2394 return -EINVAL; 2395 } else if (rgmii_tx_delay == 2000) { 2396 fep->rgmii_txc_dly = true; 2397 } 2398 } 2399 2400 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */ 2401 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { 2402 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) { 2403 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); 2404 return -EINVAL; 2405 } else if (rgmii_rx_delay == 2000) { 2406 fep->rgmii_rxc_dly = true; 2407 } 2408 } 2409 2410 return 0; 2411 } 2412 2413 static int fec_enet_mii_probe(struct net_device *ndev) 2414 { 2415 struct fec_enet_private *fep = netdev_priv(ndev); 2416 struct phy_device *phy_dev = NULL; 2417 char mdio_bus_id[MII_BUS_ID_SIZE]; 2418 char phy_name[MII_BUS_ID_SIZE + 3]; 2419 int phy_id; 2420 int dev_id = fep->dev_id; 2421 2422 if (fep->phy_node) { 2423 phy_dev = of_phy_connect(ndev, fep->phy_node, 2424 &fec_enet_adjust_link, 0, 2425 fep->phy_interface); 2426 if (!phy_dev) { 2427 netdev_err(ndev, "Unable to connect to phy\n"); 2428 return -ENODEV; 2429 } 2430 } else { 2431 /* check for attached phy */ 2432 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2433 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2434 continue; 2435 if (dev_id--) 2436 continue; 2437 strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2438 break; 2439 } 2440 2441 if (phy_id >= PHY_MAX_ADDR) { 2442 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2443 strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2444 phy_id = 0; 2445 } 2446 2447 snprintf(phy_name, sizeof(phy_name), 2448 PHY_ID_FMT, mdio_bus_id, phy_id); 2449 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2450 fep->phy_interface); 2451 } 2452 2453 if (IS_ERR(phy_dev)) { 2454 netdev_err(ndev, "could not attach to PHY\n"); 2455 return PTR_ERR(phy_dev); 2456 } 2457 2458 /* mask with MAC supported features */ 2459 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2460 phy_set_max_speed(phy_dev, 1000); 2461 phy_remove_link_mode(phy_dev, 2462 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2463 #if !defined(CONFIG_M5272) 2464 phy_support_sym_pause(phy_dev); 2465 #endif 2466 } 2467 else 2468 phy_set_max_speed(phy_dev, 100); 2469 2470 if (fep->quirks & FEC_QUIRK_HAS_EEE) 2471 phy_support_eee(phy_dev); 2472 2473 fep->link = 0; 2474 fep->full_duplex = 0; 2475 2476 phy_attached_info(phy_dev); 2477 2478 return 0; 2479 } 2480 2481 static int fec_enet_mii_init(struct platform_device *pdev) 2482 { 2483 static struct mii_bus *fec0_mii_bus; 2484 struct net_device *ndev = platform_get_drvdata(pdev); 2485 struct fec_enet_private *fep = netdev_priv(ndev); 2486 bool suppress_preamble = false; 2487 struct phy_device *phydev; 2488 struct device_node *node; 2489 int err = -ENXIO; 2490 u32 mii_speed, holdtime; 2491 u32 bus_freq; 2492 int addr; 2493 2494 /* 2495 * The i.MX28 dual fec interfaces are not equal. 2496 * Here are the differences: 2497 * 2498 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2499 * - fec0 acts as the 1588 time master while fec1 is slave 2500 * - external phys can only be configured by fec0 2501 * 2502 * That is to say fec1 can not work independently. It only works 2503 * when fec0 is working. The reason behind this design is that the 2504 * second interface is added primarily for Switch mode. 2505 * 2506 * Because of the last point above, both phys are attached on fec0 2507 * mdio interface in board design, and need to be configured by 2508 * fec0 mii_bus. 2509 */ 2510 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2511 /* fec1 uses fec0 mii_bus */ 2512 if (mii_cnt && fec0_mii_bus) { 2513 fep->mii_bus = fec0_mii_bus; 2514 mii_cnt++; 2515 return 0; 2516 } 2517 return -ENOENT; 2518 } 2519 2520 bus_freq = 2500000; /* 2.5MHz by default */ 2521 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2522 if (node) { 2523 of_property_read_u32(node, "clock-frequency", &bus_freq); 2524 suppress_preamble = of_property_read_bool(node, 2525 "suppress-preamble"); 2526 } 2527 2528 /* 2529 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2530 * 2531 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2532 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2533 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2534 * document. 2535 */ 2536 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2537 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2538 mii_speed--; 2539 if (mii_speed > 63) { 2540 dev_err(&pdev->dev, 2541 "fec clock (%lu) too fast to get right mii speed\n", 2542 clk_get_rate(fep->clk_ipg)); 2543 err = -EINVAL; 2544 goto err_out; 2545 } 2546 2547 /* 2548 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2549 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2550 * versions are RAZ there, so just ignore the difference and write the 2551 * register always. 2552 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2553 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2554 * output. 2555 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2556 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2557 * holdtime cannot result in a value greater than 3. 2558 */ 2559 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2560 2561 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2562 2563 if (suppress_preamble) 2564 fep->phy_speed |= BIT(7); 2565 2566 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2567 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2568 * MII event generation condition: 2569 * - writing MSCR: 2570 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2571 * mscr_reg_data_in[7:0] != 0 2572 * - writing MMFR: 2573 * - mscr[7:0]_not_zero 2574 */ 2575 writel(0, fep->hwp + FEC_MII_DATA); 2576 } 2577 2578 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2579 2580 /* Clear any pending transaction complete indication */ 2581 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2582 2583 fep->mii_bus = mdiobus_alloc(); 2584 if (fep->mii_bus == NULL) { 2585 err = -ENOMEM; 2586 goto err_out; 2587 } 2588 2589 fep->mii_bus->name = "fec_enet_mii_bus"; 2590 fep->mii_bus->read = fec_enet_mdio_read_c22; 2591 fep->mii_bus->write = fec_enet_mdio_write_c22; 2592 if (fep->quirks & FEC_QUIRK_HAS_MDIO_C45) { 2593 fep->mii_bus->read_c45 = fec_enet_mdio_read_c45; 2594 fep->mii_bus->write_c45 = fec_enet_mdio_write_c45; 2595 } 2596 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2597 pdev->name, fep->dev_id + 1); 2598 fep->mii_bus->priv = fep; 2599 fep->mii_bus->parent = &pdev->dev; 2600 2601 err = of_mdiobus_register(fep->mii_bus, node); 2602 if (err) 2603 goto err_out_free_mdiobus; 2604 of_node_put(node); 2605 2606 /* find all the PHY devices on the bus and set mac_managed_pm to true */ 2607 for (addr = 0; addr < PHY_MAX_ADDR; addr++) { 2608 phydev = mdiobus_get_phy(fep->mii_bus, addr); 2609 if (phydev) 2610 phydev->mac_managed_pm = true; 2611 } 2612 2613 mii_cnt++; 2614 2615 /* save fec0 mii_bus */ 2616 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2617 fec0_mii_bus = fep->mii_bus; 2618 2619 return 0; 2620 2621 err_out_free_mdiobus: 2622 mdiobus_free(fep->mii_bus); 2623 err_out: 2624 of_node_put(node); 2625 return err; 2626 } 2627 2628 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2629 { 2630 if (--mii_cnt == 0) { 2631 mdiobus_unregister(fep->mii_bus); 2632 mdiobus_free(fep->mii_bus); 2633 } 2634 } 2635 2636 static void fec_enet_get_drvinfo(struct net_device *ndev, 2637 struct ethtool_drvinfo *info) 2638 { 2639 struct fec_enet_private *fep = netdev_priv(ndev); 2640 2641 strscpy(info->driver, fep->pdev->dev.driver->name, 2642 sizeof(info->driver)); 2643 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2644 } 2645 2646 static int fec_enet_get_regs_len(struct net_device *ndev) 2647 { 2648 struct fec_enet_private *fep = netdev_priv(ndev); 2649 struct resource *r; 2650 int s = 0; 2651 2652 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2653 if (r) 2654 s = resource_size(r); 2655 2656 return s; 2657 } 2658 2659 /* List of registers that can be safety be read to dump them with ethtool */ 2660 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2661 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2662 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2663 static __u32 fec_enet_register_version = 2; 2664 static u32 fec_enet_register_offset[] = { 2665 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2666 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2667 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2668 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2669 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2670 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2671 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2672 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2673 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2674 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2675 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2676 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2677 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2678 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2679 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2680 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2681 RMON_T_P_GTE2048, RMON_T_OCTETS, 2682 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2683 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2684 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2685 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2686 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2687 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2688 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2689 RMON_R_P_GTE2048, RMON_R_OCTETS, 2690 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2691 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2692 }; 2693 /* for i.MX6ul */ 2694 static u32 fec_enet_register_offset_6ul[] = { 2695 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2696 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2697 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0, 2698 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, 2699 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0, 2700 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2701 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, 2702 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2703 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2704 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2705 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2706 RMON_T_P_GTE2048, RMON_T_OCTETS, 2707 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2708 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2709 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2710 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2711 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2712 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2713 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2714 RMON_R_P_GTE2048, RMON_R_OCTETS, 2715 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2716 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2717 }; 2718 #else 2719 static __u32 fec_enet_register_version = 1; 2720 static u32 fec_enet_register_offset[] = { 2721 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2722 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2723 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2724 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2725 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2726 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2727 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2728 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2729 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2730 }; 2731 #endif 2732 2733 static void fec_enet_get_regs(struct net_device *ndev, 2734 struct ethtool_regs *regs, void *regbuf) 2735 { 2736 struct fec_enet_private *fep = netdev_priv(ndev); 2737 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2738 struct device *dev = &fep->pdev->dev; 2739 u32 *buf = (u32 *)regbuf; 2740 u32 i, off; 2741 int ret; 2742 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2743 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2744 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2745 u32 *reg_list; 2746 u32 reg_cnt; 2747 2748 if (!of_machine_is_compatible("fsl,imx6ul")) { 2749 reg_list = fec_enet_register_offset; 2750 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2751 } else { 2752 reg_list = fec_enet_register_offset_6ul; 2753 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul); 2754 } 2755 #else 2756 /* coldfire */ 2757 static u32 *reg_list = fec_enet_register_offset; 2758 static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2759 #endif 2760 ret = pm_runtime_resume_and_get(dev); 2761 if (ret < 0) 2762 return; 2763 2764 regs->version = fec_enet_register_version; 2765 2766 memset(buf, 0, regs->len); 2767 2768 for (i = 0; i < reg_cnt; i++) { 2769 off = reg_list[i]; 2770 2771 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2772 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2773 continue; 2774 2775 off >>= 2; 2776 buf[off] = readl(&theregs[off]); 2777 } 2778 2779 pm_runtime_mark_last_busy(dev); 2780 pm_runtime_put_autosuspend(dev); 2781 } 2782 2783 static int fec_enet_get_ts_info(struct net_device *ndev, 2784 struct kernel_ethtool_ts_info *info) 2785 { 2786 struct fec_enet_private *fep = netdev_priv(ndev); 2787 2788 if (fep->bufdesc_ex) { 2789 2790 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2791 SOF_TIMESTAMPING_TX_HARDWARE | 2792 SOF_TIMESTAMPING_RX_HARDWARE | 2793 SOF_TIMESTAMPING_RAW_HARDWARE; 2794 if (fep->ptp_clock) 2795 info->phc_index = ptp_clock_index(fep->ptp_clock); 2796 2797 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2798 (1 << HWTSTAMP_TX_ON); 2799 2800 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2801 (1 << HWTSTAMP_FILTER_ALL); 2802 return 0; 2803 } else { 2804 return ethtool_op_get_ts_info(ndev, info); 2805 } 2806 } 2807 2808 #if !defined(CONFIG_M5272) 2809 2810 static void fec_enet_get_pauseparam(struct net_device *ndev, 2811 struct ethtool_pauseparam *pause) 2812 { 2813 struct fec_enet_private *fep = netdev_priv(ndev); 2814 2815 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2816 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2817 pause->rx_pause = pause->tx_pause; 2818 } 2819 2820 static int fec_enet_set_pauseparam(struct net_device *ndev, 2821 struct ethtool_pauseparam *pause) 2822 { 2823 struct fec_enet_private *fep = netdev_priv(ndev); 2824 2825 if (!ndev->phydev) 2826 return -ENODEV; 2827 2828 if (pause->tx_pause != pause->rx_pause) { 2829 netdev_info(ndev, 2830 "hardware only support enable/disable both tx and rx"); 2831 return -EINVAL; 2832 } 2833 2834 fep->pause_flag = 0; 2835 2836 /* tx pause must be same as rx pause */ 2837 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2838 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2839 2840 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2841 pause->autoneg); 2842 2843 if (pause->autoneg) { 2844 if (netif_running(ndev)) 2845 fec_stop(ndev); 2846 phy_start_aneg(ndev->phydev); 2847 } 2848 if (netif_running(ndev)) { 2849 napi_disable(&fep->napi); 2850 netif_tx_lock_bh(ndev); 2851 fec_restart(ndev); 2852 netif_tx_wake_all_queues(ndev); 2853 netif_tx_unlock_bh(ndev); 2854 napi_enable(&fep->napi); 2855 } 2856 2857 return 0; 2858 } 2859 2860 static const struct fec_stat { 2861 char name[ETH_GSTRING_LEN]; 2862 u16 offset; 2863 } fec_stats[] = { 2864 /* RMON TX */ 2865 { "tx_dropped", RMON_T_DROP }, 2866 { "tx_packets", RMON_T_PACKETS }, 2867 { "tx_broadcast", RMON_T_BC_PKT }, 2868 { "tx_multicast", RMON_T_MC_PKT }, 2869 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2870 { "tx_undersize", RMON_T_UNDERSIZE }, 2871 { "tx_oversize", RMON_T_OVERSIZE }, 2872 { "tx_fragment", RMON_T_FRAG }, 2873 { "tx_jabber", RMON_T_JAB }, 2874 { "tx_collision", RMON_T_COL }, 2875 { "tx_64byte", RMON_T_P64 }, 2876 { "tx_65to127byte", RMON_T_P65TO127 }, 2877 { "tx_128to255byte", RMON_T_P128TO255 }, 2878 { "tx_256to511byte", RMON_T_P256TO511 }, 2879 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2880 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2881 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2882 { "tx_octets", RMON_T_OCTETS }, 2883 2884 /* IEEE TX */ 2885 { "IEEE_tx_drop", IEEE_T_DROP }, 2886 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2887 { "IEEE_tx_1col", IEEE_T_1COL }, 2888 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2889 { "IEEE_tx_def", IEEE_T_DEF }, 2890 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2891 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2892 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2893 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2894 { "IEEE_tx_sqe", IEEE_T_SQE }, 2895 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2896 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2897 2898 /* RMON RX */ 2899 { "rx_packets", RMON_R_PACKETS }, 2900 { "rx_broadcast", RMON_R_BC_PKT }, 2901 { "rx_multicast", RMON_R_MC_PKT }, 2902 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2903 { "rx_undersize", RMON_R_UNDERSIZE }, 2904 { "rx_oversize", RMON_R_OVERSIZE }, 2905 { "rx_fragment", RMON_R_FRAG }, 2906 { "rx_jabber", RMON_R_JAB }, 2907 { "rx_64byte", RMON_R_P64 }, 2908 { "rx_65to127byte", RMON_R_P65TO127 }, 2909 { "rx_128to255byte", RMON_R_P128TO255 }, 2910 { "rx_256to511byte", RMON_R_P256TO511 }, 2911 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2912 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2913 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2914 { "rx_octets", RMON_R_OCTETS }, 2915 2916 /* IEEE RX */ 2917 { "IEEE_rx_drop", IEEE_R_DROP }, 2918 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2919 { "IEEE_rx_crc", IEEE_R_CRC }, 2920 { "IEEE_rx_align", IEEE_R_ALIGN }, 2921 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2922 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2923 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2924 }; 2925 2926 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2927 2928 static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = { 2929 "rx_xdp_redirect", /* RX_XDP_REDIRECT = 0, */ 2930 "rx_xdp_pass", /* RX_XDP_PASS, */ 2931 "rx_xdp_drop", /* RX_XDP_DROP, */ 2932 "rx_xdp_tx", /* RX_XDP_TX, */ 2933 "rx_xdp_tx_errors", /* RX_XDP_TX_ERRORS, */ 2934 "tx_xdp_xmit", /* TX_XDP_XMIT, */ 2935 "tx_xdp_xmit_errors", /* TX_XDP_XMIT_ERRORS, */ 2936 }; 2937 2938 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2939 { 2940 struct fec_enet_private *fep = netdev_priv(dev); 2941 int i; 2942 2943 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2944 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2945 } 2946 2947 static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data) 2948 { 2949 u64 xdp_stats[XDP_STATS_TOTAL] = { 0 }; 2950 struct fec_enet_priv_rx_q *rxq; 2951 int i, j; 2952 2953 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2954 rxq = fep->rx_queue[i]; 2955 2956 for (j = 0; j < XDP_STATS_TOTAL; j++) 2957 xdp_stats[j] += rxq->stats[j]; 2958 } 2959 2960 memcpy(data, xdp_stats, sizeof(xdp_stats)); 2961 } 2962 2963 static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data) 2964 { 2965 #ifdef CONFIG_PAGE_POOL_STATS 2966 struct page_pool_stats stats = {}; 2967 struct fec_enet_priv_rx_q *rxq; 2968 int i; 2969 2970 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2971 rxq = fep->rx_queue[i]; 2972 2973 if (!rxq->page_pool) 2974 continue; 2975 2976 page_pool_get_stats(rxq->page_pool, &stats); 2977 } 2978 2979 page_pool_ethtool_stats_get(data, &stats); 2980 #endif 2981 } 2982 2983 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2984 struct ethtool_stats *stats, u64 *data) 2985 { 2986 struct fec_enet_private *fep = netdev_priv(dev); 2987 2988 if (netif_running(dev)) 2989 fec_enet_update_ethtool_stats(dev); 2990 2991 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2992 data += FEC_STATS_SIZE / sizeof(u64); 2993 2994 fec_enet_get_xdp_stats(fep, data); 2995 data += XDP_STATS_TOTAL; 2996 2997 fec_enet_page_pool_stats(fep, data); 2998 } 2999 3000 static void fec_enet_get_strings(struct net_device *netdev, 3001 u32 stringset, u8 *data) 3002 { 3003 int i; 3004 switch (stringset) { 3005 case ETH_SS_STATS: 3006 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) { 3007 ethtool_puts(&data, fec_stats[i].name); 3008 } 3009 for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) { 3010 ethtool_puts(&data, fec_xdp_stat_strs[i]); 3011 } 3012 page_pool_ethtool_stats_get_strings(data); 3013 3014 break; 3015 case ETH_SS_TEST: 3016 net_selftest_get_strings(data); 3017 break; 3018 } 3019 } 3020 3021 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 3022 { 3023 int count; 3024 3025 switch (sset) { 3026 case ETH_SS_STATS: 3027 count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL; 3028 count += page_pool_ethtool_stats_get_count(); 3029 return count; 3030 3031 case ETH_SS_TEST: 3032 return net_selftest_get_count(); 3033 default: 3034 return -EOPNOTSUPP; 3035 } 3036 } 3037 3038 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 3039 { 3040 struct fec_enet_private *fep = netdev_priv(dev); 3041 struct fec_enet_priv_rx_q *rxq; 3042 int i, j; 3043 3044 /* Disable MIB statistics counters */ 3045 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 3046 3047 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 3048 writel(0, fep->hwp + fec_stats[i].offset); 3049 3050 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 3051 rxq = fep->rx_queue[i]; 3052 for (j = 0; j < XDP_STATS_TOTAL; j++) 3053 rxq->stats[j] = 0; 3054 } 3055 3056 /* Don't disable MIB statistics counters */ 3057 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 3058 } 3059 3060 #else /* !defined(CONFIG_M5272) */ 3061 #define FEC_STATS_SIZE 0 3062 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 3063 { 3064 } 3065 3066 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 3067 { 3068 } 3069 #endif /* !defined(CONFIG_M5272) */ 3070 3071 /* ITR clock source is enet system clock (clk_ahb). 3072 * TCTT unit is cycle_ns * 64 cycle 3073 * So, the ICTT value = X us / (cycle_ns * 64) 3074 */ 3075 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 3076 { 3077 struct fec_enet_private *fep = netdev_priv(ndev); 3078 3079 return us * (fep->itr_clk_rate / 64000) / 1000; 3080 } 3081 3082 /* Set threshold for interrupt coalescing */ 3083 static void fec_enet_itr_coal_set(struct net_device *ndev) 3084 { 3085 struct fec_enet_private *fep = netdev_priv(ndev); 3086 int rx_itr, tx_itr; 3087 3088 /* Must be greater than zero to avoid unpredictable behavior */ 3089 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 3090 !fep->tx_time_itr || !fep->tx_pkts_itr) 3091 return; 3092 3093 /* Select enet system clock as Interrupt Coalescing 3094 * timer Clock Source 3095 */ 3096 rx_itr = FEC_ITR_CLK_SEL; 3097 tx_itr = FEC_ITR_CLK_SEL; 3098 3099 /* set ICFT and ICTT */ 3100 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 3101 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 3102 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 3103 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 3104 3105 rx_itr |= FEC_ITR_EN; 3106 tx_itr |= FEC_ITR_EN; 3107 3108 writel(tx_itr, fep->hwp + FEC_TXIC0); 3109 writel(rx_itr, fep->hwp + FEC_RXIC0); 3110 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 3111 writel(tx_itr, fep->hwp + FEC_TXIC1); 3112 writel(rx_itr, fep->hwp + FEC_RXIC1); 3113 writel(tx_itr, fep->hwp + FEC_TXIC2); 3114 writel(rx_itr, fep->hwp + FEC_RXIC2); 3115 } 3116 } 3117 3118 static int fec_enet_get_coalesce(struct net_device *ndev, 3119 struct ethtool_coalesce *ec, 3120 struct kernel_ethtool_coalesce *kernel_coal, 3121 struct netlink_ext_ack *extack) 3122 { 3123 struct fec_enet_private *fep = netdev_priv(ndev); 3124 3125 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3126 return -EOPNOTSUPP; 3127 3128 ec->rx_coalesce_usecs = fep->rx_time_itr; 3129 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 3130 3131 ec->tx_coalesce_usecs = fep->tx_time_itr; 3132 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 3133 3134 return 0; 3135 } 3136 3137 static int fec_enet_set_coalesce(struct net_device *ndev, 3138 struct ethtool_coalesce *ec, 3139 struct kernel_ethtool_coalesce *kernel_coal, 3140 struct netlink_ext_ack *extack) 3141 { 3142 struct fec_enet_private *fep = netdev_priv(ndev); 3143 struct device *dev = &fep->pdev->dev; 3144 unsigned int cycle; 3145 3146 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3147 return -EOPNOTSUPP; 3148 3149 if (ec->rx_max_coalesced_frames > 255) { 3150 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 3151 return -EINVAL; 3152 } 3153 3154 if (ec->tx_max_coalesced_frames > 255) { 3155 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 3156 return -EINVAL; 3157 } 3158 3159 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 3160 if (cycle > 0xFFFF) { 3161 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 3162 return -EINVAL; 3163 } 3164 3165 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 3166 if (cycle > 0xFFFF) { 3167 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 3168 return -EINVAL; 3169 } 3170 3171 fep->rx_time_itr = ec->rx_coalesce_usecs; 3172 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 3173 3174 fep->tx_time_itr = ec->tx_coalesce_usecs; 3175 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 3176 3177 fec_enet_itr_coal_set(ndev); 3178 3179 return 0; 3180 } 3181 3182 static int 3183 fec_enet_get_eee(struct net_device *ndev, struct ethtool_keee *edata) 3184 { 3185 struct fec_enet_private *fep = netdev_priv(ndev); 3186 3187 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3188 return -EOPNOTSUPP; 3189 3190 if (!netif_running(ndev)) 3191 return -ENETDOWN; 3192 3193 return phy_ethtool_get_eee(ndev->phydev, edata); 3194 } 3195 3196 static int 3197 fec_enet_set_eee(struct net_device *ndev, struct ethtool_keee *edata) 3198 { 3199 struct fec_enet_private *fep = netdev_priv(ndev); 3200 3201 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3202 return -EOPNOTSUPP; 3203 3204 if (!netif_running(ndev)) 3205 return -ENETDOWN; 3206 3207 return phy_ethtool_set_eee(ndev->phydev, edata); 3208 } 3209 3210 static void 3211 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3212 { 3213 struct fec_enet_private *fep = netdev_priv(ndev); 3214 3215 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 3216 wol->supported = WAKE_MAGIC; 3217 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 3218 } else { 3219 wol->supported = wol->wolopts = 0; 3220 } 3221 } 3222 3223 static int 3224 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3225 { 3226 struct fec_enet_private *fep = netdev_priv(ndev); 3227 3228 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 3229 return -EINVAL; 3230 3231 if (wol->wolopts & ~WAKE_MAGIC) 3232 return -EINVAL; 3233 3234 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 3235 if (device_may_wakeup(&ndev->dev)) 3236 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 3237 else 3238 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 3239 3240 return 0; 3241 } 3242 3243 static const struct ethtool_ops fec_enet_ethtool_ops = { 3244 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3245 ETHTOOL_COALESCE_MAX_FRAMES, 3246 .get_drvinfo = fec_enet_get_drvinfo, 3247 .get_regs_len = fec_enet_get_regs_len, 3248 .get_regs = fec_enet_get_regs, 3249 .nway_reset = phy_ethtool_nway_reset, 3250 .get_link = ethtool_op_get_link, 3251 .get_coalesce = fec_enet_get_coalesce, 3252 .set_coalesce = fec_enet_set_coalesce, 3253 #ifndef CONFIG_M5272 3254 .get_pauseparam = fec_enet_get_pauseparam, 3255 .set_pauseparam = fec_enet_set_pauseparam, 3256 .get_strings = fec_enet_get_strings, 3257 .get_ethtool_stats = fec_enet_get_ethtool_stats, 3258 .get_sset_count = fec_enet_get_sset_count, 3259 #endif 3260 .get_ts_info = fec_enet_get_ts_info, 3261 .get_wol = fec_enet_get_wol, 3262 .set_wol = fec_enet_set_wol, 3263 .get_eee = fec_enet_get_eee, 3264 .set_eee = fec_enet_set_eee, 3265 .get_link_ksettings = phy_ethtool_get_link_ksettings, 3266 .set_link_ksettings = phy_ethtool_set_link_ksettings, 3267 .self_test = net_selftest, 3268 }; 3269 3270 static void fec_enet_free_buffers(struct net_device *ndev) 3271 { 3272 struct fec_enet_private *fep = netdev_priv(ndev); 3273 unsigned int i; 3274 struct fec_enet_priv_tx_q *txq; 3275 struct fec_enet_priv_rx_q *rxq; 3276 unsigned int q; 3277 3278 for (q = 0; q < fep->num_rx_queues; q++) { 3279 rxq = fep->rx_queue[q]; 3280 for (i = 0; i < rxq->bd.ring_size; i++) 3281 page_pool_put_full_page(rxq->page_pool, rxq->rx_skb_info[i].page, false); 3282 3283 for (i = 0; i < XDP_STATS_TOTAL; i++) 3284 rxq->stats[i] = 0; 3285 3286 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 3287 xdp_rxq_info_unreg(&rxq->xdp_rxq); 3288 page_pool_destroy(rxq->page_pool); 3289 rxq->page_pool = NULL; 3290 } 3291 3292 for (q = 0; q < fep->num_tx_queues; q++) { 3293 txq = fep->tx_queue[q]; 3294 for (i = 0; i < txq->bd.ring_size; i++) { 3295 kfree(txq->tx_bounce[i]); 3296 txq->tx_bounce[i] = NULL; 3297 3298 if (!txq->tx_buf[i].buf_p) { 3299 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3300 continue; 3301 } 3302 3303 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 3304 dev_kfree_skb(txq->tx_buf[i].buf_p); 3305 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 3306 xdp_return_frame(txq->tx_buf[i].buf_p); 3307 } else { 3308 struct page *page = txq->tx_buf[i].buf_p; 3309 3310 page_pool_put_page(page->pp, page, 0, false); 3311 } 3312 3313 txq->tx_buf[i].buf_p = NULL; 3314 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3315 } 3316 } 3317 } 3318 3319 static void fec_enet_free_queue(struct net_device *ndev) 3320 { 3321 struct fec_enet_private *fep = netdev_priv(ndev); 3322 int i; 3323 struct fec_enet_priv_tx_q *txq; 3324 3325 for (i = 0; i < fep->num_tx_queues; i++) 3326 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 3327 txq = fep->tx_queue[i]; 3328 fec_dma_free(&fep->pdev->dev, 3329 txq->bd.ring_size * TSO_HEADER_SIZE, 3330 txq->tso_hdrs, txq->tso_hdrs_dma); 3331 } 3332 3333 for (i = 0; i < fep->num_rx_queues; i++) 3334 kfree(fep->rx_queue[i]); 3335 for (i = 0; i < fep->num_tx_queues; i++) 3336 kfree(fep->tx_queue[i]); 3337 } 3338 3339 static int fec_enet_alloc_queue(struct net_device *ndev) 3340 { 3341 struct fec_enet_private *fep = netdev_priv(ndev); 3342 int i; 3343 int ret = 0; 3344 struct fec_enet_priv_tx_q *txq; 3345 3346 for (i = 0; i < fep->num_tx_queues; i++) { 3347 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 3348 if (!txq) { 3349 ret = -ENOMEM; 3350 goto alloc_failed; 3351 } 3352 3353 fep->tx_queue[i] = txq; 3354 txq->bd.ring_size = TX_RING_SIZE; 3355 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 3356 3357 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 3358 txq->tx_wake_threshold = FEC_MAX_SKB_DESCS + 2 * MAX_SKB_FRAGS; 3359 3360 txq->tso_hdrs = fec_dma_alloc(&fep->pdev->dev, 3361 txq->bd.ring_size * TSO_HEADER_SIZE, 3362 &txq->tso_hdrs_dma, GFP_KERNEL); 3363 if (!txq->tso_hdrs) { 3364 ret = -ENOMEM; 3365 goto alloc_failed; 3366 } 3367 } 3368 3369 for (i = 0; i < fep->num_rx_queues; i++) { 3370 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 3371 GFP_KERNEL); 3372 if (!fep->rx_queue[i]) { 3373 ret = -ENOMEM; 3374 goto alloc_failed; 3375 } 3376 3377 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 3378 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 3379 } 3380 return ret; 3381 3382 alloc_failed: 3383 fec_enet_free_queue(ndev); 3384 return ret; 3385 } 3386 3387 static int 3388 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 3389 { 3390 struct fec_enet_private *fep = netdev_priv(ndev); 3391 struct fec_enet_priv_rx_q *rxq; 3392 dma_addr_t phys_addr; 3393 struct bufdesc *bdp; 3394 struct page *page; 3395 int i, err; 3396 3397 rxq = fep->rx_queue[queue]; 3398 bdp = rxq->bd.base; 3399 3400 err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size); 3401 if (err < 0) { 3402 netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err); 3403 return err; 3404 } 3405 3406 for (i = 0; i < rxq->bd.ring_size; i++) { 3407 page = page_pool_dev_alloc_pages(rxq->page_pool); 3408 if (!page) 3409 goto err_alloc; 3410 3411 phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM; 3412 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 3413 3414 rxq->rx_skb_info[i].page = page; 3415 rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM; 3416 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3417 3418 if (fep->bufdesc_ex) { 3419 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3420 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 3421 } 3422 3423 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3424 } 3425 3426 /* Set the last buffer to wrap. */ 3427 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3428 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3429 return 0; 3430 3431 err_alloc: 3432 fec_enet_free_buffers(ndev); 3433 return -ENOMEM; 3434 } 3435 3436 static int 3437 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 3438 { 3439 struct fec_enet_private *fep = netdev_priv(ndev); 3440 unsigned int i; 3441 struct bufdesc *bdp; 3442 struct fec_enet_priv_tx_q *txq; 3443 3444 txq = fep->tx_queue[queue]; 3445 bdp = txq->bd.base; 3446 for (i = 0; i < txq->bd.ring_size; i++) { 3447 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 3448 if (!txq->tx_bounce[i]) 3449 goto err_alloc; 3450 3451 bdp->cbd_sc = cpu_to_fec16(0); 3452 bdp->cbd_bufaddr = cpu_to_fec32(0); 3453 3454 if (fep->bufdesc_ex) { 3455 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3456 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 3457 } 3458 3459 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3460 } 3461 3462 /* Set the last buffer to wrap. */ 3463 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3464 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3465 3466 return 0; 3467 3468 err_alloc: 3469 fec_enet_free_buffers(ndev); 3470 return -ENOMEM; 3471 } 3472 3473 static int fec_enet_alloc_buffers(struct net_device *ndev) 3474 { 3475 struct fec_enet_private *fep = netdev_priv(ndev); 3476 unsigned int i; 3477 3478 for (i = 0; i < fep->num_rx_queues; i++) 3479 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3480 return -ENOMEM; 3481 3482 for (i = 0; i < fep->num_tx_queues; i++) 3483 if (fec_enet_alloc_txq_buffers(ndev, i)) 3484 return -ENOMEM; 3485 return 0; 3486 } 3487 3488 static int 3489 fec_enet_open(struct net_device *ndev) 3490 { 3491 struct fec_enet_private *fep = netdev_priv(ndev); 3492 int ret; 3493 bool reset_again; 3494 3495 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3496 if (ret < 0) 3497 return ret; 3498 3499 pinctrl_pm_select_default_state(&fep->pdev->dev); 3500 ret = fec_enet_clk_enable(ndev, true); 3501 if (ret) 3502 goto clk_enable; 3503 3504 /* During the first fec_enet_open call the PHY isn't probed at this 3505 * point. Therefore the phy_reset_after_clk_enable() call within 3506 * fec_enet_clk_enable() fails. As we need this reset in order to be 3507 * sure the PHY is working correctly we check if we need to reset again 3508 * later when the PHY is probed 3509 */ 3510 if (ndev->phydev && ndev->phydev->drv) 3511 reset_again = false; 3512 else 3513 reset_again = true; 3514 3515 /* I should reset the ring buffers here, but I don't yet know 3516 * a simple way to do that. 3517 */ 3518 3519 ret = fec_enet_alloc_buffers(ndev); 3520 if (ret) 3521 goto err_enet_alloc; 3522 3523 /* Init MAC prior to mii bus probe */ 3524 fec_restart(ndev); 3525 3526 /* Call phy_reset_after_clk_enable() again if it failed during 3527 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3528 */ 3529 if (reset_again) 3530 fec_enet_phy_reset_after_clk_enable(ndev); 3531 3532 /* Probe and connect to PHY when open the interface */ 3533 ret = fec_enet_mii_probe(ndev); 3534 if (ret) 3535 goto err_enet_mii_probe; 3536 3537 if (fep->quirks & FEC_QUIRK_ERR006687) 3538 imx6q_cpuidle_fec_irqs_used(); 3539 3540 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3541 cpu_latency_qos_add_request(&fep->pm_qos_req, 0); 3542 3543 napi_enable(&fep->napi); 3544 phy_start(ndev->phydev); 3545 netif_tx_start_all_queues(ndev); 3546 3547 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3548 FEC_WOL_FLAG_ENABLE); 3549 3550 return 0; 3551 3552 err_enet_mii_probe: 3553 fec_enet_free_buffers(ndev); 3554 err_enet_alloc: 3555 fec_enet_clk_enable(ndev, false); 3556 clk_enable: 3557 pm_runtime_mark_last_busy(&fep->pdev->dev); 3558 pm_runtime_put_autosuspend(&fep->pdev->dev); 3559 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3560 return ret; 3561 } 3562 3563 static int 3564 fec_enet_close(struct net_device *ndev) 3565 { 3566 struct fec_enet_private *fep = netdev_priv(ndev); 3567 3568 phy_stop(ndev->phydev); 3569 3570 if (netif_device_present(ndev)) { 3571 napi_disable(&fep->napi); 3572 netif_tx_disable(ndev); 3573 fec_stop(ndev); 3574 } 3575 3576 phy_disconnect(ndev->phydev); 3577 3578 if (fep->quirks & FEC_QUIRK_ERR006687) 3579 imx6q_cpuidle_fec_irqs_unused(); 3580 3581 fec_enet_update_ethtool_stats(ndev); 3582 3583 fec_enet_clk_enable(ndev, false); 3584 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3585 cpu_latency_qos_remove_request(&fep->pm_qos_req); 3586 3587 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3588 pm_runtime_mark_last_busy(&fep->pdev->dev); 3589 pm_runtime_put_autosuspend(&fep->pdev->dev); 3590 3591 fec_enet_free_buffers(ndev); 3592 3593 return 0; 3594 } 3595 3596 /* Set or clear the multicast filter for this adaptor. 3597 * Skeleton taken from sunlance driver. 3598 * The CPM Ethernet implementation allows Multicast as well as individual 3599 * MAC address filtering. Some of the drivers check to make sure it is 3600 * a group multicast address, and discard those that are not. I guess I 3601 * will do the same for now, but just remove the test if you want 3602 * individual filtering as well (do the upper net layers want or support 3603 * this kind of feature?). 3604 */ 3605 3606 #define FEC_HASH_BITS 6 /* #bits in hash */ 3607 3608 static void set_multicast_list(struct net_device *ndev) 3609 { 3610 struct fec_enet_private *fep = netdev_priv(ndev); 3611 struct netdev_hw_addr *ha; 3612 unsigned int crc, tmp; 3613 unsigned char hash; 3614 unsigned int hash_high = 0, hash_low = 0; 3615 3616 if (ndev->flags & IFF_PROMISC) { 3617 tmp = readl(fep->hwp + FEC_R_CNTRL); 3618 tmp |= 0x8; 3619 writel(tmp, fep->hwp + FEC_R_CNTRL); 3620 return; 3621 } 3622 3623 tmp = readl(fep->hwp + FEC_R_CNTRL); 3624 tmp &= ~0x8; 3625 writel(tmp, fep->hwp + FEC_R_CNTRL); 3626 3627 if (ndev->flags & IFF_ALLMULTI) { 3628 /* Catch all multicast addresses, so set the 3629 * filter to all 1's 3630 */ 3631 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3632 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3633 3634 return; 3635 } 3636 3637 /* Add the addresses in hash register */ 3638 netdev_for_each_mc_addr(ha, ndev) { 3639 /* calculate crc32 value of mac address */ 3640 crc = ether_crc_le(ndev->addr_len, ha->addr); 3641 3642 /* only upper 6 bits (FEC_HASH_BITS) are used 3643 * which point to specific bit in the hash registers 3644 */ 3645 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3646 3647 if (hash > 31) 3648 hash_high |= 1 << (hash - 32); 3649 else 3650 hash_low |= 1 << hash; 3651 } 3652 3653 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3654 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3655 } 3656 3657 /* Set a MAC change in hardware. */ 3658 static int 3659 fec_set_mac_address(struct net_device *ndev, void *p) 3660 { 3661 struct fec_enet_private *fep = netdev_priv(ndev); 3662 struct sockaddr *addr = p; 3663 3664 if (addr) { 3665 if (!is_valid_ether_addr(addr->sa_data)) 3666 return -EADDRNOTAVAIL; 3667 eth_hw_addr_set(ndev, addr->sa_data); 3668 } 3669 3670 /* Add netif status check here to avoid system hang in below case: 3671 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3672 * After ethx down, fec all clocks are gated off and then register 3673 * access causes system hang. 3674 */ 3675 if (!netif_running(ndev)) 3676 return 0; 3677 3678 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3679 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3680 fep->hwp + FEC_ADDR_LOW); 3681 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3682 fep->hwp + FEC_ADDR_HIGH); 3683 return 0; 3684 } 3685 3686 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3687 netdev_features_t features) 3688 { 3689 struct fec_enet_private *fep = netdev_priv(netdev); 3690 netdev_features_t changed = features ^ netdev->features; 3691 3692 netdev->features = features; 3693 3694 /* Receive checksum has been changed */ 3695 if (changed & NETIF_F_RXCSUM) { 3696 if (features & NETIF_F_RXCSUM) 3697 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3698 else 3699 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3700 } 3701 } 3702 3703 static int fec_set_features(struct net_device *netdev, 3704 netdev_features_t features) 3705 { 3706 struct fec_enet_private *fep = netdev_priv(netdev); 3707 netdev_features_t changed = features ^ netdev->features; 3708 3709 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3710 napi_disable(&fep->napi); 3711 netif_tx_lock_bh(netdev); 3712 fec_stop(netdev); 3713 fec_enet_set_netdev_features(netdev, features); 3714 fec_restart(netdev); 3715 netif_tx_wake_all_queues(netdev); 3716 netif_tx_unlock_bh(netdev); 3717 napi_enable(&fep->napi); 3718 } else { 3719 fec_enet_set_netdev_features(netdev, features); 3720 } 3721 3722 return 0; 3723 } 3724 3725 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3726 struct net_device *sb_dev) 3727 { 3728 struct fec_enet_private *fep = netdev_priv(ndev); 3729 u16 vlan_tag = 0; 3730 3731 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3732 return netdev_pick_tx(ndev, skb, NULL); 3733 3734 /* VLAN is present in the payload.*/ 3735 if (eth_type_vlan(skb->protocol)) { 3736 struct vlan_ethhdr *vhdr = skb_vlan_eth_hdr(skb); 3737 3738 vlan_tag = ntohs(vhdr->h_vlan_TCI); 3739 /* VLAN is present in the skb but not yet pushed in the payload.*/ 3740 } else if (skb_vlan_tag_present(skb)) { 3741 vlan_tag = skb->vlan_tci; 3742 } else { 3743 return vlan_tag; 3744 } 3745 3746 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3747 } 3748 3749 static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf) 3750 { 3751 struct fec_enet_private *fep = netdev_priv(dev); 3752 bool is_run = netif_running(dev); 3753 struct bpf_prog *old_prog; 3754 3755 switch (bpf->command) { 3756 case XDP_SETUP_PROG: 3757 /* No need to support the SoCs that require to 3758 * do the frame swap because the performance wouldn't be 3759 * better than the skb mode. 3760 */ 3761 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 3762 return -EOPNOTSUPP; 3763 3764 if (!bpf->prog) 3765 xdp_features_clear_redirect_target(dev); 3766 3767 if (is_run) { 3768 napi_disable(&fep->napi); 3769 netif_tx_disable(dev); 3770 } 3771 3772 old_prog = xchg(&fep->xdp_prog, bpf->prog); 3773 if (old_prog) 3774 bpf_prog_put(old_prog); 3775 3776 fec_restart(dev); 3777 3778 if (is_run) { 3779 napi_enable(&fep->napi); 3780 netif_tx_start_all_queues(dev); 3781 } 3782 3783 if (bpf->prog) 3784 xdp_features_set_redirect_target(dev, false); 3785 3786 return 0; 3787 3788 case XDP_SETUP_XSK_POOL: 3789 return -EOPNOTSUPP; 3790 3791 default: 3792 return -EOPNOTSUPP; 3793 } 3794 } 3795 3796 static int 3797 fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index) 3798 { 3799 if (unlikely(index < 0)) 3800 return 0; 3801 3802 return (index % fep->num_tx_queues); 3803 } 3804 3805 static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep, 3806 struct fec_enet_priv_tx_q *txq, 3807 void *frame, u32 dma_sync_len, 3808 bool ndo_xmit) 3809 { 3810 unsigned int index, status, estatus; 3811 struct bufdesc *bdp; 3812 dma_addr_t dma_addr; 3813 int entries_free; 3814 u16 frame_len; 3815 3816 entries_free = fec_enet_get_free_txdesc_num(txq); 3817 if (entries_free < MAX_SKB_FRAGS + 1) { 3818 netdev_err_once(fep->netdev, "NOT enough BD for SG!\n"); 3819 return -EBUSY; 3820 } 3821 3822 /* Fill in a Tx ring entry */ 3823 bdp = txq->bd.cur; 3824 status = fec16_to_cpu(bdp->cbd_sc); 3825 status &= ~BD_ENET_TX_STATS; 3826 3827 index = fec_enet_get_bd_index(bdp, &txq->bd); 3828 3829 if (ndo_xmit) { 3830 struct xdp_frame *xdpf = frame; 3831 3832 dma_addr = dma_map_single(&fep->pdev->dev, xdpf->data, 3833 xdpf->len, DMA_TO_DEVICE); 3834 if (dma_mapping_error(&fep->pdev->dev, dma_addr)) 3835 return -ENOMEM; 3836 3837 frame_len = xdpf->len; 3838 txq->tx_buf[index].buf_p = xdpf; 3839 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_NDO; 3840 } else { 3841 struct xdp_buff *xdpb = frame; 3842 struct page *page; 3843 3844 page = virt_to_page(xdpb->data); 3845 dma_addr = page_pool_get_dma_addr(page) + 3846 (xdpb->data - xdpb->data_hard_start); 3847 dma_sync_single_for_device(&fep->pdev->dev, dma_addr, 3848 dma_sync_len, DMA_BIDIRECTIONAL); 3849 frame_len = xdpb->data_end - xdpb->data; 3850 txq->tx_buf[index].buf_p = page; 3851 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_TX; 3852 } 3853 3854 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 3855 if (fep->bufdesc_ex) 3856 estatus = BD_ENET_TX_INT; 3857 3858 bdp->cbd_bufaddr = cpu_to_fec32(dma_addr); 3859 bdp->cbd_datlen = cpu_to_fec16(frame_len); 3860 3861 if (fep->bufdesc_ex) { 3862 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3863 3864 if (fep->quirks & FEC_QUIRK_HAS_AVB) 3865 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 3866 3867 ebdp->cbd_bdu = 0; 3868 ebdp->cbd_esc = cpu_to_fec32(estatus); 3869 } 3870 3871 /* Make sure the updates to rest of the descriptor are performed before 3872 * transferring ownership. 3873 */ 3874 dma_wmb(); 3875 3876 /* Send it on its way. Tell FEC it's ready, interrupt when done, 3877 * it's the last BD of the frame, and to put the CRC on the end. 3878 */ 3879 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 3880 bdp->cbd_sc = cpu_to_fec16(status); 3881 3882 /* If this was the last BD in the ring, start at the beginning again. */ 3883 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3884 3885 /* Make sure the update to bdp are performed before txq->bd.cur. */ 3886 dma_wmb(); 3887 3888 txq->bd.cur = bdp; 3889 3890 /* Trigger transmission start */ 3891 writel(0, txq->bd.reg_desc_active); 3892 3893 return 0; 3894 } 3895 3896 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 3897 int cpu, struct xdp_buff *xdp, 3898 u32 dma_sync_len) 3899 { 3900 struct fec_enet_priv_tx_q *txq; 3901 struct netdev_queue *nq; 3902 int queue, ret; 3903 3904 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3905 txq = fep->tx_queue[queue]; 3906 nq = netdev_get_tx_queue(fep->netdev, queue); 3907 3908 __netif_tx_lock(nq, cpu); 3909 3910 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3911 txq_trans_cond_update(nq); 3912 ret = fec_enet_txq_xmit_frame(fep, txq, xdp, dma_sync_len, false); 3913 3914 __netif_tx_unlock(nq); 3915 3916 return ret; 3917 } 3918 3919 static int fec_enet_xdp_xmit(struct net_device *dev, 3920 int num_frames, 3921 struct xdp_frame **frames, 3922 u32 flags) 3923 { 3924 struct fec_enet_private *fep = netdev_priv(dev); 3925 struct fec_enet_priv_tx_q *txq; 3926 int cpu = smp_processor_id(); 3927 unsigned int sent_frames = 0; 3928 struct netdev_queue *nq; 3929 unsigned int queue; 3930 int i; 3931 3932 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3933 txq = fep->tx_queue[queue]; 3934 nq = netdev_get_tx_queue(fep->netdev, queue); 3935 3936 __netif_tx_lock(nq, cpu); 3937 3938 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3939 txq_trans_cond_update(nq); 3940 for (i = 0; i < num_frames; i++) { 3941 if (fec_enet_txq_xmit_frame(fep, txq, frames[i], 0, true) < 0) 3942 break; 3943 sent_frames++; 3944 } 3945 3946 __netif_tx_unlock(nq); 3947 3948 return sent_frames; 3949 } 3950 3951 static int fec_hwtstamp_get(struct net_device *ndev, 3952 struct kernel_hwtstamp_config *config) 3953 { 3954 struct fec_enet_private *fep = netdev_priv(ndev); 3955 3956 if (!netif_running(ndev)) 3957 return -EINVAL; 3958 3959 if (!fep->bufdesc_ex) 3960 return -EOPNOTSUPP; 3961 3962 fec_ptp_get(ndev, config); 3963 3964 return 0; 3965 } 3966 3967 static int fec_hwtstamp_set(struct net_device *ndev, 3968 struct kernel_hwtstamp_config *config, 3969 struct netlink_ext_ack *extack) 3970 { 3971 struct fec_enet_private *fep = netdev_priv(ndev); 3972 3973 if (!netif_running(ndev)) 3974 return -EINVAL; 3975 3976 if (!fep->bufdesc_ex) 3977 return -EOPNOTSUPP; 3978 3979 return fec_ptp_set(ndev, config, extack); 3980 } 3981 3982 static const struct net_device_ops fec_netdev_ops = { 3983 .ndo_open = fec_enet_open, 3984 .ndo_stop = fec_enet_close, 3985 .ndo_start_xmit = fec_enet_start_xmit, 3986 .ndo_select_queue = fec_enet_select_queue, 3987 .ndo_set_rx_mode = set_multicast_list, 3988 .ndo_validate_addr = eth_validate_addr, 3989 .ndo_tx_timeout = fec_timeout, 3990 .ndo_set_mac_address = fec_set_mac_address, 3991 .ndo_eth_ioctl = phy_do_ioctl_running, 3992 .ndo_set_features = fec_set_features, 3993 .ndo_bpf = fec_enet_bpf, 3994 .ndo_xdp_xmit = fec_enet_xdp_xmit, 3995 .ndo_hwtstamp_get = fec_hwtstamp_get, 3996 .ndo_hwtstamp_set = fec_hwtstamp_set, 3997 }; 3998 3999 static const unsigned short offset_des_active_rxq[] = { 4000 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 4001 }; 4002 4003 static const unsigned short offset_des_active_txq[] = { 4004 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 4005 }; 4006 4007 /* 4008 * XXX: We need to clean up on failure exits here. 4009 * 4010 */ 4011 static int fec_enet_init(struct net_device *ndev) 4012 { 4013 struct fec_enet_private *fep = netdev_priv(ndev); 4014 struct bufdesc *cbd_base; 4015 dma_addr_t bd_dma; 4016 int bd_size; 4017 unsigned int i; 4018 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 4019 sizeof(struct bufdesc); 4020 unsigned dsize_log2 = __fls(dsize); 4021 int ret; 4022 4023 WARN_ON(dsize != (1 << dsize_log2)); 4024 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 4025 fep->rx_align = 0xf; 4026 fep->tx_align = 0xf; 4027 #else 4028 fep->rx_align = 0x3; 4029 fep->tx_align = 0x3; 4030 #endif 4031 fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4032 fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4033 fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT; 4034 fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT; 4035 4036 /* Check mask of the streaming and coherent API */ 4037 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 4038 if (ret < 0) { 4039 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 4040 return ret; 4041 } 4042 4043 ret = fec_enet_alloc_queue(ndev); 4044 if (ret) 4045 return ret; 4046 4047 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 4048 4049 /* Allocate memory for buffer descriptors. */ 4050 cbd_base = fec_dmam_alloc(&fep->pdev->dev, bd_size, &bd_dma, 4051 GFP_KERNEL); 4052 if (!cbd_base) { 4053 ret = -ENOMEM; 4054 goto free_queue_mem; 4055 } 4056 4057 /* Get the Ethernet address */ 4058 ret = fec_get_mac(ndev); 4059 if (ret) 4060 goto free_queue_mem; 4061 4062 /* Set receive and transmit descriptor base. */ 4063 for (i = 0; i < fep->num_rx_queues; i++) { 4064 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 4065 unsigned size = dsize * rxq->bd.ring_size; 4066 4067 rxq->bd.qid = i; 4068 rxq->bd.base = cbd_base; 4069 rxq->bd.cur = cbd_base; 4070 rxq->bd.dma = bd_dma; 4071 rxq->bd.dsize = dsize; 4072 rxq->bd.dsize_log2 = dsize_log2; 4073 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 4074 bd_dma += size; 4075 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4076 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4077 } 4078 4079 for (i = 0; i < fep->num_tx_queues; i++) { 4080 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 4081 unsigned size = dsize * txq->bd.ring_size; 4082 4083 txq->bd.qid = i; 4084 txq->bd.base = cbd_base; 4085 txq->bd.cur = cbd_base; 4086 txq->bd.dma = bd_dma; 4087 txq->bd.dsize = dsize; 4088 txq->bd.dsize_log2 = dsize_log2; 4089 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 4090 bd_dma += size; 4091 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4092 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4093 } 4094 4095 4096 /* The FEC Ethernet specific entries in the device structure */ 4097 ndev->watchdog_timeo = TX_TIMEOUT; 4098 ndev->netdev_ops = &fec_netdev_ops; 4099 ndev->ethtool_ops = &fec_enet_ethtool_ops; 4100 4101 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 4102 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi); 4103 4104 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 4105 /* enable hw VLAN support */ 4106 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 4107 4108 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 4109 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS); 4110 4111 /* enable hw accelerator */ 4112 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 4113 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 4114 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 4115 } 4116 4117 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 4118 fep->tx_align = 0; 4119 fep->rx_align = 0x3f; 4120 } 4121 4122 ndev->hw_features = ndev->features; 4123 4124 if (!(fep->quirks & FEC_QUIRK_SWAP_FRAME)) 4125 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 4126 NETDEV_XDP_ACT_REDIRECT; 4127 4128 fec_restart(ndev); 4129 4130 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 4131 fec_enet_clear_ethtool_stats(ndev); 4132 else 4133 fec_enet_update_ethtool_stats(ndev); 4134 4135 return 0; 4136 4137 free_queue_mem: 4138 fec_enet_free_queue(ndev); 4139 return ret; 4140 } 4141 4142 static void fec_enet_deinit(struct net_device *ndev) 4143 { 4144 struct fec_enet_private *fep = netdev_priv(ndev); 4145 4146 netif_napi_del(&fep->napi); 4147 fec_enet_free_queue(ndev); 4148 } 4149 4150 #ifdef CONFIG_OF 4151 static int fec_reset_phy(struct platform_device *pdev) 4152 { 4153 struct gpio_desc *phy_reset; 4154 int msec = 1, phy_post_delay = 0; 4155 struct device_node *np = pdev->dev.of_node; 4156 int err; 4157 4158 if (!np) 4159 return 0; 4160 4161 err = of_property_read_u32(np, "phy-reset-duration", &msec); 4162 /* A sane reset duration should not be longer than 1s */ 4163 if (!err && msec > 1000) 4164 msec = 1; 4165 4166 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 4167 /* valid reset duration should be less than 1s */ 4168 if (!err && phy_post_delay > 1000) 4169 return -EINVAL; 4170 4171 phy_reset = devm_gpiod_get_optional(&pdev->dev, "phy-reset", 4172 GPIOD_OUT_HIGH); 4173 if (IS_ERR(phy_reset)) 4174 return dev_err_probe(&pdev->dev, PTR_ERR(phy_reset), 4175 "failed to get phy-reset-gpios\n"); 4176 4177 if (!phy_reset) 4178 return 0; 4179 4180 if (msec > 20) 4181 msleep(msec); 4182 else 4183 usleep_range(msec * 1000, msec * 1000 + 1000); 4184 4185 gpiod_set_value_cansleep(phy_reset, 0); 4186 4187 if (!phy_post_delay) 4188 return 0; 4189 4190 if (phy_post_delay > 20) 4191 msleep(phy_post_delay); 4192 else 4193 usleep_range(phy_post_delay * 1000, 4194 phy_post_delay * 1000 + 1000); 4195 4196 return 0; 4197 } 4198 #else /* CONFIG_OF */ 4199 static int fec_reset_phy(struct platform_device *pdev) 4200 { 4201 /* 4202 * In case of platform probe, the reset has been done 4203 * by machine code. 4204 */ 4205 return 0; 4206 } 4207 #endif /* CONFIG_OF */ 4208 4209 static void 4210 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 4211 { 4212 struct device_node *np = pdev->dev.of_node; 4213 4214 *num_tx = *num_rx = 1; 4215 4216 if (!np || !of_device_is_available(np)) 4217 return; 4218 4219 /* parse the num of tx and rx queues */ 4220 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 4221 4222 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 4223 4224 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 4225 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 4226 *num_tx); 4227 *num_tx = 1; 4228 return; 4229 } 4230 4231 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 4232 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 4233 *num_rx); 4234 *num_rx = 1; 4235 return; 4236 } 4237 4238 } 4239 4240 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 4241 { 4242 int irq_cnt = platform_irq_count(pdev); 4243 4244 if (irq_cnt > FEC_IRQ_NUM) 4245 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 4246 else if (irq_cnt == 2) 4247 irq_cnt = 1; /* last for pps */ 4248 else if (irq_cnt <= 0) 4249 irq_cnt = 1; /* At least 1 irq is needed */ 4250 return irq_cnt; 4251 } 4252 4253 static void fec_enet_get_wakeup_irq(struct platform_device *pdev) 4254 { 4255 struct net_device *ndev = platform_get_drvdata(pdev); 4256 struct fec_enet_private *fep = netdev_priv(ndev); 4257 4258 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) 4259 fep->wake_irq = fep->irq[2]; 4260 else 4261 fep->wake_irq = fep->irq[0]; 4262 } 4263 4264 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 4265 struct device_node *np) 4266 { 4267 struct device_node *gpr_np; 4268 u32 out_val[3]; 4269 int ret = 0; 4270 4271 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 4272 if (!gpr_np) 4273 return 0; 4274 4275 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 4276 ARRAY_SIZE(out_val)); 4277 if (ret) { 4278 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 4279 goto out; 4280 } 4281 4282 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 4283 if (IS_ERR(fep->stop_gpr.gpr)) { 4284 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 4285 ret = PTR_ERR(fep->stop_gpr.gpr); 4286 fep->stop_gpr.gpr = NULL; 4287 goto out; 4288 } 4289 4290 fep->stop_gpr.reg = out_val[1]; 4291 fep->stop_gpr.bit = out_val[2]; 4292 4293 out: 4294 of_node_put(gpr_np); 4295 4296 return ret; 4297 } 4298 4299 static int 4300 fec_probe(struct platform_device *pdev) 4301 { 4302 struct fec_enet_private *fep; 4303 struct fec_platform_data *pdata; 4304 phy_interface_t interface; 4305 struct net_device *ndev; 4306 int i, irq, ret = 0; 4307 static int dev_id; 4308 struct device_node *np = pdev->dev.of_node, *phy_node; 4309 int num_tx_qs; 4310 int num_rx_qs; 4311 char irq_name[8]; 4312 int irq_cnt; 4313 const struct fec_devinfo *dev_info; 4314 4315 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 4316 4317 /* Init network device */ 4318 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 4319 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 4320 if (!ndev) 4321 return -ENOMEM; 4322 4323 SET_NETDEV_DEV(ndev, &pdev->dev); 4324 4325 /* setup board info structure */ 4326 fep = netdev_priv(ndev); 4327 4328 dev_info = device_get_match_data(&pdev->dev); 4329 if (!dev_info) 4330 dev_info = (const struct fec_devinfo *)pdev->id_entry->driver_data; 4331 if (dev_info) 4332 fep->quirks = dev_info->quirks; 4333 4334 fep->netdev = ndev; 4335 fep->num_rx_queues = num_rx_qs; 4336 fep->num_tx_queues = num_tx_qs; 4337 4338 #if !defined(CONFIG_M5272) 4339 /* default enable pause frame auto negotiation */ 4340 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 4341 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 4342 #endif 4343 4344 /* Select default pin state */ 4345 pinctrl_pm_select_default_state(&pdev->dev); 4346 4347 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 4348 if (IS_ERR(fep->hwp)) { 4349 ret = PTR_ERR(fep->hwp); 4350 goto failed_ioremap; 4351 } 4352 4353 fep->pdev = pdev; 4354 fep->dev_id = dev_id++; 4355 4356 platform_set_drvdata(pdev, ndev); 4357 4358 if ((of_machine_is_compatible("fsl,imx6q") || 4359 of_machine_is_compatible("fsl,imx6dl")) && 4360 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 4361 fep->quirks |= FEC_QUIRK_ERR006687; 4362 4363 ret = fec_enet_ipc_handle_init(fep); 4364 if (ret) 4365 goto failed_ipc_init; 4366 4367 if (of_property_read_bool(np, "fsl,magic-packet")) 4368 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 4369 4370 ret = fec_enet_init_stop_mode(fep, np); 4371 if (ret) 4372 goto failed_stop_mode; 4373 4374 phy_node = of_parse_phandle(np, "phy-handle", 0); 4375 if (!phy_node && of_phy_is_fixed_link(np)) { 4376 ret = of_phy_register_fixed_link(np); 4377 if (ret < 0) { 4378 dev_err(&pdev->dev, 4379 "broken fixed-link specification\n"); 4380 goto failed_phy; 4381 } 4382 phy_node = of_node_get(np); 4383 } 4384 fep->phy_node = phy_node; 4385 4386 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 4387 if (ret) { 4388 pdata = dev_get_platdata(&pdev->dev); 4389 if (pdata) 4390 fep->phy_interface = pdata->phy; 4391 else 4392 fep->phy_interface = PHY_INTERFACE_MODE_MII; 4393 } else { 4394 fep->phy_interface = interface; 4395 } 4396 4397 ret = fec_enet_parse_rgmii_delay(fep, np); 4398 if (ret) 4399 goto failed_rgmii_delay; 4400 4401 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 4402 if (IS_ERR(fep->clk_ipg)) { 4403 ret = PTR_ERR(fep->clk_ipg); 4404 goto failed_clk; 4405 } 4406 4407 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 4408 if (IS_ERR(fep->clk_ahb)) { 4409 ret = PTR_ERR(fep->clk_ahb); 4410 goto failed_clk; 4411 } 4412 4413 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 4414 4415 /* enet_out is optional, depends on board */ 4416 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out"); 4417 if (IS_ERR(fep->clk_enet_out)) { 4418 ret = PTR_ERR(fep->clk_enet_out); 4419 goto failed_clk; 4420 } 4421 4422 fep->ptp_clk_on = false; 4423 mutex_init(&fep->ptp_clk_mutex); 4424 4425 /* clk_ref is optional, depends on board */ 4426 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref"); 4427 if (IS_ERR(fep->clk_ref)) { 4428 ret = PTR_ERR(fep->clk_ref); 4429 goto failed_clk; 4430 } 4431 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); 4432 4433 /* clk_2x_txclk is optional, depends on board */ 4434 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { 4435 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); 4436 if (IS_ERR(fep->clk_2x_txclk)) 4437 fep->clk_2x_txclk = NULL; 4438 } 4439 4440 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 4441 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 4442 if (IS_ERR(fep->clk_ptp)) { 4443 fep->clk_ptp = NULL; 4444 fep->bufdesc_ex = false; 4445 } 4446 4447 ret = fec_enet_clk_enable(ndev, true); 4448 if (ret) 4449 goto failed_clk; 4450 4451 ret = clk_prepare_enable(fep->clk_ipg); 4452 if (ret) 4453 goto failed_clk_ipg; 4454 ret = clk_prepare_enable(fep->clk_ahb); 4455 if (ret) 4456 goto failed_clk_ahb; 4457 4458 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 4459 if (!IS_ERR(fep->reg_phy)) { 4460 ret = regulator_enable(fep->reg_phy); 4461 if (ret) { 4462 dev_err(&pdev->dev, 4463 "Failed to enable phy regulator: %d\n", ret); 4464 goto failed_regulator; 4465 } 4466 } else { 4467 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 4468 ret = -EPROBE_DEFER; 4469 goto failed_regulator; 4470 } 4471 fep->reg_phy = NULL; 4472 } 4473 4474 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 4475 pm_runtime_use_autosuspend(&pdev->dev); 4476 pm_runtime_get_noresume(&pdev->dev); 4477 pm_runtime_set_active(&pdev->dev); 4478 pm_runtime_enable(&pdev->dev); 4479 4480 ret = fec_reset_phy(pdev); 4481 if (ret) 4482 goto failed_reset; 4483 4484 irq_cnt = fec_enet_get_irq_cnt(pdev); 4485 if (fep->bufdesc_ex) 4486 fec_ptp_init(pdev, irq_cnt); 4487 4488 ret = fec_enet_init(ndev); 4489 if (ret) 4490 goto failed_init; 4491 4492 for (i = 0; i < irq_cnt; i++) { 4493 snprintf(irq_name, sizeof(irq_name), "int%d", i); 4494 irq = platform_get_irq_byname_optional(pdev, irq_name); 4495 if (irq < 0) 4496 irq = platform_get_irq(pdev, i); 4497 if (irq < 0) { 4498 ret = irq; 4499 goto failed_irq; 4500 } 4501 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 4502 0, pdev->name, ndev); 4503 if (ret) 4504 goto failed_irq; 4505 4506 fep->irq[i] = irq; 4507 } 4508 4509 /* Decide which interrupt line is wakeup capable */ 4510 fec_enet_get_wakeup_irq(pdev); 4511 4512 ret = fec_enet_mii_init(pdev); 4513 if (ret) 4514 goto failed_mii_init; 4515 4516 /* Carrier starts down, phylib will bring it up */ 4517 netif_carrier_off(ndev); 4518 fec_enet_clk_enable(ndev, false); 4519 pinctrl_pm_select_sleep_state(&pdev->dev); 4520 4521 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN; 4522 4523 ret = register_netdev(ndev); 4524 if (ret) 4525 goto failed_register; 4526 4527 device_init_wakeup(&ndev->dev, fep->wol_flag & 4528 FEC_WOL_HAS_MAGIC_PACKET); 4529 4530 if (fep->bufdesc_ex && fep->ptp_clock) 4531 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 4532 4533 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 4534 4535 pm_runtime_mark_last_busy(&pdev->dev); 4536 pm_runtime_put_autosuspend(&pdev->dev); 4537 4538 return 0; 4539 4540 failed_register: 4541 fec_enet_mii_remove(fep); 4542 failed_mii_init: 4543 failed_irq: 4544 fec_enet_deinit(ndev); 4545 failed_init: 4546 fec_ptp_stop(pdev); 4547 failed_reset: 4548 pm_runtime_put_noidle(&pdev->dev); 4549 pm_runtime_disable(&pdev->dev); 4550 if (fep->reg_phy) 4551 regulator_disable(fep->reg_phy); 4552 failed_regulator: 4553 clk_disable_unprepare(fep->clk_ahb); 4554 failed_clk_ahb: 4555 clk_disable_unprepare(fep->clk_ipg); 4556 failed_clk_ipg: 4557 fec_enet_clk_enable(ndev, false); 4558 failed_clk: 4559 failed_rgmii_delay: 4560 if (of_phy_is_fixed_link(np)) 4561 of_phy_deregister_fixed_link(np); 4562 of_node_put(phy_node); 4563 failed_stop_mode: 4564 failed_ipc_init: 4565 failed_phy: 4566 dev_id--; 4567 failed_ioremap: 4568 free_netdev(ndev); 4569 4570 return ret; 4571 } 4572 4573 static void 4574 fec_drv_remove(struct platform_device *pdev) 4575 { 4576 struct net_device *ndev = platform_get_drvdata(pdev); 4577 struct fec_enet_private *fep = netdev_priv(ndev); 4578 struct device_node *np = pdev->dev.of_node; 4579 int ret; 4580 4581 ret = pm_runtime_get_sync(&pdev->dev); 4582 if (ret < 0) 4583 dev_err(&pdev->dev, 4584 "Failed to resume device in remove callback (%pe)\n", 4585 ERR_PTR(ret)); 4586 4587 cancel_work_sync(&fep->tx_timeout_work); 4588 fec_ptp_stop(pdev); 4589 unregister_netdev(ndev); 4590 fec_enet_mii_remove(fep); 4591 if (fep->reg_phy) 4592 regulator_disable(fep->reg_phy); 4593 4594 if (of_phy_is_fixed_link(np)) 4595 of_phy_deregister_fixed_link(np); 4596 of_node_put(fep->phy_node); 4597 4598 /* After pm_runtime_get_sync() failed, the clks are still off, so skip 4599 * disabling them again. 4600 */ 4601 if (ret >= 0) { 4602 clk_disable_unprepare(fep->clk_ahb); 4603 clk_disable_unprepare(fep->clk_ipg); 4604 } 4605 pm_runtime_put_noidle(&pdev->dev); 4606 pm_runtime_disable(&pdev->dev); 4607 4608 fec_enet_deinit(ndev); 4609 free_netdev(ndev); 4610 } 4611 4612 static int fec_suspend(struct device *dev) 4613 { 4614 struct net_device *ndev = dev_get_drvdata(dev); 4615 struct fec_enet_private *fep = netdev_priv(ndev); 4616 int ret; 4617 4618 rtnl_lock(); 4619 if (netif_running(ndev)) { 4620 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 4621 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 4622 phy_stop(ndev->phydev); 4623 napi_disable(&fep->napi); 4624 netif_tx_lock_bh(ndev); 4625 netif_device_detach(ndev); 4626 netif_tx_unlock_bh(ndev); 4627 fec_stop(ndev); 4628 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4629 fec_irqs_disable(ndev); 4630 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 4631 } else { 4632 fec_irqs_disable_except_wakeup(ndev); 4633 if (fep->wake_irq > 0) { 4634 disable_irq(fep->wake_irq); 4635 enable_irq_wake(fep->wake_irq); 4636 } 4637 fec_enet_stop_mode(fep, true); 4638 } 4639 /* It's safe to disable clocks since interrupts are masked */ 4640 fec_enet_clk_enable(ndev, false); 4641 4642 fep->rpm_active = !pm_runtime_status_suspended(dev); 4643 if (fep->rpm_active) { 4644 ret = pm_runtime_force_suspend(dev); 4645 if (ret < 0) { 4646 rtnl_unlock(); 4647 return ret; 4648 } 4649 } 4650 } 4651 rtnl_unlock(); 4652 4653 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4654 regulator_disable(fep->reg_phy); 4655 4656 /* SOC supply clock to phy, when clock is disabled, phy link down 4657 * SOC control phy regulator, when regulator is disabled, phy link down 4658 */ 4659 if (fep->clk_enet_out || fep->reg_phy) 4660 fep->link = 0; 4661 4662 return 0; 4663 } 4664 4665 static int fec_resume(struct device *dev) 4666 { 4667 struct net_device *ndev = dev_get_drvdata(dev); 4668 struct fec_enet_private *fep = netdev_priv(ndev); 4669 int ret; 4670 int val; 4671 4672 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4673 ret = regulator_enable(fep->reg_phy); 4674 if (ret) 4675 return ret; 4676 } 4677 4678 rtnl_lock(); 4679 if (netif_running(ndev)) { 4680 if (fep->rpm_active) 4681 pm_runtime_force_resume(dev); 4682 4683 ret = fec_enet_clk_enable(ndev, true); 4684 if (ret) { 4685 rtnl_unlock(); 4686 goto failed_clk; 4687 } 4688 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 4689 fec_enet_stop_mode(fep, false); 4690 if (fep->wake_irq) { 4691 disable_irq_wake(fep->wake_irq); 4692 enable_irq(fep->wake_irq); 4693 } 4694 4695 val = readl(fep->hwp + FEC_ECNTRL); 4696 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 4697 writel(val, fep->hwp + FEC_ECNTRL); 4698 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 4699 } else { 4700 pinctrl_pm_select_default_state(&fep->pdev->dev); 4701 } 4702 fec_restart(ndev); 4703 netif_tx_lock_bh(ndev); 4704 netif_device_attach(ndev); 4705 netif_tx_unlock_bh(ndev); 4706 napi_enable(&fep->napi); 4707 phy_init_hw(ndev->phydev); 4708 phy_start(ndev->phydev); 4709 } 4710 rtnl_unlock(); 4711 4712 return 0; 4713 4714 failed_clk: 4715 if (fep->reg_phy) 4716 regulator_disable(fep->reg_phy); 4717 return ret; 4718 } 4719 4720 static int fec_runtime_suspend(struct device *dev) 4721 { 4722 struct net_device *ndev = dev_get_drvdata(dev); 4723 struct fec_enet_private *fep = netdev_priv(ndev); 4724 4725 clk_disable_unprepare(fep->clk_ahb); 4726 clk_disable_unprepare(fep->clk_ipg); 4727 4728 return 0; 4729 } 4730 4731 static int fec_runtime_resume(struct device *dev) 4732 { 4733 struct net_device *ndev = dev_get_drvdata(dev); 4734 struct fec_enet_private *fep = netdev_priv(ndev); 4735 int ret; 4736 4737 ret = clk_prepare_enable(fep->clk_ahb); 4738 if (ret) 4739 return ret; 4740 ret = clk_prepare_enable(fep->clk_ipg); 4741 if (ret) 4742 goto failed_clk_ipg; 4743 4744 return 0; 4745 4746 failed_clk_ipg: 4747 clk_disable_unprepare(fep->clk_ahb); 4748 return ret; 4749 } 4750 4751 static const struct dev_pm_ops fec_pm_ops = { 4752 SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 4753 RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 4754 }; 4755 4756 static struct platform_driver fec_driver = { 4757 .driver = { 4758 .name = DRIVER_NAME, 4759 .pm = pm_ptr(&fec_pm_ops), 4760 .of_match_table = fec_dt_ids, 4761 .suppress_bind_attrs = true, 4762 }, 4763 .id_table = fec_devtype, 4764 .probe = fec_probe, 4765 .remove = fec_drv_remove, 4766 }; 4767 4768 module_platform_driver(fec_driver); 4769 4770 MODULE_DESCRIPTION("NXP Fast Ethernet Controller (FEC) driver"); 4771 MODULE_LICENSE("GPL"); 4772