1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/tso.h> 42 #include <linux/tcp.h> 43 #include <linux/udp.h> 44 #include <linux/icmp.h> 45 #include <linux/spinlock.h> 46 #include <linux/workqueue.h> 47 #include <linux/bitops.h> 48 #include <linux/io.h> 49 #include <linux/irq.h> 50 #include <linux/clk.h> 51 #include <linux/crc32.h> 52 #include <linux/platform_device.h> 53 #include <linux/mdio.h> 54 #include <linux/phy.h> 55 #include <linux/fec.h> 56 #include <linux/of.h> 57 #include <linux/of_device.h> 58 #include <linux/of_gpio.h> 59 #include <linux/of_mdio.h> 60 #include <linux/of_net.h> 61 #include <linux/regulator/consumer.h> 62 #include <linux/if_vlan.h> 63 #include <linux/pinctrl/consumer.h> 64 #include <linux/prefetch.h> 65 #include <linux/mfd/syscon.h> 66 #include <linux/regmap.h> 67 #include <soc/imx/cpuidle.h> 68 69 #include <asm/cacheflush.h> 70 71 #include "fec.h" 72 73 static void set_multicast_list(struct net_device *ndev); 74 static void fec_enet_itr_coal_init(struct net_device *ndev); 75 76 #define DRIVER_NAME "fec" 77 78 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0)) 79 80 /* Pause frame feild and FIFO threshold */ 81 #define FEC_ENET_FCE (1 << 5) 82 #define FEC_ENET_RSEM_V 0x84 83 #define FEC_ENET_RSFL_V 16 84 #define FEC_ENET_RAEM_V 0x8 85 #define FEC_ENET_RAFL_V 0x8 86 #define FEC_ENET_OPD_V 0xFFF0 87 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 88 89 struct fec_devinfo { 90 u32 quirks; 91 u8 stop_gpr_reg; 92 u8 stop_gpr_bit; 93 }; 94 95 static const struct fec_devinfo fec_imx25_info = { 96 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 97 FEC_QUIRK_HAS_FRREG, 98 }; 99 100 static const struct fec_devinfo fec_imx27_info = { 101 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG, 102 }; 103 104 static const struct fec_devinfo fec_imx28_info = { 105 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 106 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 107 FEC_QUIRK_HAS_FRREG, 108 }; 109 110 static const struct fec_devinfo fec_imx6q_info = { 111 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 112 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 113 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 114 FEC_QUIRK_HAS_RACC, 115 .stop_gpr_reg = 0x34, 116 .stop_gpr_bit = 27, 117 }; 118 119 static const struct fec_devinfo fec_mvf600_info = { 120 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 121 }; 122 123 static const struct fec_devinfo fec_imx6x_info = { 124 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 125 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 126 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 127 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 128 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE, 129 }; 130 131 static const struct fec_devinfo fec_imx6ul_info = { 132 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 133 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 134 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 135 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 136 FEC_QUIRK_HAS_COALESCE, 137 }; 138 139 static struct platform_device_id fec_devtype[] = { 140 { 141 /* keep it for coldfire */ 142 .name = DRIVER_NAME, 143 .driver_data = 0, 144 }, { 145 .name = "imx25-fec", 146 .driver_data = (kernel_ulong_t)&fec_imx25_info, 147 }, { 148 .name = "imx27-fec", 149 .driver_data = (kernel_ulong_t)&fec_imx27_info, 150 }, { 151 .name = "imx28-fec", 152 .driver_data = (kernel_ulong_t)&fec_imx28_info, 153 }, { 154 .name = "imx6q-fec", 155 .driver_data = (kernel_ulong_t)&fec_imx6q_info, 156 }, { 157 .name = "mvf600-fec", 158 .driver_data = (kernel_ulong_t)&fec_mvf600_info, 159 }, { 160 .name = "imx6sx-fec", 161 .driver_data = (kernel_ulong_t)&fec_imx6x_info, 162 }, { 163 .name = "imx6ul-fec", 164 .driver_data = (kernel_ulong_t)&fec_imx6ul_info, 165 }, { 166 /* sentinel */ 167 } 168 }; 169 MODULE_DEVICE_TABLE(platform, fec_devtype); 170 171 enum imx_fec_type { 172 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 173 IMX27_FEC, /* runs on i.mx27/35/51 */ 174 IMX28_FEC, 175 IMX6Q_FEC, 176 MVF600_FEC, 177 IMX6SX_FEC, 178 IMX6UL_FEC, 179 }; 180 181 static const struct of_device_id fec_dt_ids[] = { 182 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 183 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 184 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 185 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 186 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 187 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 188 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 189 { /* sentinel */ } 190 }; 191 MODULE_DEVICE_TABLE(of, fec_dt_ids); 192 193 static unsigned char macaddr[ETH_ALEN]; 194 module_param_array(macaddr, byte, NULL, 0); 195 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 196 197 #if defined(CONFIG_M5272) 198 /* 199 * Some hardware gets it MAC address out of local flash memory. 200 * if this is non-zero then assume it is the address to get MAC from. 201 */ 202 #if defined(CONFIG_NETtel) 203 #define FEC_FLASHMAC 0xf0006006 204 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 205 #define FEC_FLASHMAC 0xf0006000 206 #elif defined(CONFIG_CANCam) 207 #define FEC_FLASHMAC 0xf0020000 208 #elif defined (CONFIG_M5272C3) 209 #define FEC_FLASHMAC (0xffe04000 + 4) 210 #elif defined(CONFIG_MOD5272) 211 #define FEC_FLASHMAC 0xffc0406b 212 #else 213 #define FEC_FLASHMAC 0 214 #endif 215 #endif /* CONFIG_M5272 */ 216 217 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 218 * 219 * 2048 byte skbufs are allocated. However, alignment requirements 220 * varies between FEC variants. Worst case is 64, so round down by 64. 221 */ 222 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 223 #define PKT_MINBUF_SIZE 64 224 225 /* FEC receive acceleration */ 226 #define FEC_RACC_IPDIS (1 << 1) 227 #define FEC_RACC_PRODIS (1 << 2) 228 #define FEC_RACC_SHIFT16 BIT(7) 229 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 230 231 /* MIB Control Register */ 232 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 233 234 /* 235 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 236 * size bits. Other FEC hardware does not, so we need to take that into 237 * account when setting it. 238 */ 239 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 240 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 241 defined(CONFIG_ARM64) 242 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 243 #else 244 #define OPT_FRAME_SIZE 0 245 #endif 246 247 /* FEC MII MMFR bits definition */ 248 #define FEC_MMFR_ST (1 << 30) 249 #define FEC_MMFR_ST_C45 (0) 250 #define FEC_MMFR_OP_READ (2 << 28) 251 #define FEC_MMFR_OP_READ_C45 (3 << 28) 252 #define FEC_MMFR_OP_WRITE (1 << 28) 253 #define FEC_MMFR_OP_ADDR_WRITE (0) 254 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 255 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 256 #define FEC_MMFR_TA (2 << 16) 257 #define FEC_MMFR_DATA(v) (v & 0xffff) 258 /* FEC ECR bits definition */ 259 #define FEC_ECR_MAGICEN (1 << 2) 260 #define FEC_ECR_SLEEP (1 << 3) 261 262 #define FEC_MII_TIMEOUT 30000 /* us */ 263 264 /* Transmitter timeout */ 265 #define TX_TIMEOUT (2 * HZ) 266 267 #define FEC_PAUSE_FLAG_AUTONEG 0x1 268 #define FEC_PAUSE_FLAG_ENABLE 0x2 269 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 270 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 271 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 272 273 #define COPYBREAK_DEFAULT 256 274 275 /* Max number of allowed TCP segments for software TSO */ 276 #define FEC_MAX_TSO_SEGS 100 277 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 278 279 #define IS_TSO_HEADER(txq, addr) \ 280 ((addr >= txq->tso_hdrs_dma) && \ 281 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 282 283 static int mii_cnt; 284 285 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 286 struct bufdesc_prop *bd) 287 { 288 return (bdp >= bd->last) ? bd->base 289 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 290 } 291 292 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 293 struct bufdesc_prop *bd) 294 { 295 return (bdp <= bd->base) ? bd->last 296 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 297 } 298 299 static int fec_enet_get_bd_index(struct bufdesc *bdp, 300 struct bufdesc_prop *bd) 301 { 302 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 303 } 304 305 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 306 { 307 int entries; 308 309 entries = (((const char *)txq->dirty_tx - 310 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 311 312 return entries >= 0 ? entries : entries + txq->bd.ring_size; 313 } 314 315 static void swap_buffer(void *bufaddr, int len) 316 { 317 int i; 318 unsigned int *buf = bufaddr; 319 320 for (i = 0; i < len; i += 4, buf++) 321 swab32s(buf); 322 } 323 324 static void swap_buffer2(void *dst_buf, void *src_buf, int len) 325 { 326 int i; 327 unsigned int *src = src_buf; 328 unsigned int *dst = dst_buf; 329 330 for (i = 0; i < len; i += 4, src++, dst++) 331 *dst = swab32p(src); 332 } 333 334 static void fec_dump(struct net_device *ndev) 335 { 336 struct fec_enet_private *fep = netdev_priv(ndev); 337 struct bufdesc *bdp; 338 struct fec_enet_priv_tx_q *txq; 339 int index = 0; 340 341 netdev_info(ndev, "TX ring dump\n"); 342 pr_info("Nr SC addr len SKB\n"); 343 344 txq = fep->tx_queue[0]; 345 bdp = txq->bd.base; 346 347 do { 348 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 349 index, 350 bdp == txq->bd.cur ? 'S' : ' ', 351 bdp == txq->dirty_tx ? 'H' : ' ', 352 fec16_to_cpu(bdp->cbd_sc), 353 fec32_to_cpu(bdp->cbd_bufaddr), 354 fec16_to_cpu(bdp->cbd_datlen), 355 txq->tx_skbuff[index]); 356 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 357 index++; 358 } while (bdp != txq->bd.base); 359 } 360 361 static inline bool is_ipv4_pkt(struct sk_buff *skb) 362 { 363 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 364 } 365 366 static int 367 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 368 { 369 /* Only run for packets requiring a checksum. */ 370 if (skb->ip_summed != CHECKSUM_PARTIAL) 371 return 0; 372 373 if (unlikely(skb_cow_head(skb, 0))) 374 return -1; 375 376 if (is_ipv4_pkt(skb)) 377 ip_hdr(skb)->check = 0; 378 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 379 380 return 0; 381 } 382 383 static struct bufdesc * 384 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 385 struct sk_buff *skb, 386 struct net_device *ndev) 387 { 388 struct fec_enet_private *fep = netdev_priv(ndev); 389 struct bufdesc *bdp = txq->bd.cur; 390 struct bufdesc_ex *ebdp; 391 int nr_frags = skb_shinfo(skb)->nr_frags; 392 int frag, frag_len; 393 unsigned short status; 394 unsigned int estatus = 0; 395 skb_frag_t *this_frag; 396 unsigned int index; 397 void *bufaddr; 398 dma_addr_t addr; 399 int i; 400 401 for (frag = 0; frag < nr_frags; frag++) { 402 this_frag = &skb_shinfo(skb)->frags[frag]; 403 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 404 ebdp = (struct bufdesc_ex *)bdp; 405 406 status = fec16_to_cpu(bdp->cbd_sc); 407 status &= ~BD_ENET_TX_STATS; 408 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 409 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 410 411 /* Handle the last BD specially */ 412 if (frag == nr_frags - 1) { 413 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 414 if (fep->bufdesc_ex) { 415 estatus |= BD_ENET_TX_INT; 416 if (unlikely(skb_shinfo(skb)->tx_flags & 417 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 418 estatus |= BD_ENET_TX_TS; 419 } 420 } 421 422 if (fep->bufdesc_ex) { 423 if (fep->quirks & FEC_QUIRK_HAS_AVB) 424 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 425 if (skb->ip_summed == CHECKSUM_PARTIAL) 426 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 427 ebdp->cbd_bdu = 0; 428 ebdp->cbd_esc = cpu_to_fec32(estatus); 429 } 430 431 bufaddr = skb_frag_address(this_frag); 432 433 index = fec_enet_get_bd_index(bdp, &txq->bd); 434 if (((unsigned long) bufaddr) & fep->tx_align || 435 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 436 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 437 bufaddr = txq->tx_bounce[index]; 438 439 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 440 swap_buffer(bufaddr, frag_len); 441 } 442 443 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 444 DMA_TO_DEVICE); 445 if (dma_mapping_error(&fep->pdev->dev, addr)) { 446 if (net_ratelimit()) 447 netdev_err(ndev, "Tx DMA memory map failed\n"); 448 goto dma_mapping_error; 449 } 450 451 bdp->cbd_bufaddr = cpu_to_fec32(addr); 452 bdp->cbd_datlen = cpu_to_fec16(frag_len); 453 /* Make sure the updates to rest of the descriptor are 454 * performed before transferring ownership. 455 */ 456 wmb(); 457 bdp->cbd_sc = cpu_to_fec16(status); 458 } 459 460 return bdp; 461 dma_mapping_error: 462 bdp = txq->bd.cur; 463 for (i = 0; i < frag; i++) { 464 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 465 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 466 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 467 } 468 return ERR_PTR(-ENOMEM); 469 } 470 471 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 472 struct sk_buff *skb, struct net_device *ndev) 473 { 474 struct fec_enet_private *fep = netdev_priv(ndev); 475 int nr_frags = skb_shinfo(skb)->nr_frags; 476 struct bufdesc *bdp, *last_bdp; 477 void *bufaddr; 478 dma_addr_t addr; 479 unsigned short status; 480 unsigned short buflen; 481 unsigned int estatus = 0; 482 unsigned int index; 483 int entries_free; 484 485 entries_free = fec_enet_get_free_txdesc_num(txq); 486 if (entries_free < MAX_SKB_FRAGS + 1) { 487 dev_kfree_skb_any(skb); 488 if (net_ratelimit()) 489 netdev_err(ndev, "NOT enough BD for SG!\n"); 490 return NETDEV_TX_OK; 491 } 492 493 /* Protocol checksum off-load for TCP and UDP. */ 494 if (fec_enet_clear_csum(skb, ndev)) { 495 dev_kfree_skb_any(skb); 496 return NETDEV_TX_OK; 497 } 498 499 /* Fill in a Tx ring entry */ 500 bdp = txq->bd.cur; 501 last_bdp = bdp; 502 status = fec16_to_cpu(bdp->cbd_sc); 503 status &= ~BD_ENET_TX_STATS; 504 505 /* Set buffer length and buffer pointer */ 506 bufaddr = skb->data; 507 buflen = skb_headlen(skb); 508 509 index = fec_enet_get_bd_index(bdp, &txq->bd); 510 if (((unsigned long) bufaddr) & fep->tx_align || 511 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 512 memcpy(txq->tx_bounce[index], skb->data, buflen); 513 bufaddr = txq->tx_bounce[index]; 514 515 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 516 swap_buffer(bufaddr, buflen); 517 } 518 519 /* Push the data cache so the CPM does not get stale memory data. */ 520 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 521 if (dma_mapping_error(&fep->pdev->dev, addr)) { 522 dev_kfree_skb_any(skb); 523 if (net_ratelimit()) 524 netdev_err(ndev, "Tx DMA memory map failed\n"); 525 return NETDEV_TX_OK; 526 } 527 528 if (nr_frags) { 529 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 530 if (IS_ERR(last_bdp)) { 531 dma_unmap_single(&fep->pdev->dev, addr, 532 buflen, DMA_TO_DEVICE); 533 dev_kfree_skb_any(skb); 534 return NETDEV_TX_OK; 535 } 536 } else { 537 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 538 if (fep->bufdesc_ex) { 539 estatus = BD_ENET_TX_INT; 540 if (unlikely(skb_shinfo(skb)->tx_flags & 541 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 542 estatus |= BD_ENET_TX_TS; 543 } 544 } 545 bdp->cbd_bufaddr = cpu_to_fec32(addr); 546 bdp->cbd_datlen = cpu_to_fec16(buflen); 547 548 if (fep->bufdesc_ex) { 549 550 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 551 552 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 553 fep->hwts_tx_en)) 554 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 555 556 if (fep->quirks & FEC_QUIRK_HAS_AVB) 557 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 558 559 if (skb->ip_summed == CHECKSUM_PARTIAL) 560 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 561 562 ebdp->cbd_bdu = 0; 563 ebdp->cbd_esc = cpu_to_fec32(estatus); 564 } 565 566 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 567 /* Save skb pointer */ 568 txq->tx_skbuff[index] = skb; 569 570 /* Make sure the updates to rest of the descriptor are performed before 571 * transferring ownership. 572 */ 573 wmb(); 574 575 /* Send it on its way. Tell FEC it's ready, interrupt when done, 576 * it's the last BD of the frame, and to put the CRC on the end. 577 */ 578 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 579 bdp->cbd_sc = cpu_to_fec16(status); 580 581 /* If this was the last BD in the ring, start at the beginning again. */ 582 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 583 584 skb_tx_timestamp(skb); 585 586 /* Make sure the update to bdp and tx_skbuff are performed before 587 * txq->bd.cur. 588 */ 589 wmb(); 590 txq->bd.cur = bdp; 591 592 /* Trigger transmission start */ 593 writel(0, txq->bd.reg_desc_active); 594 595 return 0; 596 } 597 598 static int 599 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 600 struct net_device *ndev, 601 struct bufdesc *bdp, int index, char *data, 602 int size, bool last_tcp, bool is_last) 603 { 604 struct fec_enet_private *fep = netdev_priv(ndev); 605 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 606 unsigned short status; 607 unsigned int estatus = 0; 608 dma_addr_t addr; 609 610 status = fec16_to_cpu(bdp->cbd_sc); 611 status &= ~BD_ENET_TX_STATS; 612 613 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 614 615 if (((unsigned long) data) & fep->tx_align || 616 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 617 memcpy(txq->tx_bounce[index], data, size); 618 data = txq->tx_bounce[index]; 619 620 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 621 swap_buffer(data, size); 622 } 623 624 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 625 if (dma_mapping_error(&fep->pdev->dev, addr)) { 626 dev_kfree_skb_any(skb); 627 if (net_ratelimit()) 628 netdev_err(ndev, "Tx DMA memory map failed\n"); 629 return NETDEV_TX_BUSY; 630 } 631 632 bdp->cbd_datlen = cpu_to_fec16(size); 633 bdp->cbd_bufaddr = cpu_to_fec32(addr); 634 635 if (fep->bufdesc_ex) { 636 if (fep->quirks & FEC_QUIRK_HAS_AVB) 637 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 638 if (skb->ip_summed == CHECKSUM_PARTIAL) 639 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 640 ebdp->cbd_bdu = 0; 641 ebdp->cbd_esc = cpu_to_fec32(estatus); 642 } 643 644 /* Handle the last BD specially */ 645 if (last_tcp) 646 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 647 if (is_last) { 648 status |= BD_ENET_TX_INTR; 649 if (fep->bufdesc_ex) 650 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 651 } 652 653 bdp->cbd_sc = cpu_to_fec16(status); 654 655 return 0; 656 } 657 658 static int 659 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 660 struct sk_buff *skb, struct net_device *ndev, 661 struct bufdesc *bdp, int index) 662 { 663 struct fec_enet_private *fep = netdev_priv(ndev); 664 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 665 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 666 void *bufaddr; 667 unsigned long dmabuf; 668 unsigned short status; 669 unsigned int estatus = 0; 670 671 status = fec16_to_cpu(bdp->cbd_sc); 672 status &= ~BD_ENET_TX_STATS; 673 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 674 675 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 676 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 677 if (((unsigned long)bufaddr) & fep->tx_align || 678 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 679 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 680 bufaddr = txq->tx_bounce[index]; 681 682 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 683 swap_buffer(bufaddr, hdr_len); 684 685 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 686 hdr_len, DMA_TO_DEVICE); 687 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 688 dev_kfree_skb_any(skb); 689 if (net_ratelimit()) 690 netdev_err(ndev, "Tx DMA memory map failed\n"); 691 return NETDEV_TX_BUSY; 692 } 693 } 694 695 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 696 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 697 698 if (fep->bufdesc_ex) { 699 if (fep->quirks & FEC_QUIRK_HAS_AVB) 700 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 701 if (skb->ip_summed == CHECKSUM_PARTIAL) 702 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 703 ebdp->cbd_bdu = 0; 704 ebdp->cbd_esc = cpu_to_fec32(estatus); 705 } 706 707 bdp->cbd_sc = cpu_to_fec16(status); 708 709 return 0; 710 } 711 712 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 713 struct sk_buff *skb, 714 struct net_device *ndev) 715 { 716 struct fec_enet_private *fep = netdev_priv(ndev); 717 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 718 int total_len, data_left; 719 struct bufdesc *bdp = txq->bd.cur; 720 struct tso_t tso; 721 unsigned int index = 0; 722 int ret; 723 724 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 725 dev_kfree_skb_any(skb); 726 if (net_ratelimit()) 727 netdev_err(ndev, "NOT enough BD for TSO!\n"); 728 return NETDEV_TX_OK; 729 } 730 731 /* Protocol checksum off-load for TCP and UDP. */ 732 if (fec_enet_clear_csum(skb, ndev)) { 733 dev_kfree_skb_any(skb); 734 return NETDEV_TX_OK; 735 } 736 737 /* Initialize the TSO handler, and prepare the first payload */ 738 tso_start(skb, &tso); 739 740 total_len = skb->len - hdr_len; 741 while (total_len > 0) { 742 char *hdr; 743 744 index = fec_enet_get_bd_index(bdp, &txq->bd); 745 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 746 total_len -= data_left; 747 748 /* prepare packet headers: MAC + IP + TCP */ 749 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 750 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 751 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 752 if (ret) 753 goto err_release; 754 755 while (data_left > 0) { 756 int size; 757 758 size = min_t(int, tso.size, data_left); 759 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 760 index = fec_enet_get_bd_index(bdp, &txq->bd); 761 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 762 bdp, index, 763 tso.data, size, 764 size == data_left, 765 total_len == 0); 766 if (ret) 767 goto err_release; 768 769 data_left -= size; 770 tso_build_data(skb, &tso, size); 771 } 772 773 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 774 } 775 776 /* Save skb pointer */ 777 txq->tx_skbuff[index] = skb; 778 779 skb_tx_timestamp(skb); 780 txq->bd.cur = bdp; 781 782 /* Trigger transmission start */ 783 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 784 !readl(txq->bd.reg_desc_active) || 785 !readl(txq->bd.reg_desc_active) || 786 !readl(txq->bd.reg_desc_active) || 787 !readl(txq->bd.reg_desc_active)) 788 writel(0, txq->bd.reg_desc_active); 789 790 return 0; 791 792 err_release: 793 /* TODO: Release all used data descriptors for TSO */ 794 return ret; 795 } 796 797 static netdev_tx_t 798 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 799 { 800 struct fec_enet_private *fep = netdev_priv(ndev); 801 int entries_free; 802 unsigned short queue; 803 struct fec_enet_priv_tx_q *txq; 804 struct netdev_queue *nq; 805 int ret; 806 807 queue = skb_get_queue_mapping(skb); 808 txq = fep->tx_queue[queue]; 809 nq = netdev_get_tx_queue(ndev, queue); 810 811 if (skb_is_gso(skb)) 812 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 813 else 814 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 815 if (ret) 816 return ret; 817 818 entries_free = fec_enet_get_free_txdesc_num(txq); 819 if (entries_free <= txq->tx_stop_threshold) 820 netif_tx_stop_queue(nq); 821 822 return NETDEV_TX_OK; 823 } 824 825 /* Init RX & TX buffer descriptors 826 */ 827 static void fec_enet_bd_init(struct net_device *dev) 828 { 829 struct fec_enet_private *fep = netdev_priv(dev); 830 struct fec_enet_priv_tx_q *txq; 831 struct fec_enet_priv_rx_q *rxq; 832 struct bufdesc *bdp; 833 unsigned int i; 834 unsigned int q; 835 836 for (q = 0; q < fep->num_rx_queues; q++) { 837 /* Initialize the receive buffer descriptors. */ 838 rxq = fep->rx_queue[q]; 839 bdp = rxq->bd.base; 840 841 for (i = 0; i < rxq->bd.ring_size; i++) { 842 843 /* Initialize the BD for every fragment in the page. */ 844 if (bdp->cbd_bufaddr) 845 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 846 else 847 bdp->cbd_sc = cpu_to_fec16(0); 848 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 849 } 850 851 /* Set the last buffer to wrap */ 852 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 853 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 854 855 rxq->bd.cur = rxq->bd.base; 856 } 857 858 for (q = 0; q < fep->num_tx_queues; q++) { 859 /* ...and the same for transmit */ 860 txq = fep->tx_queue[q]; 861 bdp = txq->bd.base; 862 txq->bd.cur = bdp; 863 864 for (i = 0; i < txq->bd.ring_size; i++) { 865 /* Initialize the BD for every fragment in the page. */ 866 bdp->cbd_sc = cpu_to_fec16(0); 867 if (bdp->cbd_bufaddr && 868 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 869 dma_unmap_single(&fep->pdev->dev, 870 fec32_to_cpu(bdp->cbd_bufaddr), 871 fec16_to_cpu(bdp->cbd_datlen), 872 DMA_TO_DEVICE); 873 if (txq->tx_skbuff[i]) { 874 dev_kfree_skb_any(txq->tx_skbuff[i]); 875 txq->tx_skbuff[i] = NULL; 876 } 877 bdp->cbd_bufaddr = cpu_to_fec32(0); 878 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 879 } 880 881 /* Set the last buffer to wrap */ 882 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 883 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 884 txq->dirty_tx = bdp; 885 } 886 } 887 888 static void fec_enet_active_rxring(struct net_device *ndev) 889 { 890 struct fec_enet_private *fep = netdev_priv(ndev); 891 int i; 892 893 for (i = 0; i < fep->num_rx_queues; i++) 894 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 895 } 896 897 static void fec_enet_enable_ring(struct net_device *ndev) 898 { 899 struct fec_enet_private *fep = netdev_priv(ndev); 900 struct fec_enet_priv_tx_q *txq; 901 struct fec_enet_priv_rx_q *rxq; 902 int i; 903 904 for (i = 0; i < fep->num_rx_queues; i++) { 905 rxq = fep->rx_queue[i]; 906 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 907 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 908 909 /* enable DMA1/2 */ 910 if (i) 911 writel(RCMR_MATCHEN | RCMR_CMP(i), 912 fep->hwp + FEC_RCMR(i)); 913 } 914 915 for (i = 0; i < fep->num_tx_queues; i++) { 916 txq = fep->tx_queue[i]; 917 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 918 919 /* enable DMA1/2 */ 920 if (i) 921 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 922 fep->hwp + FEC_DMA_CFG(i)); 923 } 924 } 925 926 static void fec_enet_reset_skb(struct net_device *ndev) 927 { 928 struct fec_enet_private *fep = netdev_priv(ndev); 929 struct fec_enet_priv_tx_q *txq; 930 int i, j; 931 932 for (i = 0; i < fep->num_tx_queues; i++) { 933 txq = fep->tx_queue[i]; 934 935 for (j = 0; j < txq->bd.ring_size; j++) { 936 if (txq->tx_skbuff[j]) { 937 dev_kfree_skb_any(txq->tx_skbuff[j]); 938 txq->tx_skbuff[j] = NULL; 939 } 940 } 941 } 942 } 943 944 /* 945 * This function is called to start or restart the FEC during a link 946 * change, transmit timeout, or to reconfigure the FEC. The network 947 * packet processing for this device must be stopped before this call. 948 */ 949 static void 950 fec_restart(struct net_device *ndev) 951 { 952 struct fec_enet_private *fep = netdev_priv(ndev); 953 u32 val; 954 u32 temp_mac[2]; 955 u32 rcntl = OPT_FRAME_SIZE | 0x04; 956 u32 ecntl = 0x2; /* ETHEREN */ 957 958 /* Whack a reset. We should wait for this. 959 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 960 * instead of reset MAC itself. 961 */ 962 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 963 writel(0, fep->hwp + FEC_ECNTRL); 964 } else { 965 writel(1, fep->hwp + FEC_ECNTRL); 966 udelay(10); 967 } 968 969 /* 970 * enet-mac reset will reset mac address registers too, 971 * so need to reconfigure it. 972 */ 973 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 974 writel((__force u32)cpu_to_be32(temp_mac[0]), 975 fep->hwp + FEC_ADDR_LOW); 976 writel((__force u32)cpu_to_be32(temp_mac[1]), 977 fep->hwp + FEC_ADDR_HIGH); 978 979 /* Clear any outstanding interrupt, except MDIO. */ 980 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 981 982 fec_enet_bd_init(ndev); 983 984 fec_enet_enable_ring(ndev); 985 986 /* Reset tx SKB buffers. */ 987 fec_enet_reset_skb(ndev); 988 989 /* Enable MII mode */ 990 if (fep->full_duplex == DUPLEX_FULL) { 991 /* FD enable */ 992 writel(0x04, fep->hwp + FEC_X_CNTRL); 993 } else { 994 /* No Rcv on Xmit */ 995 rcntl |= 0x02; 996 writel(0x0, fep->hwp + FEC_X_CNTRL); 997 } 998 999 /* Set MII speed */ 1000 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1001 1002 #if !defined(CONFIG_M5272) 1003 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1004 val = readl(fep->hwp + FEC_RACC); 1005 /* align IP header */ 1006 val |= FEC_RACC_SHIFT16; 1007 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1008 /* set RX checksum */ 1009 val |= FEC_RACC_OPTIONS; 1010 else 1011 val &= ~FEC_RACC_OPTIONS; 1012 writel(val, fep->hwp + FEC_RACC); 1013 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1014 } 1015 #endif 1016 1017 /* 1018 * The phy interface and speed need to get configured 1019 * differently on enet-mac. 1020 */ 1021 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1022 /* Enable flow control and length check */ 1023 rcntl |= 0x40000000 | 0x00000020; 1024 1025 /* RGMII, RMII or MII */ 1026 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1027 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1028 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1029 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1030 rcntl |= (1 << 6); 1031 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1032 rcntl |= (1 << 8); 1033 else 1034 rcntl &= ~(1 << 8); 1035 1036 /* 1G, 100M or 10M */ 1037 if (ndev->phydev) { 1038 if (ndev->phydev->speed == SPEED_1000) 1039 ecntl |= (1 << 5); 1040 else if (ndev->phydev->speed == SPEED_100) 1041 rcntl &= ~(1 << 9); 1042 else 1043 rcntl |= (1 << 9); 1044 } 1045 } else { 1046 #ifdef FEC_MIIGSK_ENR 1047 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1048 u32 cfgr; 1049 /* disable the gasket and wait */ 1050 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1051 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1052 udelay(1); 1053 1054 /* 1055 * configure the gasket: 1056 * RMII, 50 MHz, no loopback, no echo 1057 * MII, 25 MHz, no loopback, no echo 1058 */ 1059 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1060 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1061 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1062 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1063 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1064 1065 /* re-enable the gasket */ 1066 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1067 } 1068 #endif 1069 } 1070 1071 #if !defined(CONFIG_M5272) 1072 /* enable pause frame*/ 1073 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1074 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1075 ndev->phydev && ndev->phydev->pause)) { 1076 rcntl |= FEC_ENET_FCE; 1077 1078 /* set FIFO threshold parameter to reduce overrun */ 1079 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1080 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1081 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1082 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1083 1084 /* OPD */ 1085 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1086 } else { 1087 rcntl &= ~FEC_ENET_FCE; 1088 } 1089 #endif /* !defined(CONFIG_M5272) */ 1090 1091 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1092 1093 /* Setup multicast filter. */ 1094 set_multicast_list(ndev); 1095 #ifndef CONFIG_M5272 1096 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1097 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1098 #endif 1099 1100 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1101 /* enable ENET endian swap */ 1102 ecntl |= (1 << 8); 1103 /* enable ENET store and forward mode */ 1104 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1105 } 1106 1107 if (fep->bufdesc_ex) 1108 ecntl |= (1 << 4); 1109 1110 #ifndef CONFIG_M5272 1111 /* Enable the MIB statistic event counters */ 1112 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1113 #endif 1114 1115 /* And last, enable the transmit and receive processing */ 1116 writel(ecntl, fep->hwp + FEC_ECNTRL); 1117 fec_enet_active_rxring(ndev); 1118 1119 if (fep->bufdesc_ex) 1120 fec_ptp_start_cyclecounter(ndev); 1121 1122 /* Enable interrupts we wish to service */ 1123 if (fep->link) 1124 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1125 else 1126 writel(0, fep->hwp + FEC_IMASK); 1127 1128 /* Init the interrupt coalescing */ 1129 fec_enet_itr_coal_init(ndev); 1130 1131 } 1132 1133 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1134 { 1135 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1136 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1137 1138 if (stop_gpr->gpr) { 1139 if (enabled) 1140 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1141 BIT(stop_gpr->bit), 1142 BIT(stop_gpr->bit)); 1143 else 1144 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1145 BIT(stop_gpr->bit), 0); 1146 } else if (pdata && pdata->sleep_mode_enable) { 1147 pdata->sleep_mode_enable(enabled); 1148 } 1149 } 1150 1151 static void 1152 fec_stop(struct net_device *ndev) 1153 { 1154 struct fec_enet_private *fep = netdev_priv(ndev); 1155 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1156 u32 val; 1157 1158 /* We cannot expect a graceful transmit stop without link !!! */ 1159 if (fep->link) { 1160 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1161 udelay(10); 1162 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1163 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1164 } 1165 1166 /* Whack a reset. We should wait for this. 1167 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1168 * instead of reset MAC itself. 1169 */ 1170 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1171 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 1172 writel(0, fep->hwp + FEC_ECNTRL); 1173 } else { 1174 writel(1, fep->hwp + FEC_ECNTRL); 1175 udelay(10); 1176 } 1177 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1178 } else { 1179 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1180 val = readl(fep->hwp + FEC_ECNTRL); 1181 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1182 writel(val, fep->hwp + FEC_ECNTRL); 1183 fec_enet_stop_mode(fep, true); 1184 } 1185 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1186 1187 /* We have to keep ENET enabled to have MII interrupt stay working */ 1188 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1189 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1190 writel(2, fep->hwp + FEC_ECNTRL); 1191 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1192 } 1193 } 1194 1195 1196 static void 1197 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1198 { 1199 struct fec_enet_private *fep = netdev_priv(ndev); 1200 1201 fec_dump(ndev); 1202 1203 ndev->stats.tx_errors++; 1204 1205 schedule_work(&fep->tx_timeout_work); 1206 } 1207 1208 static void fec_enet_timeout_work(struct work_struct *work) 1209 { 1210 struct fec_enet_private *fep = 1211 container_of(work, struct fec_enet_private, tx_timeout_work); 1212 struct net_device *ndev = fep->netdev; 1213 1214 rtnl_lock(); 1215 if (netif_device_present(ndev) || netif_running(ndev)) { 1216 napi_disable(&fep->napi); 1217 netif_tx_lock_bh(ndev); 1218 fec_restart(ndev); 1219 netif_tx_wake_all_queues(ndev); 1220 netif_tx_unlock_bh(ndev); 1221 napi_enable(&fep->napi); 1222 } 1223 rtnl_unlock(); 1224 } 1225 1226 static void 1227 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1228 struct skb_shared_hwtstamps *hwtstamps) 1229 { 1230 unsigned long flags; 1231 u64 ns; 1232 1233 spin_lock_irqsave(&fep->tmreg_lock, flags); 1234 ns = timecounter_cyc2time(&fep->tc, ts); 1235 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1236 1237 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1238 hwtstamps->hwtstamp = ns_to_ktime(ns); 1239 } 1240 1241 static void 1242 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1243 { 1244 struct fec_enet_private *fep; 1245 struct bufdesc *bdp; 1246 unsigned short status; 1247 struct sk_buff *skb; 1248 struct fec_enet_priv_tx_q *txq; 1249 struct netdev_queue *nq; 1250 int index = 0; 1251 int entries_free; 1252 1253 fep = netdev_priv(ndev); 1254 1255 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1256 1257 txq = fep->tx_queue[queue_id]; 1258 /* get next bdp of dirty_tx */ 1259 nq = netdev_get_tx_queue(ndev, queue_id); 1260 bdp = txq->dirty_tx; 1261 1262 /* get next bdp of dirty_tx */ 1263 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1264 1265 while (bdp != READ_ONCE(txq->bd.cur)) { 1266 /* Order the load of bd.cur and cbd_sc */ 1267 rmb(); 1268 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1269 if (status & BD_ENET_TX_READY) 1270 break; 1271 1272 index = fec_enet_get_bd_index(bdp, &txq->bd); 1273 1274 skb = txq->tx_skbuff[index]; 1275 txq->tx_skbuff[index] = NULL; 1276 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1277 dma_unmap_single(&fep->pdev->dev, 1278 fec32_to_cpu(bdp->cbd_bufaddr), 1279 fec16_to_cpu(bdp->cbd_datlen), 1280 DMA_TO_DEVICE); 1281 bdp->cbd_bufaddr = cpu_to_fec32(0); 1282 if (!skb) 1283 goto skb_done; 1284 1285 /* Check for errors. */ 1286 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1287 BD_ENET_TX_RL | BD_ENET_TX_UN | 1288 BD_ENET_TX_CSL)) { 1289 ndev->stats.tx_errors++; 1290 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1291 ndev->stats.tx_heartbeat_errors++; 1292 if (status & BD_ENET_TX_LC) /* Late collision */ 1293 ndev->stats.tx_window_errors++; 1294 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1295 ndev->stats.tx_aborted_errors++; 1296 if (status & BD_ENET_TX_UN) /* Underrun */ 1297 ndev->stats.tx_fifo_errors++; 1298 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1299 ndev->stats.tx_carrier_errors++; 1300 } else { 1301 ndev->stats.tx_packets++; 1302 ndev->stats.tx_bytes += skb->len; 1303 } 1304 1305 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && 1306 fep->bufdesc_ex) { 1307 struct skb_shared_hwtstamps shhwtstamps; 1308 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1309 1310 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1311 skb_tstamp_tx(skb, &shhwtstamps); 1312 } 1313 1314 /* Deferred means some collisions occurred during transmit, 1315 * but we eventually sent the packet OK. 1316 */ 1317 if (status & BD_ENET_TX_DEF) 1318 ndev->stats.collisions++; 1319 1320 /* Free the sk buffer associated with this last transmit */ 1321 dev_kfree_skb_any(skb); 1322 skb_done: 1323 /* Make sure the update to bdp and tx_skbuff are performed 1324 * before dirty_tx 1325 */ 1326 wmb(); 1327 txq->dirty_tx = bdp; 1328 1329 /* Update pointer to next buffer descriptor to be transmitted */ 1330 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1331 1332 /* Since we have freed up a buffer, the ring is no longer full 1333 */ 1334 if (netif_tx_queue_stopped(nq)) { 1335 entries_free = fec_enet_get_free_txdesc_num(txq); 1336 if (entries_free >= txq->tx_wake_threshold) 1337 netif_tx_wake_queue(nq); 1338 } 1339 } 1340 1341 /* ERR006358: Keep the transmitter going */ 1342 if (bdp != txq->bd.cur && 1343 readl(txq->bd.reg_desc_active) == 0) 1344 writel(0, txq->bd.reg_desc_active); 1345 } 1346 1347 static void 1348 fec_enet_tx(struct net_device *ndev) 1349 { 1350 struct fec_enet_private *fep = netdev_priv(ndev); 1351 u16 queue_id; 1352 /* First process class A queue, then Class B and Best Effort queue */ 1353 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) { 1354 clear_bit(queue_id, &fep->work_tx); 1355 fec_enet_tx_queue(ndev, queue_id); 1356 } 1357 return; 1358 } 1359 1360 static int 1361 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1362 { 1363 struct fec_enet_private *fep = netdev_priv(ndev); 1364 int off; 1365 1366 off = ((unsigned long)skb->data) & fep->rx_align; 1367 if (off) 1368 skb_reserve(skb, fep->rx_align + 1 - off); 1369 1370 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); 1371 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { 1372 if (net_ratelimit()) 1373 netdev_err(ndev, "Rx DMA memory map failed\n"); 1374 return -ENOMEM; 1375 } 1376 1377 return 0; 1378 } 1379 1380 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1381 struct bufdesc *bdp, u32 length, bool swap) 1382 { 1383 struct fec_enet_private *fep = netdev_priv(ndev); 1384 struct sk_buff *new_skb; 1385 1386 if (length > fep->rx_copybreak) 1387 return false; 1388 1389 new_skb = netdev_alloc_skb(ndev, length); 1390 if (!new_skb) 1391 return false; 1392 1393 dma_sync_single_for_cpu(&fep->pdev->dev, 1394 fec32_to_cpu(bdp->cbd_bufaddr), 1395 FEC_ENET_RX_FRSIZE - fep->rx_align, 1396 DMA_FROM_DEVICE); 1397 if (!swap) 1398 memcpy(new_skb->data, (*skb)->data, length); 1399 else 1400 swap_buffer2(new_skb->data, (*skb)->data, length); 1401 *skb = new_skb; 1402 1403 return true; 1404 } 1405 1406 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1407 * When we update through the ring, if the next incoming buffer has 1408 * not been given to the system, we just set the empty indicator, 1409 * effectively tossing the packet. 1410 */ 1411 static int 1412 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1413 { 1414 struct fec_enet_private *fep = netdev_priv(ndev); 1415 struct fec_enet_priv_rx_q *rxq; 1416 struct bufdesc *bdp; 1417 unsigned short status; 1418 struct sk_buff *skb_new = NULL; 1419 struct sk_buff *skb; 1420 ushort pkt_len; 1421 __u8 *data; 1422 int pkt_received = 0; 1423 struct bufdesc_ex *ebdp = NULL; 1424 bool vlan_packet_rcvd = false; 1425 u16 vlan_tag; 1426 int index = 0; 1427 bool is_copybreak; 1428 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1429 1430 #ifdef CONFIG_M532x 1431 flush_cache_all(); 1432 #endif 1433 queue_id = FEC_ENET_GET_QUQUE(queue_id); 1434 rxq = fep->rx_queue[queue_id]; 1435 1436 /* First, grab all of the stats for the incoming packet. 1437 * These get messed up if we get called due to a busy condition. 1438 */ 1439 bdp = rxq->bd.cur; 1440 1441 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1442 1443 if (pkt_received >= budget) 1444 break; 1445 pkt_received++; 1446 1447 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); 1448 1449 /* Check for errors. */ 1450 status ^= BD_ENET_RX_LAST; 1451 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1452 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1453 BD_ENET_RX_CL)) { 1454 ndev->stats.rx_errors++; 1455 if (status & BD_ENET_RX_OV) { 1456 /* FIFO overrun */ 1457 ndev->stats.rx_fifo_errors++; 1458 goto rx_processing_done; 1459 } 1460 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1461 | BD_ENET_RX_LAST)) { 1462 /* Frame too long or too short. */ 1463 ndev->stats.rx_length_errors++; 1464 if (status & BD_ENET_RX_LAST) 1465 netdev_err(ndev, "rcv is not +last\n"); 1466 } 1467 if (status & BD_ENET_RX_CR) /* CRC Error */ 1468 ndev->stats.rx_crc_errors++; 1469 /* Report late collisions as a frame error. */ 1470 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1471 ndev->stats.rx_frame_errors++; 1472 goto rx_processing_done; 1473 } 1474 1475 /* Process the incoming frame. */ 1476 ndev->stats.rx_packets++; 1477 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1478 ndev->stats.rx_bytes += pkt_len; 1479 1480 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1481 skb = rxq->rx_skbuff[index]; 1482 1483 /* The packet length includes FCS, but we don't want to 1484 * include that when passing upstream as it messes up 1485 * bridging applications. 1486 */ 1487 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1488 need_swap); 1489 if (!is_copybreak) { 1490 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1491 if (unlikely(!skb_new)) { 1492 ndev->stats.rx_dropped++; 1493 goto rx_processing_done; 1494 } 1495 dma_unmap_single(&fep->pdev->dev, 1496 fec32_to_cpu(bdp->cbd_bufaddr), 1497 FEC_ENET_RX_FRSIZE - fep->rx_align, 1498 DMA_FROM_DEVICE); 1499 } 1500 1501 prefetch(skb->data - NET_IP_ALIGN); 1502 skb_put(skb, pkt_len - 4); 1503 data = skb->data; 1504 1505 if (!is_copybreak && need_swap) 1506 swap_buffer(data, pkt_len); 1507 1508 #if !defined(CONFIG_M5272) 1509 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1510 data = skb_pull_inline(skb, 2); 1511 #endif 1512 1513 /* Extract the enhanced buffer descriptor */ 1514 ebdp = NULL; 1515 if (fep->bufdesc_ex) 1516 ebdp = (struct bufdesc_ex *)bdp; 1517 1518 /* If this is a VLAN packet remove the VLAN Tag */ 1519 vlan_packet_rcvd = false; 1520 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1521 fep->bufdesc_ex && 1522 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1523 /* Push and remove the vlan tag */ 1524 struct vlan_hdr *vlan_header = 1525 (struct vlan_hdr *) (data + ETH_HLEN); 1526 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1527 1528 vlan_packet_rcvd = true; 1529 1530 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1531 skb_pull(skb, VLAN_HLEN); 1532 } 1533 1534 skb->protocol = eth_type_trans(skb, ndev); 1535 1536 /* Get receive timestamp from the skb */ 1537 if (fep->hwts_rx_en && fep->bufdesc_ex) 1538 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1539 skb_hwtstamps(skb)); 1540 1541 if (fep->bufdesc_ex && 1542 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1543 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1544 /* don't check it */ 1545 skb->ip_summed = CHECKSUM_UNNECESSARY; 1546 } else { 1547 skb_checksum_none_assert(skb); 1548 } 1549 } 1550 1551 /* Handle received VLAN packets */ 1552 if (vlan_packet_rcvd) 1553 __vlan_hwaccel_put_tag(skb, 1554 htons(ETH_P_8021Q), 1555 vlan_tag); 1556 1557 napi_gro_receive(&fep->napi, skb); 1558 1559 if (is_copybreak) { 1560 dma_sync_single_for_device(&fep->pdev->dev, 1561 fec32_to_cpu(bdp->cbd_bufaddr), 1562 FEC_ENET_RX_FRSIZE - fep->rx_align, 1563 DMA_FROM_DEVICE); 1564 } else { 1565 rxq->rx_skbuff[index] = skb_new; 1566 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1567 } 1568 1569 rx_processing_done: 1570 /* Clear the status flags for this buffer */ 1571 status &= ~BD_ENET_RX_STATS; 1572 1573 /* Mark the buffer empty */ 1574 status |= BD_ENET_RX_EMPTY; 1575 1576 if (fep->bufdesc_ex) { 1577 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1578 1579 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1580 ebdp->cbd_prot = 0; 1581 ebdp->cbd_bdu = 0; 1582 } 1583 /* Make sure the updates to rest of the descriptor are 1584 * performed before transferring ownership. 1585 */ 1586 wmb(); 1587 bdp->cbd_sc = cpu_to_fec16(status); 1588 1589 /* Update BD pointer to next entry */ 1590 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1591 1592 /* Doing this here will keep the FEC running while we process 1593 * incoming frames. On a heavily loaded network, we should be 1594 * able to keep up at the expense of system resources. 1595 */ 1596 writel(0, rxq->bd.reg_desc_active); 1597 } 1598 rxq->bd.cur = bdp; 1599 return pkt_received; 1600 } 1601 1602 static int 1603 fec_enet_rx(struct net_device *ndev, int budget) 1604 { 1605 int pkt_received = 0; 1606 u16 queue_id; 1607 struct fec_enet_private *fep = netdev_priv(ndev); 1608 1609 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) { 1610 int ret; 1611 1612 ret = fec_enet_rx_queue(ndev, 1613 budget - pkt_received, queue_id); 1614 1615 if (ret < budget - pkt_received) 1616 clear_bit(queue_id, &fep->work_rx); 1617 1618 pkt_received += ret; 1619 } 1620 return pkt_received; 1621 } 1622 1623 static bool 1624 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events) 1625 { 1626 if (int_events == 0) 1627 return false; 1628 1629 if (int_events & FEC_ENET_RXF_0) 1630 fep->work_rx |= (1 << 2); 1631 if (int_events & FEC_ENET_RXF_1) 1632 fep->work_rx |= (1 << 0); 1633 if (int_events & FEC_ENET_RXF_2) 1634 fep->work_rx |= (1 << 1); 1635 1636 if (int_events & FEC_ENET_TXF_0) 1637 fep->work_tx |= (1 << 2); 1638 if (int_events & FEC_ENET_TXF_1) 1639 fep->work_tx |= (1 << 0); 1640 if (int_events & FEC_ENET_TXF_2) 1641 fep->work_tx |= (1 << 1); 1642 1643 return true; 1644 } 1645 1646 static irqreturn_t 1647 fec_enet_interrupt(int irq, void *dev_id) 1648 { 1649 struct net_device *ndev = dev_id; 1650 struct fec_enet_private *fep = netdev_priv(ndev); 1651 uint int_events; 1652 irqreturn_t ret = IRQ_NONE; 1653 1654 int_events = readl(fep->hwp + FEC_IEVENT); 1655 1656 /* Don't clear MDIO events, we poll for those */ 1657 int_events &= ~FEC_ENET_MII; 1658 1659 writel(int_events, fep->hwp + FEC_IEVENT); 1660 fec_enet_collect_events(fep, int_events); 1661 1662 if ((fep->work_tx || fep->work_rx) && fep->link) { 1663 ret = IRQ_HANDLED; 1664 1665 if (napi_schedule_prep(&fep->napi)) { 1666 /* Disable interrupts */ 1667 writel(0, fep->hwp + FEC_IMASK); 1668 __napi_schedule(&fep->napi); 1669 } 1670 } 1671 1672 return ret; 1673 } 1674 1675 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1676 { 1677 struct net_device *ndev = napi->dev; 1678 struct fec_enet_private *fep = netdev_priv(ndev); 1679 int pkts; 1680 1681 pkts = fec_enet_rx(ndev, budget); 1682 1683 fec_enet_tx(ndev); 1684 1685 if (pkts < budget) { 1686 napi_complete_done(napi, pkts); 1687 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1688 } 1689 return pkts; 1690 } 1691 1692 /* ------------------------------------------------------------------------- */ 1693 static void fec_get_mac(struct net_device *ndev) 1694 { 1695 struct fec_enet_private *fep = netdev_priv(ndev); 1696 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1697 unsigned char *iap, tmpaddr[ETH_ALEN]; 1698 1699 /* 1700 * try to get mac address in following order: 1701 * 1702 * 1) module parameter via kernel command line in form 1703 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1704 */ 1705 iap = macaddr; 1706 1707 /* 1708 * 2) from device tree data 1709 */ 1710 if (!is_valid_ether_addr(iap)) { 1711 struct device_node *np = fep->pdev->dev.of_node; 1712 if (np) { 1713 const char *mac = of_get_mac_address(np); 1714 if (!IS_ERR(mac)) 1715 iap = (unsigned char *) mac; 1716 } 1717 } 1718 1719 /* 1720 * 3) from flash or fuse (via platform data) 1721 */ 1722 if (!is_valid_ether_addr(iap)) { 1723 #ifdef CONFIG_M5272 1724 if (FEC_FLASHMAC) 1725 iap = (unsigned char *)FEC_FLASHMAC; 1726 #else 1727 if (pdata) 1728 iap = (unsigned char *)&pdata->mac; 1729 #endif 1730 } 1731 1732 /* 1733 * 4) FEC mac registers set by bootloader 1734 */ 1735 if (!is_valid_ether_addr(iap)) { 1736 *((__be32 *) &tmpaddr[0]) = 1737 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1738 *((__be16 *) &tmpaddr[4]) = 1739 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1740 iap = &tmpaddr[0]; 1741 } 1742 1743 /* 1744 * 5) random mac address 1745 */ 1746 if (!is_valid_ether_addr(iap)) { 1747 /* Report it and use a random ethernet address instead */ 1748 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 1749 eth_hw_addr_random(ndev); 1750 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 1751 ndev->dev_addr); 1752 return; 1753 } 1754 1755 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1756 1757 /* Adjust MAC if using macaddr */ 1758 if (iap == macaddr) 1759 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1760 } 1761 1762 /* ------------------------------------------------------------------------- */ 1763 1764 /* 1765 * Phy section 1766 */ 1767 static void fec_enet_adjust_link(struct net_device *ndev) 1768 { 1769 struct fec_enet_private *fep = netdev_priv(ndev); 1770 struct phy_device *phy_dev = ndev->phydev; 1771 int status_change = 0; 1772 1773 /* 1774 * If the netdev is down, or is going down, we're not interested 1775 * in link state events, so just mark our idea of the link as down 1776 * and ignore the event. 1777 */ 1778 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1779 fep->link = 0; 1780 } else if (phy_dev->link) { 1781 if (!fep->link) { 1782 fep->link = phy_dev->link; 1783 status_change = 1; 1784 } 1785 1786 if (fep->full_duplex != phy_dev->duplex) { 1787 fep->full_duplex = phy_dev->duplex; 1788 status_change = 1; 1789 } 1790 1791 if (phy_dev->speed != fep->speed) { 1792 fep->speed = phy_dev->speed; 1793 status_change = 1; 1794 } 1795 1796 /* if any of the above changed restart the FEC */ 1797 if (status_change) { 1798 napi_disable(&fep->napi); 1799 netif_tx_lock_bh(ndev); 1800 fec_restart(ndev); 1801 netif_tx_wake_all_queues(ndev); 1802 netif_tx_unlock_bh(ndev); 1803 napi_enable(&fep->napi); 1804 } 1805 } else { 1806 if (fep->link) { 1807 napi_disable(&fep->napi); 1808 netif_tx_lock_bh(ndev); 1809 fec_stop(ndev); 1810 netif_tx_unlock_bh(ndev); 1811 napi_enable(&fep->napi); 1812 fep->link = phy_dev->link; 1813 status_change = 1; 1814 } 1815 } 1816 1817 if (status_change) 1818 phy_print_status(phy_dev); 1819 } 1820 1821 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 1822 { 1823 uint ievent; 1824 int ret; 1825 1826 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 1827 ievent & FEC_ENET_MII, 2, 30000); 1828 1829 if (!ret) 1830 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 1831 1832 return ret; 1833 } 1834 1835 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1836 { 1837 struct fec_enet_private *fep = bus->priv; 1838 struct device *dev = &fep->pdev->dev; 1839 int ret = 0, frame_start, frame_addr, frame_op; 1840 bool is_c45 = !!(regnum & MII_ADDR_C45); 1841 1842 ret = pm_runtime_get_sync(dev); 1843 if (ret < 0) 1844 return ret; 1845 1846 if (is_c45) { 1847 frame_start = FEC_MMFR_ST_C45; 1848 1849 /* write address */ 1850 frame_addr = (regnum >> 16); 1851 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1852 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1853 FEC_MMFR_TA | (regnum & 0xFFFF), 1854 fep->hwp + FEC_MII_DATA); 1855 1856 /* wait for end of transfer */ 1857 ret = fec_enet_mdio_wait(fep); 1858 if (ret) { 1859 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1860 goto out; 1861 } 1862 1863 frame_op = FEC_MMFR_OP_READ_C45; 1864 1865 } else { 1866 /* C22 read */ 1867 frame_op = FEC_MMFR_OP_READ; 1868 frame_start = FEC_MMFR_ST; 1869 frame_addr = regnum; 1870 } 1871 1872 /* start a read op */ 1873 writel(frame_start | frame_op | 1874 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1875 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1876 1877 /* wait for end of transfer */ 1878 ret = fec_enet_mdio_wait(fep); 1879 if (ret) { 1880 netdev_err(fep->netdev, "MDIO read timeout\n"); 1881 goto out; 1882 } 1883 1884 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1885 1886 out: 1887 pm_runtime_mark_last_busy(dev); 1888 pm_runtime_put_autosuspend(dev); 1889 1890 return ret; 1891 } 1892 1893 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1894 u16 value) 1895 { 1896 struct fec_enet_private *fep = bus->priv; 1897 struct device *dev = &fep->pdev->dev; 1898 int ret, frame_start, frame_addr; 1899 bool is_c45 = !!(regnum & MII_ADDR_C45); 1900 1901 ret = pm_runtime_get_sync(dev); 1902 if (ret < 0) 1903 return ret; 1904 else 1905 ret = 0; 1906 1907 if (is_c45) { 1908 frame_start = FEC_MMFR_ST_C45; 1909 1910 /* write address */ 1911 frame_addr = (regnum >> 16); 1912 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1913 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1914 FEC_MMFR_TA | (regnum & 0xFFFF), 1915 fep->hwp + FEC_MII_DATA); 1916 1917 /* wait for end of transfer */ 1918 ret = fec_enet_mdio_wait(fep); 1919 if (ret) { 1920 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1921 goto out; 1922 } 1923 } else { 1924 /* C22 write */ 1925 frame_start = FEC_MMFR_ST; 1926 frame_addr = regnum; 1927 } 1928 1929 /* start a write op */ 1930 writel(frame_start | FEC_MMFR_OP_WRITE | 1931 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1932 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1933 fep->hwp + FEC_MII_DATA); 1934 1935 /* wait for end of transfer */ 1936 ret = fec_enet_mdio_wait(fep); 1937 if (ret) 1938 netdev_err(fep->netdev, "MDIO write timeout\n"); 1939 1940 out: 1941 pm_runtime_mark_last_busy(dev); 1942 pm_runtime_put_autosuspend(dev); 1943 1944 return ret; 1945 } 1946 1947 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1948 { 1949 struct fec_enet_private *fep = netdev_priv(ndev); 1950 int ret; 1951 1952 if (enable) { 1953 ret = clk_prepare_enable(fep->clk_enet_out); 1954 if (ret) 1955 return ret; 1956 1957 if (fep->clk_ptp) { 1958 mutex_lock(&fep->ptp_clk_mutex); 1959 ret = clk_prepare_enable(fep->clk_ptp); 1960 if (ret) { 1961 mutex_unlock(&fep->ptp_clk_mutex); 1962 goto failed_clk_ptp; 1963 } else { 1964 fep->ptp_clk_on = true; 1965 } 1966 mutex_unlock(&fep->ptp_clk_mutex); 1967 } 1968 1969 ret = clk_prepare_enable(fep->clk_ref); 1970 if (ret) 1971 goto failed_clk_ref; 1972 1973 phy_reset_after_clk_enable(ndev->phydev); 1974 } else { 1975 clk_disable_unprepare(fep->clk_enet_out); 1976 if (fep->clk_ptp) { 1977 mutex_lock(&fep->ptp_clk_mutex); 1978 clk_disable_unprepare(fep->clk_ptp); 1979 fep->ptp_clk_on = false; 1980 mutex_unlock(&fep->ptp_clk_mutex); 1981 } 1982 clk_disable_unprepare(fep->clk_ref); 1983 } 1984 1985 return 0; 1986 1987 failed_clk_ref: 1988 if (fep->clk_ref) 1989 clk_disable_unprepare(fep->clk_ref); 1990 failed_clk_ptp: 1991 if (fep->clk_enet_out) 1992 clk_disable_unprepare(fep->clk_enet_out); 1993 1994 return ret; 1995 } 1996 1997 static int fec_enet_mii_probe(struct net_device *ndev) 1998 { 1999 struct fec_enet_private *fep = netdev_priv(ndev); 2000 struct phy_device *phy_dev = NULL; 2001 char mdio_bus_id[MII_BUS_ID_SIZE]; 2002 char phy_name[MII_BUS_ID_SIZE + 3]; 2003 int phy_id; 2004 int dev_id = fep->dev_id; 2005 2006 if (fep->phy_node) { 2007 phy_dev = of_phy_connect(ndev, fep->phy_node, 2008 &fec_enet_adjust_link, 0, 2009 fep->phy_interface); 2010 if (!phy_dev) { 2011 netdev_err(ndev, "Unable to connect to phy\n"); 2012 return -ENODEV; 2013 } 2014 } else { 2015 /* check for attached phy */ 2016 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2017 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2018 continue; 2019 if (dev_id--) 2020 continue; 2021 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2022 break; 2023 } 2024 2025 if (phy_id >= PHY_MAX_ADDR) { 2026 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2027 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2028 phy_id = 0; 2029 } 2030 2031 snprintf(phy_name, sizeof(phy_name), 2032 PHY_ID_FMT, mdio_bus_id, phy_id); 2033 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2034 fep->phy_interface); 2035 } 2036 2037 if (IS_ERR(phy_dev)) { 2038 netdev_err(ndev, "could not attach to PHY\n"); 2039 return PTR_ERR(phy_dev); 2040 } 2041 2042 /* mask with MAC supported features */ 2043 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2044 phy_set_max_speed(phy_dev, 1000); 2045 phy_remove_link_mode(phy_dev, 2046 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2047 #if !defined(CONFIG_M5272) 2048 phy_support_sym_pause(phy_dev); 2049 #endif 2050 } 2051 else 2052 phy_set_max_speed(phy_dev, 100); 2053 2054 fep->link = 0; 2055 fep->full_duplex = 0; 2056 2057 phy_attached_info(phy_dev); 2058 2059 return 0; 2060 } 2061 2062 static int fec_enet_mii_init(struct platform_device *pdev) 2063 { 2064 static struct mii_bus *fec0_mii_bus; 2065 struct net_device *ndev = platform_get_drvdata(pdev); 2066 struct fec_enet_private *fep = netdev_priv(ndev); 2067 bool suppress_preamble = false; 2068 struct device_node *node; 2069 int err = -ENXIO; 2070 u32 mii_speed, holdtime; 2071 u32 bus_freq; 2072 2073 /* 2074 * The i.MX28 dual fec interfaces are not equal. 2075 * Here are the differences: 2076 * 2077 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2078 * - fec0 acts as the 1588 time master while fec1 is slave 2079 * - external phys can only be configured by fec0 2080 * 2081 * That is to say fec1 can not work independently. It only works 2082 * when fec0 is working. The reason behind this design is that the 2083 * second interface is added primarily for Switch mode. 2084 * 2085 * Because of the last point above, both phys are attached on fec0 2086 * mdio interface in board design, and need to be configured by 2087 * fec0 mii_bus. 2088 */ 2089 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2090 /* fec1 uses fec0 mii_bus */ 2091 if (mii_cnt && fec0_mii_bus) { 2092 fep->mii_bus = fec0_mii_bus; 2093 mii_cnt++; 2094 return 0; 2095 } 2096 return -ENOENT; 2097 } 2098 2099 bus_freq = 2500000; /* 2.5MHz by default */ 2100 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2101 if (node) { 2102 of_property_read_u32(node, "clock-frequency", &bus_freq); 2103 suppress_preamble = of_property_read_bool(node, 2104 "suppress-preamble"); 2105 } 2106 2107 /* 2108 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2109 * 2110 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2111 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2112 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2113 * document. 2114 */ 2115 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2116 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2117 mii_speed--; 2118 if (mii_speed > 63) { 2119 dev_err(&pdev->dev, 2120 "fec clock (%lu) too fast to get right mii speed\n", 2121 clk_get_rate(fep->clk_ipg)); 2122 err = -EINVAL; 2123 goto err_out; 2124 } 2125 2126 /* 2127 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2128 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2129 * versions are RAZ there, so just ignore the difference and write the 2130 * register always. 2131 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2132 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2133 * output. 2134 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2135 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2136 * holdtime cannot result in a value greater than 3. 2137 */ 2138 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2139 2140 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2141 2142 if (suppress_preamble) 2143 fep->phy_speed |= BIT(7); 2144 2145 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2146 * MII event generation condition: 2147 * - writing MSCR: 2148 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2149 * mscr_reg_data_in[7:0] != 0 2150 * - writing MMFR: 2151 * - mscr[7:0]_not_zero 2152 */ 2153 writel(0, fep->hwp + FEC_MII_DATA); 2154 2155 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2156 2157 /* Clear any pending transaction complete indication */ 2158 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2159 2160 fep->mii_bus = mdiobus_alloc(); 2161 if (fep->mii_bus == NULL) { 2162 err = -ENOMEM; 2163 goto err_out; 2164 } 2165 2166 fep->mii_bus->name = "fec_enet_mii_bus"; 2167 fep->mii_bus->read = fec_enet_mdio_read; 2168 fep->mii_bus->write = fec_enet_mdio_write; 2169 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2170 pdev->name, fep->dev_id + 1); 2171 fep->mii_bus->priv = fep; 2172 fep->mii_bus->parent = &pdev->dev; 2173 2174 err = of_mdiobus_register(fep->mii_bus, node); 2175 of_node_put(node); 2176 if (err) 2177 goto err_out_free_mdiobus; 2178 2179 mii_cnt++; 2180 2181 /* save fec0 mii_bus */ 2182 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2183 fec0_mii_bus = fep->mii_bus; 2184 2185 return 0; 2186 2187 err_out_free_mdiobus: 2188 mdiobus_free(fep->mii_bus); 2189 err_out: 2190 return err; 2191 } 2192 2193 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2194 { 2195 if (--mii_cnt == 0) { 2196 mdiobus_unregister(fep->mii_bus); 2197 mdiobus_free(fep->mii_bus); 2198 } 2199 } 2200 2201 static void fec_enet_get_drvinfo(struct net_device *ndev, 2202 struct ethtool_drvinfo *info) 2203 { 2204 struct fec_enet_private *fep = netdev_priv(ndev); 2205 2206 strlcpy(info->driver, fep->pdev->dev.driver->name, 2207 sizeof(info->driver)); 2208 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2209 } 2210 2211 static int fec_enet_get_regs_len(struct net_device *ndev) 2212 { 2213 struct fec_enet_private *fep = netdev_priv(ndev); 2214 struct resource *r; 2215 int s = 0; 2216 2217 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2218 if (r) 2219 s = resource_size(r); 2220 2221 return s; 2222 } 2223 2224 /* List of registers that can be safety be read to dump them with ethtool */ 2225 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2226 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2227 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2228 static __u32 fec_enet_register_version = 2; 2229 static u32 fec_enet_register_offset[] = { 2230 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2231 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2232 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2233 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2234 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2235 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2236 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2237 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2238 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2239 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2240 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2241 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2242 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2243 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2244 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2245 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2246 RMON_T_P_GTE2048, RMON_T_OCTETS, 2247 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2248 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2249 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2250 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2251 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2252 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2253 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2254 RMON_R_P_GTE2048, RMON_R_OCTETS, 2255 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2256 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2257 }; 2258 #else 2259 static __u32 fec_enet_register_version = 1; 2260 static u32 fec_enet_register_offset[] = { 2261 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2262 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2263 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2264 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2265 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2266 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2267 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2268 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2269 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2270 }; 2271 #endif 2272 2273 static void fec_enet_get_regs(struct net_device *ndev, 2274 struct ethtool_regs *regs, void *regbuf) 2275 { 2276 struct fec_enet_private *fep = netdev_priv(ndev); 2277 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2278 struct device *dev = &fep->pdev->dev; 2279 u32 *buf = (u32 *)regbuf; 2280 u32 i, off; 2281 int ret; 2282 2283 ret = pm_runtime_get_sync(dev); 2284 if (ret < 0) 2285 return; 2286 2287 regs->version = fec_enet_register_version; 2288 2289 memset(buf, 0, regs->len); 2290 2291 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2292 off = fec_enet_register_offset[i]; 2293 2294 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2295 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2296 continue; 2297 2298 off >>= 2; 2299 buf[off] = readl(&theregs[off]); 2300 } 2301 2302 pm_runtime_mark_last_busy(dev); 2303 pm_runtime_put_autosuspend(dev); 2304 } 2305 2306 static int fec_enet_get_ts_info(struct net_device *ndev, 2307 struct ethtool_ts_info *info) 2308 { 2309 struct fec_enet_private *fep = netdev_priv(ndev); 2310 2311 if (fep->bufdesc_ex) { 2312 2313 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2314 SOF_TIMESTAMPING_RX_SOFTWARE | 2315 SOF_TIMESTAMPING_SOFTWARE | 2316 SOF_TIMESTAMPING_TX_HARDWARE | 2317 SOF_TIMESTAMPING_RX_HARDWARE | 2318 SOF_TIMESTAMPING_RAW_HARDWARE; 2319 if (fep->ptp_clock) 2320 info->phc_index = ptp_clock_index(fep->ptp_clock); 2321 else 2322 info->phc_index = -1; 2323 2324 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2325 (1 << HWTSTAMP_TX_ON); 2326 2327 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2328 (1 << HWTSTAMP_FILTER_ALL); 2329 return 0; 2330 } else { 2331 return ethtool_op_get_ts_info(ndev, info); 2332 } 2333 } 2334 2335 #if !defined(CONFIG_M5272) 2336 2337 static void fec_enet_get_pauseparam(struct net_device *ndev, 2338 struct ethtool_pauseparam *pause) 2339 { 2340 struct fec_enet_private *fep = netdev_priv(ndev); 2341 2342 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2343 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2344 pause->rx_pause = pause->tx_pause; 2345 } 2346 2347 static int fec_enet_set_pauseparam(struct net_device *ndev, 2348 struct ethtool_pauseparam *pause) 2349 { 2350 struct fec_enet_private *fep = netdev_priv(ndev); 2351 2352 if (!ndev->phydev) 2353 return -ENODEV; 2354 2355 if (pause->tx_pause != pause->rx_pause) { 2356 netdev_info(ndev, 2357 "hardware only support enable/disable both tx and rx"); 2358 return -EINVAL; 2359 } 2360 2361 fep->pause_flag = 0; 2362 2363 /* tx pause must be same as rx pause */ 2364 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2365 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2366 2367 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2368 pause->autoneg); 2369 2370 if (pause->autoneg) { 2371 if (netif_running(ndev)) 2372 fec_stop(ndev); 2373 phy_start_aneg(ndev->phydev); 2374 } 2375 if (netif_running(ndev)) { 2376 napi_disable(&fep->napi); 2377 netif_tx_lock_bh(ndev); 2378 fec_restart(ndev); 2379 netif_tx_wake_all_queues(ndev); 2380 netif_tx_unlock_bh(ndev); 2381 napi_enable(&fep->napi); 2382 } 2383 2384 return 0; 2385 } 2386 2387 static const struct fec_stat { 2388 char name[ETH_GSTRING_LEN]; 2389 u16 offset; 2390 } fec_stats[] = { 2391 /* RMON TX */ 2392 { "tx_dropped", RMON_T_DROP }, 2393 { "tx_packets", RMON_T_PACKETS }, 2394 { "tx_broadcast", RMON_T_BC_PKT }, 2395 { "tx_multicast", RMON_T_MC_PKT }, 2396 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2397 { "tx_undersize", RMON_T_UNDERSIZE }, 2398 { "tx_oversize", RMON_T_OVERSIZE }, 2399 { "tx_fragment", RMON_T_FRAG }, 2400 { "tx_jabber", RMON_T_JAB }, 2401 { "tx_collision", RMON_T_COL }, 2402 { "tx_64byte", RMON_T_P64 }, 2403 { "tx_65to127byte", RMON_T_P65TO127 }, 2404 { "tx_128to255byte", RMON_T_P128TO255 }, 2405 { "tx_256to511byte", RMON_T_P256TO511 }, 2406 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2407 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2408 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2409 { "tx_octets", RMON_T_OCTETS }, 2410 2411 /* IEEE TX */ 2412 { "IEEE_tx_drop", IEEE_T_DROP }, 2413 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2414 { "IEEE_tx_1col", IEEE_T_1COL }, 2415 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2416 { "IEEE_tx_def", IEEE_T_DEF }, 2417 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2418 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2419 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2420 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2421 { "IEEE_tx_sqe", IEEE_T_SQE }, 2422 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2423 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2424 2425 /* RMON RX */ 2426 { "rx_packets", RMON_R_PACKETS }, 2427 { "rx_broadcast", RMON_R_BC_PKT }, 2428 { "rx_multicast", RMON_R_MC_PKT }, 2429 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2430 { "rx_undersize", RMON_R_UNDERSIZE }, 2431 { "rx_oversize", RMON_R_OVERSIZE }, 2432 { "rx_fragment", RMON_R_FRAG }, 2433 { "rx_jabber", RMON_R_JAB }, 2434 { "rx_64byte", RMON_R_P64 }, 2435 { "rx_65to127byte", RMON_R_P65TO127 }, 2436 { "rx_128to255byte", RMON_R_P128TO255 }, 2437 { "rx_256to511byte", RMON_R_P256TO511 }, 2438 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2439 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2440 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2441 { "rx_octets", RMON_R_OCTETS }, 2442 2443 /* IEEE RX */ 2444 { "IEEE_rx_drop", IEEE_R_DROP }, 2445 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2446 { "IEEE_rx_crc", IEEE_R_CRC }, 2447 { "IEEE_rx_align", IEEE_R_ALIGN }, 2448 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2449 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2450 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2451 }; 2452 2453 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2454 2455 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2456 { 2457 struct fec_enet_private *fep = netdev_priv(dev); 2458 int i; 2459 2460 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2461 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2462 } 2463 2464 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2465 struct ethtool_stats *stats, u64 *data) 2466 { 2467 struct fec_enet_private *fep = netdev_priv(dev); 2468 2469 if (netif_running(dev)) 2470 fec_enet_update_ethtool_stats(dev); 2471 2472 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2473 } 2474 2475 static void fec_enet_get_strings(struct net_device *netdev, 2476 u32 stringset, u8 *data) 2477 { 2478 int i; 2479 switch (stringset) { 2480 case ETH_SS_STATS: 2481 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2482 memcpy(data + i * ETH_GSTRING_LEN, 2483 fec_stats[i].name, ETH_GSTRING_LEN); 2484 break; 2485 } 2486 } 2487 2488 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2489 { 2490 switch (sset) { 2491 case ETH_SS_STATS: 2492 return ARRAY_SIZE(fec_stats); 2493 default: 2494 return -EOPNOTSUPP; 2495 } 2496 } 2497 2498 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2499 { 2500 struct fec_enet_private *fep = netdev_priv(dev); 2501 int i; 2502 2503 /* Disable MIB statistics counters */ 2504 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2505 2506 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2507 writel(0, fep->hwp + fec_stats[i].offset); 2508 2509 /* Don't disable MIB statistics counters */ 2510 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2511 } 2512 2513 #else /* !defined(CONFIG_M5272) */ 2514 #define FEC_STATS_SIZE 0 2515 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2516 { 2517 } 2518 2519 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2520 { 2521 } 2522 #endif /* !defined(CONFIG_M5272) */ 2523 2524 /* ITR clock source is enet system clock (clk_ahb). 2525 * TCTT unit is cycle_ns * 64 cycle 2526 * So, the ICTT value = X us / (cycle_ns * 64) 2527 */ 2528 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2529 { 2530 struct fec_enet_private *fep = netdev_priv(ndev); 2531 2532 return us * (fep->itr_clk_rate / 64000) / 1000; 2533 } 2534 2535 /* Set threshold for interrupt coalescing */ 2536 static void fec_enet_itr_coal_set(struct net_device *ndev) 2537 { 2538 struct fec_enet_private *fep = netdev_priv(ndev); 2539 int rx_itr, tx_itr; 2540 2541 /* Must be greater than zero to avoid unpredictable behavior */ 2542 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2543 !fep->tx_time_itr || !fep->tx_pkts_itr) 2544 return; 2545 2546 /* Select enet system clock as Interrupt Coalescing 2547 * timer Clock Source 2548 */ 2549 rx_itr = FEC_ITR_CLK_SEL; 2550 tx_itr = FEC_ITR_CLK_SEL; 2551 2552 /* set ICFT and ICTT */ 2553 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2554 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2555 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2556 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2557 2558 rx_itr |= FEC_ITR_EN; 2559 tx_itr |= FEC_ITR_EN; 2560 2561 writel(tx_itr, fep->hwp + FEC_TXIC0); 2562 writel(rx_itr, fep->hwp + FEC_RXIC0); 2563 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 2564 writel(tx_itr, fep->hwp + FEC_TXIC1); 2565 writel(rx_itr, fep->hwp + FEC_RXIC1); 2566 writel(tx_itr, fep->hwp + FEC_TXIC2); 2567 writel(rx_itr, fep->hwp + FEC_RXIC2); 2568 } 2569 } 2570 2571 static int 2572 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2573 { 2574 struct fec_enet_private *fep = netdev_priv(ndev); 2575 2576 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2577 return -EOPNOTSUPP; 2578 2579 ec->rx_coalesce_usecs = fep->rx_time_itr; 2580 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2581 2582 ec->tx_coalesce_usecs = fep->tx_time_itr; 2583 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2584 2585 return 0; 2586 } 2587 2588 static int 2589 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2590 { 2591 struct fec_enet_private *fep = netdev_priv(ndev); 2592 struct device *dev = &fep->pdev->dev; 2593 unsigned int cycle; 2594 2595 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2596 return -EOPNOTSUPP; 2597 2598 if (ec->rx_max_coalesced_frames > 255) { 2599 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 2600 return -EINVAL; 2601 } 2602 2603 if (ec->tx_max_coalesced_frames > 255) { 2604 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 2605 return -EINVAL; 2606 } 2607 2608 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 2609 if (cycle > 0xFFFF) { 2610 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 2611 return -EINVAL; 2612 } 2613 2614 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 2615 if (cycle > 0xFFFF) { 2616 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 2617 return -EINVAL; 2618 } 2619 2620 fep->rx_time_itr = ec->rx_coalesce_usecs; 2621 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2622 2623 fep->tx_time_itr = ec->tx_coalesce_usecs; 2624 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2625 2626 fec_enet_itr_coal_set(ndev); 2627 2628 return 0; 2629 } 2630 2631 static void fec_enet_itr_coal_init(struct net_device *ndev) 2632 { 2633 struct ethtool_coalesce ec; 2634 2635 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2636 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2637 2638 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2639 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2640 2641 fec_enet_set_coalesce(ndev, &ec); 2642 } 2643 2644 static int fec_enet_get_tunable(struct net_device *netdev, 2645 const struct ethtool_tunable *tuna, 2646 void *data) 2647 { 2648 struct fec_enet_private *fep = netdev_priv(netdev); 2649 int ret = 0; 2650 2651 switch (tuna->id) { 2652 case ETHTOOL_RX_COPYBREAK: 2653 *(u32 *)data = fep->rx_copybreak; 2654 break; 2655 default: 2656 ret = -EINVAL; 2657 break; 2658 } 2659 2660 return ret; 2661 } 2662 2663 static int fec_enet_set_tunable(struct net_device *netdev, 2664 const struct ethtool_tunable *tuna, 2665 const void *data) 2666 { 2667 struct fec_enet_private *fep = netdev_priv(netdev); 2668 int ret = 0; 2669 2670 switch (tuna->id) { 2671 case ETHTOOL_RX_COPYBREAK: 2672 fep->rx_copybreak = *(u32 *)data; 2673 break; 2674 default: 2675 ret = -EINVAL; 2676 break; 2677 } 2678 2679 return ret; 2680 } 2681 2682 static void 2683 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2684 { 2685 struct fec_enet_private *fep = netdev_priv(ndev); 2686 2687 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2688 wol->supported = WAKE_MAGIC; 2689 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2690 } else { 2691 wol->supported = wol->wolopts = 0; 2692 } 2693 } 2694 2695 static int 2696 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2697 { 2698 struct fec_enet_private *fep = netdev_priv(ndev); 2699 2700 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2701 return -EINVAL; 2702 2703 if (wol->wolopts & ~WAKE_MAGIC) 2704 return -EINVAL; 2705 2706 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2707 if (device_may_wakeup(&ndev->dev)) { 2708 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2709 if (fep->irq[0] > 0) 2710 enable_irq_wake(fep->irq[0]); 2711 } else { 2712 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2713 if (fep->irq[0] > 0) 2714 disable_irq_wake(fep->irq[0]); 2715 } 2716 2717 return 0; 2718 } 2719 2720 static const struct ethtool_ops fec_enet_ethtool_ops = { 2721 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2722 ETHTOOL_COALESCE_MAX_FRAMES, 2723 .get_drvinfo = fec_enet_get_drvinfo, 2724 .get_regs_len = fec_enet_get_regs_len, 2725 .get_regs = fec_enet_get_regs, 2726 .nway_reset = phy_ethtool_nway_reset, 2727 .get_link = ethtool_op_get_link, 2728 .get_coalesce = fec_enet_get_coalesce, 2729 .set_coalesce = fec_enet_set_coalesce, 2730 #ifndef CONFIG_M5272 2731 .get_pauseparam = fec_enet_get_pauseparam, 2732 .set_pauseparam = fec_enet_set_pauseparam, 2733 .get_strings = fec_enet_get_strings, 2734 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2735 .get_sset_count = fec_enet_get_sset_count, 2736 #endif 2737 .get_ts_info = fec_enet_get_ts_info, 2738 .get_tunable = fec_enet_get_tunable, 2739 .set_tunable = fec_enet_set_tunable, 2740 .get_wol = fec_enet_get_wol, 2741 .set_wol = fec_enet_set_wol, 2742 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2743 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2744 }; 2745 2746 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2747 { 2748 struct fec_enet_private *fep = netdev_priv(ndev); 2749 struct phy_device *phydev = ndev->phydev; 2750 2751 if (!netif_running(ndev)) 2752 return -EINVAL; 2753 2754 if (!phydev) 2755 return -ENODEV; 2756 2757 if (fep->bufdesc_ex) { 2758 if (cmd == SIOCSHWTSTAMP) 2759 return fec_ptp_set(ndev, rq); 2760 if (cmd == SIOCGHWTSTAMP) 2761 return fec_ptp_get(ndev, rq); 2762 } 2763 2764 return phy_mii_ioctl(phydev, rq, cmd); 2765 } 2766 2767 static void fec_enet_free_buffers(struct net_device *ndev) 2768 { 2769 struct fec_enet_private *fep = netdev_priv(ndev); 2770 unsigned int i; 2771 struct sk_buff *skb; 2772 struct bufdesc *bdp; 2773 struct fec_enet_priv_tx_q *txq; 2774 struct fec_enet_priv_rx_q *rxq; 2775 unsigned int q; 2776 2777 for (q = 0; q < fep->num_rx_queues; q++) { 2778 rxq = fep->rx_queue[q]; 2779 bdp = rxq->bd.base; 2780 for (i = 0; i < rxq->bd.ring_size; i++) { 2781 skb = rxq->rx_skbuff[i]; 2782 rxq->rx_skbuff[i] = NULL; 2783 if (skb) { 2784 dma_unmap_single(&fep->pdev->dev, 2785 fec32_to_cpu(bdp->cbd_bufaddr), 2786 FEC_ENET_RX_FRSIZE - fep->rx_align, 2787 DMA_FROM_DEVICE); 2788 dev_kfree_skb(skb); 2789 } 2790 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2791 } 2792 } 2793 2794 for (q = 0; q < fep->num_tx_queues; q++) { 2795 txq = fep->tx_queue[q]; 2796 for (i = 0; i < txq->bd.ring_size; i++) { 2797 kfree(txq->tx_bounce[i]); 2798 txq->tx_bounce[i] = NULL; 2799 skb = txq->tx_skbuff[i]; 2800 txq->tx_skbuff[i] = NULL; 2801 dev_kfree_skb(skb); 2802 } 2803 } 2804 } 2805 2806 static void fec_enet_free_queue(struct net_device *ndev) 2807 { 2808 struct fec_enet_private *fep = netdev_priv(ndev); 2809 int i; 2810 struct fec_enet_priv_tx_q *txq; 2811 2812 for (i = 0; i < fep->num_tx_queues; i++) 2813 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2814 txq = fep->tx_queue[i]; 2815 dma_free_coherent(&fep->pdev->dev, 2816 txq->bd.ring_size * TSO_HEADER_SIZE, 2817 txq->tso_hdrs, 2818 txq->tso_hdrs_dma); 2819 } 2820 2821 for (i = 0; i < fep->num_rx_queues; i++) 2822 kfree(fep->rx_queue[i]); 2823 for (i = 0; i < fep->num_tx_queues; i++) 2824 kfree(fep->tx_queue[i]); 2825 } 2826 2827 static int fec_enet_alloc_queue(struct net_device *ndev) 2828 { 2829 struct fec_enet_private *fep = netdev_priv(ndev); 2830 int i; 2831 int ret = 0; 2832 struct fec_enet_priv_tx_q *txq; 2833 2834 for (i = 0; i < fep->num_tx_queues; i++) { 2835 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 2836 if (!txq) { 2837 ret = -ENOMEM; 2838 goto alloc_failed; 2839 } 2840 2841 fep->tx_queue[i] = txq; 2842 txq->bd.ring_size = TX_RING_SIZE; 2843 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 2844 2845 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2846 txq->tx_wake_threshold = 2847 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 2848 2849 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 2850 txq->bd.ring_size * TSO_HEADER_SIZE, 2851 &txq->tso_hdrs_dma, 2852 GFP_KERNEL); 2853 if (!txq->tso_hdrs) { 2854 ret = -ENOMEM; 2855 goto alloc_failed; 2856 } 2857 } 2858 2859 for (i = 0; i < fep->num_rx_queues; i++) { 2860 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 2861 GFP_KERNEL); 2862 if (!fep->rx_queue[i]) { 2863 ret = -ENOMEM; 2864 goto alloc_failed; 2865 } 2866 2867 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 2868 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 2869 } 2870 return ret; 2871 2872 alloc_failed: 2873 fec_enet_free_queue(ndev); 2874 return ret; 2875 } 2876 2877 static int 2878 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 2879 { 2880 struct fec_enet_private *fep = netdev_priv(ndev); 2881 unsigned int i; 2882 struct sk_buff *skb; 2883 struct bufdesc *bdp; 2884 struct fec_enet_priv_rx_q *rxq; 2885 2886 rxq = fep->rx_queue[queue]; 2887 bdp = rxq->bd.base; 2888 for (i = 0; i < rxq->bd.ring_size; i++) { 2889 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2890 if (!skb) 2891 goto err_alloc; 2892 2893 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 2894 dev_kfree_skb(skb); 2895 goto err_alloc; 2896 } 2897 2898 rxq->rx_skbuff[i] = skb; 2899 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 2900 2901 if (fep->bufdesc_ex) { 2902 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2903 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 2904 } 2905 2906 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2907 } 2908 2909 /* Set the last buffer to wrap. */ 2910 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 2911 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2912 return 0; 2913 2914 err_alloc: 2915 fec_enet_free_buffers(ndev); 2916 return -ENOMEM; 2917 } 2918 2919 static int 2920 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 2921 { 2922 struct fec_enet_private *fep = netdev_priv(ndev); 2923 unsigned int i; 2924 struct bufdesc *bdp; 2925 struct fec_enet_priv_tx_q *txq; 2926 2927 txq = fep->tx_queue[queue]; 2928 bdp = txq->bd.base; 2929 for (i = 0; i < txq->bd.ring_size; i++) { 2930 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2931 if (!txq->tx_bounce[i]) 2932 goto err_alloc; 2933 2934 bdp->cbd_sc = cpu_to_fec16(0); 2935 bdp->cbd_bufaddr = cpu_to_fec32(0); 2936 2937 if (fep->bufdesc_ex) { 2938 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2939 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 2940 } 2941 2942 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 2943 } 2944 2945 /* Set the last buffer to wrap. */ 2946 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 2947 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2948 2949 return 0; 2950 2951 err_alloc: 2952 fec_enet_free_buffers(ndev); 2953 return -ENOMEM; 2954 } 2955 2956 static int fec_enet_alloc_buffers(struct net_device *ndev) 2957 { 2958 struct fec_enet_private *fep = netdev_priv(ndev); 2959 unsigned int i; 2960 2961 for (i = 0; i < fep->num_rx_queues; i++) 2962 if (fec_enet_alloc_rxq_buffers(ndev, i)) 2963 return -ENOMEM; 2964 2965 for (i = 0; i < fep->num_tx_queues; i++) 2966 if (fec_enet_alloc_txq_buffers(ndev, i)) 2967 return -ENOMEM; 2968 return 0; 2969 } 2970 2971 static int 2972 fec_enet_open(struct net_device *ndev) 2973 { 2974 struct fec_enet_private *fep = netdev_priv(ndev); 2975 int ret; 2976 bool reset_again; 2977 2978 ret = pm_runtime_get_sync(&fep->pdev->dev); 2979 if (ret < 0) 2980 return ret; 2981 2982 pinctrl_pm_select_default_state(&fep->pdev->dev); 2983 ret = fec_enet_clk_enable(ndev, true); 2984 if (ret) 2985 goto clk_enable; 2986 2987 /* During the first fec_enet_open call the PHY isn't probed at this 2988 * point. Therefore the phy_reset_after_clk_enable() call within 2989 * fec_enet_clk_enable() fails. As we need this reset in order to be 2990 * sure the PHY is working correctly we check if we need to reset again 2991 * later when the PHY is probed 2992 */ 2993 if (ndev->phydev && ndev->phydev->drv) 2994 reset_again = false; 2995 else 2996 reset_again = true; 2997 2998 /* I should reset the ring buffers here, but I don't yet know 2999 * a simple way to do that. 3000 */ 3001 3002 ret = fec_enet_alloc_buffers(ndev); 3003 if (ret) 3004 goto err_enet_alloc; 3005 3006 /* Init MAC prior to mii bus probe */ 3007 fec_restart(ndev); 3008 3009 /* Probe and connect to PHY when open the interface */ 3010 ret = fec_enet_mii_probe(ndev); 3011 if (ret) 3012 goto err_enet_mii_probe; 3013 3014 /* Call phy_reset_after_clk_enable() again if it failed during 3015 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3016 */ 3017 if (reset_again) 3018 phy_reset_after_clk_enable(ndev->phydev); 3019 3020 if (fep->quirks & FEC_QUIRK_ERR006687) 3021 imx6q_cpuidle_fec_irqs_used(); 3022 3023 napi_enable(&fep->napi); 3024 phy_start(ndev->phydev); 3025 netif_tx_start_all_queues(ndev); 3026 3027 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3028 FEC_WOL_FLAG_ENABLE); 3029 3030 return 0; 3031 3032 err_enet_mii_probe: 3033 fec_enet_free_buffers(ndev); 3034 err_enet_alloc: 3035 fec_enet_clk_enable(ndev, false); 3036 clk_enable: 3037 pm_runtime_mark_last_busy(&fep->pdev->dev); 3038 pm_runtime_put_autosuspend(&fep->pdev->dev); 3039 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3040 return ret; 3041 } 3042 3043 static int 3044 fec_enet_close(struct net_device *ndev) 3045 { 3046 struct fec_enet_private *fep = netdev_priv(ndev); 3047 3048 phy_stop(ndev->phydev); 3049 3050 if (netif_device_present(ndev)) { 3051 napi_disable(&fep->napi); 3052 netif_tx_disable(ndev); 3053 fec_stop(ndev); 3054 } 3055 3056 phy_disconnect(ndev->phydev); 3057 3058 if (fep->quirks & FEC_QUIRK_ERR006687) 3059 imx6q_cpuidle_fec_irqs_unused(); 3060 3061 fec_enet_update_ethtool_stats(ndev); 3062 3063 fec_enet_clk_enable(ndev, false); 3064 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3065 pm_runtime_mark_last_busy(&fep->pdev->dev); 3066 pm_runtime_put_autosuspend(&fep->pdev->dev); 3067 3068 fec_enet_free_buffers(ndev); 3069 3070 return 0; 3071 } 3072 3073 /* Set or clear the multicast filter for this adaptor. 3074 * Skeleton taken from sunlance driver. 3075 * The CPM Ethernet implementation allows Multicast as well as individual 3076 * MAC address filtering. Some of the drivers check to make sure it is 3077 * a group multicast address, and discard those that are not. I guess I 3078 * will do the same for now, but just remove the test if you want 3079 * individual filtering as well (do the upper net layers want or support 3080 * this kind of feature?). 3081 */ 3082 3083 #define FEC_HASH_BITS 6 /* #bits in hash */ 3084 3085 static void set_multicast_list(struct net_device *ndev) 3086 { 3087 struct fec_enet_private *fep = netdev_priv(ndev); 3088 struct netdev_hw_addr *ha; 3089 unsigned int crc, tmp; 3090 unsigned char hash; 3091 unsigned int hash_high = 0, hash_low = 0; 3092 3093 if (ndev->flags & IFF_PROMISC) { 3094 tmp = readl(fep->hwp + FEC_R_CNTRL); 3095 tmp |= 0x8; 3096 writel(tmp, fep->hwp + FEC_R_CNTRL); 3097 return; 3098 } 3099 3100 tmp = readl(fep->hwp + FEC_R_CNTRL); 3101 tmp &= ~0x8; 3102 writel(tmp, fep->hwp + FEC_R_CNTRL); 3103 3104 if (ndev->flags & IFF_ALLMULTI) { 3105 /* Catch all multicast addresses, so set the 3106 * filter to all 1's 3107 */ 3108 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3109 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3110 3111 return; 3112 } 3113 3114 /* Add the addresses in hash register */ 3115 netdev_for_each_mc_addr(ha, ndev) { 3116 /* calculate crc32 value of mac address */ 3117 crc = ether_crc_le(ndev->addr_len, ha->addr); 3118 3119 /* only upper 6 bits (FEC_HASH_BITS) are used 3120 * which point to specific bit in the hash registers 3121 */ 3122 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3123 3124 if (hash > 31) 3125 hash_high |= 1 << (hash - 32); 3126 else 3127 hash_low |= 1 << hash; 3128 } 3129 3130 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3131 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3132 } 3133 3134 /* Set a MAC change in hardware. */ 3135 static int 3136 fec_set_mac_address(struct net_device *ndev, void *p) 3137 { 3138 struct fec_enet_private *fep = netdev_priv(ndev); 3139 struct sockaddr *addr = p; 3140 3141 if (addr) { 3142 if (!is_valid_ether_addr(addr->sa_data)) 3143 return -EADDRNOTAVAIL; 3144 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 3145 } 3146 3147 /* Add netif status check here to avoid system hang in below case: 3148 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3149 * After ethx down, fec all clocks are gated off and then register 3150 * access causes system hang. 3151 */ 3152 if (!netif_running(ndev)) 3153 return 0; 3154 3155 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3156 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3157 fep->hwp + FEC_ADDR_LOW); 3158 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3159 fep->hwp + FEC_ADDR_HIGH); 3160 return 0; 3161 } 3162 3163 #ifdef CONFIG_NET_POLL_CONTROLLER 3164 /** 3165 * fec_poll_controller - FEC Poll controller function 3166 * @dev: The FEC network adapter 3167 * 3168 * Polled functionality used by netconsole and others in non interrupt mode 3169 * 3170 */ 3171 static void fec_poll_controller(struct net_device *dev) 3172 { 3173 int i; 3174 struct fec_enet_private *fep = netdev_priv(dev); 3175 3176 for (i = 0; i < FEC_IRQ_NUM; i++) { 3177 if (fep->irq[i] > 0) { 3178 disable_irq(fep->irq[i]); 3179 fec_enet_interrupt(fep->irq[i], dev); 3180 enable_irq(fep->irq[i]); 3181 } 3182 } 3183 } 3184 #endif 3185 3186 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3187 netdev_features_t features) 3188 { 3189 struct fec_enet_private *fep = netdev_priv(netdev); 3190 netdev_features_t changed = features ^ netdev->features; 3191 3192 netdev->features = features; 3193 3194 /* Receive checksum has been changed */ 3195 if (changed & NETIF_F_RXCSUM) { 3196 if (features & NETIF_F_RXCSUM) 3197 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3198 else 3199 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3200 } 3201 } 3202 3203 static int fec_set_features(struct net_device *netdev, 3204 netdev_features_t features) 3205 { 3206 struct fec_enet_private *fep = netdev_priv(netdev); 3207 netdev_features_t changed = features ^ netdev->features; 3208 3209 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3210 napi_disable(&fep->napi); 3211 netif_tx_lock_bh(netdev); 3212 fec_stop(netdev); 3213 fec_enet_set_netdev_features(netdev, features); 3214 fec_restart(netdev); 3215 netif_tx_wake_all_queues(netdev); 3216 netif_tx_unlock_bh(netdev); 3217 napi_enable(&fep->napi); 3218 } else { 3219 fec_enet_set_netdev_features(netdev, features); 3220 } 3221 3222 return 0; 3223 } 3224 3225 static const struct net_device_ops fec_netdev_ops = { 3226 .ndo_open = fec_enet_open, 3227 .ndo_stop = fec_enet_close, 3228 .ndo_start_xmit = fec_enet_start_xmit, 3229 .ndo_set_rx_mode = set_multicast_list, 3230 .ndo_validate_addr = eth_validate_addr, 3231 .ndo_tx_timeout = fec_timeout, 3232 .ndo_set_mac_address = fec_set_mac_address, 3233 .ndo_do_ioctl = fec_enet_ioctl, 3234 #ifdef CONFIG_NET_POLL_CONTROLLER 3235 .ndo_poll_controller = fec_poll_controller, 3236 #endif 3237 .ndo_set_features = fec_set_features, 3238 }; 3239 3240 static const unsigned short offset_des_active_rxq[] = { 3241 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3242 }; 3243 3244 static const unsigned short offset_des_active_txq[] = { 3245 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3246 }; 3247 3248 /* 3249 * XXX: We need to clean up on failure exits here. 3250 * 3251 */ 3252 static int fec_enet_init(struct net_device *ndev) 3253 { 3254 struct fec_enet_private *fep = netdev_priv(ndev); 3255 struct bufdesc *cbd_base; 3256 dma_addr_t bd_dma; 3257 int bd_size; 3258 unsigned int i; 3259 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3260 sizeof(struct bufdesc); 3261 unsigned dsize_log2 = __fls(dsize); 3262 int ret; 3263 3264 WARN_ON(dsize != (1 << dsize_log2)); 3265 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 3266 fep->rx_align = 0xf; 3267 fep->tx_align = 0xf; 3268 #else 3269 fep->rx_align = 0x3; 3270 fep->tx_align = 0x3; 3271 #endif 3272 3273 /* Check mask of the streaming and coherent API */ 3274 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 3275 if (ret < 0) { 3276 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 3277 return ret; 3278 } 3279 3280 fec_enet_alloc_queue(ndev); 3281 3282 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3283 3284 /* Allocate memory for buffer descriptors. */ 3285 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3286 GFP_KERNEL); 3287 if (!cbd_base) { 3288 return -ENOMEM; 3289 } 3290 3291 /* Get the Ethernet address */ 3292 fec_get_mac(ndev); 3293 /* make sure MAC we just acquired is programmed into the hw */ 3294 fec_set_mac_address(ndev, NULL); 3295 3296 /* Set receive and transmit descriptor base. */ 3297 for (i = 0; i < fep->num_rx_queues; i++) { 3298 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3299 unsigned size = dsize * rxq->bd.ring_size; 3300 3301 rxq->bd.qid = i; 3302 rxq->bd.base = cbd_base; 3303 rxq->bd.cur = cbd_base; 3304 rxq->bd.dma = bd_dma; 3305 rxq->bd.dsize = dsize; 3306 rxq->bd.dsize_log2 = dsize_log2; 3307 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3308 bd_dma += size; 3309 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3310 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3311 } 3312 3313 for (i = 0; i < fep->num_tx_queues; i++) { 3314 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3315 unsigned size = dsize * txq->bd.ring_size; 3316 3317 txq->bd.qid = i; 3318 txq->bd.base = cbd_base; 3319 txq->bd.cur = cbd_base; 3320 txq->bd.dma = bd_dma; 3321 txq->bd.dsize = dsize; 3322 txq->bd.dsize_log2 = dsize_log2; 3323 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3324 bd_dma += size; 3325 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3326 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3327 } 3328 3329 3330 /* The FEC Ethernet specific entries in the device structure */ 3331 ndev->watchdog_timeo = TX_TIMEOUT; 3332 ndev->netdev_ops = &fec_netdev_ops; 3333 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3334 3335 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3336 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3337 3338 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3339 /* enable hw VLAN support */ 3340 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3341 3342 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3343 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3344 3345 /* enable hw accelerator */ 3346 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3347 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3348 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3349 } 3350 3351 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 3352 fep->tx_align = 0; 3353 fep->rx_align = 0x3f; 3354 } 3355 3356 ndev->hw_features = ndev->features; 3357 3358 fec_restart(ndev); 3359 3360 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 3361 fec_enet_clear_ethtool_stats(ndev); 3362 else 3363 fec_enet_update_ethtool_stats(ndev); 3364 3365 return 0; 3366 } 3367 3368 #ifdef CONFIG_OF 3369 static int fec_reset_phy(struct platform_device *pdev) 3370 { 3371 int err, phy_reset; 3372 bool active_high = false; 3373 int msec = 1, phy_post_delay = 0; 3374 struct device_node *np = pdev->dev.of_node; 3375 3376 if (!np) 3377 return 0; 3378 3379 err = of_property_read_u32(np, "phy-reset-duration", &msec); 3380 /* A sane reset duration should not be longer than 1s */ 3381 if (!err && msec > 1000) 3382 msec = 1; 3383 3384 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3385 if (phy_reset == -EPROBE_DEFER) 3386 return phy_reset; 3387 else if (!gpio_is_valid(phy_reset)) 3388 return 0; 3389 3390 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 3391 /* valid reset duration should be less than 1s */ 3392 if (!err && phy_post_delay > 1000) 3393 return -EINVAL; 3394 3395 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3396 3397 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3398 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3399 "phy-reset"); 3400 if (err) { 3401 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3402 return err; 3403 } 3404 3405 if (msec > 20) 3406 msleep(msec); 3407 else 3408 usleep_range(msec * 1000, msec * 1000 + 1000); 3409 3410 gpio_set_value_cansleep(phy_reset, !active_high); 3411 3412 if (!phy_post_delay) 3413 return 0; 3414 3415 if (phy_post_delay > 20) 3416 msleep(phy_post_delay); 3417 else 3418 usleep_range(phy_post_delay * 1000, 3419 phy_post_delay * 1000 + 1000); 3420 3421 return 0; 3422 } 3423 #else /* CONFIG_OF */ 3424 static int fec_reset_phy(struct platform_device *pdev) 3425 { 3426 /* 3427 * In case of platform probe, the reset has been done 3428 * by machine code. 3429 */ 3430 return 0; 3431 } 3432 #endif /* CONFIG_OF */ 3433 3434 static void 3435 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3436 { 3437 struct device_node *np = pdev->dev.of_node; 3438 3439 *num_tx = *num_rx = 1; 3440 3441 if (!np || !of_device_is_available(np)) 3442 return; 3443 3444 /* parse the num of tx and rx queues */ 3445 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3446 3447 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3448 3449 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3450 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3451 *num_tx); 3452 *num_tx = 1; 3453 return; 3454 } 3455 3456 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3457 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3458 *num_rx); 3459 *num_rx = 1; 3460 return; 3461 } 3462 3463 } 3464 3465 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 3466 { 3467 int irq_cnt = platform_irq_count(pdev); 3468 3469 if (irq_cnt > FEC_IRQ_NUM) 3470 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 3471 else if (irq_cnt == 2) 3472 irq_cnt = 1; /* last for pps */ 3473 else if (irq_cnt <= 0) 3474 irq_cnt = 1; /* At least 1 irq is needed */ 3475 return irq_cnt; 3476 } 3477 3478 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 3479 struct fec_devinfo *dev_info, 3480 struct device_node *np) 3481 { 3482 struct device_node *gpr_np; 3483 int ret = 0; 3484 3485 if (!dev_info) 3486 return 0; 3487 3488 gpr_np = of_parse_phandle(np, "gpr", 0); 3489 if (!gpr_np) 3490 return 0; 3491 3492 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 3493 if (IS_ERR(fep->stop_gpr.gpr)) { 3494 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 3495 ret = PTR_ERR(fep->stop_gpr.gpr); 3496 fep->stop_gpr.gpr = NULL; 3497 goto out; 3498 } 3499 3500 fep->stop_gpr.reg = dev_info->stop_gpr_reg; 3501 fep->stop_gpr.bit = dev_info->stop_gpr_bit; 3502 3503 out: 3504 of_node_put(gpr_np); 3505 3506 return ret; 3507 } 3508 3509 static int 3510 fec_probe(struct platform_device *pdev) 3511 { 3512 struct fec_enet_private *fep; 3513 struct fec_platform_data *pdata; 3514 phy_interface_t interface; 3515 struct net_device *ndev; 3516 int i, irq, ret = 0; 3517 const struct of_device_id *of_id; 3518 static int dev_id; 3519 struct device_node *np = pdev->dev.of_node, *phy_node; 3520 int num_tx_qs; 3521 int num_rx_qs; 3522 char irq_name[8]; 3523 int irq_cnt; 3524 struct fec_devinfo *dev_info; 3525 3526 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3527 3528 /* Init network device */ 3529 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 3530 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 3531 if (!ndev) 3532 return -ENOMEM; 3533 3534 SET_NETDEV_DEV(ndev, &pdev->dev); 3535 3536 /* setup board info structure */ 3537 fep = netdev_priv(ndev); 3538 3539 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3540 if (of_id) 3541 pdev->id_entry = of_id->data; 3542 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; 3543 if (dev_info) 3544 fep->quirks = dev_info->quirks; 3545 3546 fep->netdev = ndev; 3547 fep->num_rx_queues = num_rx_qs; 3548 fep->num_tx_queues = num_tx_qs; 3549 3550 #if !defined(CONFIG_M5272) 3551 /* default enable pause frame auto negotiation */ 3552 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3553 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3554 #endif 3555 3556 /* Select default pin state */ 3557 pinctrl_pm_select_default_state(&pdev->dev); 3558 3559 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 3560 if (IS_ERR(fep->hwp)) { 3561 ret = PTR_ERR(fep->hwp); 3562 goto failed_ioremap; 3563 } 3564 3565 fep->pdev = pdev; 3566 fep->dev_id = dev_id++; 3567 3568 platform_set_drvdata(pdev, ndev); 3569 3570 if ((of_machine_is_compatible("fsl,imx6q") || 3571 of_machine_is_compatible("fsl,imx6dl")) && 3572 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 3573 fep->quirks |= FEC_QUIRK_ERR006687; 3574 3575 if (of_get_property(np, "fsl,magic-packet", NULL)) 3576 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3577 3578 ret = fec_enet_init_stop_mode(fep, dev_info, np); 3579 if (ret) 3580 goto failed_stop_mode; 3581 3582 phy_node = of_parse_phandle(np, "phy-handle", 0); 3583 if (!phy_node && of_phy_is_fixed_link(np)) { 3584 ret = of_phy_register_fixed_link(np); 3585 if (ret < 0) { 3586 dev_err(&pdev->dev, 3587 "broken fixed-link specification\n"); 3588 goto failed_phy; 3589 } 3590 phy_node = of_node_get(np); 3591 } 3592 fep->phy_node = phy_node; 3593 3594 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 3595 if (ret) { 3596 pdata = dev_get_platdata(&pdev->dev); 3597 if (pdata) 3598 fep->phy_interface = pdata->phy; 3599 else 3600 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3601 } else { 3602 fep->phy_interface = interface; 3603 } 3604 3605 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3606 if (IS_ERR(fep->clk_ipg)) { 3607 ret = PTR_ERR(fep->clk_ipg); 3608 goto failed_clk; 3609 } 3610 3611 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3612 if (IS_ERR(fep->clk_ahb)) { 3613 ret = PTR_ERR(fep->clk_ahb); 3614 goto failed_clk; 3615 } 3616 3617 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3618 3619 /* enet_out is optional, depends on board */ 3620 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3621 if (IS_ERR(fep->clk_enet_out)) 3622 fep->clk_enet_out = NULL; 3623 3624 fep->ptp_clk_on = false; 3625 mutex_init(&fep->ptp_clk_mutex); 3626 3627 /* clk_ref is optional, depends on board */ 3628 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3629 if (IS_ERR(fep->clk_ref)) 3630 fep->clk_ref = NULL; 3631 3632 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3633 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3634 if (IS_ERR(fep->clk_ptp)) { 3635 fep->clk_ptp = NULL; 3636 fep->bufdesc_ex = false; 3637 } 3638 3639 ret = fec_enet_clk_enable(ndev, true); 3640 if (ret) 3641 goto failed_clk; 3642 3643 ret = clk_prepare_enable(fep->clk_ipg); 3644 if (ret) 3645 goto failed_clk_ipg; 3646 ret = clk_prepare_enable(fep->clk_ahb); 3647 if (ret) 3648 goto failed_clk_ahb; 3649 3650 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 3651 if (!IS_ERR(fep->reg_phy)) { 3652 ret = regulator_enable(fep->reg_phy); 3653 if (ret) { 3654 dev_err(&pdev->dev, 3655 "Failed to enable phy regulator: %d\n", ret); 3656 goto failed_regulator; 3657 } 3658 } else { 3659 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 3660 ret = -EPROBE_DEFER; 3661 goto failed_regulator; 3662 } 3663 fep->reg_phy = NULL; 3664 } 3665 3666 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 3667 pm_runtime_use_autosuspend(&pdev->dev); 3668 pm_runtime_get_noresume(&pdev->dev); 3669 pm_runtime_set_active(&pdev->dev); 3670 pm_runtime_enable(&pdev->dev); 3671 3672 ret = fec_reset_phy(pdev); 3673 if (ret) 3674 goto failed_reset; 3675 3676 irq_cnt = fec_enet_get_irq_cnt(pdev); 3677 if (fep->bufdesc_ex) 3678 fec_ptp_init(pdev, irq_cnt); 3679 3680 ret = fec_enet_init(ndev); 3681 if (ret) 3682 goto failed_init; 3683 3684 for (i = 0; i < irq_cnt; i++) { 3685 snprintf(irq_name, sizeof(irq_name), "int%d", i); 3686 irq = platform_get_irq_byname_optional(pdev, irq_name); 3687 if (irq < 0) 3688 irq = platform_get_irq(pdev, i); 3689 if (irq < 0) { 3690 ret = irq; 3691 goto failed_irq; 3692 } 3693 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3694 0, pdev->name, ndev); 3695 if (ret) 3696 goto failed_irq; 3697 3698 fep->irq[i] = irq; 3699 } 3700 3701 ret = fec_enet_mii_init(pdev); 3702 if (ret) 3703 goto failed_mii_init; 3704 3705 /* Carrier starts down, phylib will bring it up */ 3706 netif_carrier_off(ndev); 3707 fec_enet_clk_enable(ndev, false); 3708 pinctrl_pm_select_sleep_state(&pdev->dev); 3709 3710 ret = register_netdev(ndev); 3711 if (ret) 3712 goto failed_register; 3713 3714 device_init_wakeup(&ndev->dev, fep->wol_flag & 3715 FEC_WOL_HAS_MAGIC_PACKET); 3716 3717 if (fep->bufdesc_ex && fep->ptp_clock) 3718 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3719 3720 fep->rx_copybreak = COPYBREAK_DEFAULT; 3721 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3722 3723 pm_runtime_mark_last_busy(&pdev->dev); 3724 pm_runtime_put_autosuspend(&pdev->dev); 3725 3726 return 0; 3727 3728 failed_register: 3729 fec_enet_mii_remove(fep); 3730 failed_mii_init: 3731 failed_irq: 3732 failed_init: 3733 fec_ptp_stop(pdev); 3734 if (fep->reg_phy) 3735 regulator_disable(fep->reg_phy); 3736 failed_reset: 3737 pm_runtime_put_noidle(&pdev->dev); 3738 pm_runtime_disable(&pdev->dev); 3739 failed_regulator: 3740 clk_disable_unprepare(fep->clk_ahb); 3741 failed_clk_ahb: 3742 clk_disable_unprepare(fep->clk_ipg); 3743 failed_clk_ipg: 3744 fec_enet_clk_enable(ndev, false); 3745 failed_clk: 3746 if (of_phy_is_fixed_link(np)) 3747 of_phy_deregister_fixed_link(np); 3748 of_node_put(phy_node); 3749 failed_stop_mode: 3750 failed_phy: 3751 dev_id--; 3752 failed_ioremap: 3753 free_netdev(ndev); 3754 3755 return ret; 3756 } 3757 3758 static int 3759 fec_drv_remove(struct platform_device *pdev) 3760 { 3761 struct net_device *ndev = platform_get_drvdata(pdev); 3762 struct fec_enet_private *fep = netdev_priv(ndev); 3763 struct device_node *np = pdev->dev.of_node; 3764 int ret; 3765 3766 ret = pm_runtime_get_sync(&pdev->dev); 3767 if (ret < 0) 3768 return ret; 3769 3770 cancel_work_sync(&fep->tx_timeout_work); 3771 fec_ptp_stop(pdev); 3772 unregister_netdev(ndev); 3773 fec_enet_mii_remove(fep); 3774 if (fep->reg_phy) 3775 regulator_disable(fep->reg_phy); 3776 3777 if (of_phy_is_fixed_link(np)) 3778 of_phy_deregister_fixed_link(np); 3779 of_node_put(fep->phy_node); 3780 free_netdev(ndev); 3781 3782 clk_disable_unprepare(fep->clk_ahb); 3783 clk_disable_unprepare(fep->clk_ipg); 3784 pm_runtime_put_noidle(&pdev->dev); 3785 pm_runtime_disable(&pdev->dev); 3786 3787 return 0; 3788 } 3789 3790 static int __maybe_unused fec_suspend(struct device *dev) 3791 { 3792 struct net_device *ndev = dev_get_drvdata(dev); 3793 struct fec_enet_private *fep = netdev_priv(ndev); 3794 3795 rtnl_lock(); 3796 if (netif_running(ndev)) { 3797 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 3798 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 3799 phy_stop(ndev->phydev); 3800 napi_disable(&fep->napi); 3801 netif_tx_lock_bh(ndev); 3802 netif_device_detach(ndev); 3803 netif_tx_unlock_bh(ndev); 3804 fec_stop(ndev); 3805 fec_enet_clk_enable(ndev, false); 3806 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3807 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3808 } 3809 rtnl_unlock(); 3810 3811 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3812 regulator_disable(fep->reg_phy); 3813 3814 /* SOC supply clock to phy, when clock is disabled, phy link down 3815 * SOC control phy regulator, when regulator is disabled, phy link down 3816 */ 3817 if (fep->clk_enet_out || fep->reg_phy) 3818 fep->link = 0; 3819 3820 return 0; 3821 } 3822 3823 static int __maybe_unused fec_resume(struct device *dev) 3824 { 3825 struct net_device *ndev = dev_get_drvdata(dev); 3826 struct fec_enet_private *fep = netdev_priv(ndev); 3827 int ret; 3828 int val; 3829 3830 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 3831 ret = regulator_enable(fep->reg_phy); 3832 if (ret) 3833 return ret; 3834 } 3835 3836 rtnl_lock(); 3837 if (netif_running(ndev)) { 3838 ret = fec_enet_clk_enable(ndev, true); 3839 if (ret) { 3840 rtnl_unlock(); 3841 goto failed_clk; 3842 } 3843 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 3844 fec_enet_stop_mode(fep, false); 3845 3846 val = readl(fep->hwp + FEC_ECNTRL); 3847 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 3848 writel(val, fep->hwp + FEC_ECNTRL); 3849 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 3850 } else { 3851 pinctrl_pm_select_default_state(&fep->pdev->dev); 3852 } 3853 fec_restart(ndev); 3854 netif_tx_lock_bh(ndev); 3855 netif_device_attach(ndev); 3856 netif_tx_unlock_bh(ndev); 3857 napi_enable(&fep->napi); 3858 phy_start(ndev->phydev); 3859 } 3860 rtnl_unlock(); 3861 3862 return 0; 3863 3864 failed_clk: 3865 if (fep->reg_phy) 3866 regulator_disable(fep->reg_phy); 3867 return ret; 3868 } 3869 3870 static int __maybe_unused fec_runtime_suspend(struct device *dev) 3871 { 3872 struct net_device *ndev = dev_get_drvdata(dev); 3873 struct fec_enet_private *fep = netdev_priv(ndev); 3874 3875 clk_disable_unprepare(fep->clk_ahb); 3876 clk_disable_unprepare(fep->clk_ipg); 3877 3878 return 0; 3879 } 3880 3881 static int __maybe_unused fec_runtime_resume(struct device *dev) 3882 { 3883 struct net_device *ndev = dev_get_drvdata(dev); 3884 struct fec_enet_private *fep = netdev_priv(ndev); 3885 int ret; 3886 3887 ret = clk_prepare_enable(fep->clk_ahb); 3888 if (ret) 3889 return ret; 3890 ret = clk_prepare_enable(fep->clk_ipg); 3891 if (ret) 3892 goto failed_clk_ipg; 3893 3894 return 0; 3895 3896 failed_clk_ipg: 3897 clk_disable_unprepare(fep->clk_ahb); 3898 return ret; 3899 } 3900 3901 static const struct dev_pm_ops fec_pm_ops = { 3902 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 3903 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 3904 }; 3905 3906 static struct platform_driver fec_driver = { 3907 .driver = { 3908 .name = DRIVER_NAME, 3909 .pm = &fec_pm_ops, 3910 .of_match_table = fec_dt_ids, 3911 .suppress_bind_attrs = true, 3912 }, 3913 .id_table = fec_devtype, 3914 .probe = fec_probe, 3915 .remove = fec_drv_remove, 3916 }; 3917 3918 module_platform_driver(fec_driver); 3919 3920 MODULE_ALIAS("platform:"DRIVER_NAME); 3921 MODULE_LICENSE("GPL"); 3922