1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/bitops.h> 26 #include <linux/bpf.h> 27 #include <linux/bpf_trace.h> 28 #include <linux/cacheflush.h> 29 #include <linux/clk.h> 30 #include <linux/crc32.h> 31 #include <linux/delay.h> 32 #include <linux/errno.h> 33 #include <linux/etherdevice.h> 34 #include <linux/fec.h> 35 #include <linux/filter.h> 36 #include <linux/gpio/consumer.h> 37 #include <linux/icmp.h> 38 #include <linux/if_vlan.h> 39 #include <linux/in.h> 40 #include <linux/interrupt.h> 41 #include <linux/io.h> 42 #include <linux/ioport.h> 43 #include <linux/ip.h> 44 #include <linux/irq.h> 45 #include <linux/kernel.h> 46 #include <linux/mdio.h> 47 #include <linux/mfd/syscon.h> 48 #include <linux/module.h> 49 #include <linux/netdevice.h> 50 #include <linux/of.h> 51 #include <linux/of_mdio.h> 52 #include <linux/of_net.h> 53 #include <linux/phy.h> 54 #include <linux/pinctrl/consumer.h> 55 #include <linux/platform_device.h> 56 #include <linux/pm_runtime.h> 57 #include <linux/prefetch.h> 58 #include <linux/property.h> 59 #include <linux/ptrace.h> 60 #include <linux/regmap.h> 61 #include <linux/regulator/consumer.h> 62 #include <linux/skbuff.h> 63 #include <linux/slab.h> 64 #include <linux/spinlock.h> 65 #include <linux/string.h> 66 #include <linux/tcp.h> 67 #include <linux/udp.h> 68 #include <linux/workqueue.h> 69 #include <net/ip.h> 70 #include <net/page_pool/helpers.h> 71 #include <net/selftests.h> 72 #include <net/tso.h> 73 #include <soc/imx/cpuidle.h> 74 75 #include "fec.h" 76 77 static void set_multicast_list(struct net_device *ndev); 78 static void fec_enet_itr_coal_set(struct net_device *ndev); 79 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 80 int cpu, struct xdp_buff *xdp, 81 u32 dma_sync_len); 82 83 #define DRIVER_NAME "fec" 84 85 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 86 87 #define FEC_ENET_RSEM_V 0x84 88 #define FEC_ENET_RSFL_V 16 89 #define FEC_ENET_RAEM_V 0x8 90 #define FEC_ENET_RAFL_V 0x8 91 #define FEC_ENET_OPD_V 0xFFF0 92 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 93 94 #define FEC_ENET_XDP_PASS 0 95 #define FEC_ENET_XDP_CONSUMED BIT(0) 96 #define FEC_ENET_XDP_TX BIT(1) 97 #define FEC_ENET_XDP_REDIR BIT(2) 98 99 struct fec_devinfo { 100 u32 quirks; 101 }; 102 103 static const struct fec_devinfo fec_imx25_info = { 104 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 105 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_HAS_MDIO_C45, 106 }; 107 108 static const struct fec_devinfo fec_imx27_info = { 109 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG | 110 FEC_QUIRK_HAS_MDIO_C45, 111 }; 112 113 static const struct fec_devinfo fec_imx28_info = { 114 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 115 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 116 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 117 FEC_QUIRK_NO_HARD_RESET | FEC_QUIRK_HAS_MDIO_C45, 118 }; 119 120 static const struct fec_devinfo fec_imx6q_info = { 121 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 122 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 123 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 124 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII | 125 FEC_QUIRK_HAS_PMQOS | FEC_QUIRK_HAS_MDIO_C45, 126 }; 127 128 static const struct fec_devinfo fec_mvf600_info = { 129 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC | 130 FEC_QUIRK_HAS_MDIO_C45, 131 }; 132 133 static const struct fec_devinfo fec_imx6sx_info = { 134 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 135 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 136 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 137 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 138 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 139 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 140 FEC_QUIRK_HAS_MDIO_C45, 141 }; 142 143 static const struct fec_devinfo fec_imx6ul_info = { 144 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 145 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 146 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 147 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 148 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII | 149 FEC_QUIRK_HAS_MDIO_C45, 150 }; 151 152 static const struct fec_devinfo fec_imx8mq_info = { 153 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 154 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 155 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 156 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 157 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 158 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 159 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2 | 160 FEC_QUIRK_HAS_MDIO_C45, 161 }; 162 163 static const struct fec_devinfo fec_imx8qm_info = { 164 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 165 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 166 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 167 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 168 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 169 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 170 FEC_QUIRK_DELAYED_CLKS_SUPPORT | FEC_QUIRK_HAS_MDIO_C45 | 171 FEC_QUIRK_JUMBO_FRAME, 172 }; 173 174 static const struct fec_devinfo fec_s32v234_info = { 175 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 176 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 177 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 178 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 179 FEC_QUIRK_HAS_MDIO_C45, 180 }; 181 182 static struct platform_device_id fec_devtype[] = { 183 { 184 /* keep it for coldfire */ 185 .name = DRIVER_NAME, 186 .driver_data = 0, 187 }, { 188 /* sentinel */ 189 } 190 }; 191 MODULE_DEVICE_TABLE(platform, fec_devtype); 192 193 static const struct of_device_id fec_dt_ids[] = { 194 { .compatible = "fsl,imx25-fec", .data = &fec_imx25_info, }, 195 { .compatible = "fsl,imx27-fec", .data = &fec_imx27_info, }, 196 { .compatible = "fsl,imx28-fec", .data = &fec_imx28_info, }, 197 { .compatible = "fsl,imx6q-fec", .data = &fec_imx6q_info, }, 198 { .compatible = "fsl,mvf600-fec", .data = &fec_mvf600_info, }, 199 { .compatible = "fsl,imx6sx-fec", .data = &fec_imx6sx_info, }, 200 { .compatible = "fsl,imx6ul-fec", .data = &fec_imx6ul_info, }, 201 { .compatible = "fsl,imx8mq-fec", .data = &fec_imx8mq_info, }, 202 { .compatible = "fsl,imx8qm-fec", .data = &fec_imx8qm_info, }, 203 { .compatible = "fsl,s32v234-fec", .data = &fec_s32v234_info, }, 204 { /* sentinel */ } 205 }; 206 MODULE_DEVICE_TABLE(of, fec_dt_ids); 207 208 static unsigned char macaddr[ETH_ALEN]; 209 module_param_array(macaddr, byte, NULL, 0); 210 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 211 212 #if defined(CONFIG_M5272) 213 /* 214 * Some hardware gets it MAC address out of local flash memory. 215 * if this is non-zero then assume it is the address to get MAC from. 216 */ 217 #if defined(CONFIG_NETtel) 218 #define FEC_FLASHMAC 0xf0006006 219 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 220 #define FEC_FLASHMAC 0xf0006000 221 #elif defined(CONFIG_CANCam) 222 #define FEC_FLASHMAC 0xf0020000 223 #elif defined (CONFIG_M5272C3) 224 #define FEC_FLASHMAC (0xffe04000 + 4) 225 #elif defined(CONFIG_MOD5272) 226 #define FEC_FLASHMAC 0xffc0406b 227 #else 228 #define FEC_FLASHMAC 0 229 #endif 230 #endif /* CONFIG_M5272 */ 231 232 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 233 * 234 * 2048 byte skbufs are allocated. However, alignment requirements 235 * varies between FEC variants. Worst case is 64, so round down by 64. 236 */ 237 #define MAX_JUMBO_BUF_SIZE (round_down(16384 - FEC_DRV_RESERVE_SPACE - 64, 64)) 238 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 239 #define PKT_MINBUF_SIZE 64 240 241 /* FEC receive acceleration */ 242 #define FEC_RACC_IPDIS BIT(1) 243 #define FEC_RACC_PRODIS BIT(2) 244 #define FEC_RACC_SHIFT16 BIT(7) 245 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 246 247 /* MIB Control Register */ 248 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 249 250 /* 251 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 252 * size bits. Other FEC hardware does not, so we need to take that into 253 * account when setting it. 254 */ 255 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 256 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 257 defined(CONFIG_ARM64) 258 #define OPT_ARCH_HAS_MAX_FL 1 259 #else 260 #define OPT_ARCH_HAS_MAX_FL 0 261 #endif 262 263 /* FEC MII MMFR bits definition */ 264 #define FEC_MMFR_ST (1 << 30) 265 #define FEC_MMFR_ST_C45 (0) 266 #define FEC_MMFR_OP_READ (2 << 28) 267 #define FEC_MMFR_OP_READ_C45 (3 << 28) 268 #define FEC_MMFR_OP_WRITE (1 << 28) 269 #define FEC_MMFR_OP_ADDR_WRITE (0) 270 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 271 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 272 #define FEC_MMFR_TA (2 << 16) 273 #define FEC_MMFR_DATA(v) (v & 0xffff) 274 /* FEC ECR bits definition */ 275 #define FEC_ECR_RESET BIT(0) 276 #define FEC_ECR_ETHEREN BIT(1) 277 #define FEC_ECR_MAGICEN BIT(2) 278 #define FEC_ECR_SLEEP BIT(3) 279 #define FEC_ECR_EN1588 BIT(4) 280 #define FEC_ECR_SPEED BIT(5) 281 #define FEC_ECR_BYTESWP BIT(8) 282 /* FEC RCR bits definition */ 283 #define FEC_RCR_LOOP BIT(0) 284 #define FEC_RCR_DRT BIT(1) 285 #define FEC_RCR_MII BIT(2) 286 #define FEC_RCR_PROMISC BIT(3) 287 #define FEC_RCR_BC_REJ BIT(4) 288 #define FEC_RCR_FLOWCTL BIT(5) 289 #define FEC_RCR_RGMII BIT(6) 290 #define FEC_RCR_RMII BIT(8) 291 #define FEC_RCR_10BASET BIT(9) 292 #define FEC_RCR_NLC BIT(30) 293 /* TX WMARK bits */ 294 #define FEC_TXWMRK_STRFWD BIT(8) 295 296 #define FEC_MII_TIMEOUT 30000 /* us */ 297 298 /* Transmitter timeout */ 299 #define TX_TIMEOUT (2 * HZ) 300 301 #define FEC_PAUSE_FLAG_AUTONEG 0x1 302 #define FEC_PAUSE_FLAG_ENABLE 0x2 303 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 304 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 305 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 306 307 /* Max number of allowed TCP segments for software TSO */ 308 #define FEC_MAX_TSO_SEGS 100 309 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 310 311 #define IS_TSO_HEADER(txq, addr) \ 312 ((addr >= txq->tso_hdrs_dma) && \ 313 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 314 315 static int mii_cnt; 316 317 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 318 struct bufdesc_prop *bd) 319 { 320 return (bdp >= bd->last) ? bd->base 321 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 322 } 323 324 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 325 struct bufdesc_prop *bd) 326 { 327 return (bdp <= bd->base) ? bd->last 328 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 329 } 330 331 static int fec_enet_get_bd_index(struct bufdesc *bdp, 332 struct bufdesc_prop *bd) 333 { 334 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 335 } 336 337 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 338 { 339 int entries; 340 341 entries = (((const char *)txq->dirty_tx - 342 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 343 344 return entries >= 0 ? entries : entries + txq->bd.ring_size; 345 } 346 347 static void swap_buffer(void *bufaddr, int len) 348 { 349 int i; 350 unsigned int *buf = bufaddr; 351 352 for (i = 0; i < len; i += 4, buf++) 353 swab32s(buf); 354 } 355 356 static void fec_dump(struct net_device *ndev) 357 { 358 struct fec_enet_private *fep = netdev_priv(ndev); 359 struct bufdesc *bdp; 360 struct fec_enet_priv_tx_q *txq; 361 int index = 0; 362 363 netdev_info(ndev, "TX ring dump\n"); 364 pr_info("Nr SC addr len SKB\n"); 365 366 txq = fep->tx_queue[0]; 367 bdp = txq->bd.base; 368 369 do { 370 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 371 index, 372 bdp == txq->bd.cur ? 'S' : ' ', 373 bdp == txq->dirty_tx ? 'H' : ' ', 374 fec16_to_cpu(bdp->cbd_sc), 375 fec32_to_cpu(bdp->cbd_bufaddr), 376 fec16_to_cpu(bdp->cbd_datlen), 377 txq->tx_buf[index].buf_p); 378 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 379 index++; 380 } while (bdp != txq->bd.base); 381 } 382 383 /* 384 * Coldfire does not support DMA coherent allocations, and has historically used 385 * a band-aid with a manual flush in fec_enet_rx_queue. 386 */ 387 #if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA) 388 static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, 389 gfp_t gfp) 390 { 391 return dma_alloc_noncoherent(dev, size, handle, DMA_BIDIRECTIONAL, gfp); 392 } 393 394 static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr, 395 dma_addr_t handle) 396 { 397 dma_free_noncoherent(dev, size, cpu_addr, handle, DMA_BIDIRECTIONAL); 398 } 399 #else /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */ 400 static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, 401 gfp_t gfp) 402 { 403 return dma_alloc_coherent(dev, size, handle, gfp); 404 } 405 406 static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr, 407 dma_addr_t handle) 408 { 409 dma_free_coherent(dev, size, cpu_addr, handle); 410 } 411 #endif /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */ 412 413 struct fec_dma_devres { 414 size_t size; 415 void *vaddr; 416 dma_addr_t dma_handle; 417 }; 418 419 static void fec_dmam_release(struct device *dev, void *res) 420 { 421 struct fec_dma_devres *this = res; 422 423 fec_dma_free(dev, this->size, this->vaddr, this->dma_handle); 424 } 425 426 static void *fec_dmam_alloc(struct device *dev, size_t size, dma_addr_t *handle, 427 gfp_t gfp) 428 { 429 struct fec_dma_devres *dr; 430 void *vaddr; 431 432 dr = devres_alloc(fec_dmam_release, sizeof(*dr), gfp); 433 if (!dr) 434 return NULL; 435 vaddr = fec_dma_alloc(dev, size, handle, gfp); 436 if (!vaddr) { 437 devres_free(dr); 438 return NULL; 439 } 440 dr->vaddr = vaddr; 441 dr->dma_handle = *handle; 442 dr->size = size; 443 devres_add(dev, dr); 444 return vaddr; 445 } 446 447 static inline bool is_ipv4_pkt(struct sk_buff *skb) 448 { 449 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 450 } 451 452 static int 453 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 454 { 455 /* Only run for packets requiring a checksum. */ 456 if (skb->ip_summed != CHECKSUM_PARTIAL) 457 return 0; 458 459 if (unlikely(skb_cow_head(skb, 0))) 460 return -1; 461 462 if (is_ipv4_pkt(skb)) 463 ip_hdr(skb)->check = 0; 464 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 465 466 return 0; 467 } 468 469 static int 470 fec_enet_create_page_pool(struct fec_enet_private *fep, 471 struct fec_enet_priv_rx_q *rxq, int size) 472 { 473 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 474 struct page_pool_params pp_params = { 475 .order = fep->pagepool_order, 476 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 477 .pool_size = size, 478 .nid = dev_to_node(&fep->pdev->dev), 479 .dev = &fep->pdev->dev, 480 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 481 .offset = FEC_ENET_XDP_HEADROOM, 482 .max_len = fep->rx_frame_size, 483 }; 484 int err; 485 486 rxq->page_pool = page_pool_create(&pp_params); 487 if (IS_ERR(rxq->page_pool)) { 488 err = PTR_ERR(rxq->page_pool); 489 rxq->page_pool = NULL; 490 return err; 491 } 492 493 err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0); 494 if (err < 0) 495 goto err_free_pp; 496 497 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 498 rxq->page_pool); 499 if (err) 500 goto err_unregister_rxq; 501 502 return 0; 503 504 err_unregister_rxq: 505 xdp_rxq_info_unreg(&rxq->xdp_rxq); 506 err_free_pp: 507 page_pool_destroy(rxq->page_pool); 508 rxq->page_pool = NULL; 509 return err; 510 } 511 512 static struct bufdesc * 513 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 514 struct sk_buff *skb, 515 struct net_device *ndev) 516 { 517 struct fec_enet_private *fep = netdev_priv(ndev); 518 struct bufdesc *bdp = txq->bd.cur; 519 struct bufdesc_ex *ebdp; 520 int nr_frags = skb_shinfo(skb)->nr_frags; 521 int frag, frag_len; 522 unsigned short status; 523 unsigned int estatus = 0; 524 skb_frag_t *this_frag; 525 unsigned int index; 526 void *bufaddr; 527 dma_addr_t addr; 528 int i; 529 530 for (frag = 0; frag < nr_frags; frag++) { 531 this_frag = &skb_shinfo(skb)->frags[frag]; 532 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 533 ebdp = (struct bufdesc_ex *)bdp; 534 535 status = fec16_to_cpu(bdp->cbd_sc); 536 status &= ~BD_ENET_TX_STATS; 537 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 538 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 539 540 /* Handle the last BD specially */ 541 if (frag == nr_frags - 1) { 542 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 543 if (fep->bufdesc_ex) { 544 estatus |= BD_ENET_TX_INT; 545 if (unlikely(skb_shinfo(skb)->tx_flags & 546 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 547 estatus |= BD_ENET_TX_TS; 548 } 549 } 550 551 if (fep->bufdesc_ex) { 552 if (fep->quirks & FEC_QUIRK_HAS_AVB) 553 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 554 if (skb->ip_summed == CHECKSUM_PARTIAL) 555 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 556 557 ebdp->cbd_bdu = 0; 558 ebdp->cbd_esc = cpu_to_fec32(estatus); 559 } 560 561 bufaddr = skb_frag_address(this_frag); 562 563 index = fec_enet_get_bd_index(bdp, &txq->bd); 564 if (((unsigned long) bufaddr) & fep->tx_align || 565 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 566 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 567 bufaddr = txq->tx_bounce[index]; 568 569 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 570 swap_buffer(bufaddr, frag_len); 571 } 572 573 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 574 DMA_TO_DEVICE); 575 if (dma_mapping_error(&fep->pdev->dev, addr)) { 576 if (net_ratelimit()) 577 netdev_err(ndev, "Tx DMA memory map failed\n"); 578 goto dma_mapping_error; 579 } 580 581 bdp->cbd_bufaddr = cpu_to_fec32(addr); 582 bdp->cbd_datlen = cpu_to_fec16(frag_len); 583 /* Make sure the updates to rest of the descriptor are 584 * performed before transferring ownership. 585 */ 586 wmb(); 587 bdp->cbd_sc = cpu_to_fec16(status); 588 } 589 590 return bdp; 591 dma_mapping_error: 592 bdp = txq->bd.cur; 593 for (i = 0; i < frag; i++) { 594 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 595 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 596 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 597 } 598 return ERR_PTR(-ENOMEM); 599 } 600 601 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 602 struct sk_buff *skb, struct net_device *ndev) 603 { 604 struct fec_enet_private *fep = netdev_priv(ndev); 605 int nr_frags = skb_shinfo(skb)->nr_frags; 606 struct bufdesc *bdp, *last_bdp; 607 void *bufaddr; 608 dma_addr_t addr; 609 unsigned short status; 610 unsigned short buflen; 611 unsigned int estatus = 0; 612 unsigned int index; 613 int entries_free; 614 615 entries_free = fec_enet_get_free_txdesc_num(txq); 616 if (entries_free < MAX_SKB_FRAGS + 1) { 617 dev_kfree_skb_any(skb); 618 if (net_ratelimit()) 619 netdev_err(ndev, "NOT enough BD for SG!\n"); 620 return NETDEV_TX_OK; 621 } 622 623 /* Protocol checksum off-load for TCP and UDP. */ 624 if (fec_enet_clear_csum(skb, ndev)) { 625 dev_kfree_skb_any(skb); 626 return NETDEV_TX_OK; 627 } 628 629 /* Fill in a Tx ring entry */ 630 bdp = txq->bd.cur; 631 last_bdp = bdp; 632 status = fec16_to_cpu(bdp->cbd_sc); 633 status &= ~BD_ENET_TX_STATS; 634 635 /* Set buffer length and buffer pointer */ 636 bufaddr = skb->data; 637 buflen = skb_headlen(skb); 638 639 index = fec_enet_get_bd_index(bdp, &txq->bd); 640 if (((unsigned long) bufaddr) & fep->tx_align || 641 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 642 memcpy(txq->tx_bounce[index], skb->data, buflen); 643 bufaddr = txq->tx_bounce[index]; 644 645 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 646 swap_buffer(bufaddr, buflen); 647 } 648 649 /* Push the data cache so the CPM does not get stale memory data. */ 650 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 651 if (dma_mapping_error(&fep->pdev->dev, addr)) { 652 dev_kfree_skb_any(skb); 653 if (net_ratelimit()) 654 netdev_err(ndev, "Tx DMA memory map failed\n"); 655 return NETDEV_TX_OK; 656 } 657 658 if (nr_frags) { 659 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 660 if (IS_ERR(last_bdp)) { 661 dma_unmap_single(&fep->pdev->dev, addr, 662 buflen, DMA_TO_DEVICE); 663 dev_kfree_skb_any(skb); 664 return NETDEV_TX_OK; 665 } 666 } else { 667 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 668 if (fep->bufdesc_ex) { 669 estatus = BD_ENET_TX_INT; 670 if (unlikely(skb_shinfo(skb)->tx_flags & 671 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 672 estatus |= BD_ENET_TX_TS; 673 } 674 } 675 bdp->cbd_bufaddr = cpu_to_fec32(addr); 676 bdp->cbd_datlen = cpu_to_fec16(buflen); 677 678 if (fep->bufdesc_ex) { 679 680 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 681 682 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 683 fep->hwts_tx_en)) 684 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 685 686 if (fep->quirks & FEC_QUIRK_HAS_AVB) 687 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 688 689 if (skb->ip_summed == CHECKSUM_PARTIAL) 690 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 691 692 ebdp->cbd_bdu = 0; 693 ebdp->cbd_esc = cpu_to_fec32(estatus); 694 } 695 696 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 697 /* Save skb pointer */ 698 txq->tx_buf[index].buf_p = skb; 699 700 /* Make sure the updates to rest of the descriptor are performed before 701 * transferring ownership. 702 */ 703 wmb(); 704 705 /* Send it on its way. Tell FEC it's ready, interrupt when done, 706 * it's the last BD of the frame, and to put the CRC on the end. 707 */ 708 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 709 bdp->cbd_sc = cpu_to_fec16(status); 710 711 /* If this was the last BD in the ring, start at the beginning again. */ 712 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 713 714 skb_tx_timestamp(skb); 715 716 /* Make sure the update to bdp is performed before txq->bd.cur. */ 717 wmb(); 718 txq->bd.cur = bdp; 719 720 /* Trigger transmission start */ 721 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 722 !readl(txq->bd.reg_desc_active) || 723 !readl(txq->bd.reg_desc_active) || 724 !readl(txq->bd.reg_desc_active) || 725 !readl(txq->bd.reg_desc_active)) 726 writel(0, txq->bd.reg_desc_active); 727 728 return 0; 729 } 730 731 static int 732 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 733 struct net_device *ndev, 734 struct bufdesc *bdp, int index, char *data, 735 int size, bool last_tcp, bool is_last) 736 { 737 struct fec_enet_private *fep = netdev_priv(ndev); 738 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 739 unsigned short status; 740 unsigned int estatus = 0; 741 dma_addr_t addr; 742 743 status = fec16_to_cpu(bdp->cbd_sc); 744 status &= ~BD_ENET_TX_STATS; 745 746 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 747 748 if (((unsigned long) data) & fep->tx_align || 749 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 750 memcpy(txq->tx_bounce[index], data, size); 751 data = txq->tx_bounce[index]; 752 753 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 754 swap_buffer(data, size); 755 } 756 757 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 758 if (dma_mapping_error(&fep->pdev->dev, addr)) { 759 dev_kfree_skb_any(skb); 760 if (net_ratelimit()) 761 netdev_err(ndev, "Tx DMA memory map failed\n"); 762 return NETDEV_TX_OK; 763 } 764 765 bdp->cbd_datlen = cpu_to_fec16(size); 766 bdp->cbd_bufaddr = cpu_to_fec32(addr); 767 768 if (fep->bufdesc_ex) { 769 if (fep->quirks & FEC_QUIRK_HAS_AVB) 770 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 771 if (skb->ip_summed == CHECKSUM_PARTIAL) 772 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 773 ebdp->cbd_bdu = 0; 774 ebdp->cbd_esc = cpu_to_fec32(estatus); 775 } 776 777 /* Handle the last BD specially */ 778 if (last_tcp) 779 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 780 if (is_last) { 781 status |= BD_ENET_TX_INTR; 782 if (fep->bufdesc_ex) 783 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 784 } 785 786 bdp->cbd_sc = cpu_to_fec16(status); 787 788 return 0; 789 } 790 791 static int 792 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 793 struct sk_buff *skb, struct net_device *ndev, 794 struct bufdesc *bdp, int index) 795 { 796 struct fec_enet_private *fep = netdev_priv(ndev); 797 int hdr_len = skb_tcp_all_headers(skb); 798 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 799 void *bufaddr; 800 unsigned long dmabuf; 801 unsigned short status; 802 unsigned int estatus = 0; 803 804 status = fec16_to_cpu(bdp->cbd_sc); 805 status &= ~BD_ENET_TX_STATS; 806 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 807 808 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 809 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 810 if (((unsigned long)bufaddr) & fep->tx_align || 811 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 812 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 813 bufaddr = txq->tx_bounce[index]; 814 815 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 816 swap_buffer(bufaddr, hdr_len); 817 818 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 819 hdr_len, DMA_TO_DEVICE); 820 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 821 dev_kfree_skb_any(skb); 822 if (net_ratelimit()) 823 netdev_err(ndev, "Tx DMA memory map failed\n"); 824 return NETDEV_TX_OK; 825 } 826 } 827 828 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 829 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 830 831 if (fep->bufdesc_ex) { 832 if (fep->quirks & FEC_QUIRK_HAS_AVB) 833 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 834 if (skb->ip_summed == CHECKSUM_PARTIAL) 835 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 836 ebdp->cbd_bdu = 0; 837 ebdp->cbd_esc = cpu_to_fec32(estatus); 838 } 839 840 bdp->cbd_sc = cpu_to_fec16(status); 841 842 return 0; 843 } 844 845 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 846 struct sk_buff *skb, 847 struct net_device *ndev) 848 { 849 struct fec_enet_private *fep = netdev_priv(ndev); 850 int hdr_len, total_len, data_left; 851 struct bufdesc *bdp = txq->bd.cur; 852 struct bufdesc *tmp_bdp; 853 struct bufdesc_ex *ebdp; 854 struct tso_t tso; 855 unsigned int index = 0; 856 int ret; 857 858 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 859 dev_kfree_skb_any(skb); 860 if (net_ratelimit()) 861 netdev_err(ndev, "NOT enough BD for TSO!\n"); 862 return NETDEV_TX_OK; 863 } 864 865 /* Protocol checksum off-load for TCP and UDP. */ 866 if (fec_enet_clear_csum(skb, ndev)) { 867 dev_kfree_skb_any(skb); 868 return NETDEV_TX_OK; 869 } 870 871 /* Initialize the TSO handler, and prepare the first payload */ 872 hdr_len = tso_start(skb, &tso); 873 874 total_len = skb->len - hdr_len; 875 while (total_len > 0) { 876 char *hdr; 877 878 index = fec_enet_get_bd_index(bdp, &txq->bd); 879 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 880 total_len -= data_left; 881 882 /* prepare packet headers: MAC + IP + TCP */ 883 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 884 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 885 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 886 if (ret) 887 goto err_release; 888 889 while (data_left > 0) { 890 int size; 891 892 size = min_t(int, tso.size, data_left); 893 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 894 index = fec_enet_get_bd_index(bdp, &txq->bd); 895 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 896 bdp, index, 897 tso.data, size, 898 size == data_left, 899 total_len == 0); 900 if (ret) 901 goto err_release; 902 903 data_left -= size; 904 tso_build_data(skb, &tso, size); 905 } 906 907 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 908 } 909 910 /* Save skb pointer */ 911 txq->tx_buf[index].buf_p = skb; 912 913 skb_tx_timestamp(skb); 914 txq->bd.cur = bdp; 915 916 /* Trigger transmission start */ 917 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 918 !readl(txq->bd.reg_desc_active) || 919 !readl(txq->bd.reg_desc_active) || 920 !readl(txq->bd.reg_desc_active) || 921 !readl(txq->bd.reg_desc_active)) 922 writel(0, txq->bd.reg_desc_active); 923 924 return 0; 925 926 err_release: 927 /* Release all used data descriptors for TSO */ 928 tmp_bdp = txq->bd.cur; 929 930 while (tmp_bdp != bdp) { 931 /* Unmap data buffers */ 932 if (tmp_bdp->cbd_bufaddr && 933 !IS_TSO_HEADER(txq, fec32_to_cpu(tmp_bdp->cbd_bufaddr))) 934 dma_unmap_single(&fep->pdev->dev, 935 fec32_to_cpu(tmp_bdp->cbd_bufaddr), 936 fec16_to_cpu(tmp_bdp->cbd_datlen), 937 DMA_TO_DEVICE); 938 939 /* Clear standard buffer descriptor fields */ 940 tmp_bdp->cbd_sc = 0; 941 tmp_bdp->cbd_datlen = 0; 942 tmp_bdp->cbd_bufaddr = 0; 943 944 /* Handle extended descriptor if enabled */ 945 if (fep->bufdesc_ex) { 946 ebdp = (struct bufdesc_ex *)tmp_bdp; 947 ebdp->cbd_esc = 0; 948 } 949 950 tmp_bdp = fec_enet_get_nextdesc(tmp_bdp, &txq->bd); 951 } 952 953 dev_kfree_skb_any(skb); 954 955 return ret; 956 } 957 958 static netdev_tx_t 959 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 960 { 961 struct fec_enet_private *fep = netdev_priv(ndev); 962 int entries_free; 963 unsigned short queue; 964 struct fec_enet_priv_tx_q *txq; 965 struct netdev_queue *nq; 966 int ret; 967 968 queue = skb_get_queue_mapping(skb); 969 txq = fep->tx_queue[queue]; 970 nq = netdev_get_tx_queue(ndev, queue); 971 972 if (skb_is_gso(skb)) 973 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 974 else 975 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 976 if (ret) 977 return ret; 978 979 entries_free = fec_enet_get_free_txdesc_num(txq); 980 if (entries_free <= txq->tx_stop_threshold) 981 netif_tx_stop_queue(nq); 982 983 return NETDEV_TX_OK; 984 } 985 986 /* Init RX & TX buffer descriptors 987 */ 988 static void fec_enet_bd_init(struct net_device *dev) 989 { 990 struct fec_enet_private *fep = netdev_priv(dev); 991 struct fec_enet_priv_tx_q *txq; 992 struct fec_enet_priv_rx_q *rxq; 993 struct bufdesc *bdp; 994 unsigned int i; 995 unsigned int q; 996 997 for (q = 0; q < fep->num_rx_queues; q++) { 998 /* Initialize the receive buffer descriptors. */ 999 rxq = fep->rx_queue[q]; 1000 bdp = rxq->bd.base; 1001 1002 for (i = 0; i < rxq->bd.ring_size; i++) { 1003 1004 /* Initialize the BD for every fragment in the page. */ 1005 if (bdp->cbd_bufaddr) 1006 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 1007 else 1008 bdp->cbd_sc = cpu_to_fec16(0); 1009 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1010 } 1011 1012 /* Set the last buffer to wrap */ 1013 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 1014 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 1015 1016 rxq->bd.cur = rxq->bd.base; 1017 } 1018 1019 for (q = 0; q < fep->num_tx_queues; q++) { 1020 /* ...and the same for transmit */ 1021 txq = fep->tx_queue[q]; 1022 bdp = txq->bd.base; 1023 txq->bd.cur = bdp; 1024 1025 for (i = 0; i < txq->bd.ring_size; i++) { 1026 /* Initialize the BD for every fragment in the page. */ 1027 bdp->cbd_sc = cpu_to_fec16(0); 1028 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 1029 if (bdp->cbd_bufaddr && 1030 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1031 dma_unmap_single(&fep->pdev->dev, 1032 fec32_to_cpu(bdp->cbd_bufaddr), 1033 fec16_to_cpu(bdp->cbd_datlen), 1034 DMA_TO_DEVICE); 1035 if (txq->tx_buf[i].buf_p) 1036 dev_kfree_skb_any(txq->tx_buf[i].buf_p); 1037 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 1038 if (bdp->cbd_bufaddr) 1039 dma_unmap_single(&fep->pdev->dev, 1040 fec32_to_cpu(bdp->cbd_bufaddr), 1041 fec16_to_cpu(bdp->cbd_datlen), 1042 DMA_TO_DEVICE); 1043 1044 if (txq->tx_buf[i].buf_p) 1045 xdp_return_frame(txq->tx_buf[i].buf_p); 1046 } else { 1047 struct page *page = txq->tx_buf[i].buf_p; 1048 1049 if (page) 1050 page_pool_put_page(pp_page_to_nmdesc(page)->pp, 1051 page, 0, 1052 false); 1053 } 1054 1055 txq->tx_buf[i].buf_p = NULL; 1056 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1057 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 1058 bdp->cbd_bufaddr = cpu_to_fec32(0); 1059 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1060 } 1061 1062 /* Set the last buffer to wrap */ 1063 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 1064 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 1065 txq->dirty_tx = bdp; 1066 } 1067 } 1068 1069 static void fec_enet_active_rxring(struct net_device *ndev) 1070 { 1071 struct fec_enet_private *fep = netdev_priv(ndev); 1072 int i; 1073 1074 for (i = 0; i < fep->num_rx_queues; i++) 1075 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 1076 } 1077 1078 static void fec_enet_enable_ring(struct net_device *ndev) 1079 { 1080 struct fec_enet_private *fep = netdev_priv(ndev); 1081 struct fec_enet_priv_tx_q *txq; 1082 struct fec_enet_priv_rx_q *rxq; 1083 int i; 1084 1085 for (i = 0; i < fep->num_rx_queues; i++) { 1086 rxq = fep->rx_queue[i]; 1087 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 1088 writel(fep->max_buf_size, fep->hwp + FEC_R_BUFF_SIZE(i)); 1089 1090 /* enable DMA1/2 */ 1091 if (i) 1092 writel(RCMR_MATCHEN | RCMR_CMP(i), 1093 fep->hwp + FEC_RCMR(i)); 1094 } 1095 1096 for (i = 0; i < fep->num_tx_queues; i++) { 1097 txq = fep->tx_queue[i]; 1098 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 1099 1100 /* enable DMA1/2 */ 1101 if (i) 1102 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 1103 fep->hwp + FEC_DMA_CFG(i)); 1104 } 1105 } 1106 1107 /* Whack a reset. We should wait for this. 1108 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1109 * instead of reset MAC itself. 1110 */ 1111 static void fec_ctrl_reset(struct fec_enet_private *fep, bool allow_wol) 1112 { 1113 u32 val; 1114 1115 if (!allow_wol || !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1116 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || 1117 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 1118 writel(0, fep->hwp + FEC_ECNTRL); 1119 } else { 1120 writel(FEC_ECR_RESET, fep->hwp + FEC_ECNTRL); 1121 udelay(10); 1122 } 1123 } else { 1124 val = readl(fep->hwp + FEC_ECNTRL); 1125 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1126 writel(val, fep->hwp + FEC_ECNTRL); 1127 } 1128 } 1129 1130 static void fec_set_hw_mac_addr(struct net_device *ndev) 1131 { 1132 struct fec_enet_private *fep = netdev_priv(ndev); 1133 1134 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 1135 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 1136 fep->hwp + FEC_ADDR_LOW); 1137 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 1138 fep->hwp + FEC_ADDR_HIGH); 1139 } 1140 1141 /* 1142 * This function is called to start or restart the FEC during a link 1143 * change, transmit timeout, or to reconfigure the FEC. The network 1144 * packet processing for this device must be stopped before this call. 1145 */ 1146 static void 1147 fec_restart(struct net_device *ndev) 1148 { 1149 struct fec_enet_private *fep = netdev_priv(ndev); 1150 u32 ecntl = FEC_ECR_ETHEREN; 1151 u32 rcntl = FEC_RCR_MII; 1152 1153 if (OPT_ARCH_HAS_MAX_FL) 1154 rcntl |= (fep->netdev->mtu + ETH_HLEN + ETH_FCS_LEN) << 16; 1155 1156 if (fep->bufdesc_ex) 1157 fec_ptp_save_state(fep); 1158 1159 fec_ctrl_reset(fep, false); 1160 1161 /* 1162 * enet-mac reset will reset mac address registers too, 1163 * so need to reconfigure it. 1164 */ 1165 fec_set_hw_mac_addr(ndev); 1166 1167 /* Clear any outstanding interrupt, except MDIO. */ 1168 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 1169 1170 fec_enet_bd_init(ndev); 1171 1172 fec_enet_enable_ring(ndev); 1173 1174 /* Enable MII mode */ 1175 if (fep->full_duplex == DUPLEX_FULL) { 1176 /* FD enable */ 1177 writel(0x04, fep->hwp + FEC_X_CNTRL); 1178 } else { 1179 /* No Rcv on Xmit */ 1180 rcntl |= FEC_RCR_DRT; 1181 writel(0x0, fep->hwp + FEC_X_CNTRL); 1182 } 1183 1184 /* Set MII speed */ 1185 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1186 1187 #if !defined(CONFIG_M5272) 1188 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1189 u32 val = readl(fep->hwp + FEC_RACC); 1190 1191 /* align IP header */ 1192 val |= FEC_RACC_SHIFT16; 1193 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1194 /* set RX checksum */ 1195 val |= FEC_RACC_OPTIONS; 1196 else 1197 val &= ~FEC_RACC_OPTIONS; 1198 writel(val, fep->hwp + FEC_RACC); 1199 writel(min(fep->rx_frame_size, fep->max_buf_size), fep->hwp + FEC_FTRL); 1200 } 1201 #endif 1202 1203 /* 1204 * The phy interface and speed need to get configured 1205 * differently on enet-mac. 1206 */ 1207 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1208 /* Enable flow control and length check */ 1209 rcntl |= FEC_RCR_NLC | FEC_RCR_FLOWCTL; 1210 1211 /* RGMII, RMII or MII */ 1212 if (phy_interface_mode_is_rgmii(fep->phy_interface)) 1213 rcntl |= FEC_RCR_RGMII; 1214 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1215 rcntl |= FEC_RCR_RMII; 1216 else 1217 rcntl &= ~FEC_RCR_RMII; 1218 1219 /* 1G, 100M or 10M */ 1220 if (ndev->phydev) { 1221 if (ndev->phydev->speed == SPEED_1000) 1222 ecntl |= FEC_ECR_SPEED; 1223 else if (ndev->phydev->speed == SPEED_100) 1224 rcntl &= ~FEC_RCR_10BASET; 1225 else 1226 rcntl |= FEC_RCR_10BASET; 1227 } 1228 } else { 1229 #ifdef FEC_MIIGSK_ENR 1230 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1231 u32 cfgr; 1232 /* disable the gasket and wait */ 1233 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1234 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1235 udelay(1); 1236 1237 /* 1238 * configure the gasket: 1239 * RMII, 50 MHz, no loopback, no echo 1240 * MII, 25 MHz, no loopback, no echo 1241 */ 1242 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1243 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1244 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1245 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1246 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1247 1248 /* re-enable the gasket */ 1249 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1250 } 1251 #endif 1252 } 1253 1254 #if !defined(CONFIG_M5272) 1255 /* enable pause frame*/ 1256 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1257 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1258 ndev->phydev && ndev->phydev->pause)) { 1259 rcntl |= FEC_RCR_FLOWCTL; 1260 1261 /* set FIFO threshold parameter to reduce overrun */ 1262 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1263 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1264 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1265 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1266 1267 /* OPD */ 1268 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1269 } else { 1270 rcntl &= ~FEC_RCR_FLOWCTL; 1271 } 1272 #endif /* !defined(CONFIG_M5272) */ 1273 1274 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1275 1276 /* Setup multicast filter. */ 1277 set_multicast_list(ndev); 1278 #ifndef CONFIG_M5272 1279 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1280 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1281 #endif 1282 1283 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1284 /* enable ENET endian swap */ 1285 ecntl |= FEC_ECR_BYTESWP; 1286 1287 /* When Jumbo Frame is enabled, the FIFO may not be large enough 1288 * to hold an entire frame. In such cases, if the MTU exceeds 1289 * (PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN), configure the interface 1290 * to operate in cut-through mode, triggered by the FIFO threshold. 1291 * Otherwise, enable the ENET store-and-forward mode. 1292 */ 1293 if ((fep->quirks & FEC_QUIRK_JUMBO_FRAME) && 1294 (ndev->mtu > (PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN))) 1295 writel(0xF, fep->hwp + FEC_X_WMRK); 1296 else 1297 writel(FEC_TXWMRK_STRFWD, fep->hwp + FEC_X_WMRK); 1298 } 1299 1300 if (fep->bufdesc_ex) 1301 ecntl |= FEC_ECR_EN1588; 1302 1303 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1304 fep->rgmii_txc_dly) 1305 ecntl |= FEC_ENET_TXC_DLY; 1306 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1307 fep->rgmii_rxc_dly) 1308 ecntl |= FEC_ENET_RXC_DLY; 1309 1310 #ifndef CONFIG_M5272 1311 /* Enable the MIB statistic event counters */ 1312 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1313 #endif 1314 1315 /* And last, enable the transmit and receive processing */ 1316 writel(ecntl, fep->hwp + FEC_ECNTRL); 1317 fec_enet_active_rxring(ndev); 1318 1319 if (fep->bufdesc_ex) { 1320 fec_ptp_start_cyclecounter(ndev); 1321 fec_ptp_restore_state(fep); 1322 } 1323 1324 /* Enable interrupts we wish to service */ 1325 if (fep->link) 1326 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1327 else 1328 writel(0, fep->hwp + FEC_IMASK); 1329 1330 /* Init the interrupt coalescing */ 1331 if (fep->quirks & FEC_QUIRK_HAS_COALESCE) 1332 fec_enet_itr_coal_set(ndev); 1333 } 1334 1335 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep) 1336 { 1337 if (!(of_machine_is_compatible("fsl,imx8qm") || 1338 of_machine_is_compatible("fsl,imx8qxp") || 1339 of_machine_is_compatible("fsl,imx8dxl"))) 1340 return 0; 1341 1342 return imx_scu_get_handle(&fep->ipc_handle); 1343 } 1344 1345 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled) 1346 { 1347 struct device_node *np = fep->pdev->dev.of_node; 1348 u32 rsrc_id, val; 1349 int idx; 1350 1351 if (!np || !fep->ipc_handle) 1352 return; 1353 1354 idx = of_alias_get_id(np, "ethernet"); 1355 if (idx < 0) 1356 idx = 0; 1357 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0; 1358 1359 val = enabled ? 1 : 0; 1360 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val); 1361 } 1362 1363 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1364 { 1365 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1366 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1367 1368 if (stop_gpr->gpr) { 1369 if (enabled) 1370 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1371 BIT(stop_gpr->bit), 1372 BIT(stop_gpr->bit)); 1373 else 1374 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1375 BIT(stop_gpr->bit), 0); 1376 } else if (pdata && pdata->sleep_mode_enable) { 1377 pdata->sleep_mode_enable(enabled); 1378 } else { 1379 fec_enet_ipg_stop_set(fep, enabled); 1380 } 1381 } 1382 1383 static void fec_irqs_disable(struct net_device *ndev) 1384 { 1385 struct fec_enet_private *fep = netdev_priv(ndev); 1386 1387 writel(0, fep->hwp + FEC_IMASK); 1388 } 1389 1390 static void fec_irqs_disable_except_wakeup(struct net_device *ndev) 1391 { 1392 struct fec_enet_private *fep = netdev_priv(ndev); 1393 1394 writel(0, fep->hwp + FEC_IMASK); 1395 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1396 } 1397 1398 static void 1399 fec_stop(struct net_device *ndev) 1400 { 1401 struct fec_enet_private *fep = netdev_priv(ndev); 1402 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & FEC_RCR_RMII; 1403 u32 val; 1404 1405 /* We cannot expect a graceful transmit stop without link !!! */ 1406 if (fep->link) { 1407 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1408 udelay(10); 1409 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1410 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1411 } 1412 1413 if (fep->bufdesc_ex) 1414 fec_ptp_save_state(fep); 1415 1416 fec_ctrl_reset(fep, true); 1417 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1418 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1419 1420 /* We have to keep ENET enabled to have MII interrupt stay working */ 1421 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1422 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1423 writel(FEC_ECR_ETHEREN, fep->hwp + FEC_ECNTRL); 1424 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1425 } 1426 1427 if (fep->bufdesc_ex) { 1428 val = readl(fep->hwp + FEC_ECNTRL); 1429 val |= FEC_ECR_EN1588; 1430 writel(val, fep->hwp + FEC_ECNTRL); 1431 1432 fec_ptp_start_cyclecounter(ndev); 1433 fec_ptp_restore_state(fep); 1434 } 1435 } 1436 1437 static void 1438 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1439 { 1440 struct fec_enet_private *fep = netdev_priv(ndev); 1441 1442 fec_dump(ndev); 1443 1444 ndev->stats.tx_errors++; 1445 1446 schedule_work(&fep->tx_timeout_work); 1447 } 1448 1449 static void fec_enet_timeout_work(struct work_struct *work) 1450 { 1451 struct fec_enet_private *fep = 1452 container_of(work, struct fec_enet_private, tx_timeout_work); 1453 struct net_device *ndev = fep->netdev; 1454 1455 rtnl_lock(); 1456 if (netif_device_present(ndev) || netif_running(ndev)) { 1457 napi_disable(&fep->napi); 1458 netif_tx_lock_bh(ndev); 1459 fec_restart(ndev); 1460 netif_tx_wake_all_queues(ndev); 1461 netif_tx_unlock_bh(ndev); 1462 napi_enable(&fep->napi); 1463 } 1464 rtnl_unlock(); 1465 } 1466 1467 static void 1468 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1469 struct skb_shared_hwtstamps *hwtstamps) 1470 { 1471 unsigned long flags; 1472 u64 ns; 1473 1474 spin_lock_irqsave(&fep->tmreg_lock, flags); 1475 ns = timecounter_cyc2time(&fep->tc, ts); 1476 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1477 1478 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1479 hwtstamps->hwtstamp = ns_to_ktime(ns); 1480 } 1481 1482 static void 1483 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id, int budget) 1484 { 1485 struct fec_enet_private *fep; 1486 struct xdp_frame *xdpf; 1487 struct bufdesc *bdp; 1488 unsigned short status; 1489 struct sk_buff *skb; 1490 struct fec_enet_priv_tx_q *txq; 1491 struct netdev_queue *nq; 1492 int index = 0; 1493 int entries_free; 1494 struct page *page; 1495 int frame_len; 1496 1497 fep = netdev_priv(ndev); 1498 1499 txq = fep->tx_queue[queue_id]; 1500 /* get next bdp of dirty_tx */ 1501 nq = netdev_get_tx_queue(ndev, queue_id); 1502 bdp = txq->dirty_tx; 1503 1504 /* get next bdp of dirty_tx */ 1505 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1506 1507 while (bdp != READ_ONCE(txq->bd.cur)) { 1508 /* Order the load of bd.cur and cbd_sc */ 1509 rmb(); 1510 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1511 if (status & BD_ENET_TX_READY) 1512 break; 1513 1514 index = fec_enet_get_bd_index(bdp, &txq->bd); 1515 1516 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1517 skb = txq->tx_buf[index].buf_p; 1518 if (bdp->cbd_bufaddr && 1519 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1520 dma_unmap_single(&fep->pdev->dev, 1521 fec32_to_cpu(bdp->cbd_bufaddr), 1522 fec16_to_cpu(bdp->cbd_datlen), 1523 DMA_TO_DEVICE); 1524 bdp->cbd_bufaddr = cpu_to_fec32(0); 1525 if (!skb) 1526 goto tx_buf_done; 1527 } else { 1528 /* Tx processing cannot call any XDP (or page pool) APIs if 1529 * the "budget" is 0. Because NAPI is called with budget of 1530 * 0 (such as netpoll) indicates we may be in an IRQ context, 1531 * however, we can't use the page pool from IRQ context. 1532 */ 1533 if (unlikely(!budget)) 1534 break; 1535 1536 if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1537 xdpf = txq->tx_buf[index].buf_p; 1538 if (bdp->cbd_bufaddr) 1539 dma_unmap_single(&fep->pdev->dev, 1540 fec32_to_cpu(bdp->cbd_bufaddr), 1541 fec16_to_cpu(bdp->cbd_datlen), 1542 DMA_TO_DEVICE); 1543 } else { 1544 page = txq->tx_buf[index].buf_p; 1545 } 1546 1547 bdp->cbd_bufaddr = cpu_to_fec32(0); 1548 if (unlikely(!txq->tx_buf[index].buf_p)) { 1549 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1550 goto tx_buf_done; 1551 } 1552 1553 frame_len = fec16_to_cpu(bdp->cbd_datlen); 1554 } 1555 1556 /* Check for errors. */ 1557 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1558 BD_ENET_TX_RL | BD_ENET_TX_UN | 1559 BD_ENET_TX_CSL)) { 1560 ndev->stats.tx_errors++; 1561 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1562 ndev->stats.tx_heartbeat_errors++; 1563 if (status & BD_ENET_TX_LC) /* Late collision */ 1564 ndev->stats.tx_window_errors++; 1565 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1566 ndev->stats.tx_aborted_errors++; 1567 if (status & BD_ENET_TX_UN) /* Underrun */ 1568 ndev->stats.tx_fifo_errors++; 1569 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1570 ndev->stats.tx_carrier_errors++; 1571 } else { 1572 ndev->stats.tx_packets++; 1573 1574 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) 1575 ndev->stats.tx_bytes += skb->len; 1576 else 1577 ndev->stats.tx_bytes += frame_len; 1578 } 1579 1580 /* Deferred means some collisions occurred during transmit, 1581 * but we eventually sent the packet OK. 1582 */ 1583 if (status & BD_ENET_TX_DEF) 1584 ndev->stats.collisions++; 1585 1586 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1587 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1588 * are to time stamp the packet, so we still need to check time 1589 * stamping enabled flag. 1590 */ 1591 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1592 fep->hwts_tx_en) && fep->bufdesc_ex) { 1593 struct skb_shared_hwtstamps shhwtstamps; 1594 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1595 1596 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1597 skb_tstamp_tx(skb, &shhwtstamps); 1598 } 1599 1600 /* Free the sk buffer associated with this last transmit */ 1601 napi_consume_skb(skb, budget); 1602 } else if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1603 xdp_return_frame_rx_napi(xdpf); 1604 } else { /* recycle pages of XDP_TX frames */ 1605 /* The dma_sync_size = 0 as XDP_TX has already synced DMA for_device */ 1606 page_pool_put_page(pp_page_to_nmdesc(page)->pp, page, 1607 0, true); 1608 } 1609 1610 txq->tx_buf[index].buf_p = NULL; 1611 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1612 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1613 1614 tx_buf_done: 1615 /* Make sure the update to bdp and tx_buf are performed 1616 * before dirty_tx 1617 */ 1618 wmb(); 1619 txq->dirty_tx = bdp; 1620 1621 /* Update pointer to next buffer descriptor to be transmitted */ 1622 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1623 1624 /* Since we have freed up a buffer, the ring is no longer full 1625 */ 1626 if (netif_tx_queue_stopped(nq)) { 1627 entries_free = fec_enet_get_free_txdesc_num(txq); 1628 if (entries_free >= txq->tx_wake_threshold) 1629 netif_tx_wake_queue(nq); 1630 } 1631 } 1632 1633 /* ERR006358: Keep the transmitter going */ 1634 if (bdp != txq->bd.cur && 1635 readl(txq->bd.reg_desc_active) == 0) 1636 writel(0, txq->bd.reg_desc_active); 1637 } 1638 1639 static void fec_enet_tx(struct net_device *ndev, int budget) 1640 { 1641 struct fec_enet_private *fep = netdev_priv(ndev); 1642 int i; 1643 1644 /* Make sure that AVB queues are processed first. */ 1645 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1646 fec_enet_tx_queue(ndev, i, budget); 1647 } 1648 1649 static int fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq, 1650 struct bufdesc *bdp, int index) 1651 { 1652 struct page *new_page; 1653 dma_addr_t phys_addr; 1654 1655 new_page = page_pool_dev_alloc_pages(rxq->page_pool); 1656 if (unlikely(!new_page)) 1657 return -ENOMEM; 1658 1659 rxq->rx_skb_info[index].page = new_page; 1660 rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM; 1661 phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM; 1662 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 1663 1664 return 0; 1665 } 1666 1667 static u32 1668 fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog, 1669 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int cpu) 1670 { 1671 unsigned int sync, len = xdp->data_end - xdp->data; 1672 u32 ret = FEC_ENET_XDP_PASS; 1673 struct page *page; 1674 int err; 1675 u32 act; 1676 1677 act = bpf_prog_run_xdp(prog, xdp); 1678 1679 /* Due xdp_adjust_tail and xdp_adjust_head: DMA sync for_device cover 1680 * max len CPU touch 1681 */ 1682 sync = xdp->data_end - xdp->data; 1683 sync = max(sync, len); 1684 1685 switch (act) { 1686 case XDP_PASS: 1687 rxq->stats[RX_XDP_PASS]++; 1688 ret = FEC_ENET_XDP_PASS; 1689 break; 1690 1691 case XDP_REDIRECT: 1692 rxq->stats[RX_XDP_REDIRECT]++; 1693 err = xdp_do_redirect(fep->netdev, xdp, prog); 1694 if (unlikely(err)) 1695 goto xdp_err; 1696 1697 ret = FEC_ENET_XDP_REDIR; 1698 break; 1699 1700 case XDP_TX: 1701 rxq->stats[RX_XDP_TX]++; 1702 err = fec_enet_xdp_tx_xmit(fep, cpu, xdp, sync); 1703 if (unlikely(err)) { 1704 rxq->stats[RX_XDP_TX_ERRORS]++; 1705 goto xdp_err; 1706 } 1707 1708 ret = FEC_ENET_XDP_TX; 1709 break; 1710 1711 default: 1712 bpf_warn_invalid_xdp_action(fep->netdev, prog, act); 1713 fallthrough; 1714 1715 case XDP_ABORTED: 1716 fallthrough; /* handle aborts by dropping packet */ 1717 1718 case XDP_DROP: 1719 rxq->stats[RX_XDP_DROP]++; 1720 xdp_err: 1721 ret = FEC_ENET_XDP_CONSUMED; 1722 page = virt_to_head_page(xdp->data); 1723 page_pool_put_page(rxq->page_pool, page, sync, true); 1724 if (act != XDP_DROP) 1725 trace_xdp_exception(fep->netdev, prog, act); 1726 break; 1727 } 1728 1729 return ret; 1730 } 1731 1732 static void fec_enet_rx_vlan(const struct net_device *ndev, struct sk_buff *skb) 1733 { 1734 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX) { 1735 const struct vlan_ethhdr *vlan_header = skb_vlan_eth_hdr(skb); 1736 const u16 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1737 1738 /* Push and remove the vlan tag */ 1739 1740 memmove(skb->data + VLAN_HLEN, skb->data, ETH_ALEN * 2); 1741 skb_pull(skb, VLAN_HLEN); 1742 __vlan_hwaccel_put_tag(skb, 1743 htons(ETH_P_8021Q), 1744 vlan_tag); 1745 } 1746 } 1747 1748 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1749 * When we update through the ring, if the next incoming buffer has 1750 * not been given to the system, we just set the empty indicator, 1751 * effectively tossing the packet. 1752 */ 1753 static int 1754 fec_enet_rx_queue(struct net_device *ndev, u16 queue_id, int budget) 1755 { 1756 struct fec_enet_private *fep = netdev_priv(ndev); 1757 struct fec_enet_priv_rx_q *rxq; 1758 struct bufdesc *bdp; 1759 unsigned short status; 1760 struct sk_buff *skb; 1761 ushort pkt_len; 1762 int pkt_received = 0; 1763 struct bufdesc_ex *ebdp = NULL; 1764 int index = 0; 1765 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1766 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 1767 u32 ret, xdp_result = FEC_ENET_XDP_PASS; 1768 u32 data_start = FEC_ENET_XDP_HEADROOM; 1769 int cpu = smp_processor_id(); 1770 struct xdp_buff xdp; 1771 struct page *page; 1772 __fec32 cbd_bufaddr; 1773 u32 sub_len = 4; 1774 1775 #if !defined(CONFIG_M5272) 1776 /*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of 1777 * FEC_RACC_SHIFT16 is set by default in the probe function. 1778 */ 1779 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1780 data_start += 2; 1781 sub_len += 2; 1782 } 1783 #endif 1784 1785 #if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA) 1786 /* 1787 * Hacky flush of all caches instead of using the DMA API for the TSO 1788 * headers. 1789 */ 1790 flush_cache_all(); 1791 #endif 1792 rxq = fep->rx_queue[queue_id]; 1793 1794 /* First, grab all of the stats for the incoming packet. 1795 * These get messed up if we get called due to a busy condition. 1796 */ 1797 bdp = rxq->bd.cur; 1798 xdp_init_buff(&xdp, PAGE_SIZE << fep->pagepool_order, &rxq->xdp_rxq); 1799 1800 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1801 1802 if (pkt_received >= budget) 1803 break; 1804 pkt_received++; 1805 1806 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT); 1807 1808 /* Check for errors. */ 1809 status ^= BD_ENET_RX_LAST; 1810 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1811 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1812 BD_ENET_RX_CL)) { 1813 ndev->stats.rx_errors++; 1814 if (status & BD_ENET_RX_OV) { 1815 /* FIFO overrun */ 1816 ndev->stats.rx_fifo_errors++; 1817 goto rx_processing_done; 1818 } 1819 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1820 | BD_ENET_RX_LAST)) { 1821 /* Frame too long or too short. */ 1822 ndev->stats.rx_length_errors++; 1823 if (status & BD_ENET_RX_LAST) 1824 netdev_err(ndev, "rcv is not +last\n"); 1825 } 1826 if (status & BD_ENET_RX_CR) /* CRC Error */ 1827 ndev->stats.rx_crc_errors++; 1828 /* Report late collisions as a frame error. */ 1829 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1830 ndev->stats.rx_frame_errors++; 1831 goto rx_processing_done; 1832 } 1833 1834 /* Process the incoming frame. */ 1835 ndev->stats.rx_packets++; 1836 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1837 ndev->stats.rx_bytes += pkt_len; 1838 1839 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1840 page = rxq->rx_skb_info[index].page; 1841 cbd_bufaddr = bdp->cbd_bufaddr; 1842 if (fec_enet_update_cbd(rxq, bdp, index)) { 1843 ndev->stats.rx_dropped++; 1844 goto rx_processing_done; 1845 } 1846 1847 dma_sync_single_for_cpu(&fep->pdev->dev, 1848 fec32_to_cpu(cbd_bufaddr), 1849 pkt_len, 1850 DMA_FROM_DEVICE); 1851 prefetch(page_address(page)); 1852 1853 if (xdp_prog) { 1854 xdp_buff_clear_frags_flag(&xdp); 1855 /* subtract 16bit shift and FCS */ 1856 xdp_prepare_buff(&xdp, page_address(page), 1857 data_start, pkt_len - sub_len, false); 1858 ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, cpu); 1859 xdp_result |= ret; 1860 if (ret != FEC_ENET_XDP_PASS) 1861 goto rx_processing_done; 1862 } 1863 1864 /* The packet length includes FCS, but we don't want to 1865 * include that when passing upstream as it messes up 1866 * bridging applications. 1867 */ 1868 skb = build_skb(page_address(page), 1869 PAGE_SIZE << fep->pagepool_order); 1870 if (unlikely(!skb)) { 1871 page_pool_recycle_direct(rxq->page_pool, page); 1872 ndev->stats.rx_dropped++; 1873 1874 netdev_err_once(ndev, "build_skb failed!\n"); 1875 goto rx_processing_done; 1876 } 1877 1878 skb_reserve(skb, data_start); 1879 skb_put(skb, pkt_len - sub_len); 1880 skb_mark_for_recycle(skb); 1881 1882 if (unlikely(need_swap)) { 1883 u8 *data; 1884 1885 data = page_address(page) + FEC_ENET_XDP_HEADROOM; 1886 swap_buffer(data, pkt_len); 1887 } 1888 1889 /* Extract the enhanced buffer descriptor */ 1890 ebdp = NULL; 1891 if (fep->bufdesc_ex) 1892 ebdp = (struct bufdesc_ex *)bdp; 1893 1894 /* If this is a VLAN packet remove the VLAN Tag */ 1895 if (fep->bufdesc_ex && 1896 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) 1897 fec_enet_rx_vlan(ndev, skb); 1898 1899 skb->protocol = eth_type_trans(skb, ndev); 1900 1901 /* Get receive timestamp from the skb */ 1902 if (fep->hwts_rx_en && fep->bufdesc_ex) 1903 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1904 skb_hwtstamps(skb)); 1905 1906 if (fep->bufdesc_ex && 1907 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1908 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1909 /* don't check it */ 1910 skb->ip_summed = CHECKSUM_UNNECESSARY; 1911 } else { 1912 skb_checksum_none_assert(skb); 1913 } 1914 } 1915 1916 skb_record_rx_queue(skb, queue_id); 1917 napi_gro_receive(&fep->napi, skb); 1918 1919 rx_processing_done: 1920 /* Clear the status flags for this buffer */ 1921 status &= ~BD_ENET_RX_STATS; 1922 1923 /* Mark the buffer empty */ 1924 status |= BD_ENET_RX_EMPTY; 1925 1926 if (fep->bufdesc_ex) { 1927 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1928 1929 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1930 ebdp->cbd_prot = 0; 1931 ebdp->cbd_bdu = 0; 1932 } 1933 /* Make sure the updates to rest of the descriptor are 1934 * performed before transferring ownership. 1935 */ 1936 wmb(); 1937 bdp->cbd_sc = cpu_to_fec16(status); 1938 1939 /* Update BD pointer to next entry */ 1940 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1941 1942 /* Doing this here will keep the FEC running while we process 1943 * incoming frames. On a heavily loaded network, we should be 1944 * able to keep up at the expense of system resources. 1945 */ 1946 writel(0, rxq->bd.reg_desc_active); 1947 } 1948 rxq->bd.cur = bdp; 1949 1950 if (xdp_result & FEC_ENET_XDP_REDIR) 1951 xdp_do_flush(); 1952 1953 return pkt_received; 1954 } 1955 1956 static int fec_enet_rx(struct net_device *ndev, int budget) 1957 { 1958 struct fec_enet_private *fep = netdev_priv(ndev); 1959 int i, done = 0; 1960 1961 /* Make sure that AVB queues are processed first. */ 1962 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1963 done += fec_enet_rx_queue(ndev, i, budget - done); 1964 1965 return done; 1966 } 1967 1968 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1969 { 1970 uint int_events; 1971 1972 int_events = readl(fep->hwp + FEC_IEVENT); 1973 1974 /* Don't clear MDIO events, we poll for those */ 1975 int_events &= ~FEC_ENET_MII; 1976 1977 writel(int_events, fep->hwp + FEC_IEVENT); 1978 1979 return int_events != 0; 1980 } 1981 1982 static irqreturn_t 1983 fec_enet_interrupt(int irq, void *dev_id) 1984 { 1985 struct net_device *ndev = dev_id; 1986 struct fec_enet_private *fep = netdev_priv(ndev); 1987 irqreturn_t ret = IRQ_NONE; 1988 1989 if (fec_enet_collect_events(fep) && fep->link) { 1990 ret = IRQ_HANDLED; 1991 1992 if (napi_schedule_prep(&fep->napi)) { 1993 /* Disable interrupts */ 1994 writel(0, fep->hwp + FEC_IMASK); 1995 __napi_schedule(&fep->napi); 1996 } 1997 } 1998 1999 return ret; 2000 } 2001 2002 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 2003 { 2004 struct net_device *ndev = napi->dev; 2005 struct fec_enet_private *fep = netdev_priv(ndev); 2006 int done = 0; 2007 2008 do { 2009 done += fec_enet_rx(ndev, budget - done); 2010 fec_enet_tx(ndev, budget); 2011 } while ((done < budget) && fec_enet_collect_events(fep)); 2012 2013 if (done < budget) { 2014 napi_complete_done(napi, done); 2015 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 2016 } 2017 2018 return done; 2019 } 2020 2021 /* ------------------------------------------------------------------------- */ 2022 static int fec_get_mac(struct net_device *ndev) 2023 { 2024 struct fec_enet_private *fep = netdev_priv(ndev); 2025 unsigned char *iap, tmpaddr[ETH_ALEN]; 2026 int ret; 2027 2028 /* 2029 * try to get mac address in following order: 2030 * 2031 * 1) module parameter via kernel command line in form 2032 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 2033 */ 2034 iap = macaddr; 2035 2036 /* 2037 * 2) from device tree data 2038 */ 2039 if (!is_valid_ether_addr(iap)) { 2040 struct device_node *np = fep->pdev->dev.of_node; 2041 if (np) { 2042 ret = of_get_mac_address(np, tmpaddr); 2043 if (!ret) 2044 iap = tmpaddr; 2045 else if (ret == -EPROBE_DEFER) 2046 return ret; 2047 } 2048 } 2049 2050 /* 2051 * 3) from flash or fuse (via platform data) 2052 */ 2053 if (!is_valid_ether_addr(iap)) { 2054 #ifdef CONFIG_M5272 2055 if (FEC_FLASHMAC) 2056 iap = (unsigned char *)FEC_FLASHMAC; 2057 #else 2058 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 2059 2060 if (pdata) 2061 iap = (unsigned char *)&pdata->mac; 2062 #endif 2063 } 2064 2065 /* 2066 * 4) FEC mac registers set by bootloader 2067 */ 2068 if (!is_valid_ether_addr(iap)) { 2069 *((__be32 *) &tmpaddr[0]) = 2070 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 2071 *((__be16 *) &tmpaddr[4]) = 2072 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 2073 iap = &tmpaddr[0]; 2074 } 2075 2076 /* 2077 * 5) random mac address 2078 */ 2079 if (!is_valid_ether_addr(iap)) { 2080 /* Report it and use a random ethernet address instead */ 2081 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 2082 eth_hw_addr_random(ndev); 2083 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 2084 ndev->dev_addr); 2085 return 0; 2086 } 2087 2088 /* Adjust MAC if using macaddr */ 2089 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0); 2090 2091 return 0; 2092 } 2093 2094 /* ------------------------------------------------------------------------- */ 2095 2096 /* 2097 * Phy section 2098 */ 2099 2100 /* LPI Sleep Ts count base on tx clk (clk_ref). 2101 * The lpi sleep cnt value = X us / (cycle_ns). 2102 */ 2103 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) 2104 { 2105 struct fec_enet_private *fep = netdev_priv(ndev); 2106 2107 return us * (fep->clk_ref_rate / 1000) / 1000; 2108 } 2109 2110 static int fec_enet_eee_mode_set(struct net_device *ndev, u32 lpi_timer, 2111 bool enable) 2112 { 2113 struct fec_enet_private *fep = netdev_priv(ndev); 2114 unsigned int sleep_cycle, wake_cycle; 2115 2116 if (enable) { 2117 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, lpi_timer); 2118 wake_cycle = sleep_cycle; 2119 } else { 2120 sleep_cycle = 0; 2121 wake_cycle = 0; 2122 } 2123 2124 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); 2125 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); 2126 2127 return 0; 2128 } 2129 2130 static void fec_enet_adjust_link(struct net_device *ndev) 2131 { 2132 struct fec_enet_private *fep = netdev_priv(ndev); 2133 struct phy_device *phy_dev = ndev->phydev; 2134 int status_change = 0; 2135 2136 /* 2137 * If the netdev is down, or is going down, we're not interested 2138 * in link state events, so just mark our idea of the link as down 2139 * and ignore the event. 2140 */ 2141 if (!netif_running(ndev) || !netif_device_present(ndev)) { 2142 fep->link = 0; 2143 } else if (phy_dev->link) { 2144 if (!fep->link) { 2145 fep->link = phy_dev->link; 2146 status_change = 1; 2147 } 2148 2149 if (fep->full_duplex != phy_dev->duplex) { 2150 fep->full_duplex = phy_dev->duplex; 2151 status_change = 1; 2152 } 2153 2154 if (phy_dev->speed != fep->speed) { 2155 fep->speed = phy_dev->speed; 2156 status_change = 1; 2157 } 2158 2159 /* if any of the above changed restart the FEC */ 2160 if (status_change) { 2161 netif_stop_queue(ndev); 2162 napi_disable(&fep->napi); 2163 netif_tx_lock_bh(ndev); 2164 fec_restart(ndev); 2165 netif_tx_wake_all_queues(ndev); 2166 netif_tx_unlock_bh(ndev); 2167 napi_enable(&fep->napi); 2168 } 2169 if (fep->quirks & FEC_QUIRK_HAS_EEE) 2170 fec_enet_eee_mode_set(ndev, 2171 phy_dev->eee_cfg.tx_lpi_timer, 2172 phy_dev->enable_tx_lpi); 2173 } else { 2174 if (fep->link) { 2175 netif_stop_queue(ndev); 2176 napi_disable(&fep->napi); 2177 netif_tx_lock_bh(ndev); 2178 fec_stop(ndev); 2179 netif_tx_unlock_bh(ndev); 2180 napi_enable(&fep->napi); 2181 fep->link = phy_dev->link; 2182 status_change = 1; 2183 } 2184 } 2185 2186 if (status_change) 2187 phy_print_status(phy_dev); 2188 } 2189 2190 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 2191 { 2192 uint ievent; 2193 int ret; 2194 2195 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 2196 ievent & FEC_ENET_MII, 2, 30000); 2197 2198 if (!ret) 2199 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2200 2201 return ret; 2202 } 2203 2204 static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) 2205 { 2206 struct fec_enet_private *fep = bus->priv; 2207 struct device *dev = &fep->pdev->dev; 2208 int ret = 0, frame_start, frame_addr, frame_op; 2209 2210 ret = pm_runtime_resume_and_get(dev); 2211 if (ret < 0) 2212 return ret; 2213 2214 /* C22 read */ 2215 frame_op = FEC_MMFR_OP_READ; 2216 frame_start = FEC_MMFR_ST; 2217 frame_addr = regnum; 2218 2219 /* start a read op */ 2220 writel(frame_start | frame_op | 2221 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2222 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2223 2224 /* wait for end of transfer */ 2225 ret = fec_enet_mdio_wait(fep); 2226 if (ret) { 2227 netdev_err(fep->netdev, "MDIO read timeout\n"); 2228 goto out; 2229 } 2230 2231 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2232 2233 out: 2234 pm_runtime_put_autosuspend(dev); 2235 2236 return ret; 2237 } 2238 2239 static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id, 2240 int devad, int regnum) 2241 { 2242 struct fec_enet_private *fep = bus->priv; 2243 struct device *dev = &fep->pdev->dev; 2244 int ret = 0, frame_start, frame_op; 2245 2246 ret = pm_runtime_resume_and_get(dev); 2247 if (ret < 0) 2248 return ret; 2249 2250 frame_start = FEC_MMFR_ST_C45; 2251 2252 /* write address */ 2253 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2254 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2255 FEC_MMFR_TA | (regnum & 0xFFFF), 2256 fep->hwp + FEC_MII_DATA); 2257 2258 /* wait for end of transfer */ 2259 ret = fec_enet_mdio_wait(fep); 2260 if (ret) { 2261 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2262 goto out; 2263 } 2264 2265 frame_op = FEC_MMFR_OP_READ_C45; 2266 2267 /* start a read op */ 2268 writel(frame_start | frame_op | 2269 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2270 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2271 2272 /* wait for end of transfer */ 2273 ret = fec_enet_mdio_wait(fep); 2274 if (ret) { 2275 netdev_err(fep->netdev, "MDIO read timeout\n"); 2276 goto out; 2277 } 2278 2279 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2280 2281 out: 2282 pm_runtime_put_autosuspend(dev); 2283 2284 return ret; 2285 } 2286 2287 static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, 2288 u16 value) 2289 { 2290 struct fec_enet_private *fep = bus->priv; 2291 struct device *dev = &fep->pdev->dev; 2292 int ret, frame_start, frame_addr; 2293 2294 ret = pm_runtime_resume_and_get(dev); 2295 if (ret < 0) 2296 return ret; 2297 2298 /* C22 write */ 2299 frame_start = FEC_MMFR_ST; 2300 frame_addr = regnum; 2301 2302 /* start a write op */ 2303 writel(frame_start | FEC_MMFR_OP_WRITE | 2304 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2305 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2306 fep->hwp + FEC_MII_DATA); 2307 2308 /* wait for end of transfer */ 2309 ret = fec_enet_mdio_wait(fep); 2310 if (ret) 2311 netdev_err(fep->netdev, "MDIO write timeout\n"); 2312 2313 pm_runtime_put_autosuspend(dev); 2314 2315 return ret; 2316 } 2317 2318 static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id, 2319 int devad, int regnum, u16 value) 2320 { 2321 struct fec_enet_private *fep = bus->priv; 2322 struct device *dev = &fep->pdev->dev; 2323 int ret, frame_start; 2324 2325 ret = pm_runtime_resume_and_get(dev); 2326 if (ret < 0) 2327 return ret; 2328 2329 frame_start = FEC_MMFR_ST_C45; 2330 2331 /* write address */ 2332 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2333 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2334 FEC_MMFR_TA | (regnum & 0xFFFF), 2335 fep->hwp + FEC_MII_DATA); 2336 2337 /* wait for end of transfer */ 2338 ret = fec_enet_mdio_wait(fep); 2339 if (ret) { 2340 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2341 goto out; 2342 } 2343 2344 /* start a write op */ 2345 writel(frame_start | FEC_MMFR_OP_WRITE | 2346 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2347 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2348 fep->hwp + FEC_MII_DATA); 2349 2350 /* wait for end of transfer */ 2351 ret = fec_enet_mdio_wait(fep); 2352 if (ret) 2353 netdev_err(fep->netdev, "MDIO write timeout\n"); 2354 2355 out: 2356 pm_runtime_put_autosuspend(dev); 2357 2358 return ret; 2359 } 2360 2361 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 2362 { 2363 struct fec_enet_private *fep = netdev_priv(ndev); 2364 struct phy_device *phy_dev = ndev->phydev; 2365 2366 if (phy_dev) { 2367 phy_reset_after_clk_enable(phy_dev); 2368 } else if (fep->phy_node) { 2369 /* 2370 * If the PHY still is not bound to the MAC, but there is 2371 * OF PHY node and a matching PHY device instance already, 2372 * use the OF PHY node to obtain the PHY device instance, 2373 * and then use that PHY device instance when triggering 2374 * the PHY reset. 2375 */ 2376 phy_dev = of_phy_find_device(fep->phy_node); 2377 phy_reset_after_clk_enable(phy_dev); 2378 if (phy_dev) 2379 put_device(&phy_dev->mdio.dev); 2380 } 2381 } 2382 2383 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 2384 { 2385 struct fec_enet_private *fep = netdev_priv(ndev); 2386 int ret; 2387 2388 if (enable) { 2389 ret = clk_prepare_enable(fep->clk_enet_out); 2390 if (ret) 2391 return ret; 2392 2393 if (fep->clk_ptp) { 2394 mutex_lock(&fep->ptp_clk_mutex); 2395 ret = clk_prepare_enable(fep->clk_ptp); 2396 if (ret) { 2397 mutex_unlock(&fep->ptp_clk_mutex); 2398 goto failed_clk_ptp; 2399 } else { 2400 fep->ptp_clk_on = true; 2401 } 2402 mutex_unlock(&fep->ptp_clk_mutex); 2403 } 2404 2405 ret = clk_prepare_enable(fep->clk_ref); 2406 if (ret) 2407 goto failed_clk_ref; 2408 2409 ret = clk_prepare_enable(fep->clk_2x_txclk); 2410 if (ret) 2411 goto failed_clk_2x_txclk; 2412 2413 fec_enet_phy_reset_after_clk_enable(ndev); 2414 } else { 2415 clk_disable_unprepare(fep->clk_enet_out); 2416 if (fep->clk_ptp) { 2417 mutex_lock(&fep->ptp_clk_mutex); 2418 clk_disable_unprepare(fep->clk_ptp); 2419 fep->ptp_clk_on = false; 2420 mutex_unlock(&fep->ptp_clk_mutex); 2421 } 2422 clk_disable_unprepare(fep->clk_ref); 2423 clk_disable_unprepare(fep->clk_2x_txclk); 2424 } 2425 2426 return 0; 2427 2428 failed_clk_2x_txclk: 2429 if (fep->clk_ref) 2430 clk_disable_unprepare(fep->clk_ref); 2431 failed_clk_ref: 2432 if (fep->clk_ptp) { 2433 mutex_lock(&fep->ptp_clk_mutex); 2434 clk_disable_unprepare(fep->clk_ptp); 2435 fep->ptp_clk_on = false; 2436 mutex_unlock(&fep->ptp_clk_mutex); 2437 } 2438 failed_clk_ptp: 2439 clk_disable_unprepare(fep->clk_enet_out); 2440 2441 return ret; 2442 } 2443 2444 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep, 2445 struct device_node *np) 2446 { 2447 u32 rgmii_tx_delay, rgmii_rx_delay; 2448 2449 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ 2450 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { 2451 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) { 2452 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); 2453 return -EINVAL; 2454 } else if (rgmii_tx_delay == 2000) { 2455 fep->rgmii_txc_dly = true; 2456 } 2457 } 2458 2459 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */ 2460 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { 2461 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) { 2462 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); 2463 return -EINVAL; 2464 } else if (rgmii_rx_delay == 2000) { 2465 fep->rgmii_rxc_dly = true; 2466 } 2467 } 2468 2469 return 0; 2470 } 2471 2472 static int fec_enet_mii_probe(struct net_device *ndev) 2473 { 2474 struct fec_enet_private *fep = netdev_priv(ndev); 2475 struct phy_device *phy_dev = NULL; 2476 char mdio_bus_id[MII_BUS_ID_SIZE]; 2477 char phy_name[MII_BUS_ID_SIZE + 3]; 2478 int phy_id; 2479 int dev_id = fep->dev_id; 2480 2481 if (fep->phy_node) { 2482 phy_dev = of_phy_connect(ndev, fep->phy_node, 2483 &fec_enet_adjust_link, 0, 2484 fep->phy_interface); 2485 if (!phy_dev) { 2486 netdev_err(ndev, "Unable to connect to phy\n"); 2487 return -ENODEV; 2488 } 2489 } else { 2490 /* check for attached phy */ 2491 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2492 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2493 continue; 2494 if (dev_id--) 2495 continue; 2496 strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2497 break; 2498 } 2499 2500 if (phy_id >= PHY_MAX_ADDR) { 2501 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2502 strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2503 phy_id = 0; 2504 } 2505 2506 snprintf(phy_name, sizeof(phy_name), 2507 PHY_ID_FMT, mdio_bus_id, phy_id); 2508 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2509 fep->phy_interface); 2510 } 2511 2512 if (IS_ERR(phy_dev)) { 2513 netdev_err(ndev, "could not attach to PHY\n"); 2514 return PTR_ERR(phy_dev); 2515 } 2516 2517 /* mask with MAC supported features */ 2518 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2519 phy_set_max_speed(phy_dev, 1000); 2520 phy_remove_link_mode(phy_dev, 2521 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2522 #if !defined(CONFIG_M5272) 2523 phy_support_sym_pause(phy_dev); 2524 #endif 2525 } 2526 else 2527 phy_set_max_speed(phy_dev, 100); 2528 2529 if (fep->quirks & FEC_QUIRK_HAS_EEE) 2530 phy_support_eee(phy_dev); 2531 2532 fep->link = 0; 2533 fep->full_duplex = 0; 2534 2535 phy_attached_info(phy_dev); 2536 2537 return 0; 2538 } 2539 2540 static int fec_enet_mii_init(struct platform_device *pdev) 2541 { 2542 static struct mii_bus *fec0_mii_bus; 2543 struct net_device *ndev = platform_get_drvdata(pdev); 2544 struct fec_enet_private *fep = netdev_priv(ndev); 2545 bool suppress_preamble = false; 2546 struct phy_device *phydev; 2547 struct device_node *node; 2548 int err = -ENXIO; 2549 u32 mii_speed, holdtime; 2550 u32 bus_freq; 2551 2552 /* 2553 * The i.MX28 dual fec interfaces are not equal. 2554 * Here are the differences: 2555 * 2556 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2557 * - fec0 acts as the 1588 time master while fec1 is slave 2558 * - external phys can only be configured by fec0 2559 * 2560 * That is to say fec1 can not work independently. It only works 2561 * when fec0 is working. The reason behind this design is that the 2562 * second interface is added primarily for Switch mode. 2563 * 2564 * Because of the last point above, both phys are attached on fec0 2565 * mdio interface in board design, and need to be configured by 2566 * fec0 mii_bus. 2567 */ 2568 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2569 /* fec1 uses fec0 mii_bus */ 2570 if (mii_cnt && fec0_mii_bus) { 2571 fep->mii_bus = fec0_mii_bus; 2572 mii_cnt++; 2573 return 0; 2574 } 2575 return -ENOENT; 2576 } 2577 2578 bus_freq = 2500000; /* 2.5MHz by default */ 2579 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2580 if (node) { 2581 of_property_read_u32(node, "clock-frequency", &bus_freq); 2582 suppress_preamble = of_property_read_bool(node, 2583 "suppress-preamble"); 2584 } 2585 2586 /* 2587 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2588 * 2589 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2590 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2591 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2592 * document. 2593 */ 2594 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2595 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2596 mii_speed--; 2597 if (mii_speed > 63) { 2598 dev_err(&pdev->dev, 2599 "fec clock (%lu) too fast to get right mii speed\n", 2600 clk_get_rate(fep->clk_ipg)); 2601 err = -EINVAL; 2602 goto err_out; 2603 } 2604 2605 /* 2606 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2607 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2608 * versions are RAZ there, so just ignore the difference and write the 2609 * register always. 2610 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2611 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2612 * output. 2613 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2614 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2615 * holdtime cannot result in a value greater than 3. 2616 */ 2617 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2618 2619 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2620 2621 if (suppress_preamble) 2622 fep->phy_speed |= BIT(7); 2623 2624 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2625 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2626 * MII event generation condition: 2627 * - writing MSCR: 2628 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2629 * mscr_reg_data_in[7:0] != 0 2630 * - writing MMFR: 2631 * - mscr[7:0]_not_zero 2632 */ 2633 writel(0, fep->hwp + FEC_MII_DATA); 2634 } 2635 2636 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2637 2638 /* Clear any pending transaction complete indication */ 2639 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2640 2641 fep->mii_bus = mdiobus_alloc(); 2642 if (fep->mii_bus == NULL) { 2643 err = -ENOMEM; 2644 goto err_out; 2645 } 2646 2647 fep->mii_bus->name = "fec_enet_mii_bus"; 2648 fep->mii_bus->read = fec_enet_mdio_read_c22; 2649 fep->mii_bus->write = fec_enet_mdio_write_c22; 2650 if (fep->quirks & FEC_QUIRK_HAS_MDIO_C45) { 2651 fep->mii_bus->read_c45 = fec_enet_mdio_read_c45; 2652 fep->mii_bus->write_c45 = fec_enet_mdio_write_c45; 2653 } 2654 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2655 pdev->name, fep->dev_id + 1); 2656 fep->mii_bus->priv = fep; 2657 fep->mii_bus->parent = &pdev->dev; 2658 2659 err = of_mdiobus_register(fep->mii_bus, node); 2660 if (err) 2661 goto err_out_free_mdiobus; 2662 of_node_put(node); 2663 2664 /* find all the PHY devices on the bus and set mac_managed_pm to true */ 2665 mdiobus_for_each_phy(fep->mii_bus, phydev) 2666 phydev->mac_managed_pm = true; 2667 2668 mii_cnt++; 2669 2670 /* save fec0 mii_bus */ 2671 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2672 fec0_mii_bus = fep->mii_bus; 2673 2674 return 0; 2675 2676 err_out_free_mdiobus: 2677 mdiobus_free(fep->mii_bus); 2678 err_out: 2679 of_node_put(node); 2680 return err; 2681 } 2682 2683 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2684 { 2685 if (--mii_cnt == 0) { 2686 mdiobus_unregister(fep->mii_bus); 2687 mdiobus_free(fep->mii_bus); 2688 } 2689 } 2690 2691 static void fec_enet_get_drvinfo(struct net_device *ndev, 2692 struct ethtool_drvinfo *info) 2693 { 2694 struct fec_enet_private *fep = netdev_priv(ndev); 2695 2696 strscpy(info->driver, fep->pdev->dev.driver->name, 2697 sizeof(info->driver)); 2698 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2699 } 2700 2701 static int fec_enet_get_regs_len(struct net_device *ndev) 2702 { 2703 struct fec_enet_private *fep = netdev_priv(ndev); 2704 struct resource *r; 2705 int s = 0; 2706 2707 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2708 if (r) 2709 s = resource_size(r); 2710 2711 return s; 2712 } 2713 2714 /* List of registers that can be safety be read to dump them with ethtool */ 2715 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2716 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2717 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2718 static __u32 fec_enet_register_version = 2; 2719 static u32 fec_enet_register_offset[] = { 2720 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2721 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2722 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2723 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2724 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2725 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2726 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2727 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2728 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2729 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2730 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2731 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2732 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2733 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2734 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2735 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2736 RMON_T_P_GTE2048, RMON_T_OCTETS, 2737 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2738 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2739 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2740 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2741 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2742 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2743 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2744 RMON_R_P_GTE2048, RMON_R_OCTETS, 2745 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2746 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2747 }; 2748 /* for i.MX6ul */ 2749 static u32 fec_enet_register_offset_6ul[] = { 2750 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2751 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2752 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0, 2753 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, 2754 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0, 2755 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2756 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, 2757 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2758 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2759 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2760 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2761 RMON_T_P_GTE2048, RMON_T_OCTETS, 2762 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2763 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2764 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2765 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2766 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2767 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2768 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2769 RMON_R_P_GTE2048, RMON_R_OCTETS, 2770 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2771 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2772 }; 2773 #else 2774 static __u32 fec_enet_register_version = 1; 2775 static u32 fec_enet_register_offset[] = { 2776 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2777 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2778 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2779 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2780 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2781 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2782 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2783 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2784 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2785 }; 2786 #endif 2787 2788 static void fec_enet_get_regs(struct net_device *ndev, 2789 struct ethtool_regs *regs, void *regbuf) 2790 { 2791 struct fec_enet_private *fep = netdev_priv(ndev); 2792 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2793 struct device *dev = &fep->pdev->dev; 2794 u32 *buf = (u32 *)regbuf; 2795 u32 i, off; 2796 int ret; 2797 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2798 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2799 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2800 u32 *reg_list; 2801 u32 reg_cnt; 2802 2803 if (!of_machine_is_compatible("fsl,imx6ul")) { 2804 reg_list = fec_enet_register_offset; 2805 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2806 } else { 2807 reg_list = fec_enet_register_offset_6ul; 2808 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul); 2809 } 2810 #else 2811 /* coldfire */ 2812 static u32 *reg_list = fec_enet_register_offset; 2813 static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2814 #endif 2815 ret = pm_runtime_resume_and_get(dev); 2816 if (ret < 0) 2817 return; 2818 2819 regs->version = fec_enet_register_version; 2820 2821 memset(buf, 0, regs->len); 2822 2823 for (i = 0; i < reg_cnt; i++) { 2824 off = reg_list[i]; 2825 2826 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2827 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2828 continue; 2829 2830 off >>= 2; 2831 buf[off] = readl(&theregs[off]); 2832 } 2833 2834 pm_runtime_put_autosuspend(dev); 2835 } 2836 2837 static int fec_enet_get_ts_info(struct net_device *ndev, 2838 struct kernel_ethtool_ts_info *info) 2839 { 2840 struct fec_enet_private *fep = netdev_priv(ndev); 2841 2842 if (fep->bufdesc_ex) { 2843 2844 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2845 SOF_TIMESTAMPING_TX_HARDWARE | 2846 SOF_TIMESTAMPING_RX_HARDWARE | 2847 SOF_TIMESTAMPING_RAW_HARDWARE; 2848 if (fep->ptp_clock) 2849 info->phc_index = ptp_clock_index(fep->ptp_clock); 2850 2851 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2852 (1 << HWTSTAMP_TX_ON); 2853 2854 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2855 (1 << HWTSTAMP_FILTER_ALL); 2856 return 0; 2857 } else { 2858 return ethtool_op_get_ts_info(ndev, info); 2859 } 2860 } 2861 2862 #if !defined(CONFIG_M5272) 2863 2864 static void fec_enet_get_pauseparam(struct net_device *ndev, 2865 struct ethtool_pauseparam *pause) 2866 { 2867 struct fec_enet_private *fep = netdev_priv(ndev); 2868 2869 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2870 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2871 pause->rx_pause = pause->tx_pause; 2872 } 2873 2874 static int fec_enet_set_pauseparam(struct net_device *ndev, 2875 struct ethtool_pauseparam *pause) 2876 { 2877 struct fec_enet_private *fep = netdev_priv(ndev); 2878 2879 if (!ndev->phydev) 2880 return -ENODEV; 2881 2882 if (pause->tx_pause != pause->rx_pause) { 2883 netdev_info(ndev, 2884 "hardware only support enable/disable both tx and rx"); 2885 return -EINVAL; 2886 } 2887 2888 fep->pause_flag = 0; 2889 2890 /* tx pause must be same as rx pause */ 2891 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2892 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2893 2894 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2895 pause->autoneg); 2896 2897 if (pause->autoneg) { 2898 if (netif_running(ndev)) 2899 fec_stop(ndev); 2900 phy_start_aneg(ndev->phydev); 2901 } 2902 if (netif_running(ndev)) { 2903 napi_disable(&fep->napi); 2904 netif_tx_lock_bh(ndev); 2905 fec_restart(ndev); 2906 netif_tx_wake_all_queues(ndev); 2907 netif_tx_unlock_bh(ndev); 2908 napi_enable(&fep->napi); 2909 } 2910 2911 return 0; 2912 } 2913 2914 static const struct fec_stat { 2915 char name[ETH_GSTRING_LEN]; 2916 u16 offset; 2917 } fec_stats[] = { 2918 /* RMON TX */ 2919 { "tx_dropped", RMON_T_DROP }, 2920 { "tx_packets", RMON_T_PACKETS }, 2921 { "tx_broadcast", RMON_T_BC_PKT }, 2922 { "tx_multicast", RMON_T_MC_PKT }, 2923 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2924 { "tx_undersize", RMON_T_UNDERSIZE }, 2925 { "tx_oversize", RMON_T_OVERSIZE }, 2926 { "tx_fragment", RMON_T_FRAG }, 2927 { "tx_jabber", RMON_T_JAB }, 2928 { "tx_collision", RMON_T_COL }, 2929 { "tx_64byte", RMON_T_P64 }, 2930 { "tx_65to127byte", RMON_T_P65TO127 }, 2931 { "tx_128to255byte", RMON_T_P128TO255 }, 2932 { "tx_256to511byte", RMON_T_P256TO511 }, 2933 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2934 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2935 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2936 { "tx_octets", RMON_T_OCTETS }, 2937 2938 /* IEEE TX */ 2939 { "IEEE_tx_drop", IEEE_T_DROP }, 2940 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2941 { "IEEE_tx_1col", IEEE_T_1COL }, 2942 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2943 { "IEEE_tx_def", IEEE_T_DEF }, 2944 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2945 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2946 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2947 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2948 { "IEEE_tx_sqe", IEEE_T_SQE }, 2949 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2950 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2951 2952 /* RMON RX */ 2953 { "rx_packets", RMON_R_PACKETS }, 2954 { "rx_broadcast", RMON_R_BC_PKT }, 2955 { "rx_multicast", RMON_R_MC_PKT }, 2956 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2957 { "rx_undersize", RMON_R_UNDERSIZE }, 2958 { "rx_oversize", RMON_R_OVERSIZE }, 2959 { "rx_fragment", RMON_R_FRAG }, 2960 { "rx_jabber", RMON_R_JAB }, 2961 { "rx_64byte", RMON_R_P64 }, 2962 { "rx_65to127byte", RMON_R_P65TO127 }, 2963 { "rx_128to255byte", RMON_R_P128TO255 }, 2964 { "rx_256to511byte", RMON_R_P256TO511 }, 2965 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2966 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2967 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2968 { "rx_octets", RMON_R_OCTETS }, 2969 2970 /* IEEE RX */ 2971 { "IEEE_rx_drop", IEEE_R_DROP }, 2972 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2973 { "IEEE_rx_crc", IEEE_R_CRC }, 2974 { "IEEE_rx_align", IEEE_R_ALIGN }, 2975 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2976 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2977 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2978 }; 2979 2980 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2981 2982 static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = { 2983 "rx_xdp_redirect", /* RX_XDP_REDIRECT = 0, */ 2984 "rx_xdp_pass", /* RX_XDP_PASS, */ 2985 "rx_xdp_drop", /* RX_XDP_DROP, */ 2986 "rx_xdp_tx", /* RX_XDP_TX, */ 2987 "rx_xdp_tx_errors", /* RX_XDP_TX_ERRORS, */ 2988 "tx_xdp_xmit", /* TX_XDP_XMIT, */ 2989 "tx_xdp_xmit_errors", /* TX_XDP_XMIT_ERRORS, */ 2990 }; 2991 2992 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2993 { 2994 struct fec_enet_private *fep = netdev_priv(dev); 2995 int i; 2996 2997 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2998 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2999 } 3000 3001 static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data) 3002 { 3003 u64 xdp_stats[XDP_STATS_TOTAL] = { 0 }; 3004 struct fec_enet_priv_rx_q *rxq; 3005 int i, j; 3006 3007 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 3008 rxq = fep->rx_queue[i]; 3009 3010 for (j = 0; j < XDP_STATS_TOTAL; j++) 3011 xdp_stats[j] += rxq->stats[j]; 3012 } 3013 3014 memcpy(data, xdp_stats, sizeof(xdp_stats)); 3015 } 3016 3017 static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data) 3018 { 3019 #ifdef CONFIG_PAGE_POOL_STATS 3020 struct page_pool_stats stats = {}; 3021 struct fec_enet_priv_rx_q *rxq; 3022 int i; 3023 3024 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 3025 rxq = fep->rx_queue[i]; 3026 3027 if (!rxq->page_pool) 3028 continue; 3029 3030 page_pool_get_stats(rxq->page_pool, &stats); 3031 } 3032 3033 page_pool_ethtool_stats_get(data, &stats); 3034 #endif 3035 } 3036 3037 static void fec_enet_get_ethtool_stats(struct net_device *dev, 3038 struct ethtool_stats *stats, u64 *data) 3039 { 3040 struct fec_enet_private *fep = netdev_priv(dev); 3041 3042 if (netif_running(dev)) 3043 fec_enet_update_ethtool_stats(dev); 3044 3045 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 3046 data += FEC_STATS_SIZE / sizeof(u64); 3047 3048 fec_enet_get_xdp_stats(fep, data); 3049 data += XDP_STATS_TOTAL; 3050 3051 fec_enet_page_pool_stats(fep, data); 3052 } 3053 3054 static void fec_enet_get_strings(struct net_device *netdev, 3055 u32 stringset, u8 *data) 3056 { 3057 int i; 3058 switch (stringset) { 3059 case ETH_SS_STATS: 3060 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) { 3061 ethtool_puts(&data, fec_stats[i].name); 3062 } 3063 for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) { 3064 ethtool_puts(&data, fec_xdp_stat_strs[i]); 3065 } 3066 page_pool_ethtool_stats_get_strings(data); 3067 3068 break; 3069 case ETH_SS_TEST: 3070 net_selftest_get_strings(data); 3071 break; 3072 } 3073 } 3074 3075 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 3076 { 3077 int count; 3078 3079 switch (sset) { 3080 case ETH_SS_STATS: 3081 count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL; 3082 count += page_pool_ethtool_stats_get_count(); 3083 return count; 3084 3085 case ETH_SS_TEST: 3086 return net_selftest_get_count(); 3087 default: 3088 return -EOPNOTSUPP; 3089 } 3090 } 3091 3092 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 3093 { 3094 struct fec_enet_private *fep = netdev_priv(dev); 3095 struct fec_enet_priv_rx_q *rxq; 3096 int i, j; 3097 3098 /* Disable MIB statistics counters */ 3099 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 3100 3101 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 3102 writel(0, fep->hwp + fec_stats[i].offset); 3103 3104 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 3105 rxq = fep->rx_queue[i]; 3106 for (j = 0; j < XDP_STATS_TOTAL; j++) 3107 rxq->stats[j] = 0; 3108 } 3109 3110 /* Don't disable MIB statistics counters */ 3111 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 3112 } 3113 3114 #else /* !defined(CONFIG_M5272) */ 3115 #define FEC_STATS_SIZE 0 3116 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 3117 { 3118 } 3119 3120 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 3121 { 3122 } 3123 #endif /* !defined(CONFIG_M5272) */ 3124 3125 /* ITR clock source is enet system clock (clk_ahb). 3126 * TCTT unit is cycle_ns * 64 cycle 3127 * So, the ICTT value = X us / (cycle_ns * 64) 3128 */ 3129 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 3130 { 3131 struct fec_enet_private *fep = netdev_priv(ndev); 3132 3133 return us * (fep->itr_clk_rate / 64000) / 1000; 3134 } 3135 3136 /* Set threshold for interrupt coalescing */ 3137 static void fec_enet_itr_coal_set(struct net_device *ndev) 3138 { 3139 struct fec_enet_private *fep = netdev_priv(ndev); 3140 u32 rx_itr = 0, tx_itr = 0; 3141 int rx_ictt, tx_ictt; 3142 3143 rx_ictt = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); 3144 tx_ictt = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); 3145 3146 if (rx_ictt > 0 && fep->rx_pkts_itr > 1) { 3147 /* Enable with enet system clock as Interrupt Coalescing timer Clock Source */ 3148 rx_itr = FEC_ITR_EN | FEC_ITR_CLK_SEL; 3149 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 3150 rx_itr |= FEC_ITR_ICTT(rx_ictt); 3151 } 3152 3153 if (tx_ictt > 0 && fep->tx_pkts_itr > 1) { 3154 /* Enable with enet system clock as Interrupt Coalescing timer Clock Source */ 3155 tx_itr = FEC_ITR_EN | FEC_ITR_CLK_SEL; 3156 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 3157 tx_itr |= FEC_ITR_ICTT(tx_ictt); 3158 } 3159 3160 writel(tx_itr, fep->hwp + FEC_TXIC0); 3161 writel(rx_itr, fep->hwp + FEC_RXIC0); 3162 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 3163 writel(tx_itr, fep->hwp + FEC_TXIC1); 3164 writel(rx_itr, fep->hwp + FEC_RXIC1); 3165 writel(tx_itr, fep->hwp + FEC_TXIC2); 3166 writel(rx_itr, fep->hwp + FEC_RXIC2); 3167 } 3168 } 3169 3170 static int fec_enet_get_coalesce(struct net_device *ndev, 3171 struct ethtool_coalesce *ec, 3172 struct kernel_ethtool_coalesce *kernel_coal, 3173 struct netlink_ext_ack *extack) 3174 { 3175 struct fec_enet_private *fep = netdev_priv(ndev); 3176 3177 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3178 return -EOPNOTSUPP; 3179 3180 ec->rx_coalesce_usecs = fep->rx_time_itr; 3181 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 3182 3183 ec->tx_coalesce_usecs = fep->tx_time_itr; 3184 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 3185 3186 return 0; 3187 } 3188 3189 static int fec_enet_set_coalesce(struct net_device *ndev, 3190 struct ethtool_coalesce *ec, 3191 struct kernel_ethtool_coalesce *kernel_coal, 3192 struct netlink_ext_ack *extack) 3193 { 3194 struct fec_enet_private *fep = netdev_priv(ndev); 3195 struct device *dev = &fep->pdev->dev; 3196 unsigned int cycle; 3197 3198 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3199 return -EOPNOTSUPP; 3200 3201 if (ec->rx_max_coalesced_frames > 255) { 3202 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 3203 return -EINVAL; 3204 } 3205 3206 if (ec->tx_max_coalesced_frames > 255) { 3207 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 3208 return -EINVAL; 3209 } 3210 3211 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 3212 if (cycle > 0xFFFF) { 3213 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 3214 return -EINVAL; 3215 } 3216 3217 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 3218 if (cycle > 0xFFFF) { 3219 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 3220 return -EINVAL; 3221 } 3222 3223 fep->rx_time_itr = ec->rx_coalesce_usecs; 3224 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 3225 3226 fep->tx_time_itr = ec->tx_coalesce_usecs; 3227 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 3228 3229 fec_enet_itr_coal_set(ndev); 3230 3231 return 0; 3232 } 3233 3234 static int 3235 fec_enet_get_eee(struct net_device *ndev, struct ethtool_keee *edata) 3236 { 3237 struct fec_enet_private *fep = netdev_priv(ndev); 3238 3239 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3240 return -EOPNOTSUPP; 3241 3242 if (!netif_running(ndev)) 3243 return -ENETDOWN; 3244 3245 return phy_ethtool_get_eee(ndev->phydev, edata); 3246 } 3247 3248 static int 3249 fec_enet_set_eee(struct net_device *ndev, struct ethtool_keee *edata) 3250 { 3251 struct fec_enet_private *fep = netdev_priv(ndev); 3252 3253 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3254 return -EOPNOTSUPP; 3255 3256 if (!netif_running(ndev)) 3257 return -ENETDOWN; 3258 3259 return phy_ethtool_set_eee(ndev->phydev, edata); 3260 } 3261 3262 static void 3263 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3264 { 3265 struct fec_enet_private *fep = netdev_priv(ndev); 3266 3267 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 3268 wol->supported = WAKE_MAGIC; 3269 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 3270 } else { 3271 wol->supported = wol->wolopts = 0; 3272 } 3273 } 3274 3275 static int 3276 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3277 { 3278 struct fec_enet_private *fep = netdev_priv(ndev); 3279 3280 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 3281 return -EINVAL; 3282 3283 if (wol->wolopts & ~WAKE_MAGIC) 3284 return -EINVAL; 3285 3286 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 3287 if (device_may_wakeup(&ndev->dev)) 3288 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 3289 else 3290 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 3291 3292 return 0; 3293 } 3294 3295 static const struct ethtool_ops fec_enet_ethtool_ops = { 3296 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3297 ETHTOOL_COALESCE_MAX_FRAMES, 3298 .get_drvinfo = fec_enet_get_drvinfo, 3299 .get_regs_len = fec_enet_get_regs_len, 3300 .get_regs = fec_enet_get_regs, 3301 .nway_reset = phy_ethtool_nway_reset, 3302 .get_link = ethtool_op_get_link, 3303 .get_coalesce = fec_enet_get_coalesce, 3304 .set_coalesce = fec_enet_set_coalesce, 3305 #ifndef CONFIG_M5272 3306 .get_pauseparam = fec_enet_get_pauseparam, 3307 .set_pauseparam = fec_enet_set_pauseparam, 3308 .get_strings = fec_enet_get_strings, 3309 .get_ethtool_stats = fec_enet_get_ethtool_stats, 3310 .get_sset_count = fec_enet_get_sset_count, 3311 #endif 3312 .get_ts_info = fec_enet_get_ts_info, 3313 .get_wol = fec_enet_get_wol, 3314 .set_wol = fec_enet_set_wol, 3315 .get_eee = fec_enet_get_eee, 3316 .set_eee = fec_enet_set_eee, 3317 .get_link_ksettings = phy_ethtool_get_link_ksettings, 3318 .set_link_ksettings = phy_ethtool_set_link_ksettings, 3319 .self_test = net_selftest, 3320 }; 3321 3322 static void fec_enet_free_buffers(struct net_device *ndev) 3323 { 3324 struct fec_enet_private *fep = netdev_priv(ndev); 3325 unsigned int i; 3326 struct fec_enet_priv_tx_q *txq; 3327 struct fec_enet_priv_rx_q *rxq; 3328 unsigned int q; 3329 3330 for (q = 0; q < fep->num_rx_queues; q++) { 3331 rxq = fep->rx_queue[q]; 3332 for (i = 0; i < rxq->bd.ring_size; i++) 3333 page_pool_put_full_page(rxq->page_pool, rxq->rx_skb_info[i].page, false); 3334 3335 for (i = 0; i < XDP_STATS_TOTAL; i++) 3336 rxq->stats[i] = 0; 3337 3338 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 3339 xdp_rxq_info_unreg(&rxq->xdp_rxq); 3340 page_pool_destroy(rxq->page_pool); 3341 rxq->page_pool = NULL; 3342 } 3343 3344 for (q = 0; q < fep->num_tx_queues; q++) { 3345 txq = fep->tx_queue[q]; 3346 for (i = 0; i < txq->bd.ring_size; i++) { 3347 kfree(txq->tx_bounce[i]); 3348 txq->tx_bounce[i] = NULL; 3349 3350 if (!txq->tx_buf[i].buf_p) { 3351 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3352 continue; 3353 } 3354 3355 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 3356 dev_kfree_skb(txq->tx_buf[i].buf_p); 3357 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 3358 xdp_return_frame(txq->tx_buf[i].buf_p); 3359 } else { 3360 struct page *page = txq->tx_buf[i].buf_p; 3361 3362 page_pool_put_page(pp_page_to_nmdesc(page)->pp, 3363 page, 0, false); 3364 } 3365 3366 txq->tx_buf[i].buf_p = NULL; 3367 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3368 } 3369 } 3370 } 3371 3372 static void fec_enet_free_queue(struct net_device *ndev) 3373 { 3374 struct fec_enet_private *fep = netdev_priv(ndev); 3375 int i; 3376 struct fec_enet_priv_tx_q *txq; 3377 3378 for (i = 0; i < fep->num_tx_queues; i++) 3379 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 3380 txq = fep->tx_queue[i]; 3381 fec_dma_free(&fep->pdev->dev, 3382 txq->bd.ring_size * TSO_HEADER_SIZE, 3383 txq->tso_hdrs, txq->tso_hdrs_dma); 3384 } 3385 3386 for (i = 0; i < fep->num_rx_queues; i++) 3387 kfree(fep->rx_queue[i]); 3388 for (i = 0; i < fep->num_tx_queues; i++) 3389 kfree(fep->tx_queue[i]); 3390 } 3391 3392 static int fec_enet_alloc_queue(struct net_device *ndev) 3393 { 3394 struct fec_enet_private *fep = netdev_priv(ndev); 3395 int i; 3396 int ret = 0; 3397 struct fec_enet_priv_tx_q *txq; 3398 3399 for (i = 0; i < fep->num_tx_queues; i++) { 3400 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 3401 if (!txq) { 3402 ret = -ENOMEM; 3403 goto alloc_failed; 3404 } 3405 3406 fep->tx_queue[i] = txq; 3407 txq->bd.ring_size = TX_RING_SIZE; 3408 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 3409 3410 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 3411 txq->tx_wake_threshold = FEC_MAX_SKB_DESCS + 2 * MAX_SKB_FRAGS; 3412 3413 txq->tso_hdrs = fec_dma_alloc(&fep->pdev->dev, 3414 txq->bd.ring_size * TSO_HEADER_SIZE, 3415 &txq->tso_hdrs_dma, GFP_KERNEL); 3416 if (!txq->tso_hdrs) { 3417 ret = -ENOMEM; 3418 goto alloc_failed; 3419 } 3420 } 3421 3422 for (i = 0; i < fep->num_rx_queues; i++) { 3423 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 3424 GFP_KERNEL); 3425 if (!fep->rx_queue[i]) { 3426 ret = -ENOMEM; 3427 goto alloc_failed; 3428 } 3429 3430 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 3431 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 3432 } 3433 return ret; 3434 3435 alloc_failed: 3436 fec_enet_free_queue(ndev); 3437 return ret; 3438 } 3439 3440 static int 3441 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 3442 { 3443 struct fec_enet_private *fep = netdev_priv(ndev); 3444 struct fec_enet_priv_rx_q *rxq; 3445 dma_addr_t phys_addr; 3446 struct bufdesc *bdp; 3447 struct page *page; 3448 int i, err; 3449 3450 rxq = fep->rx_queue[queue]; 3451 bdp = rxq->bd.base; 3452 3453 err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size); 3454 if (err < 0) { 3455 netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err); 3456 return err; 3457 } 3458 3459 for (i = 0; i < rxq->bd.ring_size; i++) { 3460 page = page_pool_dev_alloc_pages(rxq->page_pool); 3461 if (!page) 3462 goto err_alloc; 3463 3464 phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM; 3465 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 3466 3467 rxq->rx_skb_info[i].page = page; 3468 rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM; 3469 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3470 3471 if (fep->bufdesc_ex) { 3472 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3473 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 3474 } 3475 3476 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3477 } 3478 3479 /* Set the last buffer to wrap. */ 3480 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3481 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3482 return 0; 3483 3484 err_alloc: 3485 fec_enet_free_buffers(ndev); 3486 return -ENOMEM; 3487 } 3488 3489 static int 3490 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 3491 { 3492 struct fec_enet_private *fep = netdev_priv(ndev); 3493 unsigned int i; 3494 struct bufdesc *bdp; 3495 struct fec_enet_priv_tx_q *txq; 3496 3497 txq = fep->tx_queue[queue]; 3498 bdp = txq->bd.base; 3499 for (i = 0; i < txq->bd.ring_size; i++) { 3500 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 3501 if (!txq->tx_bounce[i]) 3502 goto err_alloc; 3503 3504 bdp->cbd_sc = cpu_to_fec16(0); 3505 bdp->cbd_bufaddr = cpu_to_fec32(0); 3506 3507 if (fep->bufdesc_ex) { 3508 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3509 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 3510 } 3511 3512 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3513 } 3514 3515 /* Set the last buffer to wrap. */ 3516 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3517 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3518 3519 return 0; 3520 3521 err_alloc: 3522 fec_enet_free_buffers(ndev); 3523 return -ENOMEM; 3524 } 3525 3526 static int fec_enet_alloc_buffers(struct net_device *ndev) 3527 { 3528 struct fec_enet_private *fep = netdev_priv(ndev); 3529 unsigned int i; 3530 3531 for (i = 0; i < fep->num_rx_queues; i++) 3532 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3533 return -ENOMEM; 3534 3535 for (i = 0; i < fep->num_tx_queues; i++) 3536 if (fec_enet_alloc_txq_buffers(ndev, i)) 3537 return -ENOMEM; 3538 return 0; 3539 } 3540 3541 static int 3542 fec_enet_open(struct net_device *ndev) 3543 { 3544 struct fec_enet_private *fep = netdev_priv(ndev); 3545 int ret; 3546 bool reset_again; 3547 3548 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3549 if (ret < 0) 3550 return ret; 3551 3552 pinctrl_pm_select_default_state(&fep->pdev->dev); 3553 ret = fec_enet_clk_enable(ndev, true); 3554 if (ret) 3555 goto clk_enable; 3556 3557 /* During the first fec_enet_open call the PHY isn't probed at this 3558 * point. Therefore the phy_reset_after_clk_enable() call within 3559 * fec_enet_clk_enable() fails. As we need this reset in order to be 3560 * sure the PHY is working correctly we check if we need to reset again 3561 * later when the PHY is probed 3562 */ 3563 if (ndev->phydev && ndev->phydev->drv) 3564 reset_again = false; 3565 else 3566 reset_again = true; 3567 3568 /* I should reset the ring buffers here, but I don't yet know 3569 * a simple way to do that. 3570 */ 3571 3572 ret = fec_enet_alloc_buffers(ndev); 3573 if (ret) 3574 goto err_enet_alloc; 3575 3576 /* Init MAC prior to mii bus probe */ 3577 fec_restart(ndev); 3578 3579 /* Call phy_reset_after_clk_enable() again if it failed during 3580 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3581 */ 3582 if (reset_again) 3583 fec_enet_phy_reset_after_clk_enable(ndev); 3584 3585 /* Probe and connect to PHY when open the interface */ 3586 ret = fec_enet_mii_probe(ndev); 3587 if (ret) 3588 goto err_enet_mii_probe; 3589 3590 if (fep->quirks & FEC_QUIRK_ERR006687) 3591 imx6q_cpuidle_fec_irqs_used(); 3592 3593 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3594 cpu_latency_qos_add_request(&fep->pm_qos_req, 0); 3595 3596 napi_enable(&fep->napi); 3597 phy_start(ndev->phydev); 3598 netif_tx_start_all_queues(ndev); 3599 3600 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3601 FEC_WOL_FLAG_ENABLE); 3602 3603 return 0; 3604 3605 err_enet_mii_probe: 3606 fec_enet_free_buffers(ndev); 3607 err_enet_alloc: 3608 fec_enet_clk_enable(ndev, false); 3609 clk_enable: 3610 pm_runtime_put_autosuspend(&fep->pdev->dev); 3611 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3612 return ret; 3613 } 3614 3615 static int 3616 fec_enet_close(struct net_device *ndev) 3617 { 3618 struct fec_enet_private *fep = netdev_priv(ndev); 3619 3620 phy_stop(ndev->phydev); 3621 3622 if (netif_device_present(ndev)) { 3623 napi_disable(&fep->napi); 3624 netif_tx_disable(ndev); 3625 fec_stop(ndev); 3626 } 3627 3628 phy_disconnect(ndev->phydev); 3629 3630 if (fep->quirks & FEC_QUIRK_ERR006687) 3631 imx6q_cpuidle_fec_irqs_unused(); 3632 3633 fec_enet_update_ethtool_stats(ndev); 3634 3635 fec_enet_clk_enable(ndev, false); 3636 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3637 cpu_latency_qos_remove_request(&fep->pm_qos_req); 3638 3639 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3640 pm_runtime_put_autosuspend(&fep->pdev->dev); 3641 3642 fec_enet_free_buffers(ndev); 3643 3644 return 0; 3645 } 3646 3647 /* Set or clear the multicast filter for this adaptor. 3648 * Skeleton taken from sunlance driver. 3649 * The CPM Ethernet implementation allows Multicast as well as individual 3650 * MAC address filtering. Some of the drivers check to make sure it is 3651 * a group multicast address, and discard those that are not. I guess I 3652 * will do the same for now, but just remove the test if you want 3653 * individual filtering as well (do the upper net layers want or support 3654 * this kind of feature?). 3655 */ 3656 3657 #define FEC_HASH_BITS 6 /* #bits in hash */ 3658 3659 static void set_multicast_list(struct net_device *ndev) 3660 { 3661 struct fec_enet_private *fep = netdev_priv(ndev); 3662 struct netdev_hw_addr *ha; 3663 unsigned int crc, tmp; 3664 unsigned char hash; 3665 unsigned int hash_high = 0, hash_low = 0; 3666 3667 if (ndev->flags & IFF_PROMISC) { 3668 tmp = readl(fep->hwp + FEC_R_CNTRL); 3669 tmp |= 0x8; 3670 writel(tmp, fep->hwp + FEC_R_CNTRL); 3671 return; 3672 } 3673 3674 tmp = readl(fep->hwp + FEC_R_CNTRL); 3675 tmp &= ~0x8; 3676 writel(tmp, fep->hwp + FEC_R_CNTRL); 3677 3678 if (ndev->flags & IFF_ALLMULTI) { 3679 /* Catch all multicast addresses, so set the 3680 * filter to all 1's 3681 */ 3682 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3683 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3684 3685 return; 3686 } 3687 3688 /* Add the addresses in hash register */ 3689 netdev_for_each_mc_addr(ha, ndev) { 3690 /* calculate crc32 value of mac address */ 3691 crc = ether_crc_le(ndev->addr_len, ha->addr); 3692 3693 /* only upper 6 bits (FEC_HASH_BITS) are used 3694 * which point to specific bit in the hash registers 3695 */ 3696 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3697 3698 if (hash > 31) 3699 hash_high |= 1 << (hash - 32); 3700 else 3701 hash_low |= 1 << hash; 3702 } 3703 3704 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3705 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3706 } 3707 3708 /* Set a MAC change in hardware. */ 3709 static int 3710 fec_set_mac_address(struct net_device *ndev, void *p) 3711 { 3712 struct sockaddr *addr = p; 3713 3714 if (addr) { 3715 if (!is_valid_ether_addr(addr->sa_data)) 3716 return -EADDRNOTAVAIL; 3717 eth_hw_addr_set(ndev, addr->sa_data); 3718 } 3719 3720 /* Add netif status check here to avoid system hang in below case: 3721 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3722 * After ethx down, fec all clocks are gated off and then register 3723 * access causes system hang. 3724 */ 3725 if (!netif_running(ndev)) 3726 return 0; 3727 3728 fec_set_hw_mac_addr(ndev); 3729 3730 return 0; 3731 } 3732 3733 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3734 netdev_features_t features) 3735 { 3736 struct fec_enet_private *fep = netdev_priv(netdev); 3737 netdev_features_t changed = features ^ netdev->features; 3738 3739 netdev->features = features; 3740 3741 /* Receive checksum has been changed */ 3742 if (changed & NETIF_F_RXCSUM) { 3743 if (features & NETIF_F_RXCSUM) 3744 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3745 else 3746 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3747 } 3748 } 3749 3750 static int fec_set_features(struct net_device *netdev, 3751 netdev_features_t features) 3752 { 3753 struct fec_enet_private *fep = netdev_priv(netdev); 3754 netdev_features_t changed = features ^ netdev->features; 3755 3756 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3757 napi_disable(&fep->napi); 3758 netif_tx_lock_bh(netdev); 3759 fec_stop(netdev); 3760 fec_enet_set_netdev_features(netdev, features); 3761 fec_restart(netdev); 3762 netif_tx_wake_all_queues(netdev); 3763 netif_tx_unlock_bh(netdev); 3764 napi_enable(&fep->napi); 3765 } else { 3766 fec_enet_set_netdev_features(netdev, features); 3767 } 3768 3769 return 0; 3770 } 3771 3772 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3773 struct net_device *sb_dev) 3774 { 3775 struct fec_enet_private *fep = netdev_priv(ndev); 3776 u16 vlan_tag = 0; 3777 3778 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3779 return netdev_pick_tx(ndev, skb, NULL); 3780 3781 /* VLAN is present in the payload.*/ 3782 if (eth_type_vlan(skb->protocol)) { 3783 struct vlan_ethhdr *vhdr = skb_vlan_eth_hdr(skb); 3784 3785 vlan_tag = ntohs(vhdr->h_vlan_TCI); 3786 /* VLAN is present in the skb but not yet pushed in the payload.*/ 3787 } else if (skb_vlan_tag_present(skb)) { 3788 vlan_tag = skb->vlan_tci; 3789 } else { 3790 return vlan_tag; 3791 } 3792 3793 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3794 } 3795 3796 static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf) 3797 { 3798 struct fec_enet_private *fep = netdev_priv(dev); 3799 bool is_run = netif_running(dev); 3800 struct bpf_prog *old_prog; 3801 3802 switch (bpf->command) { 3803 case XDP_SETUP_PROG: 3804 /* No need to support the SoCs that require to 3805 * do the frame swap because the performance wouldn't be 3806 * better than the skb mode. 3807 */ 3808 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 3809 return -EOPNOTSUPP; 3810 3811 if (!bpf->prog) 3812 xdp_features_clear_redirect_target(dev); 3813 3814 if (is_run) { 3815 napi_disable(&fep->napi); 3816 netif_tx_disable(dev); 3817 } 3818 3819 old_prog = xchg(&fep->xdp_prog, bpf->prog); 3820 if (old_prog) 3821 bpf_prog_put(old_prog); 3822 3823 fec_restart(dev); 3824 3825 if (is_run) { 3826 napi_enable(&fep->napi); 3827 netif_tx_start_all_queues(dev); 3828 } 3829 3830 if (bpf->prog) 3831 xdp_features_set_redirect_target(dev, false); 3832 3833 return 0; 3834 3835 case XDP_SETUP_XSK_POOL: 3836 return -EOPNOTSUPP; 3837 3838 default: 3839 return -EOPNOTSUPP; 3840 } 3841 } 3842 3843 static int 3844 fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index) 3845 { 3846 if (unlikely(index < 0)) 3847 return 0; 3848 3849 return (index % fep->num_tx_queues); 3850 } 3851 3852 static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep, 3853 struct fec_enet_priv_tx_q *txq, 3854 void *frame, u32 dma_sync_len, 3855 bool ndo_xmit) 3856 { 3857 unsigned int index, status, estatus; 3858 struct bufdesc *bdp; 3859 dma_addr_t dma_addr; 3860 int entries_free; 3861 u16 frame_len; 3862 3863 entries_free = fec_enet_get_free_txdesc_num(txq); 3864 if (entries_free < MAX_SKB_FRAGS + 1) { 3865 netdev_err_once(fep->netdev, "NOT enough BD for SG!\n"); 3866 return -EBUSY; 3867 } 3868 3869 /* Fill in a Tx ring entry */ 3870 bdp = txq->bd.cur; 3871 status = fec16_to_cpu(bdp->cbd_sc); 3872 status &= ~BD_ENET_TX_STATS; 3873 3874 index = fec_enet_get_bd_index(bdp, &txq->bd); 3875 3876 if (ndo_xmit) { 3877 struct xdp_frame *xdpf = frame; 3878 3879 dma_addr = dma_map_single(&fep->pdev->dev, xdpf->data, 3880 xdpf->len, DMA_TO_DEVICE); 3881 if (dma_mapping_error(&fep->pdev->dev, dma_addr)) 3882 return -ENOMEM; 3883 3884 frame_len = xdpf->len; 3885 txq->tx_buf[index].buf_p = xdpf; 3886 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_NDO; 3887 } else { 3888 struct xdp_buff *xdpb = frame; 3889 struct page *page; 3890 3891 page = virt_to_page(xdpb->data); 3892 dma_addr = page_pool_get_dma_addr(page) + 3893 (xdpb->data - xdpb->data_hard_start); 3894 dma_sync_single_for_device(&fep->pdev->dev, dma_addr, 3895 dma_sync_len, DMA_BIDIRECTIONAL); 3896 frame_len = xdpb->data_end - xdpb->data; 3897 txq->tx_buf[index].buf_p = page; 3898 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_TX; 3899 } 3900 3901 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 3902 if (fep->bufdesc_ex) 3903 estatus = BD_ENET_TX_INT; 3904 3905 bdp->cbd_bufaddr = cpu_to_fec32(dma_addr); 3906 bdp->cbd_datlen = cpu_to_fec16(frame_len); 3907 3908 if (fep->bufdesc_ex) { 3909 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3910 3911 if (fep->quirks & FEC_QUIRK_HAS_AVB) 3912 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 3913 3914 ebdp->cbd_bdu = 0; 3915 ebdp->cbd_esc = cpu_to_fec32(estatus); 3916 } 3917 3918 /* Make sure the updates to rest of the descriptor are performed before 3919 * transferring ownership. 3920 */ 3921 dma_wmb(); 3922 3923 /* Send it on its way. Tell FEC it's ready, interrupt when done, 3924 * it's the last BD of the frame, and to put the CRC on the end. 3925 */ 3926 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 3927 bdp->cbd_sc = cpu_to_fec16(status); 3928 3929 /* If this was the last BD in the ring, start at the beginning again. */ 3930 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3931 3932 /* Make sure the update to bdp are performed before txq->bd.cur. */ 3933 dma_wmb(); 3934 3935 txq->bd.cur = bdp; 3936 3937 /* Trigger transmission start */ 3938 writel(0, txq->bd.reg_desc_active); 3939 3940 return 0; 3941 } 3942 3943 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 3944 int cpu, struct xdp_buff *xdp, 3945 u32 dma_sync_len) 3946 { 3947 struct fec_enet_priv_tx_q *txq; 3948 struct netdev_queue *nq; 3949 int queue, ret; 3950 3951 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3952 txq = fep->tx_queue[queue]; 3953 nq = netdev_get_tx_queue(fep->netdev, queue); 3954 3955 __netif_tx_lock(nq, cpu); 3956 3957 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3958 txq_trans_cond_update(nq); 3959 ret = fec_enet_txq_xmit_frame(fep, txq, xdp, dma_sync_len, false); 3960 3961 __netif_tx_unlock(nq); 3962 3963 return ret; 3964 } 3965 3966 static int fec_enet_xdp_xmit(struct net_device *dev, 3967 int num_frames, 3968 struct xdp_frame **frames, 3969 u32 flags) 3970 { 3971 struct fec_enet_private *fep = netdev_priv(dev); 3972 struct fec_enet_priv_tx_q *txq; 3973 int cpu = smp_processor_id(); 3974 unsigned int sent_frames = 0; 3975 struct netdev_queue *nq; 3976 unsigned int queue; 3977 int i; 3978 3979 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3980 txq = fep->tx_queue[queue]; 3981 nq = netdev_get_tx_queue(fep->netdev, queue); 3982 3983 __netif_tx_lock(nq, cpu); 3984 3985 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3986 txq_trans_cond_update(nq); 3987 for (i = 0; i < num_frames; i++) { 3988 if (fec_enet_txq_xmit_frame(fep, txq, frames[i], 0, true) < 0) 3989 break; 3990 sent_frames++; 3991 } 3992 3993 __netif_tx_unlock(nq); 3994 3995 return sent_frames; 3996 } 3997 3998 static int fec_hwtstamp_get(struct net_device *ndev, 3999 struct kernel_hwtstamp_config *config) 4000 { 4001 struct fec_enet_private *fep = netdev_priv(ndev); 4002 4003 if (!netif_running(ndev)) 4004 return -EINVAL; 4005 4006 if (!fep->bufdesc_ex) 4007 return -EOPNOTSUPP; 4008 4009 fec_ptp_get(ndev, config); 4010 4011 return 0; 4012 } 4013 4014 static int fec_hwtstamp_set(struct net_device *ndev, 4015 struct kernel_hwtstamp_config *config, 4016 struct netlink_ext_ack *extack) 4017 { 4018 struct fec_enet_private *fep = netdev_priv(ndev); 4019 4020 if (!netif_running(ndev)) 4021 return -EINVAL; 4022 4023 if (!fep->bufdesc_ex) 4024 return -EOPNOTSUPP; 4025 4026 return fec_ptp_set(ndev, config, extack); 4027 } 4028 4029 static int fec_change_mtu(struct net_device *ndev, int new_mtu) 4030 { 4031 struct fec_enet_private *fep = netdev_priv(ndev); 4032 int order; 4033 4034 if (netif_running(ndev)) 4035 return -EBUSY; 4036 4037 order = get_order(new_mtu + ETH_HLEN + ETH_FCS_LEN 4038 + FEC_DRV_RESERVE_SPACE); 4039 fep->rx_frame_size = (PAGE_SIZE << order) - FEC_DRV_RESERVE_SPACE; 4040 fep->pagepool_order = order; 4041 WRITE_ONCE(ndev->mtu, new_mtu); 4042 4043 return 0; 4044 } 4045 4046 static const struct net_device_ops fec_netdev_ops = { 4047 .ndo_open = fec_enet_open, 4048 .ndo_stop = fec_enet_close, 4049 .ndo_start_xmit = fec_enet_start_xmit, 4050 .ndo_select_queue = fec_enet_select_queue, 4051 .ndo_set_rx_mode = set_multicast_list, 4052 .ndo_validate_addr = eth_validate_addr, 4053 .ndo_tx_timeout = fec_timeout, 4054 .ndo_set_mac_address = fec_set_mac_address, 4055 .ndo_change_mtu = fec_change_mtu, 4056 .ndo_eth_ioctl = phy_do_ioctl_running, 4057 .ndo_set_features = fec_set_features, 4058 .ndo_bpf = fec_enet_bpf, 4059 .ndo_xdp_xmit = fec_enet_xdp_xmit, 4060 .ndo_hwtstamp_get = fec_hwtstamp_get, 4061 .ndo_hwtstamp_set = fec_hwtstamp_set, 4062 }; 4063 4064 static const unsigned short offset_des_active_rxq[] = { 4065 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 4066 }; 4067 4068 static const unsigned short offset_des_active_txq[] = { 4069 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 4070 }; 4071 4072 /* 4073 * XXX: We need to clean up on failure exits here. 4074 * 4075 */ 4076 static int fec_enet_init(struct net_device *ndev) 4077 { 4078 struct fec_enet_private *fep = netdev_priv(ndev); 4079 struct bufdesc *cbd_base; 4080 dma_addr_t bd_dma; 4081 int bd_size; 4082 unsigned int i; 4083 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 4084 sizeof(struct bufdesc); 4085 unsigned dsize_log2 = __fls(dsize); 4086 int ret; 4087 4088 WARN_ON(dsize != (1 << dsize_log2)); 4089 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 4090 fep->rx_align = 0xf; 4091 fep->tx_align = 0xf; 4092 #else 4093 fep->rx_align = 0x3; 4094 fep->tx_align = 0x3; 4095 #endif 4096 fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4097 fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4098 fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT; 4099 fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT; 4100 4101 /* Check mask of the streaming and coherent API */ 4102 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 4103 if (ret < 0) { 4104 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 4105 return ret; 4106 } 4107 4108 ret = fec_enet_alloc_queue(ndev); 4109 if (ret) 4110 return ret; 4111 4112 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 4113 4114 /* Allocate memory for buffer descriptors. */ 4115 cbd_base = fec_dmam_alloc(&fep->pdev->dev, bd_size, &bd_dma, 4116 GFP_KERNEL); 4117 if (!cbd_base) { 4118 ret = -ENOMEM; 4119 goto free_queue_mem; 4120 } 4121 4122 /* Get the Ethernet address */ 4123 ret = fec_get_mac(ndev); 4124 if (ret) 4125 goto free_queue_mem; 4126 4127 /* Set receive and transmit descriptor base. */ 4128 for (i = 0; i < fep->num_rx_queues; i++) { 4129 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 4130 unsigned size = dsize * rxq->bd.ring_size; 4131 4132 rxq->bd.qid = i; 4133 rxq->bd.base = cbd_base; 4134 rxq->bd.cur = cbd_base; 4135 rxq->bd.dma = bd_dma; 4136 rxq->bd.dsize = dsize; 4137 rxq->bd.dsize_log2 = dsize_log2; 4138 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 4139 bd_dma += size; 4140 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4141 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4142 } 4143 4144 for (i = 0; i < fep->num_tx_queues; i++) { 4145 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 4146 unsigned size = dsize * txq->bd.ring_size; 4147 4148 txq->bd.qid = i; 4149 txq->bd.base = cbd_base; 4150 txq->bd.cur = cbd_base; 4151 txq->bd.dma = bd_dma; 4152 txq->bd.dsize = dsize; 4153 txq->bd.dsize_log2 = dsize_log2; 4154 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 4155 bd_dma += size; 4156 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4157 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4158 } 4159 4160 4161 /* The FEC Ethernet specific entries in the device structure */ 4162 ndev->watchdog_timeo = TX_TIMEOUT; 4163 ndev->netdev_ops = &fec_netdev_ops; 4164 ndev->ethtool_ops = &fec_enet_ethtool_ops; 4165 4166 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 4167 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi); 4168 4169 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 4170 /* enable hw VLAN support */ 4171 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 4172 4173 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 4174 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS); 4175 4176 /* enable hw accelerator */ 4177 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 4178 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 4179 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 4180 } 4181 4182 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 4183 fep->tx_align = 0; 4184 fep->rx_align = 0x3f; 4185 } 4186 4187 ndev->hw_features = ndev->features; 4188 4189 if (!(fep->quirks & FEC_QUIRK_SWAP_FRAME)) 4190 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 4191 NETDEV_XDP_ACT_REDIRECT; 4192 4193 fec_restart(ndev); 4194 4195 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 4196 fec_enet_clear_ethtool_stats(ndev); 4197 else 4198 fec_enet_update_ethtool_stats(ndev); 4199 4200 return 0; 4201 4202 free_queue_mem: 4203 fec_enet_free_queue(ndev); 4204 return ret; 4205 } 4206 4207 static void fec_enet_deinit(struct net_device *ndev) 4208 { 4209 struct fec_enet_private *fep = netdev_priv(ndev); 4210 4211 netif_napi_del(&fep->napi); 4212 fec_enet_free_queue(ndev); 4213 } 4214 4215 #ifdef CONFIG_OF 4216 static int fec_reset_phy(struct platform_device *pdev) 4217 { 4218 struct gpio_desc *phy_reset; 4219 int msec = 1, phy_post_delay = 0; 4220 struct device_node *np = pdev->dev.of_node; 4221 int err; 4222 4223 if (!np) 4224 return 0; 4225 4226 err = of_property_read_u32(np, "phy-reset-duration", &msec); 4227 /* A sane reset duration should not be longer than 1s */ 4228 if (!err && msec > 1000) 4229 msec = 1; 4230 4231 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 4232 /* valid reset duration should be less than 1s */ 4233 if (!err && phy_post_delay > 1000) 4234 return -EINVAL; 4235 4236 phy_reset = devm_gpiod_get_optional(&pdev->dev, "phy-reset", 4237 GPIOD_OUT_HIGH); 4238 if (IS_ERR(phy_reset)) 4239 return dev_err_probe(&pdev->dev, PTR_ERR(phy_reset), 4240 "failed to get phy-reset-gpios\n"); 4241 4242 if (!phy_reset) 4243 return 0; 4244 4245 if (msec > 20) 4246 msleep(msec); 4247 else 4248 usleep_range(msec * 1000, msec * 1000 + 1000); 4249 4250 gpiod_set_value_cansleep(phy_reset, 0); 4251 4252 if (!phy_post_delay) 4253 return 0; 4254 4255 if (phy_post_delay > 20) 4256 msleep(phy_post_delay); 4257 else 4258 usleep_range(phy_post_delay * 1000, 4259 phy_post_delay * 1000 + 1000); 4260 4261 return 0; 4262 } 4263 #else /* CONFIG_OF */ 4264 static int fec_reset_phy(struct platform_device *pdev) 4265 { 4266 /* 4267 * In case of platform probe, the reset has been done 4268 * by machine code. 4269 */ 4270 return 0; 4271 } 4272 #endif /* CONFIG_OF */ 4273 4274 static void 4275 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 4276 { 4277 struct device_node *np = pdev->dev.of_node; 4278 4279 *num_tx = *num_rx = 1; 4280 4281 if (!np || !of_device_is_available(np)) 4282 return; 4283 4284 /* parse the num of tx and rx queues */ 4285 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 4286 4287 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 4288 4289 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 4290 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 4291 *num_tx); 4292 *num_tx = 1; 4293 return; 4294 } 4295 4296 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 4297 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 4298 *num_rx); 4299 *num_rx = 1; 4300 return; 4301 } 4302 4303 } 4304 4305 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 4306 { 4307 int irq_cnt = platform_irq_count(pdev); 4308 4309 if (irq_cnt > FEC_IRQ_NUM) 4310 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 4311 else if (irq_cnt == 2) 4312 irq_cnt = 1; /* last for pps */ 4313 else if (irq_cnt <= 0) 4314 irq_cnt = 1; /* At least 1 irq is needed */ 4315 return irq_cnt; 4316 } 4317 4318 static void fec_enet_get_wakeup_irq(struct platform_device *pdev) 4319 { 4320 struct net_device *ndev = platform_get_drvdata(pdev); 4321 struct fec_enet_private *fep = netdev_priv(ndev); 4322 4323 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) 4324 fep->wake_irq = fep->irq[2]; 4325 else 4326 fep->wake_irq = fep->irq[0]; 4327 } 4328 4329 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 4330 struct device_node *np) 4331 { 4332 struct device_node *gpr_np; 4333 u32 out_val[3]; 4334 int ret = 0; 4335 4336 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 4337 if (!gpr_np) 4338 return 0; 4339 4340 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 4341 ARRAY_SIZE(out_val)); 4342 if (ret) { 4343 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 4344 goto out; 4345 } 4346 4347 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 4348 if (IS_ERR(fep->stop_gpr.gpr)) { 4349 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 4350 ret = PTR_ERR(fep->stop_gpr.gpr); 4351 fep->stop_gpr.gpr = NULL; 4352 goto out; 4353 } 4354 4355 fep->stop_gpr.reg = out_val[1]; 4356 fep->stop_gpr.bit = out_val[2]; 4357 4358 out: 4359 of_node_put(gpr_np); 4360 4361 return ret; 4362 } 4363 4364 static int 4365 fec_probe(struct platform_device *pdev) 4366 { 4367 struct fec_enet_private *fep; 4368 struct fec_platform_data *pdata; 4369 phy_interface_t interface; 4370 struct net_device *ndev; 4371 int i, irq, ret = 0; 4372 static int dev_id; 4373 struct device_node *np = pdev->dev.of_node, *phy_node; 4374 int num_tx_qs; 4375 int num_rx_qs; 4376 char irq_name[8]; 4377 int irq_cnt; 4378 const struct fec_devinfo *dev_info; 4379 4380 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 4381 4382 /* Init network device */ 4383 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 4384 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 4385 if (!ndev) 4386 return -ENOMEM; 4387 4388 SET_NETDEV_DEV(ndev, &pdev->dev); 4389 4390 /* setup board info structure */ 4391 fep = netdev_priv(ndev); 4392 4393 dev_info = device_get_match_data(&pdev->dev); 4394 if (!dev_info) 4395 dev_info = (const struct fec_devinfo *)pdev->id_entry->driver_data; 4396 if (dev_info) 4397 fep->quirks = dev_info->quirks; 4398 4399 fep->netdev = ndev; 4400 fep->num_rx_queues = num_rx_qs; 4401 fep->num_tx_queues = num_tx_qs; 4402 4403 #if !defined(CONFIG_M5272) 4404 /* default enable pause frame auto negotiation */ 4405 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 4406 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 4407 #endif 4408 4409 /* Select default pin state */ 4410 pinctrl_pm_select_default_state(&pdev->dev); 4411 4412 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 4413 if (IS_ERR(fep->hwp)) { 4414 ret = PTR_ERR(fep->hwp); 4415 goto failed_ioremap; 4416 } 4417 4418 fep->pdev = pdev; 4419 fep->dev_id = dev_id++; 4420 4421 platform_set_drvdata(pdev, ndev); 4422 4423 if ((of_machine_is_compatible("fsl,imx6q") || 4424 of_machine_is_compatible("fsl,imx6dl")) && 4425 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 4426 fep->quirks |= FEC_QUIRK_ERR006687; 4427 4428 ret = fec_enet_ipc_handle_init(fep); 4429 if (ret) 4430 goto failed_ipc_init; 4431 4432 if (of_property_read_bool(np, "fsl,magic-packet")) 4433 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 4434 4435 ret = fec_enet_init_stop_mode(fep, np); 4436 if (ret) 4437 goto failed_stop_mode; 4438 4439 phy_node = of_parse_phandle(np, "phy-handle", 0); 4440 if (!phy_node && of_phy_is_fixed_link(np)) { 4441 ret = of_phy_register_fixed_link(np); 4442 if (ret < 0) { 4443 dev_err(&pdev->dev, 4444 "broken fixed-link specification\n"); 4445 goto failed_phy; 4446 } 4447 phy_node = of_node_get(np); 4448 } 4449 fep->phy_node = phy_node; 4450 4451 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 4452 if (ret) { 4453 pdata = dev_get_platdata(&pdev->dev); 4454 if (pdata) 4455 fep->phy_interface = pdata->phy; 4456 else 4457 fep->phy_interface = PHY_INTERFACE_MODE_MII; 4458 } else { 4459 fep->phy_interface = interface; 4460 } 4461 4462 ret = fec_enet_parse_rgmii_delay(fep, np); 4463 if (ret) 4464 goto failed_rgmii_delay; 4465 4466 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 4467 if (IS_ERR(fep->clk_ipg)) { 4468 ret = PTR_ERR(fep->clk_ipg); 4469 goto failed_clk; 4470 } 4471 4472 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 4473 if (IS_ERR(fep->clk_ahb)) { 4474 ret = PTR_ERR(fep->clk_ahb); 4475 goto failed_clk; 4476 } 4477 4478 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 4479 4480 /* enet_out is optional, depends on board */ 4481 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out"); 4482 if (IS_ERR(fep->clk_enet_out)) { 4483 ret = PTR_ERR(fep->clk_enet_out); 4484 goto failed_clk; 4485 } 4486 4487 fep->ptp_clk_on = false; 4488 mutex_init(&fep->ptp_clk_mutex); 4489 4490 /* clk_ref is optional, depends on board */ 4491 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref"); 4492 if (IS_ERR(fep->clk_ref)) { 4493 ret = PTR_ERR(fep->clk_ref); 4494 goto failed_clk; 4495 } 4496 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); 4497 4498 /* clk_2x_txclk is optional, depends on board */ 4499 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { 4500 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); 4501 if (IS_ERR(fep->clk_2x_txclk)) 4502 fep->clk_2x_txclk = NULL; 4503 } 4504 4505 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 4506 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 4507 if (IS_ERR(fep->clk_ptp)) { 4508 fep->clk_ptp = NULL; 4509 fep->bufdesc_ex = false; 4510 } 4511 4512 ret = fec_enet_clk_enable(ndev, true); 4513 if (ret) 4514 goto failed_clk; 4515 4516 ret = clk_prepare_enable(fep->clk_ipg); 4517 if (ret) 4518 goto failed_clk_ipg; 4519 ret = clk_prepare_enable(fep->clk_ahb); 4520 if (ret) 4521 goto failed_clk_ahb; 4522 4523 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 4524 if (!IS_ERR(fep->reg_phy)) { 4525 ret = regulator_enable(fep->reg_phy); 4526 if (ret) { 4527 dev_err(&pdev->dev, 4528 "Failed to enable phy regulator: %d\n", ret); 4529 goto failed_regulator; 4530 } 4531 } else { 4532 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 4533 ret = -EPROBE_DEFER; 4534 goto failed_regulator; 4535 } 4536 fep->reg_phy = NULL; 4537 } 4538 4539 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 4540 pm_runtime_use_autosuspend(&pdev->dev); 4541 pm_runtime_get_noresume(&pdev->dev); 4542 pm_runtime_set_active(&pdev->dev); 4543 pm_runtime_enable(&pdev->dev); 4544 4545 ret = fec_reset_phy(pdev); 4546 if (ret) 4547 goto failed_reset; 4548 4549 irq_cnt = fec_enet_get_irq_cnt(pdev); 4550 if (fep->bufdesc_ex) 4551 fec_ptp_init(pdev, irq_cnt); 4552 4553 ret = fec_enet_init(ndev); 4554 if (ret) 4555 goto failed_init; 4556 4557 for (i = 0; i < irq_cnt; i++) { 4558 snprintf(irq_name, sizeof(irq_name), "int%d", i); 4559 irq = platform_get_irq_byname_optional(pdev, irq_name); 4560 if (irq < 0) 4561 irq = platform_get_irq(pdev, i); 4562 if (irq < 0) { 4563 ret = irq; 4564 goto failed_irq; 4565 } 4566 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 4567 0, pdev->name, ndev); 4568 if (ret) 4569 goto failed_irq; 4570 4571 fep->irq[i] = irq; 4572 } 4573 4574 /* Decide which interrupt line is wakeup capable */ 4575 fec_enet_get_wakeup_irq(pdev); 4576 4577 ret = fec_enet_mii_init(pdev); 4578 if (ret) 4579 goto failed_mii_init; 4580 4581 /* Carrier starts down, phylib will bring it up */ 4582 netif_carrier_off(ndev); 4583 fec_enet_clk_enable(ndev, false); 4584 pinctrl_pm_select_sleep_state(&pdev->dev); 4585 4586 fep->pagepool_order = 0; 4587 fep->rx_frame_size = FEC_ENET_RX_FRSIZE; 4588 4589 if (fep->quirks & FEC_QUIRK_JUMBO_FRAME) 4590 fep->max_buf_size = MAX_JUMBO_BUF_SIZE; 4591 else 4592 fep->max_buf_size = PKT_MAXBUF_SIZE; 4593 4594 ndev->max_mtu = fep->max_buf_size - ETH_HLEN - ETH_FCS_LEN; 4595 4596 ret = register_netdev(ndev); 4597 if (ret) 4598 goto failed_register; 4599 4600 device_init_wakeup(&ndev->dev, fep->wol_flag & 4601 FEC_WOL_HAS_MAGIC_PACKET); 4602 4603 if (fep->bufdesc_ex && fep->ptp_clock) 4604 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 4605 4606 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 4607 4608 pm_runtime_put_autosuspend(&pdev->dev); 4609 4610 return 0; 4611 4612 failed_register: 4613 fec_enet_mii_remove(fep); 4614 failed_mii_init: 4615 failed_irq: 4616 fec_enet_deinit(ndev); 4617 failed_init: 4618 fec_ptp_stop(pdev); 4619 failed_reset: 4620 pm_runtime_put_noidle(&pdev->dev); 4621 pm_runtime_disable(&pdev->dev); 4622 if (fep->reg_phy) 4623 regulator_disable(fep->reg_phy); 4624 failed_regulator: 4625 clk_disable_unprepare(fep->clk_ahb); 4626 failed_clk_ahb: 4627 clk_disable_unprepare(fep->clk_ipg); 4628 failed_clk_ipg: 4629 fec_enet_clk_enable(ndev, false); 4630 failed_clk: 4631 failed_rgmii_delay: 4632 if (of_phy_is_fixed_link(np)) 4633 of_phy_deregister_fixed_link(np); 4634 of_node_put(phy_node); 4635 failed_stop_mode: 4636 failed_ipc_init: 4637 failed_phy: 4638 dev_id--; 4639 failed_ioremap: 4640 free_netdev(ndev); 4641 4642 return ret; 4643 } 4644 4645 static void 4646 fec_drv_remove(struct platform_device *pdev) 4647 { 4648 struct net_device *ndev = platform_get_drvdata(pdev); 4649 struct fec_enet_private *fep = netdev_priv(ndev); 4650 struct device_node *np = pdev->dev.of_node; 4651 int ret; 4652 4653 ret = pm_runtime_get_sync(&pdev->dev); 4654 if (ret < 0) 4655 dev_err(&pdev->dev, 4656 "Failed to resume device in remove callback (%pe)\n", 4657 ERR_PTR(ret)); 4658 4659 cancel_work_sync(&fep->tx_timeout_work); 4660 fec_ptp_stop(pdev); 4661 unregister_netdev(ndev); 4662 fec_enet_mii_remove(fep); 4663 if (fep->reg_phy) 4664 regulator_disable(fep->reg_phy); 4665 4666 if (of_phy_is_fixed_link(np)) 4667 of_phy_deregister_fixed_link(np); 4668 of_node_put(fep->phy_node); 4669 4670 /* After pm_runtime_get_sync() failed, the clks are still off, so skip 4671 * disabling them again. 4672 */ 4673 if (ret >= 0) { 4674 clk_disable_unprepare(fep->clk_ahb); 4675 clk_disable_unprepare(fep->clk_ipg); 4676 } 4677 pm_runtime_put_noidle(&pdev->dev); 4678 pm_runtime_disable(&pdev->dev); 4679 4680 fec_enet_deinit(ndev); 4681 free_netdev(ndev); 4682 } 4683 4684 static int fec_suspend(struct device *dev) 4685 { 4686 struct net_device *ndev = dev_get_drvdata(dev); 4687 struct fec_enet_private *fep = netdev_priv(ndev); 4688 int ret; 4689 4690 rtnl_lock(); 4691 if (netif_running(ndev)) { 4692 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 4693 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 4694 phy_stop(ndev->phydev); 4695 napi_disable(&fep->napi); 4696 netif_tx_lock_bh(ndev); 4697 netif_device_detach(ndev); 4698 netif_tx_unlock_bh(ndev); 4699 fec_stop(ndev); 4700 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4701 fec_irqs_disable(ndev); 4702 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 4703 } else { 4704 fec_irqs_disable_except_wakeup(ndev); 4705 if (fep->wake_irq > 0) { 4706 disable_irq(fep->wake_irq); 4707 enable_irq_wake(fep->wake_irq); 4708 } 4709 fec_enet_stop_mode(fep, true); 4710 } 4711 /* It's safe to disable clocks since interrupts are masked */ 4712 fec_enet_clk_enable(ndev, false); 4713 4714 fep->rpm_active = !pm_runtime_status_suspended(dev); 4715 if (fep->rpm_active) { 4716 ret = pm_runtime_force_suspend(dev); 4717 if (ret < 0) { 4718 rtnl_unlock(); 4719 return ret; 4720 } 4721 } 4722 } 4723 rtnl_unlock(); 4724 4725 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4726 regulator_disable(fep->reg_phy); 4727 4728 /* SOC supply clock to phy, when clock is disabled, phy link down 4729 * SOC control phy regulator, when regulator is disabled, phy link down 4730 */ 4731 if (fep->clk_enet_out || fep->reg_phy) 4732 fep->link = 0; 4733 4734 return 0; 4735 } 4736 4737 static int fec_resume(struct device *dev) 4738 { 4739 struct net_device *ndev = dev_get_drvdata(dev); 4740 struct fec_enet_private *fep = netdev_priv(ndev); 4741 int ret; 4742 int val; 4743 4744 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4745 ret = regulator_enable(fep->reg_phy); 4746 if (ret) 4747 return ret; 4748 } 4749 4750 rtnl_lock(); 4751 if (netif_running(ndev)) { 4752 if (fep->rpm_active) 4753 pm_runtime_force_resume(dev); 4754 4755 ret = fec_enet_clk_enable(ndev, true); 4756 if (ret) { 4757 rtnl_unlock(); 4758 goto failed_clk; 4759 } 4760 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 4761 fec_enet_stop_mode(fep, false); 4762 if (fep->wake_irq) { 4763 disable_irq_wake(fep->wake_irq); 4764 enable_irq(fep->wake_irq); 4765 } 4766 4767 val = readl(fep->hwp + FEC_ECNTRL); 4768 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 4769 writel(val, fep->hwp + FEC_ECNTRL); 4770 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 4771 } else { 4772 pinctrl_pm_select_default_state(&fep->pdev->dev); 4773 } 4774 fec_restart(ndev); 4775 netif_tx_lock_bh(ndev); 4776 netif_device_attach(ndev); 4777 netif_tx_unlock_bh(ndev); 4778 napi_enable(&fep->napi); 4779 phy_init_hw(ndev->phydev); 4780 phy_start(ndev->phydev); 4781 } 4782 rtnl_unlock(); 4783 4784 return 0; 4785 4786 failed_clk: 4787 if (fep->reg_phy) 4788 regulator_disable(fep->reg_phy); 4789 return ret; 4790 } 4791 4792 static int fec_runtime_suspend(struct device *dev) 4793 { 4794 struct net_device *ndev = dev_get_drvdata(dev); 4795 struct fec_enet_private *fep = netdev_priv(ndev); 4796 4797 clk_disable_unprepare(fep->clk_ahb); 4798 clk_disable_unprepare(fep->clk_ipg); 4799 4800 return 0; 4801 } 4802 4803 static int fec_runtime_resume(struct device *dev) 4804 { 4805 struct net_device *ndev = dev_get_drvdata(dev); 4806 struct fec_enet_private *fep = netdev_priv(ndev); 4807 int ret; 4808 4809 ret = clk_prepare_enable(fep->clk_ahb); 4810 if (ret) 4811 return ret; 4812 ret = clk_prepare_enable(fep->clk_ipg); 4813 if (ret) 4814 goto failed_clk_ipg; 4815 4816 return 0; 4817 4818 failed_clk_ipg: 4819 clk_disable_unprepare(fep->clk_ahb); 4820 return ret; 4821 } 4822 4823 static const struct dev_pm_ops fec_pm_ops = { 4824 SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 4825 RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 4826 }; 4827 4828 static struct platform_driver fec_driver = { 4829 .driver = { 4830 .name = DRIVER_NAME, 4831 .pm = pm_ptr(&fec_pm_ops), 4832 .of_match_table = fec_dt_ids, 4833 .suppress_bind_attrs = true, 4834 }, 4835 .id_table = fec_devtype, 4836 .probe = fec_probe, 4837 .remove = fec_drv_remove, 4838 }; 4839 4840 module_platform_driver(fec_driver); 4841 4842 MODULE_DESCRIPTION("NXP Fast Ethernet Controller (FEC) driver"); 4843 MODULE_LICENSE("GPL"); 4844