1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/page_pool/helpers.h> 42 #include <net/selftests.h> 43 #include <net/tso.h> 44 #include <linux/tcp.h> 45 #include <linux/udp.h> 46 #include <linux/icmp.h> 47 #include <linux/spinlock.h> 48 #include <linux/workqueue.h> 49 #include <linux/bitops.h> 50 #include <linux/io.h> 51 #include <linux/irq.h> 52 #include <linux/clk.h> 53 #include <linux/crc32.h> 54 #include <linux/platform_device.h> 55 #include <linux/property.h> 56 #include <linux/mdio.h> 57 #include <linux/phy.h> 58 #include <linux/fec.h> 59 #include <linux/of.h> 60 #include <linux/of_mdio.h> 61 #include <linux/of_net.h> 62 #include <linux/regulator/consumer.h> 63 #include <linux/if_vlan.h> 64 #include <linux/pinctrl/consumer.h> 65 #include <linux/gpio/consumer.h> 66 #include <linux/prefetch.h> 67 #include <linux/mfd/syscon.h> 68 #include <linux/regmap.h> 69 #include <soc/imx/cpuidle.h> 70 #include <linux/filter.h> 71 #include <linux/bpf.h> 72 #include <linux/bpf_trace.h> 73 74 #include <asm/cacheflush.h> 75 76 #include "fec.h" 77 78 static void set_multicast_list(struct net_device *ndev); 79 static void fec_enet_itr_coal_set(struct net_device *ndev); 80 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 81 int cpu, struct xdp_buff *xdp, 82 u32 dma_sync_len); 83 84 #define DRIVER_NAME "fec" 85 86 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 87 88 /* Pause frame feild and FIFO threshold */ 89 #define FEC_ENET_FCE (1 << 5) 90 #define FEC_ENET_RSEM_V 0x84 91 #define FEC_ENET_RSFL_V 16 92 #define FEC_ENET_RAEM_V 0x8 93 #define FEC_ENET_RAFL_V 0x8 94 #define FEC_ENET_OPD_V 0xFFF0 95 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 96 97 #define FEC_ENET_XDP_PASS 0 98 #define FEC_ENET_XDP_CONSUMED BIT(0) 99 #define FEC_ENET_XDP_TX BIT(1) 100 #define FEC_ENET_XDP_REDIR BIT(2) 101 102 struct fec_devinfo { 103 u32 quirks; 104 }; 105 106 static const struct fec_devinfo fec_imx25_info = { 107 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 108 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_HAS_MDIO_C45, 109 }; 110 111 static const struct fec_devinfo fec_imx27_info = { 112 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG | 113 FEC_QUIRK_HAS_MDIO_C45, 114 }; 115 116 static const struct fec_devinfo fec_imx28_info = { 117 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 118 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 119 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 120 FEC_QUIRK_NO_HARD_RESET | FEC_QUIRK_HAS_MDIO_C45, 121 }; 122 123 static const struct fec_devinfo fec_imx6q_info = { 124 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 125 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 126 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 127 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII | 128 FEC_QUIRK_HAS_PMQOS | FEC_QUIRK_HAS_MDIO_C45, 129 }; 130 131 static const struct fec_devinfo fec_mvf600_info = { 132 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC | 133 FEC_QUIRK_HAS_MDIO_C45, 134 }; 135 136 static const struct fec_devinfo fec_imx6x_info = { 137 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 138 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 139 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 140 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 141 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 142 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 143 FEC_QUIRK_HAS_MDIO_C45, 144 }; 145 146 static const struct fec_devinfo fec_imx6ul_info = { 147 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 148 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 149 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 150 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 151 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII | 152 FEC_QUIRK_HAS_MDIO_C45, 153 }; 154 155 static const struct fec_devinfo fec_imx8mq_info = { 156 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 157 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 158 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 159 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 160 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 161 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 162 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2 | 163 FEC_QUIRK_HAS_MDIO_C45, 164 }; 165 166 static const struct fec_devinfo fec_imx8qm_info = { 167 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 168 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 169 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 170 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 171 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 172 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 173 FEC_QUIRK_DELAYED_CLKS_SUPPORT | FEC_QUIRK_HAS_MDIO_C45, 174 }; 175 176 static const struct fec_devinfo fec_s32v234_info = { 177 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 178 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 179 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 180 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 181 FEC_QUIRK_HAS_MDIO_C45, 182 }; 183 184 static struct platform_device_id fec_devtype[] = { 185 { 186 /* keep it for coldfire */ 187 .name = DRIVER_NAME, 188 .driver_data = 0, 189 }, { 190 /* sentinel */ 191 } 192 }; 193 MODULE_DEVICE_TABLE(platform, fec_devtype); 194 195 static const struct of_device_id fec_dt_ids[] = { 196 { .compatible = "fsl,imx25-fec", .data = &fec_imx25_info, }, 197 { .compatible = "fsl,imx27-fec", .data = &fec_imx27_info, }, 198 { .compatible = "fsl,imx28-fec", .data = &fec_imx28_info, }, 199 { .compatible = "fsl,imx6q-fec", .data = &fec_imx6q_info, }, 200 { .compatible = "fsl,mvf600-fec", .data = &fec_mvf600_info, }, 201 { .compatible = "fsl,imx6sx-fec", .data = &fec_imx6x_info, }, 202 { .compatible = "fsl,imx6ul-fec", .data = &fec_imx6ul_info, }, 203 { .compatible = "fsl,imx8mq-fec", .data = &fec_imx8mq_info, }, 204 { .compatible = "fsl,imx8qm-fec", .data = &fec_imx8qm_info, }, 205 { .compatible = "fsl,s32v234-fec", .data = &fec_s32v234_info, }, 206 { /* sentinel */ } 207 }; 208 MODULE_DEVICE_TABLE(of, fec_dt_ids); 209 210 static unsigned char macaddr[ETH_ALEN]; 211 module_param_array(macaddr, byte, NULL, 0); 212 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 213 214 #if defined(CONFIG_M5272) 215 /* 216 * Some hardware gets it MAC address out of local flash memory. 217 * if this is non-zero then assume it is the address to get MAC from. 218 */ 219 #if defined(CONFIG_NETtel) 220 #define FEC_FLASHMAC 0xf0006006 221 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 222 #define FEC_FLASHMAC 0xf0006000 223 #elif defined(CONFIG_CANCam) 224 #define FEC_FLASHMAC 0xf0020000 225 #elif defined (CONFIG_M5272C3) 226 #define FEC_FLASHMAC (0xffe04000 + 4) 227 #elif defined(CONFIG_MOD5272) 228 #define FEC_FLASHMAC 0xffc0406b 229 #else 230 #define FEC_FLASHMAC 0 231 #endif 232 #endif /* CONFIG_M5272 */ 233 234 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 235 * 236 * 2048 byte skbufs are allocated. However, alignment requirements 237 * varies between FEC variants. Worst case is 64, so round down by 64. 238 */ 239 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 240 #define PKT_MINBUF_SIZE 64 241 242 /* FEC receive acceleration */ 243 #define FEC_RACC_IPDIS (1 << 1) 244 #define FEC_RACC_PRODIS (1 << 2) 245 #define FEC_RACC_SHIFT16 BIT(7) 246 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 247 248 /* MIB Control Register */ 249 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 250 251 /* 252 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 253 * size bits. Other FEC hardware does not, so we need to take that into 254 * account when setting it. 255 */ 256 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 257 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 258 defined(CONFIG_ARM64) 259 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 260 #else 261 #define OPT_FRAME_SIZE 0 262 #endif 263 264 /* FEC MII MMFR bits definition */ 265 #define FEC_MMFR_ST (1 << 30) 266 #define FEC_MMFR_ST_C45 (0) 267 #define FEC_MMFR_OP_READ (2 << 28) 268 #define FEC_MMFR_OP_READ_C45 (3 << 28) 269 #define FEC_MMFR_OP_WRITE (1 << 28) 270 #define FEC_MMFR_OP_ADDR_WRITE (0) 271 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 272 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 273 #define FEC_MMFR_TA (2 << 16) 274 #define FEC_MMFR_DATA(v) (v & 0xffff) 275 /* FEC ECR bits definition */ 276 #define FEC_ECR_MAGICEN (1 << 2) 277 #define FEC_ECR_SLEEP (1 << 3) 278 279 #define FEC_MII_TIMEOUT 30000 /* us */ 280 281 /* Transmitter timeout */ 282 #define TX_TIMEOUT (2 * HZ) 283 284 #define FEC_PAUSE_FLAG_AUTONEG 0x1 285 #define FEC_PAUSE_FLAG_ENABLE 0x2 286 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 287 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 288 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 289 290 /* Max number of allowed TCP segments for software TSO */ 291 #define FEC_MAX_TSO_SEGS 100 292 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 293 294 #define IS_TSO_HEADER(txq, addr) \ 295 ((addr >= txq->tso_hdrs_dma) && \ 296 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 297 298 static int mii_cnt; 299 300 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 301 struct bufdesc_prop *bd) 302 { 303 return (bdp >= bd->last) ? bd->base 304 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 305 } 306 307 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 308 struct bufdesc_prop *bd) 309 { 310 return (bdp <= bd->base) ? bd->last 311 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 312 } 313 314 static int fec_enet_get_bd_index(struct bufdesc *bdp, 315 struct bufdesc_prop *bd) 316 { 317 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 318 } 319 320 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 321 { 322 int entries; 323 324 entries = (((const char *)txq->dirty_tx - 325 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 326 327 return entries >= 0 ? entries : entries + txq->bd.ring_size; 328 } 329 330 static void swap_buffer(void *bufaddr, int len) 331 { 332 int i; 333 unsigned int *buf = bufaddr; 334 335 for (i = 0; i < len; i += 4, buf++) 336 swab32s(buf); 337 } 338 339 static void fec_dump(struct net_device *ndev) 340 { 341 struct fec_enet_private *fep = netdev_priv(ndev); 342 struct bufdesc *bdp; 343 struct fec_enet_priv_tx_q *txq; 344 int index = 0; 345 346 netdev_info(ndev, "TX ring dump\n"); 347 pr_info("Nr SC addr len SKB\n"); 348 349 txq = fep->tx_queue[0]; 350 bdp = txq->bd.base; 351 352 do { 353 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 354 index, 355 bdp == txq->bd.cur ? 'S' : ' ', 356 bdp == txq->dirty_tx ? 'H' : ' ', 357 fec16_to_cpu(bdp->cbd_sc), 358 fec32_to_cpu(bdp->cbd_bufaddr), 359 fec16_to_cpu(bdp->cbd_datlen), 360 txq->tx_buf[index].buf_p); 361 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 362 index++; 363 } while (bdp != txq->bd.base); 364 } 365 366 static inline bool is_ipv4_pkt(struct sk_buff *skb) 367 { 368 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 369 } 370 371 static int 372 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 373 { 374 /* Only run for packets requiring a checksum. */ 375 if (skb->ip_summed != CHECKSUM_PARTIAL) 376 return 0; 377 378 if (unlikely(skb_cow_head(skb, 0))) 379 return -1; 380 381 if (is_ipv4_pkt(skb)) 382 ip_hdr(skb)->check = 0; 383 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 384 385 return 0; 386 } 387 388 static int 389 fec_enet_create_page_pool(struct fec_enet_private *fep, 390 struct fec_enet_priv_rx_q *rxq, int size) 391 { 392 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 393 struct page_pool_params pp_params = { 394 .order = 0, 395 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 396 .pool_size = size, 397 .nid = dev_to_node(&fep->pdev->dev), 398 .dev = &fep->pdev->dev, 399 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 400 .offset = FEC_ENET_XDP_HEADROOM, 401 .max_len = FEC_ENET_RX_FRSIZE, 402 }; 403 int err; 404 405 rxq->page_pool = page_pool_create(&pp_params); 406 if (IS_ERR(rxq->page_pool)) { 407 err = PTR_ERR(rxq->page_pool); 408 rxq->page_pool = NULL; 409 return err; 410 } 411 412 err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0); 413 if (err < 0) 414 goto err_free_pp; 415 416 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 417 rxq->page_pool); 418 if (err) 419 goto err_unregister_rxq; 420 421 return 0; 422 423 err_unregister_rxq: 424 xdp_rxq_info_unreg(&rxq->xdp_rxq); 425 err_free_pp: 426 page_pool_destroy(rxq->page_pool); 427 rxq->page_pool = NULL; 428 return err; 429 } 430 431 static struct bufdesc * 432 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 433 struct sk_buff *skb, 434 struct net_device *ndev) 435 { 436 struct fec_enet_private *fep = netdev_priv(ndev); 437 struct bufdesc *bdp = txq->bd.cur; 438 struct bufdesc_ex *ebdp; 439 int nr_frags = skb_shinfo(skb)->nr_frags; 440 int frag, frag_len; 441 unsigned short status; 442 unsigned int estatus = 0; 443 skb_frag_t *this_frag; 444 unsigned int index; 445 void *bufaddr; 446 dma_addr_t addr; 447 int i; 448 449 for (frag = 0; frag < nr_frags; frag++) { 450 this_frag = &skb_shinfo(skb)->frags[frag]; 451 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 452 ebdp = (struct bufdesc_ex *)bdp; 453 454 status = fec16_to_cpu(bdp->cbd_sc); 455 status &= ~BD_ENET_TX_STATS; 456 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 457 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 458 459 /* Handle the last BD specially */ 460 if (frag == nr_frags - 1) { 461 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 462 if (fep->bufdesc_ex) { 463 estatus |= BD_ENET_TX_INT; 464 if (unlikely(skb_shinfo(skb)->tx_flags & 465 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 466 estatus |= BD_ENET_TX_TS; 467 } 468 } 469 470 if (fep->bufdesc_ex) { 471 if (fep->quirks & FEC_QUIRK_HAS_AVB) 472 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 473 if (skb->ip_summed == CHECKSUM_PARTIAL) 474 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 475 476 ebdp->cbd_bdu = 0; 477 ebdp->cbd_esc = cpu_to_fec32(estatus); 478 } 479 480 bufaddr = skb_frag_address(this_frag); 481 482 index = fec_enet_get_bd_index(bdp, &txq->bd); 483 if (((unsigned long) bufaddr) & fep->tx_align || 484 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 485 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 486 bufaddr = txq->tx_bounce[index]; 487 488 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 489 swap_buffer(bufaddr, frag_len); 490 } 491 492 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 493 DMA_TO_DEVICE); 494 if (dma_mapping_error(&fep->pdev->dev, addr)) { 495 if (net_ratelimit()) 496 netdev_err(ndev, "Tx DMA memory map failed\n"); 497 goto dma_mapping_error; 498 } 499 500 bdp->cbd_bufaddr = cpu_to_fec32(addr); 501 bdp->cbd_datlen = cpu_to_fec16(frag_len); 502 /* Make sure the updates to rest of the descriptor are 503 * performed before transferring ownership. 504 */ 505 wmb(); 506 bdp->cbd_sc = cpu_to_fec16(status); 507 } 508 509 return bdp; 510 dma_mapping_error: 511 bdp = txq->bd.cur; 512 for (i = 0; i < frag; i++) { 513 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 514 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 515 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 516 } 517 return ERR_PTR(-ENOMEM); 518 } 519 520 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 521 struct sk_buff *skb, struct net_device *ndev) 522 { 523 struct fec_enet_private *fep = netdev_priv(ndev); 524 int nr_frags = skb_shinfo(skb)->nr_frags; 525 struct bufdesc *bdp, *last_bdp; 526 void *bufaddr; 527 dma_addr_t addr; 528 unsigned short status; 529 unsigned short buflen; 530 unsigned int estatus = 0; 531 unsigned int index; 532 int entries_free; 533 534 entries_free = fec_enet_get_free_txdesc_num(txq); 535 if (entries_free < MAX_SKB_FRAGS + 1) { 536 dev_kfree_skb_any(skb); 537 if (net_ratelimit()) 538 netdev_err(ndev, "NOT enough BD for SG!\n"); 539 return NETDEV_TX_OK; 540 } 541 542 /* Protocol checksum off-load for TCP and UDP. */ 543 if (fec_enet_clear_csum(skb, ndev)) { 544 dev_kfree_skb_any(skb); 545 return NETDEV_TX_OK; 546 } 547 548 /* Fill in a Tx ring entry */ 549 bdp = txq->bd.cur; 550 last_bdp = bdp; 551 status = fec16_to_cpu(bdp->cbd_sc); 552 status &= ~BD_ENET_TX_STATS; 553 554 /* Set buffer length and buffer pointer */ 555 bufaddr = skb->data; 556 buflen = skb_headlen(skb); 557 558 index = fec_enet_get_bd_index(bdp, &txq->bd); 559 if (((unsigned long) bufaddr) & fep->tx_align || 560 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 561 memcpy(txq->tx_bounce[index], skb->data, buflen); 562 bufaddr = txq->tx_bounce[index]; 563 564 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 565 swap_buffer(bufaddr, buflen); 566 } 567 568 /* Push the data cache so the CPM does not get stale memory data. */ 569 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 570 if (dma_mapping_error(&fep->pdev->dev, addr)) { 571 dev_kfree_skb_any(skb); 572 if (net_ratelimit()) 573 netdev_err(ndev, "Tx DMA memory map failed\n"); 574 return NETDEV_TX_OK; 575 } 576 577 if (nr_frags) { 578 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 579 if (IS_ERR(last_bdp)) { 580 dma_unmap_single(&fep->pdev->dev, addr, 581 buflen, DMA_TO_DEVICE); 582 dev_kfree_skb_any(skb); 583 return NETDEV_TX_OK; 584 } 585 } else { 586 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 587 if (fep->bufdesc_ex) { 588 estatus = BD_ENET_TX_INT; 589 if (unlikely(skb_shinfo(skb)->tx_flags & 590 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 591 estatus |= BD_ENET_TX_TS; 592 } 593 } 594 bdp->cbd_bufaddr = cpu_to_fec32(addr); 595 bdp->cbd_datlen = cpu_to_fec16(buflen); 596 597 if (fep->bufdesc_ex) { 598 599 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 600 601 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 602 fep->hwts_tx_en)) 603 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 604 605 if (fep->quirks & FEC_QUIRK_HAS_AVB) 606 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 607 608 if (skb->ip_summed == CHECKSUM_PARTIAL) 609 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 610 611 ebdp->cbd_bdu = 0; 612 ebdp->cbd_esc = cpu_to_fec32(estatus); 613 } 614 615 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 616 /* Save skb pointer */ 617 txq->tx_buf[index].buf_p = skb; 618 619 /* Make sure the updates to rest of the descriptor are performed before 620 * transferring ownership. 621 */ 622 wmb(); 623 624 /* Send it on its way. Tell FEC it's ready, interrupt when done, 625 * it's the last BD of the frame, and to put the CRC on the end. 626 */ 627 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 628 bdp->cbd_sc = cpu_to_fec16(status); 629 630 /* If this was the last BD in the ring, start at the beginning again. */ 631 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 632 633 skb_tx_timestamp(skb); 634 635 /* Make sure the update to bdp is performed before txq->bd.cur. */ 636 wmb(); 637 txq->bd.cur = bdp; 638 639 /* Trigger transmission start */ 640 writel(0, txq->bd.reg_desc_active); 641 642 return 0; 643 } 644 645 static int 646 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 647 struct net_device *ndev, 648 struct bufdesc *bdp, int index, char *data, 649 int size, bool last_tcp, bool is_last) 650 { 651 struct fec_enet_private *fep = netdev_priv(ndev); 652 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 653 unsigned short status; 654 unsigned int estatus = 0; 655 dma_addr_t addr; 656 657 status = fec16_to_cpu(bdp->cbd_sc); 658 status &= ~BD_ENET_TX_STATS; 659 660 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 661 662 if (((unsigned long) data) & fep->tx_align || 663 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 664 memcpy(txq->tx_bounce[index], data, size); 665 data = txq->tx_bounce[index]; 666 667 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 668 swap_buffer(data, size); 669 } 670 671 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 672 if (dma_mapping_error(&fep->pdev->dev, addr)) { 673 dev_kfree_skb_any(skb); 674 if (net_ratelimit()) 675 netdev_err(ndev, "Tx DMA memory map failed\n"); 676 return NETDEV_TX_OK; 677 } 678 679 bdp->cbd_datlen = cpu_to_fec16(size); 680 bdp->cbd_bufaddr = cpu_to_fec32(addr); 681 682 if (fep->bufdesc_ex) { 683 if (fep->quirks & FEC_QUIRK_HAS_AVB) 684 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 685 if (skb->ip_summed == CHECKSUM_PARTIAL) 686 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 687 ebdp->cbd_bdu = 0; 688 ebdp->cbd_esc = cpu_to_fec32(estatus); 689 } 690 691 /* Handle the last BD specially */ 692 if (last_tcp) 693 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 694 if (is_last) { 695 status |= BD_ENET_TX_INTR; 696 if (fep->bufdesc_ex) 697 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 698 } 699 700 bdp->cbd_sc = cpu_to_fec16(status); 701 702 return 0; 703 } 704 705 static int 706 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 707 struct sk_buff *skb, struct net_device *ndev, 708 struct bufdesc *bdp, int index) 709 { 710 struct fec_enet_private *fep = netdev_priv(ndev); 711 int hdr_len = skb_tcp_all_headers(skb); 712 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 713 void *bufaddr; 714 unsigned long dmabuf; 715 unsigned short status; 716 unsigned int estatus = 0; 717 718 status = fec16_to_cpu(bdp->cbd_sc); 719 status &= ~BD_ENET_TX_STATS; 720 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 721 722 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 723 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 724 if (((unsigned long)bufaddr) & fep->tx_align || 725 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 726 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 727 bufaddr = txq->tx_bounce[index]; 728 729 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 730 swap_buffer(bufaddr, hdr_len); 731 732 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 733 hdr_len, DMA_TO_DEVICE); 734 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 735 dev_kfree_skb_any(skb); 736 if (net_ratelimit()) 737 netdev_err(ndev, "Tx DMA memory map failed\n"); 738 return NETDEV_TX_OK; 739 } 740 } 741 742 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 743 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 744 745 if (fep->bufdesc_ex) { 746 if (fep->quirks & FEC_QUIRK_HAS_AVB) 747 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 748 if (skb->ip_summed == CHECKSUM_PARTIAL) 749 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 750 ebdp->cbd_bdu = 0; 751 ebdp->cbd_esc = cpu_to_fec32(estatus); 752 } 753 754 bdp->cbd_sc = cpu_to_fec16(status); 755 756 return 0; 757 } 758 759 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 760 struct sk_buff *skb, 761 struct net_device *ndev) 762 { 763 struct fec_enet_private *fep = netdev_priv(ndev); 764 int hdr_len, total_len, data_left; 765 struct bufdesc *bdp = txq->bd.cur; 766 struct tso_t tso; 767 unsigned int index = 0; 768 int ret; 769 770 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 771 dev_kfree_skb_any(skb); 772 if (net_ratelimit()) 773 netdev_err(ndev, "NOT enough BD for TSO!\n"); 774 return NETDEV_TX_OK; 775 } 776 777 /* Protocol checksum off-load for TCP and UDP. */ 778 if (fec_enet_clear_csum(skb, ndev)) { 779 dev_kfree_skb_any(skb); 780 return NETDEV_TX_OK; 781 } 782 783 /* Initialize the TSO handler, and prepare the first payload */ 784 hdr_len = tso_start(skb, &tso); 785 786 total_len = skb->len - hdr_len; 787 while (total_len > 0) { 788 char *hdr; 789 790 index = fec_enet_get_bd_index(bdp, &txq->bd); 791 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 792 total_len -= data_left; 793 794 /* prepare packet headers: MAC + IP + TCP */ 795 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 796 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 797 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 798 if (ret) 799 goto err_release; 800 801 while (data_left > 0) { 802 int size; 803 804 size = min_t(int, tso.size, data_left); 805 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 806 index = fec_enet_get_bd_index(bdp, &txq->bd); 807 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 808 bdp, index, 809 tso.data, size, 810 size == data_left, 811 total_len == 0); 812 if (ret) 813 goto err_release; 814 815 data_left -= size; 816 tso_build_data(skb, &tso, size); 817 } 818 819 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 820 } 821 822 /* Save skb pointer */ 823 txq->tx_buf[index].buf_p = skb; 824 825 skb_tx_timestamp(skb); 826 txq->bd.cur = bdp; 827 828 /* Trigger transmission start */ 829 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 830 !readl(txq->bd.reg_desc_active) || 831 !readl(txq->bd.reg_desc_active) || 832 !readl(txq->bd.reg_desc_active) || 833 !readl(txq->bd.reg_desc_active)) 834 writel(0, txq->bd.reg_desc_active); 835 836 return 0; 837 838 err_release: 839 /* TODO: Release all used data descriptors for TSO */ 840 return ret; 841 } 842 843 static netdev_tx_t 844 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 845 { 846 struct fec_enet_private *fep = netdev_priv(ndev); 847 int entries_free; 848 unsigned short queue; 849 struct fec_enet_priv_tx_q *txq; 850 struct netdev_queue *nq; 851 int ret; 852 853 queue = skb_get_queue_mapping(skb); 854 txq = fep->tx_queue[queue]; 855 nq = netdev_get_tx_queue(ndev, queue); 856 857 if (skb_is_gso(skb)) 858 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 859 else 860 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 861 if (ret) 862 return ret; 863 864 entries_free = fec_enet_get_free_txdesc_num(txq); 865 if (entries_free <= txq->tx_stop_threshold) 866 netif_tx_stop_queue(nq); 867 868 return NETDEV_TX_OK; 869 } 870 871 /* Init RX & TX buffer descriptors 872 */ 873 static void fec_enet_bd_init(struct net_device *dev) 874 { 875 struct fec_enet_private *fep = netdev_priv(dev); 876 struct fec_enet_priv_tx_q *txq; 877 struct fec_enet_priv_rx_q *rxq; 878 struct bufdesc *bdp; 879 unsigned int i; 880 unsigned int q; 881 882 for (q = 0; q < fep->num_rx_queues; q++) { 883 /* Initialize the receive buffer descriptors. */ 884 rxq = fep->rx_queue[q]; 885 bdp = rxq->bd.base; 886 887 for (i = 0; i < rxq->bd.ring_size; i++) { 888 889 /* Initialize the BD for every fragment in the page. */ 890 if (bdp->cbd_bufaddr) 891 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 892 else 893 bdp->cbd_sc = cpu_to_fec16(0); 894 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 895 } 896 897 /* Set the last buffer to wrap */ 898 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 899 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 900 901 rxq->bd.cur = rxq->bd.base; 902 } 903 904 for (q = 0; q < fep->num_tx_queues; q++) { 905 /* ...and the same for transmit */ 906 txq = fep->tx_queue[q]; 907 bdp = txq->bd.base; 908 txq->bd.cur = bdp; 909 910 for (i = 0; i < txq->bd.ring_size; i++) { 911 /* Initialize the BD for every fragment in the page. */ 912 bdp->cbd_sc = cpu_to_fec16(0); 913 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 914 if (bdp->cbd_bufaddr && 915 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 916 dma_unmap_single(&fep->pdev->dev, 917 fec32_to_cpu(bdp->cbd_bufaddr), 918 fec16_to_cpu(bdp->cbd_datlen), 919 DMA_TO_DEVICE); 920 if (txq->tx_buf[i].buf_p) 921 dev_kfree_skb_any(txq->tx_buf[i].buf_p); 922 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 923 if (bdp->cbd_bufaddr) 924 dma_unmap_single(&fep->pdev->dev, 925 fec32_to_cpu(bdp->cbd_bufaddr), 926 fec16_to_cpu(bdp->cbd_datlen), 927 DMA_TO_DEVICE); 928 929 if (txq->tx_buf[i].buf_p) 930 xdp_return_frame(txq->tx_buf[i].buf_p); 931 } else { 932 struct page *page = txq->tx_buf[i].buf_p; 933 934 if (page) 935 page_pool_put_page(page->pp, page, 0, false); 936 } 937 938 txq->tx_buf[i].buf_p = NULL; 939 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 940 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 941 bdp->cbd_bufaddr = cpu_to_fec32(0); 942 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 943 } 944 945 /* Set the last buffer to wrap */ 946 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 947 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 948 txq->dirty_tx = bdp; 949 } 950 } 951 952 static void fec_enet_active_rxring(struct net_device *ndev) 953 { 954 struct fec_enet_private *fep = netdev_priv(ndev); 955 int i; 956 957 for (i = 0; i < fep->num_rx_queues; i++) 958 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 959 } 960 961 static void fec_enet_enable_ring(struct net_device *ndev) 962 { 963 struct fec_enet_private *fep = netdev_priv(ndev); 964 struct fec_enet_priv_tx_q *txq; 965 struct fec_enet_priv_rx_q *rxq; 966 int i; 967 968 for (i = 0; i < fep->num_rx_queues; i++) { 969 rxq = fep->rx_queue[i]; 970 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 971 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 972 973 /* enable DMA1/2 */ 974 if (i) 975 writel(RCMR_MATCHEN | RCMR_CMP(i), 976 fep->hwp + FEC_RCMR(i)); 977 } 978 979 for (i = 0; i < fep->num_tx_queues; i++) { 980 txq = fep->tx_queue[i]; 981 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 982 983 /* enable DMA1/2 */ 984 if (i) 985 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 986 fep->hwp + FEC_DMA_CFG(i)); 987 } 988 } 989 990 /* 991 * This function is called to start or restart the FEC during a link 992 * change, transmit timeout, or to reconfigure the FEC. The network 993 * packet processing for this device must be stopped before this call. 994 */ 995 static void 996 fec_restart(struct net_device *ndev) 997 { 998 struct fec_enet_private *fep = netdev_priv(ndev); 999 u32 temp_mac[2]; 1000 u32 rcntl = OPT_FRAME_SIZE | 0x04; 1001 u32 ecntl = 0x2; /* ETHEREN */ 1002 1003 /* Whack a reset. We should wait for this. 1004 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1005 * instead of reset MAC itself. 1006 */ 1007 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || 1008 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 1009 writel(0, fep->hwp + FEC_ECNTRL); 1010 } else { 1011 writel(1, fep->hwp + FEC_ECNTRL); 1012 udelay(10); 1013 } 1014 1015 /* 1016 * enet-mac reset will reset mac address registers too, 1017 * so need to reconfigure it. 1018 */ 1019 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 1020 writel((__force u32)cpu_to_be32(temp_mac[0]), 1021 fep->hwp + FEC_ADDR_LOW); 1022 writel((__force u32)cpu_to_be32(temp_mac[1]), 1023 fep->hwp + FEC_ADDR_HIGH); 1024 1025 /* Clear any outstanding interrupt, except MDIO. */ 1026 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 1027 1028 fec_enet_bd_init(ndev); 1029 1030 fec_enet_enable_ring(ndev); 1031 1032 /* Enable MII mode */ 1033 if (fep->full_duplex == DUPLEX_FULL) { 1034 /* FD enable */ 1035 writel(0x04, fep->hwp + FEC_X_CNTRL); 1036 } else { 1037 /* No Rcv on Xmit */ 1038 rcntl |= 0x02; 1039 writel(0x0, fep->hwp + FEC_X_CNTRL); 1040 } 1041 1042 /* Set MII speed */ 1043 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1044 1045 #if !defined(CONFIG_M5272) 1046 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1047 u32 val = readl(fep->hwp + FEC_RACC); 1048 1049 /* align IP header */ 1050 val |= FEC_RACC_SHIFT16; 1051 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1052 /* set RX checksum */ 1053 val |= FEC_RACC_OPTIONS; 1054 else 1055 val &= ~FEC_RACC_OPTIONS; 1056 writel(val, fep->hwp + FEC_RACC); 1057 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1058 } 1059 #endif 1060 1061 /* 1062 * The phy interface and speed need to get configured 1063 * differently on enet-mac. 1064 */ 1065 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1066 /* Enable flow control and length check */ 1067 rcntl |= 0x40000000 | 0x00000020; 1068 1069 /* RGMII, RMII or MII */ 1070 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1071 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1072 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1073 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1074 rcntl |= (1 << 6); 1075 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1076 rcntl |= (1 << 8); 1077 else 1078 rcntl &= ~(1 << 8); 1079 1080 /* 1G, 100M or 10M */ 1081 if (ndev->phydev) { 1082 if (ndev->phydev->speed == SPEED_1000) 1083 ecntl |= (1 << 5); 1084 else if (ndev->phydev->speed == SPEED_100) 1085 rcntl &= ~(1 << 9); 1086 else 1087 rcntl |= (1 << 9); 1088 } 1089 } else { 1090 #ifdef FEC_MIIGSK_ENR 1091 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1092 u32 cfgr; 1093 /* disable the gasket and wait */ 1094 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1095 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1096 udelay(1); 1097 1098 /* 1099 * configure the gasket: 1100 * RMII, 50 MHz, no loopback, no echo 1101 * MII, 25 MHz, no loopback, no echo 1102 */ 1103 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1104 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1105 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1106 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1107 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1108 1109 /* re-enable the gasket */ 1110 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1111 } 1112 #endif 1113 } 1114 1115 #if !defined(CONFIG_M5272) 1116 /* enable pause frame*/ 1117 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1118 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1119 ndev->phydev && ndev->phydev->pause)) { 1120 rcntl |= FEC_ENET_FCE; 1121 1122 /* set FIFO threshold parameter to reduce overrun */ 1123 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1124 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1125 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1126 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1127 1128 /* OPD */ 1129 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1130 } else { 1131 rcntl &= ~FEC_ENET_FCE; 1132 } 1133 #endif /* !defined(CONFIG_M5272) */ 1134 1135 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1136 1137 /* Setup multicast filter. */ 1138 set_multicast_list(ndev); 1139 #ifndef CONFIG_M5272 1140 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1141 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1142 #endif 1143 1144 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1145 /* enable ENET endian swap */ 1146 ecntl |= (1 << 8); 1147 /* enable ENET store and forward mode */ 1148 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1149 } 1150 1151 if (fep->bufdesc_ex) 1152 ecntl |= (1 << 4); 1153 1154 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1155 fep->rgmii_txc_dly) 1156 ecntl |= FEC_ENET_TXC_DLY; 1157 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1158 fep->rgmii_rxc_dly) 1159 ecntl |= FEC_ENET_RXC_DLY; 1160 1161 #ifndef CONFIG_M5272 1162 /* Enable the MIB statistic event counters */ 1163 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1164 #endif 1165 1166 /* And last, enable the transmit and receive processing */ 1167 writel(ecntl, fep->hwp + FEC_ECNTRL); 1168 fec_enet_active_rxring(ndev); 1169 1170 if (fep->bufdesc_ex) 1171 fec_ptp_start_cyclecounter(ndev); 1172 1173 /* Enable interrupts we wish to service */ 1174 if (fep->link) 1175 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1176 else 1177 writel(0, fep->hwp + FEC_IMASK); 1178 1179 /* Init the interrupt coalescing */ 1180 if (fep->quirks & FEC_QUIRK_HAS_COALESCE) 1181 fec_enet_itr_coal_set(ndev); 1182 } 1183 1184 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep) 1185 { 1186 if (!(of_machine_is_compatible("fsl,imx8qm") || 1187 of_machine_is_compatible("fsl,imx8qxp") || 1188 of_machine_is_compatible("fsl,imx8dxl"))) 1189 return 0; 1190 1191 return imx_scu_get_handle(&fep->ipc_handle); 1192 } 1193 1194 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled) 1195 { 1196 struct device_node *np = fep->pdev->dev.of_node; 1197 u32 rsrc_id, val; 1198 int idx; 1199 1200 if (!np || !fep->ipc_handle) 1201 return; 1202 1203 idx = of_alias_get_id(np, "ethernet"); 1204 if (idx < 0) 1205 idx = 0; 1206 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0; 1207 1208 val = enabled ? 1 : 0; 1209 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val); 1210 } 1211 1212 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1213 { 1214 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1215 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1216 1217 if (stop_gpr->gpr) { 1218 if (enabled) 1219 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1220 BIT(stop_gpr->bit), 1221 BIT(stop_gpr->bit)); 1222 else 1223 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1224 BIT(stop_gpr->bit), 0); 1225 } else if (pdata && pdata->sleep_mode_enable) { 1226 pdata->sleep_mode_enable(enabled); 1227 } else { 1228 fec_enet_ipg_stop_set(fep, enabled); 1229 } 1230 } 1231 1232 static void fec_irqs_disable(struct net_device *ndev) 1233 { 1234 struct fec_enet_private *fep = netdev_priv(ndev); 1235 1236 writel(0, fep->hwp + FEC_IMASK); 1237 } 1238 1239 static void fec_irqs_disable_except_wakeup(struct net_device *ndev) 1240 { 1241 struct fec_enet_private *fep = netdev_priv(ndev); 1242 1243 writel(0, fep->hwp + FEC_IMASK); 1244 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1245 } 1246 1247 static void 1248 fec_stop(struct net_device *ndev) 1249 { 1250 struct fec_enet_private *fep = netdev_priv(ndev); 1251 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1252 u32 val; 1253 1254 /* We cannot expect a graceful transmit stop without link !!! */ 1255 if (fep->link) { 1256 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1257 udelay(10); 1258 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1259 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1260 } 1261 1262 /* Whack a reset. We should wait for this. 1263 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1264 * instead of reset MAC itself. 1265 */ 1266 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1267 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 1268 writel(0, fep->hwp + FEC_ECNTRL); 1269 } else { 1270 writel(1, fep->hwp + FEC_ECNTRL); 1271 udelay(10); 1272 } 1273 } else { 1274 val = readl(fep->hwp + FEC_ECNTRL); 1275 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1276 writel(val, fep->hwp + FEC_ECNTRL); 1277 } 1278 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1279 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1280 1281 /* We have to keep ENET enabled to have MII interrupt stay working */ 1282 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1283 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1284 writel(2, fep->hwp + FEC_ECNTRL); 1285 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1286 } 1287 } 1288 1289 1290 static void 1291 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1292 { 1293 struct fec_enet_private *fep = netdev_priv(ndev); 1294 1295 fec_dump(ndev); 1296 1297 ndev->stats.tx_errors++; 1298 1299 schedule_work(&fep->tx_timeout_work); 1300 } 1301 1302 static void fec_enet_timeout_work(struct work_struct *work) 1303 { 1304 struct fec_enet_private *fep = 1305 container_of(work, struct fec_enet_private, tx_timeout_work); 1306 struct net_device *ndev = fep->netdev; 1307 1308 rtnl_lock(); 1309 if (netif_device_present(ndev) || netif_running(ndev)) { 1310 napi_disable(&fep->napi); 1311 netif_tx_lock_bh(ndev); 1312 fec_restart(ndev); 1313 netif_tx_wake_all_queues(ndev); 1314 netif_tx_unlock_bh(ndev); 1315 napi_enable(&fep->napi); 1316 } 1317 rtnl_unlock(); 1318 } 1319 1320 static void 1321 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1322 struct skb_shared_hwtstamps *hwtstamps) 1323 { 1324 unsigned long flags; 1325 u64 ns; 1326 1327 spin_lock_irqsave(&fep->tmreg_lock, flags); 1328 ns = timecounter_cyc2time(&fep->tc, ts); 1329 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1330 1331 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1332 hwtstamps->hwtstamp = ns_to_ktime(ns); 1333 } 1334 1335 static void 1336 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id, int budget) 1337 { 1338 struct fec_enet_private *fep; 1339 struct xdp_frame *xdpf; 1340 struct bufdesc *bdp; 1341 unsigned short status; 1342 struct sk_buff *skb; 1343 struct fec_enet_priv_tx_q *txq; 1344 struct netdev_queue *nq; 1345 int index = 0; 1346 int entries_free; 1347 struct page *page; 1348 int frame_len; 1349 1350 fep = netdev_priv(ndev); 1351 1352 txq = fep->tx_queue[queue_id]; 1353 /* get next bdp of dirty_tx */ 1354 nq = netdev_get_tx_queue(ndev, queue_id); 1355 bdp = txq->dirty_tx; 1356 1357 /* get next bdp of dirty_tx */ 1358 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1359 1360 while (bdp != READ_ONCE(txq->bd.cur)) { 1361 /* Order the load of bd.cur and cbd_sc */ 1362 rmb(); 1363 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1364 if (status & BD_ENET_TX_READY) 1365 break; 1366 1367 index = fec_enet_get_bd_index(bdp, &txq->bd); 1368 1369 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1370 skb = txq->tx_buf[index].buf_p; 1371 if (bdp->cbd_bufaddr && 1372 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1373 dma_unmap_single(&fep->pdev->dev, 1374 fec32_to_cpu(bdp->cbd_bufaddr), 1375 fec16_to_cpu(bdp->cbd_datlen), 1376 DMA_TO_DEVICE); 1377 bdp->cbd_bufaddr = cpu_to_fec32(0); 1378 if (!skb) 1379 goto tx_buf_done; 1380 } else { 1381 /* Tx processing cannot call any XDP (or page pool) APIs if 1382 * the "budget" is 0. Because NAPI is called with budget of 1383 * 0 (such as netpoll) indicates we may be in an IRQ context, 1384 * however, we can't use the page pool from IRQ context. 1385 */ 1386 if (unlikely(!budget)) 1387 break; 1388 1389 if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1390 xdpf = txq->tx_buf[index].buf_p; 1391 if (bdp->cbd_bufaddr) 1392 dma_unmap_single(&fep->pdev->dev, 1393 fec32_to_cpu(bdp->cbd_bufaddr), 1394 fec16_to_cpu(bdp->cbd_datlen), 1395 DMA_TO_DEVICE); 1396 } else { 1397 page = txq->tx_buf[index].buf_p; 1398 } 1399 1400 bdp->cbd_bufaddr = cpu_to_fec32(0); 1401 if (unlikely(!txq->tx_buf[index].buf_p)) { 1402 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1403 goto tx_buf_done; 1404 } 1405 1406 frame_len = fec16_to_cpu(bdp->cbd_datlen); 1407 } 1408 1409 /* Check for errors. */ 1410 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1411 BD_ENET_TX_RL | BD_ENET_TX_UN | 1412 BD_ENET_TX_CSL)) { 1413 ndev->stats.tx_errors++; 1414 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1415 ndev->stats.tx_heartbeat_errors++; 1416 if (status & BD_ENET_TX_LC) /* Late collision */ 1417 ndev->stats.tx_window_errors++; 1418 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1419 ndev->stats.tx_aborted_errors++; 1420 if (status & BD_ENET_TX_UN) /* Underrun */ 1421 ndev->stats.tx_fifo_errors++; 1422 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1423 ndev->stats.tx_carrier_errors++; 1424 } else { 1425 ndev->stats.tx_packets++; 1426 1427 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) 1428 ndev->stats.tx_bytes += skb->len; 1429 else 1430 ndev->stats.tx_bytes += frame_len; 1431 } 1432 1433 /* Deferred means some collisions occurred during transmit, 1434 * but we eventually sent the packet OK. 1435 */ 1436 if (status & BD_ENET_TX_DEF) 1437 ndev->stats.collisions++; 1438 1439 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1440 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1441 * are to time stamp the packet, so we still need to check time 1442 * stamping enabled flag. 1443 */ 1444 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1445 fep->hwts_tx_en) && fep->bufdesc_ex) { 1446 struct skb_shared_hwtstamps shhwtstamps; 1447 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1448 1449 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1450 skb_tstamp_tx(skb, &shhwtstamps); 1451 } 1452 1453 /* Free the sk buffer associated with this last transmit */ 1454 napi_consume_skb(skb, budget); 1455 } else if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1456 xdp_return_frame_rx_napi(xdpf); 1457 } else { /* recycle pages of XDP_TX frames */ 1458 /* The dma_sync_size = 0 as XDP_TX has already synced DMA for_device */ 1459 page_pool_put_page(page->pp, page, 0, true); 1460 } 1461 1462 txq->tx_buf[index].buf_p = NULL; 1463 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1464 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1465 1466 tx_buf_done: 1467 /* Make sure the update to bdp and tx_buf are performed 1468 * before dirty_tx 1469 */ 1470 wmb(); 1471 txq->dirty_tx = bdp; 1472 1473 /* Update pointer to next buffer descriptor to be transmitted */ 1474 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1475 1476 /* Since we have freed up a buffer, the ring is no longer full 1477 */ 1478 if (netif_tx_queue_stopped(nq)) { 1479 entries_free = fec_enet_get_free_txdesc_num(txq); 1480 if (entries_free >= txq->tx_wake_threshold) 1481 netif_tx_wake_queue(nq); 1482 } 1483 } 1484 1485 /* ERR006358: Keep the transmitter going */ 1486 if (bdp != txq->bd.cur && 1487 readl(txq->bd.reg_desc_active) == 0) 1488 writel(0, txq->bd.reg_desc_active); 1489 } 1490 1491 static void fec_enet_tx(struct net_device *ndev, int budget) 1492 { 1493 struct fec_enet_private *fep = netdev_priv(ndev); 1494 int i; 1495 1496 /* Make sure that AVB queues are processed first. */ 1497 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1498 fec_enet_tx_queue(ndev, i, budget); 1499 } 1500 1501 static void fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq, 1502 struct bufdesc *bdp, int index) 1503 { 1504 struct page *new_page; 1505 dma_addr_t phys_addr; 1506 1507 new_page = page_pool_dev_alloc_pages(rxq->page_pool); 1508 WARN_ON(!new_page); 1509 rxq->rx_skb_info[index].page = new_page; 1510 1511 rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM; 1512 phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM; 1513 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 1514 } 1515 1516 static u32 1517 fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog, 1518 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int cpu) 1519 { 1520 unsigned int sync, len = xdp->data_end - xdp->data; 1521 u32 ret = FEC_ENET_XDP_PASS; 1522 struct page *page; 1523 int err; 1524 u32 act; 1525 1526 act = bpf_prog_run_xdp(prog, xdp); 1527 1528 /* Due xdp_adjust_tail and xdp_adjust_head: DMA sync for_device cover 1529 * max len CPU touch 1530 */ 1531 sync = xdp->data_end - xdp->data; 1532 sync = max(sync, len); 1533 1534 switch (act) { 1535 case XDP_PASS: 1536 rxq->stats[RX_XDP_PASS]++; 1537 ret = FEC_ENET_XDP_PASS; 1538 break; 1539 1540 case XDP_REDIRECT: 1541 rxq->stats[RX_XDP_REDIRECT]++; 1542 err = xdp_do_redirect(fep->netdev, xdp, prog); 1543 if (unlikely(err)) 1544 goto xdp_err; 1545 1546 ret = FEC_ENET_XDP_REDIR; 1547 break; 1548 1549 case XDP_TX: 1550 rxq->stats[RX_XDP_TX]++; 1551 err = fec_enet_xdp_tx_xmit(fep, cpu, xdp, sync); 1552 if (unlikely(err)) { 1553 rxq->stats[RX_XDP_TX_ERRORS]++; 1554 goto xdp_err; 1555 } 1556 1557 ret = FEC_ENET_XDP_TX; 1558 break; 1559 1560 default: 1561 bpf_warn_invalid_xdp_action(fep->netdev, prog, act); 1562 fallthrough; 1563 1564 case XDP_ABORTED: 1565 fallthrough; /* handle aborts by dropping packet */ 1566 1567 case XDP_DROP: 1568 rxq->stats[RX_XDP_DROP]++; 1569 xdp_err: 1570 ret = FEC_ENET_XDP_CONSUMED; 1571 page = virt_to_head_page(xdp->data); 1572 page_pool_put_page(rxq->page_pool, page, sync, true); 1573 if (act != XDP_DROP) 1574 trace_xdp_exception(fep->netdev, prog, act); 1575 break; 1576 } 1577 1578 return ret; 1579 } 1580 1581 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1582 * When we update through the ring, if the next incoming buffer has 1583 * not been given to the system, we just set the empty indicator, 1584 * effectively tossing the packet. 1585 */ 1586 static int 1587 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1588 { 1589 struct fec_enet_private *fep = netdev_priv(ndev); 1590 struct fec_enet_priv_rx_q *rxq; 1591 struct bufdesc *bdp; 1592 unsigned short status; 1593 struct sk_buff *skb; 1594 ushort pkt_len; 1595 __u8 *data; 1596 int pkt_received = 0; 1597 struct bufdesc_ex *ebdp = NULL; 1598 bool vlan_packet_rcvd = false; 1599 u16 vlan_tag; 1600 int index = 0; 1601 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1602 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 1603 u32 ret, xdp_result = FEC_ENET_XDP_PASS; 1604 u32 data_start = FEC_ENET_XDP_HEADROOM; 1605 int cpu = smp_processor_id(); 1606 struct xdp_buff xdp; 1607 struct page *page; 1608 u32 sub_len = 4; 1609 1610 #if !defined(CONFIG_M5272) 1611 /*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of 1612 * FEC_RACC_SHIFT16 is set by default in the probe function. 1613 */ 1614 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1615 data_start += 2; 1616 sub_len += 2; 1617 } 1618 #endif 1619 1620 #ifdef CONFIG_M532x 1621 flush_cache_all(); 1622 #endif 1623 rxq = fep->rx_queue[queue_id]; 1624 1625 /* First, grab all of the stats for the incoming packet. 1626 * These get messed up if we get called due to a busy condition. 1627 */ 1628 bdp = rxq->bd.cur; 1629 xdp_init_buff(&xdp, PAGE_SIZE, &rxq->xdp_rxq); 1630 1631 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1632 1633 if (pkt_received >= budget) 1634 break; 1635 pkt_received++; 1636 1637 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT); 1638 1639 /* Check for errors. */ 1640 status ^= BD_ENET_RX_LAST; 1641 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1642 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1643 BD_ENET_RX_CL)) { 1644 ndev->stats.rx_errors++; 1645 if (status & BD_ENET_RX_OV) { 1646 /* FIFO overrun */ 1647 ndev->stats.rx_fifo_errors++; 1648 goto rx_processing_done; 1649 } 1650 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1651 | BD_ENET_RX_LAST)) { 1652 /* Frame too long or too short. */ 1653 ndev->stats.rx_length_errors++; 1654 if (status & BD_ENET_RX_LAST) 1655 netdev_err(ndev, "rcv is not +last\n"); 1656 } 1657 if (status & BD_ENET_RX_CR) /* CRC Error */ 1658 ndev->stats.rx_crc_errors++; 1659 /* Report late collisions as a frame error. */ 1660 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1661 ndev->stats.rx_frame_errors++; 1662 goto rx_processing_done; 1663 } 1664 1665 /* Process the incoming frame. */ 1666 ndev->stats.rx_packets++; 1667 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1668 ndev->stats.rx_bytes += pkt_len; 1669 1670 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1671 page = rxq->rx_skb_info[index].page; 1672 dma_sync_single_for_cpu(&fep->pdev->dev, 1673 fec32_to_cpu(bdp->cbd_bufaddr), 1674 pkt_len, 1675 DMA_FROM_DEVICE); 1676 prefetch(page_address(page)); 1677 fec_enet_update_cbd(rxq, bdp, index); 1678 1679 if (xdp_prog) { 1680 xdp_buff_clear_frags_flag(&xdp); 1681 /* subtract 16bit shift and FCS */ 1682 xdp_prepare_buff(&xdp, page_address(page), 1683 data_start, pkt_len - sub_len, false); 1684 ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, cpu); 1685 xdp_result |= ret; 1686 if (ret != FEC_ENET_XDP_PASS) 1687 goto rx_processing_done; 1688 } 1689 1690 /* The packet length includes FCS, but we don't want to 1691 * include that when passing upstream as it messes up 1692 * bridging applications. 1693 */ 1694 skb = build_skb(page_address(page), PAGE_SIZE); 1695 if (unlikely(!skb)) { 1696 page_pool_recycle_direct(rxq->page_pool, page); 1697 ndev->stats.rx_dropped++; 1698 1699 netdev_err_once(ndev, "build_skb failed!\n"); 1700 goto rx_processing_done; 1701 } 1702 1703 skb_reserve(skb, data_start); 1704 skb_put(skb, pkt_len - sub_len); 1705 skb_mark_for_recycle(skb); 1706 1707 if (unlikely(need_swap)) { 1708 data = page_address(page) + FEC_ENET_XDP_HEADROOM; 1709 swap_buffer(data, pkt_len); 1710 } 1711 data = skb->data; 1712 1713 /* Extract the enhanced buffer descriptor */ 1714 ebdp = NULL; 1715 if (fep->bufdesc_ex) 1716 ebdp = (struct bufdesc_ex *)bdp; 1717 1718 /* If this is a VLAN packet remove the VLAN Tag */ 1719 vlan_packet_rcvd = false; 1720 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1721 fep->bufdesc_ex && 1722 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1723 /* Push and remove the vlan tag */ 1724 struct vlan_hdr *vlan_header = 1725 (struct vlan_hdr *) (data + ETH_HLEN); 1726 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1727 1728 vlan_packet_rcvd = true; 1729 1730 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1731 skb_pull(skb, VLAN_HLEN); 1732 } 1733 1734 skb->protocol = eth_type_trans(skb, ndev); 1735 1736 /* Get receive timestamp from the skb */ 1737 if (fep->hwts_rx_en && fep->bufdesc_ex) 1738 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1739 skb_hwtstamps(skb)); 1740 1741 if (fep->bufdesc_ex && 1742 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1743 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1744 /* don't check it */ 1745 skb->ip_summed = CHECKSUM_UNNECESSARY; 1746 } else { 1747 skb_checksum_none_assert(skb); 1748 } 1749 } 1750 1751 /* Handle received VLAN packets */ 1752 if (vlan_packet_rcvd) 1753 __vlan_hwaccel_put_tag(skb, 1754 htons(ETH_P_8021Q), 1755 vlan_tag); 1756 1757 skb_record_rx_queue(skb, queue_id); 1758 napi_gro_receive(&fep->napi, skb); 1759 1760 rx_processing_done: 1761 /* Clear the status flags for this buffer */ 1762 status &= ~BD_ENET_RX_STATS; 1763 1764 /* Mark the buffer empty */ 1765 status |= BD_ENET_RX_EMPTY; 1766 1767 if (fep->bufdesc_ex) { 1768 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1769 1770 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1771 ebdp->cbd_prot = 0; 1772 ebdp->cbd_bdu = 0; 1773 } 1774 /* Make sure the updates to rest of the descriptor are 1775 * performed before transferring ownership. 1776 */ 1777 wmb(); 1778 bdp->cbd_sc = cpu_to_fec16(status); 1779 1780 /* Update BD pointer to next entry */ 1781 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1782 1783 /* Doing this here will keep the FEC running while we process 1784 * incoming frames. On a heavily loaded network, we should be 1785 * able to keep up at the expense of system resources. 1786 */ 1787 writel(0, rxq->bd.reg_desc_active); 1788 } 1789 rxq->bd.cur = bdp; 1790 1791 if (xdp_result & FEC_ENET_XDP_REDIR) 1792 xdp_do_flush(); 1793 1794 return pkt_received; 1795 } 1796 1797 static int fec_enet_rx(struct net_device *ndev, int budget) 1798 { 1799 struct fec_enet_private *fep = netdev_priv(ndev); 1800 int i, done = 0; 1801 1802 /* Make sure that AVB queues are processed first. */ 1803 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1804 done += fec_enet_rx_queue(ndev, budget - done, i); 1805 1806 return done; 1807 } 1808 1809 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1810 { 1811 uint int_events; 1812 1813 int_events = readl(fep->hwp + FEC_IEVENT); 1814 1815 /* Don't clear MDIO events, we poll for those */ 1816 int_events &= ~FEC_ENET_MII; 1817 1818 writel(int_events, fep->hwp + FEC_IEVENT); 1819 1820 return int_events != 0; 1821 } 1822 1823 static irqreturn_t 1824 fec_enet_interrupt(int irq, void *dev_id) 1825 { 1826 struct net_device *ndev = dev_id; 1827 struct fec_enet_private *fep = netdev_priv(ndev); 1828 irqreturn_t ret = IRQ_NONE; 1829 1830 if (fec_enet_collect_events(fep) && fep->link) { 1831 ret = IRQ_HANDLED; 1832 1833 if (napi_schedule_prep(&fep->napi)) { 1834 /* Disable interrupts */ 1835 writel(0, fep->hwp + FEC_IMASK); 1836 __napi_schedule(&fep->napi); 1837 } 1838 } 1839 1840 return ret; 1841 } 1842 1843 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1844 { 1845 struct net_device *ndev = napi->dev; 1846 struct fec_enet_private *fep = netdev_priv(ndev); 1847 int done = 0; 1848 1849 do { 1850 done += fec_enet_rx(ndev, budget - done); 1851 fec_enet_tx(ndev, budget); 1852 } while ((done < budget) && fec_enet_collect_events(fep)); 1853 1854 if (done < budget) { 1855 napi_complete_done(napi, done); 1856 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1857 } 1858 1859 return done; 1860 } 1861 1862 /* ------------------------------------------------------------------------- */ 1863 static int fec_get_mac(struct net_device *ndev) 1864 { 1865 struct fec_enet_private *fep = netdev_priv(ndev); 1866 unsigned char *iap, tmpaddr[ETH_ALEN]; 1867 int ret; 1868 1869 /* 1870 * try to get mac address in following order: 1871 * 1872 * 1) module parameter via kernel command line in form 1873 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1874 */ 1875 iap = macaddr; 1876 1877 /* 1878 * 2) from device tree data 1879 */ 1880 if (!is_valid_ether_addr(iap)) { 1881 struct device_node *np = fep->pdev->dev.of_node; 1882 if (np) { 1883 ret = of_get_mac_address(np, tmpaddr); 1884 if (!ret) 1885 iap = tmpaddr; 1886 else if (ret == -EPROBE_DEFER) 1887 return ret; 1888 } 1889 } 1890 1891 /* 1892 * 3) from flash or fuse (via platform data) 1893 */ 1894 if (!is_valid_ether_addr(iap)) { 1895 #ifdef CONFIG_M5272 1896 if (FEC_FLASHMAC) 1897 iap = (unsigned char *)FEC_FLASHMAC; 1898 #else 1899 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1900 1901 if (pdata) 1902 iap = (unsigned char *)&pdata->mac; 1903 #endif 1904 } 1905 1906 /* 1907 * 4) FEC mac registers set by bootloader 1908 */ 1909 if (!is_valid_ether_addr(iap)) { 1910 *((__be32 *) &tmpaddr[0]) = 1911 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1912 *((__be16 *) &tmpaddr[4]) = 1913 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1914 iap = &tmpaddr[0]; 1915 } 1916 1917 /* 1918 * 5) random mac address 1919 */ 1920 if (!is_valid_ether_addr(iap)) { 1921 /* Report it and use a random ethernet address instead */ 1922 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 1923 eth_hw_addr_random(ndev); 1924 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 1925 ndev->dev_addr); 1926 return 0; 1927 } 1928 1929 /* Adjust MAC if using macaddr */ 1930 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0); 1931 1932 return 0; 1933 } 1934 1935 /* ------------------------------------------------------------------------- */ 1936 1937 /* 1938 * Phy section 1939 */ 1940 static void fec_enet_adjust_link(struct net_device *ndev) 1941 { 1942 struct fec_enet_private *fep = netdev_priv(ndev); 1943 struct phy_device *phy_dev = ndev->phydev; 1944 int status_change = 0; 1945 1946 /* 1947 * If the netdev is down, or is going down, we're not interested 1948 * in link state events, so just mark our idea of the link as down 1949 * and ignore the event. 1950 */ 1951 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1952 fep->link = 0; 1953 } else if (phy_dev->link) { 1954 if (!fep->link) { 1955 fep->link = phy_dev->link; 1956 status_change = 1; 1957 } 1958 1959 if (fep->full_duplex != phy_dev->duplex) { 1960 fep->full_duplex = phy_dev->duplex; 1961 status_change = 1; 1962 } 1963 1964 if (phy_dev->speed != fep->speed) { 1965 fep->speed = phy_dev->speed; 1966 status_change = 1; 1967 } 1968 1969 /* if any of the above changed restart the FEC */ 1970 if (status_change) { 1971 napi_disable(&fep->napi); 1972 netif_tx_lock_bh(ndev); 1973 fec_restart(ndev); 1974 netif_tx_wake_all_queues(ndev); 1975 netif_tx_unlock_bh(ndev); 1976 napi_enable(&fep->napi); 1977 } 1978 } else { 1979 if (fep->link) { 1980 napi_disable(&fep->napi); 1981 netif_tx_lock_bh(ndev); 1982 fec_stop(ndev); 1983 netif_tx_unlock_bh(ndev); 1984 napi_enable(&fep->napi); 1985 fep->link = phy_dev->link; 1986 status_change = 1; 1987 } 1988 } 1989 1990 if (status_change) 1991 phy_print_status(phy_dev); 1992 } 1993 1994 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 1995 { 1996 uint ievent; 1997 int ret; 1998 1999 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 2000 ievent & FEC_ENET_MII, 2, 30000); 2001 2002 if (!ret) 2003 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2004 2005 return ret; 2006 } 2007 2008 static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) 2009 { 2010 struct fec_enet_private *fep = bus->priv; 2011 struct device *dev = &fep->pdev->dev; 2012 int ret = 0, frame_start, frame_addr, frame_op; 2013 2014 ret = pm_runtime_resume_and_get(dev); 2015 if (ret < 0) 2016 return ret; 2017 2018 /* C22 read */ 2019 frame_op = FEC_MMFR_OP_READ; 2020 frame_start = FEC_MMFR_ST; 2021 frame_addr = regnum; 2022 2023 /* start a read op */ 2024 writel(frame_start | frame_op | 2025 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2026 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2027 2028 /* wait for end of transfer */ 2029 ret = fec_enet_mdio_wait(fep); 2030 if (ret) { 2031 netdev_err(fep->netdev, "MDIO read timeout\n"); 2032 goto out; 2033 } 2034 2035 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2036 2037 out: 2038 pm_runtime_mark_last_busy(dev); 2039 pm_runtime_put_autosuspend(dev); 2040 2041 return ret; 2042 } 2043 2044 static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id, 2045 int devad, int regnum) 2046 { 2047 struct fec_enet_private *fep = bus->priv; 2048 struct device *dev = &fep->pdev->dev; 2049 int ret = 0, frame_start, frame_op; 2050 2051 ret = pm_runtime_resume_and_get(dev); 2052 if (ret < 0) 2053 return ret; 2054 2055 frame_start = FEC_MMFR_ST_C45; 2056 2057 /* write address */ 2058 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2059 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2060 FEC_MMFR_TA | (regnum & 0xFFFF), 2061 fep->hwp + FEC_MII_DATA); 2062 2063 /* wait for end of transfer */ 2064 ret = fec_enet_mdio_wait(fep); 2065 if (ret) { 2066 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2067 goto out; 2068 } 2069 2070 frame_op = FEC_MMFR_OP_READ_C45; 2071 2072 /* start a read op */ 2073 writel(frame_start | frame_op | 2074 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2075 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2076 2077 /* wait for end of transfer */ 2078 ret = fec_enet_mdio_wait(fep); 2079 if (ret) { 2080 netdev_err(fep->netdev, "MDIO read timeout\n"); 2081 goto out; 2082 } 2083 2084 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2085 2086 out: 2087 pm_runtime_mark_last_busy(dev); 2088 pm_runtime_put_autosuspend(dev); 2089 2090 return ret; 2091 } 2092 2093 static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, 2094 u16 value) 2095 { 2096 struct fec_enet_private *fep = bus->priv; 2097 struct device *dev = &fep->pdev->dev; 2098 int ret, frame_start, frame_addr; 2099 2100 ret = pm_runtime_resume_and_get(dev); 2101 if (ret < 0) 2102 return ret; 2103 2104 /* C22 write */ 2105 frame_start = FEC_MMFR_ST; 2106 frame_addr = regnum; 2107 2108 /* start a write op */ 2109 writel(frame_start | FEC_MMFR_OP_WRITE | 2110 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2111 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2112 fep->hwp + FEC_MII_DATA); 2113 2114 /* wait for end of transfer */ 2115 ret = fec_enet_mdio_wait(fep); 2116 if (ret) 2117 netdev_err(fep->netdev, "MDIO write timeout\n"); 2118 2119 pm_runtime_mark_last_busy(dev); 2120 pm_runtime_put_autosuspend(dev); 2121 2122 return ret; 2123 } 2124 2125 static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id, 2126 int devad, int regnum, u16 value) 2127 { 2128 struct fec_enet_private *fep = bus->priv; 2129 struct device *dev = &fep->pdev->dev; 2130 int ret, frame_start; 2131 2132 ret = pm_runtime_resume_and_get(dev); 2133 if (ret < 0) 2134 return ret; 2135 2136 frame_start = FEC_MMFR_ST_C45; 2137 2138 /* write address */ 2139 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2140 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2141 FEC_MMFR_TA | (regnum & 0xFFFF), 2142 fep->hwp + FEC_MII_DATA); 2143 2144 /* wait for end of transfer */ 2145 ret = fec_enet_mdio_wait(fep); 2146 if (ret) { 2147 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2148 goto out; 2149 } 2150 2151 /* start a write op */ 2152 writel(frame_start | FEC_MMFR_OP_WRITE | 2153 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2154 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2155 fep->hwp + FEC_MII_DATA); 2156 2157 /* wait for end of transfer */ 2158 ret = fec_enet_mdio_wait(fep); 2159 if (ret) 2160 netdev_err(fep->netdev, "MDIO write timeout\n"); 2161 2162 out: 2163 pm_runtime_mark_last_busy(dev); 2164 pm_runtime_put_autosuspend(dev); 2165 2166 return ret; 2167 } 2168 2169 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 2170 { 2171 struct fec_enet_private *fep = netdev_priv(ndev); 2172 struct phy_device *phy_dev = ndev->phydev; 2173 2174 if (phy_dev) { 2175 phy_reset_after_clk_enable(phy_dev); 2176 } else if (fep->phy_node) { 2177 /* 2178 * If the PHY still is not bound to the MAC, but there is 2179 * OF PHY node and a matching PHY device instance already, 2180 * use the OF PHY node to obtain the PHY device instance, 2181 * and then use that PHY device instance when triggering 2182 * the PHY reset. 2183 */ 2184 phy_dev = of_phy_find_device(fep->phy_node); 2185 phy_reset_after_clk_enable(phy_dev); 2186 put_device(&phy_dev->mdio.dev); 2187 } 2188 } 2189 2190 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 2191 { 2192 struct fec_enet_private *fep = netdev_priv(ndev); 2193 int ret; 2194 2195 if (enable) { 2196 ret = clk_prepare_enable(fep->clk_enet_out); 2197 if (ret) 2198 return ret; 2199 2200 if (fep->clk_ptp) { 2201 mutex_lock(&fep->ptp_clk_mutex); 2202 ret = clk_prepare_enable(fep->clk_ptp); 2203 if (ret) { 2204 mutex_unlock(&fep->ptp_clk_mutex); 2205 goto failed_clk_ptp; 2206 } else { 2207 fep->ptp_clk_on = true; 2208 } 2209 mutex_unlock(&fep->ptp_clk_mutex); 2210 } 2211 2212 ret = clk_prepare_enable(fep->clk_ref); 2213 if (ret) 2214 goto failed_clk_ref; 2215 2216 ret = clk_prepare_enable(fep->clk_2x_txclk); 2217 if (ret) 2218 goto failed_clk_2x_txclk; 2219 2220 fec_enet_phy_reset_after_clk_enable(ndev); 2221 } else { 2222 clk_disable_unprepare(fep->clk_enet_out); 2223 if (fep->clk_ptp) { 2224 mutex_lock(&fep->ptp_clk_mutex); 2225 clk_disable_unprepare(fep->clk_ptp); 2226 fep->ptp_clk_on = false; 2227 mutex_unlock(&fep->ptp_clk_mutex); 2228 } 2229 clk_disable_unprepare(fep->clk_ref); 2230 clk_disable_unprepare(fep->clk_2x_txclk); 2231 } 2232 2233 return 0; 2234 2235 failed_clk_2x_txclk: 2236 if (fep->clk_ref) 2237 clk_disable_unprepare(fep->clk_ref); 2238 failed_clk_ref: 2239 if (fep->clk_ptp) { 2240 mutex_lock(&fep->ptp_clk_mutex); 2241 clk_disable_unprepare(fep->clk_ptp); 2242 fep->ptp_clk_on = false; 2243 mutex_unlock(&fep->ptp_clk_mutex); 2244 } 2245 failed_clk_ptp: 2246 clk_disable_unprepare(fep->clk_enet_out); 2247 2248 return ret; 2249 } 2250 2251 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep, 2252 struct device_node *np) 2253 { 2254 u32 rgmii_tx_delay, rgmii_rx_delay; 2255 2256 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ 2257 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { 2258 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) { 2259 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); 2260 return -EINVAL; 2261 } else if (rgmii_tx_delay == 2000) { 2262 fep->rgmii_txc_dly = true; 2263 } 2264 } 2265 2266 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */ 2267 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { 2268 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) { 2269 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); 2270 return -EINVAL; 2271 } else if (rgmii_rx_delay == 2000) { 2272 fep->rgmii_rxc_dly = true; 2273 } 2274 } 2275 2276 return 0; 2277 } 2278 2279 static int fec_enet_mii_probe(struct net_device *ndev) 2280 { 2281 struct fec_enet_private *fep = netdev_priv(ndev); 2282 struct phy_device *phy_dev = NULL; 2283 char mdio_bus_id[MII_BUS_ID_SIZE]; 2284 char phy_name[MII_BUS_ID_SIZE + 3]; 2285 int phy_id; 2286 int dev_id = fep->dev_id; 2287 2288 if (fep->phy_node) { 2289 phy_dev = of_phy_connect(ndev, fep->phy_node, 2290 &fec_enet_adjust_link, 0, 2291 fep->phy_interface); 2292 if (!phy_dev) { 2293 netdev_err(ndev, "Unable to connect to phy\n"); 2294 return -ENODEV; 2295 } 2296 } else { 2297 /* check for attached phy */ 2298 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2299 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2300 continue; 2301 if (dev_id--) 2302 continue; 2303 strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2304 break; 2305 } 2306 2307 if (phy_id >= PHY_MAX_ADDR) { 2308 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2309 strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2310 phy_id = 0; 2311 } 2312 2313 snprintf(phy_name, sizeof(phy_name), 2314 PHY_ID_FMT, mdio_bus_id, phy_id); 2315 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2316 fep->phy_interface); 2317 } 2318 2319 if (IS_ERR(phy_dev)) { 2320 netdev_err(ndev, "could not attach to PHY\n"); 2321 return PTR_ERR(phy_dev); 2322 } 2323 2324 /* mask with MAC supported features */ 2325 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2326 phy_set_max_speed(phy_dev, 1000); 2327 phy_remove_link_mode(phy_dev, 2328 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2329 #if !defined(CONFIG_M5272) 2330 phy_support_sym_pause(phy_dev); 2331 #endif 2332 } 2333 else 2334 phy_set_max_speed(phy_dev, 100); 2335 2336 fep->link = 0; 2337 fep->full_duplex = 0; 2338 2339 phy_dev->mac_managed_pm = true; 2340 2341 phy_attached_info(phy_dev); 2342 2343 return 0; 2344 } 2345 2346 static int fec_enet_mii_init(struct platform_device *pdev) 2347 { 2348 static struct mii_bus *fec0_mii_bus; 2349 struct net_device *ndev = platform_get_drvdata(pdev); 2350 struct fec_enet_private *fep = netdev_priv(ndev); 2351 bool suppress_preamble = false; 2352 struct device_node *node; 2353 int err = -ENXIO; 2354 u32 mii_speed, holdtime; 2355 u32 bus_freq; 2356 2357 /* 2358 * The i.MX28 dual fec interfaces are not equal. 2359 * Here are the differences: 2360 * 2361 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2362 * - fec0 acts as the 1588 time master while fec1 is slave 2363 * - external phys can only be configured by fec0 2364 * 2365 * That is to say fec1 can not work independently. It only works 2366 * when fec0 is working. The reason behind this design is that the 2367 * second interface is added primarily for Switch mode. 2368 * 2369 * Because of the last point above, both phys are attached on fec0 2370 * mdio interface in board design, and need to be configured by 2371 * fec0 mii_bus. 2372 */ 2373 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2374 /* fec1 uses fec0 mii_bus */ 2375 if (mii_cnt && fec0_mii_bus) { 2376 fep->mii_bus = fec0_mii_bus; 2377 mii_cnt++; 2378 return 0; 2379 } 2380 return -ENOENT; 2381 } 2382 2383 bus_freq = 2500000; /* 2.5MHz by default */ 2384 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2385 if (node) { 2386 of_property_read_u32(node, "clock-frequency", &bus_freq); 2387 suppress_preamble = of_property_read_bool(node, 2388 "suppress-preamble"); 2389 } 2390 2391 /* 2392 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2393 * 2394 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2395 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2396 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2397 * document. 2398 */ 2399 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2400 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2401 mii_speed--; 2402 if (mii_speed > 63) { 2403 dev_err(&pdev->dev, 2404 "fec clock (%lu) too fast to get right mii speed\n", 2405 clk_get_rate(fep->clk_ipg)); 2406 err = -EINVAL; 2407 goto err_out; 2408 } 2409 2410 /* 2411 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2412 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2413 * versions are RAZ there, so just ignore the difference and write the 2414 * register always. 2415 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2416 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2417 * output. 2418 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2419 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2420 * holdtime cannot result in a value greater than 3. 2421 */ 2422 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2423 2424 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2425 2426 if (suppress_preamble) 2427 fep->phy_speed |= BIT(7); 2428 2429 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2430 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2431 * MII event generation condition: 2432 * - writing MSCR: 2433 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2434 * mscr_reg_data_in[7:0] != 0 2435 * - writing MMFR: 2436 * - mscr[7:0]_not_zero 2437 */ 2438 writel(0, fep->hwp + FEC_MII_DATA); 2439 } 2440 2441 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2442 2443 /* Clear any pending transaction complete indication */ 2444 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2445 2446 fep->mii_bus = mdiobus_alloc(); 2447 if (fep->mii_bus == NULL) { 2448 err = -ENOMEM; 2449 goto err_out; 2450 } 2451 2452 fep->mii_bus->name = "fec_enet_mii_bus"; 2453 fep->mii_bus->read = fec_enet_mdio_read_c22; 2454 fep->mii_bus->write = fec_enet_mdio_write_c22; 2455 if (fep->quirks & FEC_QUIRK_HAS_MDIO_C45) { 2456 fep->mii_bus->read_c45 = fec_enet_mdio_read_c45; 2457 fep->mii_bus->write_c45 = fec_enet_mdio_write_c45; 2458 } 2459 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2460 pdev->name, fep->dev_id + 1); 2461 fep->mii_bus->priv = fep; 2462 fep->mii_bus->parent = &pdev->dev; 2463 2464 err = of_mdiobus_register(fep->mii_bus, node); 2465 if (err) 2466 goto err_out_free_mdiobus; 2467 of_node_put(node); 2468 2469 mii_cnt++; 2470 2471 /* save fec0 mii_bus */ 2472 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2473 fec0_mii_bus = fep->mii_bus; 2474 2475 return 0; 2476 2477 err_out_free_mdiobus: 2478 mdiobus_free(fep->mii_bus); 2479 err_out: 2480 of_node_put(node); 2481 return err; 2482 } 2483 2484 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2485 { 2486 if (--mii_cnt == 0) { 2487 mdiobus_unregister(fep->mii_bus); 2488 mdiobus_free(fep->mii_bus); 2489 } 2490 } 2491 2492 static void fec_enet_get_drvinfo(struct net_device *ndev, 2493 struct ethtool_drvinfo *info) 2494 { 2495 struct fec_enet_private *fep = netdev_priv(ndev); 2496 2497 strscpy(info->driver, fep->pdev->dev.driver->name, 2498 sizeof(info->driver)); 2499 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2500 } 2501 2502 static int fec_enet_get_regs_len(struct net_device *ndev) 2503 { 2504 struct fec_enet_private *fep = netdev_priv(ndev); 2505 struct resource *r; 2506 int s = 0; 2507 2508 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2509 if (r) 2510 s = resource_size(r); 2511 2512 return s; 2513 } 2514 2515 /* List of registers that can be safety be read to dump them with ethtool */ 2516 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2517 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2518 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2519 static __u32 fec_enet_register_version = 2; 2520 static u32 fec_enet_register_offset[] = { 2521 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2522 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2523 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2524 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2525 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2526 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2527 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2528 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2529 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2530 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2531 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2532 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2533 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2534 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2535 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2536 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2537 RMON_T_P_GTE2048, RMON_T_OCTETS, 2538 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2539 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2540 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2541 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2542 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2543 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2544 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2545 RMON_R_P_GTE2048, RMON_R_OCTETS, 2546 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2547 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2548 }; 2549 /* for i.MX6ul */ 2550 static u32 fec_enet_register_offset_6ul[] = { 2551 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2552 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2553 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0, 2554 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, 2555 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0, 2556 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2557 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, 2558 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2559 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2560 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2561 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2562 RMON_T_P_GTE2048, RMON_T_OCTETS, 2563 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2564 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2565 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2566 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2567 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2568 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2569 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2570 RMON_R_P_GTE2048, RMON_R_OCTETS, 2571 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2572 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2573 }; 2574 #else 2575 static __u32 fec_enet_register_version = 1; 2576 static u32 fec_enet_register_offset[] = { 2577 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2578 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2579 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2580 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2581 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2582 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2583 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2584 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2585 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2586 }; 2587 #endif 2588 2589 static void fec_enet_get_regs(struct net_device *ndev, 2590 struct ethtool_regs *regs, void *regbuf) 2591 { 2592 struct fec_enet_private *fep = netdev_priv(ndev); 2593 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2594 struct device *dev = &fep->pdev->dev; 2595 u32 *buf = (u32 *)regbuf; 2596 u32 i, off; 2597 int ret; 2598 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2599 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2600 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2601 u32 *reg_list; 2602 u32 reg_cnt; 2603 2604 if (!of_machine_is_compatible("fsl,imx6ul")) { 2605 reg_list = fec_enet_register_offset; 2606 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2607 } else { 2608 reg_list = fec_enet_register_offset_6ul; 2609 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul); 2610 } 2611 #else 2612 /* coldfire */ 2613 static u32 *reg_list = fec_enet_register_offset; 2614 static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2615 #endif 2616 ret = pm_runtime_resume_and_get(dev); 2617 if (ret < 0) 2618 return; 2619 2620 regs->version = fec_enet_register_version; 2621 2622 memset(buf, 0, regs->len); 2623 2624 for (i = 0; i < reg_cnt; i++) { 2625 off = reg_list[i]; 2626 2627 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2628 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2629 continue; 2630 2631 off >>= 2; 2632 buf[off] = readl(&theregs[off]); 2633 } 2634 2635 pm_runtime_mark_last_busy(dev); 2636 pm_runtime_put_autosuspend(dev); 2637 } 2638 2639 static int fec_enet_get_ts_info(struct net_device *ndev, 2640 struct ethtool_ts_info *info) 2641 { 2642 struct fec_enet_private *fep = netdev_priv(ndev); 2643 2644 if (fep->bufdesc_ex) { 2645 2646 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2647 SOF_TIMESTAMPING_RX_SOFTWARE | 2648 SOF_TIMESTAMPING_SOFTWARE | 2649 SOF_TIMESTAMPING_TX_HARDWARE | 2650 SOF_TIMESTAMPING_RX_HARDWARE | 2651 SOF_TIMESTAMPING_RAW_HARDWARE; 2652 if (fep->ptp_clock) 2653 info->phc_index = ptp_clock_index(fep->ptp_clock); 2654 else 2655 info->phc_index = -1; 2656 2657 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2658 (1 << HWTSTAMP_TX_ON); 2659 2660 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2661 (1 << HWTSTAMP_FILTER_ALL); 2662 return 0; 2663 } else { 2664 return ethtool_op_get_ts_info(ndev, info); 2665 } 2666 } 2667 2668 #if !defined(CONFIG_M5272) 2669 2670 static void fec_enet_get_pauseparam(struct net_device *ndev, 2671 struct ethtool_pauseparam *pause) 2672 { 2673 struct fec_enet_private *fep = netdev_priv(ndev); 2674 2675 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2676 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2677 pause->rx_pause = pause->tx_pause; 2678 } 2679 2680 static int fec_enet_set_pauseparam(struct net_device *ndev, 2681 struct ethtool_pauseparam *pause) 2682 { 2683 struct fec_enet_private *fep = netdev_priv(ndev); 2684 2685 if (!ndev->phydev) 2686 return -ENODEV; 2687 2688 if (pause->tx_pause != pause->rx_pause) { 2689 netdev_info(ndev, 2690 "hardware only support enable/disable both tx and rx"); 2691 return -EINVAL; 2692 } 2693 2694 fep->pause_flag = 0; 2695 2696 /* tx pause must be same as rx pause */ 2697 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2698 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2699 2700 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2701 pause->autoneg); 2702 2703 if (pause->autoneg) { 2704 if (netif_running(ndev)) 2705 fec_stop(ndev); 2706 phy_start_aneg(ndev->phydev); 2707 } 2708 if (netif_running(ndev)) { 2709 napi_disable(&fep->napi); 2710 netif_tx_lock_bh(ndev); 2711 fec_restart(ndev); 2712 netif_tx_wake_all_queues(ndev); 2713 netif_tx_unlock_bh(ndev); 2714 napi_enable(&fep->napi); 2715 } 2716 2717 return 0; 2718 } 2719 2720 static const struct fec_stat { 2721 char name[ETH_GSTRING_LEN]; 2722 u16 offset; 2723 } fec_stats[] = { 2724 /* RMON TX */ 2725 { "tx_dropped", RMON_T_DROP }, 2726 { "tx_packets", RMON_T_PACKETS }, 2727 { "tx_broadcast", RMON_T_BC_PKT }, 2728 { "tx_multicast", RMON_T_MC_PKT }, 2729 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2730 { "tx_undersize", RMON_T_UNDERSIZE }, 2731 { "tx_oversize", RMON_T_OVERSIZE }, 2732 { "tx_fragment", RMON_T_FRAG }, 2733 { "tx_jabber", RMON_T_JAB }, 2734 { "tx_collision", RMON_T_COL }, 2735 { "tx_64byte", RMON_T_P64 }, 2736 { "tx_65to127byte", RMON_T_P65TO127 }, 2737 { "tx_128to255byte", RMON_T_P128TO255 }, 2738 { "tx_256to511byte", RMON_T_P256TO511 }, 2739 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2740 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2741 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2742 { "tx_octets", RMON_T_OCTETS }, 2743 2744 /* IEEE TX */ 2745 { "IEEE_tx_drop", IEEE_T_DROP }, 2746 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2747 { "IEEE_tx_1col", IEEE_T_1COL }, 2748 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2749 { "IEEE_tx_def", IEEE_T_DEF }, 2750 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2751 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2752 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2753 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2754 { "IEEE_tx_sqe", IEEE_T_SQE }, 2755 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2756 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2757 2758 /* RMON RX */ 2759 { "rx_packets", RMON_R_PACKETS }, 2760 { "rx_broadcast", RMON_R_BC_PKT }, 2761 { "rx_multicast", RMON_R_MC_PKT }, 2762 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2763 { "rx_undersize", RMON_R_UNDERSIZE }, 2764 { "rx_oversize", RMON_R_OVERSIZE }, 2765 { "rx_fragment", RMON_R_FRAG }, 2766 { "rx_jabber", RMON_R_JAB }, 2767 { "rx_64byte", RMON_R_P64 }, 2768 { "rx_65to127byte", RMON_R_P65TO127 }, 2769 { "rx_128to255byte", RMON_R_P128TO255 }, 2770 { "rx_256to511byte", RMON_R_P256TO511 }, 2771 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2772 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2773 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2774 { "rx_octets", RMON_R_OCTETS }, 2775 2776 /* IEEE RX */ 2777 { "IEEE_rx_drop", IEEE_R_DROP }, 2778 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2779 { "IEEE_rx_crc", IEEE_R_CRC }, 2780 { "IEEE_rx_align", IEEE_R_ALIGN }, 2781 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2782 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2783 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2784 }; 2785 2786 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2787 2788 static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = { 2789 "rx_xdp_redirect", /* RX_XDP_REDIRECT = 0, */ 2790 "rx_xdp_pass", /* RX_XDP_PASS, */ 2791 "rx_xdp_drop", /* RX_XDP_DROP, */ 2792 "rx_xdp_tx", /* RX_XDP_TX, */ 2793 "rx_xdp_tx_errors", /* RX_XDP_TX_ERRORS, */ 2794 "tx_xdp_xmit", /* TX_XDP_XMIT, */ 2795 "tx_xdp_xmit_errors", /* TX_XDP_XMIT_ERRORS, */ 2796 }; 2797 2798 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2799 { 2800 struct fec_enet_private *fep = netdev_priv(dev); 2801 int i; 2802 2803 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2804 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2805 } 2806 2807 static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data) 2808 { 2809 u64 xdp_stats[XDP_STATS_TOTAL] = { 0 }; 2810 struct fec_enet_priv_rx_q *rxq; 2811 int i, j; 2812 2813 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2814 rxq = fep->rx_queue[i]; 2815 2816 for (j = 0; j < XDP_STATS_TOTAL; j++) 2817 xdp_stats[j] += rxq->stats[j]; 2818 } 2819 2820 memcpy(data, xdp_stats, sizeof(xdp_stats)); 2821 } 2822 2823 static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data) 2824 { 2825 #ifdef CONFIG_PAGE_POOL_STATS 2826 struct page_pool_stats stats = {}; 2827 struct fec_enet_priv_rx_q *rxq; 2828 int i; 2829 2830 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2831 rxq = fep->rx_queue[i]; 2832 2833 if (!rxq->page_pool) 2834 continue; 2835 2836 page_pool_get_stats(rxq->page_pool, &stats); 2837 } 2838 2839 page_pool_ethtool_stats_get(data, &stats); 2840 #endif 2841 } 2842 2843 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2844 struct ethtool_stats *stats, u64 *data) 2845 { 2846 struct fec_enet_private *fep = netdev_priv(dev); 2847 2848 if (netif_running(dev)) 2849 fec_enet_update_ethtool_stats(dev); 2850 2851 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2852 data += FEC_STATS_SIZE / sizeof(u64); 2853 2854 fec_enet_get_xdp_stats(fep, data); 2855 data += XDP_STATS_TOTAL; 2856 2857 fec_enet_page_pool_stats(fep, data); 2858 } 2859 2860 static void fec_enet_get_strings(struct net_device *netdev, 2861 u32 stringset, u8 *data) 2862 { 2863 int i; 2864 switch (stringset) { 2865 case ETH_SS_STATS: 2866 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) { 2867 ethtool_sprintf(&data, "%s", fec_stats[i].name); 2868 } 2869 for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) { 2870 ethtool_sprintf(&data, "%s", fec_xdp_stat_strs[i]); 2871 } 2872 page_pool_ethtool_stats_get_strings(data); 2873 2874 break; 2875 case ETH_SS_TEST: 2876 net_selftest_get_strings(data); 2877 break; 2878 } 2879 } 2880 2881 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2882 { 2883 int count; 2884 2885 switch (sset) { 2886 case ETH_SS_STATS: 2887 count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL; 2888 count += page_pool_ethtool_stats_get_count(); 2889 return count; 2890 2891 case ETH_SS_TEST: 2892 return net_selftest_get_count(); 2893 default: 2894 return -EOPNOTSUPP; 2895 } 2896 } 2897 2898 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2899 { 2900 struct fec_enet_private *fep = netdev_priv(dev); 2901 struct fec_enet_priv_rx_q *rxq; 2902 int i, j; 2903 2904 /* Disable MIB statistics counters */ 2905 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2906 2907 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2908 writel(0, fep->hwp + fec_stats[i].offset); 2909 2910 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2911 rxq = fep->rx_queue[i]; 2912 for (j = 0; j < XDP_STATS_TOTAL; j++) 2913 rxq->stats[j] = 0; 2914 } 2915 2916 /* Don't disable MIB statistics counters */ 2917 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2918 } 2919 2920 #else /* !defined(CONFIG_M5272) */ 2921 #define FEC_STATS_SIZE 0 2922 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2923 { 2924 } 2925 2926 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2927 { 2928 } 2929 #endif /* !defined(CONFIG_M5272) */ 2930 2931 /* ITR clock source is enet system clock (clk_ahb). 2932 * TCTT unit is cycle_ns * 64 cycle 2933 * So, the ICTT value = X us / (cycle_ns * 64) 2934 */ 2935 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2936 { 2937 struct fec_enet_private *fep = netdev_priv(ndev); 2938 2939 return us * (fep->itr_clk_rate / 64000) / 1000; 2940 } 2941 2942 /* Set threshold for interrupt coalescing */ 2943 static void fec_enet_itr_coal_set(struct net_device *ndev) 2944 { 2945 struct fec_enet_private *fep = netdev_priv(ndev); 2946 int rx_itr, tx_itr; 2947 2948 /* Must be greater than zero to avoid unpredictable behavior */ 2949 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2950 !fep->tx_time_itr || !fep->tx_pkts_itr) 2951 return; 2952 2953 /* Select enet system clock as Interrupt Coalescing 2954 * timer Clock Source 2955 */ 2956 rx_itr = FEC_ITR_CLK_SEL; 2957 tx_itr = FEC_ITR_CLK_SEL; 2958 2959 /* set ICFT and ICTT */ 2960 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2961 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2962 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2963 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2964 2965 rx_itr |= FEC_ITR_EN; 2966 tx_itr |= FEC_ITR_EN; 2967 2968 writel(tx_itr, fep->hwp + FEC_TXIC0); 2969 writel(rx_itr, fep->hwp + FEC_RXIC0); 2970 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 2971 writel(tx_itr, fep->hwp + FEC_TXIC1); 2972 writel(rx_itr, fep->hwp + FEC_RXIC1); 2973 writel(tx_itr, fep->hwp + FEC_TXIC2); 2974 writel(rx_itr, fep->hwp + FEC_RXIC2); 2975 } 2976 } 2977 2978 static int fec_enet_get_coalesce(struct net_device *ndev, 2979 struct ethtool_coalesce *ec, 2980 struct kernel_ethtool_coalesce *kernel_coal, 2981 struct netlink_ext_ack *extack) 2982 { 2983 struct fec_enet_private *fep = netdev_priv(ndev); 2984 2985 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2986 return -EOPNOTSUPP; 2987 2988 ec->rx_coalesce_usecs = fep->rx_time_itr; 2989 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2990 2991 ec->tx_coalesce_usecs = fep->tx_time_itr; 2992 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2993 2994 return 0; 2995 } 2996 2997 static int fec_enet_set_coalesce(struct net_device *ndev, 2998 struct ethtool_coalesce *ec, 2999 struct kernel_ethtool_coalesce *kernel_coal, 3000 struct netlink_ext_ack *extack) 3001 { 3002 struct fec_enet_private *fep = netdev_priv(ndev); 3003 struct device *dev = &fep->pdev->dev; 3004 unsigned int cycle; 3005 3006 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3007 return -EOPNOTSUPP; 3008 3009 if (ec->rx_max_coalesced_frames > 255) { 3010 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 3011 return -EINVAL; 3012 } 3013 3014 if (ec->tx_max_coalesced_frames > 255) { 3015 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 3016 return -EINVAL; 3017 } 3018 3019 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 3020 if (cycle > 0xFFFF) { 3021 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 3022 return -EINVAL; 3023 } 3024 3025 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 3026 if (cycle > 0xFFFF) { 3027 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 3028 return -EINVAL; 3029 } 3030 3031 fep->rx_time_itr = ec->rx_coalesce_usecs; 3032 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 3033 3034 fep->tx_time_itr = ec->tx_coalesce_usecs; 3035 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 3036 3037 fec_enet_itr_coal_set(ndev); 3038 3039 return 0; 3040 } 3041 3042 /* LPI Sleep Ts count base on tx clk (clk_ref). 3043 * The lpi sleep cnt value = X us / (cycle_ns). 3044 */ 3045 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) 3046 { 3047 struct fec_enet_private *fep = netdev_priv(ndev); 3048 3049 return us * (fep->clk_ref_rate / 1000) / 1000; 3050 } 3051 3052 static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable) 3053 { 3054 struct fec_enet_private *fep = netdev_priv(ndev); 3055 struct ethtool_eee *p = &fep->eee; 3056 unsigned int sleep_cycle, wake_cycle; 3057 int ret = 0; 3058 3059 if (enable) { 3060 ret = phy_init_eee(ndev->phydev, false); 3061 if (ret) 3062 return ret; 3063 3064 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer); 3065 wake_cycle = sleep_cycle; 3066 } else { 3067 sleep_cycle = 0; 3068 wake_cycle = 0; 3069 } 3070 3071 p->tx_lpi_enabled = enable; 3072 p->eee_enabled = enable; 3073 p->eee_active = enable; 3074 3075 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); 3076 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); 3077 3078 return 0; 3079 } 3080 3081 static int 3082 fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *edata) 3083 { 3084 struct fec_enet_private *fep = netdev_priv(ndev); 3085 struct ethtool_eee *p = &fep->eee; 3086 3087 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3088 return -EOPNOTSUPP; 3089 3090 if (!netif_running(ndev)) 3091 return -ENETDOWN; 3092 3093 edata->eee_enabled = p->eee_enabled; 3094 edata->eee_active = p->eee_active; 3095 edata->tx_lpi_timer = p->tx_lpi_timer; 3096 edata->tx_lpi_enabled = p->tx_lpi_enabled; 3097 3098 return phy_ethtool_get_eee(ndev->phydev, edata); 3099 } 3100 3101 static int 3102 fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *edata) 3103 { 3104 struct fec_enet_private *fep = netdev_priv(ndev); 3105 struct ethtool_eee *p = &fep->eee; 3106 int ret = 0; 3107 3108 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3109 return -EOPNOTSUPP; 3110 3111 if (!netif_running(ndev)) 3112 return -ENETDOWN; 3113 3114 p->tx_lpi_timer = edata->tx_lpi_timer; 3115 3116 if (!edata->eee_enabled || !edata->tx_lpi_enabled || 3117 !edata->tx_lpi_timer) 3118 ret = fec_enet_eee_mode_set(ndev, false); 3119 else 3120 ret = fec_enet_eee_mode_set(ndev, true); 3121 3122 if (ret) 3123 return ret; 3124 3125 return phy_ethtool_set_eee(ndev->phydev, edata); 3126 } 3127 3128 static void 3129 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3130 { 3131 struct fec_enet_private *fep = netdev_priv(ndev); 3132 3133 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 3134 wol->supported = WAKE_MAGIC; 3135 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 3136 } else { 3137 wol->supported = wol->wolopts = 0; 3138 } 3139 } 3140 3141 static int 3142 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3143 { 3144 struct fec_enet_private *fep = netdev_priv(ndev); 3145 3146 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 3147 return -EINVAL; 3148 3149 if (wol->wolopts & ~WAKE_MAGIC) 3150 return -EINVAL; 3151 3152 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 3153 if (device_may_wakeup(&ndev->dev)) 3154 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 3155 else 3156 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 3157 3158 return 0; 3159 } 3160 3161 static const struct ethtool_ops fec_enet_ethtool_ops = { 3162 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3163 ETHTOOL_COALESCE_MAX_FRAMES, 3164 .get_drvinfo = fec_enet_get_drvinfo, 3165 .get_regs_len = fec_enet_get_regs_len, 3166 .get_regs = fec_enet_get_regs, 3167 .nway_reset = phy_ethtool_nway_reset, 3168 .get_link = ethtool_op_get_link, 3169 .get_coalesce = fec_enet_get_coalesce, 3170 .set_coalesce = fec_enet_set_coalesce, 3171 #ifndef CONFIG_M5272 3172 .get_pauseparam = fec_enet_get_pauseparam, 3173 .set_pauseparam = fec_enet_set_pauseparam, 3174 .get_strings = fec_enet_get_strings, 3175 .get_ethtool_stats = fec_enet_get_ethtool_stats, 3176 .get_sset_count = fec_enet_get_sset_count, 3177 #endif 3178 .get_ts_info = fec_enet_get_ts_info, 3179 .get_wol = fec_enet_get_wol, 3180 .set_wol = fec_enet_set_wol, 3181 .get_eee = fec_enet_get_eee, 3182 .set_eee = fec_enet_set_eee, 3183 .get_link_ksettings = phy_ethtool_get_link_ksettings, 3184 .set_link_ksettings = phy_ethtool_set_link_ksettings, 3185 .self_test = net_selftest, 3186 }; 3187 3188 static void fec_enet_free_buffers(struct net_device *ndev) 3189 { 3190 struct fec_enet_private *fep = netdev_priv(ndev); 3191 unsigned int i; 3192 struct fec_enet_priv_tx_q *txq; 3193 struct fec_enet_priv_rx_q *rxq; 3194 unsigned int q; 3195 3196 for (q = 0; q < fep->num_rx_queues; q++) { 3197 rxq = fep->rx_queue[q]; 3198 for (i = 0; i < rxq->bd.ring_size; i++) 3199 page_pool_put_full_page(rxq->page_pool, rxq->rx_skb_info[i].page, false); 3200 3201 for (i = 0; i < XDP_STATS_TOTAL; i++) 3202 rxq->stats[i] = 0; 3203 3204 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 3205 xdp_rxq_info_unreg(&rxq->xdp_rxq); 3206 page_pool_destroy(rxq->page_pool); 3207 rxq->page_pool = NULL; 3208 } 3209 3210 for (q = 0; q < fep->num_tx_queues; q++) { 3211 txq = fep->tx_queue[q]; 3212 for (i = 0; i < txq->bd.ring_size; i++) { 3213 kfree(txq->tx_bounce[i]); 3214 txq->tx_bounce[i] = NULL; 3215 3216 if (!txq->tx_buf[i].buf_p) { 3217 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3218 continue; 3219 } 3220 3221 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 3222 dev_kfree_skb(txq->tx_buf[i].buf_p); 3223 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 3224 xdp_return_frame(txq->tx_buf[i].buf_p); 3225 } else { 3226 struct page *page = txq->tx_buf[i].buf_p; 3227 3228 page_pool_put_page(page->pp, page, 0, false); 3229 } 3230 3231 txq->tx_buf[i].buf_p = NULL; 3232 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3233 } 3234 } 3235 } 3236 3237 static void fec_enet_free_queue(struct net_device *ndev) 3238 { 3239 struct fec_enet_private *fep = netdev_priv(ndev); 3240 int i; 3241 struct fec_enet_priv_tx_q *txq; 3242 3243 for (i = 0; i < fep->num_tx_queues; i++) 3244 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 3245 txq = fep->tx_queue[i]; 3246 dma_free_coherent(&fep->pdev->dev, 3247 txq->bd.ring_size * TSO_HEADER_SIZE, 3248 txq->tso_hdrs, 3249 txq->tso_hdrs_dma); 3250 } 3251 3252 for (i = 0; i < fep->num_rx_queues; i++) 3253 kfree(fep->rx_queue[i]); 3254 for (i = 0; i < fep->num_tx_queues; i++) 3255 kfree(fep->tx_queue[i]); 3256 } 3257 3258 static int fec_enet_alloc_queue(struct net_device *ndev) 3259 { 3260 struct fec_enet_private *fep = netdev_priv(ndev); 3261 int i; 3262 int ret = 0; 3263 struct fec_enet_priv_tx_q *txq; 3264 3265 for (i = 0; i < fep->num_tx_queues; i++) { 3266 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 3267 if (!txq) { 3268 ret = -ENOMEM; 3269 goto alloc_failed; 3270 } 3271 3272 fep->tx_queue[i] = txq; 3273 txq->bd.ring_size = TX_RING_SIZE; 3274 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 3275 3276 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 3277 txq->tx_wake_threshold = FEC_MAX_SKB_DESCS + 2 * MAX_SKB_FRAGS; 3278 3279 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 3280 txq->bd.ring_size * TSO_HEADER_SIZE, 3281 &txq->tso_hdrs_dma, 3282 GFP_KERNEL); 3283 if (!txq->tso_hdrs) { 3284 ret = -ENOMEM; 3285 goto alloc_failed; 3286 } 3287 } 3288 3289 for (i = 0; i < fep->num_rx_queues; i++) { 3290 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 3291 GFP_KERNEL); 3292 if (!fep->rx_queue[i]) { 3293 ret = -ENOMEM; 3294 goto alloc_failed; 3295 } 3296 3297 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 3298 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 3299 } 3300 return ret; 3301 3302 alloc_failed: 3303 fec_enet_free_queue(ndev); 3304 return ret; 3305 } 3306 3307 static int 3308 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 3309 { 3310 struct fec_enet_private *fep = netdev_priv(ndev); 3311 struct fec_enet_priv_rx_q *rxq; 3312 dma_addr_t phys_addr; 3313 struct bufdesc *bdp; 3314 struct page *page; 3315 int i, err; 3316 3317 rxq = fep->rx_queue[queue]; 3318 bdp = rxq->bd.base; 3319 3320 err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size); 3321 if (err < 0) { 3322 netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err); 3323 return err; 3324 } 3325 3326 for (i = 0; i < rxq->bd.ring_size; i++) { 3327 page = page_pool_dev_alloc_pages(rxq->page_pool); 3328 if (!page) 3329 goto err_alloc; 3330 3331 phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM; 3332 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 3333 3334 rxq->rx_skb_info[i].page = page; 3335 rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM; 3336 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3337 3338 if (fep->bufdesc_ex) { 3339 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3340 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 3341 } 3342 3343 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3344 } 3345 3346 /* Set the last buffer to wrap. */ 3347 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3348 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3349 return 0; 3350 3351 err_alloc: 3352 fec_enet_free_buffers(ndev); 3353 return -ENOMEM; 3354 } 3355 3356 static int 3357 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 3358 { 3359 struct fec_enet_private *fep = netdev_priv(ndev); 3360 unsigned int i; 3361 struct bufdesc *bdp; 3362 struct fec_enet_priv_tx_q *txq; 3363 3364 txq = fep->tx_queue[queue]; 3365 bdp = txq->bd.base; 3366 for (i = 0; i < txq->bd.ring_size; i++) { 3367 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 3368 if (!txq->tx_bounce[i]) 3369 goto err_alloc; 3370 3371 bdp->cbd_sc = cpu_to_fec16(0); 3372 bdp->cbd_bufaddr = cpu_to_fec32(0); 3373 3374 if (fep->bufdesc_ex) { 3375 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3376 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 3377 } 3378 3379 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3380 } 3381 3382 /* Set the last buffer to wrap. */ 3383 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3384 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3385 3386 return 0; 3387 3388 err_alloc: 3389 fec_enet_free_buffers(ndev); 3390 return -ENOMEM; 3391 } 3392 3393 static int fec_enet_alloc_buffers(struct net_device *ndev) 3394 { 3395 struct fec_enet_private *fep = netdev_priv(ndev); 3396 unsigned int i; 3397 3398 for (i = 0; i < fep->num_rx_queues; i++) 3399 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3400 return -ENOMEM; 3401 3402 for (i = 0; i < fep->num_tx_queues; i++) 3403 if (fec_enet_alloc_txq_buffers(ndev, i)) 3404 return -ENOMEM; 3405 return 0; 3406 } 3407 3408 static int 3409 fec_enet_open(struct net_device *ndev) 3410 { 3411 struct fec_enet_private *fep = netdev_priv(ndev); 3412 int ret; 3413 bool reset_again; 3414 3415 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3416 if (ret < 0) 3417 return ret; 3418 3419 pinctrl_pm_select_default_state(&fep->pdev->dev); 3420 ret = fec_enet_clk_enable(ndev, true); 3421 if (ret) 3422 goto clk_enable; 3423 3424 /* During the first fec_enet_open call the PHY isn't probed at this 3425 * point. Therefore the phy_reset_after_clk_enable() call within 3426 * fec_enet_clk_enable() fails. As we need this reset in order to be 3427 * sure the PHY is working correctly we check if we need to reset again 3428 * later when the PHY is probed 3429 */ 3430 if (ndev->phydev && ndev->phydev->drv) 3431 reset_again = false; 3432 else 3433 reset_again = true; 3434 3435 /* I should reset the ring buffers here, but I don't yet know 3436 * a simple way to do that. 3437 */ 3438 3439 ret = fec_enet_alloc_buffers(ndev); 3440 if (ret) 3441 goto err_enet_alloc; 3442 3443 /* Init MAC prior to mii bus probe */ 3444 fec_restart(ndev); 3445 3446 /* Call phy_reset_after_clk_enable() again if it failed during 3447 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3448 */ 3449 if (reset_again) 3450 fec_enet_phy_reset_after_clk_enable(ndev); 3451 3452 /* Probe and connect to PHY when open the interface */ 3453 ret = fec_enet_mii_probe(ndev); 3454 if (ret) 3455 goto err_enet_mii_probe; 3456 3457 if (fep->quirks & FEC_QUIRK_ERR006687) 3458 imx6q_cpuidle_fec_irqs_used(); 3459 3460 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3461 cpu_latency_qos_add_request(&fep->pm_qos_req, 0); 3462 3463 napi_enable(&fep->napi); 3464 phy_start(ndev->phydev); 3465 netif_tx_start_all_queues(ndev); 3466 3467 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3468 FEC_WOL_FLAG_ENABLE); 3469 3470 return 0; 3471 3472 err_enet_mii_probe: 3473 fec_enet_free_buffers(ndev); 3474 err_enet_alloc: 3475 fec_enet_clk_enable(ndev, false); 3476 clk_enable: 3477 pm_runtime_mark_last_busy(&fep->pdev->dev); 3478 pm_runtime_put_autosuspend(&fep->pdev->dev); 3479 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3480 return ret; 3481 } 3482 3483 static int 3484 fec_enet_close(struct net_device *ndev) 3485 { 3486 struct fec_enet_private *fep = netdev_priv(ndev); 3487 3488 phy_stop(ndev->phydev); 3489 3490 if (netif_device_present(ndev)) { 3491 napi_disable(&fep->napi); 3492 netif_tx_disable(ndev); 3493 fec_stop(ndev); 3494 } 3495 3496 phy_disconnect(ndev->phydev); 3497 3498 if (fep->quirks & FEC_QUIRK_ERR006687) 3499 imx6q_cpuidle_fec_irqs_unused(); 3500 3501 fec_enet_update_ethtool_stats(ndev); 3502 3503 fec_enet_clk_enable(ndev, false); 3504 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3505 cpu_latency_qos_remove_request(&fep->pm_qos_req); 3506 3507 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3508 pm_runtime_mark_last_busy(&fep->pdev->dev); 3509 pm_runtime_put_autosuspend(&fep->pdev->dev); 3510 3511 fec_enet_free_buffers(ndev); 3512 3513 return 0; 3514 } 3515 3516 /* Set or clear the multicast filter for this adaptor. 3517 * Skeleton taken from sunlance driver. 3518 * The CPM Ethernet implementation allows Multicast as well as individual 3519 * MAC address filtering. Some of the drivers check to make sure it is 3520 * a group multicast address, and discard those that are not. I guess I 3521 * will do the same for now, but just remove the test if you want 3522 * individual filtering as well (do the upper net layers want or support 3523 * this kind of feature?). 3524 */ 3525 3526 #define FEC_HASH_BITS 6 /* #bits in hash */ 3527 3528 static void set_multicast_list(struct net_device *ndev) 3529 { 3530 struct fec_enet_private *fep = netdev_priv(ndev); 3531 struct netdev_hw_addr *ha; 3532 unsigned int crc, tmp; 3533 unsigned char hash; 3534 unsigned int hash_high = 0, hash_low = 0; 3535 3536 if (ndev->flags & IFF_PROMISC) { 3537 tmp = readl(fep->hwp + FEC_R_CNTRL); 3538 tmp |= 0x8; 3539 writel(tmp, fep->hwp + FEC_R_CNTRL); 3540 return; 3541 } 3542 3543 tmp = readl(fep->hwp + FEC_R_CNTRL); 3544 tmp &= ~0x8; 3545 writel(tmp, fep->hwp + FEC_R_CNTRL); 3546 3547 if (ndev->flags & IFF_ALLMULTI) { 3548 /* Catch all multicast addresses, so set the 3549 * filter to all 1's 3550 */ 3551 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3552 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3553 3554 return; 3555 } 3556 3557 /* Add the addresses in hash register */ 3558 netdev_for_each_mc_addr(ha, ndev) { 3559 /* calculate crc32 value of mac address */ 3560 crc = ether_crc_le(ndev->addr_len, ha->addr); 3561 3562 /* only upper 6 bits (FEC_HASH_BITS) are used 3563 * which point to specific bit in the hash registers 3564 */ 3565 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3566 3567 if (hash > 31) 3568 hash_high |= 1 << (hash - 32); 3569 else 3570 hash_low |= 1 << hash; 3571 } 3572 3573 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3574 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3575 } 3576 3577 /* Set a MAC change in hardware. */ 3578 static int 3579 fec_set_mac_address(struct net_device *ndev, void *p) 3580 { 3581 struct fec_enet_private *fep = netdev_priv(ndev); 3582 struct sockaddr *addr = p; 3583 3584 if (addr) { 3585 if (!is_valid_ether_addr(addr->sa_data)) 3586 return -EADDRNOTAVAIL; 3587 eth_hw_addr_set(ndev, addr->sa_data); 3588 } 3589 3590 /* Add netif status check here to avoid system hang in below case: 3591 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3592 * After ethx down, fec all clocks are gated off and then register 3593 * access causes system hang. 3594 */ 3595 if (!netif_running(ndev)) 3596 return 0; 3597 3598 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3599 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3600 fep->hwp + FEC_ADDR_LOW); 3601 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3602 fep->hwp + FEC_ADDR_HIGH); 3603 return 0; 3604 } 3605 3606 #ifdef CONFIG_NET_POLL_CONTROLLER 3607 /** 3608 * fec_poll_controller - FEC Poll controller function 3609 * @dev: The FEC network adapter 3610 * 3611 * Polled functionality used by netconsole and others in non interrupt mode 3612 * 3613 */ 3614 static void fec_poll_controller(struct net_device *dev) 3615 { 3616 int i; 3617 struct fec_enet_private *fep = netdev_priv(dev); 3618 3619 for (i = 0; i < FEC_IRQ_NUM; i++) { 3620 if (fep->irq[i] > 0) { 3621 disable_irq(fep->irq[i]); 3622 fec_enet_interrupt(fep->irq[i], dev); 3623 enable_irq(fep->irq[i]); 3624 } 3625 } 3626 } 3627 #endif 3628 3629 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3630 netdev_features_t features) 3631 { 3632 struct fec_enet_private *fep = netdev_priv(netdev); 3633 netdev_features_t changed = features ^ netdev->features; 3634 3635 netdev->features = features; 3636 3637 /* Receive checksum has been changed */ 3638 if (changed & NETIF_F_RXCSUM) { 3639 if (features & NETIF_F_RXCSUM) 3640 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3641 else 3642 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3643 } 3644 } 3645 3646 static int fec_set_features(struct net_device *netdev, 3647 netdev_features_t features) 3648 { 3649 struct fec_enet_private *fep = netdev_priv(netdev); 3650 netdev_features_t changed = features ^ netdev->features; 3651 3652 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3653 napi_disable(&fep->napi); 3654 netif_tx_lock_bh(netdev); 3655 fec_stop(netdev); 3656 fec_enet_set_netdev_features(netdev, features); 3657 fec_restart(netdev); 3658 netif_tx_wake_all_queues(netdev); 3659 netif_tx_unlock_bh(netdev); 3660 napi_enable(&fep->napi); 3661 } else { 3662 fec_enet_set_netdev_features(netdev, features); 3663 } 3664 3665 return 0; 3666 } 3667 3668 static u16 fec_enet_get_raw_vlan_tci(struct sk_buff *skb) 3669 { 3670 struct vlan_ethhdr *vhdr; 3671 unsigned short vlan_TCI = 0; 3672 3673 if (skb->protocol == htons(ETH_P_ALL)) { 3674 vhdr = (struct vlan_ethhdr *)(skb->data); 3675 vlan_TCI = ntohs(vhdr->h_vlan_TCI); 3676 } 3677 3678 return vlan_TCI; 3679 } 3680 3681 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3682 struct net_device *sb_dev) 3683 { 3684 struct fec_enet_private *fep = netdev_priv(ndev); 3685 u16 vlan_tag; 3686 3687 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3688 return netdev_pick_tx(ndev, skb, NULL); 3689 3690 vlan_tag = fec_enet_get_raw_vlan_tci(skb); 3691 if (!vlan_tag) 3692 return vlan_tag; 3693 3694 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3695 } 3696 3697 static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf) 3698 { 3699 struct fec_enet_private *fep = netdev_priv(dev); 3700 bool is_run = netif_running(dev); 3701 struct bpf_prog *old_prog; 3702 3703 switch (bpf->command) { 3704 case XDP_SETUP_PROG: 3705 /* No need to support the SoCs that require to 3706 * do the frame swap because the performance wouldn't be 3707 * better than the skb mode. 3708 */ 3709 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 3710 return -EOPNOTSUPP; 3711 3712 if (!bpf->prog) 3713 xdp_features_clear_redirect_target(dev); 3714 3715 if (is_run) { 3716 napi_disable(&fep->napi); 3717 netif_tx_disable(dev); 3718 } 3719 3720 old_prog = xchg(&fep->xdp_prog, bpf->prog); 3721 if (old_prog) 3722 bpf_prog_put(old_prog); 3723 3724 fec_restart(dev); 3725 3726 if (is_run) { 3727 napi_enable(&fep->napi); 3728 netif_tx_start_all_queues(dev); 3729 } 3730 3731 if (bpf->prog) 3732 xdp_features_set_redirect_target(dev, false); 3733 3734 return 0; 3735 3736 case XDP_SETUP_XSK_POOL: 3737 return -EOPNOTSUPP; 3738 3739 default: 3740 return -EOPNOTSUPP; 3741 } 3742 } 3743 3744 static int 3745 fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index) 3746 { 3747 if (unlikely(index < 0)) 3748 return 0; 3749 3750 return (index % fep->num_tx_queues); 3751 } 3752 3753 static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep, 3754 struct fec_enet_priv_tx_q *txq, 3755 void *frame, u32 dma_sync_len, 3756 bool ndo_xmit) 3757 { 3758 unsigned int index, status, estatus; 3759 struct bufdesc *bdp; 3760 dma_addr_t dma_addr; 3761 int entries_free; 3762 u16 frame_len; 3763 3764 entries_free = fec_enet_get_free_txdesc_num(txq); 3765 if (entries_free < MAX_SKB_FRAGS + 1) { 3766 netdev_err_once(fep->netdev, "NOT enough BD for SG!\n"); 3767 return -EBUSY; 3768 } 3769 3770 /* Fill in a Tx ring entry */ 3771 bdp = txq->bd.cur; 3772 status = fec16_to_cpu(bdp->cbd_sc); 3773 status &= ~BD_ENET_TX_STATS; 3774 3775 index = fec_enet_get_bd_index(bdp, &txq->bd); 3776 3777 if (ndo_xmit) { 3778 struct xdp_frame *xdpf = frame; 3779 3780 dma_addr = dma_map_single(&fep->pdev->dev, xdpf->data, 3781 xdpf->len, DMA_TO_DEVICE); 3782 if (dma_mapping_error(&fep->pdev->dev, dma_addr)) 3783 return -ENOMEM; 3784 3785 frame_len = xdpf->len; 3786 txq->tx_buf[index].buf_p = xdpf; 3787 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_NDO; 3788 } else { 3789 struct xdp_buff *xdpb = frame; 3790 struct page *page; 3791 3792 page = virt_to_page(xdpb->data); 3793 dma_addr = page_pool_get_dma_addr(page) + 3794 (xdpb->data - xdpb->data_hard_start); 3795 dma_sync_single_for_device(&fep->pdev->dev, dma_addr, 3796 dma_sync_len, DMA_BIDIRECTIONAL); 3797 frame_len = xdpb->data_end - xdpb->data; 3798 txq->tx_buf[index].buf_p = page; 3799 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_TX; 3800 } 3801 3802 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 3803 if (fep->bufdesc_ex) 3804 estatus = BD_ENET_TX_INT; 3805 3806 bdp->cbd_bufaddr = cpu_to_fec32(dma_addr); 3807 bdp->cbd_datlen = cpu_to_fec16(frame_len); 3808 3809 if (fep->bufdesc_ex) { 3810 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3811 3812 if (fep->quirks & FEC_QUIRK_HAS_AVB) 3813 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 3814 3815 ebdp->cbd_bdu = 0; 3816 ebdp->cbd_esc = cpu_to_fec32(estatus); 3817 } 3818 3819 /* Make sure the updates to rest of the descriptor are performed before 3820 * transferring ownership. 3821 */ 3822 dma_wmb(); 3823 3824 /* Send it on its way. Tell FEC it's ready, interrupt when done, 3825 * it's the last BD of the frame, and to put the CRC on the end. 3826 */ 3827 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 3828 bdp->cbd_sc = cpu_to_fec16(status); 3829 3830 /* If this was the last BD in the ring, start at the beginning again. */ 3831 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3832 3833 /* Make sure the update to bdp are performed before txq->bd.cur. */ 3834 dma_wmb(); 3835 3836 txq->bd.cur = bdp; 3837 3838 /* Trigger transmission start */ 3839 writel(0, txq->bd.reg_desc_active); 3840 3841 return 0; 3842 } 3843 3844 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 3845 int cpu, struct xdp_buff *xdp, 3846 u32 dma_sync_len) 3847 { 3848 struct fec_enet_priv_tx_q *txq; 3849 struct netdev_queue *nq; 3850 int queue, ret; 3851 3852 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3853 txq = fep->tx_queue[queue]; 3854 nq = netdev_get_tx_queue(fep->netdev, queue); 3855 3856 __netif_tx_lock(nq, cpu); 3857 3858 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3859 txq_trans_cond_update(nq); 3860 ret = fec_enet_txq_xmit_frame(fep, txq, xdp, dma_sync_len, false); 3861 3862 __netif_tx_unlock(nq); 3863 3864 return ret; 3865 } 3866 3867 static int fec_enet_xdp_xmit(struct net_device *dev, 3868 int num_frames, 3869 struct xdp_frame **frames, 3870 u32 flags) 3871 { 3872 struct fec_enet_private *fep = netdev_priv(dev); 3873 struct fec_enet_priv_tx_q *txq; 3874 int cpu = smp_processor_id(); 3875 unsigned int sent_frames = 0; 3876 struct netdev_queue *nq; 3877 unsigned int queue; 3878 int i; 3879 3880 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3881 txq = fep->tx_queue[queue]; 3882 nq = netdev_get_tx_queue(fep->netdev, queue); 3883 3884 __netif_tx_lock(nq, cpu); 3885 3886 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3887 txq_trans_cond_update(nq); 3888 for (i = 0; i < num_frames; i++) { 3889 if (fec_enet_txq_xmit_frame(fep, txq, frames[i], 0, true) < 0) 3890 break; 3891 sent_frames++; 3892 } 3893 3894 __netif_tx_unlock(nq); 3895 3896 return sent_frames; 3897 } 3898 3899 static int fec_hwtstamp_get(struct net_device *ndev, 3900 struct kernel_hwtstamp_config *config) 3901 { 3902 struct fec_enet_private *fep = netdev_priv(ndev); 3903 3904 if (!netif_running(ndev)) 3905 return -EINVAL; 3906 3907 if (!fep->bufdesc_ex) 3908 return -EOPNOTSUPP; 3909 3910 fec_ptp_get(ndev, config); 3911 3912 return 0; 3913 } 3914 3915 static int fec_hwtstamp_set(struct net_device *ndev, 3916 struct kernel_hwtstamp_config *config, 3917 struct netlink_ext_ack *extack) 3918 { 3919 struct fec_enet_private *fep = netdev_priv(ndev); 3920 3921 if (!netif_running(ndev)) 3922 return -EINVAL; 3923 3924 if (!fep->bufdesc_ex) 3925 return -EOPNOTSUPP; 3926 3927 return fec_ptp_set(ndev, config, extack); 3928 } 3929 3930 static const struct net_device_ops fec_netdev_ops = { 3931 .ndo_open = fec_enet_open, 3932 .ndo_stop = fec_enet_close, 3933 .ndo_start_xmit = fec_enet_start_xmit, 3934 .ndo_select_queue = fec_enet_select_queue, 3935 .ndo_set_rx_mode = set_multicast_list, 3936 .ndo_validate_addr = eth_validate_addr, 3937 .ndo_tx_timeout = fec_timeout, 3938 .ndo_set_mac_address = fec_set_mac_address, 3939 .ndo_eth_ioctl = phy_do_ioctl_running, 3940 #ifdef CONFIG_NET_POLL_CONTROLLER 3941 .ndo_poll_controller = fec_poll_controller, 3942 #endif 3943 .ndo_set_features = fec_set_features, 3944 .ndo_bpf = fec_enet_bpf, 3945 .ndo_xdp_xmit = fec_enet_xdp_xmit, 3946 .ndo_hwtstamp_get = fec_hwtstamp_get, 3947 .ndo_hwtstamp_set = fec_hwtstamp_set, 3948 }; 3949 3950 static const unsigned short offset_des_active_rxq[] = { 3951 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3952 }; 3953 3954 static const unsigned short offset_des_active_txq[] = { 3955 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3956 }; 3957 3958 /* 3959 * XXX: We need to clean up on failure exits here. 3960 * 3961 */ 3962 static int fec_enet_init(struct net_device *ndev) 3963 { 3964 struct fec_enet_private *fep = netdev_priv(ndev); 3965 struct bufdesc *cbd_base; 3966 dma_addr_t bd_dma; 3967 int bd_size; 3968 unsigned int i; 3969 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3970 sizeof(struct bufdesc); 3971 unsigned dsize_log2 = __fls(dsize); 3972 int ret; 3973 3974 WARN_ON(dsize != (1 << dsize_log2)); 3975 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 3976 fep->rx_align = 0xf; 3977 fep->tx_align = 0xf; 3978 #else 3979 fep->rx_align = 0x3; 3980 fep->tx_align = 0x3; 3981 #endif 3982 fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 3983 fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 3984 fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT; 3985 fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT; 3986 3987 /* Check mask of the streaming and coherent API */ 3988 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 3989 if (ret < 0) { 3990 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 3991 return ret; 3992 } 3993 3994 ret = fec_enet_alloc_queue(ndev); 3995 if (ret) 3996 return ret; 3997 3998 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3999 4000 /* Allocate memory for buffer descriptors. */ 4001 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 4002 GFP_KERNEL); 4003 if (!cbd_base) { 4004 ret = -ENOMEM; 4005 goto free_queue_mem; 4006 } 4007 4008 /* Get the Ethernet address */ 4009 ret = fec_get_mac(ndev); 4010 if (ret) 4011 goto free_queue_mem; 4012 4013 /* Set receive and transmit descriptor base. */ 4014 for (i = 0; i < fep->num_rx_queues; i++) { 4015 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 4016 unsigned size = dsize * rxq->bd.ring_size; 4017 4018 rxq->bd.qid = i; 4019 rxq->bd.base = cbd_base; 4020 rxq->bd.cur = cbd_base; 4021 rxq->bd.dma = bd_dma; 4022 rxq->bd.dsize = dsize; 4023 rxq->bd.dsize_log2 = dsize_log2; 4024 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 4025 bd_dma += size; 4026 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4027 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4028 } 4029 4030 for (i = 0; i < fep->num_tx_queues; i++) { 4031 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 4032 unsigned size = dsize * txq->bd.ring_size; 4033 4034 txq->bd.qid = i; 4035 txq->bd.base = cbd_base; 4036 txq->bd.cur = cbd_base; 4037 txq->bd.dma = bd_dma; 4038 txq->bd.dsize = dsize; 4039 txq->bd.dsize_log2 = dsize_log2; 4040 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 4041 bd_dma += size; 4042 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4043 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4044 } 4045 4046 4047 /* The FEC Ethernet specific entries in the device structure */ 4048 ndev->watchdog_timeo = TX_TIMEOUT; 4049 ndev->netdev_ops = &fec_netdev_ops; 4050 ndev->ethtool_ops = &fec_enet_ethtool_ops; 4051 4052 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 4053 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi); 4054 4055 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 4056 /* enable hw VLAN support */ 4057 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 4058 4059 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 4060 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS); 4061 4062 /* enable hw accelerator */ 4063 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 4064 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 4065 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 4066 } 4067 4068 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 4069 fep->tx_align = 0; 4070 fep->rx_align = 0x3f; 4071 } 4072 4073 ndev->hw_features = ndev->features; 4074 4075 if (!(fep->quirks & FEC_QUIRK_SWAP_FRAME)) 4076 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 4077 NETDEV_XDP_ACT_REDIRECT; 4078 4079 fec_restart(ndev); 4080 4081 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 4082 fec_enet_clear_ethtool_stats(ndev); 4083 else 4084 fec_enet_update_ethtool_stats(ndev); 4085 4086 return 0; 4087 4088 free_queue_mem: 4089 fec_enet_free_queue(ndev); 4090 return ret; 4091 } 4092 4093 #ifdef CONFIG_OF 4094 static int fec_reset_phy(struct platform_device *pdev) 4095 { 4096 struct gpio_desc *phy_reset; 4097 int msec = 1, phy_post_delay = 0; 4098 struct device_node *np = pdev->dev.of_node; 4099 int err; 4100 4101 if (!np) 4102 return 0; 4103 4104 err = of_property_read_u32(np, "phy-reset-duration", &msec); 4105 /* A sane reset duration should not be longer than 1s */ 4106 if (!err && msec > 1000) 4107 msec = 1; 4108 4109 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 4110 /* valid reset duration should be less than 1s */ 4111 if (!err && phy_post_delay > 1000) 4112 return -EINVAL; 4113 4114 phy_reset = devm_gpiod_get_optional(&pdev->dev, "phy-reset", 4115 GPIOD_OUT_HIGH); 4116 if (IS_ERR(phy_reset)) 4117 return dev_err_probe(&pdev->dev, PTR_ERR(phy_reset), 4118 "failed to get phy-reset-gpios\n"); 4119 4120 if (!phy_reset) 4121 return 0; 4122 4123 if (msec > 20) 4124 msleep(msec); 4125 else 4126 usleep_range(msec * 1000, msec * 1000 + 1000); 4127 4128 gpiod_set_value_cansleep(phy_reset, 0); 4129 4130 if (!phy_post_delay) 4131 return 0; 4132 4133 if (phy_post_delay > 20) 4134 msleep(phy_post_delay); 4135 else 4136 usleep_range(phy_post_delay * 1000, 4137 phy_post_delay * 1000 + 1000); 4138 4139 return 0; 4140 } 4141 #else /* CONFIG_OF */ 4142 static int fec_reset_phy(struct platform_device *pdev) 4143 { 4144 /* 4145 * In case of platform probe, the reset has been done 4146 * by machine code. 4147 */ 4148 return 0; 4149 } 4150 #endif /* CONFIG_OF */ 4151 4152 static void 4153 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 4154 { 4155 struct device_node *np = pdev->dev.of_node; 4156 4157 *num_tx = *num_rx = 1; 4158 4159 if (!np || !of_device_is_available(np)) 4160 return; 4161 4162 /* parse the num of tx and rx queues */ 4163 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 4164 4165 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 4166 4167 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 4168 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 4169 *num_tx); 4170 *num_tx = 1; 4171 return; 4172 } 4173 4174 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 4175 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 4176 *num_rx); 4177 *num_rx = 1; 4178 return; 4179 } 4180 4181 } 4182 4183 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 4184 { 4185 int irq_cnt = platform_irq_count(pdev); 4186 4187 if (irq_cnt > FEC_IRQ_NUM) 4188 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 4189 else if (irq_cnt == 2) 4190 irq_cnt = 1; /* last for pps */ 4191 else if (irq_cnt <= 0) 4192 irq_cnt = 1; /* At least 1 irq is needed */ 4193 return irq_cnt; 4194 } 4195 4196 static void fec_enet_get_wakeup_irq(struct platform_device *pdev) 4197 { 4198 struct net_device *ndev = platform_get_drvdata(pdev); 4199 struct fec_enet_private *fep = netdev_priv(ndev); 4200 4201 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) 4202 fep->wake_irq = fep->irq[2]; 4203 else 4204 fep->wake_irq = fep->irq[0]; 4205 } 4206 4207 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 4208 struct device_node *np) 4209 { 4210 struct device_node *gpr_np; 4211 u32 out_val[3]; 4212 int ret = 0; 4213 4214 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 4215 if (!gpr_np) 4216 return 0; 4217 4218 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 4219 ARRAY_SIZE(out_val)); 4220 if (ret) { 4221 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 4222 goto out; 4223 } 4224 4225 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 4226 if (IS_ERR(fep->stop_gpr.gpr)) { 4227 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 4228 ret = PTR_ERR(fep->stop_gpr.gpr); 4229 fep->stop_gpr.gpr = NULL; 4230 goto out; 4231 } 4232 4233 fep->stop_gpr.reg = out_val[1]; 4234 fep->stop_gpr.bit = out_val[2]; 4235 4236 out: 4237 of_node_put(gpr_np); 4238 4239 return ret; 4240 } 4241 4242 static int 4243 fec_probe(struct platform_device *pdev) 4244 { 4245 struct fec_enet_private *fep; 4246 struct fec_platform_data *pdata; 4247 phy_interface_t interface; 4248 struct net_device *ndev; 4249 int i, irq, ret = 0; 4250 static int dev_id; 4251 struct device_node *np = pdev->dev.of_node, *phy_node; 4252 int num_tx_qs; 4253 int num_rx_qs; 4254 char irq_name[8]; 4255 int irq_cnt; 4256 const struct fec_devinfo *dev_info; 4257 4258 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 4259 4260 /* Init network device */ 4261 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 4262 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 4263 if (!ndev) 4264 return -ENOMEM; 4265 4266 SET_NETDEV_DEV(ndev, &pdev->dev); 4267 4268 /* setup board info structure */ 4269 fep = netdev_priv(ndev); 4270 4271 dev_info = device_get_match_data(&pdev->dev); 4272 if (!dev_info) 4273 dev_info = (const struct fec_devinfo *)pdev->id_entry->driver_data; 4274 if (dev_info) 4275 fep->quirks = dev_info->quirks; 4276 4277 fep->netdev = ndev; 4278 fep->num_rx_queues = num_rx_qs; 4279 fep->num_tx_queues = num_tx_qs; 4280 4281 #if !defined(CONFIG_M5272) 4282 /* default enable pause frame auto negotiation */ 4283 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 4284 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 4285 #endif 4286 4287 /* Select default pin state */ 4288 pinctrl_pm_select_default_state(&pdev->dev); 4289 4290 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 4291 if (IS_ERR(fep->hwp)) { 4292 ret = PTR_ERR(fep->hwp); 4293 goto failed_ioremap; 4294 } 4295 4296 fep->pdev = pdev; 4297 fep->dev_id = dev_id++; 4298 4299 platform_set_drvdata(pdev, ndev); 4300 4301 if ((of_machine_is_compatible("fsl,imx6q") || 4302 of_machine_is_compatible("fsl,imx6dl")) && 4303 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 4304 fep->quirks |= FEC_QUIRK_ERR006687; 4305 4306 ret = fec_enet_ipc_handle_init(fep); 4307 if (ret) 4308 goto failed_ipc_init; 4309 4310 if (of_property_read_bool(np, "fsl,magic-packet")) 4311 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 4312 4313 ret = fec_enet_init_stop_mode(fep, np); 4314 if (ret) 4315 goto failed_stop_mode; 4316 4317 phy_node = of_parse_phandle(np, "phy-handle", 0); 4318 if (!phy_node && of_phy_is_fixed_link(np)) { 4319 ret = of_phy_register_fixed_link(np); 4320 if (ret < 0) { 4321 dev_err(&pdev->dev, 4322 "broken fixed-link specification\n"); 4323 goto failed_phy; 4324 } 4325 phy_node = of_node_get(np); 4326 } 4327 fep->phy_node = phy_node; 4328 4329 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 4330 if (ret) { 4331 pdata = dev_get_platdata(&pdev->dev); 4332 if (pdata) 4333 fep->phy_interface = pdata->phy; 4334 else 4335 fep->phy_interface = PHY_INTERFACE_MODE_MII; 4336 } else { 4337 fep->phy_interface = interface; 4338 } 4339 4340 ret = fec_enet_parse_rgmii_delay(fep, np); 4341 if (ret) 4342 goto failed_rgmii_delay; 4343 4344 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 4345 if (IS_ERR(fep->clk_ipg)) { 4346 ret = PTR_ERR(fep->clk_ipg); 4347 goto failed_clk; 4348 } 4349 4350 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 4351 if (IS_ERR(fep->clk_ahb)) { 4352 ret = PTR_ERR(fep->clk_ahb); 4353 goto failed_clk; 4354 } 4355 4356 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 4357 4358 /* enet_out is optional, depends on board */ 4359 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out"); 4360 if (IS_ERR(fep->clk_enet_out)) { 4361 ret = PTR_ERR(fep->clk_enet_out); 4362 goto failed_clk; 4363 } 4364 4365 fep->ptp_clk_on = false; 4366 mutex_init(&fep->ptp_clk_mutex); 4367 4368 /* clk_ref is optional, depends on board */ 4369 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref"); 4370 if (IS_ERR(fep->clk_ref)) { 4371 ret = PTR_ERR(fep->clk_ref); 4372 goto failed_clk; 4373 } 4374 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); 4375 4376 /* clk_2x_txclk is optional, depends on board */ 4377 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { 4378 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); 4379 if (IS_ERR(fep->clk_2x_txclk)) 4380 fep->clk_2x_txclk = NULL; 4381 } 4382 4383 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 4384 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 4385 if (IS_ERR(fep->clk_ptp)) { 4386 fep->clk_ptp = NULL; 4387 fep->bufdesc_ex = false; 4388 } 4389 4390 ret = fec_enet_clk_enable(ndev, true); 4391 if (ret) 4392 goto failed_clk; 4393 4394 ret = clk_prepare_enable(fep->clk_ipg); 4395 if (ret) 4396 goto failed_clk_ipg; 4397 ret = clk_prepare_enable(fep->clk_ahb); 4398 if (ret) 4399 goto failed_clk_ahb; 4400 4401 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 4402 if (!IS_ERR(fep->reg_phy)) { 4403 ret = regulator_enable(fep->reg_phy); 4404 if (ret) { 4405 dev_err(&pdev->dev, 4406 "Failed to enable phy regulator: %d\n", ret); 4407 goto failed_regulator; 4408 } 4409 } else { 4410 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 4411 ret = -EPROBE_DEFER; 4412 goto failed_regulator; 4413 } 4414 fep->reg_phy = NULL; 4415 } 4416 4417 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 4418 pm_runtime_use_autosuspend(&pdev->dev); 4419 pm_runtime_get_noresume(&pdev->dev); 4420 pm_runtime_set_active(&pdev->dev); 4421 pm_runtime_enable(&pdev->dev); 4422 4423 ret = fec_reset_phy(pdev); 4424 if (ret) 4425 goto failed_reset; 4426 4427 irq_cnt = fec_enet_get_irq_cnt(pdev); 4428 if (fep->bufdesc_ex) 4429 fec_ptp_init(pdev, irq_cnt); 4430 4431 ret = fec_enet_init(ndev); 4432 if (ret) 4433 goto failed_init; 4434 4435 for (i = 0; i < irq_cnt; i++) { 4436 snprintf(irq_name, sizeof(irq_name), "int%d", i); 4437 irq = platform_get_irq_byname_optional(pdev, irq_name); 4438 if (irq < 0) 4439 irq = platform_get_irq(pdev, i); 4440 if (irq < 0) { 4441 ret = irq; 4442 goto failed_irq; 4443 } 4444 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 4445 0, pdev->name, ndev); 4446 if (ret) 4447 goto failed_irq; 4448 4449 fep->irq[i] = irq; 4450 } 4451 4452 /* Decide which interrupt line is wakeup capable */ 4453 fec_enet_get_wakeup_irq(pdev); 4454 4455 ret = fec_enet_mii_init(pdev); 4456 if (ret) 4457 goto failed_mii_init; 4458 4459 /* Carrier starts down, phylib will bring it up */ 4460 netif_carrier_off(ndev); 4461 fec_enet_clk_enable(ndev, false); 4462 pinctrl_pm_select_sleep_state(&pdev->dev); 4463 4464 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN; 4465 4466 ret = register_netdev(ndev); 4467 if (ret) 4468 goto failed_register; 4469 4470 device_init_wakeup(&ndev->dev, fep->wol_flag & 4471 FEC_WOL_HAS_MAGIC_PACKET); 4472 4473 if (fep->bufdesc_ex && fep->ptp_clock) 4474 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 4475 4476 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 4477 4478 pm_runtime_mark_last_busy(&pdev->dev); 4479 pm_runtime_put_autosuspend(&pdev->dev); 4480 4481 return 0; 4482 4483 failed_register: 4484 fec_enet_mii_remove(fep); 4485 failed_mii_init: 4486 failed_irq: 4487 failed_init: 4488 fec_ptp_stop(pdev); 4489 failed_reset: 4490 pm_runtime_put_noidle(&pdev->dev); 4491 pm_runtime_disable(&pdev->dev); 4492 if (fep->reg_phy) 4493 regulator_disable(fep->reg_phy); 4494 failed_regulator: 4495 clk_disable_unprepare(fep->clk_ahb); 4496 failed_clk_ahb: 4497 clk_disable_unprepare(fep->clk_ipg); 4498 failed_clk_ipg: 4499 fec_enet_clk_enable(ndev, false); 4500 failed_clk: 4501 failed_rgmii_delay: 4502 if (of_phy_is_fixed_link(np)) 4503 of_phy_deregister_fixed_link(np); 4504 of_node_put(phy_node); 4505 failed_stop_mode: 4506 failed_ipc_init: 4507 failed_phy: 4508 dev_id--; 4509 failed_ioremap: 4510 free_netdev(ndev); 4511 4512 return ret; 4513 } 4514 4515 static void 4516 fec_drv_remove(struct platform_device *pdev) 4517 { 4518 struct net_device *ndev = platform_get_drvdata(pdev); 4519 struct fec_enet_private *fep = netdev_priv(ndev); 4520 struct device_node *np = pdev->dev.of_node; 4521 int ret; 4522 4523 ret = pm_runtime_get_sync(&pdev->dev); 4524 if (ret < 0) 4525 dev_err(&pdev->dev, 4526 "Failed to resume device in remove callback (%pe)\n", 4527 ERR_PTR(ret)); 4528 4529 cancel_work_sync(&fep->tx_timeout_work); 4530 fec_ptp_stop(pdev); 4531 unregister_netdev(ndev); 4532 fec_enet_mii_remove(fep); 4533 if (fep->reg_phy) 4534 regulator_disable(fep->reg_phy); 4535 4536 if (of_phy_is_fixed_link(np)) 4537 of_phy_deregister_fixed_link(np); 4538 of_node_put(fep->phy_node); 4539 4540 /* After pm_runtime_get_sync() failed, the clks are still off, so skip 4541 * disabling them again. 4542 */ 4543 if (ret >= 0) { 4544 clk_disable_unprepare(fep->clk_ahb); 4545 clk_disable_unprepare(fep->clk_ipg); 4546 } 4547 pm_runtime_put_noidle(&pdev->dev); 4548 pm_runtime_disable(&pdev->dev); 4549 4550 free_netdev(ndev); 4551 } 4552 4553 static int __maybe_unused fec_suspend(struct device *dev) 4554 { 4555 struct net_device *ndev = dev_get_drvdata(dev); 4556 struct fec_enet_private *fep = netdev_priv(ndev); 4557 int ret; 4558 4559 rtnl_lock(); 4560 if (netif_running(ndev)) { 4561 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 4562 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 4563 phy_stop(ndev->phydev); 4564 napi_disable(&fep->napi); 4565 netif_tx_lock_bh(ndev); 4566 netif_device_detach(ndev); 4567 netif_tx_unlock_bh(ndev); 4568 fec_stop(ndev); 4569 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4570 fec_irqs_disable(ndev); 4571 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 4572 } else { 4573 fec_irqs_disable_except_wakeup(ndev); 4574 if (fep->wake_irq > 0) { 4575 disable_irq(fep->wake_irq); 4576 enable_irq_wake(fep->wake_irq); 4577 } 4578 fec_enet_stop_mode(fep, true); 4579 } 4580 /* It's safe to disable clocks since interrupts are masked */ 4581 fec_enet_clk_enable(ndev, false); 4582 4583 fep->rpm_active = !pm_runtime_status_suspended(dev); 4584 if (fep->rpm_active) { 4585 ret = pm_runtime_force_suspend(dev); 4586 if (ret < 0) { 4587 rtnl_unlock(); 4588 return ret; 4589 } 4590 } 4591 } 4592 rtnl_unlock(); 4593 4594 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4595 regulator_disable(fep->reg_phy); 4596 4597 /* SOC supply clock to phy, when clock is disabled, phy link down 4598 * SOC control phy regulator, when regulator is disabled, phy link down 4599 */ 4600 if (fep->clk_enet_out || fep->reg_phy) 4601 fep->link = 0; 4602 4603 return 0; 4604 } 4605 4606 static int __maybe_unused fec_resume(struct device *dev) 4607 { 4608 struct net_device *ndev = dev_get_drvdata(dev); 4609 struct fec_enet_private *fep = netdev_priv(ndev); 4610 int ret; 4611 int val; 4612 4613 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4614 ret = regulator_enable(fep->reg_phy); 4615 if (ret) 4616 return ret; 4617 } 4618 4619 rtnl_lock(); 4620 if (netif_running(ndev)) { 4621 if (fep->rpm_active) 4622 pm_runtime_force_resume(dev); 4623 4624 ret = fec_enet_clk_enable(ndev, true); 4625 if (ret) { 4626 rtnl_unlock(); 4627 goto failed_clk; 4628 } 4629 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 4630 fec_enet_stop_mode(fep, false); 4631 if (fep->wake_irq) { 4632 disable_irq_wake(fep->wake_irq); 4633 enable_irq(fep->wake_irq); 4634 } 4635 4636 val = readl(fep->hwp + FEC_ECNTRL); 4637 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 4638 writel(val, fep->hwp + FEC_ECNTRL); 4639 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 4640 } else { 4641 pinctrl_pm_select_default_state(&fep->pdev->dev); 4642 } 4643 fec_restart(ndev); 4644 netif_tx_lock_bh(ndev); 4645 netif_device_attach(ndev); 4646 netif_tx_unlock_bh(ndev); 4647 napi_enable(&fep->napi); 4648 phy_init_hw(ndev->phydev); 4649 phy_start(ndev->phydev); 4650 } 4651 rtnl_unlock(); 4652 4653 return 0; 4654 4655 failed_clk: 4656 if (fep->reg_phy) 4657 regulator_disable(fep->reg_phy); 4658 return ret; 4659 } 4660 4661 static int __maybe_unused fec_runtime_suspend(struct device *dev) 4662 { 4663 struct net_device *ndev = dev_get_drvdata(dev); 4664 struct fec_enet_private *fep = netdev_priv(ndev); 4665 4666 clk_disable_unprepare(fep->clk_ahb); 4667 clk_disable_unprepare(fep->clk_ipg); 4668 4669 return 0; 4670 } 4671 4672 static int __maybe_unused fec_runtime_resume(struct device *dev) 4673 { 4674 struct net_device *ndev = dev_get_drvdata(dev); 4675 struct fec_enet_private *fep = netdev_priv(ndev); 4676 int ret; 4677 4678 ret = clk_prepare_enable(fep->clk_ahb); 4679 if (ret) 4680 return ret; 4681 ret = clk_prepare_enable(fep->clk_ipg); 4682 if (ret) 4683 goto failed_clk_ipg; 4684 4685 return 0; 4686 4687 failed_clk_ipg: 4688 clk_disable_unprepare(fep->clk_ahb); 4689 return ret; 4690 } 4691 4692 static const struct dev_pm_ops fec_pm_ops = { 4693 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 4694 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 4695 }; 4696 4697 static struct platform_driver fec_driver = { 4698 .driver = { 4699 .name = DRIVER_NAME, 4700 .pm = &fec_pm_ops, 4701 .of_match_table = fec_dt_ids, 4702 .suppress_bind_attrs = true, 4703 }, 4704 .id_table = fec_devtype, 4705 .probe = fec_probe, 4706 .remove_new = fec_drv_remove, 4707 }; 4708 4709 module_platform_driver(fec_driver); 4710 4711 MODULE_LICENSE("GPL"); 4712