1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/bitops.h> 26 #include <linux/bpf.h> 27 #include <linux/bpf_trace.h> 28 #include <linux/cacheflush.h> 29 #include <linux/clk.h> 30 #include <linux/crc32.h> 31 #include <linux/delay.h> 32 #include <linux/errno.h> 33 #include <linux/etherdevice.h> 34 #include <linux/fec.h> 35 #include <linux/filter.h> 36 #include <linux/gpio/consumer.h> 37 #include <linux/icmp.h> 38 #include <linux/if_vlan.h> 39 #include <linux/in.h> 40 #include <linux/interrupt.h> 41 #include <linux/io.h> 42 #include <linux/ioport.h> 43 #include <linux/ip.h> 44 #include <linux/irq.h> 45 #include <linux/kernel.h> 46 #include <linux/mdio.h> 47 #include <linux/mfd/syscon.h> 48 #include <linux/module.h> 49 #include <linux/netdevice.h> 50 #include <linux/of.h> 51 #include <linux/of_mdio.h> 52 #include <linux/of_net.h> 53 #include <linux/phy.h> 54 #include <linux/pinctrl/consumer.h> 55 #include <linux/phy_fixed.h> 56 #include <linux/platform_device.h> 57 #include <linux/pm_runtime.h> 58 #include <linux/prefetch.h> 59 #include <linux/property.h> 60 #include <linux/ptrace.h> 61 #include <linux/regmap.h> 62 #include <linux/regulator/consumer.h> 63 #include <linux/skbuff.h> 64 #include <linux/slab.h> 65 #include <linux/spinlock.h> 66 #include <linux/string.h> 67 #include <linux/tcp.h> 68 #include <linux/udp.h> 69 #include <linux/workqueue.h> 70 #include <net/ip.h> 71 #include <net/page_pool/helpers.h> 72 #include <net/selftests.h> 73 #include <net/tso.h> 74 #include <soc/imx/cpuidle.h> 75 76 #include "fec.h" 77 78 static void set_multicast_list(struct net_device *ndev); 79 static void fec_enet_itr_coal_set(struct net_device *ndev); 80 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 81 int cpu, struct xdp_buff *xdp, 82 u32 dma_sync_len); 83 84 #define DRIVER_NAME "fec" 85 86 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 87 88 #define FEC_ENET_RSEM_V 0x84 89 #define FEC_ENET_RSFL_V 16 90 #define FEC_ENET_RAEM_V 0x8 91 #define FEC_ENET_RAFL_V 0x8 92 #define FEC_ENET_OPD_V 0xFFF0 93 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 94 95 #define FEC_ENET_XDP_PASS 0 96 #define FEC_ENET_XDP_CONSUMED BIT(0) 97 #define FEC_ENET_XDP_TX BIT(1) 98 #define FEC_ENET_XDP_REDIR BIT(2) 99 100 struct fec_devinfo { 101 u32 quirks; 102 }; 103 104 static const struct fec_devinfo fec_imx25_info = { 105 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 106 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_HAS_MDIO_C45, 107 }; 108 109 static const struct fec_devinfo fec_imx27_info = { 110 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG | 111 FEC_QUIRK_HAS_MDIO_C45, 112 }; 113 114 static const struct fec_devinfo fec_imx28_info = { 115 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 116 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 117 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 118 FEC_QUIRK_NO_HARD_RESET | FEC_QUIRK_HAS_MDIO_C45, 119 }; 120 121 static const struct fec_devinfo fec_imx6q_info = { 122 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 125 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII | 126 FEC_QUIRK_HAS_PMQOS | FEC_QUIRK_HAS_MDIO_C45, 127 }; 128 129 static const struct fec_devinfo fec_mvf600_info = { 130 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC | 131 FEC_QUIRK_HAS_MDIO_C45, 132 }; 133 134 static const struct fec_devinfo fec_imx6sx_info = { 135 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 136 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 137 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 138 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 139 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 140 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 141 FEC_QUIRK_HAS_MDIO_C45, 142 }; 143 144 static const struct fec_devinfo fec_imx6ul_info = { 145 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 146 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 147 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 148 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 149 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII | 150 FEC_QUIRK_HAS_MDIO_C45, 151 }; 152 153 static const struct fec_devinfo fec_imx8mq_info = { 154 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 155 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 156 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 157 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 158 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 159 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 160 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2 | 161 FEC_QUIRK_HAS_MDIO_C45, 162 }; 163 164 static const struct fec_devinfo fec_imx8qm_info = { 165 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 166 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 167 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 168 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 169 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 170 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 171 FEC_QUIRK_DELAYED_CLKS_SUPPORT | FEC_QUIRK_HAS_MDIO_C45 | 172 FEC_QUIRK_JUMBO_FRAME, 173 }; 174 175 static const struct fec_devinfo fec_s32v234_info = { 176 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 177 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 178 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 179 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 180 FEC_QUIRK_HAS_MDIO_C45, 181 }; 182 183 static struct platform_device_id fec_devtype[] = { 184 { 185 /* keep it for coldfire */ 186 .name = DRIVER_NAME, 187 .driver_data = 0, 188 }, { 189 /* sentinel */ 190 } 191 }; 192 MODULE_DEVICE_TABLE(platform, fec_devtype); 193 194 static const struct of_device_id fec_dt_ids[] = { 195 { .compatible = "fsl,imx25-fec", .data = &fec_imx25_info, }, 196 { .compatible = "fsl,imx27-fec", .data = &fec_imx27_info, }, 197 { .compatible = "fsl,imx28-fec", .data = &fec_imx28_info, }, 198 { .compatible = "fsl,imx6q-fec", .data = &fec_imx6q_info, }, 199 { .compatible = "fsl,mvf600-fec", .data = &fec_mvf600_info, }, 200 { .compatible = "fsl,imx6sx-fec", .data = &fec_imx6sx_info, }, 201 { .compatible = "fsl,imx6ul-fec", .data = &fec_imx6ul_info, }, 202 { .compatible = "fsl,imx8mq-fec", .data = &fec_imx8mq_info, }, 203 { .compatible = "fsl,imx8qm-fec", .data = &fec_imx8qm_info, }, 204 { .compatible = "fsl,s32v234-fec", .data = &fec_s32v234_info, }, 205 { /* sentinel */ } 206 }; 207 MODULE_DEVICE_TABLE(of, fec_dt_ids); 208 209 static unsigned char macaddr[ETH_ALEN]; 210 module_param_array(macaddr, byte, NULL, 0); 211 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 212 213 #if defined(CONFIG_M5272) 214 /* 215 * Some hardware gets it MAC address out of local flash memory. 216 * if this is non-zero then assume it is the address to get MAC from. 217 */ 218 #if defined(CONFIG_NETtel) 219 #define FEC_FLASHMAC 0xf0006006 220 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 221 #define FEC_FLASHMAC 0xf0006000 222 #elif defined(CONFIG_CANCam) 223 #define FEC_FLASHMAC 0xf0020000 224 #elif defined (CONFIG_M5272C3) 225 #define FEC_FLASHMAC (0xffe04000 + 4) 226 #elif defined(CONFIG_MOD5272) 227 #define FEC_FLASHMAC 0xffc0406b 228 #else 229 #define FEC_FLASHMAC 0 230 #endif 231 #endif /* CONFIG_M5272 */ 232 233 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 234 * 235 * 2048 byte skbufs are allocated. However, alignment requirements 236 * varies between FEC variants. Worst case is 64, so round down by 64. 237 */ 238 #define MAX_JUMBO_BUF_SIZE (round_down(16384 - FEC_DRV_RESERVE_SPACE - 64, 64)) 239 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 240 #define PKT_MINBUF_SIZE 64 241 242 /* FEC receive acceleration */ 243 #define FEC_RACC_IPDIS BIT(1) 244 #define FEC_RACC_PRODIS BIT(2) 245 #define FEC_RACC_SHIFT16 BIT(7) 246 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 247 248 /* MIB Control Register */ 249 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 250 251 /* 252 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 253 * size bits. Other FEC hardware does not, so we need to take that into 254 * account when setting it. 255 */ 256 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 257 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 258 defined(CONFIG_ARM64) 259 #define OPT_ARCH_HAS_MAX_FL 1 260 #else 261 #define OPT_ARCH_HAS_MAX_FL 0 262 #endif 263 264 /* FEC MII MMFR bits definition */ 265 #define FEC_MMFR_ST (1 << 30) 266 #define FEC_MMFR_ST_C45 (0) 267 #define FEC_MMFR_OP_READ (2 << 28) 268 #define FEC_MMFR_OP_READ_C45 (3 << 28) 269 #define FEC_MMFR_OP_WRITE (1 << 28) 270 #define FEC_MMFR_OP_ADDR_WRITE (0) 271 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 272 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 273 #define FEC_MMFR_TA (2 << 16) 274 #define FEC_MMFR_DATA(v) (v & 0xffff) 275 /* FEC ECR bits definition */ 276 #define FEC_ECR_RESET BIT(0) 277 #define FEC_ECR_ETHEREN BIT(1) 278 #define FEC_ECR_MAGICEN BIT(2) 279 #define FEC_ECR_SLEEP BIT(3) 280 #define FEC_ECR_EN1588 BIT(4) 281 #define FEC_ECR_SPEED BIT(5) 282 #define FEC_ECR_BYTESWP BIT(8) 283 /* FEC RCR bits definition */ 284 #define FEC_RCR_LOOP BIT(0) 285 #define FEC_RCR_DRT BIT(1) 286 #define FEC_RCR_MII BIT(2) 287 #define FEC_RCR_PROMISC BIT(3) 288 #define FEC_RCR_BC_REJ BIT(4) 289 #define FEC_RCR_FLOWCTL BIT(5) 290 #define FEC_RCR_RGMII BIT(6) 291 #define FEC_RCR_RMII BIT(8) 292 #define FEC_RCR_10BASET BIT(9) 293 #define FEC_RCR_NLC BIT(30) 294 /* TX WMARK bits */ 295 #define FEC_TXWMRK_STRFWD BIT(8) 296 297 #define FEC_MII_TIMEOUT 30000 /* us */ 298 299 /* Transmitter timeout */ 300 #define TX_TIMEOUT (2 * HZ) 301 302 #define FEC_PAUSE_FLAG_AUTONEG 0x1 303 #define FEC_PAUSE_FLAG_ENABLE 0x2 304 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 305 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 306 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 307 308 /* Max number of allowed TCP segments for software TSO */ 309 #define FEC_MAX_TSO_SEGS 100 310 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 311 312 #define IS_TSO_HEADER(txq, addr) \ 313 ((addr >= txq->tso_hdrs_dma) && \ 314 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 315 316 static int mii_cnt; 317 318 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 319 struct bufdesc_prop *bd) 320 { 321 return (bdp >= bd->last) ? bd->base 322 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 323 } 324 325 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 326 struct bufdesc_prop *bd) 327 { 328 return (bdp <= bd->base) ? bd->last 329 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 330 } 331 332 static int fec_enet_get_bd_index(struct bufdesc *bdp, 333 struct bufdesc_prop *bd) 334 { 335 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 336 } 337 338 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 339 { 340 int entries; 341 342 entries = (((const char *)txq->dirty_tx - 343 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 344 345 return entries >= 0 ? entries : entries + txq->bd.ring_size; 346 } 347 348 static void swap_buffer(void *bufaddr, int len) 349 { 350 int i; 351 unsigned int *buf = bufaddr; 352 353 for (i = 0; i < len; i += 4, buf++) 354 swab32s(buf); 355 } 356 357 static void fec_dump(struct net_device *ndev) 358 { 359 struct fec_enet_private *fep = netdev_priv(ndev); 360 struct bufdesc *bdp; 361 struct fec_enet_priv_tx_q *txq; 362 int index = 0; 363 364 netdev_info(ndev, "TX ring dump\n"); 365 pr_info("Nr SC addr len SKB\n"); 366 367 txq = fep->tx_queue[0]; 368 bdp = txq->bd.base; 369 370 do { 371 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 372 index, 373 bdp == txq->bd.cur ? 'S' : ' ', 374 bdp == txq->dirty_tx ? 'H' : ' ', 375 fec16_to_cpu(bdp->cbd_sc), 376 fec32_to_cpu(bdp->cbd_bufaddr), 377 fec16_to_cpu(bdp->cbd_datlen), 378 txq->tx_buf[index].buf_p); 379 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 380 index++; 381 } while (bdp != txq->bd.base); 382 } 383 384 /* 385 * Coldfire does not support DMA coherent allocations, and has historically used 386 * a band-aid with a manual flush in fec_enet_rx_queue. 387 */ 388 #if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA) 389 static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, 390 gfp_t gfp) 391 { 392 return dma_alloc_noncoherent(dev, size, handle, DMA_BIDIRECTIONAL, gfp); 393 } 394 395 static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr, 396 dma_addr_t handle) 397 { 398 dma_free_noncoherent(dev, size, cpu_addr, handle, DMA_BIDIRECTIONAL); 399 } 400 #else /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */ 401 static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, 402 gfp_t gfp) 403 { 404 return dma_alloc_coherent(dev, size, handle, gfp); 405 } 406 407 static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr, 408 dma_addr_t handle) 409 { 410 dma_free_coherent(dev, size, cpu_addr, handle); 411 } 412 #endif /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */ 413 414 struct fec_dma_devres { 415 size_t size; 416 void *vaddr; 417 dma_addr_t dma_handle; 418 }; 419 420 static void fec_dmam_release(struct device *dev, void *res) 421 { 422 struct fec_dma_devres *this = res; 423 424 fec_dma_free(dev, this->size, this->vaddr, this->dma_handle); 425 } 426 427 static void *fec_dmam_alloc(struct device *dev, size_t size, dma_addr_t *handle, 428 gfp_t gfp) 429 { 430 struct fec_dma_devres *dr; 431 void *vaddr; 432 433 dr = devres_alloc(fec_dmam_release, sizeof(*dr), gfp); 434 if (!dr) 435 return NULL; 436 vaddr = fec_dma_alloc(dev, size, handle, gfp); 437 if (!vaddr) { 438 devres_free(dr); 439 return NULL; 440 } 441 dr->vaddr = vaddr; 442 dr->dma_handle = *handle; 443 dr->size = size; 444 devres_add(dev, dr); 445 return vaddr; 446 } 447 448 static inline bool is_ipv4_pkt(struct sk_buff *skb) 449 { 450 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 451 } 452 453 static int 454 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 455 { 456 /* Only run for packets requiring a checksum. */ 457 if (skb->ip_summed != CHECKSUM_PARTIAL) 458 return 0; 459 460 if (unlikely(skb_cow_head(skb, 0))) 461 return -1; 462 463 if (is_ipv4_pkt(skb)) 464 ip_hdr(skb)->check = 0; 465 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 466 467 return 0; 468 } 469 470 static int 471 fec_enet_create_page_pool(struct fec_enet_private *fep, 472 struct fec_enet_priv_rx_q *rxq, int size) 473 { 474 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 475 struct page_pool_params pp_params = { 476 .order = fep->pagepool_order, 477 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 478 .pool_size = size, 479 .nid = dev_to_node(&fep->pdev->dev), 480 .dev = &fep->pdev->dev, 481 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 482 .offset = FEC_ENET_XDP_HEADROOM, 483 .max_len = fep->rx_frame_size, 484 }; 485 int err; 486 487 rxq->page_pool = page_pool_create(&pp_params); 488 if (IS_ERR(rxq->page_pool)) { 489 err = PTR_ERR(rxq->page_pool); 490 rxq->page_pool = NULL; 491 return err; 492 } 493 494 err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0); 495 if (err < 0) 496 goto err_free_pp; 497 498 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 499 rxq->page_pool); 500 if (err) 501 goto err_unregister_rxq; 502 503 return 0; 504 505 err_unregister_rxq: 506 xdp_rxq_info_unreg(&rxq->xdp_rxq); 507 err_free_pp: 508 page_pool_destroy(rxq->page_pool); 509 rxq->page_pool = NULL; 510 return err; 511 } 512 513 static struct bufdesc * 514 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 515 struct sk_buff *skb, 516 struct net_device *ndev) 517 { 518 struct fec_enet_private *fep = netdev_priv(ndev); 519 struct bufdesc *bdp = txq->bd.cur; 520 struct bufdesc_ex *ebdp; 521 int nr_frags = skb_shinfo(skb)->nr_frags; 522 int frag, frag_len; 523 unsigned short status; 524 unsigned int estatus = 0; 525 skb_frag_t *this_frag; 526 unsigned int index; 527 void *bufaddr; 528 dma_addr_t addr; 529 int i; 530 531 for (frag = 0; frag < nr_frags; frag++) { 532 this_frag = &skb_shinfo(skb)->frags[frag]; 533 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 534 ebdp = (struct bufdesc_ex *)bdp; 535 536 status = fec16_to_cpu(bdp->cbd_sc); 537 status &= ~BD_ENET_TX_STATS; 538 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 539 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 540 541 /* Handle the last BD specially */ 542 if (frag == nr_frags - 1) { 543 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 544 if (fep->bufdesc_ex) { 545 estatus |= BD_ENET_TX_INT; 546 if (unlikely(skb_shinfo(skb)->tx_flags & 547 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 548 estatus |= BD_ENET_TX_TS; 549 } 550 } 551 552 if (fep->bufdesc_ex) { 553 if (fep->quirks & FEC_QUIRK_HAS_AVB) 554 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 555 if (skb->ip_summed == CHECKSUM_PARTIAL) 556 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 557 558 ebdp->cbd_bdu = 0; 559 ebdp->cbd_esc = cpu_to_fec32(estatus); 560 } 561 562 bufaddr = skb_frag_address(this_frag); 563 564 index = fec_enet_get_bd_index(bdp, &txq->bd); 565 if (((unsigned long) bufaddr) & fep->tx_align || 566 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 567 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 568 bufaddr = txq->tx_bounce[index]; 569 570 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 571 swap_buffer(bufaddr, frag_len); 572 } 573 574 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 575 DMA_TO_DEVICE); 576 if (dma_mapping_error(&fep->pdev->dev, addr)) { 577 if (net_ratelimit()) 578 netdev_err(ndev, "Tx DMA memory map failed\n"); 579 goto dma_mapping_error; 580 } 581 582 bdp->cbd_bufaddr = cpu_to_fec32(addr); 583 bdp->cbd_datlen = cpu_to_fec16(frag_len); 584 /* Make sure the updates to rest of the descriptor are 585 * performed before transferring ownership. 586 */ 587 wmb(); 588 bdp->cbd_sc = cpu_to_fec16(status); 589 } 590 591 return bdp; 592 dma_mapping_error: 593 bdp = txq->bd.cur; 594 for (i = 0; i < frag; i++) { 595 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 596 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 597 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 598 } 599 return ERR_PTR(-ENOMEM); 600 } 601 602 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 603 struct sk_buff *skb, struct net_device *ndev) 604 { 605 struct fec_enet_private *fep = netdev_priv(ndev); 606 int nr_frags = skb_shinfo(skb)->nr_frags; 607 struct bufdesc *bdp, *last_bdp; 608 void *bufaddr; 609 dma_addr_t addr; 610 unsigned short status; 611 unsigned short buflen; 612 unsigned int estatus = 0; 613 unsigned int index; 614 int entries_free; 615 616 entries_free = fec_enet_get_free_txdesc_num(txq); 617 if (entries_free < MAX_SKB_FRAGS + 1) { 618 dev_kfree_skb_any(skb); 619 if (net_ratelimit()) 620 netdev_err(ndev, "NOT enough BD for SG!\n"); 621 return NETDEV_TX_OK; 622 } 623 624 /* Protocol checksum off-load for TCP and UDP. */ 625 if (fec_enet_clear_csum(skb, ndev)) { 626 dev_kfree_skb_any(skb); 627 return NETDEV_TX_OK; 628 } 629 630 /* Fill in a Tx ring entry */ 631 bdp = txq->bd.cur; 632 last_bdp = bdp; 633 status = fec16_to_cpu(bdp->cbd_sc); 634 status &= ~BD_ENET_TX_STATS; 635 636 /* Set buffer length and buffer pointer */ 637 bufaddr = skb->data; 638 buflen = skb_headlen(skb); 639 640 index = fec_enet_get_bd_index(bdp, &txq->bd); 641 if (((unsigned long) bufaddr) & fep->tx_align || 642 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 643 memcpy(txq->tx_bounce[index], skb->data, buflen); 644 bufaddr = txq->tx_bounce[index]; 645 646 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 647 swap_buffer(bufaddr, buflen); 648 } 649 650 /* Push the data cache so the CPM does not get stale memory data. */ 651 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 652 if (dma_mapping_error(&fep->pdev->dev, addr)) { 653 dev_kfree_skb_any(skb); 654 if (net_ratelimit()) 655 netdev_err(ndev, "Tx DMA memory map failed\n"); 656 return NETDEV_TX_OK; 657 } 658 659 if (nr_frags) { 660 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 661 if (IS_ERR(last_bdp)) { 662 dma_unmap_single(&fep->pdev->dev, addr, 663 buflen, DMA_TO_DEVICE); 664 dev_kfree_skb_any(skb); 665 return NETDEV_TX_OK; 666 } 667 } else { 668 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 669 if (fep->bufdesc_ex) { 670 estatus = BD_ENET_TX_INT; 671 if (unlikely(skb_shinfo(skb)->tx_flags & 672 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 673 estatus |= BD_ENET_TX_TS; 674 } 675 } 676 bdp->cbd_bufaddr = cpu_to_fec32(addr); 677 bdp->cbd_datlen = cpu_to_fec16(buflen); 678 679 if (fep->bufdesc_ex) { 680 681 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 682 683 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 684 fep->hwts_tx_en)) 685 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 686 687 if (fep->quirks & FEC_QUIRK_HAS_AVB) 688 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 689 690 if (skb->ip_summed == CHECKSUM_PARTIAL) 691 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 692 693 ebdp->cbd_bdu = 0; 694 ebdp->cbd_esc = cpu_to_fec32(estatus); 695 } 696 697 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 698 /* Save skb pointer */ 699 txq->tx_buf[index].buf_p = skb; 700 701 /* Make sure the updates to rest of the descriptor are performed before 702 * transferring ownership. 703 */ 704 wmb(); 705 706 /* Send it on its way. Tell FEC it's ready, interrupt when done, 707 * it's the last BD of the frame, and to put the CRC on the end. 708 */ 709 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 710 bdp->cbd_sc = cpu_to_fec16(status); 711 712 /* If this was the last BD in the ring, start at the beginning again. */ 713 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 714 715 skb_tx_timestamp(skb); 716 717 /* Make sure the update to bdp is performed before txq->bd.cur. */ 718 wmb(); 719 txq->bd.cur = bdp; 720 721 /* Trigger transmission start */ 722 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 723 !readl(txq->bd.reg_desc_active) || 724 !readl(txq->bd.reg_desc_active) || 725 !readl(txq->bd.reg_desc_active) || 726 !readl(txq->bd.reg_desc_active)) 727 writel(0, txq->bd.reg_desc_active); 728 729 return 0; 730 } 731 732 static int 733 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 734 struct net_device *ndev, 735 struct bufdesc *bdp, int index, char *data, 736 int size, bool last_tcp, bool is_last) 737 { 738 struct fec_enet_private *fep = netdev_priv(ndev); 739 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 740 unsigned short status; 741 unsigned int estatus = 0; 742 dma_addr_t addr; 743 744 status = fec16_to_cpu(bdp->cbd_sc); 745 status &= ~BD_ENET_TX_STATS; 746 747 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 748 749 if (((unsigned long) data) & fep->tx_align || 750 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 751 memcpy(txq->tx_bounce[index], data, size); 752 data = txq->tx_bounce[index]; 753 754 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 755 swap_buffer(data, size); 756 } 757 758 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 759 if (dma_mapping_error(&fep->pdev->dev, addr)) { 760 dev_kfree_skb_any(skb); 761 if (net_ratelimit()) 762 netdev_err(ndev, "Tx DMA memory map failed\n"); 763 return NETDEV_TX_OK; 764 } 765 766 bdp->cbd_datlen = cpu_to_fec16(size); 767 bdp->cbd_bufaddr = cpu_to_fec32(addr); 768 769 if (fep->bufdesc_ex) { 770 if (fep->quirks & FEC_QUIRK_HAS_AVB) 771 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 772 if (skb->ip_summed == CHECKSUM_PARTIAL) 773 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 774 ebdp->cbd_bdu = 0; 775 ebdp->cbd_esc = cpu_to_fec32(estatus); 776 } 777 778 /* Handle the last BD specially */ 779 if (last_tcp) 780 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 781 if (is_last) { 782 status |= BD_ENET_TX_INTR; 783 if (fep->bufdesc_ex) 784 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 785 } 786 787 bdp->cbd_sc = cpu_to_fec16(status); 788 789 return 0; 790 } 791 792 static int 793 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 794 struct sk_buff *skb, struct net_device *ndev, 795 struct bufdesc *bdp, int index) 796 { 797 struct fec_enet_private *fep = netdev_priv(ndev); 798 int hdr_len = skb_tcp_all_headers(skb); 799 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 800 void *bufaddr; 801 unsigned long dmabuf; 802 unsigned short status; 803 unsigned int estatus = 0; 804 805 status = fec16_to_cpu(bdp->cbd_sc); 806 status &= ~BD_ENET_TX_STATS; 807 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 808 809 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 810 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 811 if (((unsigned long)bufaddr) & fep->tx_align || 812 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 813 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 814 bufaddr = txq->tx_bounce[index]; 815 816 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 817 swap_buffer(bufaddr, hdr_len); 818 819 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 820 hdr_len, DMA_TO_DEVICE); 821 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 822 dev_kfree_skb_any(skb); 823 if (net_ratelimit()) 824 netdev_err(ndev, "Tx DMA memory map failed\n"); 825 return NETDEV_TX_OK; 826 } 827 } 828 829 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 830 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 831 832 if (fep->bufdesc_ex) { 833 if (fep->quirks & FEC_QUIRK_HAS_AVB) 834 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 835 if (skb->ip_summed == CHECKSUM_PARTIAL) 836 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 837 ebdp->cbd_bdu = 0; 838 ebdp->cbd_esc = cpu_to_fec32(estatus); 839 } 840 841 bdp->cbd_sc = cpu_to_fec16(status); 842 843 return 0; 844 } 845 846 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 847 struct sk_buff *skb, 848 struct net_device *ndev) 849 { 850 struct fec_enet_private *fep = netdev_priv(ndev); 851 int hdr_len, total_len, data_left; 852 struct bufdesc *bdp = txq->bd.cur; 853 struct bufdesc *tmp_bdp; 854 struct bufdesc_ex *ebdp; 855 struct tso_t tso; 856 unsigned int index = 0; 857 int ret; 858 859 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 860 dev_kfree_skb_any(skb); 861 if (net_ratelimit()) 862 netdev_err(ndev, "NOT enough BD for TSO!\n"); 863 return NETDEV_TX_OK; 864 } 865 866 /* Protocol checksum off-load for TCP and UDP. */ 867 if (fec_enet_clear_csum(skb, ndev)) { 868 dev_kfree_skb_any(skb); 869 return NETDEV_TX_OK; 870 } 871 872 /* Initialize the TSO handler, and prepare the first payload */ 873 hdr_len = tso_start(skb, &tso); 874 875 total_len = skb->len - hdr_len; 876 while (total_len > 0) { 877 char *hdr; 878 879 index = fec_enet_get_bd_index(bdp, &txq->bd); 880 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 881 total_len -= data_left; 882 883 /* prepare packet headers: MAC + IP + TCP */ 884 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 885 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 886 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 887 if (ret) 888 goto err_release; 889 890 while (data_left > 0) { 891 int size; 892 893 size = min_t(int, tso.size, data_left); 894 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 895 index = fec_enet_get_bd_index(bdp, &txq->bd); 896 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 897 bdp, index, 898 tso.data, size, 899 size == data_left, 900 total_len == 0); 901 if (ret) 902 goto err_release; 903 904 data_left -= size; 905 tso_build_data(skb, &tso, size); 906 } 907 908 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 909 } 910 911 /* Save skb pointer */ 912 txq->tx_buf[index].buf_p = skb; 913 914 skb_tx_timestamp(skb); 915 txq->bd.cur = bdp; 916 917 /* Trigger transmission start */ 918 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 919 !readl(txq->bd.reg_desc_active) || 920 !readl(txq->bd.reg_desc_active) || 921 !readl(txq->bd.reg_desc_active) || 922 !readl(txq->bd.reg_desc_active)) 923 writel(0, txq->bd.reg_desc_active); 924 925 return 0; 926 927 err_release: 928 /* Release all used data descriptors for TSO */ 929 tmp_bdp = txq->bd.cur; 930 931 while (tmp_bdp != bdp) { 932 /* Unmap data buffers */ 933 if (tmp_bdp->cbd_bufaddr && 934 !IS_TSO_HEADER(txq, fec32_to_cpu(tmp_bdp->cbd_bufaddr))) 935 dma_unmap_single(&fep->pdev->dev, 936 fec32_to_cpu(tmp_bdp->cbd_bufaddr), 937 fec16_to_cpu(tmp_bdp->cbd_datlen), 938 DMA_TO_DEVICE); 939 940 /* Clear standard buffer descriptor fields */ 941 tmp_bdp->cbd_sc = 0; 942 tmp_bdp->cbd_datlen = 0; 943 tmp_bdp->cbd_bufaddr = 0; 944 945 /* Handle extended descriptor if enabled */ 946 if (fep->bufdesc_ex) { 947 ebdp = (struct bufdesc_ex *)tmp_bdp; 948 ebdp->cbd_esc = 0; 949 } 950 951 tmp_bdp = fec_enet_get_nextdesc(tmp_bdp, &txq->bd); 952 } 953 954 dev_kfree_skb_any(skb); 955 956 return ret; 957 } 958 959 static netdev_tx_t 960 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 961 { 962 struct fec_enet_private *fep = netdev_priv(ndev); 963 int entries_free; 964 unsigned short queue; 965 struct fec_enet_priv_tx_q *txq; 966 struct netdev_queue *nq; 967 int ret; 968 969 queue = skb_get_queue_mapping(skb); 970 txq = fep->tx_queue[queue]; 971 nq = netdev_get_tx_queue(ndev, queue); 972 973 if (skb_is_gso(skb)) 974 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 975 else 976 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 977 if (ret) 978 return ret; 979 980 entries_free = fec_enet_get_free_txdesc_num(txq); 981 if (entries_free <= txq->tx_stop_threshold) 982 netif_tx_stop_queue(nq); 983 984 return NETDEV_TX_OK; 985 } 986 987 /* Init RX & TX buffer descriptors 988 */ 989 static void fec_enet_bd_init(struct net_device *dev) 990 { 991 struct fec_enet_private *fep = netdev_priv(dev); 992 struct fec_enet_priv_tx_q *txq; 993 struct fec_enet_priv_rx_q *rxq; 994 struct bufdesc *bdp; 995 unsigned int i; 996 unsigned int q; 997 998 for (q = 0; q < fep->num_rx_queues; q++) { 999 /* Initialize the receive buffer descriptors. */ 1000 rxq = fep->rx_queue[q]; 1001 bdp = rxq->bd.base; 1002 1003 for (i = 0; i < rxq->bd.ring_size; i++) { 1004 1005 /* Initialize the BD for every fragment in the page. */ 1006 if (bdp->cbd_bufaddr) 1007 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 1008 else 1009 bdp->cbd_sc = cpu_to_fec16(0); 1010 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1011 } 1012 1013 /* Set the last buffer to wrap */ 1014 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 1015 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 1016 1017 rxq->bd.cur = rxq->bd.base; 1018 } 1019 1020 for (q = 0; q < fep->num_tx_queues; q++) { 1021 /* ...and the same for transmit */ 1022 txq = fep->tx_queue[q]; 1023 bdp = txq->bd.base; 1024 txq->bd.cur = bdp; 1025 1026 for (i = 0; i < txq->bd.ring_size; i++) { 1027 /* Initialize the BD for every fragment in the page. */ 1028 bdp->cbd_sc = cpu_to_fec16(0); 1029 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 1030 if (bdp->cbd_bufaddr && 1031 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1032 dma_unmap_single(&fep->pdev->dev, 1033 fec32_to_cpu(bdp->cbd_bufaddr), 1034 fec16_to_cpu(bdp->cbd_datlen), 1035 DMA_TO_DEVICE); 1036 if (txq->tx_buf[i].buf_p) 1037 dev_kfree_skb_any(txq->tx_buf[i].buf_p); 1038 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 1039 if (bdp->cbd_bufaddr) 1040 dma_unmap_single(&fep->pdev->dev, 1041 fec32_to_cpu(bdp->cbd_bufaddr), 1042 fec16_to_cpu(bdp->cbd_datlen), 1043 DMA_TO_DEVICE); 1044 1045 if (txq->tx_buf[i].buf_p) 1046 xdp_return_frame(txq->tx_buf[i].buf_p); 1047 } else { 1048 struct page *page = txq->tx_buf[i].buf_p; 1049 1050 if (page) 1051 page_pool_put_page(pp_page_to_nmdesc(page)->pp, 1052 page, 0, 1053 false); 1054 } 1055 1056 txq->tx_buf[i].buf_p = NULL; 1057 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1058 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 1059 bdp->cbd_bufaddr = cpu_to_fec32(0); 1060 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1061 } 1062 1063 /* Set the last buffer to wrap */ 1064 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 1065 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 1066 txq->dirty_tx = bdp; 1067 } 1068 } 1069 1070 static void fec_enet_active_rxring(struct net_device *ndev) 1071 { 1072 struct fec_enet_private *fep = netdev_priv(ndev); 1073 int i; 1074 1075 for (i = 0; i < fep->num_rx_queues; i++) 1076 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 1077 } 1078 1079 static void fec_enet_enable_ring(struct net_device *ndev) 1080 { 1081 struct fec_enet_private *fep = netdev_priv(ndev); 1082 struct fec_enet_priv_tx_q *txq; 1083 struct fec_enet_priv_rx_q *rxq; 1084 int i; 1085 1086 for (i = 0; i < fep->num_rx_queues; i++) { 1087 rxq = fep->rx_queue[i]; 1088 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 1089 writel(fep->max_buf_size, fep->hwp + FEC_R_BUFF_SIZE(i)); 1090 1091 /* enable DMA1/2 */ 1092 if (i) 1093 writel(RCMR_MATCHEN | RCMR_CMP(i), 1094 fep->hwp + FEC_RCMR(i)); 1095 } 1096 1097 for (i = 0; i < fep->num_tx_queues; i++) { 1098 txq = fep->tx_queue[i]; 1099 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 1100 1101 /* enable DMA1/2 */ 1102 if (i) 1103 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 1104 fep->hwp + FEC_DMA_CFG(i)); 1105 } 1106 } 1107 1108 /* Whack a reset. We should wait for this. 1109 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1110 * instead of reset MAC itself. 1111 */ 1112 static void fec_ctrl_reset(struct fec_enet_private *fep, bool allow_wol) 1113 { 1114 u32 val; 1115 1116 if (!allow_wol || !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1117 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || 1118 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 1119 writel(0, fep->hwp + FEC_ECNTRL); 1120 } else { 1121 writel(FEC_ECR_RESET, fep->hwp + FEC_ECNTRL); 1122 udelay(10); 1123 } 1124 } else { 1125 val = readl(fep->hwp + FEC_ECNTRL); 1126 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1127 writel(val, fep->hwp + FEC_ECNTRL); 1128 } 1129 } 1130 1131 static void fec_set_hw_mac_addr(struct net_device *ndev) 1132 { 1133 struct fec_enet_private *fep = netdev_priv(ndev); 1134 1135 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 1136 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 1137 fep->hwp + FEC_ADDR_LOW); 1138 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 1139 fep->hwp + FEC_ADDR_HIGH); 1140 } 1141 1142 /* 1143 * This function is called to start or restart the FEC during a link 1144 * change, transmit timeout, or to reconfigure the FEC. The network 1145 * packet processing for this device must be stopped before this call. 1146 */ 1147 static void 1148 fec_restart(struct net_device *ndev) 1149 { 1150 struct fec_enet_private *fep = netdev_priv(ndev); 1151 u32 ecntl = FEC_ECR_ETHEREN; 1152 u32 rcntl = FEC_RCR_MII; 1153 1154 if (OPT_ARCH_HAS_MAX_FL) 1155 rcntl |= (fep->netdev->mtu + ETH_HLEN + ETH_FCS_LEN) << 16; 1156 1157 if (fep->bufdesc_ex) 1158 fec_ptp_save_state(fep); 1159 1160 fec_ctrl_reset(fep, false); 1161 1162 /* 1163 * enet-mac reset will reset mac address registers too, 1164 * so need to reconfigure it. 1165 */ 1166 fec_set_hw_mac_addr(ndev); 1167 1168 /* Clear any outstanding interrupt, except MDIO. */ 1169 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 1170 1171 fec_enet_bd_init(ndev); 1172 1173 fec_enet_enable_ring(ndev); 1174 1175 /* Enable MII mode */ 1176 if (fep->full_duplex == DUPLEX_FULL) { 1177 /* FD enable */ 1178 writel(0x04, fep->hwp + FEC_X_CNTRL); 1179 } else { 1180 /* No Rcv on Xmit */ 1181 rcntl |= FEC_RCR_DRT; 1182 writel(0x0, fep->hwp + FEC_X_CNTRL); 1183 } 1184 1185 /* Set MII speed */ 1186 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1187 1188 #if !defined(CONFIG_M5272) 1189 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1190 u32 val = readl(fep->hwp + FEC_RACC); 1191 1192 /* align IP header */ 1193 val |= FEC_RACC_SHIFT16; 1194 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1195 /* set RX checksum */ 1196 val |= FEC_RACC_OPTIONS; 1197 else 1198 val &= ~FEC_RACC_OPTIONS; 1199 writel(val, fep->hwp + FEC_RACC); 1200 writel(min(fep->rx_frame_size, fep->max_buf_size), fep->hwp + FEC_FTRL); 1201 } 1202 #endif 1203 1204 /* 1205 * The phy interface and speed need to get configured 1206 * differently on enet-mac. 1207 */ 1208 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1209 /* Enable flow control and length check */ 1210 rcntl |= FEC_RCR_NLC | FEC_RCR_FLOWCTL; 1211 1212 /* RGMII, RMII or MII */ 1213 if (phy_interface_mode_is_rgmii(fep->phy_interface)) 1214 rcntl |= FEC_RCR_RGMII; 1215 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1216 rcntl |= FEC_RCR_RMII; 1217 else 1218 rcntl &= ~FEC_RCR_RMII; 1219 1220 /* 1G, 100M or 10M */ 1221 if (ndev->phydev) { 1222 if (ndev->phydev->speed == SPEED_1000) 1223 ecntl |= FEC_ECR_SPEED; 1224 else if (ndev->phydev->speed == SPEED_100) 1225 rcntl &= ~FEC_RCR_10BASET; 1226 else 1227 rcntl |= FEC_RCR_10BASET; 1228 } 1229 } else { 1230 #ifdef FEC_MIIGSK_ENR 1231 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1232 u32 cfgr; 1233 /* disable the gasket and wait */ 1234 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1235 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1236 udelay(1); 1237 1238 /* 1239 * configure the gasket: 1240 * RMII, 50 MHz, no loopback, no echo 1241 * MII, 25 MHz, no loopback, no echo 1242 */ 1243 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1244 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1245 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1246 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1247 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1248 1249 /* re-enable the gasket */ 1250 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1251 } 1252 #endif 1253 } 1254 1255 #if !defined(CONFIG_M5272) 1256 /* enable pause frame*/ 1257 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1258 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1259 ndev->phydev && ndev->phydev->pause)) { 1260 rcntl |= FEC_RCR_FLOWCTL; 1261 1262 /* set FIFO threshold parameter to reduce overrun */ 1263 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1264 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1265 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1266 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1267 1268 /* OPD */ 1269 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1270 } else { 1271 rcntl &= ~FEC_RCR_FLOWCTL; 1272 } 1273 #endif /* !defined(CONFIG_M5272) */ 1274 1275 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1276 1277 /* Setup multicast filter. */ 1278 set_multicast_list(ndev); 1279 #ifndef CONFIG_M5272 1280 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1281 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1282 #endif 1283 1284 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1285 /* enable ENET endian swap */ 1286 ecntl |= FEC_ECR_BYTESWP; 1287 1288 /* When Jumbo Frame is enabled, the FIFO may not be large enough 1289 * to hold an entire frame. In such cases, if the MTU exceeds 1290 * (PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN), configure the interface 1291 * to operate in cut-through mode, triggered by the FIFO threshold. 1292 * Otherwise, enable the ENET store-and-forward mode. 1293 */ 1294 if ((fep->quirks & FEC_QUIRK_JUMBO_FRAME) && 1295 (ndev->mtu > (PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN))) 1296 writel(0xF, fep->hwp + FEC_X_WMRK); 1297 else 1298 writel(FEC_TXWMRK_STRFWD, fep->hwp + FEC_X_WMRK); 1299 } 1300 1301 if (fep->bufdesc_ex) 1302 ecntl |= FEC_ECR_EN1588; 1303 1304 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1305 fep->rgmii_txc_dly) 1306 ecntl |= FEC_ENET_TXC_DLY; 1307 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1308 fep->rgmii_rxc_dly) 1309 ecntl |= FEC_ENET_RXC_DLY; 1310 1311 #ifndef CONFIG_M5272 1312 /* Enable the MIB statistic event counters */ 1313 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1314 #endif 1315 1316 /* And last, enable the transmit and receive processing */ 1317 writel(ecntl, fep->hwp + FEC_ECNTRL); 1318 fec_enet_active_rxring(ndev); 1319 1320 if (fep->bufdesc_ex) { 1321 fec_ptp_start_cyclecounter(ndev); 1322 fec_ptp_restore_state(fep); 1323 } 1324 1325 /* Enable interrupts we wish to service */ 1326 if (fep->link) 1327 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1328 else 1329 writel(0, fep->hwp + FEC_IMASK); 1330 1331 /* Init the interrupt coalescing */ 1332 if (fep->quirks & FEC_QUIRK_HAS_COALESCE) 1333 fec_enet_itr_coal_set(ndev); 1334 } 1335 1336 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep) 1337 { 1338 if (!(of_machine_is_compatible("fsl,imx8qm") || 1339 of_machine_is_compatible("fsl,imx8qxp") || 1340 of_machine_is_compatible("fsl,imx8dxl"))) 1341 return 0; 1342 1343 return imx_scu_get_handle(&fep->ipc_handle); 1344 } 1345 1346 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled) 1347 { 1348 struct device_node *np = fep->pdev->dev.of_node; 1349 u32 rsrc_id, val; 1350 int idx; 1351 1352 if (!np || !fep->ipc_handle) 1353 return; 1354 1355 idx = of_alias_get_id(np, "ethernet"); 1356 if (idx < 0) 1357 idx = 0; 1358 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0; 1359 1360 val = enabled ? 1 : 0; 1361 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val); 1362 } 1363 1364 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1365 { 1366 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1367 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1368 1369 if (stop_gpr->gpr) { 1370 if (enabled) 1371 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1372 BIT(stop_gpr->bit), 1373 BIT(stop_gpr->bit)); 1374 else 1375 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1376 BIT(stop_gpr->bit), 0); 1377 } else if (pdata && pdata->sleep_mode_enable) { 1378 pdata->sleep_mode_enable(enabled); 1379 } else { 1380 fec_enet_ipg_stop_set(fep, enabled); 1381 } 1382 } 1383 1384 static void fec_irqs_disable(struct net_device *ndev) 1385 { 1386 struct fec_enet_private *fep = netdev_priv(ndev); 1387 1388 writel(0, fep->hwp + FEC_IMASK); 1389 } 1390 1391 static void fec_irqs_disable_except_wakeup(struct net_device *ndev) 1392 { 1393 struct fec_enet_private *fep = netdev_priv(ndev); 1394 1395 writel(0, fep->hwp + FEC_IMASK); 1396 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1397 } 1398 1399 static void 1400 fec_stop(struct net_device *ndev) 1401 { 1402 struct fec_enet_private *fep = netdev_priv(ndev); 1403 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & FEC_RCR_RMII; 1404 u32 val; 1405 1406 /* We cannot expect a graceful transmit stop without link !!! */ 1407 if (fep->link) { 1408 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1409 udelay(10); 1410 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1411 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1412 } 1413 1414 if (fep->bufdesc_ex) 1415 fec_ptp_save_state(fep); 1416 1417 fec_ctrl_reset(fep, true); 1418 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1419 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1420 1421 /* We have to keep ENET enabled to have MII interrupt stay working */ 1422 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1423 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1424 writel(FEC_ECR_ETHEREN, fep->hwp + FEC_ECNTRL); 1425 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1426 } 1427 1428 if (fep->bufdesc_ex) { 1429 val = readl(fep->hwp + FEC_ECNTRL); 1430 val |= FEC_ECR_EN1588; 1431 writel(val, fep->hwp + FEC_ECNTRL); 1432 1433 fec_ptp_start_cyclecounter(ndev); 1434 fec_ptp_restore_state(fep); 1435 } 1436 } 1437 1438 static void 1439 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1440 { 1441 struct fec_enet_private *fep = netdev_priv(ndev); 1442 1443 fec_dump(ndev); 1444 1445 ndev->stats.tx_errors++; 1446 1447 schedule_work(&fep->tx_timeout_work); 1448 } 1449 1450 static void fec_enet_timeout_work(struct work_struct *work) 1451 { 1452 struct fec_enet_private *fep = 1453 container_of(work, struct fec_enet_private, tx_timeout_work); 1454 struct net_device *ndev = fep->netdev; 1455 1456 rtnl_lock(); 1457 if (netif_device_present(ndev) || netif_running(ndev)) { 1458 napi_disable(&fep->napi); 1459 netif_tx_lock_bh(ndev); 1460 fec_restart(ndev); 1461 netif_tx_wake_all_queues(ndev); 1462 netif_tx_unlock_bh(ndev); 1463 napi_enable(&fep->napi); 1464 } 1465 rtnl_unlock(); 1466 } 1467 1468 static void 1469 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1470 struct skb_shared_hwtstamps *hwtstamps) 1471 { 1472 unsigned long flags; 1473 u64 ns; 1474 1475 spin_lock_irqsave(&fep->tmreg_lock, flags); 1476 ns = timecounter_cyc2time(&fep->tc, ts); 1477 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1478 1479 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1480 hwtstamps->hwtstamp = ns_to_ktime(ns); 1481 } 1482 1483 static void 1484 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id, int budget) 1485 { 1486 struct fec_enet_private *fep; 1487 struct xdp_frame *xdpf; 1488 struct bufdesc *bdp; 1489 unsigned short status; 1490 struct sk_buff *skb; 1491 struct fec_enet_priv_tx_q *txq; 1492 struct netdev_queue *nq; 1493 int index = 0; 1494 int entries_free; 1495 struct page *page; 1496 int frame_len; 1497 1498 fep = netdev_priv(ndev); 1499 1500 txq = fep->tx_queue[queue_id]; 1501 /* get next bdp of dirty_tx */ 1502 nq = netdev_get_tx_queue(ndev, queue_id); 1503 bdp = txq->dirty_tx; 1504 1505 /* get next bdp of dirty_tx */ 1506 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1507 1508 while (bdp != READ_ONCE(txq->bd.cur)) { 1509 /* Order the load of bd.cur and cbd_sc */ 1510 rmb(); 1511 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1512 if (status & BD_ENET_TX_READY) 1513 break; 1514 1515 index = fec_enet_get_bd_index(bdp, &txq->bd); 1516 1517 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1518 skb = txq->tx_buf[index].buf_p; 1519 if (bdp->cbd_bufaddr && 1520 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1521 dma_unmap_single(&fep->pdev->dev, 1522 fec32_to_cpu(bdp->cbd_bufaddr), 1523 fec16_to_cpu(bdp->cbd_datlen), 1524 DMA_TO_DEVICE); 1525 bdp->cbd_bufaddr = cpu_to_fec32(0); 1526 if (!skb) 1527 goto tx_buf_done; 1528 } else { 1529 /* Tx processing cannot call any XDP (or page pool) APIs if 1530 * the "budget" is 0. Because NAPI is called with budget of 1531 * 0 (such as netpoll) indicates we may be in an IRQ context, 1532 * however, we can't use the page pool from IRQ context. 1533 */ 1534 if (unlikely(!budget)) 1535 break; 1536 1537 if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1538 xdpf = txq->tx_buf[index].buf_p; 1539 if (bdp->cbd_bufaddr) 1540 dma_unmap_single(&fep->pdev->dev, 1541 fec32_to_cpu(bdp->cbd_bufaddr), 1542 fec16_to_cpu(bdp->cbd_datlen), 1543 DMA_TO_DEVICE); 1544 } else { 1545 page = txq->tx_buf[index].buf_p; 1546 } 1547 1548 bdp->cbd_bufaddr = cpu_to_fec32(0); 1549 if (unlikely(!txq->tx_buf[index].buf_p)) { 1550 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1551 goto tx_buf_done; 1552 } 1553 1554 frame_len = fec16_to_cpu(bdp->cbd_datlen); 1555 } 1556 1557 /* Check for errors. */ 1558 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1559 BD_ENET_TX_RL | BD_ENET_TX_UN | 1560 BD_ENET_TX_CSL)) { 1561 ndev->stats.tx_errors++; 1562 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1563 ndev->stats.tx_heartbeat_errors++; 1564 if (status & BD_ENET_TX_LC) /* Late collision */ 1565 ndev->stats.tx_window_errors++; 1566 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1567 ndev->stats.tx_aborted_errors++; 1568 if (status & BD_ENET_TX_UN) /* Underrun */ 1569 ndev->stats.tx_fifo_errors++; 1570 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1571 ndev->stats.tx_carrier_errors++; 1572 } else { 1573 ndev->stats.tx_packets++; 1574 1575 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) 1576 ndev->stats.tx_bytes += skb->len; 1577 else 1578 ndev->stats.tx_bytes += frame_len; 1579 } 1580 1581 /* Deferred means some collisions occurred during transmit, 1582 * but we eventually sent the packet OK. 1583 */ 1584 if (status & BD_ENET_TX_DEF) 1585 ndev->stats.collisions++; 1586 1587 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1588 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1589 * are to time stamp the packet, so we still need to check time 1590 * stamping enabled flag. 1591 */ 1592 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1593 fep->hwts_tx_en) && fep->bufdesc_ex) { 1594 struct skb_shared_hwtstamps shhwtstamps; 1595 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1596 1597 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1598 skb_tstamp_tx(skb, &shhwtstamps); 1599 } 1600 1601 /* Free the sk buffer associated with this last transmit */ 1602 napi_consume_skb(skb, budget); 1603 } else if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1604 xdp_return_frame_rx_napi(xdpf); 1605 } else { /* recycle pages of XDP_TX frames */ 1606 /* The dma_sync_size = 0 as XDP_TX has already synced DMA for_device */ 1607 page_pool_put_page(pp_page_to_nmdesc(page)->pp, page, 1608 0, true); 1609 } 1610 1611 txq->tx_buf[index].buf_p = NULL; 1612 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1613 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1614 1615 tx_buf_done: 1616 /* Make sure the update to bdp and tx_buf are performed 1617 * before dirty_tx 1618 */ 1619 wmb(); 1620 txq->dirty_tx = bdp; 1621 1622 /* Update pointer to next buffer descriptor to be transmitted */ 1623 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1624 1625 /* Since we have freed up a buffer, the ring is no longer full 1626 */ 1627 if (netif_tx_queue_stopped(nq)) { 1628 entries_free = fec_enet_get_free_txdesc_num(txq); 1629 if (entries_free >= txq->tx_wake_threshold) 1630 netif_tx_wake_queue(nq); 1631 } 1632 } 1633 1634 /* ERR006358: Keep the transmitter going */ 1635 if (bdp != txq->bd.cur && 1636 readl(txq->bd.reg_desc_active) == 0) 1637 writel(0, txq->bd.reg_desc_active); 1638 } 1639 1640 static void fec_enet_tx(struct net_device *ndev, int budget) 1641 { 1642 struct fec_enet_private *fep = netdev_priv(ndev); 1643 int i; 1644 1645 /* Make sure that AVB queues are processed first. */ 1646 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1647 fec_enet_tx_queue(ndev, i, budget); 1648 } 1649 1650 static int fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq, 1651 struct bufdesc *bdp, int index) 1652 { 1653 struct page *new_page; 1654 dma_addr_t phys_addr; 1655 1656 new_page = page_pool_dev_alloc_pages(rxq->page_pool); 1657 if (unlikely(!new_page)) 1658 return -ENOMEM; 1659 1660 rxq->rx_skb_info[index].page = new_page; 1661 rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM; 1662 phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM; 1663 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 1664 1665 return 0; 1666 } 1667 1668 static u32 1669 fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog, 1670 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int cpu) 1671 { 1672 unsigned int sync, len = xdp->data_end - xdp->data; 1673 u32 ret = FEC_ENET_XDP_PASS; 1674 struct page *page; 1675 int err; 1676 u32 act; 1677 1678 act = bpf_prog_run_xdp(prog, xdp); 1679 1680 /* Due xdp_adjust_tail and xdp_adjust_head: DMA sync for_device cover 1681 * max len CPU touch 1682 */ 1683 sync = xdp->data_end - xdp->data; 1684 sync = max(sync, len); 1685 1686 switch (act) { 1687 case XDP_PASS: 1688 rxq->stats[RX_XDP_PASS]++; 1689 ret = FEC_ENET_XDP_PASS; 1690 break; 1691 1692 case XDP_REDIRECT: 1693 rxq->stats[RX_XDP_REDIRECT]++; 1694 err = xdp_do_redirect(fep->netdev, xdp, prog); 1695 if (unlikely(err)) 1696 goto xdp_err; 1697 1698 ret = FEC_ENET_XDP_REDIR; 1699 break; 1700 1701 case XDP_TX: 1702 rxq->stats[RX_XDP_TX]++; 1703 err = fec_enet_xdp_tx_xmit(fep, cpu, xdp, sync); 1704 if (unlikely(err)) { 1705 rxq->stats[RX_XDP_TX_ERRORS]++; 1706 goto xdp_err; 1707 } 1708 1709 ret = FEC_ENET_XDP_TX; 1710 break; 1711 1712 default: 1713 bpf_warn_invalid_xdp_action(fep->netdev, prog, act); 1714 fallthrough; 1715 1716 case XDP_ABORTED: 1717 fallthrough; /* handle aborts by dropping packet */ 1718 1719 case XDP_DROP: 1720 rxq->stats[RX_XDP_DROP]++; 1721 xdp_err: 1722 ret = FEC_ENET_XDP_CONSUMED; 1723 page = virt_to_head_page(xdp->data); 1724 page_pool_put_page(rxq->page_pool, page, sync, true); 1725 if (act != XDP_DROP) 1726 trace_xdp_exception(fep->netdev, prog, act); 1727 break; 1728 } 1729 1730 return ret; 1731 } 1732 1733 static void fec_enet_rx_vlan(const struct net_device *ndev, struct sk_buff *skb) 1734 { 1735 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX) { 1736 const struct vlan_ethhdr *vlan_header = skb_vlan_eth_hdr(skb); 1737 const u16 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1738 1739 /* Push and remove the vlan tag */ 1740 1741 memmove(skb->data + VLAN_HLEN, skb->data, ETH_ALEN * 2); 1742 skb_pull(skb, VLAN_HLEN); 1743 __vlan_hwaccel_put_tag(skb, 1744 htons(ETH_P_8021Q), 1745 vlan_tag); 1746 } 1747 } 1748 1749 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1750 * When we update through the ring, if the next incoming buffer has 1751 * not been given to the system, we just set the empty indicator, 1752 * effectively tossing the packet. 1753 */ 1754 static int 1755 fec_enet_rx_queue(struct net_device *ndev, u16 queue_id, int budget) 1756 { 1757 struct fec_enet_private *fep = netdev_priv(ndev); 1758 struct fec_enet_priv_rx_q *rxq; 1759 struct bufdesc *bdp; 1760 unsigned short status; 1761 struct sk_buff *skb; 1762 ushort pkt_len; 1763 int pkt_received = 0; 1764 struct bufdesc_ex *ebdp = NULL; 1765 int index = 0; 1766 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1767 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 1768 u32 ret, xdp_result = FEC_ENET_XDP_PASS; 1769 u32 data_start = FEC_ENET_XDP_HEADROOM; 1770 int cpu = smp_processor_id(); 1771 struct xdp_buff xdp; 1772 struct page *page; 1773 __fec32 cbd_bufaddr; 1774 u32 sub_len = 4; 1775 1776 #if !defined(CONFIG_M5272) 1777 /*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of 1778 * FEC_RACC_SHIFT16 is set by default in the probe function. 1779 */ 1780 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1781 data_start += 2; 1782 sub_len += 2; 1783 } 1784 #endif 1785 1786 #if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA) 1787 /* 1788 * Hacky flush of all caches instead of using the DMA API for the TSO 1789 * headers. 1790 */ 1791 flush_cache_all(); 1792 #endif 1793 rxq = fep->rx_queue[queue_id]; 1794 1795 /* First, grab all of the stats for the incoming packet. 1796 * These get messed up if we get called due to a busy condition. 1797 */ 1798 bdp = rxq->bd.cur; 1799 xdp_init_buff(&xdp, PAGE_SIZE << fep->pagepool_order, &rxq->xdp_rxq); 1800 1801 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1802 1803 if (pkt_received >= budget) 1804 break; 1805 pkt_received++; 1806 1807 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT); 1808 1809 /* Check for errors. */ 1810 status ^= BD_ENET_RX_LAST; 1811 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1812 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1813 BD_ENET_RX_CL)) { 1814 ndev->stats.rx_errors++; 1815 if (status & BD_ENET_RX_OV) { 1816 /* FIFO overrun */ 1817 ndev->stats.rx_fifo_errors++; 1818 goto rx_processing_done; 1819 } 1820 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1821 | BD_ENET_RX_LAST)) { 1822 /* Frame too long or too short. */ 1823 ndev->stats.rx_length_errors++; 1824 if (status & BD_ENET_RX_LAST) 1825 netdev_err(ndev, "rcv is not +last\n"); 1826 } 1827 if (status & BD_ENET_RX_CR) /* CRC Error */ 1828 ndev->stats.rx_crc_errors++; 1829 /* Report late collisions as a frame error. */ 1830 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1831 ndev->stats.rx_frame_errors++; 1832 goto rx_processing_done; 1833 } 1834 1835 /* Process the incoming frame. */ 1836 ndev->stats.rx_packets++; 1837 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1838 ndev->stats.rx_bytes += pkt_len; 1839 1840 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1841 page = rxq->rx_skb_info[index].page; 1842 cbd_bufaddr = bdp->cbd_bufaddr; 1843 if (fec_enet_update_cbd(rxq, bdp, index)) { 1844 ndev->stats.rx_dropped++; 1845 goto rx_processing_done; 1846 } 1847 1848 dma_sync_single_for_cpu(&fep->pdev->dev, 1849 fec32_to_cpu(cbd_bufaddr), 1850 pkt_len, 1851 DMA_FROM_DEVICE); 1852 prefetch(page_address(page)); 1853 1854 if (xdp_prog) { 1855 xdp_buff_clear_frags_flag(&xdp); 1856 /* subtract 16bit shift and FCS */ 1857 xdp_prepare_buff(&xdp, page_address(page), 1858 data_start, pkt_len - sub_len, false); 1859 ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, cpu); 1860 xdp_result |= ret; 1861 if (ret != FEC_ENET_XDP_PASS) 1862 goto rx_processing_done; 1863 } 1864 1865 /* The packet length includes FCS, but we don't want to 1866 * include that when passing upstream as it messes up 1867 * bridging applications. 1868 */ 1869 skb = build_skb(page_address(page), 1870 PAGE_SIZE << fep->pagepool_order); 1871 if (unlikely(!skb)) { 1872 page_pool_recycle_direct(rxq->page_pool, page); 1873 ndev->stats.rx_dropped++; 1874 1875 netdev_err_once(ndev, "build_skb failed!\n"); 1876 goto rx_processing_done; 1877 } 1878 1879 skb_reserve(skb, data_start); 1880 skb_put(skb, pkt_len - sub_len); 1881 skb_mark_for_recycle(skb); 1882 1883 if (unlikely(need_swap)) { 1884 u8 *data; 1885 1886 data = page_address(page) + FEC_ENET_XDP_HEADROOM; 1887 swap_buffer(data, pkt_len); 1888 } 1889 1890 /* Extract the enhanced buffer descriptor */ 1891 ebdp = NULL; 1892 if (fep->bufdesc_ex) 1893 ebdp = (struct bufdesc_ex *)bdp; 1894 1895 /* If this is a VLAN packet remove the VLAN Tag */ 1896 if (fep->bufdesc_ex && 1897 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) 1898 fec_enet_rx_vlan(ndev, skb); 1899 1900 skb->protocol = eth_type_trans(skb, ndev); 1901 1902 /* Get receive timestamp from the skb */ 1903 if (fep->hwts_rx_en && fep->bufdesc_ex) 1904 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1905 skb_hwtstamps(skb)); 1906 1907 if (fep->bufdesc_ex && 1908 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1909 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1910 /* don't check it */ 1911 skb->ip_summed = CHECKSUM_UNNECESSARY; 1912 } else { 1913 skb_checksum_none_assert(skb); 1914 } 1915 } 1916 1917 skb_record_rx_queue(skb, queue_id); 1918 napi_gro_receive(&fep->napi, skb); 1919 1920 rx_processing_done: 1921 /* Clear the status flags for this buffer */ 1922 status &= ~BD_ENET_RX_STATS; 1923 1924 /* Mark the buffer empty */ 1925 status |= BD_ENET_RX_EMPTY; 1926 1927 if (fep->bufdesc_ex) { 1928 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1929 1930 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1931 ebdp->cbd_prot = 0; 1932 ebdp->cbd_bdu = 0; 1933 } 1934 /* Make sure the updates to rest of the descriptor are 1935 * performed before transferring ownership. 1936 */ 1937 wmb(); 1938 bdp->cbd_sc = cpu_to_fec16(status); 1939 1940 /* Update BD pointer to next entry */ 1941 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1942 1943 /* Doing this here will keep the FEC running while we process 1944 * incoming frames. On a heavily loaded network, we should be 1945 * able to keep up at the expense of system resources. 1946 */ 1947 writel(0, rxq->bd.reg_desc_active); 1948 } 1949 rxq->bd.cur = bdp; 1950 1951 if (xdp_result & FEC_ENET_XDP_REDIR) 1952 xdp_do_flush(); 1953 1954 return pkt_received; 1955 } 1956 1957 static int fec_enet_rx(struct net_device *ndev, int budget) 1958 { 1959 struct fec_enet_private *fep = netdev_priv(ndev); 1960 int i, done = 0; 1961 1962 /* Make sure that AVB queues are processed first. */ 1963 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1964 done += fec_enet_rx_queue(ndev, i, budget - done); 1965 1966 return done; 1967 } 1968 1969 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1970 { 1971 uint int_events; 1972 1973 int_events = readl(fep->hwp + FEC_IEVENT); 1974 1975 /* Don't clear MDIO events, we poll for those */ 1976 int_events &= ~FEC_ENET_MII; 1977 1978 writel(int_events, fep->hwp + FEC_IEVENT); 1979 1980 return int_events != 0; 1981 } 1982 1983 static irqreturn_t 1984 fec_enet_interrupt(int irq, void *dev_id) 1985 { 1986 struct net_device *ndev = dev_id; 1987 struct fec_enet_private *fep = netdev_priv(ndev); 1988 irqreturn_t ret = IRQ_NONE; 1989 1990 if (fec_enet_collect_events(fep) && fep->link) { 1991 ret = IRQ_HANDLED; 1992 1993 if (napi_schedule_prep(&fep->napi)) { 1994 /* Disable interrupts */ 1995 writel(0, fep->hwp + FEC_IMASK); 1996 __napi_schedule(&fep->napi); 1997 } 1998 } 1999 2000 return ret; 2001 } 2002 2003 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 2004 { 2005 struct net_device *ndev = napi->dev; 2006 struct fec_enet_private *fep = netdev_priv(ndev); 2007 int done = 0; 2008 2009 do { 2010 done += fec_enet_rx(ndev, budget - done); 2011 fec_enet_tx(ndev, budget); 2012 } while ((done < budget) && fec_enet_collect_events(fep)); 2013 2014 if (done < budget) { 2015 napi_complete_done(napi, done); 2016 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 2017 } 2018 2019 return done; 2020 } 2021 2022 /* ------------------------------------------------------------------------- */ 2023 static int fec_get_mac(struct net_device *ndev) 2024 { 2025 struct fec_enet_private *fep = netdev_priv(ndev); 2026 unsigned char *iap, tmpaddr[ETH_ALEN]; 2027 int ret; 2028 2029 /* 2030 * try to get mac address in following order: 2031 * 2032 * 1) module parameter via kernel command line in form 2033 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 2034 */ 2035 iap = macaddr; 2036 2037 /* 2038 * 2) from device tree data 2039 */ 2040 if (!is_valid_ether_addr(iap)) { 2041 struct device_node *np = fep->pdev->dev.of_node; 2042 if (np) { 2043 ret = of_get_mac_address(np, tmpaddr); 2044 if (!ret) 2045 iap = tmpaddr; 2046 else if (ret == -EPROBE_DEFER) 2047 return ret; 2048 } 2049 } 2050 2051 /* 2052 * 3) from flash or fuse (via platform data) 2053 */ 2054 if (!is_valid_ether_addr(iap)) { 2055 #ifdef CONFIG_M5272 2056 if (FEC_FLASHMAC) 2057 iap = (unsigned char *)FEC_FLASHMAC; 2058 #else 2059 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 2060 2061 if (pdata) 2062 iap = (unsigned char *)&pdata->mac; 2063 #endif 2064 } 2065 2066 /* 2067 * 4) FEC mac registers set by bootloader 2068 */ 2069 if (!is_valid_ether_addr(iap)) { 2070 *((__be32 *) &tmpaddr[0]) = 2071 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 2072 *((__be16 *) &tmpaddr[4]) = 2073 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 2074 iap = &tmpaddr[0]; 2075 } 2076 2077 /* 2078 * 5) random mac address 2079 */ 2080 if (!is_valid_ether_addr(iap)) { 2081 /* Report it and use a random ethernet address instead */ 2082 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 2083 eth_hw_addr_random(ndev); 2084 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 2085 ndev->dev_addr); 2086 return 0; 2087 } 2088 2089 /* Adjust MAC if using macaddr */ 2090 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0); 2091 2092 return 0; 2093 } 2094 2095 /* ------------------------------------------------------------------------- */ 2096 2097 /* 2098 * Phy section 2099 */ 2100 2101 /* LPI Sleep Ts count base on tx clk (clk_ref). 2102 * The lpi sleep cnt value = X us / (cycle_ns). 2103 */ 2104 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) 2105 { 2106 struct fec_enet_private *fep = netdev_priv(ndev); 2107 2108 return us * (fep->clk_ref_rate / 1000) / 1000; 2109 } 2110 2111 static int fec_enet_eee_mode_set(struct net_device *ndev, u32 lpi_timer, 2112 bool enable) 2113 { 2114 struct fec_enet_private *fep = netdev_priv(ndev); 2115 unsigned int sleep_cycle, wake_cycle; 2116 2117 if (enable) { 2118 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, lpi_timer); 2119 wake_cycle = sleep_cycle; 2120 } else { 2121 sleep_cycle = 0; 2122 wake_cycle = 0; 2123 } 2124 2125 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); 2126 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); 2127 2128 return 0; 2129 } 2130 2131 static void fec_enet_adjust_link(struct net_device *ndev) 2132 { 2133 struct fec_enet_private *fep = netdev_priv(ndev); 2134 struct phy_device *phy_dev = ndev->phydev; 2135 int status_change = 0; 2136 2137 /* 2138 * If the netdev is down, or is going down, we're not interested 2139 * in link state events, so just mark our idea of the link as down 2140 * and ignore the event. 2141 */ 2142 if (!netif_running(ndev) || !netif_device_present(ndev)) { 2143 fep->link = 0; 2144 } else if (phy_dev->link) { 2145 if (!fep->link) { 2146 fep->link = phy_dev->link; 2147 status_change = 1; 2148 } 2149 2150 if (fep->full_duplex != phy_dev->duplex) { 2151 fep->full_duplex = phy_dev->duplex; 2152 status_change = 1; 2153 } 2154 2155 if (phy_dev->speed != fep->speed) { 2156 fep->speed = phy_dev->speed; 2157 status_change = 1; 2158 } 2159 2160 /* if any of the above changed restart the FEC */ 2161 if (status_change) { 2162 netif_stop_queue(ndev); 2163 napi_disable(&fep->napi); 2164 netif_tx_lock_bh(ndev); 2165 fec_restart(ndev); 2166 netif_tx_wake_all_queues(ndev); 2167 netif_tx_unlock_bh(ndev); 2168 napi_enable(&fep->napi); 2169 } 2170 if (fep->quirks & FEC_QUIRK_HAS_EEE) 2171 fec_enet_eee_mode_set(ndev, 2172 phy_dev->eee_cfg.tx_lpi_timer, 2173 phy_dev->enable_tx_lpi); 2174 } else { 2175 if (fep->link) { 2176 netif_stop_queue(ndev); 2177 napi_disable(&fep->napi); 2178 netif_tx_lock_bh(ndev); 2179 fec_stop(ndev); 2180 netif_tx_unlock_bh(ndev); 2181 napi_enable(&fep->napi); 2182 fep->link = phy_dev->link; 2183 status_change = 1; 2184 } 2185 } 2186 2187 if (status_change) 2188 phy_print_status(phy_dev); 2189 } 2190 2191 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 2192 { 2193 uint ievent; 2194 int ret; 2195 2196 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 2197 ievent & FEC_ENET_MII, 2, 30000); 2198 2199 if (!ret) 2200 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2201 2202 return ret; 2203 } 2204 2205 static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) 2206 { 2207 struct fec_enet_private *fep = bus->priv; 2208 struct device *dev = &fep->pdev->dev; 2209 int ret = 0, frame_start, frame_addr, frame_op; 2210 2211 ret = pm_runtime_resume_and_get(dev); 2212 if (ret < 0) 2213 return ret; 2214 2215 /* C22 read */ 2216 frame_op = FEC_MMFR_OP_READ; 2217 frame_start = FEC_MMFR_ST; 2218 frame_addr = regnum; 2219 2220 /* start a read op */ 2221 writel(frame_start | frame_op | 2222 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2223 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2224 2225 /* wait for end of transfer */ 2226 ret = fec_enet_mdio_wait(fep); 2227 if (ret) { 2228 netdev_err(fep->netdev, "MDIO read timeout\n"); 2229 goto out; 2230 } 2231 2232 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2233 2234 out: 2235 pm_runtime_put_autosuspend(dev); 2236 2237 return ret; 2238 } 2239 2240 static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id, 2241 int devad, int regnum) 2242 { 2243 struct fec_enet_private *fep = bus->priv; 2244 struct device *dev = &fep->pdev->dev; 2245 int ret = 0, frame_start, frame_op; 2246 2247 ret = pm_runtime_resume_and_get(dev); 2248 if (ret < 0) 2249 return ret; 2250 2251 frame_start = FEC_MMFR_ST_C45; 2252 2253 /* write address */ 2254 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2255 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2256 FEC_MMFR_TA | (regnum & 0xFFFF), 2257 fep->hwp + FEC_MII_DATA); 2258 2259 /* wait for end of transfer */ 2260 ret = fec_enet_mdio_wait(fep); 2261 if (ret) { 2262 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2263 goto out; 2264 } 2265 2266 frame_op = FEC_MMFR_OP_READ_C45; 2267 2268 /* start a read op */ 2269 writel(frame_start | frame_op | 2270 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2271 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2272 2273 /* wait for end of transfer */ 2274 ret = fec_enet_mdio_wait(fep); 2275 if (ret) { 2276 netdev_err(fep->netdev, "MDIO read timeout\n"); 2277 goto out; 2278 } 2279 2280 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2281 2282 out: 2283 pm_runtime_put_autosuspend(dev); 2284 2285 return ret; 2286 } 2287 2288 static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, 2289 u16 value) 2290 { 2291 struct fec_enet_private *fep = bus->priv; 2292 struct device *dev = &fep->pdev->dev; 2293 int ret, frame_start, frame_addr; 2294 2295 ret = pm_runtime_resume_and_get(dev); 2296 if (ret < 0) 2297 return ret; 2298 2299 /* C22 write */ 2300 frame_start = FEC_MMFR_ST; 2301 frame_addr = regnum; 2302 2303 /* start a write op */ 2304 writel(frame_start | FEC_MMFR_OP_WRITE | 2305 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2306 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2307 fep->hwp + FEC_MII_DATA); 2308 2309 /* wait for end of transfer */ 2310 ret = fec_enet_mdio_wait(fep); 2311 if (ret) 2312 netdev_err(fep->netdev, "MDIO write timeout\n"); 2313 2314 pm_runtime_put_autosuspend(dev); 2315 2316 return ret; 2317 } 2318 2319 static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id, 2320 int devad, int regnum, u16 value) 2321 { 2322 struct fec_enet_private *fep = bus->priv; 2323 struct device *dev = &fep->pdev->dev; 2324 int ret, frame_start; 2325 2326 ret = pm_runtime_resume_and_get(dev); 2327 if (ret < 0) 2328 return ret; 2329 2330 frame_start = FEC_MMFR_ST_C45; 2331 2332 /* write address */ 2333 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2334 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2335 FEC_MMFR_TA | (regnum & 0xFFFF), 2336 fep->hwp + FEC_MII_DATA); 2337 2338 /* wait for end of transfer */ 2339 ret = fec_enet_mdio_wait(fep); 2340 if (ret) { 2341 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2342 goto out; 2343 } 2344 2345 /* start a write op */ 2346 writel(frame_start | FEC_MMFR_OP_WRITE | 2347 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2348 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2349 fep->hwp + FEC_MII_DATA); 2350 2351 /* wait for end of transfer */ 2352 ret = fec_enet_mdio_wait(fep); 2353 if (ret) 2354 netdev_err(fep->netdev, "MDIO write timeout\n"); 2355 2356 out: 2357 pm_runtime_put_autosuspend(dev); 2358 2359 return ret; 2360 } 2361 2362 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 2363 { 2364 struct fec_enet_private *fep = netdev_priv(ndev); 2365 struct phy_device *phy_dev = ndev->phydev; 2366 2367 if (phy_dev) { 2368 phy_reset_after_clk_enable(phy_dev); 2369 } else if (fep->phy_node) { 2370 /* 2371 * If the PHY still is not bound to the MAC, but there is 2372 * OF PHY node and a matching PHY device instance already, 2373 * use the OF PHY node to obtain the PHY device instance, 2374 * and then use that PHY device instance when triggering 2375 * the PHY reset. 2376 */ 2377 phy_dev = of_phy_find_device(fep->phy_node); 2378 phy_reset_after_clk_enable(phy_dev); 2379 if (phy_dev) 2380 put_device(&phy_dev->mdio.dev); 2381 } 2382 } 2383 2384 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 2385 { 2386 struct fec_enet_private *fep = netdev_priv(ndev); 2387 int ret; 2388 2389 if (enable) { 2390 ret = clk_prepare_enable(fep->clk_enet_out); 2391 if (ret) 2392 return ret; 2393 2394 if (fep->clk_ptp) { 2395 mutex_lock(&fep->ptp_clk_mutex); 2396 ret = clk_prepare_enable(fep->clk_ptp); 2397 if (ret) { 2398 mutex_unlock(&fep->ptp_clk_mutex); 2399 goto failed_clk_ptp; 2400 } else { 2401 fep->ptp_clk_on = true; 2402 } 2403 mutex_unlock(&fep->ptp_clk_mutex); 2404 } 2405 2406 ret = clk_prepare_enable(fep->clk_ref); 2407 if (ret) 2408 goto failed_clk_ref; 2409 2410 ret = clk_prepare_enable(fep->clk_2x_txclk); 2411 if (ret) 2412 goto failed_clk_2x_txclk; 2413 2414 fec_enet_phy_reset_after_clk_enable(ndev); 2415 } else { 2416 clk_disable_unprepare(fep->clk_enet_out); 2417 if (fep->clk_ptp) { 2418 mutex_lock(&fep->ptp_clk_mutex); 2419 clk_disable_unprepare(fep->clk_ptp); 2420 fep->ptp_clk_on = false; 2421 mutex_unlock(&fep->ptp_clk_mutex); 2422 } 2423 clk_disable_unprepare(fep->clk_ref); 2424 clk_disable_unprepare(fep->clk_2x_txclk); 2425 } 2426 2427 return 0; 2428 2429 failed_clk_2x_txclk: 2430 if (fep->clk_ref) 2431 clk_disable_unprepare(fep->clk_ref); 2432 failed_clk_ref: 2433 if (fep->clk_ptp) { 2434 mutex_lock(&fep->ptp_clk_mutex); 2435 clk_disable_unprepare(fep->clk_ptp); 2436 fep->ptp_clk_on = false; 2437 mutex_unlock(&fep->ptp_clk_mutex); 2438 } 2439 failed_clk_ptp: 2440 clk_disable_unprepare(fep->clk_enet_out); 2441 2442 return ret; 2443 } 2444 2445 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep, 2446 struct device_node *np) 2447 { 2448 u32 rgmii_tx_delay, rgmii_rx_delay; 2449 2450 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ 2451 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { 2452 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) { 2453 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); 2454 return -EINVAL; 2455 } else if (rgmii_tx_delay == 2000) { 2456 fep->rgmii_txc_dly = true; 2457 } 2458 } 2459 2460 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */ 2461 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { 2462 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) { 2463 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); 2464 return -EINVAL; 2465 } else if (rgmii_rx_delay == 2000) { 2466 fep->rgmii_rxc_dly = true; 2467 } 2468 } 2469 2470 return 0; 2471 } 2472 2473 static int fec_enet_mii_probe(struct net_device *ndev) 2474 { 2475 struct fec_enet_private *fep = netdev_priv(ndev); 2476 struct phy_device *phy_dev; 2477 int ret; 2478 2479 if (fep->phy_node) { 2480 phy_dev = of_phy_connect(ndev, fep->phy_node, 2481 &fec_enet_adjust_link, 0, 2482 fep->phy_interface); 2483 if (!phy_dev) { 2484 netdev_err(ndev, "Unable to connect to phy\n"); 2485 return -ENODEV; 2486 } 2487 } else { 2488 /* check for attached phy */ 2489 phy_dev = phy_find_first(fep->mii_bus); 2490 if (fep->dev_id && phy_dev) 2491 phy_dev = phy_find_next(fep->mii_bus, phy_dev); 2492 2493 if (!phy_dev) { 2494 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2495 phy_dev = fixed_phy_register_100fd(); 2496 if (IS_ERR(phy_dev)) { 2497 netdev_err(ndev, "could not register fixed PHY\n"); 2498 return PTR_ERR(phy_dev); 2499 } 2500 } 2501 2502 ret = phy_connect_direct(ndev, phy_dev, &fec_enet_adjust_link, 2503 fep->phy_interface); 2504 if (ret) { 2505 if (phy_is_pseudo_fixed_link(phy_dev)) 2506 fixed_phy_unregister(phy_dev); 2507 netdev_err(ndev, "could not attach to PHY\n"); 2508 return ret; 2509 } 2510 2511 } 2512 2513 /* mask with MAC supported features */ 2514 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2515 phy_set_max_speed(phy_dev, 1000); 2516 phy_remove_link_mode(phy_dev, 2517 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2518 #if !defined(CONFIG_M5272) 2519 phy_support_sym_pause(phy_dev); 2520 #endif 2521 } 2522 else 2523 phy_set_max_speed(phy_dev, 100); 2524 2525 if (fep->quirks & FEC_QUIRK_HAS_EEE) 2526 phy_support_eee(phy_dev); 2527 2528 fep->link = 0; 2529 fep->full_duplex = 0; 2530 2531 phy_attached_info(phy_dev); 2532 2533 return 0; 2534 } 2535 2536 static int fec_enet_mii_init(struct platform_device *pdev) 2537 { 2538 static struct mii_bus *fec0_mii_bus; 2539 struct net_device *ndev = platform_get_drvdata(pdev); 2540 struct fec_enet_private *fep = netdev_priv(ndev); 2541 bool suppress_preamble = false; 2542 struct phy_device *phydev; 2543 struct device_node *node; 2544 int err = -ENXIO; 2545 u32 mii_speed, holdtime; 2546 u32 bus_freq; 2547 2548 /* 2549 * The i.MX28 dual fec interfaces are not equal. 2550 * Here are the differences: 2551 * 2552 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2553 * - fec0 acts as the 1588 time master while fec1 is slave 2554 * - external phys can only be configured by fec0 2555 * 2556 * That is to say fec1 can not work independently. It only works 2557 * when fec0 is working. The reason behind this design is that the 2558 * second interface is added primarily for Switch mode. 2559 * 2560 * Because of the last point above, both phys are attached on fec0 2561 * mdio interface in board design, and need to be configured by 2562 * fec0 mii_bus. 2563 */ 2564 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2565 /* fec1 uses fec0 mii_bus */ 2566 if (mii_cnt && fec0_mii_bus) { 2567 fep->mii_bus = fec0_mii_bus; 2568 mii_cnt++; 2569 return 0; 2570 } 2571 return -ENOENT; 2572 } 2573 2574 bus_freq = 2500000; /* 2.5MHz by default */ 2575 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2576 if (node) { 2577 of_property_read_u32(node, "clock-frequency", &bus_freq); 2578 suppress_preamble = of_property_read_bool(node, 2579 "suppress-preamble"); 2580 } 2581 2582 /* 2583 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2584 * 2585 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2586 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2587 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2588 * document. 2589 */ 2590 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2591 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2592 mii_speed--; 2593 if (mii_speed > 63) { 2594 dev_err(&pdev->dev, 2595 "fec clock (%lu) too fast to get right mii speed\n", 2596 clk_get_rate(fep->clk_ipg)); 2597 err = -EINVAL; 2598 goto err_out; 2599 } 2600 2601 /* 2602 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2603 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2604 * versions are RAZ there, so just ignore the difference and write the 2605 * register always. 2606 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2607 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2608 * output. 2609 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2610 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2611 * holdtime cannot result in a value greater than 3. 2612 */ 2613 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2614 2615 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2616 2617 if (suppress_preamble) 2618 fep->phy_speed |= BIT(7); 2619 2620 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2621 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2622 * MII event generation condition: 2623 * - writing MSCR: 2624 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2625 * mscr_reg_data_in[7:0] != 0 2626 * - writing MMFR: 2627 * - mscr[7:0]_not_zero 2628 */ 2629 writel(0, fep->hwp + FEC_MII_DATA); 2630 } 2631 2632 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2633 2634 /* Clear any pending transaction complete indication */ 2635 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2636 2637 fep->mii_bus = mdiobus_alloc(); 2638 if (fep->mii_bus == NULL) { 2639 err = -ENOMEM; 2640 goto err_out; 2641 } 2642 2643 fep->mii_bus->name = "fec_enet_mii_bus"; 2644 fep->mii_bus->read = fec_enet_mdio_read_c22; 2645 fep->mii_bus->write = fec_enet_mdio_write_c22; 2646 if (fep->quirks & FEC_QUIRK_HAS_MDIO_C45) { 2647 fep->mii_bus->read_c45 = fec_enet_mdio_read_c45; 2648 fep->mii_bus->write_c45 = fec_enet_mdio_write_c45; 2649 } 2650 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2651 pdev->name, fep->dev_id + 1); 2652 fep->mii_bus->priv = fep; 2653 fep->mii_bus->parent = &pdev->dev; 2654 2655 err = of_mdiobus_register(fep->mii_bus, node); 2656 if (err) 2657 goto err_out_free_mdiobus; 2658 of_node_put(node); 2659 2660 /* find all the PHY devices on the bus and set mac_managed_pm to true */ 2661 mdiobus_for_each_phy(fep->mii_bus, phydev) 2662 phydev->mac_managed_pm = true; 2663 2664 mii_cnt++; 2665 2666 /* save fec0 mii_bus */ 2667 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2668 fec0_mii_bus = fep->mii_bus; 2669 2670 return 0; 2671 2672 err_out_free_mdiobus: 2673 mdiobus_free(fep->mii_bus); 2674 err_out: 2675 of_node_put(node); 2676 return err; 2677 } 2678 2679 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2680 { 2681 if (--mii_cnt == 0) { 2682 mdiobus_unregister(fep->mii_bus); 2683 mdiobus_free(fep->mii_bus); 2684 } 2685 } 2686 2687 static void fec_enet_get_drvinfo(struct net_device *ndev, 2688 struct ethtool_drvinfo *info) 2689 { 2690 struct fec_enet_private *fep = netdev_priv(ndev); 2691 2692 strscpy(info->driver, fep->pdev->dev.driver->name, 2693 sizeof(info->driver)); 2694 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2695 } 2696 2697 static int fec_enet_get_regs_len(struct net_device *ndev) 2698 { 2699 struct fec_enet_private *fep = netdev_priv(ndev); 2700 struct resource *r; 2701 int s = 0; 2702 2703 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2704 if (r) 2705 s = resource_size(r); 2706 2707 return s; 2708 } 2709 2710 /* List of registers that can be safety be read to dump them with ethtool */ 2711 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2712 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2713 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2714 static __u32 fec_enet_register_version = 2; 2715 static u32 fec_enet_register_offset[] = { 2716 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2717 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2718 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2719 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2720 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2721 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2722 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2723 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2724 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2725 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2726 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2727 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2728 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2729 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2730 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2731 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2732 RMON_T_P_GTE2048, RMON_T_OCTETS, 2733 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2734 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2735 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2736 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2737 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2738 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2739 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2740 RMON_R_P_GTE2048, RMON_R_OCTETS, 2741 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2742 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2743 }; 2744 /* for i.MX6ul */ 2745 static u32 fec_enet_register_offset_6ul[] = { 2746 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2747 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2748 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0, 2749 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, 2750 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0, 2751 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2752 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, 2753 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2754 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2755 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2756 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2757 RMON_T_P_GTE2048, RMON_T_OCTETS, 2758 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2759 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2760 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2761 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2762 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2763 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2764 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2765 RMON_R_P_GTE2048, RMON_R_OCTETS, 2766 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2767 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2768 }; 2769 #else 2770 static __u32 fec_enet_register_version = 1; 2771 static u32 fec_enet_register_offset[] = { 2772 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2773 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2774 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2775 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2776 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2777 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2778 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2779 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2780 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2781 }; 2782 #endif 2783 2784 static void fec_enet_get_regs(struct net_device *ndev, 2785 struct ethtool_regs *regs, void *regbuf) 2786 { 2787 struct fec_enet_private *fep = netdev_priv(ndev); 2788 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2789 struct device *dev = &fep->pdev->dev; 2790 u32 *buf = (u32 *)regbuf; 2791 u32 i, off; 2792 int ret; 2793 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2794 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2795 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2796 u32 *reg_list; 2797 u32 reg_cnt; 2798 2799 if (!of_machine_is_compatible("fsl,imx6ul")) { 2800 reg_list = fec_enet_register_offset; 2801 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2802 } else { 2803 reg_list = fec_enet_register_offset_6ul; 2804 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul); 2805 } 2806 #else 2807 /* coldfire */ 2808 static u32 *reg_list = fec_enet_register_offset; 2809 static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2810 #endif 2811 ret = pm_runtime_resume_and_get(dev); 2812 if (ret < 0) 2813 return; 2814 2815 regs->version = fec_enet_register_version; 2816 2817 memset(buf, 0, regs->len); 2818 2819 for (i = 0; i < reg_cnt; i++) { 2820 off = reg_list[i]; 2821 2822 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2823 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2824 continue; 2825 2826 off >>= 2; 2827 buf[off] = readl(&theregs[off]); 2828 } 2829 2830 pm_runtime_put_autosuspend(dev); 2831 } 2832 2833 static int fec_enet_get_ts_info(struct net_device *ndev, 2834 struct kernel_ethtool_ts_info *info) 2835 { 2836 struct fec_enet_private *fep = netdev_priv(ndev); 2837 2838 if (fep->bufdesc_ex) { 2839 2840 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2841 SOF_TIMESTAMPING_TX_HARDWARE | 2842 SOF_TIMESTAMPING_RX_HARDWARE | 2843 SOF_TIMESTAMPING_RAW_HARDWARE; 2844 if (fep->ptp_clock) 2845 info->phc_index = ptp_clock_index(fep->ptp_clock); 2846 2847 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2848 (1 << HWTSTAMP_TX_ON); 2849 2850 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2851 (1 << HWTSTAMP_FILTER_ALL); 2852 return 0; 2853 } else { 2854 return ethtool_op_get_ts_info(ndev, info); 2855 } 2856 } 2857 2858 #if !defined(CONFIG_M5272) 2859 2860 static void fec_enet_get_pauseparam(struct net_device *ndev, 2861 struct ethtool_pauseparam *pause) 2862 { 2863 struct fec_enet_private *fep = netdev_priv(ndev); 2864 2865 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2866 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2867 pause->rx_pause = pause->tx_pause; 2868 } 2869 2870 static int fec_enet_set_pauseparam(struct net_device *ndev, 2871 struct ethtool_pauseparam *pause) 2872 { 2873 struct fec_enet_private *fep = netdev_priv(ndev); 2874 2875 if (!ndev->phydev) 2876 return -ENODEV; 2877 2878 if (pause->tx_pause != pause->rx_pause) { 2879 netdev_info(ndev, 2880 "hardware only support enable/disable both tx and rx"); 2881 return -EINVAL; 2882 } 2883 2884 fep->pause_flag = 0; 2885 2886 /* tx pause must be same as rx pause */ 2887 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2888 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2889 2890 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2891 pause->autoneg); 2892 2893 if (pause->autoneg) { 2894 if (netif_running(ndev)) 2895 fec_stop(ndev); 2896 phy_start_aneg(ndev->phydev); 2897 } 2898 if (netif_running(ndev)) { 2899 napi_disable(&fep->napi); 2900 netif_tx_lock_bh(ndev); 2901 fec_restart(ndev); 2902 netif_tx_wake_all_queues(ndev); 2903 netif_tx_unlock_bh(ndev); 2904 napi_enable(&fep->napi); 2905 } 2906 2907 return 0; 2908 } 2909 2910 static const struct fec_stat { 2911 char name[ETH_GSTRING_LEN]; 2912 u16 offset; 2913 } fec_stats[] = { 2914 /* RMON TX */ 2915 { "tx_dropped", RMON_T_DROP }, 2916 { "tx_packets", RMON_T_PACKETS }, 2917 { "tx_broadcast", RMON_T_BC_PKT }, 2918 { "tx_multicast", RMON_T_MC_PKT }, 2919 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2920 { "tx_undersize", RMON_T_UNDERSIZE }, 2921 { "tx_oversize", RMON_T_OVERSIZE }, 2922 { "tx_fragment", RMON_T_FRAG }, 2923 { "tx_jabber", RMON_T_JAB }, 2924 { "tx_collision", RMON_T_COL }, 2925 { "tx_64byte", RMON_T_P64 }, 2926 { "tx_65to127byte", RMON_T_P65TO127 }, 2927 { "tx_128to255byte", RMON_T_P128TO255 }, 2928 { "tx_256to511byte", RMON_T_P256TO511 }, 2929 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2930 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2931 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2932 { "tx_octets", RMON_T_OCTETS }, 2933 2934 /* IEEE TX */ 2935 { "IEEE_tx_drop", IEEE_T_DROP }, 2936 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2937 { "IEEE_tx_1col", IEEE_T_1COL }, 2938 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2939 { "IEEE_tx_def", IEEE_T_DEF }, 2940 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2941 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2942 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2943 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2944 { "IEEE_tx_sqe", IEEE_T_SQE }, 2945 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2946 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2947 2948 /* RMON RX */ 2949 { "rx_packets", RMON_R_PACKETS }, 2950 { "rx_broadcast", RMON_R_BC_PKT }, 2951 { "rx_multicast", RMON_R_MC_PKT }, 2952 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2953 { "rx_undersize", RMON_R_UNDERSIZE }, 2954 { "rx_oversize", RMON_R_OVERSIZE }, 2955 { "rx_fragment", RMON_R_FRAG }, 2956 { "rx_jabber", RMON_R_JAB }, 2957 { "rx_64byte", RMON_R_P64 }, 2958 { "rx_65to127byte", RMON_R_P65TO127 }, 2959 { "rx_128to255byte", RMON_R_P128TO255 }, 2960 { "rx_256to511byte", RMON_R_P256TO511 }, 2961 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2962 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2963 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2964 { "rx_octets", RMON_R_OCTETS }, 2965 2966 /* IEEE RX */ 2967 { "IEEE_rx_drop", IEEE_R_DROP }, 2968 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2969 { "IEEE_rx_crc", IEEE_R_CRC }, 2970 { "IEEE_rx_align", IEEE_R_ALIGN }, 2971 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2972 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2973 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2974 }; 2975 2976 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2977 2978 static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = { 2979 "rx_xdp_redirect", /* RX_XDP_REDIRECT = 0, */ 2980 "rx_xdp_pass", /* RX_XDP_PASS, */ 2981 "rx_xdp_drop", /* RX_XDP_DROP, */ 2982 "rx_xdp_tx", /* RX_XDP_TX, */ 2983 "rx_xdp_tx_errors", /* RX_XDP_TX_ERRORS, */ 2984 "tx_xdp_xmit", /* TX_XDP_XMIT, */ 2985 "tx_xdp_xmit_errors", /* TX_XDP_XMIT_ERRORS, */ 2986 }; 2987 2988 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2989 { 2990 struct fec_enet_private *fep = netdev_priv(dev); 2991 int i; 2992 2993 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2994 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2995 } 2996 2997 static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data) 2998 { 2999 u64 xdp_stats[XDP_STATS_TOTAL] = { 0 }; 3000 struct fec_enet_priv_rx_q *rxq; 3001 int i, j; 3002 3003 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 3004 rxq = fep->rx_queue[i]; 3005 3006 for (j = 0; j < XDP_STATS_TOTAL; j++) 3007 xdp_stats[j] += rxq->stats[j]; 3008 } 3009 3010 memcpy(data, xdp_stats, sizeof(xdp_stats)); 3011 } 3012 3013 static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data) 3014 { 3015 #ifdef CONFIG_PAGE_POOL_STATS 3016 struct page_pool_stats stats = {}; 3017 struct fec_enet_priv_rx_q *rxq; 3018 int i; 3019 3020 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 3021 rxq = fep->rx_queue[i]; 3022 3023 if (!rxq->page_pool) 3024 continue; 3025 3026 page_pool_get_stats(rxq->page_pool, &stats); 3027 } 3028 3029 page_pool_ethtool_stats_get(data, &stats); 3030 #endif 3031 } 3032 3033 static void fec_enet_get_ethtool_stats(struct net_device *dev, 3034 struct ethtool_stats *stats, u64 *data) 3035 { 3036 struct fec_enet_private *fep = netdev_priv(dev); 3037 3038 if (netif_running(dev)) 3039 fec_enet_update_ethtool_stats(dev); 3040 3041 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 3042 data += FEC_STATS_SIZE / sizeof(u64); 3043 3044 fec_enet_get_xdp_stats(fep, data); 3045 data += XDP_STATS_TOTAL; 3046 3047 fec_enet_page_pool_stats(fep, data); 3048 } 3049 3050 static void fec_enet_get_strings(struct net_device *netdev, 3051 u32 stringset, u8 *data) 3052 { 3053 int i; 3054 switch (stringset) { 3055 case ETH_SS_STATS: 3056 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) { 3057 ethtool_puts(&data, fec_stats[i].name); 3058 } 3059 for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) { 3060 ethtool_puts(&data, fec_xdp_stat_strs[i]); 3061 } 3062 page_pool_ethtool_stats_get_strings(data); 3063 3064 break; 3065 case ETH_SS_TEST: 3066 net_selftest_get_strings(data); 3067 break; 3068 } 3069 } 3070 3071 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 3072 { 3073 int count; 3074 3075 switch (sset) { 3076 case ETH_SS_STATS: 3077 count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL; 3078 count += page_pool_ethtool_stats_get_count(); 3079 return count; 3080 3081 case ETH_SS_TEST: 3082 return net_selftest_get_count(); 3083 default: 3084 return -EOPNOTSUPP; 3085 } 3086 } 3087 3088 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 3089 { 3090 struct fec_enet_private *fep = netdev_priv(dev); 3091 struct fec_enet_priv_rx_q *rxq; 3092 int i, j; 3093 3094 /* Disable MIB statistics counters */ 3095 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 3096 3097 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 3098 writel(0, fep->hwp + fec_stats[i].offset); 3099 3100 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 3101 rxq = fep->rx_queue[i]; 3102 for (j = 0; j < XDP_STATS_TOTAL; j++) 3103 rxq->stats[j] = 0; 3104 } 3105 3106 /* Don't disable MIB statistics counters */ 3107 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 3108 } 3109 3110 #else /* !defined(CONFIG_M5272) */ 3111 #define FEC_STATS_SIZE 0 3112 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 3113 { 3114 } 3115 3116 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 3117 { 3118 } 3119 #endif /* !defined(CONFIG_M5272) */ 3120 3121 /* ITR clock source is enet system clock (clk_ahb). 3122 * TCTT unit is cycle_ns * 64 cycle 3123 * So, the ICTT value = X us / (cycle_ns * 64) 3124 */ 3125 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 3126 { 3127 struct fec_enet_private *fep = netdev_priv(ndev); 3128 3129 return us * (fep->itr_clk_rate / 64000) / 1000; 3130 } 3131 3132 /* Set threshold for interrupt coalescing */ 3133 static void fec_enet_itr_coal_set(struct net_device *ndev) 3134 { 3135 struct fec_enet_private *fep = netdev_priv(ndev); 3136 u32 rx_itr = 0, tx_itr = 0; 3137 int rx_ictt, tx_ictt; 3138 3139 rx_ictt = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); 3140 tx_ictt = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); 3141 3142 if (rx_ictt > 0 && fep->rx_pkts_itr > 1) { 3143 /* Enable with enet system clock as Interrupt Coalescing timer Clock Source */ 3144 rx_itr = FEC_ITR_EN | FEC_ITR_CLK_SEL; 3145 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 3146 rx_itr |= FEC_ITR_ICTT(rx_ictt); 3147 } 3148 3149 if (tx_ictt > 0 && fep->tx_pkts_itr > 1) { 3150 /* Enable with enet system clock as Interrupt Coalescing timer Clock Source */ 3151 tx_itr = FEC_ITR_EN | FEC_ITR_CLK_SEL; 3152 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 3153 tx_itr |= FEC_ITR_ICTT(tx_ictt); 3154 } 3155 3156 writel(tx_itr, fep->hwp + FEC_TXIC0); 3157 writel(rx_itr, fep->hwp + FEC_RXIC0); 3158 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 3159 writel(tx_itr, fep->hwp + FEC_TXIC1); 3160 writel(rx_itr, fep->hwp + FEC_RXIC1); 3161 writel(tx_itr, fep->hwp + FEC_TXIC2); 3162 writel(rx_itr, fep->hwp + FEC_RXIC2); 3163 } 3164 } 3165 3166 static int fec_enet_get_coalesce(struct net_device *ndev, 3167 struct ethtool_coalesce *ec, 3168 struct kernel_ethtool_coalesce *kernel_coal, 3169 struct netlink_ext_ack *extack) 3170 { 3171 struct fec_enet_private *fep = netdev_priv(ndev); 3172 3173 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3174 return -EOPNOTSUPP; 3175 3176 ec->rx_coalesce_usecs = fep->rx_time_itr; 3177 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 3178 3179 ec->tx_coalesce_usecs = fep->tx_time_itr; 3180 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 3181 3182 return 0; 3183 } 3184 3185 static int fec_enet_set_coalesce(struct net_device *ndev, 3186 struct ethtool_coalesce *ec, 3187 struct kernel_ethtool_coalesce *kernel_coal, 3188 struct netlink_ext_ack *extack) 3189 { 3190 struct fec_enet_private *fep = netdev_priv(ndev); 3191 struct device *dev = &fep->pdev->dev; 3192 unsigned int cycle; 3193 3194 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3195 return -EOPNOTSUPP; 3196 3197 if (ec->rx_max_coalesced_frames > 255) { 3198 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 3199 return -EINVAL; 3200 } 3201 3202 if (ec->tx_max_coalesced_frames > 255) { 3203 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 3204 return -EINVAL; 3205 } 3206 3207 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 3208 if (cycle > 0xFFFF) { 3209 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 3210 return -EINVAL; 3211 } 3212 3213 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 3214 if (cycle > 0xFFFF) { 3215 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 3216 return -EINVAL; 3217 } 3218 3219 fep->rx_time_itr = ec->rx_coalesce_usecs; 3220 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 3221 3222 fep->tx_time_itr = ec->tx_coalesce_usecs; 3223 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 3224 3225 fec_enet_itr_coal_set(ndev); 3226 3227 return 0; 3228 } 3229 3230 static int 3231 fec_enet_get_eee(struct net_device *ndev, struct ethtool_keee *edata) 3232 { 3233 struct fec_enet_private *fep = netdev_priv(ndev); 3234 3235 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3236 return -EOPNOTSUPP; 3237 3238 if (!netif_running(ndev)) 3239 return -ENETDOWN; 3240 3241 return phy_ethtool_get_eee(ndev->phydev, edata); 3242 } 3243 3244 static int 3245 fec_enet_set_eee(struct net_device *ndev, struct ethtool_keee *edata) 3246 { 3247 struct fec_enet_private *fep = netdev_priv(ndev); 3248 3249 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3250 return -EOPNOTSUPP; 3251 3252 if (!netif_running(ndev)) 3253 return -ENETDOWN; 3254 3255 return phy_ethtool_set_eee(ndev->phydev, edata); 3256 } 3257 3258 static void 3259 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3260 { 3261 struct fec_enet_private *fep = netdev_priv(ndev); 3262 3263 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 3264 wol->supported = WAKE_MAGIC; 3265 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 3266 } else { 3267 wol->supported = wol->wolopts = 0; 3268 } 3269 } 3270 3271 static int 3272 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3273 { 3274 struct fec_enet_private *fep = netdev_priv(ndev); 3275 3276 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 3277 return -EINVAL; 3278 3279 if (wol->wolopts & ~WAKE_MAGIC) 3280 return -EINVAL; 3281 3282 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 3283 if (device_may_wakeup(&ndev->dev)) 3284 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 3285 else 3286 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 3287 3288 return 0; 3289 } 3290 3291 static const struct ethtool_ops fec_enet_ethtool_ops = { 3292 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3293 ETHTOOL_COALESCE_MAX_FRAMES, 3294 .get_drvinfo = fec_enet_get_drvinfo, 3295 .get_regs_len = fec_enet_get_regs_len, 3296 .get_regs = fec_enet_get_regs, 3297 .nway_reset = phy_ethtool_nway_reset, 3298 .get_link = ethtool_op_get_link, 3299 .get_coalesce = fec_enet_get_coalesce, 3300 .set_coalesce = fec_enet_set_coalesce, 3301 #ifndef CONFIG_M5272 3302 .get_pauseparam = fec_enet_get_pauseparam, 3303 .set_pauseparam = fec_enet_set_pauseparam, 3304 .get_strings = fec_enet_get_strings, 3305 .get_ethtool_stats = fec_enet_get_ethtool_stats, 3306 .get_sset_count = fec_enet_get_sset_count, 3307 #endif 3308 .get_ts_info = fec_enet_get_ts_info, 3309 .get_wol = fec_enet_get_wol, 3310 .set_wol = fec_enet_set_wol, 3311 .get_eee = fec_enet_get_eee, 3312 .set_eee = fec_enet_set_eee, 3313 .get_link_ksettings = phy_ethtool_get_link_ksettings, 3314 .set_link_ksettings = phy_ethtool_set_link_ksettings, 3315 .self_test = net_selftest, 3316 }; 3317 3318 static void fec_enet_free_buffers(struct net_device *ndev) 3319 { 3320 struct fec_enet_private *fep = netdev_priv(ndev); 3321 unsigned int i; 3322 struct fec_enet_priv_tx_q *txq; 3323 struct fec_enet_priv_rx_q *rxq; 3324 unsigned int q; 3325 3326 for (q = 0; q < fep->num_rx_queues; q++) { 3327 rxq = fep->rx_queue[q]; 3328 for (i = 0; i < rxq->bd.ring_size; i++) 3329 page_pool_put_full_page(rxq->page_pool, rxq->rx_skb_info[i].page, false); 3330 3331 for (i = 0; i < XDP_STATS_TOTAL; i++) 3332 rxq->stats[i] = 0; 3333 3334 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 3335 xdp_rxq_info_unreg(&rxq->xdp_rxq); 3336 page_pool_destroy(rxq->page_pool); 3337 rxq->page_pool = NULL; 3338 } 3339 3340 for (q = 0; q < fep->num_tx_queues; q++) { 3341 txq = fep->tx_queue[q]; 3342 for (i = 0; i < txq->bd.ring_size; i++) { 3343 kfree(txq->tx_bounce[i]); 3344 txq->tx_bounce[i] = NULL; 3345 3346 if (!txq->tx_buf[i].buf_p) { 3347 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3348 continue; 3349 } 3350 3351 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 3352 dev_kfree_skb(txq->tx_buf[i].buf_p); 3353 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 3354 xdp_return_frame(txq->tx_buf[i].buf_p); 3355 } else { 3356 struct page *page = txq->tx_buf[i].buf_p; 3357 3358 page_pool_put_page(pp_page_to_nmdesc(page)->pp, 3359 page, 0, false); 3360 } 3361 3362 txq->tx_buf[i].buf_p = NULL; 3363 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3364 } 3365 } 3366 } 3367 3368 static void fec_enet_free_queue(struct net_device *ndev) 3369 { 3370 struct fec_enet_private *fep = netdev_priv(ndev); 3371 int i; 3372 struct fec_enet_priv_tx_q *txq; 3373 3374 for (i = 0; i < fep->num_tx_queues; i++) 3375 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 3376 txq = fep->tx_queue[i]; 3377 fec_dma_free(&fep->pdev->dev, 3378 txq->bd.ring_size * TSO_HEADER_SIZE, 3379 txq->tso_hdrs, txq->tso_hdrs_dma); 3380 } 3381 3382 for (i = 0; i < fep->num_rx_queues; i++) 3383 kfree(fep->rx_queue[i]); 3384 for (i = 0; i < fep->num_tx_queues; i++) 3385 kfree(fep->tx_queue[i]); 3386 } 3387 3388 static int fec_enet_alloc_queue(struct net_device *ndev) 3389 { 3390 struct fec_enet_private *fep = netdev_priv(ndev); 3391 int i; 3392 int ret = 0; 3393 struct fec_enet_priv_tx_q *txq; 3394 3395 for (i = 0; i < fep->num_tx_queues; i++) { 3396 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 3397 if (!txq) { 3398 ret = -ENOMEM; 3399 goto alloc_failed; 3400 } 3401 3402 fep->tx_queue[i] = txq; 3403 txq->bd.ring_size = TX_RING_SIZE; 3404 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 3405 3406 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 3407 txq->tx_wake_threshold = FEC_MAX_SKB_DESCS + 2 * MAX_SKB_FRAGS; 3408 3409 txq->tso_hdrs = fec_dma_alloc(&fep->pdev->dev, 3410 txq->bd.ring_size * TSO_HEADER_SIZE, 3411 &txq->tso_hdrs_dma, GFP_KERNEL); 3412 if (!txq->tso_hdrs) { 3413 ret = -ENOMEM; 3414 goto alloc_failed; 3415 } 3416 } 3417 3418 for (i = 0; i < fep->num_rx_queues; i++) { 3419 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 3420 GFP_KERNEL); 3421 if (!fep->rx_queue[i]) { 3422 ret = -ENOMEM; 3423 goto alloc_failed; 3424 } 3425 3426 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 3427 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 3428 } 3429 return ret; 3430 3431 alloc_failed: 3432 fec_enet_free_queue(ndev); 3433 return ret; 3434 } 3435 3436 static int 3437 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 3438 { 3439 struct fec_enet_private *fep = netdev_priv(ndev); 3440 struct fec_enet_priv_rx_q *rxq; 3441 dma_addr_t phys_addr; 3442 struct bufdesc *bdp; 3443 struct page *page; 3444 int i, err; 3445 3446 rxq = fep->rx_queue[queue]; 3447 bdp = rxq->bd.base; 3448 3449 err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size); 3450 if (err < 0) { 3451 netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err); 3452 return err; 3453 } 3454 3455 for (i = 0; i < rxq->bd.ring_size; i++) { 3456 page = page_pool_dev_alloc_pages(rxq->page_pool); 3457 if (!page) 3458 goto err_alloc; 3459 3460 phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM; 3461 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 3462 3463 rxq->rx_skb_info[i].page = page; 3464 rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM; 3465 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3466 3467 if (fep->bufdesc_ex) { 3468 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3469 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 3470 } 3471 3472 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3473 } 3474 3475 /* Set the last buffer to wrap. */ 3476 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3477 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3478 return 0; 3479 3480 err_alloc: 3481 fec_enet_free_buffers(ndev); 3482 return -ENOMEM; 3483 } 3484 3485 static int 3486 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 3487 { 3488 struct fec_enet_private *fep = netdev_priv(ndev); 3489 unsigned int i; 3490 struct bufdesc *bdp; 3491 struct fec_enet_priv_tx_q *txq; 3492 3493 txq = fep->tx_queue[queue]; 3494 bdp = txq->bd.base; 3495 for (i = 0; i < txq->bd.ring_size; i++) { 3496 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 3497 if (!txq->tx_bounce[i]) 3498 goto err_alloc; 3499 3500 bdp->cbd_sc = cpu_to_fec16(0); 3501 bdp->cbd_bufaddr = cpu_to_fec32(0); 3502 3503 if (fep->bufdesc_ex) { 3504 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3505 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 3506 } 3507 3508 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3509 } 3510 3511 /* Set the last buffer to wrap. */ 3512 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3513 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3514 3515 return 0; 3516 3517 err_alloc: 3518 fec_enet_free_buffers(ndev); 3519 return -ENOMEM; 3520 } 3521 3522 static int fec_enet_alloc_buffers(struct net_device *ndev) 3523 { 3524 struct fec_enet_private *fep = netdev_priv(ndev); 3525 unsigned int i; 3526 3527 for (i = 0; i < fep->num_rx_queues; i++) 3528 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3529 return -ENOMEM; 3530 3531 for (i = 0; i < fep->num_tx_queues; i++) 3532 if (fec_enet_alloc_txq_buffers(ndev, i)) 3533 return -ENOMEM; 3534 return 0; 3535 } 3536 3537 static int 3538 fec_enet_open(struct net_device *ndev) 3539 { 3540 struct fec_enet_private *fep = netdev_priv(ndev); 3541 int ret; 3542 bool reset_again; 3543 3544 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3545 if (ret < 0) 3546 return ret; 3547 3548 pinctrl_pm_select_default_state(&fep->pdev->dev); 3549 ret = fec_enet_clk_enable(ndev, true); 3550 if (ret) 3551 goto clk_enable; 3552 3553 /* During the first fec_enet_open call the PHY isn't probed at this 3554 * point. Therefore the phy_reset_after_clk_enable() call within 3555 * fec_enet_clk_enable() fails. As we need this reset in order to be 3556 * sure the PHY is working correctly we check if we need to reset again 3557 * later when the PHY is probed 3558 */ 3559 if (ndev->phydev && ndev->phydev->drv) 3560 reset_again = false; 3561 else 3562 reset_again = true; 3563 3564 /* I should reset the ring buffers here, but I don't yet know 3565 * a simple way to do that. 3566 */ 3567 3568 ret = fec_enet_alloc_buffers(ndev); 3569 if (ret) 3570 goto err_enet_alloc; 3571 3572 /* Init MAC prior to mii bus probe */ 3573 fec_restart(ndev); 3574 3575 /* Call phy_reset_after_clk_enable() again if it failed during 3576 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3577 */ 3578 if (reset_again) 3579 fec_enet_phy_reset_after_clk_enable(ndev); 3580 3581 /* Probe and connect to PHY when open the interface */ 3582 ret = fec_enet_mii_probe(ndev); 3583 if (ret) 3584 goto err_enet_mii_probe; 3585 3586 if (fep->quirks & FEC_QUIRK_ERR006687) 3587 imx6q_cpuidle_fec_irqs_used(); 3588 3589 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3590 cpu_latency_qos_add_request(&fep->pm_qos_req, 0); 3591 3592 napi_enable(&fep->napi); 3593 phy_start(ndev->phydev); 3594 netif_tx_start_all_queues(ndev); 3595 3596 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3597 FEC_WOL_FLAG_ENABLE); 3598 3599 return 0; 3600 3601 err_enet_mii_probe: 3602 fec_enet_free_buffers(ndev); 3603 err_enet_alloc: 3604 fec_enet_clk_enable(ndev, false); 3605 clk_enable: 3606 pm_runtime_put_autosuspend(&fep->pdev->dev); 3607 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3608 return ret; 3609 } 3610 3611 static int 3612 fec_enet_close(struct net_device *ndev) 3613 { 3614 struct fec_enet_private *fep = netdev_priv(ndev); 3615 struct phy_device *phy_dev = ndev->phydev; 3616 3617 phy_stop(phy_dev); 3618 3619 if (netif_device_present(ndev)) { 3620 napi_disable(&fep->napi); 3621 netif_tx_disable(ndev); 3622 fec_stop(ndev); 3623 } 3624 3625 phy_disconnect(phy_dev); 3626 3627 if (!fep->phy_node && phy_is_pseudo_fixed_link(phy_dev)) 3628 fixed_phy_unregister(phy_dev); 3629 3630 if (fep->quirks & FEC_QUIRK_ERR006687) 3631 imx6q_cpuidle_fec_irqs_unused(); 3632 3633 fec_enet_update_ethtool_stats(ndev); 3634 3635 fec_enet_clk_enable(ndev, false); 3636 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3637 cpu_latency_qos_remove_request(&fep->pm_qos_req); 3638 3639 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3640 pm_runtime_put_autosuspend(&fep->pdev->dev); 3641 3642 fec_enet_free_buffers(ndev); 3643 3644 return 0; 3645 } 3646 3647 /* Set or clear the multicast filter for this adaptor. 3648 * Skeleton taken from sunlance driver. 3649 * The CPM Ethernet implementation allows Multicast as well as individual 3650 * MAC address filtering. Some of the drivers check to make sure it is 3651 * a group multicast address, and discard those that are not. I guess I 3652 * will do the same for now, but just remove the test if you want 3653 * individual filtering as well (do the upper net layers want or support 3654 * this kind of feature?). 3655 */ 3656 3657 #define FEC_HASH_BITS 6 /* #bits in hash */ 3658 3659 static void set_multicast_list(struct net_device *ndev) 3660 { 3661 struct fec_enet_private *fep = netdev_priv(ndev); 3662 struct netdev_hw_addr *ha; 3663 unsigned int crc, tmp; 3664 unsigned char hash; 3665 unsigned int hash_high = 0, hash_low = 0; 3666 3667 if (ndev->flags & IFF_PROMISC) { 3668 tmp = readl(fep->hwp + FEC_R_CNTRL); 3669 tmp |= 0x8; 3670 writel(tmp, fep->hwp + FEC_R_CNTRL); 3671 return; 3672 } 3673 3674 tmp = readl(fep->hwp + FEC_R_CNTRL); 3675 tmp &= ~0x8; 3676 writel(tmp, fep->hwp + FEC_R_CNTRL); 3677 3678 if (ndev->flags & IFF_ALLMULTI) { 3679 /* Catch all multicast addresses, so set the 3680 * filter to all 1's 3681 */ 3682 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3683 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3684 3685 return; 3686 } 3687 3688 /* Add the addresses in hash register */ 3689 netdev_for_each_mc_addr(ha, ndev) { 3690 /* calculate crc32 value of mac address */ 3691 crc = ether_crc_le(ndev->addr_len, ha->addr); 3692 3693 /* only upper 6 bits (FEC_HASH_BITS) are used 3694 * which point to specific bit in the hash registers 3695 */ 3696 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3697 3698 if (hash > 31) 3699 hash_high |= 1 << (hash - 32); 3700 else 3701 hash_low |= 1 << hash; 3702 } 3703 3704 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3705 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3706 } 3707 3708 /* Set a MAC change in hardware. */ 3709 static int 3710 fec_set_mac_address(struct net_device *ndev, void *p) 3711 { 3712 struct sockaddr *addr = p; 3713 3714 if (addr) { 3715 if (!is_valid_ether_addr(addr->sa_data)) 3716 return -EADDRNOTAVAIL; 3717 eth_hw_addr_set(ndev, addr->sa_data); 3718 } 3719 3720 /* Add netif status check here to avoid system hang in below case: 3721 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3722 * After ethx down, fec all clocks are gated off and then register 3723 * access causes system hang. 3724 */ 3725 if (!netif_running(ndev)) 3726 return 0; 3727 3728 fec_set_hw_mac_addr(ndev); 3729 3730 return 0; 3731 } 3732 3733 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3734 netdev_features_t features) 3735 { 3736 struct fec_enet_private *fep = netdev_priv(netdev); 3737 netdev_features_t changed = features ^ netdev->features; 3738 3739 netdev->features = features; 3740 3741 /* Receive checksum has been changed */ 3742 if (changed & NETIF_F_RXCSUM) { 3743 if (features & NETIF_F_RXCSUM) 3744 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3745 else 3746 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3747 } 3748 } 3749 3750 static int fec_set_features(struct net_device *netdev, 3751 netdev_features_t features) 3752 { 3753 struct fec_enet_private *fep = netdev_priv(netdev); 3754 netdev_features_t changed = features ^ netdev->features; 3755 3756 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3757 napi_disable(&fep->napi); 3758 netif_tx_lock_bh(netdev); 3759 fec_stop(netdev); 3760 fec_enet_set_netdev_features(netdev, features); 3761 fec_restart(netdev); 3762 netif_tx_wake_all_queues(netdev); 3763 netif_tx_unlock_bh(netdev); 3764 napi_enable(&fep->napi); 3765 } else { 3766 fec_enet_set_netdev_features(netdev, features); 3767 } 3768 3769 return 0; 3770 } 3771 3772 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3773 struct net_device *sb_dev) 3774 { 3775 struct fec_enet_private *fep = netdev_priv(ndev); 3776 u16 vlan_tag = 0; 3777 3778 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3779 return netdev_pick_tx(ndev, skb, NULL); 3780 3781 /* VLAN is present in the payload.*/ 3782 if (eth_type_vlan(skb->protocol)) { 3783 struct vlan_ethhdr *vhdr = skb_vlan_eth_hdr(skb); 3784 3785 vlan_tag = ntohs(vhdr->h_vlan_TCI); 3786 /* VLAN is present in the skb but not yet pushed in the payload.*/ 3787 } else if (skb_vlan_tag_present(skb)) { 3788 vlan_tag = skb->vlan_tci; 3789 } else { 3790 return vlan_tag; 3791 } 3792 3793 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3794 } 3795 3796 static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf) 3797 { 3798 struct fec_enet_private *fep = netdev_priv(dev); 3799 bool is_run = netif_running(dev); 3800 struct bpf_prog *old_prog; 3801 3802 switch (bpf->command) { 3803 case XDP_SETUP_PROG: 3804 /* No need to support the SoCs that require to 3805 * do the frame swap because the performance wouldn't be 3806 * better than the skb mode. 3807 */ 3808 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 3809 return -EOPNOTSUPP; 3810 3811 if (!bpf->prog) 3812 xdp_features_clear_redirect_target(dev); 3813 3814 if (is_run) { 3815 napi_disable(&fep->napi); 3816 netif_tx_disable(dev); 3817 } 3818 3819 old_prog = xchg(&fep->xdp_prog, bpf->prog); 3820 if (old_prog) 3821 bpf_prog_put(old_prog); 3822 3823 fec_restart(dev); 3824 3825 if (is_run) { 3826 napi_enable(&fep->napi); 3827 netif_tx_start_all_queues(dev); 3828 } 3829 3830 if (bpf->prog) 3831 xdp_features_set_redirect_target(dev, false); 3832 3833 return 0; 3834 3835 case XDP_SETUP_XSK_POOL: 3836 return -EOPNOTSUPP; 3837 3838 default: 3839 return -EOPNOTSUPP; 3840 } 3841 } 3842 3843 static int 3844 fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index) 3845 { 3846 if (unlikely(index < 0)) 3847 return 0; 3848 3849 return (index % fep->num_tx_queues); 3850 } 3851 3852 static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep, 3853 struct fec_enet_priv_tx_q *txq, 3854 void *frame, u32 dma_sync_len, 3855 bool ndo_xmit) 3856 { 3857 unsigned int index, status, estatus; 3858 struct bufdesc *bdp; 3859 dma_addr_t dma_addr; 3860 int entries_free; 3861 u16 frame_len; 3862 3863 entries_free = fec_enet_get_free_txdesc_num(txq); 3864 if (entries_free < MAX_SKB_FRAGS + 1) { 3865 netdev_err_once(fep->netdev, "NOT enough BD for SG!\n"); 3866 return -EBUSY; 3867 } 3868 3869 /* Fill in a Tx ring entry */ 3870 bdp = txq->bd.cur; 3871 status = fec16_to_cpu(bdp->cbd_sc); 3872 status &= ~BD_ENET_TX_STATS; 3873 3874 index = fec_enet_get_bd_index(bdp, &txq->bd); 3875 3876 if (ndo_xmit) { 3877 struct xdp_frame *xdpf = frame; 3878 3879 dma_addr = dma_map_single(&fep->pdev->dev, xdpf->data, 3880 xdpf->len, DMA_TO_DEVICE); 3881 if (dma_mapping_error(&fep->pdev->dev, dma_addr)) 3882 return -ENOMEM; 3883 3884 frame_len = xdpf->len; 3885 txq->tx_buf[index].buf_p = xdpf; 3886 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_NDO; 3887 } else { 3888 struct xdp_buff *xdpb = frame; 3889 struct page *page; 3890 3891 page = virt_to_page(xdpb->data); 3892 dma_addr = page_pool_get_dma_addr(page) + 3893 (xdpb->data - xdpb->data_hard_start); 3894 dma_sync_single_for_device(&fep->pdev->dev, dma_addr, 3895 dma_sync_len, DMA_BIDIRECTIONAL); 3896 frame_len = xdpb->data_end - xdpb->data; 3897 txq->tx_buf[index].buf_p = page; 3898 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_TX; 3899 } 3900 3901 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 3902 if (fep->bufdesc_ex) 3903 estatus = BD_ENET_TX_INT; 3904 3905 bdp->cbd_bufaddr = cpu_to_fec32(dma_addr); 3906 bdp->cbd_datlen = cpu_to_fec16(frame_len); 3907 3908 if (fep->bufdesc_ex) { 3909 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3910 3911 if (fep->quirks & FEC_QUIRK_HAS_AVB) 3912 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 3913 3914 ebdp->cbd_bdu = 0; 3915 ebdp->cbd_esc = cpu_to_fec32(estatus); 3916 } 3917 3918 /* Make sure the updates to rest of the descriptor are performed before 3919 * transferring ownership. 3920 */ 3921 dma_wmb(); 3922 3923 /* Send it on its way. Tell FEC it's ready, interrupt when done, 3924 * it's the last BD of the frame, and to put the CRC on the end. 3925 */ 3926 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 3927 bdp->cbd_sc = cpu_to_fec16(status); 3928 3929 /* If this was the last BD in the ring, start at the beginning again. */ 3930 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3931 3932 /* Make sure the update to bdp are performed before txq->bd.cur. */ 3933 dma_wmb(); 3934 3935 txq->bd.cur = bdp; 3936 3937 /* Trigger transmission start */ 3938 writel(0, txq->bd.reg_desc_active); 3939 3940 return 0; 3941 } 3942 3943 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 3944 int cpu, struct xdp_buff *xdp, 3945 u32 dma_sync_len) 3946 { 3947 struct fec_enet_priv_tx_q *txq; 3948 struct netdev_queue *nq; 3949 int queue, ret; 3950 3951 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3952 txq = fep->tx_queue[queue]; 3953 nq = netdev_get_tx_queue(fep->netdev, queue); 3954 3955 __netif_tx_lock(nq, cpu); 3956 3957 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3958 txq_trans_cond_update(nq); 3959 ret = fec_enet_txq_xmit_frame(fep, txq, xdp, dma_sync_len, false); 3960 3961 __netif_tx_unlock(nq); 3962 3963 return ret; 3964 } 3965 3966 static int fec_enet_xdp_xmit(struct net_device *dev, 3967 int num_frames, 3968 struct xdp_frame **frames, 3969 u32 flags) 3970 { 3971 struct fec_enet_private *fep = netdev_priv(dev); 3972 struct fec_enet_priv_tx_q *txq; 3973 int cpu = smp_processor_id(); 3974 unsigned int sent_frames = 0; 3975 struct netdev_queue *nq; 3976 unsigned int queue; 3977 int i; 3978 3979 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3980 txq = fep->tx_queue[queue]; 3981 nq = netdev_get_tx_queue(fep->netdev, queue); 3982 3983 __netif_tx_lock(nq, cpu); 3984 3985 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3986 txq_trans_cond_update(nq); 3987 for (i = 0; i < num_frames; i++) { 3988 if (fec_enet_txq_xmit_frame(fep, txq, frames[i], 0, true) < 0) 3989 break; 3990 sent_frames++; 3991 } 3992 3993 __netif_tx_unlock(nq); 3994 3995 return sent_frames; 3996 } 3997 3998 static int fec_hwtstamp_get(struct net_device *ndev, 3999 struct kernel_hwtstamp_config *config) 4000 { 4001 struct fec_enet_private *fep = netdev_priv(ndev); 4002 4003 if (!netif_running(ndev)) 4004 return -EINVAL; 4005 4006 if (!fep->bufdesc_ex) 4007 return -EOPNOTSUPP; 4008 4009 fec_ptp_get(ndev, config); 4010 4011 return 0; 4012 } 4013 4014 static int fec_hwtstamp_set(struct net_device *ndev, 4015 struct kernel_hwtstamp_config *config, 4016 struct netlink_ext_ack *extack) 4017 { 4018 struct fec_enet_private *fep = netdev_priv(ndev); 4019 4020 if (!netif_running(ndev)) 4021 return -EINVAL; 4022 4023 if (!fep->bufdesc_ex) 4024 return -EOPNOTSUPP; 4025 4026 return fec_ptp_set(ndev, config, extack); 4027 } 4028 4029 static int fec_change_mtu(struct net_device *ndev, int new_mtu) 4030 { 4031 struct fec_enet_private *fep = netdev_priv(ndev); 4032 int order; 4033 4034 if (netif_running(ndev)) 4035 return -EBUSY; 4036 4037 order = get_order(new_mtu + ETH_HLEN + ETH_FCS_LEN 4038 + FEC_DRV_RESERVE_SPACE); 4039 fep->rx_frame_size = (PAGE_SIZE << order) - FEC_DRV_RESERVE_SPACE; 4040 fep->pagepool_order = order; 4041 WRITE_ONCE(ndev->mtu, new_mtu); 4042 4043 return 0; 4044 } 4045 4046 static const struct net_device_ops fec_netdev_ops = { 4047 .ndo_open = fec_enet_open, 4048 .ndo_stop = fec_enet_close, 4049 .ndo_start_xmit = fec_enet_start_xmit, 4050 .ndo_select_queue = fec_enet_select_queue, 4051 .ndo_set_rx_mode = set_multicast_list, 4052 .ndo_validate_addr = eth_validate_addr, 4053 .ndo_tx_timeout = fec_timeout, 4054 .ndo_set_mac_address = fec_set_mac_address, 4055 .ndo_change_mtu = fec_change_mtu, 4056 .ndo_eth_ioctl = phy_do_ioctl_running, 4057 .ndo_set_features = fec_set_features, 4058 .ndo_bpf = fec_enet_bpf, 4059 .ndo_xdp_xmit = fec_enet_xdp_xmit, 4060 .ndo_hwtstamp_get = fec_hwtstamp_get, 4061 .ndo_hwtstamp_set = fec_hwtstamp_set, 4062 }; 4063 4064 static const unsigned short offset_des_active_rxq[] = { 4065 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 4066 }; 4067 4068 static const unsigned short offset_des_active_txq[] = { 4069 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 4070 }; 4071 4072 /* 4073 * XXX: We need to clean up on failure exits here. 4074 * 4075 */ 4076 static int fec_enet_init(struct net_device *ndev) 4077 { 4078 struct fec_enet_private *fep = netdev_priv(ndev); 4079 struct bufdesc *cbd_base; 4080 dma_addr_t bd_dma; 4081 int bd_size; 4082 unsigned int i; 4083 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 4084 sizeof(struct bufdesc); 4085 unsigned dsize_log2 = __fls(dsize); 4086 int ret; 4087 4088 WARN_ON(dsize != (1 << dsize_log2)); 4089 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 4090 fep->rx_align = 0xf; 4091 fep->tx_align = 0xf; 4092 #else 4093 fep->rx_align = 0x3; 4094 fep->tx_align = 0x3; 4095 #endif 4096 fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4097 fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4098 fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT; 4099 fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT; 4100 4101 /* Check mask of the streaming and coherent API */ 4102 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 4103 if (ret < 0) { 4104 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 4105 return ret; 4106 } 4107 4108 ret = fec_enet_alloc_queue(ndev); 4109 if (ret) 4110 return ret; 4111 4112 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 4113 4114 /* Allocate memory for buffer descriptors. */ 4115 cbd_base = fec_dmam_alloc(&fep->pdev->dev, bd_size, &bd_dma, 4116 GFP_KERNEL); 4117 if (!cbd_base) { 4118 ret = -ENOMEM; 4119 goto free_queue_mem; 4120 } 4121 4122 /* Get the Ethernet address */ 4123 ret = fec_get_mac(ndev); 4124 if (ret) 4125 goto free_queue_mem; 4126 4127 /* Set receive and transmit descriptor base. */ 4128 for (i = 0; i < fep->num_rx_queues; i++) { 4129 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 4130 unsigned size = dsize * rxq->bd.ring_size; 4131 4132 rxq->bd.qid = i; 4133 rxq->bd.base = cbd_base; 4134 rxq->bd.cur = cbd_base; 4135 rxq->bd.dma = bd_dma; 4136 rxq->bd.dsize = dsize; 4137 rxq->bd.dsize_log2 = dsize_log2; 4138 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 4139 bd_dma += size; 4140 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4141 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4142 } 4143 4144 for (i = 0; i < fep->num_tx_queues; i++) { 4145 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 4146 unsigned size = dsize * txq->bd.ring_size; 4147 4148 txq->bd.qid = i; 4149 txq->bd.base = cbd_base; 4150 txq->bd.cur = cbd_base; 4151 txq->bd.dma = bd_dma; 4152 txq->bd.dsize = dsize; 4153 txq->bd.dsize_log2 = dsize_log2; 4154 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 4155 bd_dma += size; 4156 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4157 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4158 } 4159 4160 4161 /* The FEC Ethernet specific entries in the device structure */ 4162 ndev->watchdog_timeo = TX_TIMEOUT; 4163 ndev->netdev_ops = &fec_netdev_ops; 4164 ndev->ethtool_ops = &fec_enet_ethtool_ops; 4165 4166 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 4167 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi); 4168 4169 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 4170 /* enable hw VLAN support */ 4171 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 4172 4173 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 4174 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS); 4175 4176 /* enable hw accelerator */ 4177 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 4178 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 4179 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 4180 } 4181 4182 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 4183 fep->tx_align = 0; 4184 fep->rx_align = 0x3f; 4185 } 4186 4187 ndev->hw_features = ndev->features; 4188 4189 if (!(fep->quirks & FEC_QUIRK_SWAP_FRAME)) 4190 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 4191 NETDEV_XDP_ACT_REDIRECT; 4192 4193 fec_restart(ndev); 4194 4195 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 4196 fec_enet_clear_ethtool_stats(ndev); 4197 else 4198 fec_enet_update_ethtool_stats(ndev); 4199 4200 return 0; 4201 4202 free_queue_mem: 4203 fec_enet_free_queue(ndev); 4204 return ret; 4205 } 4206 4207 static void fec_enet_deinit(struct net_device *ndev) 4208 { 4209 struct fec_enet_private *fep = netdev_priv(ndev); 4210 4211 netif_napi_del(&fep->napi); 4212 fec_enet_free_queue(ndev); 4213 } 4214 4215 #ifdef CONFIG_OF 4216 static int fec_reset_phy(struct platform_device *pdev) 4217 { 4218 struct gpio_desc *phy_reset; 4219 int msec = 1, phy_post_delay = 0; 4220 struct device_node *np = pdev->dev.of_node; 4221 int err; 4222 4223 if (!np) 4224 return 0; 4225 4226 err = of_property_read_u32(np, "phy-reset-duration", &msec); 4227 /* A sane reset duration should not be longer than 1s */ 4228 if (!err && msec > 1000) 4229 msec = 1; 4230 4231 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 4232 /* valid reset duration should be less than 1s */ 4233 if (!err && phy_post_delay > 1000) 4234 return -EINVAL; 4235 4236 phy_reset = devm_gpiod_get_optional(&pdev->dev, "phy-reset", 4237 GPIOD_OUT_HIGH); 4238 if (IS_ERR(phy_reset)) 4239 return dev_err_probe(&pdev->dev, PTR_ERR(phy_reset), 4240 "failed to get phy-reset-gpios\n"); 4241 4242 if (!phy_reset) 4243 return 0; 4244 4245 if (msec > 20) 4246 msleep(msec); 4247 else 4248 usleep_range(msec * 1000, msec * 1000 + 1000); 4249 4250 gpiod_set_value_cansleep(phy_reset, 0); 4251 4252 if (!phy_post_delay) 4253 return 0; 4254 4255 if (phy_post_delay > 20) 4256 msleep(phy_post_delay); 4257 else 4258 usleep_range(phy_post_delay * 1000, 4259 phy_post_delay * 1000 + 1000); 4260 4261 return 0; 4262 } 4263 #else /* CONFIG_OF */ 4264 static int fec_reset_phy(struct platform_device *pdev) 4265 { 4266 /* 4267 * In case of platform probe, the reset has been done 4268 * by machine code. 4269 */ 4270 return 0; 4271 } 4272 #endif /* CONFIG_OF */ 4273 4274 static void 4275 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 4276 { 4277 struct device_node *np = pdev->dev.of_node; 4278 4279 *num_tx = *num_rx = 1; 4280 4281 if (!np || !of_device_is_available(np)) 4282 return; 4283 4284 /* parse the num of tx and rx queues */ 4285 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 4286 4287 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 4288 4289 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 4290 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 4291 *num_tx); 4292 *num_tx = 1; 4293 return; 4294 } 4295 4296 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 4297 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 4298 *num_rx); 4299 *num_rx = 1; 4300 return; 4301 } 4302 4303 } 4304 4305 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 4306 { 4307 int irq_cnt = platform_irq_count(pdev); 4308 4309 if (irq_cnt > FEC_IRQ_NUM) 4310 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 4311 else if (irq_cnt == 2) 4312 irq_cnt = 1; /* last for pps */ 4313 else if (irq_cnt <= 0) 4314 irq_cnt = 1; /* At least 1 irq is needed */ 4315 return irq_cnt; 4316 } 4317 4318 static void fec_enet_get_wakeup_irq(struct platform_device *pdev) 4319 { 4320 struct net_device *ndev = platform_get_drvdata(pdev); 4321 struct fec_enet_private *fep = netdev_priv(ndev); 4322 4323 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) 4324 fep->wake_irq = fep->irq[2]; 4325 else 4326 fep->wake_irq = fep->irq[0]; 4327 } 4328 4329 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 4330 struct device_node *np) 4331 { 4332 struct device_node *gpr_np; 4333 u32 out_val[3]; 4334 int ret = 0; 4335 4336 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 4337 if (!gpr_np) 4338 return 0; 4339 4340 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 4341 ARRAY_SIZE(out_val)); 4342 if (ret) { 4343 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 4344 goto out; 4345 } 4346 4347 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 4348 if (IS_ERR(fep->stop_gpr.gpr)) { 4349 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 4350 ret = PTR_ERR(fep->stop_gpr.gpr); 4351 fep->stop_gpr.gpr = NULL; 4352 goto out; 4353 } 4354 4355 fep->stop_gpr.reg = out_val[1]; 4356 fep->stop_gpr.bit = out_val[2]; 4357 4358 out: 4359 of_node_put(gpr_np); 4360 4361 return ret; 4362 } 4363 4364 static int 4365 fec_probe(struct platform_device *pdev) 4366 { 4367 struct fec_enet_private *fep; 4368 struct fec_platform_data *pdata; 4369 phy_interface_t interface; 4370 struct net_device *ndev; 4371 int i, irq, ret = 0; 4372 static int dev_id; 4373 struct device_node *np = pdev->dev.of_node, *phy_node; 4374 int num_tx_qs; 4375 int num_rx_qs; 4376 char irq_name[8]; 4377 int irq_cnt; 4378 const struct fec_devinfo *dev_info; 4379 4380 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 4381 4382 /* Init network device */ 4383 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 4384 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 4385 if (!ndev) 4386 return -ENOMEM; 4387 4388 SET_NETDEV_DEV(ndev, &pdev->dev); 4389 4390 /* setup board info structure */ 4391 fep = netdev_priv(ndev); 4392 4393 dev_info = device_get_match_data(&pdev->dev); 4394 if (!dev_info) 4395 dev_info = (const struct fec_devinfo *)pdev->id_entry->driver_data; 4396 if (dev_info) 4397 fep->quirks = dev_info->quirks; 4398 4399 fep->netdev = ndev; 4400 fep->num_rx_queues = num_rx_qs; 4401 fep->num_tx_queues = num_tx_qs; 4402 4403 #if !defined(CONFIG_M5272) 4404 /* default enable pause frame auto negotiation */ 4405 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 4406 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 4407 #endif 4408 4409 /* Select default pin state */ 4410 pinctrl_pm_select_default_state(&pdev->dev); 4411 4412 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 4413 if (IS_ERR(fep->hwp)) { 4414 ret = PTR_ERR(fep->hwp); 4415 goto failed_ioremap; 4416 } 4417 4418 fep->pdev = pdev; 4419 fep->dev_id = dev_id++; 4420 4421 platform_set_drvdata(pdev, ndev); 4422 4423 if ((of_machine_is_compatible("fsl,imx6q") || 4424 of_machine_is_compatible("fsl,imx6dl")) && 4425 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 4426 fep->quirks |= FEC_QUIRK_ERR006687; 4427 4428 ret = fec_enet_ipc_handle_init(fep); 4429 if (ret) 4430 goto failed_ipc_init; 4431 4432 if (of_property_read_bool(np, "fsl,magic-packet")) 4433 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 4434 4435 ret = fec_enet_init_stop_mode(fep, np); 4436 if (ret) 4437 goto failed_stop_mode; 4438 4439 phy_node = of_parse_phandle(np, "phy-handle", 0); 4440 if (!phy_node && of_phy_is_fixed_link(np)) { 4441 ret = of_phy_register_fixed_link(np); 4442 if (ret < 0) { 4443 dev_err(&pdev->dev, 4444 "broken fixed-link specification\n"); 4445 goto failed_phy; 4446 } 4447 phy_node = of_node_get(np); 4448 } 4449 fep->phy_node = phy_node; 4450 4451 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 4452 if (ret) { 4453 pdata = dev_get_platdata(&pdev->dev); 4454 if (pdata) 4455 fep->phy_interface = pdata->phy; 4456 else 4457 fep->phy_interface = PHY_INTERFACE_MODE_MII; 4458 } else { 4459 fep->phy_interface = interface; 4460 } 4461 4462 ret = fec_enet_parse_rgmii_delay(fep, np); 4463 if (ret) 4464 goto failed_rgmii_delay; 4465 4466 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 4467 if (IS_ERR(fep->clk_ipg)) { 4468 ret = PTR_ERR(fep->clk_ipg); 4469 goto failed_clk; 4470 } 4471 4472 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 4473 if (IS_ERR(fep->clk_ahb)) { 4474 ret = PTR_ERR(fep->clk_ahb); 4475 goto failed_clk; 4476 } 4477 4478 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 4479 4480 /* enet_out is optional, depends on board */ 4481 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out"); 4482 if (IS_ERR(fep->clk_enet_out)) { 4483 ret = PTR_ERR(fep->clk_enet_out); 4484 goto failed_clk; 4485 } 4486 4487 fep->ptp_clk_on = false; 4488 mutex_init(&fep->ptp_clk_mutex); 4489 4490 /* clk_ref is optional, depends on board */ 4491 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref"); 4492 if (IS_ERR(fep->clk_ref)) { 4493 ret = PTR_ERR(fep->clk_ref); 4494 goto failed_clk; 4495 } 4496 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); 4497 4498 /* clk_2x_txclk is optional, depends on board */ 4499 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { 4500 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); 4501 if (IS_ERR(fep->clk_2x_txclk)) 4502 fep->clk_2x_txclk = NULL; 4503 } 4504 4505 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 4506 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 4507 if (IS_ERR(fep->clk_ptp)) { 4508 fep->clk_ptp = NULL; 4509 fep->bufdesc_ex = false; 4510 } 4511 4512 ret = fec_enet_clk_enable(ndev, true); 4513 if (ret) 4514 goto failed_clk; 4515 4516 ret = clk_prepare_enable(fep->clk_ipg); 4517 if (ret) 4518 goto failed_clk_ipg; 4519 ret = clk_prepare_enable(fep->clk_ahb); 4520 if (ret) 4521 goto failed_clk_ahb; 4522 4523 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 4524 if (!IS_ERR(fep->reg_phy)) { 4525 ret = regulator_enable(fep->reg_phy); 4526 if (ret) { 4527 dev_err(&pdev->dev, 4528 "Failed to enable phy regulator: %d\n", ret); 4529 goto failed_regulator; 4530 } 4531 } else { 4532 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 4533 ret = -EPROBE_DEFER; 4534 goto failed_regulator; 4535 } 4536 fep->reg_phy = NULL; 4537 } 4538 4539 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 4540 pm_runtime_use_autosuspend(&pdev->dev); 4541 pm_runtime_get_noresume(&pdev->dev); 4542 pm_runtime_set_active(&pdev->dev); 4543 pm_runtime_enable(&pdev->dev); 4544 4545 ret = fec_reset_phy(pdev); 4546 if (ret) 4547 goto failed_reset; 4548 4549 irq_cnt = fec_enet_get_irq_cnt(pdev); 4550 if (fep->bufdesc_ex) 4551 fec_ptp_init(pdev, irq_cnt); 4552 4553 ret = fec_enet_init(ndev); 4554 if (ret) 4555 goto failed_init; 4556 4557 for (i = 0; i < irq_cnt; i++) { 4558 snprintf(irq_name, sizeof(irq_name), "int%d", i); 4559 irq = platform_get_irq_byname_optional(pdev, irq_name); 4560 if (irq < 0) 4561 irq = platform_get_irq(pdev, i); 4562 if (irq < 0) { 4563 ret = irq; 4564 goto failed_irq; 4565 } 4566 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 4567 0, pdev->name, ndev); 4568 if (ret) 4569 goto failed_irq; 4570 4571 fep->irq[i] = irq; 4572 } 4573 4574 /* Decide which interrupt line is wakeup capable */ 4575 fec_enet_get_wakeup_irq(pdev); 4576 4577 ret = fec_enet_mii_init(pdev); 4578 if (ret) 4579 goto failed_mii_init; 4580 4581 /* Carrier starts down, phylib will bring it up */ 4582 netif_carrier_off(ndev); 4583 fec_enet_clk_enable(ndev, false); 4584 pinctrl_pm_select_sleep_state(&pdev->dev); 4585 4586 fep->pagepool_order = 0; 4587 fep->rx_frame_size = FEC_ENET_RX_FRSIZE; 4588 4589 if (fep->quirks & FEC_QUIRK_JUMBO_FRAME) 4590 fep->max_buf_size = MAX_JUMBO_BUF_SIZE; 4591 else 4592 fep->max_buf_size = PKT_MAXBUF_SIZE; 4593 4594 ndev->max_mtu = fep->max_buf_size - ETH_HLEN - ETH_FCS_LEN; 4595 4596 ret = register_netdev(ndev); 4597 if (ret) 4598 goto failed_register; 4599 4600 device_init_wakeup(&ndev->dev, fep->wol_flag & 4601 FEC_WOL_HAS_MAGIC_PACKET); 4602 4603 if (fep->bufdesc_ex && fep->ptp_clock) 4604 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 4605 4606 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 4607 4608 pm_runtime_put_autosuspend(&pdev->dev); 4609 4610 return 0; 4611 4612 failed_register: 4613 fec_enet_mii_remove(fep); 4614 failed_mii_init: 4615 failed_irq: 4616 fec_enet_deinit(ndev); 4617 failed_init: 4618 fec_ptp_stop(pdev); 4619 failed_reset: 4620 pm_runtime_put_noidle(&pdev->dev); 4621 pm_runtime_disable(&pdev->dev); 4622 if (fep->reg_phy) 4623 regulator_disable(fep->reg_phy); 4624 failed_regulator: 4625 clk_disable_unprepare(fep->clk_ahb); 4626 failed_clk_ahb: 4627 clk_disable_unprepare(fep->clk_ipg); 4628 failed_clk_ipg: 4629 fec_enet_clk_enable(ndev, false); 4630 failed_clk: 4631 failed_rgmii_delay: 4632 if (of_phy_is_fixed_link(np)) 4633 of_phy_deregister_fixed_link(np); 4634 of_node_put(phy_node); 4635 failed_stop_mode: 4636 failed_ipc_init: 4637 failed_phy: 4638 dev_id--; 4639 failed_ioremap: 4640 free_netdev(ndev); 4641 4642 return ret; 4643 } 4644 4645 static void 4646 fec_drv_remove(struct platform_device *pdev) 4647 { 4648 struct net_device *ndev = platform_get_drvdata(pdev); 4649 struct fec_enet_private *fep = netdev_priv(ndev); 4650 struct device_node *np = pdev->dev.of_node; 4651 int ret; 4652 4653 ret = pm_runtime_get_sync(&pdev->dev); 4654 if (ret < 0) 4655 dev_err(&pdev->dev, 4656 "Failed to resume device in remove callback (%pe)\n", 4657 ERR_PTR(ret)); 4658 4659 cancel_work_sync(&fep->tx_timeout_work); 4660 fec_ptp_stop(pdev); 4661 unregister_netdev(ndev); 4662 fec_enet_mii_remove(fep); 4663 if (fep->reg_phy) 4664 regulator_disable(fep->reg_phy); 4665 4666 if (of_phy_is_fixed_link(np)) 4667 of_phy_deregister_fixed_link(np); 4668 of_node_put(fep->phy_node); 4669 4670 /* After pm_runtime_get_sync() failed, the clks are still off, so skip 4671 * disabling them again. 4672 */ 4673 if (ret >= 0) { 4674 clk_disable_unprepare(fep->clk_ahb); 4675 clk_disable_unprepare(fep->clk_ipg); 4676 } 4677 pm_runtime_put_noidle(&pdev->dev); 4678 pm_runtime_disable(&pdev->dev); 4679 4680 fec_enet_deinit(ndev); 4681 free_netdev(ndev); 4682 } 4683 4684 static int fec_suspend(struct device *dev) 4685 { 4686 struct net_device *ndev = dev_get_drvdata(dev); 4687 struct fec_enet_private *fep = netdev_priv(ndev); 4688 int ret; 4689 4690 rtnl_lock(); 4691 if (netif_running(ndev)) { 4692 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 4693 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 4694 phy_stop(ndev->phydev); 4695 napi_disable(&fep->napi); 4696 netif_tx_lock_bh(ndev); 4697 netif_device_detach(ndev); 4698 netif_tx_unlock_bh(ndev); 4699 fec_stop(ndev); 4700 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4701 fec_irqs_disable(ndev); 4702 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 4703 } else { 4704 fec_irqs_disable_except_wakeup(ndev); 4705 if (fep->wake_irq > 0) { 4706 disable_irq(fep->wake_irq); 4707 enable_irq_wake(fep->wake_irq); 4708 } 4709 fec_enet_stop_mode(fep, true); 4710 } 4711 /* It's safe to disable clocks since interrupts are masked */ 4712 fec_enet_clk_enable(ndev, false); 4713 4714 fep->rpm_active = !pm_runtime_status_suspended(dev); 4715 if (fep->rpm_active) { 4716 ret = pm_runtime_force_suspend(dev); 4717 if (ret < 0) { 4718 rtnl_unlock(); 4719 return ret; 4720 } 4721 } 4722 } 4723 rtnl_unlock(); 4724 4725 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4726 regulator_disable(fep->reg_phy); 4727 4728 /* SOC supply clock to phy, when clock is disabled, phy link down 4729 * SOC control phy regulator, when regulator is disabled, phy link down 4730 */ 4731 if (fep->clk_enet_out || fep->reg_phy) 4732 fep->link = 0; 4733 4734 return 0; 4735 } 4736 4737 static int fec_resume(struct device *dev) 4738 { 4739 struct net_device *ndev = dev_get_drvdata(dev); 4740 struct fec_enet_private *fep = netdev_priv(ndev); 4741 int ret; 4742 int val; 4743 4744 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4745 ret = regulator_enable(fep->reg_phy); 4746 if (ret) 4747 return ret; 4748 } 4749 4750 rtnl_lock(); 4751 if (netif_running(ndev)) { 4752 if (fep->rpm_active) 4753 pm_runtime_force_resume(dev); 4754 4755 ret = fec_enet_clk_enable(ndev, true); 4756 if (ret) { 4757 rtnl_unlock(); 4758 goto failed_clk; 4759 } 4760 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 4761 fec_enet_stop_mode(fep, false); 4762 if (fep->wake_irq) { 4763 disable_irq_wake(fep->wake_irq); 4764 enable_irq(fep->wake_irq); 4765 } 4766 4767 val = readl(fep->hwp + FEC_ECNTRL); 4768 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 4769 writel(val, fep->hwp + FEC_ECNTRL); 4770 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 4771 } else { 4772 pinctrl_pm_select_default_state(&fep->pdev->dev); 4773 } 4774 fec_restart(ndev); 4775 netif_tx_lock_bh(ndev); 4776 netif_device_attach(ndev); 4777 netif_tx_unlock_bh(ndev); 4778 napi_enable(&fep->napi); 4779 phy_init_hw(ndev->phydev); 4780 phy_start(ndev->phydev); 4781 } 4782 rtnl_unlock(); 4783 4784 return 0; 4785 4786 failed_clk: 4787 if (fep->reg_phy) 4788 regulator_disable(fep->reg_phy); 4789 return ret; 4790 } 4791 4792 static int fec_runtime_suspend(struct device *dev) 4793 { 4794 struct net_device *ndev = dev_get_drvdata(dev); 4795 struct fec_enet_private *fep = netdev_priv(ndev); 4796 4797 clk_disable_unprepare(fep->clk_ahb); 4798 clk_disable_unprepare(fep->clk_ipg); 4799 4800 return 0; 4801 } 4802 4803 static int fec_runtime_resume(struct device *dev) 4804 { 4805 struct net_device *ndev = dev_get_drvdata(dev); 4806 struct fec_enet_private *fep = netdev_priv(ndev); 4807 int ret; 4808 4809 ret = clk_prepare_enable(fep->clk_ahb); 4810 if (ret) 4811 return ret; 4812 ret = clk_prepare_enable(fep->clk_ipg); 4813 if (ret) 4814 goto failed_clk_ipg; 4815 4816 return 0; 4817 4818 failed_clk_ipg: 4819 clk_disable_unprepare(fep->clk_ahb); 4820 return ret; 4821 } 4822 4823 static const struct dev_pm_ops fec_pm_ops = { 4824 SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 4825 RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 4826 }; 4827 4828 static struct platform_driver fec_driver = { 4829 .driver = { 4830 .name = DRIVER_NAME, 4831 .pm = pm_ptr(&fec_pm_ops), 4832 .of_match_table = fec_dt_ids, 4833 .suppress_bind_attrs = true, 4834 }, 4835 .id_table = fec_devtype, 4836 .probe = fec_probe, 4837 .remove = fec_drv_remove, 4838 }; 4839 4840 module_platform_driver(fec_driver); 4841 4842 MODULE_DESCRIPTION("NXP Fast Ethernet Controller (FEC) driver"); 4843 MODULE_LICENSE("GPL"); 4844