1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/string.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/ptrace.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/slab.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/netdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <net/ip.h> 41 #include <net/page_pool/helpers.h> 42 #include <net/selftests.h> 43 #include <net/tso.h> 44 #include <linux/tcp.h> 45 #include <linux/udp.h> 46 #include <linux/icmp.h> 47 #include <linux/spinlock.h> 48 #include <linux/workqueue.h> 49 #include <linux/bitops.h> 50 #include <linux/io.h> 51 #include <linux/irq.h> 52 #include <linux/clk.h> 53 #include <linux/crc32.h> 54 #include <linux/platform_device.h> 55 #include <linux/mdio.h> 56 #include <linux/phy.h> 57 #include <linux/fec.h> 58 #include <linux/of.h> 59 #include <linux/of_device.h> 60 #include <linux/of_mdio.h> 61 #include <linux/of_net.h> 62 #include <linux/regulator/consumer.h> 63 #include <linux/if_vlan.h> 64 #include <linux/pinctrl/consumer.h> 65 #include <linux/gpio/consumer.h> 66 #include <linux/prefetch.h> 67 #include <linux/mfd/syscon.h> 68 #include <linux/regmap.h> 69 #include <soc/imx/cpuidle.h> 70 #include <linux/filter.h> 71 #include <linux/bpf.h> 72 #include <linux/bpf_trace.h> 73 74 #include <asm/cacheflush.h> 75 76 #include "fec.h" 77 78 static void set_multicast_list(struct net_device *ndev); 79 static void fec_enet_itr_coal_set(struct net_device *ndev); 80 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 81 int cpu, struct xdp_buff *xdp, 82 u32 dma_sync_len); 83 84 #define DRIVER_NAME "fec" 85 86 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 87 88 /* Pause frame feild and FIFO threshold */ 89 #define FEC_ENET_FCE (1 << 5) 90 #define FEC_ENET_RSEM_V 0x84 91 #define FEC_ENET_RSFL_V 16 92 #define FEC_ENET_RAEM_V 0x8 93 #define FEC_ENET_RAFL_V 0x8 94 #define FEC_ENET_OPD_V 0xFFF0 95 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 96 97 #define FEC_ENET_XDP_PASS 0 98 #define FEC_ENET_XDP_CONSUMED BIT(0) 99 #define FEC_ENET_XDP_TX BIT(1) 100 #define FEC_ENET_XDP_REDIR BIT(2) 101 102 struct fec_devinfo { 103 u32 quirks; 104 }; 105 106 static const struct fec_devinfo fec_imx25_info = { 107 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 108 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_HAS_MDIO_C45, 109 }; 110 111 static const struct fec_devinfo fec_imx27_info = { 112 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG | 113 FEC_QUIRK_HAS_MDIO_C45, 114 }; 115 116 static const struct fec_devinfo fec_imx28_info = { 117 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 118 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 119 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 120 FEC_QUIRK_NO_HARD_RESET | FEC_QUIRK_HAS_MDIO_C45, 121 }; 122 123 static const struct fec_devinfo fec_imx6q_info = { 124 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 125 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 126 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 127 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII | 128 FEC_QUIRK_HAS_PMQOS | FEC_QUIRK_HAS_MDIO_C45, 129 }; 130 131 static const struct fec_devinfo fec_mvf600_info = { 132 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC | 133 FEC_QUIRK_HAS_MDIO_C45, 134 }; 135 136 static const struct fec_devinfo fec_imx6x_info = { 137 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 138 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 139 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 140 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 141 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 142 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 143 FEC_QUIRK_HAS_MDIO_C45, 144 }; 145 146 static const struct fec_devinfo fec_imx6ul_info = { 147 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 148 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 149 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 150 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 151 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII | 152 FEC_QUIRK_HAS_MDIO_C45, 153 }; 154 155 static const struct fec_devinfo fec_imx8mq_info = { 156 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 157 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 158 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 159 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 160 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 161 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 162 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2 | 163 FEC_QUIRK_HAS_MDIO_C45, 164 }; 165 166 static const struct fec_devinfo fec_imx8qm_info = { 167 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 168 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 169 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 170 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 171 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 172 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 173 FEC_QUIRK_DELAYED_CLKS_SUPPORT | FEC_QUIRK_HAS_MDIO_C45, 174 }; 175 176 static const struct fec_devinfo fec_s32v234_info = { 177 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 178 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 179 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 180 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 181 FEC_QUIRK_HAS_MDIO_C45, 182 }; 183 184 static struct platform_device_id fec_devtype[] = { 185 { 186 /* keep it for coldfire */ 187 .name = DRIVER_NAME, 188 .driver_data = 0, 189 }, { 190 .name = "imx25-fec", 191 .driver_data = (kernel_ulong_t)&fec_imx25_info, 192 }, { 193 .name = "imx27-fec", 194 .driver_data = (kernel_ulong_t)&fec_imx27_info, 195 }, { 196 .name = "imx28-fec", 197 .driver_data = (kernel_ulong_t)&fec_imx28_info, 198 }, { 199 .name = "imx6q-fec", 200 .driver_data = (kernel_ulong_t)&fec_imx6q_info, 201 }, { 202 .name = "mvf600-fec", 203 .driver_data = (kernel_ulong_t)&fec_mvf600_info, 204 }, { 205 .name = "imx6sx-fec", 206 .driver_data = (kernel_ulong_t)&fec_imx6x_info, 207 }, { 208 .name = "imx6ul-fec", 209 .driver_data = (kernel_ulong_t)&fec_imx6ul_info, 210 }, { 211 .name = "imx8mq-fec", 212 .driver_data = (kernel_ulong_t)&fec_imx8mq_info, 213 }, { 214 .name = "imx8qm-fec", 215 .driver_data = (kernel_ulong_t)&fec_imx8qm_info, 216 }, { 217 .name = "s32v234-fec", 218 .driver_data = (kernel_ulong_t)&fec_s32v234_info, 219 }, { 220 /* sentinel */ 221 } 222 }; 223 MODULE_DEVICE_TABLE(platform, fec_devtype); 224 225 enum imx_fec_type { 226 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 227 IMX27_FEC, /* runs on i.mx27/35/51 */ 228 IMX28_FEC, 229 IMX6Q_FEC, 230 MVF600_FEC, 231 IMX6SX_FEC, 232 IMX6UL_FEC, 233 IMX8MQ_FEC, 234 IMX8QM_FEC, 235 S32V234_FEC, 236 }; 237 238 static const struct of_device_id fec_dt_ids[] = { 239 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 240 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 241 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 242 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 243 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 244 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 245 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 246 { .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], }, 247 { .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], }, 248 { .compatible = "fsl,s32v234-fec", .data = &fec_devtype[S32V234_FEC], }, 249 { /* sentinel */ } 250 }; 251 MODULE_DEVICE_TABLE(of, fec_dt_ids); 252 253 static unsigned char macaddr[ETH_ALEN]; 254 module_param_array(macaddr, byte, NULL, 0); 255 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 256 257 #if defined(CONFIG_M5272) 258 /* 259 * Some hardware gets it MAC address out of local flash memory. 260 * if this is non-zero then assume it is the address to get MAC from. 261 */ 262 #if defined(CONFIG_NETtel) 263 #define FEC_FLASHMAC 0xf0006006 264 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 265 #define FEC_FLASHMAC 0xf0006000 266 #elif defined(CONFIG_CANCam) 267 #define FEC_FLASHMAC 0xf0020000 268 #elif defined (CONFIG_M5272C3) 269 #define FEC_FLASHMAC (0xffe04000 + 4) 270 #elif defined(CONFIG_MOD5272) 271 #define FEC_FLASHMAC 0xffc0406b 272 #else 273 #define FEC_FLASHMAC 0 274 #endif 275 #endif /* CONFIG_M5272 */ 276 277 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 278 * 279 * 2048 byte skbufs are allocated. However, alignment requirements 280 * varies between FEC variants. Worst case is 64, so round down by 64. 281 */ 282 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 283 #define PKT_MINBUF_SIZE 64 284 285 /* FEC receive acceleration */ 286 #define FEC_RACC_IPDIS (1 << 1) 287 #define FEC_RACC_PRODIS (1 << 2) 288 #define FEC_RACC_SHIFT16 BIT(7) 289 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 290 291 /* MIB Control Register */ 292 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 293 294 /* 295 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 296 * size bits. Other FEC hardware does not, so we need to take that into 297 * account when setting it. 298 */ 299 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 300 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 301 defined(CONFIG_ARM64) 302 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 303 #else 304 #define OPT_FRAME_SIZE 0 305 #endif 306 307 /* FEC MII MMFR bits definition */ 308 #define FEC_MMFR_ST (1 << 30) 309 #define FEC_MMFR_ST_C45 (0) 310 #define FEC_MMFR_OP_READ (2 << 28) 311 #define FEC_MMFR_OP_READ_C45 (3 << 28) 312 #define FEC_MMFR_OP_WRITE (1 << 28) 313 #define FEC_MMFR_OP_ADDR_WRITE (0) 314 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 315 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 316 #define FEC_MMFR_TA (2 << 16) 317 #define FEC_MMFR_DATA(v) (v & 0xffff) 318 /* FEC ECR bits definition */ 319 #define FEC_ECR_MAGICEN (1 << 2) 320 #define FEC_ECR_SLEEP (1 << 3) 321 322 #define FEC_MII_TIMEOUT 30000 /* us */ 323 324 /* Transmitter timeout */ 325 #define TX_TIMEOUT (2 * HZ) 326 327 #define FEC_PAUSE_FLAG_AUTONEG 0x1 328 #define FEC_PAUSE_FLAG_ENABLE 0x2 329 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 330 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 331 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 332 333 /* Max number of allowed TCP segments for software TSO */ 334 #define FEC_MAX_TSO_SEGS 100 335 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 336 337 #define IS_TSO_HEADER(txq, addr) \ 338 ((addr >= txq->tso_hdrs_dma) && \ 339 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 340 341 static int mii_cnt; 342 343 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 344 struct bufdesc_prop *bd) 345 { 346 return (bdp >= bd->last) ? bd->base 347 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 348 } 349 350 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 351 struct bufdesc_prop *bd) 352 { 353 return (bdp <= bd->base) ? bd->last 354 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 355 } 356 357 static int fec_enet_get_bd_index(struct bufdesc *bdp, 358 struct bufdesc_prop *bd) 359 { 360 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 361 } 362 363 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 364 { 365 int entries; 366 367 entries = (((const char *)txq->dirty_tx - 368 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 369 370 return entries >= 0 ? entries : entries + txq->bd.ring_size; 371 } 372 373 static void swap_buffer(void *bufaddr, int len) 374 { 375 int i; 376 unsigned int *buf = bufaddr; 377 378 for (i = 0; i < len; i += 4, buf++) 379 swab32s(buf); 380 } 381 382 static void fec_dump(struct net_device *ndev) 383 { 384 struct fec_enet_private *fep = netdev_priv(ndev); 385 struct bufdesc *bdp; 386 struct fec_enet_priv_tx_q *txq; 387 int index = 0; 388 389 netdev_info(ndev, "TX ring dump\n"); 390 pr_info("Nr SC addr len SKB\n"); 391 392 txq = fep->tx_queue[0]; 393 bdp = txq->bd.base; 394 395 do { 396 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 397 index, 398 bdp == txq->bd.cur ? 'S' : ' ', 399 bdp == txq->dirty_tx ? 'H' : ' ', 400 fec16_to_cpu(bdp->cbd_sc), 401 fec32_to_cpu(bdp->cbd_bufaddr), 402 fec16_to_cpu(bdp->cbd_datlen), 403 txq->tx_buf[index].buf_p); 404 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 405 index++; 406 } while (bdp != txq->bd.base); 407 } 408 409 static inline bool is_ipv4_pkt(struct sk_buff *skb) 410 { 411 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 412 } 413 414 static int 415 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 416 { 417 /* Only run for packets requiring a checksum. */ 418 if (skb->ip_summed != CHECKSUM_PARTIAL) 419 return 0; 420 421 if (unlikely(skb_cow_head(skb, 0))) 422 return -1; 423 424 if (is_ipv4_pkt(skb)) 425 ip_hdr(skb)->check = 0; 426 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 427 428 return 0; 429 } 430 431 static int 432 fec_enet_create_page_pool(struct fec_enet_private *fep, 433 struct fec_enet_priv_rx_q *rxq, int size) 434 { 435 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 436 struct page_pool_params pp_params = { 437 .order = 0, 438 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 439 .pool_size = size, 440 .nid = dev_to_node(&fep->pdev->dev), 441 .dev = &fep->pdev->dev, 442 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 443 .offset = FEC_ENET_XDP_HEADROOM, 444 .max_len = FEC_ENET_RX_FRSIZE, 445 }; 446 int err; 447 448 rxq->page_pool = page_pool_create(&pp_params); 449 if (IS_ERR(rxq->page_pool)) { 450 err = PTR_ERR(rxq->page_pool); 451 rxq->page_pool = NULL; 452 return err; 453 } 454 455 err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0); 456 if (err < 0) 457 goto err_free_pp; 458 459 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 460 rxq->page_pool); 461 if (err) 462 goto err_unregister_rxq; 463 464 return 0; 465 466 err_unregister_rxq: 467 xdp_rxq_info_unreg(&rxq->xdp_rxq); 468 err_free_pp: 469 page_pool_destroy(rxq->page_pool); 470 rxq->page_pool = NULL; 471 return err; 472 } 473 474 static struct bufdesc * 475 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 476 struct sk_buff *skb, 477 struct net_device *ndev) 478 { 479 struct fec_enet_private *fep = netdev_priv(ndev); 480 struct bufdesc *bdp = txq->bd.cur; 481 struct bufdesc_ex *ebdp; 482 int nr_frags = skb_shinfo(skb)->nr_frags; 483 int frag, frag_len; 484 unsigned short status; 485 unsigned int estatus = 0; 486 skb_frag_t *this_frag; 487 unsigned int index; 488 void *bufaddr; 489 dma_addr_t addr; 490 int i; 491 492 for (frag = 0; frag < nr_frags; frag++) { 493 this_frag = &skb_shinfo(skb)->frags[frag]; 494 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 495 ebdp = (struct bufdesc_ex *)bdp; 496 497 status = fec16_to_cpu(bdp->cbd_sc); 498 status &= ~BD_ENET_TX_STATS; 499 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 500 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 501 502 /* Handle the last BD specially */ 503 if (frag == nr_frags - 1) { 504 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 505 if (fep->bufdesc_ex) { 506 estatus |= BD_ENET_TX_INT; 507 if (unlikely(skb_shinfo(skb)->tx_flags & 508 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 509 estatus |= BD_ENET_TX_TS; 510 } 511 } 512 513 if (fep->bufdesc_ex) { 514 if (fep->quirks & FEC_QUIRK_HAS_AVB) 515 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 516 if (skb->ip_summed == CHECKSUM_PARTIAL) 517 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 518 519 ebdp->cbd_bdu = 0; 520 ebdp->cbd_esc = cpu_to_fec32(estatus); 521 } 522 523 bufaddr = skb_frag_address(this_frag); 524 525 index = fec_enet_get_bd_index(bdp, &txq->bd); 526 if (((unsigned long) bufaddr) & fep->tx_align || 527 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 528 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 529 bufaddr = txq->tx_bounce[index]; 530 531 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 532 swap_buffer(bufaddr, frag_len); 533 } 534 535 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 536 DMA_TO_DEVICE); 537 if (dma_mapping_error(&fep->pdev->dev, addr)) { 538 if (net_ratelimit()) 539 netdev_err(ndev, "Tx DMA memory map failed\n"); 540 goto dma_mapping_error; 541 } 542 543 bdp->cbd_bufaddr = cpu_to_fec32(addr); 544 bdp->cbd_datlen = cpu_to_fec16(frag_len); 545 /* Make sure the updates to rest of the descriptor are 546 * performed before transferring ownership. 547 */ 548 wmb(); 549 bdp->cbd_sc = cpu_to_fec16(status); 550 } 551 552 return bdp; 553 dma_mapping_error: 554 bdp = txq->bd.cur; 555 for (i = 0; i < frag; i++) { 556 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 557 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 558 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 559 } 560 return ERR_PTR(-ENOMEM); 561 } 562 563 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 564 struct sk_buff *skb, struct net_device *ndev) 565 { 566 struct fec_enet_private *fep = netdev_priv(ndev); 567 int nr_frags = skb_shinfo(skb)->nr_frags; 568 struct bufdesc *bdp, *last_bdp; 569 void *bufaddr; 570 dma_addr_t addr; 571 unsigned short status; 572 unsigned short buflen; 573 unsigned int estatus = 0; 574 unsigned int index; 575 int entries_free; 576 577 entries_free = fec_enet_get_free_txdesc_num(txq); 578 if (entries_free < MAX_SKB_FRAGS + 1) { 579 dev_kfree_skb_any(skb); 580 if (net_ratelimit()) 581 netdev_err(ndev, "NOT enough BD for SG!\n"); 582 return NETDEV_TX_OK; 583 } 584 585 /* Protocol checksum off-load for TCP and UDP. */ 586 if (fec_enet_clear_csum(skb, ndev)) { 587 dev_kfree_skb_any(skb); 588 return NETDEV_TX_OK; 589 } 590 591 /* Fill in a Tx ring entry */ 592 bdp = txq->bd.cur; 593 last_bdp = bdp; 594 status = fec16_to_cpu(bdp->cbd_sc); 595 status &= ~BD_ENET_TX_STATS; 596 597 /* Set buffer length and buffer pointer */ 598 bufaddr = skb->data; 599 buflen = skb_headlen(skb); 600 601 index = fec_enet_get_bd_index(bdp, &txq->bd); 602 if (((unsigned long) bufaddr) & fep->tx_align || 603 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 604 memcpy(txq->tx_bounce[index], skb->data, buflen); 605 bufaddr = txq->tx_bounce[index]; 606 607 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 608 swap_buffer(bufaddr, buflen); 609 } 610 611 /* Push the data cache so the CPM does not get stale memory data. */ 612 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 613 if (dma_mapping_error(&fep->pdev->dev, addr)) { 614 dev_kfree_skb_any(skb); 615 if (net_ratelimit()) 616 netdev_err(ndev, "Tx DMA memory map failed\n"); 617 return NETDEV_TX_OK; 618 } 619 620 if (nr_frags) { 621 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 622 if (IS_ERR(last_bdp)) { 623 dma_unmap_single(&fep->pdev->dev, addr, 624 buflen, DMA_TO_DEVICE); 625 dev_kfree_skb_any(skb); 626 return NETDEV_TX_OK; 627 } 628 } else { 629 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 630 if (fep->bufdesc_ex) { 631 estatus = BD_ENET_TX_INT; 632 if (unlikely(skb_shinfo(skb)->tx_flags & 633 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 634 estatus |= BD_ENET_TX_TS; 635 } 636 } 637 bdp->cbd_bufaddr = cpu_to_fec32(addr); 638 bdp->cbd_datlen = cpu_to_fec16(buflen); 639 640 if (fep->bufdesc_ex) { 641 642 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 643 644 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 645 fep->hwts_tx_en)) 646 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 647 648 if (fep->quirks & FEC_QUIRK_HAS_AVB) 649 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 650 651 if (skb->ip_summed == CHECKSUM_PARTIAL) 652 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 653 654 ebdp->cbd_bdu = 0; 655 ebdp->cbd_esc = cpu_to_fec32(estatus); 656 } 657 658 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 659 /* Save skb pointer */ 660 txq->tx_buf[index].buf_p = skb; 661 662 /* Make sure the updates to rest of the descriptor are performed before 663 * transferring ownership. 664 */ 665 wmb(); 666 667 /* Send it on its way. Tell FEC it's ready, interrupt when done, 668 * it's the last BD of the frame, and to put the CRC on the end. 669 */ 670 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 671 bdp->cbd_sc = cpu_to_fec16(status); 672 673 /* If this was the last BD in the ring, start at the beginning again. */ 674 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 675 676 skb_tx_timestamp(skb); 677 678 /* Make sure the update to bdp is performed before txq->bd.cur. */ 679 wmb(); 680 txq->bd.cur = bdp; 681 682 /* Trigger transmission start */ 683 writel(0, txq->bd.reg_desc_active); 684 685 return 0; 686 } 687 688 static int 689 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 690 struct net_device *ndev, 691 struct bufdesc *bdp, int index, char *data, 692 int size, bool last_tcp, bool is_last) 693 { 694 struct fec_enet_private *fep = netdev_priv(ndev); 695 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 696 unsigned short status; 697 unsigned int estatus = 0; 698 dma_addr_t addr; 699 700 status = fec16_to_cpu(bdp->cbd_sc); 701 status &= ~BD_ENET_TX_STATS; 702 703 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 704 705 if (((unsigned long) data) & fep->tx_align || 706 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 707 memcpy(txq->tx_bounce[index], data, size); 708 data = txq->tx_bounce[index]; 709 710 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 711 swap_buffer(data, size); 712 } 713 714 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 715 if (dma_mapping_error(&fep->pdev->dev, addr)) { 716 dev_kfree_skb_any(skb); 717 if (net_ratelimit()) 718 netdev_err(ndev, "Tx DMA memory map failed\n"); 719 return NETDEV_TX_OK; 720 } 721 722 bdp->cbd_datlen = cpu_to_fec16(size); 723 bdp->cbd_bufaddr = cpu_to_fec32(addr); 724 725 if (fep->bufdesc_ex) { 726 if (fep->quirks & FEC_QUIRK_HAS_AVB) 727 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 728 if (skb->ip_summed == CHECKSUM_PARTIAL) 729 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 730 ebdp->cbd_bdu = 0; 731 ebdp->cbd_esc = cpu_to_fec32(estatus); 732 } 733 734 /* Handle the last BD specially */ 735 if (last_tcp) 736 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 737 if (is_last) { 738 status |= BD_ENET_TX_INTR; 739 if (fep->bufdesc_ex) 740 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 741 } 742 743 bdp->cbd_sc = cpu_to_fec16(status); 744 745 return 0; 746 } 747 748 static int 749 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 750 struct sk_buff *skb, struct net_device *ndev, 751 struct bufdesc *bdp, int index) 752 { 753 struct fec_enet_private *fep = netdev_priv(ndev); 754 int hdr_len = skb_tcp_all_headers(skb); 755 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 756 void *bufaddr; 757 unsigned long dmabuf; 758 unsigned short status; 759 unsigned int estatus = 0; 760 761 status = fec16_to_cpu(bdp->cbd_sc); 762 status &= ~BD_ENET_TX_STATS; 763 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 764 765 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 766 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 767 if (((unsigned long)bufaddr) & fep->tx_align || 768 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 769 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 770 bufaddr = txq->tx_bounce[index]; 771 772 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 773 swap_buffer(bufaddr, hdr_len); 774 775 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 776 hdr_len, DMA_TO_DEVICE); 777 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 778 dev_kfree_skb_any(skb); 779 if (net_ratelimit()) 780 netdev_err(ndev, "Tx DMA memory map failed\n"); 781 return NETDEV_TX_OK; 782 } 783 } 784 785 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 786 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 787 788 if (fep->bufdesc_ex) { 789 if (fep->quirks & FEC_QUIRK_HAS_AVB) 790 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 791 if (skb->ip_summed == CHECKSUM_PARTIAL) 792 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 793 ebdp->cbd_bdu = 0; 794 ebdp->cbd_esc = cpu_to_fec32(estatus); 795 } 796 797 bdp->cbd_sc = cpu_to_fec16(status); 798 799 return 0; 800 } 801 802 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 803 struct sk_buff *skb, 804 struct net_device *ndev) 805 { 806 struct fec_enet_private *fep = netdev_priv(ndev); 807 int hdr_len, total_len, data_left; 808 struct bufdesc *bdp = txq->bd.cur; 809 struct tso_t tso; 810 unsigned int index = 0; 811 int ret; 812 813 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 814 dev_kfree_skb_any(skb); 815 if (net_ratelimit()) 816 netdev_err(ndev, "NOT enough BD for TSO!\n"); 817 return NETDEV_TX_OK; 818 } 819 820 /* Protocol checksum off-load for TCP and UDP. */ 821 if (fec_enet_clear_csum(skb, ndev)) { 822 dev_kfree_skb_any(skb); 823 return NETDEV_TX_OK; 824 } 825 826 /* Initialize the TSO handler, and prepare the first payload */ 827 hdr_len = tso_start(skb, &tso); 828 829 total_len = skb->len - hdr_len; 830 while (total_len > 0) { 831 char *hdr; 832 833 index = fec_enet_get_bd_index(bdp, &txq->bd); 834 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 835 total_len -= data_left; 836 837 /* prepare packet headers: MAC + IP + TCP */ 838 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 839 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 840 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 841 if (ret) 842 goto err_release; 843 844 while (data_left > 0) { 845 int size; 846 847 size = min_t(int, tso.size, data_left); 848 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 849 index = fec_enet_get_bd_index(bdp, &txq->bd); 850 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 851 bdp, index, 852 tso.data, size, 853 size == data_left, 854 total_len == 0); 855 if (ret) 856 goto err_release; 857 858 data_left -= size; 859 tso_build_data(skb, &tso, size); 860 } 861 862 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 863 } 864 865 /* Save skb pointer */ 866 txq->tx_buf[index].buf_p = skb; 867 868 skb_tx_timestamp(skb); 869 txq->bd.cur = bdp; 870 871 /* Trigger transmission start */ 872 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 873 !readl(txq->bd.reg_desc_active) || 874 !readl(txq->bd.reg_desc_active) || 875 !readl(txq->bd.reg_desc_active) || 876 !readl(txq->bd.reg_desc_active)) 877 writel(0, txq->bd.reg_desc_active); 878 879 return 0; 880 881 err_release: 882 /* TODO: Release all used data descriptors for TSO */ 883 return ret; 884 } 885 886 static netdev_tx_t 887 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 888 { 889 struct fec_enet_private *fep = netdev_priv(ndev); 890 int entries_free; 891 unsigned short queue; 892 struct fec_enet_priv_tx_q *txq; 893 struct netdev_queue *nq; 894 int ret; 895 896 queue = skb_get_queue_mapping(skb); 897 txq = fep->tx_queue[queue]; 898 nq = netdev_get_tx_queue(ndev, queue); 899 900 if (skb_is_gso(skb)) 901 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 902 else 903 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 904 if (ret) 905 return ret; 906 907 entries_free = fec_enet_get_free_txdesc_num(txq); 908 if (entries_free <= txq->tx_stop_threshold) 909 netif_tx_stop_queue(nq); 910 911 return NETDEV_TX_OK; 912 } 913 914 /* Init RX & TX buffer descriptors 915 */ 916 static void fec_enet_bd_init(struct net_device *dev) 917 { 918 struct fec_enet_private *fep = netdev_priv(dev); 919 struct fec_enet_priv_tx_q *txq; 920 struct fec_enet_priv_rx_q *rxq; 921 struct bufdesc *bdp; 922 unsigned int i; 923 unsigned int q; 924 925 for (q = 0; q < fep->num_rx_queues; q++) { 926 /* Initialize the receive buffer descriptors. */ 927 rxq = fep->rx_queue[q]; 928 bdp = rxq->bd.base; 929 930 for (i = 0; i < rxq->bd.ring_size; i++) { 931 932 /* Initialize the BD for every fragment in the page. */ 933 if (bdp->cbd_bufaddr) 934 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 935 else 936 bdp->cbd_sc = cpu_to_fec16(0); 937 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 938 } 939 940 /* Set the last buffer to wrap */ 941 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 942 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 943 944 rxq->bd.cur = rxq->bd.base; 945 } 946 947 for (q = 0; q < fep->num_tx_queues; q++) { 948 /* ...and the same for transmit */ 949 txq = fep->tx_queue[q]; 950 bdp = txq->bd.base; 951 txq->bd.cur = bdp; 952 953 for (i = 0; i < txq->bd.ring_size; i++) { 954 /* Initialize the BD for every fragment in the page. */ 955 bdp->cbd_sc = cpu_to_fec16(0); 956 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 957 if (bdp->cbd_bufaddr && 958 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 959 dma_unmap_single(&fep->pdev->dev, 960 fec32_to_cpu(bdp->cbd_bufaddr), 961 fec16_to_cpu(bdp->cbd_datlen), 962 DMA_TO_DEVICE); 963 if (txq->tx_buf[i].buf_p) 964 dev_kfree_skb_any(txq->tx_buf[i].buf_p); 965 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 966 if (bdp->cbd_bufaddr) 967 dma_unmap_single(&fep->pdev->dev, 968 fec32_to_cpu(bdp->cbd_bufaddr), 969 fec16_to_cpu(bdp->cbd_datlen), 970 DMA_TO_DEVICE); 971 972 if (txq->tx_buf[i].buf_p) 973 xdp_return_frame(txq->tx_buf[i].buf_p); 974 } else { 975 struct page *page = txq->tx_buf[i].buf_p; 976 977 if (page) 978 page_pool_put_page(page->pp, page, 0, false); 979 } 980 981 txq->tx_buf[i].buf_p = NULL; 982 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 983 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 984 bdp->cbd_bufaddr = cpu_to_fec32(0); 985 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 986 } 987 988 /* Set the last buffer to wrap */ 989 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 990 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 991 txq->dirty_tx = bdp; 992 } 993 } 994 995 static void fec_enet_active_rxring(struct net_device *ndev) 996 { 997 struct fec_enet_private *fep = netdev_priv(ndev); 998 int i; 999 1000 for (i = 0; i < fep->num_rx_queues; i++) 1001 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 1002 } 1003 1004 static void fec_enet_enable_ring(struct net_device *ndev) 1005 { 1006 struct fec_enet_private *fep = netdev_priv(ndev); 1007 struct fec_enet_priv_tx_q *txq; 1008 struct fec_enet_priv_rx_q *rxq; 1009 int i; 1010 1011 for (i = 0; i < fep->num_rx_queues; i++) { 1012 rxq = fep->rx_queue[i]; 1013 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 1014 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 1015 1016 /* enable DMA1/2 */ 1017 if (i) 1018 writel(RCMR_MATCHEN | RCMR_CMP(i), 1019 fep->hwp + FEC_RCMR(i)); 1020 } 1021 1022 for (i = 0; i < fep->num_tx_queues; i++) { 1023 txq = fep->tx_queue[i]; 1024 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 1025 1026 /* enable DMA1/2 */ 1027 if (i) 1028 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 1029 fep->hwp + FEC_DMA_CFG(i)); 1030 } 1031 } 1032 1033 /* 1034 * This function is called to start or restart the FEC during a link 1035 * change, transmit timeout, or to reconfigure the FEC. The network 1036 * packet processing for this device must be stopped before this call. 1037 */ 1038 static void 1039 fec_restart(struct net_device *ndev) 1040 { 1041 struct fec_enet_private *fep = netdev_priv(ndev); 1042 u32 temp_mac[2]; 1043 u32 rcntl = OPT_FRAME_SIZE | 0x04; 1044 u32 ecntl = 0x2; /* ETHEREN */ 1045 1046 /* Whack a reset. We should wait for this. 1047 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1048 * instead of reset MAC itself. 1049 */ 1050 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || 1051 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 1052 writel(0, fep->hwp + FEC_ECNTRL); 1053 } else { 1054 writel(1, fep->hwp + FEC_ECNTRL); 1055 udelay(10); 1056 } 1057 1058 /* 1059 * enet-mac reset will reset mac address registers too, 1060 * so need to reconfigure it. 1061 */ 1062 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 1063 writel((__force u32)cpu_to_be32(temp_mac[0]), 1064 fep->hwp + FEC_ADDR_LOW); 1065 writel((__force u32)cpu_to_be32(temp_mac[1]), 1066 fep->hwp + FEC_ADDR_HIGH); 1067 1068 /* Clear any outstanding interrupt, except MDIO. */ 1069 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 1070 1071 fec_enet_bd_init(ndev); 1072 1073 fec_enet_enable_ring(ndev); 1074 1075 /* Enable MII mode */ 1076 if (fep->full_duplex == DUPLEX_FULL) { 1077 /* FD enable */ 1078 writel(0x04, fep->hwp + FEC_X_CNTRL); 1079 } else { 1080 /* No Rcv on Xmit */ 1081 rcntl |= 0x02; 1082 writel(0x0, fep->hwp + FEC_X_CNTRL); 1083 } 1084 1085 /* Set MII speed */ 1086 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1087 1088 #if !defined(CONFIG_M5272) 1089 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1090 u32 val = readl(fep->hwp + FEC_RACC); 1091 1092 /* align IP header */ 1093 val |= FEC_RACC_SHIFT16; 1094 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1095 /* set RX checksum */ 1096 val |= FEC_RACC_OPTIONS; 1097 else 1098 val &= ~FEC_RACC_OPTIONS; 1099 writel(val, fep->hwp + FEC_RACC); 1100 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1101 } 1102 #endif 1103 1104 /* 1105 * The phy interface and speed need to get configured 1106 * differently on enet-mac. 1107 */ 1108 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1109 /* Enable flow control and length check */ 1110 rcntl |= 0x40000000 | 0x00000020; 1111 1112 /* RGMII, RMII or MII */ 1113 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1114 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1115 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1116 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1117 rcntl |= (1 << 6); 1118 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1119 rcntl |= (1 << 8); 1120 else 1121 rcntl &= ~(1 << 8); 1122 1123 /* 1G, 100M or 10M */ 1124 if (ndev->phydev) { 1125 if (ndev->phydev->speed == SPEED_1000) 1126 ecntl |= (1 << 5); 1127 else if (ndev->phydev->speed == SPEED_100) 1128 rcntl &= ~(1 << 9); 1129 else 1130 rcntl |= (1 << 9); 1131 } 1132 } else { 1133 #ifdef FEC_MIIGSK_ENR 1134 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1135 u32 cfgr; 1136 /* disable the gasket and wait */ 1137 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1138 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1139 udelay(1); 1140 1141 /* 1142 * configure the gasket: 1143 * RMII, 50 MHz, no loopback, no echo 1144 * MII, 25 MHz, no loopback, no echo 1145 */ 1146 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1147 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1148 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1149 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1150 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1151 1152 /* re-enable the gasket */ 1153 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1154 } 1155 #endif 1156 } 1157 1158 #if !defined(CONFIG_M5272) 1159 /* enable pause frame*/ 1160 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1161 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1162 ndev->phydev && ndev->phydev->pause)) { 1163 rcntl |= FEC_ENET_FCE; 1164 1165 /* set FIFO threshold parameter to reduce overrun */ 1166 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1167 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1168 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1169 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1170 1171 /* OPD */ 1172 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1173 } else { 1174 rcntl &= ~FEC_ENET_FCE; 1175 } 1176 #endif /* !defined(CONFIG_M5272) */ 1177 1178 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1179 1180 /* Setup multicast filter. */ 1181 set_multicast_list(ndev); 1182 #ifndef CONFIG_M5272 1183 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1184 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1185 #endif 1186 1187 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1188 /* enable ENET endian swap */ 1189 ecntl |= (1 << 8); 1190 /* enable ENET store and forward mode */ 1191 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1192 } 1193 1194 if (fep->bufdesc_ex) 1195 ecntl |= (1 << 4); 1196 1197 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1198 fep->rgmii_txc_dly) 1199 ecntl |= FEC_ENET_TXC_DLY; 1200 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1201 fep->rgmii_rxc_dly) 1202 ecntl |= FEC_ENET_RXC_DLY; 1203 1204 #ifndef CONFIG_M5272 1205 /* Enable the MIB statistic event counters */ 1206 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1207 #endif 1208 1209 /* And last, enable the transmit and receive processing */ 1210 writel(ecntl, fep->hwp + FEC_ECNTRL); 1211 fec_enet_active_rxring(ndev); 1212 1213 if (fep->bufdesc_ex) 1214 fec_ptp_start_cyclecounter(ndev); 1215 1216 /* Enable interrupts we wish to service */ 1217 if (fep->link) 1218 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1219 else 1220 writel(0, fep->hwp + FEC_IMASK); 1221 1222 /* Init the interrupt coalescing */ 1223 if (fep->quirks & FEC_QUIRK_HAS_COALESCE) 1224 fec_enet_itr_coal_set(ndev); 1225 } 1226 1227 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep) 1228 { 1229 if (!(of_machine_is_compatible("fsl,imx8qm") || 1230 of_machine_is_compatible("fsl,imx8qxp") || 1231 of_machine_is_compatible("fsl,imx8dxl"))) 1232 return 0; 1233 1234 return imx_scu_get_handle(&fep->ipc_handle); 1235 } 1236 1237 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled) 1238 { 1239 struct device_node *np = fep->pdev->dev.of_node; 1240 u32 rsrc_id, val; 1241 int idx; 1242 1243 if (!np || !fep->ipc_handle) 1244 return; 1245 1246 idx = of_alias_get_id(np, "ethernet"); 1247 if (idx < 0) 1248 idx = 0; 1249 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0; 1250 1251 val = enabled ? 1 : 0; 1252 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val); 1253 } 1254 1255 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1256 { 1257 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1258 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1259 1260 if (stop_gpr->gpr) { 1261 if (enabled) 1262 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1263 BIT(stop_gpr->bit), 1264 BIT(stop_gpr->bit)); 1265 else 1266 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1267 BIT(stop_gpr->bit), 0); 1268 } else if (pdata && pdata->sleep_mode_enable) { 1269 pdata->sleep_mode_enable(enabled); 1270 } else { 1271 fec_enet_ipg_stop_set(fep, enabled); 1272 } 1273 } 1274 1275 static void fec_irqs_disable(struct net_device *ndev) 1276 { 1277 struct fec_enet_private *fep = netdev_priv(ndev); 1278 1279 writel(0, fep->hwp + FEC_IMASK); 1280 } 1281 1282 static void fec_irqs_disable_except_wakeup(struct net_device *ndev) 1283 { 1284 struct fec_enet_private *fep = netdev_priv(ndev); 1285 1286 writel(0, fep->hwp + FEC_IMASK); 1287 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1288 } 1289 1290 static void 1291 fec_stop(struct net_device *ndev) 1292 { 1293 struct fec_enet_private *fep = netdev_priv(ndev); 1294 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1295 u32 val; 1296 1297 /* We cannot expect a graceful transmit stop without link !!! */ 1298 if (fep->link) { 1299 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1300 udelay(10); 1301 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1302 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1303 } 1304 1305 /* Whack a reset. We should wait for this. 1306 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1307 * instead of reset MAC itself. 1308 */ 1309 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1310 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 1311 writel(0, fep->hwp + FEC_ECNTRL); 1312 } else { 1313 writel(1, fep->hwp + FEC_ECNTRL); 1314 udelay(10); 1315 } 1316 } else { 1317 val = readl(fep->hwp + FEC_ECNTRL); 1318 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1319 writel(val, fep->hwp + FEC_ECNTRL); 1320 } 1321 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1322 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1323 1324 /* We have to keep ENET enabled to have MII interrupt stay working */ 1325 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1326 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1327 writel(2, fep->hwp + FEC_ECNTRL); 1328 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1329 } 1330 } 1331 1332 1333 static void 1334 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1335 { 1336 struct fec_enet_private *fep = netdev_priv(ndev); 1337 1338 fec_dump(ndev); 1339 1340 ndev->stats.tx_errors++; 1341 1342 schedule_work(&fep->tx_timeout_work); 1343 } 1344 1345 static void fec_enet_timeout_work(struct work_struct *work) 1346 { 1347 struct fec_enet_private *fep = 1348 container_of(work, struct fec_enet_private, tx_timeout_work); 1349 struct net_device *ndev = fep->netdev; 1350 1351 rtnl_lock(); 1352 if (netif_device_present(ndev) || netif_running(ndev)) { 1353 napi_disable(&fep->napi); 1354 netif_tx_lock_bh(ndev); 1355 fec_restart(ndev); 1356 netif_tx_wake_all_queues(ndev); 1357 netif_tx_unlock_bh(ndev); 1358 napi_enable(&fep->napi); 1359 } 1360 rtnl_unlock(); 1361 } 1362 1363 static void 1364 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1365 struct skb_shared_hwtstamps *hwtstamps) 1366 { 1367 unsigned long flags; 1368 u64 ns; 1369 1370 spin_lock_irqsave(&fep->tmreg_lock, flags); 1371 ns = timecounter_cyc2time(&fep->tc, ts); 1372 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1373 1374 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1375 hwtstamps->hwtstamp = ns_to_ktime(ns); 1376 } 1377 1378 static void 1379 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id, int budget) 1380 { 1381 struct fec_enet_private *fep; 1382 struct xdp_frame *xdpf; 1383 struct bufdesc *bdp; 1384 unsigned short status; 1385 struct sk_buff *skb; 1386 struct fec_enet_priv_tx_q *txq; 1387 struct netdev_queue *nq; 1388 int index = 0; 1389 int entries_free; 1390 struct page *page; 1391 int frame_len; 1392 1393 fep = netdev_priv(ndev); 1394 1395 txq = fep->tx_queue[queue_id]; 1396 /* get next bdp of dirty_tx */ 1397 nq = netdev_get_tx_queue(ndev, queue_id); 1398 bdp = txq->dirty_tx; 1399 1400 /* get next bdp of dirty_tx */ 1401 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1402 1403 while (bdp != READ_ONCE(txq->bd.cur)) { 1404 /* Order the load of bd.cur and cbd_sc */ 1405 rmb(); 1406 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1407 if (status & BD_ENET_TX_READY) 1408 break; 1409 1410 index = fec_enet_get_bd_index(bdp, &txq->bd); 1411 1412 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1413 skb = txq->tx_buf[index].buf_p; 1414 if (bdp->cbd_bufaddr && 1415 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1416 dma_unmap_single(&fep->pdev->dev, 1417 fec32_to_cpu(bdp->cbd_bufaddr), 1418 fec16_to_cpu(bdp->cbd_datlen), 1419 DMA_TO_DEVICE); 1420 bdp->cbd_bufaddr = cpu_to_fec32(0); 1421 if (!skb) 1422 goto tx_buf_done; 1423 } else { 1424 /* Tx processing cannot call any XDP (or page pool) APIs if 1425 * the "budget" is 0. Because NAPI is called with budget of 1426 * 0 (such as netpoll) indicates we may be in an IRQ context, 1427 * however, we can't use the page pool from IRQ context. 1428 */ 1429 if (unlikely(!budget)) 1430 break; 1431 1432 if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1433 xdpf = txq->tx_buf[index].buf_p; 1434 if (bdp->cbd_bufaddr) 1435 dma_unmap_single(&fep->pdev->dev, 1436 fec32_to_cpu(bdp->cbd_bufaddr), 1437 fec16_to_cpu(bdp->cbd_datlen), 1438 DMA_TO_DEVICE); 1439 } else { 1440 page = txq->tx_buf[index].buf_p; 1441 } 1442 1443 bdp->cbd_bufaddr = cpu_to_fec32(0); 1444 if (unlikely(!txq->tx_buf[index].buf_p)) { 1445 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1446 goto tx_buf_done; 1447 } 1448 1449 frame_len = fec16_to_cpu(bdp->cbd_datlen); 1450 } 1451 1452 /* Check for errors. */ 1453 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1454 BD_ENET_TX_RL | BD_ENET_TX_UN | 1455 BD_ENET_TX_CSL)) { 1456 ndev->stats.tx_errors++; 1457 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1458 ndev->stats.tx_heartbeat_errors++; 1459 if (status & BD_ENET_TX_LC) /* Late collision */ 1460 ndev->stats.tx_window_errors++; 1461 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1462 ndev->stats.tx_aborted_errors++; 1463 if (status & BD_ENET_TX_UN) /* Underrun */ 1464 ndev->stats.tx_fifo_errors++; 1465 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1466 ndev->stats.tx_carrier_errors++; 1467 } else { 1468 ndev->stats.tx_packets++; 1469 1470 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) 1471 ndev->stats.tx_bytes += skb->len; 1472 else 1473 ndev->stats.tx_bytes += frame_len; 1474 } 1475 1476 /* Deferred means some collisions occurred during transmit, 1477 * but we eventually sent the packet OK. 1478 */ 1479 if (status & BD_ENET_TX_DEF) 1480 ndev->stats.collisions++; 1481 1482 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1483 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1484 * are to time stamp the packet, so we still need to check time 1485 * stamping enabled flag. 1486 */ 1487 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1488 fep->hwts_tx_en) && fep->bufdesc_ex) { 1489 struct skb_shared_hwtstamps shhwtstamps; 1490 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1491 1492 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1493 skb_tstamp_tx(skb, &shhwtstamps); 1494 } 1495 1496 /* Free the sk buffer associated with this last transmit */ 1497 napi_consume_skb(skb, budget); 1498 } else if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1499 xdp_return_frame_rx_napi(xdpf); 1500 } else { /* recycle pages of XDP_TX frames */ 1501 /* The dma_sync_size = 0 as XDP_TX has already synced DMA for_device */ 1502 page_pool_put_page(page->pp, page, 0, true); 1503 } 1504 1505 txq->tx_buf[index].buf_p = NULL; 1506 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1507 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1508 1509 tx_buf_done: 1510 /* Make sure the update to bdp and tx_buf are performed 1511 * before dirty_tx 1512 */ 1513 wmb(); 1514 txq->dirty_tx = bdp; 1515 1516 /* Update pointer to next buffer descriptor to be transmitted */ 1517 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1518 1519 /* Since we have freed up a buffer, the ring is no longer full 1520 */ 1521 if (netif_tx_queue_stopped(nq)) { 1522 entries_free = fec_enet_get_free_txdesc_num(txq); 1523 if (entries_free >= txq->tx_wake_threshold) 1524 netif_tx_wake_queue(nq); 1525 } 1526 } 1527 1528 /* ERR006358: Keep the transmitter going */ 1529 if (bdp != txq->bd.cur && 1530 readl(txq->bd.reg_desc_active) == 0) 1531 writel(0, txq->bd.reg_desc_active); 1532 } 1533 1534 static void fec_enet_tx(struct net_device *ndev, int budget) 1535 { 1536 struct fec_enet_private *fep = netdev_priv(ndev); 1537 int i; 1538 1539 /* Make sure that AVB queues are processed first. */ 1540 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1541 fec_enet_tx_queue(ndev, i, budget); 1542 } 1543 1544 static void fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq, 1545 struct bufdesc *bdp, int index) 1546 { 1547 struct page *new_page; 1548 dma_addr_t phys_addr; 1549 1550 new_page = page_pool_dev_alloc_pages(rxq->page_pool); 1551 WARN_ON(!new_page); 1552 rxq->rx_skb_info[index].page = new_page; 1553 1554 rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM; 1555 phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM; 1556 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 1557 } 1558 1559 static u32 1560 fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog, 1561 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int cpu) 1562 { 1563 unsigned int sync, len = xdp->data_end - xdp->data; 1564 u32 ret = FEC_ENET_XDP_PASS; 1565 struct page *page; 1566 int err; 1567 u32 act; 1568 1569 act = bpf_prog_run_xdp(prog, xdp); 1570 1571 /* Due xdp_adjust_tail and xdp_adjust_head: DMA sync for_device cover 1572 * max len CPU touch 1573 */ 1574 sync = xdp->data_end - xdp->data; 1575 sync = max(sync, len); 1576 1577 switch (act) { 1578 case XDP_PASS: 1579 rxq->stats[RX_XDP_PASS]++; 1580 ret = FEC_ENET_XDP_PASS; 1581 break; 1582 1583 case XDP_REDIRECT: 1584 rxq->stats[RX_XDP_REDIRECT]++; 1585 err = xdp_do_redirect(fep->netdev, xdp, prog); 1586 if (!err) { 1587 ret = FEC_ENET_XDP_REDIR; 1588 } else { 1589 ret = FEC_ENET_XDP_CONSUMED; 1590 page = virt_to_head_page(xdp->data); 1591 page_pool_put_page(rxq->page_pool, page, sync, true); 1592 } 1593 break; 1594 1595 case XDP_TX: 1596 err = fec_enet_xdp_tx_xmit(fep, cpu, xdp, sync); 1597 if (unlikely(err)) { 1598 ret = FEC_ENET_XDP_CONSUMED; 1599 page = virt_to_head_page(xdp->data); 1600 page_pool_put_page(rxq->page_pool, page, sync, true); 1601 trace_xdp_exception(fep->netdev, prog, act); 1602 } else { 1603 ret = FEC_ENET_XDP_TX; 1604 } 1605 break; 1606 1607 default: 1608 bpf_warn_invalid_xdp_action(fep->netdev, prog, act); 1609 fallthrough; 1610 1611 case XDP_ABORTED: 1612 fallthrough; /* handle aborts by dropping packet */ 1613 1614 case XDP_DROP: 1615 rxq->stats[RX_XDP_DROP]++; 1616 ret = FEC_ENET_XDP_CONSUMED; 1617 page = virt_to_head_page(xdp->data); 1618 page_pool_put_page(rxq->page_pool, page, sync, true); 1619 break; 1620 } 1621 1622 return ret; 1623 } 1624 1625 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1626 * When we update through the ring, if the next incoming buffer has 1627 * not been given to the system, we just set the empty indicator, 1628 * effectively tossing the packet. 1629 */ 1630 static int 1631 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1632 { 1633 struct fec_enet_private *fep = netdev_priv(ndev); 1634 struct fec_enet_priv_rx_q *rxq; 1635 struct bufdesc *bdp; 1636 unsigned short status; 1637 struct sk_buff *skb; 1638 ushort pkt_len; 1639 __u8 *data; 1640 int pkt_received = 0; 1641 struct bufdesc_ex *ebdp = NULL; 1642 bool vlan_packet_rcvd = false; 1643 u16 vlan_tag; 1644 int index = 0; 1645 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1646 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 1647 u32 ret, xdp_result = FEC_ENET_XDP_PASS; 1648 u32 data_start = FEC_ENET_XDP_HEADROOM; 1649 int cpu = smp_processor_id(); 1650 struct xdp_buff xdp; 1651 struct page *page; 1652 u32 sub_len = 4; 1653 1654 #if !defined(CONFIG_M5272) 1655 /*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of 1656 * FEC_RACC_SHIFT16 is set by default in the probe function. 1657 */ 1658 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1659 data_start += 2; 1660 sub_len += 2; 1661 } 1662 #endif 1663 1664 #ifdef CONFIG_M532x 1665 flush_cache_all(); 1666 #endif 1667 rxq = fep->rx_queue[queue_id]; 1668 1669 /* First, grab all of the stats for the incoming packet. 1670 * These get messed up if we get called due to a busy condition. 1671 */ 1672 bdp = rxq->bd.cur; 1673 xdp_init_buff(&xdp, PAGE_SIZE, &rxq->xdp_rxq); 1674 1675 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1676 1677 if (pkt_received >= budget) 1678 break; 1679 pkt_received++; 1680 1681 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT); 1682 1683 /* Check for errors. */ 1684 status ^= BD_ENET_RX_LAST; 1685 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1686 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1687 BD_ENET_RX_CL)) { 1688 ndev->stats.rx_errors++; 1689 if (status & BD_ENET_RX_OV) { 1690 /* FIFO overrun */ 1691 ndev->stats.rx_fifo_errors++; 1692 goto rx_processing_done; 1693 } 1694 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1695 | BD_ENET_RX_LAST)) { 1696 /* Frame too long or too short. */ 1697 ndev->stats.rx_length_errors++; 1698 if (status & BD_ENET_RX_LAST) 1699 netdev_err(ndev, "rcv is not +last\n"); 1700 } 1701 if (status & BD_ENET_RX_CR) /* CRC Error */ 1702 ndev->stats.rx_crc_errors++; 1703 /* Report late collisions as a frame error. */ 1704 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1705 ndev->stats.rx_frame_errors++; 1706 goto rx_processing_done; 1707 } 1708 1709 /* Process the incoming frame. */ 1710 ndev->stats.rx_packets++; 1711 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1712 ndev->stats.rx_bytes += pkt_len; 1713 1714 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1715 page = rxq->rx_skb_info[index].page; 1716 dma_sync_single_for_cpu(&fep->pdev->dev, 1717 fec32_to_cpu(bdp->cbd_bufaddr), 1718 pkt_len, 1719 DMA_FROM_DEVICE); 1720 prefetch(page_address(page)); 1721 fec_enet_update_cbd(rxq, bdp, index); 1722 1723 if (xdp_prog) { 1724 xdp_buff_clear_frags_flag(&xdp); 1725 /* subtract 16bit shift and FCS */ 1726 xdp_prepare_buff(&xdp, page_address(page), 1727 data_start, pkt_len - sub_len, false); 1728 ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, cpu); 1729 xdp_result |= ret; 1730 if (ret != FEC_ENET_XDP_PASS) 1731 goto rx_processing_done; 1732 } 1733 1734 /* The packet length includes FCS, but we don't want to 1735 * include that when passing upstream as it messes up 1736 * bridging applications. 1737 */ 1738 skb = build_skb(page_address(page), PAGE_SIZE); 1739 if (unlikely(!skb)) { 1740 page_pool_recycle_direct(rxq->page_pool, page); 1741 ndev->stats.rx_dropped++; 1742 1743 netdev_err_once(ndev, "build_skb failed!\n"); 1744 goto rx_processing_done; 1745 } 1746 1747 skb_reserve(skb, data_start); 1748 skb_put(skb, pkt_len - sub_len); 1749 skb_mark_for_recycle(skb); 1750 1751 if (unlikely(need_swap)) { 1752 data = page_address(page) + FEC_ENET_XDP_HEADROOM; 1753 swap_buffer(data, pkt_len); 1754 } 1755 data = skb->data; 1756 1757 /* Extract the enhanced buffer descriptor */ 1758 ebdp = NULL; 1759 if (fep->bufdesc_ex) 1760 ebdp = (struct bufdesc_ex *)bdp; 1761 1762 /* If this is a VLAN packet remove the VLAN Tag */ 1763 vlan_packet_rcvd = false; 1764 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1765 fep->bufdesc_ex && 1766 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1767 /* Push and remove the vlan tag */ 1768 struct vlan_hdr *vlan_header = 1769 (struct vlan_hdr *) (data + ETH_HLEN); 1770 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1771 1772 vlan_packet_rcvd = true; 1773 1774 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1775 skb_pull(skb, VLAN_HLEN); 1776 } 1777 1778 skb->protocol = eth_type_trans(skb, ndev); 1779 1780 /* Get receive timestamp from the skb */ 1781 if (fep->hwts_rx_en && fep->bufdesc_ex) 1782 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1783 skb_hwtstamps(skb)); 1784 1785 if (fep->bufdesc_ex && 1786 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1787 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1788 /* don't check it */ 1789 skb->ip_summed = CHECKSUM_UNNECESSARY; 1790 } else { 1791 skb_checksum_none_assert(skb); 1792 } 1793 } 1794 1795 /* Handle received VLAN packets */ 1796 if (vlan_packet_rcvd) 1797 __vlan_hwaccel_put_tag(skb, 1798 htons(ETH_P_8021Q), 1799 vlan_tag); 1800 1801 skb_record_rx_queue(skb, queue_id); 1802 napi_gro_receive(&fep->napi, skb); 1803 1804 rx_processing_done: 1805 /* Clear the status flags for this buffer */ 1806 status &= ~BD_ENET_RX_STATS; 1807 1808 /* Mark the buffer empty */ 1809 status |= BD_ENET_RX_EMPTY; 1810 1811 if (fep->bufdesc_ex) { 1812 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1813 1814 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1815 ebdp->cbd_prot = 0; 1816 ebdp->cbd_bdu = 0; 1817 } 1818 /* Make sure the updates to rest of the descriptor are 1819 * performed before transferring ownership. 1820 */ 1821 wmb(); 1822 bdp->cbd_sc = cpu_to_fec16(status); 1823 1824 /* Update BD pointer to next entry */ 1825 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1826 1827 /* Doing this here will keep the FEC running while we process 1828 * incoming frames. On a heavily loaded network, we should be 1829 * able to keep up at the expense of system resources. 1830 */ 1831 writel(0, rxq->bd.reg_desc_active); 1832 } 1833 rxq->bd.cur = bdp; 1834 1835 if (xdp_result & FEC_ENET_XDP_REDIR) 1836 xdp_do_flush_map(); 1837 1838 return pkt_received; 1839 } 1840 1841 static int fec_enet_rx(struct net_device *ndev, int budget) 1842 { 1843 struct fec_enet_private *fep = netdev_priv(ndev); 1844 int i, done = 0; 1845 1846 /* Make sure that AVB queues are processed first. */ 1847 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1848 done += fec_enet_rx_queue(ndev, budget - done, i); 1849 1850 return done; 1851 } 1852 1853 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1854 { 1855 uint int_events; 1856 1857 int_events = readl(fep->hwp + FEC_IEVENT); 1858 1859 /* Don't clear MDIO events, we poll for those */ 1860 int_events &= ~FEC_ENET_MII; 1861 1862 writel(int_events, fep->hwp + FEC_IEVENT); 1863 1864 return int_events != 0; 1865 } 1866 1867 static irqreturn_t 1868 fec_enet_interrupt(int irq, void *dev_id) 1869 { 1870 struct net_device *ndev = dev_id; 1871 struct fec_enet_private *fep = netdev_priv(ndev); 1872 irqreturn_t ret = IRQ_NONE; 1873 1874 if (fec_enet_collect_events(fep) && fep->link) { 1875 ret = IRQ_HANDLED; 1876 1877 if (napi_schedule_prep(&fep->napi)) { 1878 /* Disable interrupts */ 1879 writel(0, fep->hwp + FEC_IMASK); 1880 __napi_schedule(&fep->napi); 1881 } 1882 } 1883 1884 return ret; 1885 } 1886 1887 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1888 { 1889 struct net_device *ndev = napi->dev; 1890 struct fec_enet_private *fep = netdev_priv(ndev); 1891 int done = 0; 1892 1893 do { 1894 done += fec_enet_rx(ndev, budget - done); 1895 fec_enet_tx(ndev, budget); 1896 } while ((done < budget) && fec_enet_collect_events(fep)); 1897 1898 if (done < budget) { 1899 napi_complete_done(napi, done); 1900 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1901 } 1902 1903 return done; 1904 } 1905 1906 /* ------------------------------------------------------------------------- */ 1907 static int fec_get_mac(struct net_device *ndev) 1908 { 1909 struct fec_enet_private *fep = netdev_priv(ndev); 1910 unsigned char *iap, tmpaddr[ETH_ALEN]; 1911 int ret; 1912 1913 /* 1914 * try to get mac address in following order: 1915 * 1916 * 1) module parameter via kernel command line in form 1917 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1918 */ 1919 iap = macaddr; 1920 1921 /* 1922 * 2) from device tree data 1923 */ 1924 if (!is_valid_ether_addr(iap)) { 1925 struct device_node *np = fep->pdev->dev.of_node; 1926 if (np) { 1927 ret = of_get_mac_address(np, tmpaddr); 1928 if (!ret) 1929 iap = tmpaddr; 1930 else if (ret == -EPROBE_DEFER) 1931 return ret; 1932 } 1933 } 1934 1935 /* 1936 * 3) from flash or fuse (via platform data) 1937 */ 1938 if (!is_valid_ether_addr(iap)) { 1939 #ifdef CONFIG_M5272 1940 if (FEC_FLASHMAC) 1941 iap = (unsigned char *)FEC_FLASHMAC; 1942 #else 1943 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1944 1945 if (pdata) 1946 iap = (unsigned char *)&pdata->mac; 1947 #endif 1948 } 1949 1950 /* 1951 * 4) FEC mac registers set by bootloader 1952 */ 1953 if (!is_valid_ether_addr(iap)) { 1954 *((__be32 *) &tmpaddr[0]) = 1955 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1956 *((__be16 *) &tmpaddr[4]) = 1957 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1958 iap = &tmpaddr[0]; 1959 } 1960 1961 /* 1962 * 5) random mac address 1963 */ 1964 if (!is_valid_ether_addr(iap)) { 1965 /* Report it and use a random ethernet address instead */ 1966 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 1967 eth_hw_addr_random(ndev); 1968 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 1969 ndev->dev_addr); 1970 return 0; 1971 } 1972 1973 /* Adjust MAC if using macaddr */ 1974 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0); 1975 1976 return 0; 1977 } 1978 1979 /* ------------------------------------------------------------------------- */ 1980 1981 /* 1982 * Phy section 1983 */ 1984 static void fec_enet_adjust_link(struct net_device *ndev) 1985 { 1986 struct fec_enet_private *fep = netdev_priv(ndev); 1987 struct phy_device *phy_dev = ndev->phydev; 1988 int status_change = 0; 1989 1990 /* 1991 * If the netdev is down, or is going down, we're not interested 1992 * in link state events, so just mark our idea of the link as down 1993 * and ignore the event. 1994 */ 1995 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1996 fep->link = 0; 1997 } else if (phy_dev->link) { 1998 if (!fep->link) { 1999 fep->link = phy_dev->link; 2000 status_change = 1; 2001 } 2002 2003 if (fep->full_duplex != phy_dev->duplex) { 2004 fep->full_duplex = phy_dev->duplex; 2005 status_change = 1; 2006 } 2007 2008 if (phy_dev->speed != fep->speed) { 2009 fep->speed = phy_dev->speed; 2010 status_change = 1; 2011 } 2012 2013 /* if any of the above changed restart the FEC */ 2014 if (status_change) { 2015 napi_disable(&fep->napi); 2016 netif_tx_lock_bh(ndev); 2017 fec_restart(ndev); 2018 netif_tx_wake_all_queues(ndev); 2019 netif_tx_unlock_bh(ndev); 2020 napi_enable(&fep->napi); 2021 } 2022 } else { 2023 if (fep->link) { 2024 napi_disable(&fep->napi); 2025 netif_tx_lock_bh(ndev); 2026 fec_stop(ndev); 2027 netif_tx_unlock_bh(ndev); 2028 napi_enable(&fep->napi); 2029 fep->link = phy_dev->link; 2030 status_change = 1; 2031 } 2032 } 2033 2034 if (status_change) 2035 phy_print_status(phy_dev); 2036 } 2037 2038 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 2039 { 2040 uint ievent; 2041 int ret; 2042 2043 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 2044 ievent & FEC_ENET_MII, 2, 30000); 2045 2046 if (!ret) 2047 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2048 2049 return ret; 2050 } 2051 2052 static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) 2053 { 2054 struct fec_enet_private *fep = bus->priv; 2055 struct device *dev = &fep->pdev->dev; 2056 int ret = 0, frame_start, frame_addr, frame_op; 2057 2058 ret = pm_runtime_resume_and_get(dev); 2059 if (ret < 0) 2060 return ret; 2061 2062 /* C22 read */ 2063 frame_op = FEC_MMFR_OP_READ; 2064 frame_start = FEC_MMFR_ST; 2065 frame_addr = regnum; 2066 2067 /* start a read op */ 2068 writel(frame_start | frame_op | 2069 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2070 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2071 2072 /* wait for end of transfer */ 2073 ret = fec_enet_mdio_wait(fep); 2074 if (ret) { 2075 netdev_err(fep->netdev, "MDIO read timeout\n"); 2076 goto out; 2077 } 2078 2079 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2080 2081 out: 2082 pm_runtime_mark_last_busy(dev); 2083 pm_runtime_put_autosuspend(dev); 2084 2085 return ret; 2086 } 2087 2088 static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id, 2089 int devad, int regnum) 2090 { 2091 struct fec_enet_private *fep = bus->priv; 2092 struct device *dev = &fep->pdev->dev; 2093 int ret = 0, frame_start, frame_op; 2094 2095 ret = pm_runtime_resume_and_get(dev); 2096 if (ret < 0) 2097 return ret; 2098 2099 frame_start = FEC_MMFR_ST_C45; 2100 2101 /* write address */ 2102 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2103 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2104 FEC_MMFR_TA | (regnum & 0xFFFF), 2105 fep->hwp + FEC_MII_DATA); 2106 2107 /* wait for end of transfer */ 2108 ret = fec_enet_mdio_wait(fep); 2109 if (ret) { 2110 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2111 goto out; 2112 } 2113 2114 frame_op = FEC_MMFR_OP_READ_C45; 2115 2116 /* start a read op */ 2117 writel(frame_start | frame_op | 2118 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2119 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2120 2121 /* wait for end of transfer */ 2122 ret = fec_enet_mdio_wait(fep); 2123 if (ret) { 2124 netdev_err(fep->netdev, "MDIO read timeout\n"); 2125 goto out; 2126 } 2127 2128 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2129 2130 out: 2131 pm_runtime_mark_last_busy(dev); 2132 pm_runtime_put_autosuspend(dev); 2133 2134 return ret; 2135 } 2136 2137 static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, 2138 u16 value) 2139 { 2140 struct fec_enet_private *fep = bus->priv; 2141 struct device *dev = &fep->pdev->dev; 2142 int ret, frame_start, frame_addr; 2143 2144 ret = pm_runtime_resume_and_get(dev); 2145 if (ret < 0) 2146 return ret; 2147 2148 /* C22 write */ 2149 frame_start = FEC_MMFR_ST; 2150 frame_addr = regnum; 2151 2152 /* start a write op */ 2153 writel(frame_start | FEC_MMFR_OP_WRITE | 2154 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2155 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2156 fep->hwp + FEC_MII_DATA); 2157 2158 /* wait for end of transfer */ 2159 ret = fec_enet_mdio_wait(fep); 2160 if (ret) 2161 netdev_err(fep->netdev, "MDIO write timeout\n"); 2162 2163 pm_runtime_mark_last_busy(dev); 2164 pm_runtime_put_autosuspend(dev); 2165 2166 return ret; 2167 } 2168 2169 static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id, 2170 int devad, int regnum, u16 value) 2171 { 2172 struct fec_enet_private *fep = bus->priv; 2173 struct device *dev = &fep->pdev->dev; 2174 int ret, frame_start; 2175 2176 ret = pm_runtime_resume_and_get(dev); 2177 if (ret < 0) 2178 return ret; 2179 2180 frame_start = FEC_MMFR_ST_C45; 2181 2182 /* write address */ 2183 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2184 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2185 FEC_MMFR_TA | (regnum & 0xFFFF), 2186 fep->hwp + FEC_MII_DATA); 2187 2188 /* wait for end of transfer */ 2189 ret = fec_enet_mdio_wait(fep); 2190 if (ret) { 2191 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2192 goto out; 2193 } 2194 2195 /* start a write op */ 2196 writel(frame_start | FEC_MMFR_OP_WRITE | 2197 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2198 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2199 fep->hwp + FEC_MII_DATA); 2200 2201 /* wait for end of transfer */ 2202 ret = fec_enet_mdio_wait(fep); 2203 if (ret) 2204 netdev_err(fep->netdev, "MDIO write timeout\n"); 2205 2206 out: 2207 pm_runtime_mark_last_busy(dev); 2208 pm_runtime_put_autosuspend(dev); 2209 2210 return ret; 2211 } 2212 2213 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 2214 { 2215 struct fec_enet_private *fep = netdev_priv(ndev); 2216 struct phy_device *phy_dev = ndev->phydev; 2217 2218 if (phy_dev) { 2219 phy_reset_after_clk_enable(phy_dev); 2220 } else if (fep->phy_node) { 2221 /* 2222 * If the PHY still is not bound to the MAC, but there is 2223 * OF PHY node and a matching PHY device instance already, 2224 * use the OF PHY node to obtain the PHY device instance, 2225 * and then use that PHY device instance when triggering 2226 * the PHY reset. 2227 */ 2228 phy_dev = of_phy_find_device(fep->phy_node); 2229 phy_reset_after_clk_enable(phy_dev); 2230 put_device(&phy_dev->mdio.dev); 2231 } 2232 } 2233 2234 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 2235 { 2236 struct fec_enet_private *fep = netdev_priv(ndev); 2237 int ret; 2238 2239 if (enable) { 2240 ret = clk_prepare_enable(fep->clk_enet_out); 2241 if (ret) 2242 return ret; 2243 2244 if (fep->clk_ptp) { 2245 mutex_lock(&fep->ptp_clk_mutex); 2246 ret = clk_prepare_enable(fep->clk_ptp); 2247 if (ret) { 2248 mutex_unlock(&fep->ptp_clk_mutex); 2249 goto failed_clk_ptp; 2250 } else { 2251 fep->ptp_clk_on = true; 2252 } 2253 mutex_unlock(&fep->ptp_clk_mutex); 2254 } 2255 2256 ret = clk_prepare_enable(fep->clk_ref); 2257 if (ret) 2258 goto failed_clk_ref; 2259 2260 ret = clk_prepare_enable(fep->clk_2x_txclk); 2261 if (ret) 2262 goto failed_clk_2x_txclk; 2263 2264 fec_enet_phy_reset_after_clk_enable(ndev); 2265 } else { 2266 clk_disable_unprepare(fep->clk_enet_out); 2267 if (fep->clk_ptp) { 2268 mutex_lock(&fep->ptp_clk_mutex); 2269 clk_disable_unprepare(fep->clk_ptp); 2270 fep->ptp_clk_on = false; 2271 mutex_unlock(&fep->ptp_clk_mutex); 2272 } 2273 clk_disable_unprepare(fep->clk_ref); 2274 clk_disable_unprepare(fep->clk_2x_txclk); 2275 } 2276 2277 return 0; 2278 2279 failed_clk_2x_txclk: 2280 if (fep->clk_ref) 2281 clk_disable_unprepare(fep->clk_ref); 2282 failed_clk_ref: 2283 if (fep->clk_ptp) { 2284 mutex_lock(&fep->ptp_clk_mutex); 2285 clk_disable_unprepare(fep->clk_ptp); 2286 fep->ptp_clk_on = false; 2287 mutex_unlock(&fep->ptp_clk_mutex); 2288 } 2289 failed_clk_ptp: 2290 clk_disable_unprepare(fep->clk_enet_out); 2291 2292 return ret; 2293 } 2294 2295 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep, 2296 struct device_node *np) 2297 { 2298 u32 rgmii_tx_delay, rgmii_rx_delay; 2299 2300 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ 2301 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { 2302 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) { 2303 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); 2304 return -EINVAL; 2305 } else if (rgmii_tx_delay == 2000) { 2306 fep->rgmii_txc_dly = true; 2307 } 2308 } 2309 2310 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */ 2311 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { 2312 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) { 2313 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); 2314 return -EINVAL; 2315 } else if (rgmii_rx_delay == 2000) { 2316 fep->rgmii_rxc_dly = true; 2317 } 2318 } 2319 2320 return 0; 2321 } 2322 2323 static int fec_enet_mii_probe(struct net_device *ndev) 2324 { 2325 struct fec_enet_private *fep = netdev_priv(ndev); 2326 struct phy_device *phy_dev = NULL; 2327 char mdio_bus_id[MII_BUS_ID_SIZE]; 2328 char phy_name[MII_BUS_ID_SIZE + 3]; 2329 int phy_id; 2330 int dev_id = fep->dev_id; 2331 2332 if (fep->phy_node) { 2333 phy_dev = of_phy_connect(ndev, fep->phy_node, 2334 &fec_enet_adjust_link, 0, 2335 fep->phy_interface); 2336 if (!phy_dev) { 2337 netdev_err(ndev, "Unable to connect to phy\n"); 2338 return -ENODEV; 2339 } 2340 } else { 2341 /* check for attached phy */ 2342 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2343 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2344 continue; 2345 if (dev_id--) 2346 continue; 2347 strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2348 break; 2349 } 2350 2351 if (phy_id >= PHY_MAX_ADDR) { 2352 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2353 strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2354 phy_id = 0; 2355 } 2356 2357 snprintf(phy_name, sizeof(phy_name), 2358 PHY_ID_FMT, mdio_bus_id, phy_id); 2359 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2360 fep->phy_interface); 2361 } 2362 2363 if (IS_ERR(phy_dev)) { 2364 netdev_err(ndev, "could not attach to PHY\n"); 2365 return PTR_ERR(phy_dev); 2366 } 2367 2368 /* mask with MAC supported features */ 2369 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2370 phy_set_max_speed(phy_dev, 1000); 2371 phy_remove_link_mode(phy_dev, 2372 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2373 #if !defined(CONFIG_M5272) 2374 phy_support_sym_pause(phy_dev); 2375 #endif 2376 } 2377 else 2378 phy_set_max_speed(phy_dev, 100); 2379 2380 fep->link = 0; 2381 fep->full_duplex = 0; 2382 2383 phy_dev->mac_managed_pm = true; 2384 2385 phy_attached_info(phy_dev); 2386 2387 return 0; 2388 } 2389 2390 static int fec_enet_mii_init(struct platform_device *pdev) 2391 { 2392 static struct mii_bus *fec0_mii_bus; 2393 struct net_device *ndev = platform_get_drvdata(pdev); 2394 struct fec_enet_private *fep = netdev_priv(ndev); 2395 bool suppress_preamble = false; 2396 struct device_node *node; 2397 int err = -ENXIO; 2398 u32 mii_speed, holdtime; 2399 u32 bus_freq; 2400 2401 /* 2402 * The i.MX28 dual fec interfaces are not equal. 2403 * Here are the differences: 2404 * 2405 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2406 * - fec0 acts as the 1588 time master while fec1 is slave 2407 * - external phys can only be configured by fec0 2408 * 2409 * That is to say fec1 can not work independently. It only works 2410 * when fec0 is working. The reason behind this design is that the 2411 * second interface is added primarily for Switch mode. 2412 * 2413 * Because of the last point above, both phys are attached on fec0 2414 * mdio interface in board design, and need to be configured by 2415 * fec0 mii_bus. 2416 */ 2417 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2418 /* fec1 uses fec0 mii_bus */ 2419 if (mii_cnt && fec0_mii_bus) { 2420 fep->mii_bus = fec0_mii_bus; 2421 mii_cnt++; 2422 return 0; 2423 } 2424 return -ENOENT; 2425 } 2426 2427 bus_freq = 2500000; /* 2.5MHz by default */ 2428 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2429 if (node) { 2430 of_property_read_u32(node, "clock-frequency", &bus_freq); 2431 suppress_preamble = of_property_read_bool(node, 2432 "suppress-preamble"); 2433 } 2434 2435 /* 2436 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2437 * 2438 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2439 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2440 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2441 * document. 2442 */ 2443 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2444 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2445 mii_speed--; 2446 if (mii_speed > 63) { 2447 dev_err(&pdev->dev, 2448 "fec clock (%lu) too fast to get right mii speed\n", 2449 clk_get_rate(fep->clk_ipg)); 2450 err = -EINVAL; 2451 goto err_out; 2452 } 2453 2454 /* 2455 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2456 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2457 * versions are RAZ there, so just ignore the difference and write the 2458 * register always. 2459 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2460 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2461 * output. 2462 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2463 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2464 * holdtime cannot result in a value greater than 3. 2465 */ 2466 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2467 2468 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2469 2470 if (suppress_preamble) 2471 fep->phy_speed |= BIT(7); 2472 2473 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2474 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2475 * MII event generation condition: 2476 * - writing MSCR: 2477 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2478 * mscr_reg_data_in[7:0] != 0 2479 * - writing MMFR: 2480 * - mscr[7:0]_not_zero 2481 */ 2482 writel(0, fep->hwp + FEC_MII_DATA); 2483 } 2484 2485 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2486 2487 /* Clear any pending transaction complete indication */ 2488 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2489 2490 fep->mii_bus = mdiobus_alloc(); 2491 if (fep->mii_bus == NULL) { 2492 err = -ENOMEM; 2493 goto err_out; 2494 } 2495 2496 fep->mii_bus->name = "fec_enet_mii_bus"; 2497 fep->mii_bus->read = fec_enet_mdio_read_c22; 2498 fep->mii_bus->write = fec_enet_mdio_write_c22; 2499 if (fep->quirks & FEC_QUIRK_HAS_MDIO_C45) { 2500 fep->mii_bus->read_c45 = fec_enet_mdio_read_c45; 2501 fep->mii_bus->write_c45 = fec_enet_mdio_write_c45; 2502 } 2503 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2504 pdev->name, fep->dev_id + 1); 2505 fep->mii_bus->priv = fep; 2506 fep->mii_bus->parent = &pdev->dev; 2507 2508 err = of_mdiobus_register(fep->mii_bus, node); 2509 if (err) 2510 goto err_out_free_mdiobus; 2511 of_node_put(node); 2512 2513 mii_cnt++; 2514 2515 /* save fec0 mii_bus */ 2516 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2517 fec0_mii_bus = fep->mii_bus; 2518 2519 return 0; 2520 2521 err_out_free_mdiobus: 2522 mdiobus_free(fep->mii_bus); 2523 err_out: 2524 of_node_put(node); 2525 return err; 2526 } 2527 2528 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2529 { 2530 if (--mii_cnt == 0) { 2531 mdiobus_unregister(fep->mii_bus); 2532 mdiobus_free(fep->mii_bus); 2533 } 2534 } 2535 2536 static void fec_enet_get_drvinfo(struct net_device *ndev, 2537 struct ethtool_drvinfo *info) 2538 { 2539 struct fec_enet_private *fep = netdev_priv(ndev); 2540 2541 strscpy(info->driver, fep->pdev->dev.driver->name, 2542 sizeof(info->driver)); 2543 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2544 } 2545 2546 static int fec_enet_get_regs_len(struct net_device *ndev) 2547 { 2548 struct fec_enet_private *fep = netdev_priv(ndev); 2549 struct resource *r; 2550 int s = 0; 2551 2552 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2553 if (r) 2554 s = resource_size(r); 2555 2556 return s; 2557 } 2558 2559 /* List of registers that can be safety be read to dump them with ethtool */ 2560 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2561 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2562 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2563 static __u32 fec_enet_register_version = 2; 2564 static u32 fec_enet_register_offset[] = { 2565 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2566 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2567 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2568 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2569 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2570 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2571 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2572 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2573 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2574 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2575 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2576 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2577 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2578 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2579 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2580 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2581 RMON_T_P_GTE2048, RMON_T_OCTETS, 2582 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2583 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2584 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2585 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2586 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2587 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2588 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2589 RMON_R_P_GTE2048, RMON_R_OCTETS, 2590 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2591 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2592 }; 2593 /* for i.MX6ul */ 2594 static u32 fec_enet_register_offset_6ul[] = { 2595 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2596 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2597 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0, 2598 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, 2599 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0, 2600 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2601 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, 2602 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2603 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2604 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2605 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2606 RMON_T_P_GTE2048, RMON_T_OCTETS, 2607 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2608 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2609 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2610 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2611 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2612 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2613 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2614 RMON_R_P_GTE2048, RMON_R_OCTETS, 2615 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2616 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2617 }; 2618 #else 2619 static __u32 fec_enet_register_version = 1; 2620 static u32 fec_enet_register_offset[] = { 2621 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2622 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2623 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2624 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2625 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2626 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2627 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2628 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2629 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2630 }; 2631 #endif 2632 2633 static void fec_enet_get_regs(struct net_device *ndev, 2634 struct ethtool_regs *regs, void *regbuf) 2635 { 2636 struct fec_enet_private *fep = netdev_priv(ndev); 2637 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2638 struct device *dev = &fep->pdev->dev; 2639 u32 *buf = (u32 *)regbuf; 2640 u32 i, off; 2641 int ret; 2642 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2643 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2644 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2645 u32 *reg_list; 2646 u32 reg_cnt; 2647 2648 if (!of_machine_is_compatible("fsl,imx6ul")) { 2649 reg_list = fec_enet_register_offset; 2650 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2651 } else { 2652 reg_list = fec_enet_register_offset_6ul; 2653 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul); 2654 } 2655 #else 2656 /* coldfire */ 2657 static u32 *reg_list = fec_enet_register_offset; 2658 static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2659 #endif 2660 ret = pm_runtime_resume_and_get(dev); 2661 if (ret < 0) 2662 return; 2663 2664 regs->version = fec_enet_register_version; 2665 2666 memset(buf, 0, regs->len); 2667 2668 for (i = 0; i < reg_cnt; i++) { 2669 off = reg_list[i]; 2670 2671 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2672 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2673 continue; 2674 2675 off >>= 2; 2676 buf[off] = readl(&theregs[off]); 2677 } 2678 2679 pm_runtime_mark_last_busy(dev); 2680 pm_runtime_put_autosuspend(dev); 2681 } 2682 2683 static int fec_enet_get_ts_info(struct net_device *ndev, 2684 struct ethtool_ts_info *info) 2685 { 2686 struct fec_enet_private *fep = netdev_priv(ndev); 2687 2688 if (fep->bufdesc_ex) { 2689 2690 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2691 SOF_TIMESTAMPING_RX_SOFTWARE | 2692 SOF_TIMESTAMPING_SOFTWARE | 2693 SOF_TIMESTAMPING_TX_HARDWARE | 2694 SOF_TIMESTAMPING_RX_HARDWARE | 2695 SOF_TIMESTAMPING_RAW_HARDWARE; 2696 if (fep->ptp_clock) 2697 info->phc_index = ptp_clock_index(fep->ptp_clock); 2698 else 2699 info->phc_index = -1; 2700 2701 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2702 (1 << HWTSTAMP_TX_ON); 2703 2704 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2705 (1 << HWTSTAMP_FILTER_ALL); 2706 return 0; 2707 } else { 2708 return ethtool_op_get_ts_info(ndev, info); 2709 } 2710 } 2711 2712 #if !defined(CONFIG_M5272) 2713 2714 static void fec_enet_get_pauseparam(struct net_device *ndev, 2715 struct ethtool_pauseparam *pause) 2716 { 2717 struct fec_enet_private *fep = netdev_priv(ndev); 2718 2719 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2720 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2721 pause->rx_pause = pause->tx_pause; 2722 } 2723 2724 static int fec_enet_set_pauseparam(struct net_device *ndev, 2725 struct ethtool_pauseparam *pause) 2726 { 2727 struct fec_enet_private *fep = netdev_priv(ndev); 2728 2729 if (!ndev->phydev) 2730 return -ENODEV; 2731 2732 if (pause->tx_pause != pause->rx_pause) { 2733 netdev_info(ndev, 2734 "hardware only support enable/disable both tx and rx"); 2735 return -EINVAL; 2736 } 2737 2738 fep->pause_flag = 0; 2739 2740 /* tx pause must be same as rx pause */ 2741 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2742 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2743 2744 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2745 pause->autoneg); 2746 2747 if (pause->autoneg) { 2748 if (netif_running(ndev)) 2749 fec_stop(ndev); 2750 phy_start_aneg(ndev->phydev); 2751 } 2752 if (netif_running(ndev)) { 2753 napi_disable(&fep->napi); 2754 netif_tx_lock_bh(ndev); 2755 fec_restart(ndev); 2756 netif_tx_wake_all_queues(ndev); 2757 netif_tx_unlock_bh(ndev); 2758 napi_enable(&fep->napi); 2759 } 2760 2761 return 0; 2762 } 2763 2764 static const struct fec_stat { 2765 char name[ETH_GSTRING_LEN]; 2766 u16 offset; 2767 } fec_stats[] = { 2768 /* RMON TX */ 2769 { "tx_dropped", RMON_T_DROP }, 2770 { "tx_packets", RMON_T_PACKETS }, 2771 { "tx_broadcast", RMON_T_BC_PKT }, 2772 { "tx_multicast", RMON_T_MC_PKT }, 2773 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2774 { "tx_undersize", RMON_T_UNDERSIZE }, 2775 { "tx_oversize", RMON_T_OVERSIZE }, 2776 { "tx_fragment", RMON_T_FRAG }, 2777 { "tx_jabber", RMON_T_JAB }, 2778 { "tx_collision", RMON_T_COL }, 2779 { "tx_64byte", RMON_T_P64 }, 2780 { "tx_65to127byte", RMON_T_P65TO127 }, 2781 { "tx_128to255byte", RMON_T_P128TO255 }, 2782 { "tx_256to511byte", RMON_T_P256TO511 }, 2783 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2784 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2785 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2786 { "tx_octets", RMON_T_OCTETS }, 2787 2788 /* IEEE TX */ 2789 { "IEEE_tx_drop", IEEE_T_DROP }, 2790 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2791 { "IEEE_tx_1col", IEEE_T_1COL }, 2792 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2793 { "IEEE_tx_def", IEEE_T_DEF }, 2794 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2795 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2796 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2797 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2798 { "IEEE_tx_sqe", IEEE_T_SQE }, 2799 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2800 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2801 2802 /* RMON RX */ 2803 { "rx_packets", RMON_R_PACKETS }, 2804 { "rx_broadcast", RMON_R_BC_PKT }, 2805 { "rx_multicast", RMON_R_MC_PKT }, 2806 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2807 { "rx_undersize", RMON_R_UNDERSIZE }, 2808 { "rx_oversize", RMON_R_OVERSIZE }, 2809 { "rx_fragment", RMON_R_FRAG }, 2810 { "rx_jabber", RMON_R_JAB }, 2811 { "rx_64byte", RMON_R_P64 }, 2812 { "rx_65to127byte", RMON_R_P65TO127 }, 2813 { "rx_128to255byte", RMON_R_P128TO255 }, 2814 { "rx_256to511byte", RMON_R_P256TO511 }, 2815 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2816 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2817 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2818 { "rx_octets", RMON_R_OCTETS }, 2819 2820 /* IEEE RX */ 2821 { "IEEE_rx_drop", IEEE_R_DROP }, 2822 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2823 { "IEEE_rx_crc", IEEE_R_CRC }, 2824 { "IEEE_rx_align", IEEE_R_ALIGN }, 2825 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2826 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2827 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2828 }; 2829 2830 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2831 2832 static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = { 2833 "rx_xdp_redirect", /* RX_XDP_REDIRECT = 0, */ 2834 "rx_xdp_pass", /* RX_XDP_PASS, */ 2835 "rx_xdp_drop", /* RX_XDP_DROP, */ 2836 "rx_xdp_tx", /* RX_XDP_TX, */ 2837 "rx_xdp_tx_errors", /* RX_XDP_TX_ERRORS, */ 2838 "tx_xdp_xmit", /* TX_XDP_XMIT, */ 2839 "tx_xdp_xmit_errors", /* TX_XDP_XMIT_ERRORS, */ 2840 }; 2841 2842 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2843 { 2844 struct fec_enet_private *fep = netdev_priv(dev); 2845 int i; 2846 2847 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2848 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2849 } 2850 2851 static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data) 2852 { 2853 u64 xdp_stats[XDP_STATS_TOTAL] = { 0 }; 2854 struct fec_enet_priv_rx_q *rxq; 2855 int i, j; 2856 2857 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2858 rxq = fep->rx_queue[i]; 2859 2860 for (j = 0; j < XDP_STATS_TOTAL; j++) 2861 xdp_stats[j] += rxq->stats[j]; 2862 } 2863 2864 memcpy(data, xdp_stats, sizeof(xdp_stats)); 2865 } 2866 2867 static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data) 2868 { 2869 #ifdef CONFIG_PAGE_POOL_STATS 2870 struct page_pool_stats stats = {}; 2871 struct fec_enet_priv_rx_q *rxq; 2872 int i; 2873 2874 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2875 rxq = fep->rx_queue[i]; 2876 2877 if (!rxq->page_pool) 2878 continue; 2879 2880 page_pool_get_stats(rxq->page_pool, &stats); 2881 } 2882 2883 page_pool_ethtool_stats_get(data, &stats); 2884 #endif 2885 } 2886 2887 static void fec_enet_get_ethtool_stats(struct net_device *dev, 2888 struct ethtool_stats *stats, u64 *data) 2889 { 2890 struct fec_enet_private *fep = netdev_priv(dev); 2891 2892 if (netif_running(dev)) 2893 fec_enet_update_ethtool_stats(dev); 2894 2895 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2896 data += FEC_STATS_SIZE / sizeof(u64); 2897 2898 fec_enet_get_xdp_stats(fep, data); 2899 data += XDP_STATS_TOTAL; 2900 2901 fec_enet_page_pool_stats(fep, data); 2902 } 2903 2904 static void fec_enet_get_strings(struct net_device *netdev, 2905 u32 stringset, u8 *data) 2906 { 2907 int i; 2908 switch (stringset) { 2909 case ETH_SS_STATS: 2910 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) { 2911 memcpy(data, fec_stats[i].name, ETH_GSTRING_LEN); 2912 data += ETH_GSTRING_LEN; 2913 } 2914 for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) { 2915 strncpy(data, fec_xdp_stat_strs[i], ETH_GSTRING_LEN); 2916 data += ETH_GSTRING_LEN; 2917 } 2918 page_pool_ethtool_stats_get_strings(data); 2919 2920 break; 2921 case ETH_SS_TEST: 2922 net_selftest_get_strings(data); 2923 break; 2924 } 2925 } 2926 2927 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2928 { 2929 int count; 2930 2931 switch (sset) { 2932 case ETH_SS_STATS: 2933 count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL; 2934 count += page_pool_ethtool_stats_get_count(); 2935 return count; 2936 2937 case ETH_SS_TEST: 2938 return net_selftest_get_count(); 2939 default: 2940 return -EOPNOTSUPP; 2941 } 2942 } 2943 2944 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2945 { 2946 struct fec_enet_private *fep = netdev_priv(dev); 2947 struct fec_enet_priv_rx_q *rxq; 2948 int i, j; 2949 2950 /* Disable MIB statistics counters */ 2951 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2952 2953 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2954 writel(0, fep->hwp + fec_stats[i].offset); 2955 2956 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2957 rxq = fep->rx_queue[i]; 2958 for (j = 0; j < XDP_STATS_TOTAL; j++) 2959 rxq->stats[j] = 0; 2960 } 2961 2962 /* Don't disable MIB statistics counters */ 2963 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2964 } 2965 2966 #else /* !defined(CONFIG_M5272) */ 2967 #define FEC_STATS_SIZE 0 2968 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2969 { 2970 } 2971 2972 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2973 { 2974 } 2975 #endif /* !defined(CONFIG_M5272) */ 2976 2977 /* ITR clock source is enet system clock (clk_ahb). 2978 * TCTT unit is cycle_ns * 64 cycle 2979 * So, the ICTT value = X us / (cycle_ns * 64) 2980 */ 2981 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2982 { 2983 struct fec_enet_private *fep = netdev_priv(ndev); 2984 2985 return us * (fep->itr_clk_rate / 64000) / 1000; 2986 } 2987 2988 /* Set threshold for interrupt coalescing */ 2989 static void fec_enet_itr_coal_set(struct net_device *ndev) 2990 { 2991 struct fec_enet_private *fep = netdev_priv(ndev); 2992 int rx_itr, tx_itr; 2993 2994 /* Must be greater than zero to avoid unpredictable behavior */ 2995 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2996 !fep->tx_time_itr || !fep->tx_pkts_itr) 2997 return; 2998 2999 /* Select enet system clock as Interrupt Coalescing 3000 * timer Clock Source 3001 */ 3002 rx_itr = FEC_ITR_CLK_SEL; 3003 tx_itr = FEC_ITR_CLK_SEL; 3004 3005 /* set ICFT and ICTT */ 3006 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 3007 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 3008 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 3009 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 3010 3011 rx_itr |= FEC_ITR_EN; 3012 tx_itr |= FEC_ITR_EN; 3013 3014 writel(tx_itr, fep->hwp + FEC_TXIC0); 3015 writel(rx_itr, fep->hwp + FEC_RXIC0); 3016 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 3017 writel(tx_itr, fep->hwp + FEC_TXIC1); 3018 writel(rx_itr, fep->hwp + FEC_RXIC1); 3019 writel(tx_itr, fep->hwp + FEC_TXIC2); 3020 writel(rx_itr, fep->hwp + FEC_RXIC2); 3021 } 3022 } 3023 3024 static int fec_enet_get_coalesce(struct net_device *ndev, 3025 struct ethtool_coalesce *ec, 3026 struct kernel_ethtool_coalesce *kernel_coal, 3027 struct netlink_ext_ack *extack) 3028 { 3029 struct fec_enet_private *fep = netdev_priv(ndev); 3030 3031 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3032 return -EOPNOTSUPP; 3033 3034 ec->rx_coalesce_usecs = fep->rx_time_itr; 3035 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 3036 3037 ec->tx_coalesce_usecs = fep->tx_time_itr; 3038 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 3039 3040 return 0; 3041 } 3042 3043 static int fec_enet_set_coalesce(struct net_device *ndev, 3044 struct ethtool_coalesce *ec, 3045 struct kernel_ethtool_coalesce *kernel_coal, 3046 struct netlink_ext_ack *extack) 3047 { 3048 struct fec_enet_private *fep = netdev_priv(ndev); 3049 struct device *dev = &fep->pdev->dev; 3050 unsigned int cycle; 3051 3052 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3053 return -EOPNOTSUPP; 3054 3055 if (ec->rx_max_coalesced_frames > 255) { 3056 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 3057 return -EINVAL; 3058 } 3059 3060 if (ec->tx_max_coalesced_frames > 255) { 3061 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 3062 return -EINVAL; 3063 } 3064 3065 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 3066 if (cycle > 0xFFFF) { 3067 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 3068 return -EINVAL; 3069 } 3070 3071 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 3072 if (cycle > 0xFFFF) { 3073 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 3074 return -EINVAL; 3075 } 3076 3077 fep->rx_time_itr = ec->rx_coalesce_usecs; 3078 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 3079 3080 fep->tx_time_itr = ec->tx_coalesce_usecs; 3081 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 3082 3083 fec_enet_itr_coal_set(ndev); 3084 3085 return 0; 3086 } 3087 3088 /* LPI Sleep Ts count base on tx clk (clk_ref). 3089 * The lpi sleep cnt value = X us / (cycle_ns). 3090 */ 3091 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) 3092 { 3093 struct fec_enet_private *fep = netdev_priv(ndev); 3094 3095 return us * (fep->clk_ref_rate / 1000) / 1000; 3096 } 3097 3098 static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable) 3099 { 3100 struct fec_enet_private *fep = netdev_priv(ndev); 3101 struct ethtool_eee *p = &fep->eee; 3102 unsigned int sleep_cycle, wake_cycle; 3103 int ret = 0; 3104 3105 if (enable) { 3106 ret = phy_init_eee(ndev->phydev, false); 3107 if (ret) 3108 return ret; 3109 3110 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer); 3111 wake_cycle = sleep_cycle; 3112 } else { 3113 sleep_cycle = 0; 3114 wake_cycle = 0; 3115 } 3116 3117 p->tx_lpi_enabled = enable; 3118 p->eee_enabled = enable; 3119 p->eee_active = enable; 3120 3121 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); 3122 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); 3123 3124 return 0; 3125 } 3126 3127 static int 3128 fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *edata) 3129 { 3130 struct fec_enet_private *fep = netdev_priv(ndev); 3131 struct ethtool_eee *p = &fep->eee; 3132 3133 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3134 return -EOPNOTSUPP; 3135 3136 if (!netif_running(ndev)) 3137 return -ENETDOWN; 3138 3139 edata->eee_enabled = p->eee_enabled; 3140 edata->eee_active = p->eee_active; 3141 edata->tx_lpi_timer = p->tx_lpi_timer; 3142 edata->tx_lpi_enabled = p->tx_lpi_enabled; 3143 3144 return phy_ethtool_get_eee(ndev->phydev, edata); 3145 } 3146 3147 static int 3148 fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *edata) 3149 { 3150 struct fec_enet_private *fep = netdev_priv(ndev); 3151 struct ethtool_eee *p = &fep->eee; 3152 int ret = 0; 3153 3154 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3155 return -EOPNOTSUPP; 3156 3157 if (!netif_running(ndev)) 3158 return -ENETDOWN; 3159 3160 p->tx_lpi_timer = edata->tx_lpi_timer; 3161 3162 if (!edata->eee_enabled || !edata->tx_lpi_enabled || 3163 !edata->tx_lpi_timer) 3164 ret = fec_enet_eee_mode_set(ndev, false); 3165 else 3166 ret = fec_enet_eee_mode_set(ndev, true); 3167 3168 if (ret) 3169 return ret; 3170 3171 return phy_ethtool_set_eee(ndev->phydev, edata); 3172 } 3173 3174 static void 3175 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3176 { 3177 struct fec_enet_private *fep = netdev_priv(ndev); 3178 3179 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 3180 wol->supported = WAKE_MAGIC; 3181 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 3182 } else { 3183 wol->supported = wol->wolopts = 0; 3184 } 3185 } 3186 3187 static int 3188 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3189 { 3190 struct fec_enet_private *fep = netdev_priv(ndev); 3191 3192 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 3193 return -EINVAL; 3194 3195 if (wol->wolopts & ~WAKE_MAGIC) 3196 return -EINVAL; 3197 3198 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 3199 if (device_may_wakeup(&ndev->dev)) 3200 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 3201 else 3202 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 3203 3204 return 0; 3205 } 3206 3207 static const struct ethtool_ops fec_enet_ethtool_ops = { 3208 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3209 ETHTOOL_COALESCE_MAX_FRAMES, 3210 .get_drvinfo = fec_enet_get_drvinfo, 3211 .get_regs_len = fec_enet_get_regs_len, 3212 .get_regs = fec_enet_get_regs, 3213 .nway_reset = phy_ethtool_nway_reset, 3214 .get_link = ethtool_op_get_link, 3215 .get_coalesce = fec_enet_get_coalesce, 3216 .set_coalesce = fec_enet_set_coalesce, 3217 #ifndef CONFIG_M5272 3218 .get_pauseparam = fec_enet_get_pauseparam, 3219 .set_pauseparam = fec_enet_set_pauseparam, 3220 .get_strings = fec_enet_get_strings, 3221 .get_ethtool_stats = fec_enet_get_ethtool_stats, 3222 .get_sset_count = fec_enet_get_sset_count, 3223 #endif 3224 .get_ts_info = fec_enet_get_ts_info, 3225 .get_wol = fec_enet_get_wol, 3226 .set_wol = fec_enet_set_wol, 3227 .get_eee = fec_enet_get_eee, 3228 .set_eee = fec_enet_set_eee, 3229 .get_link_ksettings = phy_ethtool_get_link_ksettings, 3230 .set_link_ksettings = phy_ethtool_set_link_ksettings, 3231 .self_test = net_selftest, 3232 }; 3233 3234 static void fec_enet_free_buffers(struct net_device *ndev) 3235 { 3236 struct fec_enet_private *fep = netdev_priv(ndev); 3237 unsigned int i; 3238 struct fec_enet_priv_tx_q *txq; 3239 struct fec_enet_priv_rx_q *rxq; 3240 unsigned int q; 3241 3242 for (q = 0; q < fep->num_rx_queues; q++) { 3243 rxq = fep->rx_queue[q]; 3244 for (i = 0; i < rxq->bd.ring_size; i++) 3245 page_pool_put_full_page(rxq->page_pool, rxq->rx_skb_info[i].page, false); 3246 3247 for (i = 0; i < XDP_STATS_TOTAL; i++) 3248 rxq->stats[i] = 0; 3249 3250 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 3251 xdp_rxq_info_unreg(&rxq->xdp_rxq); 3252 page_pool_destroy(rxq->page_pool); 3253 rxq->page_pool = NULL; 3254 } 3255 3256 for (q = 0; q < fep->num_tx_queues; q++) { 3257 txq = fep->tx_queue[q]; 3258 for (i = 0; i < txq->bd.ring_size; i++) { 3259 kfree(txq->tx_bounce[i]); 3260 txq->tx_bounce[i] = NULL; 3261 3262 if (!txq->tx_buf[i].buf_p) { 3263 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3264 continue; 3265 } 3266 3267 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 3268 dev_kfree_skb(txq->tx_buf[i].buf_p); 3269 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 3270 xdp_return_frame(txq->tx_buf[i].buf_p); 3271 } else { 3272 struct page *page = txq->tx_buf[i].buf_p; 3273 3274 page_pool_put_page(page->pp, page, 0, false); 3275 } 3276 3277 txq->tx_buf[i].buf_p = NULL; 3278 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3279 } 3280 } 3281 } 3282 3283 static void fec_enet_free_queue(struct net_device *ndev) 3284 { 3285 struct fec_enet_private *fep = netdev_priv(ndev); 3286 int i; 3287 struct fec_enet_priv_tx_q *txq; 3288 3289 for (i = 0; i < fep->num_tx_queues; i++) 3290 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 3291 txq = fep->tx_queue[i]; 3292 dma_free_coherent(&fep->pdev->dev, 3293 txq->bd.ring_size * TSO_HEADER_SIZE, 3294 txq->tso_hdrs, 3295 txq->tso_hdrs_dma); 3296 } 3297 3298 for (i = 0; i < fep->num_rx_queues; i++) 3299 kfree(fep->rx_queue[i]); 3300 for (i = 0; i < fep->num_tx_queues; i++) 3301 kfree(fep->tx_queue[i]); 3302 } 3303 3304 static int fec_enet_alloc_queue(struct net_device *ndev) 3305 { 3306 struct fec_enet_private *fep = netdev_priv(ndev); 3307 int i; 3308 int ret = 0; 3309 struct fec_enet_priv_tx_q *txq; 3310 3311 for (i = 0; i < fep->num_tx_queues; i++) { 3312 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 3313 if (!txq) { 3314 ret = -ENOMEM; 3315 goto alloc_failed; 3316 } 3317 3318 fep->tx_queue[i] = txq; 3319 txq->bd.ring_size = TX_RING_SIZE; 3320 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 3321 3322 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 3323 txq->tx_wake_threshold = FEC_MAX_SKB_DESCS + 2 * MAX_SKB_FRAGS; 3324 3325 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 3326 txq->bd.ring_size * TSO_HEADER_SIZE, 3327 &txq->tso_hdrs_dma, 3328 GFP_KERNEL); 3329 if (!txq->tso_hdrs) { 3330 ret = -ENOMEM; 3331 goto alloc_failed; 3332 } 3333 } 3334 3335 for (i = 0; i < fep->num_rx_queues; i++) { 3336 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 3337 GFP_KERNEL); 3338 if (!fep->rx_queue[i]) { 3339 ret = -ENOMEM; 3340 goto alloc_failed; 3341 } 3342 3343 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 3344 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 3345 } 3346 return ret; 3347 3348 alloc_failed: 3349 fec_enet_free_queue(ndev); 3350 return ret; 3351 } 3352 3353 static int 3354 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 3355 { 3356 struct fec_enet_private *fep = netdev_priv(ndev); 3357 struct fec_enet_priv_rx_q *rxq; 3358 dma_addr_t phys_addr; 3359 struct bufdesc *bdp; 3360 struct page *page; 3361 int i, err; 3362 3363 rxq = fep->rx_queue[queue]; 3364 bdp = rxq->bd.base; 3365 3366 err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size); 3367 if (err < 0) { 3368 netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err); 3369 return err; 3370 } 3371 3372 for (i = 0; i < rxq->bd.ring_size; i++) { 3373 page = page_pool_dev_alloc_pages(rxq->page_pool); 3374 if (!page) 3375 goto err_alloc; 3376 3377 phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM; 3378 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 3379 3380 rxq->rx_skb_info[i].page = page; 3381 rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM; 3382 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3383 3384 if (fep->bufdesc_ex) { 3385 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3386 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 3387 } 3388 3389 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3390 } 3391 3392 /* Set the last buffer to wrap. */ 3393 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3394 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3395 return 0; 3396 3397 err_alloc: 3398 fec_enet_free_buffers(ndev); 3399 return -ENOMEM; 3400 } 3401 3402 static int 3403 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 3404 { 3405 struct fec_enet_private *fep = netdev_priv(ndev); 3406 unsigned int i; 3407 struct bufdesc *bdp; 3408 struct fec_enet_priv_tx_q *txq; 3409 3410 txq = fep->tx_queue[queue]; 3411 bdp = txq->bd.base; 3412 for (i = 0; i < txq->bd.ring_size; i++) { 3413 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 3414 if (!txq->tx_bounce[i]) 3415 goto err_alloc; 3416 3417 bdp->cbd_sc = cpu_to_fec16(0); 3418 bdp->cbd_bufaddr = cpu_to_fec32(0); 3419 3420 if (fep->bufdesc_ex) { 3421 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3422 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 3423 } 3424 3425 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3426 } 3427 3428 /* Set the last buffer to wrap. */ 3429 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3430 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3431 3432 return 0; 3433 3434 err_alloc: 3435 fec_enet_free_buffers(ndev); 3436 return -ENOMEM; 3437 } 3438 3439 static int fec_enet_alloc_buffers(struct net_device *ndev) 3440 { 3441 struct fec_enet_private *fep = netdev_priv(ndev); 3442 unsigned int i; 3443 3444 for (i = 0; i < fep->num_rx_queues; i++) 3445 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3446 return -ENOMEM; 3447 3448 for (i = 0; i < fep->num_tx_queues; i++) 3449 if (fec_enet_alloc_txq_buffers(ndev, i)) 3450 return -ENOMEM; 3451 return 0; 3452 } 3453 3454 static int 3455 fec_enet_open(struct net_device *ndev) 3456 { 3457 struct fec_enet_private *fep = netdev_priv(ndev); 3458 int ret; 3459 bool reset_again; 3460 3461 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3462 if (ret < 0) 3463 return ret; 3464 3465 pinctrl_pm_select_default_state(&fep->pdev->dev); 3466 ret = fec_enet_clk_enable(ndev, true); 3467 if (ret) 3468 goto clk_enable; 3469 3470 /* During the first fec_enet_open call the PHY isn't probed at this 3471 * point. Therefore the phy_reset_after_clk_enable() call within 3472 * fec_enet_clk_enable() fails. As we need this reset in order to be 3473 * sure the PHY is working correctly we check if we need to reset again 3474 * later when the PHY is probed 3475 */ 3476 if (ndev->phydev && ndev->phydev->drv) 3477 reset_again = false; 3478 else 3479 reset_again = true; 3480 3481 /* I should reset the ring buffers here, but I don't yet know 3482 * a simple way to do that. 3483 */ 3484 3485 ret = fec_enet_alloc_buffers(ndev); 3486 if (ret) 3487 goto err_enet_alloc; 3488 3489 /* Init MAC prior to mii bus probe */ 3490 fec_restart(ndev); 3491 3492 /* Call phy_reset_after_clk_enable() again if it failed during 3493 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3494 */ 3495 if (reset_again) 3496 fec_enet_phy_reset_after_clk_enable(ndev); 3497 3498 /* Probe and connect to PHY when open the interface */ 3499 ret = fec_enet_mii_probe(ndev); 3500 if (ret) 3501 goto err_enet_mii_probe; 3502 3503 if (fep->quirks & FEC_QUIRK_ERR006687) 3504 imx6q_cpuidle_fec_irqs_used(); 3505 3506 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3507 cpu_latency_qos_add_request(&fep->pm_qos_req, 0); 3508 3509 napi_enable(&fep->napi); 3510 phy_start(ndev->phydev); 3511 netif_tx_start_all_queues(ndev); 3512 3513 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3514 FEC_WOL_FLAG_ENABLE); 3515 3516 return 0; 3517 3518 err_enet_mii_probe: 3519 fec_enet_free_buffers(ndev); 3520 err_enet_alloc: 3521 fec_enet_clk_enable(ndev, false); 3522 clk_enable: 3523 pm_runtime_mark_last_busy(&fep->pdev->dev); 3524 pm_runtime_put_autosuspend(&fep->pdev->dev); 3525 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3526 return ret; 3527 } 3528 3529 static int 3530 fec_enet_close(struct net_device *ndev) 3531 { 3532 struct fec_enet_private *fep = netdev_priv(ndev); 3533 3534 phy_stop(ndev->phydev); 3535 3536 if (netif_device_present(ndev)) { 3537 napi_disable(&fep->napi); 3538 netif_tx_disable(ndev); 3539 fec_stop(ndev); 3540 } 3541 3542 phy_disconnect(ndev->phydev); 3543 3544 if (fep->quirks & FEC_QUIRK_ERR006687) 3545 imx6q_cpuidle_fec_irqs_unused(); 3546 3547 fec_enet_update_ethtool_stats(ndev); 3548 3549 fec_enet_clk_enable(ndev, false); 3550 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3551 cpu_latency_qos_remove_request(&fep->pm_qos_req); 3552 3553 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3554 pm_runtime_mark_last_busy(&fep->pdev->dev); 3555 pm_runtime_put_autosuspend(&fep->pdev->dev); 3556 3557 fec_enet_free_buffers(ndev); 3558 3559 return 0; 3560 } 3561 3562 /* Set or clear the multicast filter for this adaptor. 3563 * Skeleton taken from sunlance driver. 3564 * The CPM Ethernet implementation allows Multicast as well as individual 3565 * MAC address filtering. Some of the drivers check to make sure it is 3566 * a group multicast address, and discard those that are not. I guess I 3567 * will do the same for now, but just remove the test if you want 3568 * individual filtering as well (do the upper net layers want or support 3569 * this kind of feature?). 3570 */ 3571 3572 #define FEC_HASH_BITS 6 /* #bits in hash */ 3573 3574 static void set_multicast_list(struct net_device *ndev) 3575 { 3576 struct fec_enet_private *fep = netdev_priv(ndev); 3577 struct netdev_hw_addr *ha; 3578 unsigned int crc, tmp; 3579 unsigned char hash; 3580 unsigned int hash_high = 0, hash_low = 0; 3581 3582 if (ndev->flags & IFF_PROMISC) { 3583 tmp = readl(fep->hwp + FEC_R_CNTRL); 3584 tmp |= 0x8; 3585 writel(tmp, fep->hwp + FEC_R_CNTRL); 3586 return; 3587 } 3588 3589 tmp = readl(fep->hwp + FEC_R_CNTRL); 3590 tmp &= ~0x8; 3591 writel(tmp, fep->hwp + FEC_R_CNTRL); 3592 3593 if (ndev->flags & IFF_ALLMULTI) { 3594 /* Catch all multicast addresses, so set the 3595 * filter to all 1's 3596 */ 3597 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3598 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3599 3600 return; 3601 } 3602 3603 /* Add the addresses in hash register */ 3604 netdev_for_each_mc_addr(ha, ndev) { 3605 /* calculate crc32 value of mac address */ 3606 crc = ether_crc_le(ndev->addr_len, ha->addr); 3607 3608 /* only upper 6 bits (FEC_HASH_BITS) are used 3609 * which point to specific bit in the hash registers 3610 */ 3611 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3612 3613 if (hash > 31) 3614 hash_high |= 1 << (hash - 32); 3615 else 3616 hash_low |= 1 << hash; 3617 } 3618 3619 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3620 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3621 } 3622 3623 /* Set a MAC change in hardware. */ 3624 static int 3625 fec_set_mac_address(struct net_device *ndev, void *p) 3626 { 3627 struct fec_enet_private *fep = netdev_priv(ndev); 3628 struct sockaddr *addr = p; 3629 3630 if (addr) { 3631 if (!is_valid_ether_addr(addr->sa_data)) 3632 return -EADDRNOTAVAIL; 3633 eth_hw_addr_set(ndev, addr->sa_data); 3634 } 3635 3636 /* Add netif status check here to avoid system hang in below case: 3637 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3638 * After ethx down, fec all clocks are gated off and then register 3639 * access causes system hang. 3640 */ 3641 if (!netif_running(ndev)) 3642 return 0; 3643 3644 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3645 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3646 fep->hwp + FEC_ADDR_LOW); 3647 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3648 fep->hwp + FEC_ADDR_HIGH); 3649 return 0; 3650 } 3651 3652 #ifdef CONFIG_NET_POLL_CONTROLLER 3653 /** 3654 * fec_poll_controller - FEC Poll controller function 3655 * @dev: The FEC network adapter 3656 * 3657 * Polled functionality used by netconsole and others in non interrupt mode 3658 * 3659 */ 3660 static void fec_poll_controller(struct net_device *dev) 3661 { 3662 int i; 3663 struct fec_enet_private *fep = netdev_priv(dev); 3664 3665 for (i = 0; i < FEC_IRQ_NUM; i++) { 3666 if (fep->irq[i] > 0) { 3667 disable_irq(fep->irq[i]); 3668 fec_enet_interrupt(fep->irq[i], dev); 3669 enable_irq(fep->irq[i]); 3670 } 3671 } 3672 } 3673 #endif 3674 3675 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3676 netdev_features_t features) 3677 { 3678 struct fec_enet_private *fep = netdev_priv(netdev); 3679 netdev_features_t changed = features ^ netdev->features; 3680 3681 netdev->features = features; 3682 3683 /* Receive checksum has been changed */ 3684 if (changed & NETIF_F_RXCSUM) { 3685 if (features & NETIF_F_RXCSUM) 3686 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3687 else 3688 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3689 } 3690 } 3691 3692 static int fec_set_features(struct net_device *netdev, 3693 netdev_features_t features) 3694 { 3695 struct fec_enet_private *fep = netdev_priv(netdev); 3696 netdev_features_t changed = features ^ netdev->features; 3697 3698 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3699 napi_disable(&fep->napi); 3700 netif_tx_lock_bh(netdev); 3701 fec_stop(netdev); 3702 fec_enet_set_netdev_features(netdev, features); 3703 fec_restart(netdev); 3704 netif_tx_wake_all_queues(netdev); 3705 netif_tx_unlock_bh(netdev); 3706 napi_enable(&fep->napi); 3707 } else { 3708 fec_enet_set_netdev_features(netdev, features); 3709 } 3710 3711 return 0; 3712 } 3713 3714 static u16 fec_enet_get_raw_vlan_tci(struct sk_buff *skb) 3715 { 3716 struct vlan_ethhdr *vhdr; 3717 unsigned short vlan_TCI = 0; 3718 3719 if (skb->protocol == htons(ETH_P_ALL)) { 3720 vhdr = (struct vlan_ethhdr *)(skb->data); 3721 vlan_TCI = ntohs(vhdr->h_vlan_TCI); 3722 } 3723 3724 return vlan_TCI; 3725 } 3726 3727 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3728 struct net_device *sb_dev) 3729 { 3730 struct fec_enet_private *fep = netdev_priv(ndev); 3731 u16 vlan_tag; 3732 3733 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3734 return netdev_pick_tx(ndev, skb, NULL); 3735 3736 vlan_tag = fec_enet_get_raw_vlan_tci(skb); 3737 if (!vlan_tag) 3738 return vlan_tag; 3739 3740 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3741 } 3742 3743 static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf) 3744 { 3745 struct fec_enet_private *fep = netdev_priv(dev); 3746 bool is_run = netif_running(dev); 3747 struct bpf_prog *old_prog; 3748 3749 switch (bpf->command) { 3750 case XDP_SETUP_PROG: 3751 /* No need to support the SoCs that require to 3752 * do the frame swap because the performance wouldn't be 3753 * better than the skb mode. 3754 */ 3755 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 3756 return -EOPNOTSUPP; 3757 3758 if (!bpf->prog) 3759 xdp_features_clear_redirect_target(dev); 3760 3761 if (is_run) { 3762 napi_disable(&fep->napi); 3763 netif_tx_disable(dev); 3764 } 3765 3766 old_prog = xchg(&fep->xdp_prog, bpf->prog); 3767 if (old_prog) 3768 bpf_prog_put(old_prog); 3769 3770 fec_restart(dev); 3771 3772 if (is_run) { 3773 napi_enable(&fep->napi); 3774 netif_tx_start_all_queues(dev); 3775 } 3776 3777 if (bpf->prog) 3778 xdp_features_set_redirect_target(dev, false); 3779 3780 return 0; 3781 3782 case XDP_SETUP_XSK_POOL: 3783 return -EOPNOTSUPP; 3784 3785 default: 3786 return -EOPNOTSUPP; 3787 } 3788 } 3789 3790 static int 3791 fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index) 3792 { 3793 if (unlikely(index < 0)) 3794 return 0; 3795 3796 return (index % fep->num_tx_queues); 3797 } 3798 3799 static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep, 3800 struct fec_enet_priv_tx_q *txq, 3801 void *frame, u32 dma_sync_len, 3802 bool ndo_xmit) 3803 { 3804 unsigned int index, status, estatus; 3805 struct bufdesc *bdp; 3806 dma_addr_t dma_addr; 3807 int entries_free; 3808 u16 frame_len; 3809 3810 entries_free = fec_enet_get_free_txdesc_num(txq); 3811 if (entries_free < MAX_SKB_FRAGS + 1) { 3812 netdev_err_once(fep->netdev, "NOT enough BD for SG!\n"); 3813 return -EBUSY; 3814 } 3815 3816 /* Fill in a Tx ring entry */ 3817 bdp = txq->bd.cur; 3818 status = fec16_to_cpu(bdp->cbd_sc); 3819 status &= ~BD_ENET_TX_STATS; 3820 3821 index = fec_enet_get_bd_index(bdp, &txq->bd); 3822 3823 if (ndo_xmit) { 3824 struct xdp_frame *xdpf = frame; 3825 3826 dma_addr = dma_map_single(&fep->pdev->dev, xdpf->data, 3827 xdpf->len, DMA_TO_DEVICE); 3828 if (dma_mapping_error(&fep->pdev->dev, dma_addr)) 3829 return -ENOMEM; 3830 3831 frame_len = xdpf->len; 3832 txq->tx_buf[index].buf_p = xdpf; 3833 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_NDO; 3834 } else { 3835 struct xdp_buff *xdpb = frame; 3836 struct page *page; 3837 3838 page = virt_to_page(xdpb->data); 3839 dma_addr = page_pool_get_dma_addr(page) + 3840 (xdpb->data - xdpb->data_hard_start); 3841 dma_sync_single_for_device(&fep->pdev->dev, dma_addr, 3842 dma_sync_len, DMA_BIDIRECTIONAL); 3843 frame_len = xdpb->data_end - xdpb->data; 3844 txq->tx_buf[index].buf_p = page; 3845 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_TX; 3846 } 3847 3848 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 3849 if (fep->bufdesc_ex) 3850 estatus = BD_ENET_TX_INT; 3851 3852 bdp->cbd_bufaddr = cpu_to_fec32(dma_addr); 3853 bdp->cbd_datlen = cpu_to_fec16(frame_len); 3854 3855 if (fep->bufdesc_ex) { 3856 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3857 3858 if (fep->quirks & FEC_QUIRK_HAS_AVB) 3859 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 3860 3861 ebdp->cbd_bdu = 0; 3862 ebdp->cbd_esc = cpu_to_fec32(estatus); 3863 } 3864 3865 /* Make sure the updates to rest of the descriptor are performed before 3866 * transferring ownership. 3867 */ 3868 dma_wmb(); 3869 3870 /* Send it on its way. Tell FEC it's ready, interrupt when done, 3871 * it's the last BD of the frame, and to put the CRC on the end. 3872 */ 3873 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 3874 bdp->cbd_sc = cpu_to_fec16(status); 3875 3876 /* If this was the last BD in the ring, start at the beginning again. */ 3877 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3878 3879 /* Make sure the update to bdp are performed before txq->bd.cur. */ 3880 dma_wmb(); 3881 3882 txq->bd.cur = bdp; 3883 3884 /* Trigger transmission start */ 3885 writel(0, txq->bd.reg_desc_active); 3886 3887 return 0; 3888 } 3889 3890 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 3891 int cpu, struct xdp_buff *xdp, 3892 u32 dma_sync_len) 3893 { 3894 struct fec_enet_priv_tx_q *txq; 3895 struct netdev_queue *nq; 3896 int queue, ret; 3897 3898 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3899 txq = fep->tx_queue[queue]; 3900 nq = netdev_get_tx_queue(fep->netdev, queue); 3901 3902 __netif_tx_lock(nq, cpu); 3903 3904 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3905 txq_trans_cond_update(nq); 3906 ret = fec_enet_txq_xmit_frame(fep, txq, xdp, dma_sync_len, false); 3907 3908 __netif_tx_unlock(nq); 3909 3910 return ret; 3911 } 3912 3913 static int fec_enet_xdp_xmit(struct net_device *dev, 3914 int num_frames, 3915 struct xdp_frame **frames, 3916 u32 flags) 3917 { 3918 struct fec_enet_private *fep = netdev_priv(dev); 3919 struct fec_enet_priv_tx_q *txq; 3920 int cpu = smp_processor_id(); 3921 unsigned int sent_frames = 0; 3922 struct netdev_queue *nq; 3923 unsigned int queue; 3924 int i; 3925 3926 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3927 txq = fep->tx_queue[queue]; 3928 nq = netdev_get_tx_queue(fep->netdev, queue); 3929 3930 __netif_tx_lock(nq, cpu); 3931 3932 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3933 txq_trans_cond_update(nq); 3934 for (i = 0; i < num_frames; i++) { 3935 if (fec_enet_txq_xmit_frame(fep, txq, frames[i], 0, true) < 0) 3936 break; 3937 sent_frames++; 3938 } 3939 3940 __netif_tx_unlock(nq); 3941 3942 return sent_frames; 3943 } 3944 3945 static int fec_hwtstamp_get(struct net_device *ndev, 3946 struct kernel_hwtstamp_config *config) 3947 { 3948 struct fec_enet_private *fep = netdev_priv(ndev); 3949 3950 if (!netif_running(ndev)) 3951 return -EINVAL; 3952 3953 if (!fep->bufdesc_ex) 3954 return -EOPNOTSUPP; 3955 3956 fec_ptp_get(ndev, config); 3957 3958 return 0; 3959 } 3960 3961 static int fec_hwtstamp_set(struct net_device *ndev, 3962 struct kernel_hwtstamp_config *config, 3963 struct netlink_ext_ack *extack) 3964 { 3965 struct fec_enet_private *fep = netdev_priv(ndev); 3966 3967 if (!netif_running(ndev)) 3968 return -EINVAL; 3969 3970 if (!fep->bufdesc_ex) 3971 return -EOPNOTSUPP; 3972 3973 return fec_ptp_set(ndev, config, extack); 3974 } 3975 3976 static const struct net_device_ops fec_netdev_ops = { 3977 .ndo_open = fec_enet_open, 3978 .ndo_stop = fec_enet_close, 3979 .ndo_start_xmit = fec_enet_start_xmit, 3980 .ndo_select_queue = fec_enet_select_queue, 3981 .ndo_set_rx_mode = set_multicast_list, 3982 .ndo_validate_addr = eth_validate_addr, 3983 .ndo_tx_timeout = fec_timeout, 3984 .ndo_set_mac_address = fec_set_mac_address, 3985 .ndo_eth_ioctl = phy_do_ioctl_running, 3986 #ifdef CONFIG_NET_POLL_CONTROLLER 3987 .ndo_poll_controller = fec_poll_controller, 3988 #endif 3989 .ndo_set_features = fec_set_features, 3990 .ndo_bpf = fec_enet_bpf, 3991 .ndo_xdp_xmit = fec_enet_xdp_xmit, 3992 .ndo_hwtstamp_get = fec_hwtstamp_get, 3993 .ndo_hwtstamp_set = fec_hwtstamp_set, 3994 }; 3995 3996 static const unsigned short offset_des_active_rxq[] = { 3997 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3998 }; 3999 4000 static const unsigned short offset_des_active_txq[] = { 4001 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 4002 }; 4003 4004 /* 4005 * XXX: We need to clean up on failure exits here. 4006 * 4007 */ 4008 static int fec_enet_init(struct net_device *ndev) 4009 { 4010 struct fec_enet_private *fep = netdev_priv(ndev); 4011 struct bufdesc *cbd_base; 4012 dma_addr_t bd_dma; 4013 int bd_size; 4014 unsigned int i; 4015 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 4016 sizeof(struct bufdesc); 4017 unsigned dsize_log2 = __fls(dsize); 4018 int ret; 4019 4020 WARN_ON(dsize != (1 << dsize_log2)); 4021 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 4022 fep->rx_align = 0xf; 4023 fep->tx_align = 0xf; 4024 #else 4025 fep->rx_align = 0x3; 4026 fep->tx_align = 0x3; 4027 #endif 4028 fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4029 fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4030 fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT; 4031 fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT; 4032 4033 /* Check mask of the streaming and coherent API */ 4034 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 4035 if (ret < 0) { 4036 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 4037 return ret; 4038 } 4039 4040 ret = fec_enet_alloc_queue(ndev); 4041 if (ret) 4042 return ret; 4043 4044 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 4045 4046 /* Allocate memory for buffer descriptors. */ 4047 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 4048 GFP_KERNEL); 4049 if (!cbd_base) { 4050 ret = -ENOMEM; 4051 goto free_queue_mem; 4052 } 4053 4054 /* Get the Ethernet address */ 4055 ret = fec_get_mac(ndev); 4056 if (ret) 4057 goto free_queue_mem; 4058 4059 /* Set receive and transmit descriptor base. */ 4060 for (i = 0; i < fep->num_rx_queues; i++) { 4061 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 4062 unsigned size = dsize * rxq->bd.ring_size; 4063 4064 rxq->bd.qid = i; 4065 rxq->bd.base = cbd_base; 4066 rxq->bd.cur = cbd_base; 4067 rxq->bd.dma = bd_dma; 4068 rxq->bd.dsize = dsize; 4069 rxq->bd.dsize_log2 = dsize_log2; 4070 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 4071 bd_dma += size; 4072 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4073 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4074 } 4075 4076 for (i = 0; i < fep->num_tx_queues; i++) { 4077 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 4078 unsigned size = dsize * txq->bd.ring_size; 4079 4080 txq->bd.qid = i; 4081 txq->bd.base = cbd_base; 4082 txq->bd.cur = cbd_base; 4083 txq->bd.dma = bd_dma; 4084 txq->bd.dsize = dsize; 4085 txq->bd.dsize_log2 = dsize_log2; 4086 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 4087 bd_dma += size; 4088 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4089 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4090 } 4091 4092 4093 /* The FEC Ethernet specific entries in the device structure */ 4094 ndev->watchdog_timeo = TX_TIMEOUT; 4095 ndev->netdev_ops = &fec_netdev_ops; 4096 ndev->ethtool_ops = &fec_enet_ethtool_ops; 4097 4098 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 4099 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi); 4100 4101 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 4102 /* enable hw VLAN support */ 4103 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 4104 4105 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 4106 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS); 4107 4108 /* enable hw accelerator */ 4109 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 4110 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 4111 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 4112 } 4113 4114 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 4115 fep->tx_align = 0; 4116 fep->rx_align = 0x3f; 4117 } 4118 4119 ndev->hw_features = ndev->features; 4120 4121 if (!(fep->quirks & FEC_QUIRK_SWAP_FRAME)) 4122 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 4123 NETDEV_XDP_ACT_REDIRECT; 4124 4125 fec_restart(ndev); 4126 4127 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 4128 fec_enet_clear_ethtool_stats(ndev); 4129 else 4130 fec_enet_update_ethtool_stats(ndev); 4131 4132 return 0; 4133 4134 free_queue_mem: 4135 fec_enet_free_queue(ndev); 4136 return ret; 4137 } 4138 4139 #ifdef CONFIG_OF 4140 static int fec_reset_phy(struct platform_device *pdev) 4141 { 4142 struct gpio_desc *phy_reset; 4143 int msec = 1, phy_post_delay = 0; 4144 struct device_node *np = pdev->dev.of_node; 4145 int err; 4146 4147 if (!np) 4148 return 0; 4149 4150 err = of_property_read_u32(np, "phy-reset-duration", &msec); 4151 /* A sane reset duration should not be longer than 1s */ 4152 if (!err && msec > 1000) 4153 msec = 1; 4154 4155 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 4156 /* valid reset duration should be less than 1s */ 4157 if (!err && phy_post_delay > 1000) 4158 return -EINVAL; 4159 4160 phy_reset = devm_gpiod_get_optional(&pdev->dev, "phy-reset", 4161 GPIOD_OUT_HIGH); 4162 if (IS_ERR(phy_reset)) 4163 return dev_err_probe(&pdev->dev, PTR_ERR(phy_reset), 4164 "failed to get phy-reset-gpios\n"); 4165 4166 if (!phy_reset) 4167 return 0; 4168 4169 if (msec > 20) 4170 msleep(msec); 4171 else 4172 usleep_range(msec * 1000, msec * 1000 + 1000); 4173 4174 gpiod_set_value_cansleep(phy_reset, 0); 4175 4176 if (!phy_post_delay) 4177 return 0; 4178 4179 if (phy_post_delay > 20) 4180 msleep(phy_post_delay); 4181 else 4182 usleep_range(phy_post_delay * 1000, 4183 phy_post_delay * 1000 + 1000); 4184 4185 return 0; 4186 } 4187 #else /* CONFIG_OF */ 4188 static int fec_reset_phy(struct platform_device *pdev) 4189 { 4190 /* 4191 * In case of platform probe, the reset has been done 4192 * by machine code. 4193 */ 4194 return 0; 4195 } 4196 #endif /* CONFIG_OF */ 4197 4198 static void 4199 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 4200 { 4201 struct device_node *np = pdev->dev.of_node; 4202 4203 *num_tx = *num_rx = 1; 4204 4205 if (!np || !of_device_is_available(np)) 4206 return; 4207 4208 /* parse the num of tx and rx queues */ 4209 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 4210 4211 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 4212 4213 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 4214 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 4215 *num_tx); 4216 *num_tx = 1; 4217 return; 4218 } 4219 4220 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 4221 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 4222 *num_rx); 4223 *num_rx = 1; 4224 return; 4225 } 4226 4227 } 4228 4229 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 4230 { 4231 int irq_cnt = platform_irq_count(pdev); 4232 4233 if (irq_cnt > FEC_IRQ_NUM) 4234 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 4235 else if (irq_cnt == 2) 4236 irq_cnt = 1; /* last for pps */ 4237 else if (irq_cnt <= 0) 4238 irq_cnt = 1; /* At least 1 irq is needed */ 4239 return irq_cnt; 4240 } 4241 4242 static void fec_enet_get_wakeup_irq(struct platform_device *pdev) 4243 { 4244 struct net_device *ndev = platform_get_drvdata(pdev); 4245 struct fec_enet_private *fep = netdev_priv(ndev); 4246 4247 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) 4248 fep->wake_irq = fep->irq[2]; 4249 else 4250 fep->wake_irq = fep->irq[0]; 4251 } 4252 4253 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 4254 struct device_node *np) 4255 { 4256 struct device_node *gpr_np; 4257 u32 out_val[3]; 4258 int ret = 0; 4259 4260 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 4261 if (!gpr_np) 4262 return 0; 4263 4264 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 4265 ARRAY_SIZE(out_val)); 4266 if (ret) { 4267 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 4268 goto out; 4269 } 4270 4271 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 4272 if (IS_ERR(fep->stop_gpr.gpr)) { 4273 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 4274 ret = PTR_ERR(fep->stop_gpr.gpr); 4275 fep->stop_gpr.gpr = NULL; 4276 goto out; 4277 } 4278 4279 fep->stop_gpr.reg = out_val[1]; 4280 fep->stop_gpr.bit = out_val[2]; 4281 4282 out: 4283 of_node_put(gpr_np); 4284 4285 return ret; 4286 } 4287 4288 static int 4289 fec_probe(struct platform_device *pdev) 4290 { 4291 struct fec_enet_private *fep; 4292 struct fec_platform_data *pdata; 4293 phy_interface_t interface; 4294 struct net_device *ndev; 4295 int i, irq, ret = 0; 4296 const struct of_device_id *of_id; 4297 static int dev_id; 4298 struct device_node *np = pdev->dev.of_node, *phy_node; 4299 int num_tx_qs; 4300 int num_rx_qs; 4301 char irq_name[8]; 4302 int irq_cnt; 4303 struct fec_devinfo *dev_info; 4304 4305 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 4306 4307 /* Init network device */ 4308 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 4309 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 4310 if (!ndev) 4311 return -ENOMEM; 4312 4313 SET_NETDEV_DEV(ndev, &pdev->dev); 4314 4315 /* setup board info structure */ 4316 fep = netdev_priv(ndev); 4317 4318 of_id = of_match_device(fec_dt_ids, &pdev->dev); 4319 if (of_id) 4320 pdev->id_entry = of_id->data; 4321 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; 4322 if (dev_info) 4323 fep->quirks = dev_info->quirks; 4324 4325 fep->netdev = ndev; 4326 fep->num_rx_queues = num_rx_qs; 4327 fep->num_tx_queues = num_tx_qs; 4328 4329 #if !defined(CONFIG_M5272) 4330 /* default enable pause frame auto negotiation */ 4331 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 4332 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 4333 #endif 4334 4335 /* Select default pin state */ 4336 pinctrl_pm_select_default_state(&pdev->dev); 4337 4338 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 4339 if (IS_ERR(fep->hwp)) { 4340 ret = PTR_ERR(fep->hwp); 4341 goto failed_ioremap; 4342 } 4343 4344 fep->pdev = pdev; 4345 fep->dev_id = dev_id++; 4346 4347 platform_set_drvdata(pdev, ndev); 4348 4349 if ((of_machine_is_compatible("fsl,imx6q") || 4350 of_machine_is_compatible("fsl,imx6dl")) && 4351 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 4352 fep->quirks |= FEC_QUIRK_ERR006687; 4353 4354 ret = fec_enet_ipc_handle_init(fep); 4355 if (ret) 4356 goto failed_ipc_init; 4357 4358 if (of_property_read_bool(np, "fsl,magic-packet")) 4359 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 4360 4361 ret = fec_enet_init_stop_mode(fep, np); 4362 if (ret) 4363 goto failed_stop_mode; 4364 4365 phy_node = of_parse_phandle(np, "phy-handle", 0); 4366 if (!phy_node && of_phy_is_fixed_link(np)) { 4367 ret = of_phy_register_fixed_link(np); 4368 if (ret < 0) { 4369 dev_err(&pdev->dev, 4370 "broken fixed-link specification\n"); 4371 goto failed_phy; 4372 } 4373 phy_node = of_node_get(np); 4374 } 4375 fep->phy_node = phy_node; 4376 4377 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 4378 if (ret) { 4379 pdata = dev_get_platdata(&pdev->dev); 4380 if (pdata) 4381 fep->phy_interface = pdata->phy; 4382 else 4383 fep->phy_interface = PHY_INTERFACE_MODE_MII; 4384 } else { 4385 fep->phy_interface = interface; 4386 } 4387 4388 ret = fec_enet_parse_rgmii_delay(fep, np); 4389 if (ret) 4390 goto failed_rgmii_delay; 4391 4392 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 4393 if (IS_ERR(fep->clk_ipg)) { 4394 ret = PTR_ERR(fep->clk_ipg); 4395 goto failed_clk; 4396 } 4397 4398 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 4399 if (IS_ERR(fep->clk_ahb)) { 4400 ret = PTR_ERR(fep->clk_ahb); 4401 goto failed_clk; 4402 } 4403 4404 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 4405 4406 /* enet_out is optional, depends on board */ 4407 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out"); 4408 if (IS_ERR(fep->clk_enet_out)) { 4409 ret = PTR_ERR(fep->clk_enet_out); 4410 goto failed_clk; 4411 } 4412 4413 fep->ptp_clk_on = false; 4414 mutex_init(&fep->ptp_clk_mutex); 4415 4416 /* clk_ref is optional, depends on board */ 4417 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref"); 4418 if (IS_ERR(fep->clk_ref)) { 4419 ret = PTR_ERR(fep->clk_ref); 4420 goto failed_clk; 4421 } 4422 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); 4423 4424 /* clk_2x_txclk is optional, depends on board */ 4425 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { 4426 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); 4427 if (IS_ERR(fep->clk_2x_txclk)) 4428 fep->clk_2x_txclk = NULL; 4429 } 4430 4431 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 4432 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 4433 if (IS_ERR(fep->clk_ptp)) { 4434 fep->clk_ptp = NULL; 4435 fep->bufdesc_ex = false; 4436 } 4437 4438 ret = fec_enet_clk_enable(ndev, true); 4439 if (ret) 4440 goto failed_clk; 4441 4442 ret = clk_prepare_enable(fep->clk_ipg); 4443 if (ret) 4444 goto failed_clk_ipg; 4445 ret = clk_prepare_enable(fep->clk_ahb); 4446 if (ret) 4447 goto failed_clk_ahb; 4448 4449 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 4450 if (!IS_ERR(fep->reg_phy)) { 4451 ret = regulator_enable(fep->reg_phy); 4452 if (ret) { 4453 dev_err(&pdev->dev, 4454 "Failed to enable phy regulator: %d\n", ret); 4455 goto failed_regulator; 4456 } 4457 } else { 4458 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 4459 ret = -EPROBE_DEFER; 4460 goto failed_regulator; 4461 } 4462 fep->reg_phy = NULL; 4463 } 4464 4465 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 4466 pm_runtime_use_autosuspend(&pdev->dev); 4467 pm_runtime_get_noresume(&pdev->dev); 4468 pm_runtime_set_active(&pdev->dev); 4469 pm_runtime_enable(&pdev->dev); 4470 4471 ret = fec_reset_phy(pdev); 4472 if (ret) 4473 goto failed_reset; 4474 4475 irq_cnt = fec_enet_get_irq_cnt(pdev); 4476 if (fep->bufdesc_ex) 4477 fec_ptp_init(pdev, irq_cnt); 4478 4479 ret = fec_enet_init(ndev); 4480 if (ret) 4481 goto failed_init; 4482 4483 for (i = 0; i < irq_cnt; i++) { 4484 snprintf(irq_name, sizeof(irq_name), "int%d", i); 4485 irq = platform_get_irq_byname_optional(pdev, irq_name); 4486 if (irq < 0) 4487 irq = platform_get_irq(pdev, i); 4488 if (irq < 0) { 4489 ret = irq; 4490 goto failed_irq; 4491 } 4492 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 4493 0, pdev->name, ndev); 4494 if (ret) 4495 goto failed_irq; 4496 4497 fep->irq[i] = irq; 4498 } 4499 4500 /* Decide which interrupt line is wakeup capable */ 4501 fec_enet_get_wakeup_irq(pdev); 4502 4503 ret = fec_enet_mii_init(pdev); 4504 if (ret) 4505 goto failed_mii_init; 4506 4507 /* Carrier starts down, phylib will bring it up */ 4508 netif_carrier_off(ndev); 4509 fec_enet_clk_enable(ndev, false); 4510 pinctrl_pm_select_sleep_state(&pdev->dev); 4511 4512 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN; 4513 4514 ret = register_netdev(ndev); 4515 if (ret) 4516 goto failed_register; 4517 4518 device_init_wakeup(&ndev->dev, fep->wol_flag & 4519 FEC_WOL_HAS_MAGIC_PACKET); 4520 4521 if (fep->bufdesc_ex && fep->ptp_clock) 4522 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 4523 4524 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 4525 4526 pm_runtime_mark_last_busy(&pdev->dev); 4527 pm_runtime_put_autosuspend(&pdev->dev); 4528 4529 return 0; 4530 4531 failed_register: 4532 fec_enet_mii_remove(fep); 4533 failed_mii_init: 4534 failed_irq: 4535 failed_init: 4536 fec_ptp_stop(pdev); 4537 failed_reset: 4538 pm_runtime_put_noidle(&pdev->dev); 4539 pm_runtime_disable(&pdev->dev); 4540 if (fep->reg_phy) 4541 regulator_disable(fep->reg_phy); 4542 failed_regulator: 4543 clk_disable_unprepare(fep->clk_ahb); 4544 failed_clk_ahb: 4545 clk_disable_unprepare(fep->clk_ipg); 4546 failed_clk_ipg: 4547 fec_enet_clk_enable(ndev, false); 4548 failed_clk: 4549 failed_rgmii_delay: 4550 if (of_phy_is_fixed_link(np)) 4551 of_phy_deregister_fixed_link(np); 4552 of_node_put(phy_node); 4553 failed_stop_mode: 4554 failed_ipc_init: 4555 failed_phy: 4556 dev_id--; 4557 failed_ioremap: 4558 free_netdev(ndev); 4559 4560 return ret; 4561 } 4562 4563 static void 4564 fec_drv_remove(struct platform_device *pdev) 4565 { 4566 struct net_device *ndev = platform_get_drvdata(pdev); 4567 struct fec_enet_private *fep = netdev_priv(ndev); 4568 struct device_node *np = pdev->dev.of_node; 4569 int ret; 4570 4571 ret = pm_runtime_get_sync(&pdev->dev); 4572 if (ret < 0) 4573 dev_err(&pdev->dev, 4574 "Failed to resume device in remove callback (%pe)\n", 4575 ERR_PTR(ret)); 4576 4577 cancel_work_sync(&fep->tx_timeout_work); 4578 fec_ptp_stop(pdev); 4579 unregister_netdev(ndev); 4580 fec_enet_mii_remove(fep); 4581 if (fep->reg_phy) 4582 regulator_disable(fep->reg_phy); 4583 4584 if (of_phy_is_fixed_link(np)) 4585 of_phy_deregister_fixed_link(np); 4586 of_node_put(fep->phy_node); 4587 4588 /* After pm_runtime_get_sync() failed, the clks are still off, so skip 4589 * disabling them again. 4590 */ 4591 if (ret >= 0) { 4592 clk_disable_unprepare(fep->clk_ahb); 4593 clk_disable_unprepare(fep->clk_ipg); 4594 } 4595 pm_runtime_put_noidle(&pdev->dev); 4596 pm_runtime_disable(&pdev->dev); 4597 4598 free_netdev(ndev); 4599 } 4600 4601 static int __maybe_unused fec_suspend(struct device *dev) 4602 { 4603 struct net_device *ndev = dev_get_drvdata(dev); 4604 struct fec_enet_private *fep = netdev_priv(ndev); 4605 int ret; 4606 4607 rtnl_lock(); 4608 if (netif_running(ndev)) { 4609 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 4610 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 4611 phy_stop(ndev->phydev); 4612 napi_disable(&fep->napi); 4613 netif_tx_lock_bh(ndev); 4614 netif_device_detach(ndev); 4615 netif_tx_unlock_bh(ndev); 4616 fec_stop(ndev); 4617 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4618 fec_irqs_disable(ndev); 4619 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 4620 } else { 4621 fec_irqs_disable_except_wakeup(ndev); 4622 if (fep->wake_irq > 0) { 4623 disable_irq(fep->wake_irq); 4624 enable_irq_wake(fep->wake_irq); 4625 } 4626 fec_enet_stop_mode(fep, true); 4627 } 4628 /* It's safe to disable clocks since interrupts are masked */ 4629 fec_enet_clk_enable(ndev, false); 4630 4631 fep->rpm_active = !pm_runtime_status_suspended(dev); 4632 if (fep->rpm_active) { 4633 ret = pm_runtime_force_suspend(dev); 4634 if (ret < 0) { 4635 rtnl_unlock(); 4636 return ret; 4637 } 4638 } 4639 } 4640 rtnl_unlock(); 4641 4642 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4643 regulator_disable(fep->reg_phy); 4644 4645 /* SOC supply clock to phy, when clock is disabled, phy link down 4646 * SOC control phy regulator, when regulator is disabled, phy link down 4647 */ 4648 if (fep->clk_enet_out || fep->reg_phy) 4649 fep->link = 0; 4650 4651 return 0; 4652 } 4653 4654 static int __maybe_unused fec_resume(struct device *dev) 4655 { 4656 struct net_device *ndev = dev_get_drvdata(dev); 4657 struct fec_enet_private *fep = netdev_priv(ndev); 4658 int ret; 4659 int val; 4660 4661 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4662 ret = regulator_enable(fep->reg_phy); 4663 if (ret) 4664 return ret; 4665 } 4666 4667 rtnl_lock(); 4668 if (netif_running(ndev)) { 4669 if (fep->rpm_active) 4670 pm_runtime_force_resume(dev); 4671 4672 ret = fec_enet_clk_enable(ndev, true); 4673 if (ret) { 4674 rtnl_unlock(); 4675 goto failed_clk; 4676 } 4677 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 4678 fec_enet_stop_mode(fep, false); 4679 if (fep->wake_irq) { 4680 disable_irq_wake(fep->wake_irq); 4681 enable_irq(fep->wake_irq); 4682 } 4683 4684 val = readl(fep->hwp + FEC_ECNTRL); 4685 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 4686 writel(val, fep->hwp + FEC_ECNTRL); 4687 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 4688 } else { 4689 pinctrl_pm_select_default_state(&fep->pdev->dev); 4690 } 4691 fec_restart(ndev); 4692 netif_tx_lock_bh(ndev); 4693 netif_device_attach(ndev); 4694 netif_tx_unlock_bh(ndev); 4695 napi_enable(&fep->napi); 4696 phy_init_hw(ndev->phydev); 4697 phy_start(ndev->phydev); 4698 } 4699 rtnl_unlock(); 4700 4701 return 0; 4702 4703 failed_clk: 4704 if (fep->reg_phy) 4705 regulator_disable(fep->reg_phy); 4706 return ret; 4707 } 4708 4709 static int __maybe_unused fec_runtime_suspend(struct device *dev) 4710 { 4711 struct net_device *ndev = dev_get_drvdata(dev); 4712 struct fec_enet_private *fep = netdev_priv(ndev); 4713 4714 clk_disable_unprepare(fep->clk_ahb); 4715 clk_disable_unprepare(fep->clk_ipg); 4716 4717 return 0; 4718 } 4719 4720 static int __maybe_unused fec_runtime_resume(struct device *dev) 4721 { 4722 struct net_device *ndev = dev_get_drvdata(dev); 4723 struct fec_enet_private *fep = netdev_priv(ndev); 4724 int ret; 4725 4726 ret = clk_prepare_enable(fep->clk_ahb); 4727 if (ret) 4728 return ret; 4729 ret = clk_prepare_enable(fep->clk_ipg); 4730 if (ret) 4731 goto failed_clk_ipg; 4732 4733 return 0; 4734 4735 failed_clk_ipg: 4736 clk_disable_unprepare(fep->clk_ahb); 4737 return ret; 4738 } 4739 4740 static const struct dev_pm_ops fec_pm_ops = { 4741 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 4742 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 4743 }; 4744 4745 static struct platform_driver fec_driver = { 4746 .driver = { 4747 .name = DRIVER_NAME, 4748 .pm = &fec_pm_ops, 4749 .of_match_table = fec_dt_ids, 4750 .suppress_bind_attrs = true, 4751 }, 4752 .id_table = fec_devtype, 4753 .probe = fec_probe, 4754 .remove_new = fec_drv_remove, 4755 }; 4756 4757 module_platform_driver(fec_driver); 4758 4759 MODULE_LICENSE("GPL"); 4760