1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2ec21e2ecSJeff Kirsher /****************************************************************************/ 3ec21e2ecSJeff Kirsher 4ec21e2ecSJeff Kirsher /* 5ec21e2ecSJeff Kirsher * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC 6ec21e2ecSJeff Kirsher * processors. 7ec21e2ecSJeff Kirsher * 8ec21e2ecSJeff Kirsher * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com) 9ec21e2ecSJeff Kirsher * (C) Copyright 2000-2001, Lineo (www.lineo.com) 10ec21e2ecSJeff Kirsher */ 11ec21e2ecSJeff Kirsher 12ec21e2ecSJeff Kirsher /****************************************************************************/ 13ec21e2ecSJeff Kirsher #ifndef FEC_H 14ec21e2ecSJeff Kirsher #define FEC_H 15ec21e2ecSJeff Kirsher /****************************************************************************/ 16ec21e2ecSJeff Kirsher 176605b730SFrank Li #include <linux/clocksource.h> 186605b730SFrank Li #include <linux/net_tstamp.h> 197d650df9SWei Fang #include <linux/pm_qos.h> 20*95698ff6SShenwei Wang #include <linux/bpf.h> 216605b730SFrank Li #include <linux/ptp_clock_kernel.h> 2274d23cc7SRichard Cochran #include <linux/timecounter.h> 2340c79ce1SWei Fang #include <dt-bindings/firmware/imx/rsrc.h> 2440c79ce1SWei Fang #include <linux/firmware/imx/sci.h> 256605b730SFrank Li 26ec21e2ecSJeff Kirsher #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 273f1dcc6aSLucas Stach defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2878cc6e7eSFlorian Fainelli defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 29ec21e2ecSJeff Kirsher /* 30ec21e2ecSJeff Kirsher * Just figures, Motorola would have to change the offsets for 31ec21e2ecSJeff Kirsher * registers in the same peripheral device on different models 32ec21e2ecSJeff Kirsher * of the ColdFire! 33ec21e2ecSJeff Kirsher */ 34ec21e2ecSJeff Kirsher #define FEC_IEVENT 0x004 /* Interrupt event reg */ 35ec21e2ecSJeff Kirsher #define FEC_IMASK 0x008 /* Interrupt mask reg */ 364d494cdcSFugang Duan #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */ 374d494cdcSFugang Duan #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */ 38ec21e2ecSJeff Kirsher #define FEC_ECNTRL 0x024 /* Ethernet control reg */ 39ec21e2ecSJeff Kirsher #define FEC_MII_DATA 0x040 /* MII manage frame reg */ 40ec21e2ecSJeff Kirsher #define FEC_MII_SPEED 0x044 /* MII speed control reg */ 41ec21e2ecSJeff Kirsher #define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */ 42ec21e2ecSJeff Kirsher #define FEC_R_CNTRL 0x084 /* Receive control reg */ 43ec21e2ecSJeff Kirsher #define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */ 44ec21e2ecSJeff Kirsher #define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */ 45ec21e2ecSJeff Kirsher #define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */ 46ec21e2ecSJeff Kirsher #define FEC_OPD 0x0ec /* Opcode + Pause duration */ 47745f42baSLothar Waßmann #define FEC_TXIC0 0x0f0 /* Tx Interrupt Coalescing for ring 0 */ 48745f42baSLothar Waßmann #define FEC_TXIC1 0x0f4 /* Tx Interrupt Coalescing for ring 1 */ 49745f42baSLothar Waßmann #define FEC_TXIC2 0x0f8 /* Tx Interrupt Coalescing for ring 2 */ 50ce99d0d3SFrank Li #define FEC_RXIC0 0x100 /* Rx Interrupt Coalescing for ring 0 */ 51ce99d0d3SFrank Li #define FEC_RXIC1 0x104 /* Rx Interrupt Coalescing for ring 1 */ 52ce99d0d3SFrank Li #define FEC_RXIC2 0x108 /* Rx Interrupt Coalescing for ring 2 */ 53ec21e2ecSJeff Kirsher #define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */ 54ec21e2ecSJeff Kirsher #define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */ 55ec21e2ecSJeff Kirsher #define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */ 56ec21e2ecSJeff Kirsher #define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */ 57ec21e2ecSJeff Kirsher #define FEC_X_WMRK 0x144 /* FIFO transmit water mark */ 58ec21e2ecSJeff Kirsher #define FEC_R_BOUND 0x14c /* FIFO receive bound reg */ 59ec21e2ecSJeff Kirsher #define FEC_R_FSTART 0x150 /* FIFO receive start reg */ 604d494cdcSFugang Duan #define FEC_R_DES_START_1 0x160 /* Receive descriptor ring 1 */ 614d494cdcSFugang Duan #define FEC_X_DES_START_1 0x164 /* Transmit descriptor ring 1 */ 62d543a762SNimrod Andy #define FEC_R_BUFF_SIZE_1 0x168 /* Maximum receive buff ring1 size */ 634d494cdcSFugang Duan #define FEC_R_DES_START_2 0x16c /* Receive descriptor ring 2 */ 644d494cdcSFugang Duan #define FEC_X_DES_START_2 0x170 /* Transmit descriptor ring 2 */ 65d543a762SNimrod Andy #define FEC_R_BUFF_SIZE_2 0x174 /* Maximum receive buff ring2 size */ 664d494cdcSFugang Duan #define FEC_R_DES_START_0 0x180 /* Receive descriptor ring */ 674d494cdcSFugang Duan #define FEC_X_DES_START_0 0x184 /* Transmit descriptor ring */ 68d543a762SNimrod Andy #define FEC_R_BUFF_SIZE_0 0x188 /* Maximum receive buff size */ 69baa70a5cSFrank Li #define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */ 70baa70a5cSFrank Li #define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */ 71baa70a5cSFrank Li #define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */ 72baa70a5cSFrank Li #define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */ 7355cd48c8STroy Kisky #define FEC_FTRL 0x1b0 /* Frame truncation receive length*/ 74745f42baSLothar Waßmann #define FEC_RACC 0x1c4 /* Receive Accelerator function */ 754d494cdcSFugang Duan #define FEC_RCMR_1 0x1c8 /* Receive classification match ring 1 */ 764d494cdcSFugang Duan #define FEC_RCMR_2 0x1cc /* Receive classification match ring 2 */ 774d494cdcSFugang Duan #define FEC_DMA_CFG_1 0x1d8 /* DMA class configuration for ring 1 */ 784d494cdcSFugang Duan #define FEC_DMA_CFG_2 0x1dc /* DMA class Configuration for ring 2 */ 794d494cdcSFugang Duan #define FEC_R_DES_ACTIVE_1 0x1e0 /* Rx descriptor active for ring 1 */ 804d494cdcSFugang Duan #define FEC_X_DES_ACTIVE_1 0x1e4 /* Tx descriptor active for ring 1 */ 814d494cdcSFugang Duan #define FEC_R_DES_ACTIVE_2 0x1e8 /* Rx descriptor active for ring 2 */ 824d494cdcSFugang Duan #define FEC_X_DES_ACTIVE_2 0x1ec /* Tx descriptor active for ring 2 */ 83ce99d0d3SFrank Li #define FEC_QOS_SCHEME 0x1f0 /* Set multi queues Qos scheme */ 84b82f8c3fSFugang Duan #define FEC_LPI_SLEEP 0x1f4 /* Set IEEE802.3az LPI Sleep Ts time */ 85b82f8c3fSFugang Duan #define FEC_LPI_WAKE 0x1f8 /* Set IEEE802.3az LPI Wake Tw time */ 86ec21e2ecSJeff Kirsher #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */ 87ec21e2ecSJeff Kirsher #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */ 88ec21e2ecSJeff Kirsher 898d82f219SEric Benard #define BM_MIIGSK_CFGR_MII 0x00 908d82f219SEric Benard #define BM_MIIGSK_CFGR_RMII 0x01 918d82f219SEric Benard #define BM_MIIGSK_CFGR_FRCONT_10M 0x40 928d82f219SEric Benard 9338ae92dcSChris Healy #define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */ 9438ae92dcSChris Healy #define RMON_T_PACKETS 0x204 /* RMON TX packet count */ 9538ae92dcSChris Healy #define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */ 96745f42baSLothar Waßmann #define RMON_T_MC_PKT 0x20c /* RMON TX multicast pkts */ 9738ae92dcSChris Healy #define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */ 9838ae92dcSChris Healy #define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */ 9938ae92dcSChris Healy #define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */ 100745f42baSLothar Waßmann #define RMON_T_FRAG 0x21c /* RMON TX pkts < 64 bytes, bad CRC */ 10138ae92dcSChris Healy #define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */ 10238ae92dcSChris Healy #define RMON_T_COL 0x224 /* RMON TX collision count */ 10338ae92dcSChris Healy #define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */ 104745f42baSLothar Waßmann #define RMON_T_P65TO127 0x22c /* RMON TX 65 to 127 byte pkts */ 10538ae92dcSChris Healy #define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */ 10638ae92dcSChris Healy #define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */ 10738ae92dcSChris Healy #define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */ 108745f42baSLothar Waßmann #define RMON_T_P1024TO2047 0x23c /* RMON TX 1024 to 2047 byte pkts */ 10938ae92dcSChris Healy #define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */ 11038ae92dcSChris Healy #define RMON_T_OCTETS 0x244 /* RMON TX octets */ 11138ae92dcSChris Healy #define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */ 112745f42baSLothar Waßmann #define IEEE_T_FRAME_OK 0x24c /* Frames tx'd OK */ 11338ae92dcSChris Healy #define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */ 11438ae92dcSChris Healy #define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */ 11538ae92dcSChris Healy #define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */ 116745f42baSLothar Waßmann #define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */ 11738ae92dcSChris Healy #define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */ 11838ae92dcSChris Healy #define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */ 11938ae92dcSChris Healy #define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */ 120745f42baSLothar Waßmann #define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */ 12138ae92dcSChris Healy #define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */ 12238ae92dcSChris Healy #define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */ 12338ae92dcSChris Healy #define RMON_R_PACKETS 0x284 /* RMON RX packet count */ 12438ae92dcSChris Healy #define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */ 125745f42baSLothar Waßmann #define RMON_R_MC_PKT 0x28c /* RMON RX multicast pkts */ 12638ae92dcSChris Healy #define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */ 12738ae92dcSChris Healy #define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */ 12838ae92dcSChris Healy #define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */ 129745f42baSLothar Waßmann #define RMON_R_FRAG 0x29c /* RMON RX pkts < 64 bytes, bad CRC */ 130745f42baSLothar Waßmann #define RMON_R_JAB 0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */ 131745f42baSLothar Waßmann #define RMON_R_RESVD_O 0x2a4 /* Reserved */ 132745f42baSLothar Waßmann #define RMON_R_P64 0x2a8 /* RMON RX 64 byte pkts */ 133745f42baSLothar Waßmann #define RMON_R_P65TO127 0x2ac /* RMON RX 65 to 127 byte pkts */ 134745f42baSLothar Waßmann #define RMON_R_P128TO255 0x2b0 /* RMON RX 128 to 255 byte pkts */ 135745f42baSLothar Waßmann #define RMON_R_P256TO511 0x2b4 /* RMON RX 256 to 511 byte pkts */ 136745f42baSLothar Waßmann #define RMON_R_P512TO1023 0x2b8 /* RMON RX 512 to 1023 byte pkts */ 137745f42baSLothar Waßmann #define RMON_R_P1024TO2047 0x2bc /* RMON RX 1024 to 2047 byte pkts */ 138745f42baSLothar Waßmann #define RMON_R_P_GTE2048 0x2c0 /* RMON RX pkts > 2048 bytes */ 139745f42baSLothar Waßmann #define RMON_R_OCTETS 0x2c4 /* RMON RX octets */ 140745f42baSLothar Waßmann #define IEEE_R_DROP 0x2c8 /* Count frames not counted correctly */ 141745f42baSLothar Waßmann #define IEEE_R_FRAME_OK 0x2cc /* Frames rx'd OK */ 142745f42baSLothar Waßmann #define IEEE_R_CRC 0x2d0 /* Frames rx'd with CRC err */ 143745f42baSLothar Waßmann #define IEEE_R_ALIGN 0x2d4 /* Frames rx'd with alignment err */ 144745f42baSLothar Waßmann #define IEEE_R_MACERR 0x2d8 /* Receive FIFO overflow count */ 145745f42baSLothar Waßmann #define IEEE_R_FDXFC 0x2dc /* Flow control pause frames rx'd */ 146745f42baSLothar Waßmann #define IEEE_R_OCTETS_OK 0x2e0 /* Octet cnt for frames rx'd w/o err */ 14738ae92dcSChris Healy 148ec21e2ecSJeff Kirsher #else 149ec21e2ecSJeff Kirsher 150ec21e2ecSJeff Kirsher #define FEC_ECNTRL 0x000 /* Ethernet control reg */ 151ec21e2ecSJeff Kirsher #define FEC_IEVENT 0x004 /* Interrupt even reg */ 152ec21e2ecSJeff Kirsher #define FEC_IMASK 0x008 /* Interrupt mask reg */ 153ec21e2ecSJeff Kirsher #define FEC_IVEC 0x00c /* Interrupt vec status reg */ 154bf3c228dSFrank Li #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */ 155bf3c228dSFrank Li #define FEC_R_DES_ACTIVE_1 FEC_R_DES_ACTIVE_0 156bf3c228dSFrank Li #define FEC_R_DES_ACTIVE_2 FEC_R_DES_ACTIVE_0 157bf3c228dSFrank Li #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */ 158bf3c228dSFrank Li #define FEC_X_DES_ACTIVE_1 FEC_X_DES_ACTIVE_0 159bf3c228dSFrank Li #define FEC_X_DES_ACTIVE_2 FEC_X_DES_ACTIVE_0 160ec21e2ecSJeff Kirsher #define FEC_MII_DATA 0x040 /* MII manage frame reg */ 161ec21e2ecSJeff Kirsher #define FEC_MII_SPEED 0x044 /* MII speed control reg */ 162ec21e2ecSJeff Kirsher #define FEC_R_BOUND 0x08c /* FIFO receive bound reg */ 163ec21e2ecSJeff Kirsher #define FEC_R_FSTART 0x090 /* FIFO receive start reg */ 164ec21e2ecSJeff Kirsher #define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */ 165ec21e2ecSJeff Kirsher #define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */ 166ec21e2ecSJeff Kirsher #define FEC_R_CNTRL 0x104 /* Receive control reg */ 167ec21e2ecSJeff Kirsher #define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */ 168ec21e2ecSJeff Kirsher #define FEC_X_CNTRL 0x144 /* Transmit Control reg */ 169ec21e2ecSJeff Kirsher #define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */ 170ec21e2ecSJeff Kirsher #define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */ 171ec21e2ecSJeff Kirsher #define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */ 172ec21e2ecSJeff Kirsher #define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */ 173bf3c228dSFrank Li #define FEC_R_DES_START_0 0x3d0 /* Receive descriptor ring */ 174bf3c228dSFrank Li #define FEC_R_DES_START_1 FEC_R_DES_START_0 175bf3c228dSFrank Li #define FEC_R_DES_START_2 FEC_R_DES_START_0 176bf3c228dSFrank Li #define FEC_X_DES_START_0 0x3d4 /* Transmit descriptor ring */ 177bf3c228dSFrank Li #define FEC_X_DES_START_1 FEC_X_DES_START_0 178bf3c228dSFrank Li #define FEC_X_DES_START_2 FEC_X_DES_START_0 179d543a762SNimrod Andy #define FEC_R_BUFF_SIZE_0 0x3d8 /* Maximum receive buff size */ 180d543a762SNimrod Andy #define FEC_R_BUFF_SIZE_1 FEC_R_BUFF_SIZE_0 181d543a762SNimrod Andy #define FEC_R_BUFF_SIZE_2 FEC_R_BUFF_SIZE_0 182ec21e2ecSJeff Kirsher #define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */ 183bf3c228dSFrank Li /* Not existed in real chip 184bf3c228dSFrank Li * Just for pass build. 185bf3c228dSFrank Li */ 186745f42baSLothar Waßmann #define FEC_RCMR_1 0xfff 187745f42baSLothar Waßmann #define FEC_RCMR_2 0xfff 188745f42baSLothar Waßmann #define FEC_DMA_CFG_1 0xfff 189745f42baSLothar Waßmann #define FEC_DMA_CFG_2 0xfff 190745f42baSLothar Waßmann #define FEC_TXIC0 0xfff 191745f42baSLothar Waßmann #define FEC_TXIC1 0xfff 192745f42baSLothar Waßmann #define FEC_TXIC2 0xfff 193745f42baSLothar Waßmann #define FEC_RXIC0 0xfff 194745f42baSLothar Waßmann #define FEC_RXIC1 0xfff 195745f42baSLothar Waßmann #define FEC_RXIC2 0xfff 196e08d6d42SJoakim Zhang #define FEC_LPI_SLEEP 0xfff 197e08d6d42SJoakim Zhang #define FEC_LPI_WAKE 0xfff 198ec21e2ecSJeff Kirsher #endif /* CONFIG_M5272 */ 199ec21e2ecSJeff Kirsher 200ec21e2ecSJeff Kirsher 201ec21e2ecSJeff Kirsher /* 202ec21e2ecSJeff Kirsher * Define the buffer descriptor structure. 2035cfa3039SJohannes Berg * 2045cfa3039SJohannes Berg * Evidently, ARM SoCs have the FEC block generated in a 20505f3b50eSJohannes Berg * little endian mode so adjust endianness accordingly. 206ec21e2ecSJeff Kirsher */ 2073f1dcc6aSLucas Stach #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 2085cfa3039SJohannes Berg #define fec32_to_cpu le32_to_cpu 2095cfa3039SJohannes Berg #define fec16_to_cpu le16_to_cpu 2105cfa3039SJohannes Berg #define cpu_to_fec32 cpu_to_le32 2115cfa3039SJohannes Berg #define cpu_to_fec16 cpu_to_le16 2125cfa3039SJohannes Berg #define __fec32 __le32 2135cfa3039SJohannes Berg #define __fec16 __le16 2145cfa3039SJohannes Berg 215ec21e2ecSJeff Kirsher struct bufdesc { 2165cfa3039SJohannes Berg __fec16 cbd_datlen; /* Data length */ 2175cfa3039SJohannes Berg __fec16 cbd_sc; /* Control and status info */ 2185cfa3039SJohannes Berg __fec32 cbd_bufaddr; /* Buffer address */ 219ff43da86SFrank Li }; 220acac8406SFrank Li #else 2215cfa3039SJohannes Berg #define fec32_to_cpu be32_to_cpu 2225cfa3039SJohannes Berg #define fec16_to_cpu be16_to_cpu 2235cfa3039SJohannes Berg #define cpu_to_fec32 cpu_to_be32 2245cfa3039SJohannes Berg #define cpu_to_fec16 cpu_to_be16 2255cfa3039SJohannes Berg #define __fec32 __be32 2265cfa3039SJohannes Berg #define __fec16 __be16 2275cfa3039SJohannes Berg 228acac8406SFrank Li struct bufdesc { 2295cfa3039SJohannes Berg __fec16 cbd_sc; /* Control and status info */ 2305cfa3039SJohannes Berg __fec16 cbd_datlen; /* Data length */ 2315cfa3039SJohannes Berg __fec32 cbd_bufaddr; /* Buffer address */ 232acac8406SFrank Li }; 233acac8406SFrank Li #endif 234ff43da86SFrank Li 235ff43da86SFrank Li struct bufdesc_ex { 236ff43da86SFrank Li struct bufdesc desc; 2375cfa3039SJohannes Berg __fec32 cbd_esc; 2385cfa3039SJohannes Berg __fec32 cbd_prot; 2395cfa3039SJohannes Berg __fec32 cbd_bdu; 2405cfa3039SJohannes Berg __fec32 ts; 2415cfa3039SJohannes Berg __fec16 res0[4]; 242ec21e2ecSJeff Kirsher }; 243ff43da86SFrank Li 244ec21e2ecSJeff Kirsher /* 245ec21e2ecSJeff Kirsher * The following definitions courtesy of commproc.h, which where 246ec21e2ecSJeff Kirsher * Copyright (c) 1997 Dan Malek (dmalek@jlc.net). 247ec21e2ecSJeff Kirsher */ 248ec21e2ecSJeff Kirsher #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ 249ec21e2ecSJeff Kirsher #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 250ec21e2ecSJeff Kirsher #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ 251ec21e2ecSJeff Kirsher #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 252ec21e2ecSJeff Kirsher #define BD_SC_CM ((ushort)0x0200) /* Continuous mode */ 253ec21e2ecSJeff Kirsher #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ 254ec21e2ecSJeff Kirsher #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 255ec21e2ecSJeff Kirsher #define BD_SC_BR ((ushort)0x0020) /* Break received */ 256ec21e2ecSJeff Kirsher #define BD_SC_FR ((ushort)0x0010) /* Framing error */ 257ec21e2ecSJeff Kirsher #define BD_SC_PR ((ushort)0x0008) /* Parity error */ 258ec21e2ecSJeff Kirsher #define BD_SC_OV ((ushort)0x0002) /* Overrun */ 259ec21e2ecSJeff Kirsher #define BD_SC_CD ((ushort)0x0001) /* ?? */ 260ec21e2ecSJeff Kirsher 261ec21e2ecSJeff Kirsher /* Buffer descriptor control/status used by Ethernet receive. 262ec21e2ecSJeff Kirsher */ 263ec21e2ecSJeff Kirsher #define BD_ENET_RX_EMPTY ((ushort)0x8000) 264ec21e2ecSJeff Kirsher #define BD_ENET_RX_WRAP ((ushort)0x2000) 265ec21e2ecSJeff Kirsher #define BD_ENET_RX_INTR ((ushort)0x1000) 266ec21e2ecSJeff Kirsher #define BD_ENET_RX_LAST ((ushort)0x0800) 267ec21e2ecSJeff Kirsher #define BD_ENET_RX_FIRST ((ushort)0x0400) 268ec21e2ecSJeff Kirsher #define BD_ENET_RX_MISS ((ushort)0x0100) 269ec21e2ecSJeff Kirsher #define BD_ENET_RX_LG ((ushort)0x0020) 270ec21e2ecSJeff Kirsher #define BD_ENET_RX_NO ((ushort)0x0010) 271ec21e2ecSJeff Kirsher #define BD_ENET_RX_SH ((ushort)0x0008) 272ec21e2ecSJeff Kirsher #define BD_ENET_RX_CR ((ushort)0x0004) 273ec21e2ecSJeff Kirsher #define BD_ENET_RX_OV ((ushort)0x0002) 274ec21e2ecSJeff Kirsher #define BD_ENET_RX_CL ((ushort)0x0001) 275ec21e2ecSJeff Kirsher #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ 276ec21e2ecSJeff Kirsher 277cdffcf1bSJim Baxter /* Enhanced buffer descriptor control/status used by Ethernet receive */ 278cdffcf1bSJim Baxter #define BD_ENET_RX_VLAN 0x00000004 279cdffcf1bSJim Baxter 280ec21e2ecSJeff Kirsher /* Buffer descriptor control/status used by Ethernet transmit. 281ec21e2ecSJeff Kirsher */ 282ec21e2ecSJeff Kirsher #define BD_ENET_TX_READY ((ushort)0x8000) 283ec21e2ecSJeff Kirsher #define BD_ENET_TX_PAD ((ushort)0x4000) 284ec21e2ecSJeff Kirsher #define BD_ENET_TX_WRAP ((ushort)0x2000) 285ec21e2ecSJeff Kirsher #define BD_ENET_TX_INTR ((ushort)0x1000) 286ec21e2ecSJeff Kirsher #define BD_ENET_TX_LAST ((ushort)0x0800) 287ec21e2ecSJeff Kirsher #define BD_ENET_TX_TC ((ushort)0x0400) 288ec21e2ecSJeff Kirsher #define BD_ENET_TX_DEF ((ushort)0x0200) 289ec21e2ecSJeff Kirsher #define BD_ENET_TX_HB ((ushort)0x0100) 290ec21e2ecSJeff Kirsher #define BD_ENET_TX_LC ((ushort)0x0080) 291ec21e2ecSJeff Kirsher #define BD_ENET_TX_RL ((ushort)0x0040) 292ec21e2ecSJeff Kirsher #define BD_ENET_TX_RCMASK ((ushort)0x003c) 293ec21e2ecSJeff Kirsher #define BD_ENET_TX_UN ((ushort)0x0002) 294ec21e2ecSJeff Kirsher #define BD_ENET_TX_CSL ((ushort)0x0001) 2956e909283SNimrod Andy #define BD_ENET_TX_STATS ((ushort)0x0fff) /* All status bits */ 296ec21e2ecSJeff Kirsher 2974c09eed9SJim Baxter /* enhanced buffer descriptor control/status used by Ethernet transmit */ 298405f257fSFrank Li #define BD_ENET_TX_INT 0x40000000 299405f257fSFrank Li #define BD_ENET_TX_TS 0x20000000 3004c09eed9SJim Baxter #define BD_ENET_TX_PINS 0x10000000 3014c09eed9SJim Baxter #define BD_ENET_TX_IINS 0x08000000 302405f257fSFrank Li 303405f257fSFrank Li 304405f257fSFrank Li /* This device has up to three irqs on some platforms */ 305405f257fSFrank Li #define FEC_IRQ_NUM 3 306405f257fSFrank Li 3074d494cdcSFugang Duan /* Maximum number of queues supported 3084d494cdcSFugang Duan * ENET with AVB IP can support up to 3 independent tx queues and rx queues. 3094d494cdcSFugang Duan * User can point the queue number that is less than or equal to 3. 3104d494cdcSFugang Duan */ 3114d494cdcSFugang Duan #define FEC_ENET_MAX_TX_QS 3 3124d494cdcSFugang Duan #define FEC_ENET_MAX_RX_QS 3 3134d494cdcSFugang Duan 314df406bc9SLothar Waßmann #define FEC_R_DES_START(X) (((X) == 1) ? FEC_R_DES_START_1 : \ 315df406bc9SLothar Waßmann (((X) == 2) ? \ 3164d494cdcSFugang Duan FEC_R_DES_START_2 : FEC_R_DES_START_0)) 317df406bc9SLothar Waßmann #define FEC_X_DES_START(X) (((X) == 1) ? FEC_X_DES_START_1 : \ 318df406bc9SLothar Waßmann (((X) == 2) ? \ 3194d494cdcSFugang Duan FEC_X_DES_START_2 : FEC_X_DES_START_0)) 320d543a762SNimrod Andy #define FEC_R_BUFF_SIZE(X) (((X) == 1) ? FEC_R_BUFF_SIZE_1 : \ 321d543a762SNimrod Andy (((X) == 2) ? \ 322d543a762SNimrod Andy FEC_R_BUFF_SIZE_2 : FEC_R_BUFF_SIZE_0)) 3234d494cdcSFugang Duan 324df406bc9SLothar Waßmann #define FEC_DMA_CFG(X) (((X) == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1) 3254d494cdcSFugang Duan 3264d494cdcSFugang Duan #define DMA_CLASS_EN (1 << 16) 327df406bc9SLothar Waßmann #define FEC_RCMR(X) (((X) == 2) ? FEC_RCMR_2 : FEC_RCMR_1) 328745f42baSLothar Waßmann #define IDLE_SLOPE_MASK 0xffff 3294d494cdcSFugang Duan #define IDLE_SLOPE_1 0x200 /* BW fraction: 0.5 */ 3304d494cdcSFugang Duan #define IDLE_SLOPE_2 0x200 /* BW fraction: 0.5 */ 331df406bc9SLothar Waßmann #define IDLE_SLOPE(X) (((X) == 1) ? \ 332df406bc9SLothar Waßmann (IDLE_SLOPE_1 & IDLE_SLOPE_MASK) : \ 3334d494cdcSFugang Duan (IDLE_SLOPE_2 & IDLE_SLOPE_MASK)) 3344d494cdcSFugang Duan #define RCMR_MATCHEN (0x1 << 16) 335df406bc9SLothar Waßmann #define RCMR_CMP_CFG(v, n) (((v) & 0x7) << (n << 2)) 3364d494cdcSFugang Duan #define RCMR_CMP_1 (RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \ 3374d494cdcSFugang Duan RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3)) 3384d494cdcSFugang Duan #define RCMR_CMP_2 (RCMR_CMP_CFG(4, 0) | RCMR_CMP_CFG(5, 1) | \ 3394d494cdcSFugang Duan RCMR_CMP_CFG(6, 2) | RCMR_CMP_CFG(7, 3)) 340df406bc9SLothar Waßmann #define RCMR_CMP(X) (((X) == 1) ? RCMR_CMP_1 : RCMR_CMP_2) 341df406bc9SLothar Waßmann #define FEC_TX_BD_FTYPE(X) (((X) & 0xf) << 20) 3424d494cdcSFugang Duan 343405f257fSFrank Li /* The number of Tx and Rx buffers. These are allocated from the page 344405f257fSFrank Li * pool. The code may assume these are power of two, so it it best 345405f257fSFrank Li * to keep them that size. 346405f257fSFrank Li * We don't need to allocate pages for the transmitter. We just use 347405f257fSFrank Li * the skbuffer directly. 348405f257fSFrank Li */ 349405f257fSFrank Li 350*95698ff6SShenwei Wang #define FEC_ENET_XDP_HEADROOM (XDP_PACKET_HEADROOM) 351*95698ff6SShenwei Wang 35273e72289SFugang Duan #define FEC_ENET_RX_PAGES 256 353*95698ff6SShenwei Wang #define FEC_ENET_RX_FRSIZE (PAGE_SIZE - FEC_ENET_XDP_HEADROOM \ 354*95698ff6SShenwei Wang - SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 355405f257fSFrank Li #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) 356405f257fSFrank Li #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) 357405f257fSFrank Li #define FEC_ENET_TX_FRSIZE 2048 358405f257fSFrank Li #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) 35955d0218aSNimrod Andy #define TX_RING_SIZE 512 /* Must be power of two */ 36055d0218aSNimrod Andy #define TX_RING_MOD_MASK 511 /* for this to work */ 361405f257fSFrank Li 362405f257fSFrank Li #define BD_ENET_RX_INT 0x00800000 363405f257fSFrank Li #define BD_ENET_RX_PTP ((ushort)0x0400) 3644c09eed9SJim Baxter #define BD_ENET_RX_ICE 0x00000020 3654c09eed9SJim Baxter #define BD_ENET_RX_PCR 0x00000010 3664c09eed9SJim Baxter #define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE | BD_ENET_RX_PCR) 3674c09eed9SJim Baxter #define FLAG_RX_CSUM_ERROR (BD_ENET_RX_ICE | BD_ENET_RX_PCR) 368405f257fSFrank Li 369ce99d0d3SFrank Li /* Interrupt events/masks. */ 370ce99d0d3SFrank Li #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ 371ce99d0d3SFrank Li #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ 372ce99d0d3SFrank Li #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ 373ce99d0d3SFrank Li #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ 374ce99d0d3SFrank Li #define FEC_ENET_TXF_0 ((uint)0x08000000) /* Full frame transmitted */ 375ce99d0d3SFrank Li #define FEC_ENET_TXF_1 ((uint)0x00000008) /* Full frame transmitted */ 376ce99d0d3SFrank Li #define FEC_ENET_TXF_2 ((uint)0x00000080) /* Full frame transmitted */ 377ce99d0d3SFrank Li #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ 378ce99d0d3SFrank Li #define FEC_ENET_RXF_0 ((uint)0x02000000) /* Full frame received */ 379ce99d0d3SFrank Li #define FEC_ENET_RXF_1 ((uint)0x00000002) /* Full frame received */ 380ce99d0d3SFrank Li #define FEC_ENET_RXF_2 ((uint)0x00000020) /* Full frame received */ 381ce99d0d3SFrank Li #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ 382ce99d0d3SFrank Li #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ 383ce99d0d3SFrank Li #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ 384de40ed31SNimrod Andy #define FEC_ENET_WAKEUP ((uint)0x00020000) /* Wakeup request */ 385ce99d0d3SFrank Li #define FEC_ENET_TXF (FEC_ENET_TXF_0 | FEC_ENET_TXF_1 | FEC_ENET_TXF_2) 386ce99d0d3SFrank Li #define FEC_ENET_RXF (FEC_ENET_RXF_0 | FEC_ENET_RXF_1 | FEC_ENET_RXF_2) 387b5bd95d1SJoakim Zhang #define FEC_ENET_RXF_GET(X) (((X) == 0) ? FEC_ENET_RXF_0 : \ 388b5bd95d1SJoakim Zhang (((X) == 1) ? FEC_ENET_RXF_1 : \ 389b5bd95d1SJoakim Zhang FEC_ENET_RXF_2)) 390ce99d0d3SFrank Li #define FEC_ENET_TS_AVAIL ((uint)0x00010000) 391ce99d0d3SFrank Li #define FEC_ENET_TS_TIMER ((uint)0x00008000) 392ce99d0d3SFrank Li 393f166f890SAndrew Lunn #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF) 394ce99d0d3SFrank Li #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) 395ce99d0d3SFrank Li 396fc539459SFugang Duan #define FEC_ENET_TXC_DLY ((uint)0x00010000) 397fc539459SFugang Duan #define FEC_ENET_RXC_DLY ((uint)0x00020000) 398fc539459SFugang Duan 399d851b47bSFugang Duan /* ENET interrupt coalescing macro define */ 400d851b47bSFugang Duan #define FEC_ITR_CLK_SEL (0x1 << 30) 401d851b47bSFugang Duan #define FEC_ITR_EN (0x1 << 31) 402df406bc9SLothar Waßmann #define FEC_ITR_ICFT(X) (((X) & 0xff) << 20) 403745f42baSLothar Waßmann #define FEC_ITR_ICTT(X) ((X) & 0xffff) 404d851b47bSFugang Duan #define FEC_ITR_ICFT_DEFAULT 200 /* Set 200 frame count threshold */ 405d851b47bSFugang Duan #define FEC_ITR_ICTT_DEFAULT 1000 /* Set 1000us timer threshold */ 406d851b47bSFugang Duan 407ce99d0d3SFrank Li #define FEC_VLAN_TAG_LEN 0x04 408ce99d0d3SFrank Li #define FEC_ETHTYPE_LEN 0x02 409ce99d0d3SFrank Li 41028b5f058SNimrod Andy /* Controller is ENET-MAC */ 41128b5f058SNimrod Andy #define FEC_QUIRK_ENET_MAC (1 << 0) 41228b5f058SNimrod Andy /* Controller needs driver to swap frame */ 41328b5f058SNimrod Andy #define FEC_QUIRK_SWAP_FRAME (1 << 1) 41428b5f058SNimrod Andy /* Controller uses gasket */ 41528b5f058SNimrod Andy #define FEC_QUIRK_USE_GASKET (1 << 2) 41628b5f058SNimrod Andy /* Controller has GBIT support */ 41728b5f058SNimrod Andy #define FEC_QUIRK_HAS_GBIT (1 << 3) 41828b5f058SNimrod Andy /* Controller has extend desc buffer */ 41928b5f058SNimrod Andy #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) 42028b5f058SNimrod Andy /* Controller has hardware checksum support */ 42128b5f058SNimrod Andy #define FEC_QUIRK_HAS_CSUM (1 << 5) 42228b5f058SNimrod Andy /* Controller has hardware vlan support */ 42328b5f058SNimrod Andy #define FEC_QUIRK_HAS_VLAN (1 << 6) 42428b5f058SNimrod Andy /* ENET IP errata ERR006358 42528b5f058SNimrod Andy * 42628b5f058SNimrod Andy * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously 42728b5f058SNimrod Andy * detected as not set during a prior frame transmission, then the 42828b5f058SNimrod Andy * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs 42928b5f058SNimrod Andy * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in 43028b5f058SNimrod Andy * frames not being transmitted until there is a 0-to-1 transition on 43128b5f058SNimrod Andy * ENET_TDAR[TDAR]. 43228b5f058SNimrod Andy */ 43328b5f058SNimrod Andy #define FEC_QUIRK_ERR006358 (1 << 7) 43428b5f058SNimrod Andy /* ENET IP hw AVB 43528b5f058SNimrod Andy * 43628b5f058SNimrod Andy * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support. 43728b5f058SNimrod Andy * - Two class indicators on receive with configurable priority 43828b5f058SNimrod Andy * - Two class indicators and line speed timer on transmit allowing 43928b5f058SNimrod Andy * implementation class credit based shapers externally 44028b5f058SNimrod Andy * - Additional DMA registers provisioned to allow managing up to 3 44128b5f058SNimrod Andy * independent rings 44228b5f058SNimrod Andy */ 44328b5f058SNimrod Andy #define FEC_QUIRK_HAS_AVB (1 << 8) 44428b5f058SNimrod Andy /* There is a TDAR race condition for mutliQ when the software sets TDAR 44528b5f058SNimrod Andy * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles). 44628b5f058SNimrod Andy * This will cause the udma_tx and udma_tx_arbiter state machines to hang. 44728b5f058SNimrod Andy * The issue exist at i.MX6SX enet IP. 44828b5f058SNimrod Andy */ 44928b5f058SNimrod Andy #define FEC_QUIRK_ERR007885 (1 << 9) 45028b5f058SNimrod Andy /* ENET Block Guide/ Chapter for the iMX6SX (PELE) address one issue: 45128b5f058SNimrod Andy * After set ENET_ATCR[Capture], there need some time cycles before the counter 45228b5f058SNimrod Andy * value is capture in the register clock domain. 45328b5f058SNimrod Andy * The wait-time-cycles is at least 6 clock cycles of the slower clock between 45428b5f058SNimrod Andy * the register clock and the 1588 clock. The 1588 ts_clk is fixed to 25Mhz, 45528b5f058SNimrod Andy * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns 45628b5f058SNimrod Andy * (40ns * 6). 45728b5f058SNimrod Andy */ 45828b5f058SNimrod Andy #define FEC_QUIRK_BUG_CAPTURE (1 << 10) 4593d125f9cSStefan Agner /* Controller has only one MDIO bus */ 4603d125f9cSStefan Agner #define FEC_QUIRK_SINGLE_MDIO (1 << 11) 46118803495SGreg Ungerer /* Controller supports RACC register */ 46218803495SGreg Ungerer #define FEC_QUIRK_HAS_RACC (1 << 12) 463ff7566b8SFugang Duan /* Controller supports interrupt coalesc */ 464ff7566b8SFugang Duan #define FEC_QUIRK_HAS_COALESCE (1 << 13) 46529380905SLucas Stach /* Interrupt doesn't wake CPU from deep idle */ 466fbae5cbbSLinus Torvalds #define FEC_QUIRK_ERR006687 (1 << 14) 4672b30842bSAndrew Lunn /* The MIB counters should be cleared and enabled during 4682b30842bSAndrew Lunn * initialisation. 4692b30842bSAndrew Lunn */ 4702b30842bSAndrew Lunn #define FEC_QUIRK_MIB_CLEAR (1 << 15) 471ec20a63aSFugang Duan /* Only i.MX25/i.MX27/i.MX28 controller supports FRBR,FRSR registers, 472ec20a63aSFugang Duan * those FIFO receive registers are resolved in other platforms. 473ec20a63aSFugang Duan */ 474ec20a63aSFugang Duan #define FEC_QUIRK_HAS_FRREG (1 << 16) 47528b5f058SNimrod Andy 4761e6114f5SGreg Ungerer /* Some FEC hardware blocks need the MMFR cleared at setup time to avoid 4771e6114f5SGreg Ungerer * the generation of an MII event. This must be avoided in the older 4781e6114f5SGreg Ungerer * FEC blocks where it will stop MII events being generated. 4791e6114f5SGreg Ungerer */ 4801e6114f5SGreg Ungerer #define FEC_QUIRK_CLEAR_SETUP_MII (1 << 17) 4811e6114f5SGreg Ungerer 482c730ab42SLaurent Badel /* Some link partners do not tolerate the momentary reset of the REF_CLK 483c730ab42SLaurent Badel * frequency when the RNCTL register is cleared by hardware reset. 484c730ab42SLaurent Badel */ 485c730ab42SLaurent Badel #define FEC_QUIRK_NO_HARD_RESET (1 << 18) 486c730ab42SLaurent Badel 487471ff445SJoakim Zhang /* i.MX6SX ENET IP supports multiple queues (3 queues), use this quirk to 488471ff445SJoakim Zhang * represents this ENET IP. 489471ff445SJoakim Zhang */ 490471ff445SJoakim Zhang #define FEC_QUIRK_HAS_MULTI_QUEUES (1 << 19) 491471ff445SJoakim Zhang 492947240ebSFugang Duan /* i.MX8MQ ENET IP version add new feature to support IEEE 802.3az EEE 493947240ebSFugang Duan * standard. For the transmission, MAC supply two user registers to set 494947240ebSFugang Duan * Sleep (TS) and Wake (TW) time. 495947240ebSFugang Duan */ 496947240ebSFugang Duan #define FEC_QUIRK_HAS_EEE (1 << 20) 497947240ebSFugang Duan 498947240ebSFugang Duan /* i.MX8QM ENET IP version add new feture to generate delayed TXC/RXC 499947240ebSFugang Duan * as an alternative option to make sure it works well with various PHYs. 500947240ebSFugang Duan * For the implementation of delayed clock, ENET takes synchronized 250MHz 501947240ebSFugang Duan * clocks to generate 2ns delay. 502947240ebSFugang Duan */ 503947240ebSFugang Duan #define FEC_QUIRK_DELAYED_CLKS_SUPPORT (1 << 21) 504947240ebSFugang Duan 505b7cdc965SJoakim Zhang /* i.MX8MQ SoC integration mix wakeup interrupt signal into "int2" interrupt line. */ 506b7cdc965SJoakim Zhang #define FEC_QUIRK_WAKEUP_FROM_INT2 (1 << 22) 507b7cdc965SJoakim Zhang 5087d650df9SWei Fang /* i.MX6Q adds pm_qos support */ 5097d650df9SWei Fang #define FEC_QUIRK_HAS_PMQOS BIT(23) 5107d650df9SWei Fang 5117355f276STroy Kisky struct bufdesc_prop { 5127355f276STroy Kisky int qid; 5137355f276STroy Kisky /* Address of Rx and Tx buffers */ 5147355f276STroy Kisky struct bufdesc *base; 5157355f276STroy Kisky struct bufdesc *last; 5167355f276STroy Kisky struct bufdesc *cur; 51753bb20d1STroy Kisky void __iomem *reg_desc_active; 5187355f276STroy Kisky dma_addr_t dma; 5197355f276STroy Kisky unsigned short ring_size; 5207355f276STroy Kisky unsigned char dsize; 5217355f276STroy Kisky unsigned char dsize_log2; 5227355f276STroy Kisky }; 5237355f276STroy Kisky 524*95698ff6SShenwei Wang struct fec_enet_priv_txrx_info { 525*95698ff6SShenwei Wang int offset; 526*95698ff6SShenwei Wang struct page *page; 527*95698ff6SShenwei Wang struct sk_buff *skb; 528*95698ff6SShenwei Wang }; 529*95698ff6SShenwei Wang 5304d494cdcSFugang Duan struct fec_enet_priv_tx_q { 5317355f276STroy Kisky struct bufdesc_prop bd; 5324d494cdcSFugang Duan unsigned char *tx_bounce[TX_RING_SIZE]; 5334d494cdcSFugang Duan struct sk_buff *tx_skbuff[TX_RING_SIZE]; 5344d494cdcSFugang Duan 5354d494cdcSFugang Duan unsigned short tx_stop_threshold; 5364d494cdcSFugang Duan unsigned short tx_wake_threshold; 5374d494cdcSFugang Duan 5384d494cdcSFugang Duan struct bufdesc *dirty_tx; 5394d494cdcSFugang Duan char *tso_hdrs; 5404d494cdcSFugang Duan dma_addr_t tso_hdrs_dma; 5414d494cdcSFugang Duan }; 5424d494cdcSFugang Duan 5434d494cdcSFugang Duan struct fec_enet_priv_rx_q { 5447355f276STroy Kisky struct bufdesc_prop bd; 545*95698ff6SShenwei Wang struct fec_enet_priv_txrx_info rx_skb_info[RX_RING_SIZE]; 546*95698ff6SShenwei Wang 547*95698ff6SShenwei Wang /* page_pool */ 548*95698ff6SShenwei Wang struct page_pool *page_pool; 549*95698ff6SShenwei Wang struct xdp_rxq_info xdp_rxq; 550*95698ff6SShenwei Wang 551*95698ff6SShenwei Wang /* rx queue number, in the range 0-7 */ 552*95698ff6SShenwei Wang u8 id; 5534d494cdcSFugang Duan }; 5544d494cdcSFugang Duan 555da722186SMartin Fuzzey struct fec_stop_mode_gpr { 556da722186SMartin Fuzzey struct regmap *gpr; 557da722186SMartin Fuzzey u8 reg; 558da722186SMartin Fuzzey u8 bit; 559da722186SMartin Fuzzey }; 560da722186SMartin Fuzzey 561405f257fSFrank Li /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and 562405f257fSFrank Li * tx_bd_base always point to the base of the buffer descriptors. The 563405f257fSFrank Li * cur_rx and cur_tx point to the currently available buffer. 564405f257fSFrank Li * The dirty_tx tracks the current buffer that is being sent by the 565405f257fSFrank Li * controller. The cur_tx and dirty_tx are equal under both completely 566405f257fSFrank Li * empty and completely full conditions. The empty/ready indicator in 567405f257fSFrank Li * the buffer descriptor determines the actual condition. 568405f257fSFrank Li */ 569405f257fSFrank Li struct fec_enet_private { 570405f257fSFrank Li /* Hardware registers of the FEC device */ 571405f257fSFrank Li void __iomem *hwp; 572405f257fSFrank Li 573405f257fSFrank Li struct net_device *netdev; 574405f257fSFrank Li 575405f257fSFrank Li struct clk *clk_ipg; 576405f257fSFrank Li struct clk *clk_ahb; 5779b5330edSFugang Duan struct clk *clk_ref; 578daa7d392SWolfram Sang struct clk *clk_enet_out; 5796605b730SFrank Li struct clk *clk_ptp; 580fc539459SFugang Duan struct clk *clk_2x_txclk; 581405f257fSFrank Li 58291c0d987SNimrod Andy bool ptp_clk_on; 58301b825f9SFrancesco Dolcini struct mutex ptp_clk_mutex; 5849fc095f1SFugang Duan unsigned int num_tx_queues; 5859fc095f1SFugang Duan unsigned int num_rx_queues; 58691c0d987SNimrod Andy 587405f257fSFrank Li /* The saved address of a sent-in-place packet/buffer, for skfree(). */ 5884d494cdcSFugang Duan struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS]; 5894d494cdcSFugang Duan struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS]; 590405f257fSFrank Li 5914d494cdcSFugang Duan unsigned int total_tx_ring_size; 5924d494cdcSFugang Duan unsigned int total_rx_ring_size; 5934d494cdcSFugang Duan 594405f257fSFrank Li struct platform_device *pdev; 595405f257fSFrank Li 596405f257fSFrank Li int dev_id; 597405f257fSFrank Li 598405f257fSFrank Li /* Phylib and MDIO interface */ 599405f257fSFrank Li struct mii_bus *mii_bus; 600405f257fSFrank Li uint phy_speed; 601405f257fSFrank Li phy_interface_t phy_interface; 602407066f8SUwe Kleine-König struct device_node *phy_node; 603fc539459SFugang Duan bool rgmii_txc_dly; 604fc539459SFugang Duan bool rgmii_rxc_dly; 605da970726SWei Fang bool rpm_active; 606405f257fSFrank Li int link; 607405f257fSFrank Li int full_duplex; 608d97e7497SLucas Stach int speed; 609405f257fSFrank Li int irq[FEC_IRQ_NUM]; 610217b5844SLothar Waßmann bool bufdesc_ex; 611baa70a5cSFrank Li int pause_flag; 612de40ed31SNimrod Andy int wol_flag; 613b7cdc965SJoakim Zhang int wake_irq; 6146b7e4008SLothar Waßmann u32 quirks; 6156605b730SFrank Li 616dc975382SFrank Li struct napi_struct napi; 6174c09eed9SJim Baxter int csum_flags; 618dc975382SFrank Li 61936cdc743SRussell King struct work_struct tx_timeout_work; 62036cdc743SRussell King 6216605b730SFrank Li struct ptp_clock *ptp_clock; 6226605b730SFrank Li struct ptp_clock_info ptp_caps; 6236605b730SFrank Li unsigned long last_overflow_check; 6246605b730SFrank Li spinlock_t tmreg_lock; 6256605b730SFrank Li struct cyclecounter cc; 6266605b730SFrank Li struct timecounter tc; 6276605b730SFrank Li int rx_hwtstamp_filter; 6286605b730SFrank Li u32 base_incval; 6296605b730SFrank Li u32 cycle_speed; 6306605b730SFrank Li int hwts_rx_en; 6316605b730SFrank Li int hwts_tx_en; 63291c0d987SNimrod Andy struct delayed_work time_keep; 633f4e9f3d2SFabio Estevam struct regulator *reg_phy; 634da722186SMartin Fuzzey struct fec_stop_mode_gpr stop_gpr; 6357d650df9SWei Fang struct pm_qos_request pm_qos_req; 63641ef84ceSFugang Duan 63741ef84ceSFugang Duan unsigned int tx_align; 63841ef84ceSFugang Duan unsigned int rx_align; 639d851b47bSFugang Duan 640d851b47bSFugang Duan /* hw interrupt coalesce */ 641d851b47bSFugang Duan unsigned int rx_pkts_itr; 642d851b47bSFugang Duan unsigned int rx_time_itr; 643d851b47bSFugang Duan unsigned int tx_pkts_itr; 644d851b47bSFugang Duan unsigned int tx_time_itr; 645d851b47bSFugang Duan unsigned int itr_clk_rate; 6461b7bde6dSNimrod Andy 647b82f8c3fSFugang Duan /* tx lpi eee mode */ 648b82f8c3fSFugang Duan struct ethtool_eee eee; 649b82f8c3fSFugang Duan unsigned int clk_ref_rate; 650b82f8c3fSFugang Duan 6511b7bde6dSNimrod Andy u32 rx_copybreak; 65289bddcdaSLuwei Zhou 65389bddcdaSLuwei Zhou /* ptp clock period in ns*/ 65489bddcdaSLuwei Zhou unsigned int ptp_inc; 655278d2404SLuwei Zhou 656278d2404SLuwei Zhou /* pps */ 657278d2404SLuwei Zhou int pps_channel; 658278d2404SLuwei Zhou unsigned int reload_period; 659278d2404SLuwei Zhou int pps_enable; 660278d2404SLuwei Zhou unsigned int next_counter; 66180cca775SNikita Yushchenko 66240c79ce1SWei Fang struct imx_sc_ipc *ipc_handle; 66340c79ce1SWei Fang 664cc5b48b5SGustavo A. R. Silva u64 ethtool_stats[]; 665405f257fSFrank Li }; 666ec21e2ecSJeff Kirsher 6674ad1ceecSTroy Kisky void fec_ptp_init(struct platform_device *pdev, int irq_idx); 66832cba57bSLucas Stach void fec_ptp_stop(struct platform_device *pdev); 6696605b730SFrank Li void fec_ptp_start_cyclecounter(struct net_device *ndev); 67034074639SSergey Organov void fec_ptp_disable_hwts(struct net_device *ndev); 6711d5244d0SBen Hutchings int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr); 6721d5244d0SBen Hutchings int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr); 6736605b730SFrank Li 674ec21e2ecSJeff Kirsher /****************************************************************************/ 675ec21e2ecSJeff Kirsher #endif /* FEC_H */ 676