1ec21e2ecSJeff Kirsher /****************************************************************************/ 2ec21e2ecSJeff Kirsher 3ec21e2ecSJeff Kirsher /* 4ec21e2ecSJeff Kirsher * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC 5ec21e2ecSJeff Kirsher * processors. 6ec21e2ecSJeff Kirsher * 7ec21e2ecSJeff Kirsher * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com) 8ec21e2ecSJeff Kirsher * (C) Copyright 2000-2001, Lineo (www.lineo.com) 9ec21e2ecSJeff Kirsher */ 10ec21e2ecSJeff Kirsher 11ec21e2ecSJeff Kirsher /****************************************************************************/ 12ec21e2ecSJeff Kirsher #ifndef FEC_H 13ec21e2ecSJeff Kirsher #define FEC_H 14ec21e2ecSJeff Kirsher /****************************************************************************/ 15ec21e2ecSJeff Kirsher 166605b730SFrank Li #include <linux/clocksource.h> 176605b730SFrank Li #include <linux/net_tstamp.h> 186605b730SFrank Li #include <linux/ptp_clock_kernel.h> 196605b730SFrank Li 20ec21e2ecSJeff Kirsher #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 21ec21e2ecSJeff Kirsher defined(CONFIG_M520x) || defined(CONFIG_M532x) || \ 22ec21e2ecSJeff Kirsher defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) 23ec21e2ecSJeff Kirsher /* 24ec21e2ecSJeff Kirsher * Just figures, Motorola would have to change the offsets for 25ec21e2ecSJeff Kirsher * registers in the same peripheral device on different models 26ec21e2ecSJeff Kirsher * of the ColdFire! 27ec21e2ecSJeff Kirsher */ 28ec21e2ecSJeff Kirsher #define FEC_IEVENT 0x004 /* Interrupt event reg */ 29ec21e2ecSJeff Kirsher #define FEC_IMASK 0x008 /* Interrupt mask reg */ 304d494cdcSFugang Duan #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */ 314d494cdcSFugang Duan #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */ 32ec21e2ecSJeff Kirsher #define FEC_ECNTRL 0x024 /* Ethernet control reg */ 33ec21e2ecSJeff Kirsher #define FEC_MII_DATA 0x040 /* MII manage frame reg */ 34ec21e2ecSJeff Kirsher #define FEC_MII_SPEED 0x044 /* MII speed control reg */ 35ec21e2ecSJeff Kirsher #define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */ 36ec21e2ecSJeff Kirsher #define FEC_R_CNTRL 0x084 /* Receive control reg */ 37ec21e2ecSJeff Kirsher #define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */ 38ec21e2ecSJeff Kirsher #define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */ 39ec21e2ecSJeff Kirsher #define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */ 40ec21e2ecSJeff Kirsher #define FEC_OPD 0x0ec /* Opcode + Pause duration */ 41745f42baSLothar Waßmann #define FEC_TXIC0 0x0f0 /* Tx Interrupt Coalescing for ring 0 */ 42745f42baSLothar Waßmann #define FEC_TXIC1 0x0f4 /* Tx Interrupt Coalescing for ring 1 */ 43745f42baSLothar Waßmann #define FEC_TXIC2 0x0f8 /* Tx Interrupt Coalescing for ring 2 */ 44ce99d0d3SFrank Li #define FEC_RXIC0 0x100 /* Rx Interrupt Coalescing for ring 0 */ 45ce99d0d3SFrank Li #define FEC_RXIC1 0x104 /* Rx Interrupt Coalescing for ring 1 */ 46ce99d0d3SFrank Li #define FEC_RXIC2 0x108 /* Rx Interrupt Coalescing for ring 2 */ 47ec21e2ecSJeff Kirsher #define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */ 48ec21e2ecSJeff Kirsher #define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */ 49ec21e2ecSJeff Kirsher #define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */ 50ec21e2ecSJeff Kirsher #define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */ 51ec21e2ecSJeff Kirsher #define FEC_X_WMRK 0x144 /* FIFO transmit water mark */ 52ec21e2ecSJeff Kirsher #define FEC_R_BOUND 0x14c /* FIFO receive bound reg */ 53ec21e2ecSJeff Kirsher #define FEC_R_FSTART 0x150 /* FIFO receive start reg */ 544d494cdcSFugang Duan #define FEC_R_DES_START_1 0x160 /* Receive descriptor ring 1 */ 554d494cdcSFugang Duan #define FEC_X_DES_START_1 0x164 /* Transmit descriptor ring 1 */ 564d494cdcSFugang Duan #define FEC_R_DES_START_2 0x16c /* Receive descriptor ring 2 */ 574d494cdcSFugang Duan #define FEC_X_DES_START_2 0x170 /* Transmit descriptor ring 2 */ 584d494cdcSFugang Duan #define FEC_R_DES_START_0 0x180 /* Receive descriptor ring */ 594d494cdcSFugang Duan #define FEC_X_DES_START_0 0x184 /* Transmit descriptor ring */ 60ec21e2ecSJeff Kirsher #define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */ 61baa70a5cSFrank Li #define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */ 62baa70a5cSFrank Li #define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */ 63baa70a5cSFrank Li #define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */ 64baa70a5cSFrank Li #define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */ 65745f42baSLothar Waßmann #define FEC_RACC 0x1c4 /* Receive Accelerator function */ 664d494cdcSFugang Duan #define FEC_RCMR_1 0x1c8 /* Receive classification match ring 1 */ 674d494cdcSFugang Duan #define FEC_RCMR_2 0x1cc /* Receive classification match ring 2 */ 684d494cdcSFugang Duan #define FEC_DMA_CFG_1 0x1d8 /* DMA class configuration for ring 1 */ 694d494cdcSFugang Duan #define FEC_DMA_CFG_2 0x1dc /* DMA class Configuration for ring 2 */ 704d494cdcSFugang Duan #define FEC_R_DES_ACTIVE_1 0x1e0 /* Rx descriptor active for ring 1 */ 714d494cdcSFugang Duan #define FEC_X_DES_ACTIVE_1 0x1e4 /* Tx descriptor active for ring 1 */ 724d494cdcSFugang Duan #define FEC_R_DES_ACTIVE_2 0x1e8 /* Rx descriptor active for ring 2 */ 734d494cdcSFugang Duan #define FEC_X_DES_ACTIVE_2 0x1ec /* Tx descriptor active for ring 2 */ 74ce99d0d3SFrank Li #define FEC_QOS_SCHEME 0x1f0 /* Set multi queues Qos scheme */ 75ec21e2ecSJeff Kirsher #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */ 76ec21e2ecSJeff Kirsher #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */ 77ec21e2ecSJeff Kirsher 788d82f219SEric Benard #define BM_MIIGSK_CFGR_MII 0x00 798d82f219SEric Benard #define BM_MIIGSK_CFGR_RMII 0x01 808d82f219SEric Benard #define BM_MIIGSK_CFGR_FRCONT_10M 0x40 818d82f219SEric Benard 8238ae92dcSChris Healy #define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */ 8338ae92dcSChris Healy #define RMON_T_PACKETS 0x204 /* RMON TX packet count */ 8438ae92dcSChris Healy #define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */ 85745f42baSLothar Waßmann #define RMON_T_MC_PKT 0x20c /* RMON TX multicast pkts */ 8638ae92dcSChris Healy #define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */ 8738ae92dcSChris Healy #define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */ 8838ae92dcSChris Healy #define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */ 89745f42baSLothar Waßmann #define RMON_T_FRAG 0x21c /* RMON TX pkts < 64 bytes, bad CRC */ 9038ae92dcSChris Healy #define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */ 9138ae92dcSChris Healy #define RMON_T_COL 0x224 /* RMON TX collision count */ 9238ae92dcSChris Healy #define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */ 93745f42baSLothar Waßmann #define RMON_T_P65TO127 0x22c /* RMON TX 65 to 127 byte pkts */ 9438ae92dcSChris Healy #define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */ 9538ae92dcSChris Healy #define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */ 9638ae92dcSChris Healy #define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */ 97745f42baSLothar Waßmann #define RMON_T_P1024TO2047 0x23c /* RMON TX 1024 to 2047 byte pkts */ 9838ae92dcSChris Healy #define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */ 9938ae92dcSChris Healy #define RMON_T_OCTETS 0x244 /* RMON TX octets */ 10038ae92dcSChris Healy #define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */ 101745f42baSLothar Waßmann #define IEEE_T_FRAME_OK 0x24c /* Frames tx'd OK */ 10238ae92dcSChris Healy #define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */ 10338ae92dcSChris Healy #define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */ 10438ae92dcSChris Healy #define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */ 105745f42baSLothar Waßmann #define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */ 10638ae92dcSChris Healy #define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */ 10738ae92dcSChris Healy #define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */ 10838ae92dcSChris Healy #define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */ 109745f42baSLothar Waßmann #define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */ 11038ae92dcSChris Healy #define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */ 11138ae92dcSChris Healy #define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */ 11238ae92dcSChris Healy #define RMON_R_PACKETS 0x284 /* RMON RX packet count */ 11338ae92dcSChris Healy #define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */ 114745f42baSLothar Waßmann #define RMON_R_MC_PKT 0x28c /* RMON RX multicast pkts */ 11538ae92dcSChris Healy #define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */ 11638ae92dcSChris Healy #define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */ 11738ae92dcSChris Healy #define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */ 118745f42baSLothar Waßmann #define RMON_R_FRAG 0x29c /* RMON RX pkts < 64 bytes, bad CRC */ 119745f42baSLothar Waßmann #define RMON_R_JAB 0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */ 120745f42baSLothar Waßmann #define RMON_R_RESVD_O 0x2a4 /* Reserved */ 121745f42baSLothar Waßmann #define RMON_R_P64 0x2a8 /* RMON RX 64 byte pkts */ 122745f42baSLothar Waßmann #define RMON_R_P65TO127 0x2ac /* RMON RX 65 to 127 byte pkts */ 123745f42baSLothar Waßmann #define RMON_R_P128TO255 0x2b0 /* RMON RX 128 to 255 byte pkts */ 124745f42baSLothar Waßmann #define RMON_R_P256TO511 0x2b4 /* RMON RX 256 to 511 byte pkts */ 125745f42baSLothar Waßmann #define RMON_R_P512TO1023 0x2b8 /* RMON RX 512 to 1023 byte pkts */ 126745f42baSLothar Waßmann #define RMON_R_P1024TO2047 0x2bc /* RMON RX 1024 to 2047 byte pkts */ 127745f42baSLothar Waßmann #define RMON_R_P_GTE2048 0x2c0 /* RMON RX pkts > 2048 bytes */ 128745f42baSLothar Waßmann #define RMON_R_OCTETS 0x2c4 /* RMON RX octets */ 129745f42baSLothar Waßmann #define IEEE_R_DROP 0x2c8 /* Count frames not counted correctly */ 130745f42baSLothar Waßmann #define IEEE_R_FRAME_OK 0x2cc /* Frames rx'd OK */ 131745f42baSLothar Waßmann #define IEEE_R_CRC 0x2d0 /* Frames rx'd with CRC err */ 132745f42baSLothar Waßmann #define IEEE_R_ALIGN 0x2d4 /* Frames rx'd with alignment err */ 133745f42baSLothar Waßmann #define IEEE_R_MACERR 0x2d8 /* Receive FIFO overflow count */ 134745f42baSLothar Waßmann #define IEEE_R_FDXFC 0x2dc /* Flow control pause frames rx'd */ 135745f42baSLothar Waßmann #define IEEE_R_OCTETS_OK 0x2e0 /* Octet cnt for frames rx'd w/o err */ 13638ae92dcSChris Healy 137ec21e2ecSJeff Kirsher #else 138ec21e2ecSJeff Kirsher 139ec21e2ecSJeff Kirsher #define FEC_ECNTRL 0x000 /* Ethernet control reg */ 140ec21e2ecSJeff Kirsher #define FEC_IEVENT 0x004 /* Interrupt even reg */ 141ec21e2ecSJeff Kirsher #define FEC_IMASK 0x008 /* Interrupt mask reg */ 142ec21e2ecSJeff Kirsher #define FEC_IVEC 0x00c /* Interrupt vec status reg */ 143bf3c228dSFrank Li #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */ 144bf3c228dSFrank Li #define FEC_R_DES_ACTIVE_1 FEC_R_DES_ACTIVE_0 145bf3c228dSFrank Li #define FEC_R_DES_ACTIVE_2 FEC_R_DES_ACTIVE_0 146bf3c228dSFrank Li #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */ 147bf3c228dSFrank Li #define FEC_X_DES_ACTIVE_1 FEC_X_DES_ACTIVE_0 148bf3c228dSFrank Li #define FEC_X_DES_ACTIVE_2 FEC_X_DES_ACTIVE_0 149ec21e2ecSJeff Kirsher #define FEC_MII_DATA 0x040 /* MII manage frame reg */ 150ec21e2ecSJeff Kirsher #define FEC_MII_SPEED 0x044 /* MII speed control reg */ 151ec21e2ecSJeff Kirsher #define FEC_R_BOUND 0x08c /* FIFO receive bound reg */ 152ec21e2ecSJeff Kirsher #define FEC_R_FSTART 0x090 /* FIFO receive start reg */ 153ec21e2ecSJeff Kirsher #define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */ 154ec21e2ecSJeff Kirsher #define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */ 155ec21e2ecSJeff Kirsher #define FEC_R_CNTRL 0x104 /* Receive control reg */ 156ec21e2ecSJeff Kirsher #define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */ 157ec21e2ecSJeff Kirsher #define FEC_X_CNTRL 0x144 /* Transmit Control reg */ 158ec21e2ecSJeff Kirsher #define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */ 159ec21e2ecSJeff Kirsher #define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */ 160ec21e2ecSJeff Kirsher #define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */ 161ec21e2ecSJeff Kirsher #define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */ 162bf3c228dSFrank Li #define FEC_R_DES_START_0 0x3d0 /* Receive descriptor ring */ 163bf3c228dSFrank Li #define FEC_R_DES_START_1 FEC_R_DES_START_0 164bf3c228dSFrank Li #define FEC_R_DES_START_2 FEC_R_DES_START_0 165bf3c228dSFrank Li #define FEC_X_DES_START_0 0x3d4 /* Transmit descriptor ring */ 166bf3c228dSFrank Li #define FEC_X_DES_START_1 FEC_X_DES_START_0 167bf3c228dSFrank Li #define FEC_X_DES_START_2 FEC_X_DES_START_0 168ec21e2ecSJeff Kirsher #define FEC_R_BUFF_SIZE 0x3d8 /* Maximum receive buff size */ 169ec21e2ecSJeff Kirsher #define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */ 170bf3c228dSFrank Li /* Not existed in real chip 171bf3c228dSFrank Li * Just for pass build. 172bf3c228dSFrank Li */ 173745f42baSLothar Waßmann #define FEC_RCMR_1 0xfff 174745f42baSLothar Waßmann #define FEC_RCMR_2 0xfff 175745f42baSLothar Waßmann #define FEC_DMA_CFG_1 0xfff 176745f42baSLothar Waßmann #define FEC_DMA_CFG_2 0xfff 177745f42baSLothar Waßmann #define FEC_TXIC0 0xfff 178745f42baSLothar Waßmann #define FEC_TXIC1 0xfff 179745f42baSLothar Waßmann #define FEC_TXIC2 0xfff 180745f42baSLothar Waßmann #define FEC_RXIC0 0xfff 181745f42baSLothar Waßmann #define FEC_RXIC1 0xfff 182745f42baSLothar Waßmann #define FEC_RXIC2 0xfff 183ec21e2ecSJeff Kirsher #endif /* CONFIG_M5272 */ 184ec21e2ecSJeff Kirsher 185ec21e2ecSJeff Kirsher 186ec21e2ecSJeff Kirsher /* 187ec21e2ecSJeff Kirsher * Define the buffer descriptor structure. 188ec21e2ecSJeff Kirsher */ 189ec21e2ecSJeff Kirsher #if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) 190ec21e2ecSJeff Kirsher struct bufdesc { 191ec21e2ecSJeff Kirsher unsigned short cbd_datlen; /* Data length */ 192ec21e2ecSJeff Kirsher unsigned short cbd_sc; /* Control and status info */ 193ec21e2ecSJeff Kirsher unsigned long cbd_bufaddr; /* Buffer address */ 194ff43da86SFrank Li }; 195acac8406SFrank Li #else 196acac8406SFrank Li struct bufdesc { 197acac8406SFrank Li unsigned short cbd_sc; /* Control and status info */ 198acac8406SFrank Li unsigned short cbd_datlen; /* Data length */ 199acac8406SFrank Li unsigned long cbd_bufaddr; /* Buffer address */ 200acac8406SFrank Li }; 201acac8406SFrank Li #endif 202ff43da86SFrank Li 203ff43da86SFrank Li struct bufdesc_ex { 204ff43da86SFrank Li struct bufdesc desc; 2056605b730SFrank Li unsigned long cbd_esc; 2066605b730SFrank Li unsigned long cbd_prot; 2076605b730SFrank Li unsigned long cbd_bdu; 2086605b730SFrank Li unsigned long ts; 2096605b730SFrank Li unsigned short res0[4]; 210ec21e2ecSJeff Kirsher }; 211ff43da86SFrank Li 212ec21e2ecSJeff Kirsher /* 213ec21e2ecSJeff Kirsher * The following definitions courtesy of commproc.h, which where 214ec21e2ecSJeff Kirsher * Copyright (c) 1997 Dan Malek (dmalek@jlc.net). 215ec21e2ecSJeff Kirsher */ 216ec21e2ecSJeff Kirsher #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ 217ec21e2ecSJeff Kirsher #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 218ec21e2ecSJeff Kirsher #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ 219ec21e2ecSJeff Kirsher #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 220ec21e2ecSJeff Kirsher #define BD_SC_CM ((ushort)0x0200) /* Continuous mode */ 221ec21e2ecSJeff Kirsher #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ 222ec21e2ecSJeff Kirsher #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 223ec21e2ecSJeff Kirsher #define BD_SC_BR ((ushort)0x0020) /* Break received */ 224ec21e2ecSJeff Kirsher #define BD_SC_FR ((ushort)0x0010) /* Framing error */ 225ec21e2ecSJeff Kirsher #define BD_SC_PR ((ushort)0x0008) /* Parity error */ 226ec21e2ecSJeff Kirsher #define BD_SC_OV ((ushort)0x0002) /* Overrun */ 227ec21e2ecSJeff Kirsher #define BD_SC_CD ((ushort)0x0001) /* ?? */ 228ec21e2ecSJeff Kirsher 229ec21e2ecSJeff Kirsher /* Buffer descriptor control/status used by Ethernet receive. 230ec21e2ecSJeff Kirsher */ 231ec21e2ecSJeff Kirsher #define BD_ENET_RX_EMPTY ((ushort)0x8000) 232ec21e2ecSJeff Kirsher #define BD_ENET_RX_WRAP ((ushort)0x2000) 233ec21e2ecSJeff Kirsher #define BD_ENET_RX_INTR ((ushort)0x1000) 234ec21e2ecSJeff Kirsher #define BD_ENET_RX_LAST ((ushort)0x0800) 235ec21e2ecSJeff Kirsher #define BD_ENET_RX_FIRST ((ushort)0x0400) 236ec21e2ecSJeff Kirsher #define BD_ENET_RX_MISS ((ushort)0x0100) 237ec21e2ecSJeff Kirsher #define BD_ENET_RX_LG ((ushort)0x0020) 238ec21e2ecSJeff Kirsher #define BD_ENET_RX_NO ((ushort)0x0010) 239ec21e2ecSJeff Kirsher #define BD_ENET_RX_SH ((ushort)0x0008) 240ec21e2ecSJeff Kirsher #define BD_ENET_RX_CR ((ushort)0x0004) 241ec21e2ecSJeff Kirsher #define BD_ENET_RX_OV ((ushort)0x0002) 242ec21e2ecSJeff Kirsher #define BD_ENET_RX_CL ((ushort)0x0001) 243ec21e2ecSJeff Kirsher #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ 244ec21e2ecSJeff Kirsher 245cdffcf1bSJim Baxter /* Enhanced buffer descriptor control/status used by Ethernet receive */ 246cdffcf1bSJim Baxter #define BD_ENET_RX_VLAN 0x00000004 247cdffcf1bSJim Baxter 248ec21e2ecSJeff Kirsher /* Buffer descriptor control/status used by Ethernet transmit. 249ec21e2ecSJeff Kirsher */ 250ec21e2ecSJeff Kirsher #define BD_ENET_TX_READY ((ushort)0x8000) 251ec21e2ecSJeff Kirsher #define BD_ENET_TX_PAD ((ushort)0x4000) 252ec21e2ecSJeff Kirsher #define BD_ENET_TX_WRAP ((ushort)0x2000) 253ec21e2ecSJeff Kirsher #define BD_ENET_TX_INTR ((ushort)0x1000) 254ec21e2ecSJeff Kirsher #define BD_ENET_TX_LAST ((ushort)0x0800) 255ec21e2ecSJeff Kirsher #define BD_ENET_TX_TC ((ushort)0x0400) 256ec21e2ecSJeff Kirsher #define BD_ENET_TX_DEF ((ushort)0x0200) 257ec21e2ecSJeff Kirsher #define BD_ENET_TX_HB ((ushort)0x0100) 258ec21e2ecSJeff Kirsher #define BD_ENET_TX_LC ((ushort)0x0080) 259ec21e2ecSJeff Kirsher #define BD_ENET_TX_RL ((ushort)0x0040) 260ec21e2ecSJeff Kirsher #define BD_ENET_TX_RCMASK ((ushort)0x003c) 261ec21e2ecSJeff Kirsher #define BD_ENET_TX_UN ((ushort)0x0002) 262ec21e2ecSJeff Kirsher #define BD_ENET_TX_CSL ((ushort)0x0001) 2636e909283SNimrod Andy #define BD_ENET_TX_STATS ((ushort)0x0fff) /* All status bits */ 264ec21e2ecSJeff Kirsher 2654c09eed9SJim Baxter /* enhanced buffer descriptor control/status used by Ethernet transmit */ 266405f257fSFrank Li #define BD_ENET_TX_INT 0x40000000 267405f257fSFrank Li #define BD_ENET_TX_TS 0x20000000 2684c09eed9SJim Baxter #define BD_ENET_TX_PINS 0x10000000 2694c09eed9SJim Baxter #define BD_ENET_TX_IINS 0x08000000 270405f257fSFrank Li 271405f257fSFrank Li 272405f257fSFrank Li /* This device has up to three irqs on some platforms */ 273405f257fSFrank Li #define FEC_IRQ_NUM 3 274405f257fSFrank Li 2754d494cdcSFugang Duan /* Maximum number of queues supported 2764d494cdcSFugang Duan * ENET with AVB IP can support up to 3 independent tx queues and rx queues. 2774d494cdcSFugang Duan * User can point the queue number that is less than or equal to 3. 2784d494cdcSFugang Duan */ 2794d494cdcSFugang Duan #define FEC_ENET_MAX_TX_QS 3 2804d494cdcSFugang Duan #define FEC_ENET_MAX_RX_QS 3 2814d494cdcSFugang Duan 282df406bc9SLothar Waßmann #define FEC_R_DES_START(X) (((X) == 1) ? FEC_R_DES_START_1 : \ 283df406bc9SLothar Waßmann (((X) == 2) ? \ 2844d494cdcSFugang Duan FEC_R_DES_START_2 : FEC_R_DES_START_0)) 285df406bc9SLothar Waßmann #define FEC_X_DES_START(X) (((X) == 1) ? FEC_X_DES_START_1 : \ 286df406bc9SLothar Waßmann (((X) == 2) ? \ 2874d494cdcSFugang Duan FEC_X_DES_START_2 : FEC_X_DES_START_0)) 288df406bc9SLothar Waßmann #define FEC_R_DES_ACTIVE(X) (((X) == 1) ? FEC_R_DES_ACTIVE_1 : \ 289df406bc9SLothar Waßmann (((X) == 2) ? \ 2904d494cdcSFugang Duan FEC_R_DES_ACTIVE_2 : FEC_R_DES_ACTIVE_0)) 291df406bc9SLothar Waßmann #define FEC_X_DES_ACTIVE(X) (((X) == 1) ? FEC_X_DES_ACTIVE_1 : \ 292df406bc9SLothar Waßmann (((X) == 2) ? \ 2934d494cdcSFugang Duan FEC_X_DES_ACTIVE_2 : FEC_X_DES_ACTIVE_0)) 2944d494cdcSFugang Duan 295df406bc9SLothar Waßmann #define FEC_DMA_CFG(X) (((X) == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1) 2964d494cdcSFugang Duan 2974d494cdcSFugang Duan #define DMA_CLASS_EN (1 << 16) 298df406bc9SLothar Waßmann #define FEC_RCMR(X) (((X) == 2) ? FEC_RCMR_2 : FEC_RCMR_1) 299745f42baSLothar Waßmann #define IDLE_SLOPE_MASK 0xffff 3004d494cdcSFugang Duan #define IDLE_SLOPE_1 0x200 /* BW fraction: 0.5 */ 3014d494cdcSFugang Duan #define IDLE_SLOPE_2 0x200 /* BW fraction: 0.5 */ 302df406bc9SLothar Waßmann #define IDLE_SLOPE(X) (((X) == 1) ? \ 303df406bc9SLothar Waßmann (IDLE_SLOPE_1 & IDLE_SLOPE_MASK) : \ 3044d494cdcSFugang Duan (IDLE_SLOPE_2 & IDLE_SLOPE_MASK)) 3054d494cdcSFugang Duan #define RCMR_MATCHEN (0x1 << 16) 306df406bc9SLothar Waßmann #define RCMR_CMP_CFG(v, n) (((v) & 0x7) << (n << 2)) 3074d494cdcSFugang Duan #define RCMR_CMP_1 (RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \ 3084d494cdcSFugang Duan RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3)) 3094d494cdcSFugang Duan #define RCMR_CMP_2 (RCMR_CMP_CFG(4, 0) | RCMR_CMP_CFG(5, 1) | \ 3104d494cdcSFugang Duan RCMR_CMP_CFG(6, 2) | RCMR_CMP_CFG(7, 3)) 311df406bc9SLothar Waßmann #define RCMR_CMP(X) (((X) == 1) ? RCMR_CMP_1 : RCMR_CMP_2) 312df406bc9SLothar Waßmann #define FEC_TX_BD_FTYPE(X) (((X) & 0xf) << 20) 3134d494cdcSFugang Duan 314405f257fSFrank Li /* The number of Tx and Rx buffers. These are allocated from the page 315405f257fSFrank Li * pool. The code may assume these are power of two, so it it best 316405f257fSFrank Li * to keep them that size. 317405f257fSFrank Li * We don't need to allocate pages for the transmitter. We just use 318405f257fSFrank Li * the skbuffer directly. 319405f257fSFrank Li */ 320405f257fSFrank Li 32173e72289SFugang Duan #define FEC_ENET_RX_PAGES 256 322405f257fSFrank Li #define FEC_ENET_RX_FRSIZE 2048 323405f257fSFrank Li #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) 324405f257fSFrank Li #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) 325405f257fSFrank Li #define FEC_ENET_TX_FRSIZE 2048 326405f257fSFrank Li #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) 32755d0218aSNimrod Andy #define TX_RING_SIZE 512 /* Must be power of two */ 32855d0218aSNimrod Andy #define TX_RING_MOD_MASK 511 /* for this to work */ 329405f257fSFrank Li 330405f257fSFrank Li #define BD_ENET_RX_INT 0x00800000 331405f257fSFrank Li #define BD_ENET_RX_PTP ((ushort)0x0400) 3324c09eed9SJim Baxter #define BD_ENET_RX_ICE 0x00000020 3334c09eed9SJim Baxter #define BD_ENET_RX_PCR 0x00000010 3344c09eed9SJim Baxter #define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE | BD_ENET_RX_PCR) 3354c09eed9SJim Baxter #define FLAG_RX_CSUM_ERROR (BD_ENET_RX_ICE | BD_ENET_RX_PCR) 336405f257fSFrank Li 337ce99d0d3SFrank Li /* Interrupt events/masks. */ 338ce99d0d3SFrank Li #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ 339ce99d0d3SFrank Li #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ 340ce99d0d3SFrank Li #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ 341ce99d0d3SFrank Li #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ 342ce99d0d3SFrank Li #define FEC_ENET_TXF_0 ((uint)0x08000000) /* Full frame transmitted */ 343ce99d0d3SFrank Li #define FEC_ENET_TXF_1 ((uint)0x00000008) /* Full frame transmitted */ 344ce99d0d3SFrank Li #define FEC_ENET_TXF_2 ((uint)0x00000080) /* Full frame transmitted */ 345ce99d0d3SFrank Li #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ 346ce99d0d3SFrank Li #define FEC_ENET_RXF_0 ((uint)0x02000000) /* Full frame received */ 347ce99d0d3SFrank Li #define FEC_ENET_RXF_1 ((uint)0x00000002) /* Full frame received */ 348ce99d0d3SFrank Li #define FEC_ENET_RXF_2 ((uint)0x00000020) /* Full frame received */ 349ce99d0d3SFrank Li #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ 350ce99d0d3SFrank Li #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ 351ce99d0d3SFrank Li #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ 352ce99d0d3SFrank Li #define FEC_ENET_TXF (FEC_ENET_TXF_0 | FEC_ENET_TXF_1 | FEC_ENET_TXF_2) 353ce99d0d3SFrank Li #define FEC_ENET_RXF (FEC_ENET_RXF_0 | FEC_ENET_RXF_1 | FEC_ENET_RXF_2) 354ce99d0d3SFrank Li #define FEC_ENET_TS_AVAIL ((uint)0x00010000) 355ce99d0d3SFrank Li #define FEC_ENET_TS_TIMER ((uint)0x00008000) 356ce99d0d3SFrank Li 357ce99d0d3SFrank Li #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII | FEC_ENET_TS_TIMER) 358ce99d0d3SFrank Li #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) 359ce99d0d3SFrank Li 360d851b47bSFugang Duan /* ENET interrupt coalescing macro define */ 361d851b47bSFugang Duan #define FEC_ITR_CLK_SEL (0x1 << 30) 362d851b47bSFugang Duan #define FEC_ITR_EN (0x1 << 31) 363df406bc9SLothar Waßmann #define FEC_ITR_ICFT(X) (((X) & 0xff) << 20) 364745f42baSLothar Waßmann #define FEC_ITR_ICTT(X) ((X) & 0xffff) 365d851b47bSFugang Duan #define FEC_ITR_ICFT_DEFAULT 200 /* Set 200 frame count threshold */ 366d851b47bSFugang Duan #define FEC_ITR_ICTT_DEFAULT 1000 /* Set 1000us timer threshold */ 367d851b47bSFugang Duan 368ce99d0d3SFrank Li #define FEC_VLAN_TAG_LEN 0x04 369ce99d0d3SFrank Li #define FEC_ETHTYPE_LEN 0x02 370ce99d0d3SFrank Li 37128b5f058SNimrod Andy /* Controller is ENET-MAC */ 37228b5f058SNimrod Andy #define FEC_QUIRK_ENET_MAC (1 << 0) 37328b5f058SNimrod Andy /* Controller needs driver to swap frame */ 37428b5f058SNimrod Andy #define FEC_QUIRK_SWAP_FRAME (1 << 1) 37528b5f058SNimrod Andy /* Controller uses gasket */ 37628b5f058SNimrod Andy #define FEC_QUIRK_USE_GASKET (1 << 2) 37728b5f058SNimrod Andy /* Controller has GBIT support */ 37828b5f058SNimrod Andy #define FEC_QUIRK_HAS_GBIT (1 << 3) 37928b5f058SNimrod Andy /* Controller has extend desc buffer */ 38028b5f058SNimrod Andy #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) 38128b5f058SNimrod Andy /* Controller has hardware checksum support */ 38228b5f058SNimrod Andy #define FEC_QUIRK_HAS_CSUM (1 << 5) 38328b5f058SNimrod Andy /* Controller has hardware vlan support */ 38428b5f058SNimrod Andy #define FEC_QUIRK_HAS_VLAN (1 << 6) 38528b5f058SNimrod Andy /* ENET IP errata ERR006358 38628b5f058SNimrod Andy * 38728b5f058SNimrod Andy * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously 38828b5f058SNimrod Andy * detected as not set during a prior frame transmission, then the 38928b5f058SNimrod Andy * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs 39028b5f058SNimrod Andy * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in 39128b5f058SNimrod Andy * frames not being transmitted until there is a 0-to-1 transition on 39228b5f058SNimrod Andy * ENET_TDAR[TDAR]. 39328b5f058SNimrod Andy */ 39428b5f058SNimrod Andy #define FEC_QUIRK_ERR006358 (1 << 7) 39528b5f058SNimrod Andy /* ENET IP hw AVB 39628b5f058SNimrod Andy * 39728b5f058SNimrod Andy * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support. 39828b5f058SNimrod Andy * - Two class indicators on receive with configurable priority 39928b5f058SNimrod Andy * - Two class indicators and line speed timer on transmit allowing 40028b5f058SNimrod Andy * implementation class credit based shapers externally 40128b5f058SNimrod Andy * - Additional DMA registers provisioned to allow managing up to 3 40228b5f058SNimrod Andy * independent rings 40328b5f058SNimrod Andy */ 40428b5f058SNimrod Andy #define FEC_QUIRK_HAS_AVB (1 << 8) 40528b5f058SNimrod Andy /* There is a TDAR race condition for mutliQ when the software sets TDAR 40628b5f058SNimrod Andy * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles). 40728b5f058SNimrod Andy * This will cause the udma_tx and udma_tx_arbiter state machines to hang. 40828b5f058SNimrod Andy * The issue exist at i.MX6SX enet IP. 40928b5f058SNimrod Andy */ 41028b5f058SNimrod Andy #define FEC_QUIRK_ERR007885 (1 << 9) 41128b5f058SNimrod Andy /* ENET Block Guide/ Chapter for the iMX6SX (PELE) address one issue: 41228b5f058SNimrod Andy * After set ENET_ATCR[Capture], there need some time cycles before the counter 41328b5f058SNimrod Andy * value is capture in the register clock domain. 41428b5f058SNimrod Andy * The wait-time-cycles is at least 6 clock cycles of the slower clock between 41528b5f058SNimrod Andy * the register clock and the 1588 clock. The 1588 ts_clk is fixed to 25Mhz, 41628b5f058SNimrod Andy * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns 41728b5f058SNimrod Andy * (40ns * 6). 41828b5f058SNimrod Andy */ 41928b5f058SNimrod Andy #define FEC_QUIRK_BUG_CAPTURE (1 << 10) 42028b5f058SNimrod Andy 4214d494cdcSFugang Duan struct fec_enet_priv_tx_q { 4224d494cdcSFugang Duan int index; 4234d494cdcSFugang Duan unsigned char *tx_bounce[TX_RING_SIZE]; 4244d494cdcSFugang Duan struct sk_buff *tx_skbuff[TX_RING_SIZE]; 4254d494cdcSFugang Duan 4264d494cdcSFugang Duan dma_addr_t bd_dma; 4274d494cdcSFugang Duan struct bufdesc *tx_bd_base; 4284d494cdcSFugang Duan uint tx_ring_size; 4294d494cdcSFugang Duan 4304d494cdcSFugang Duan unsigned short tx_stop_threshold; 4314d494cdcSFugang Duan unsigned short tx_wake_threshold; 4324d494cdcSFugang Duan 4334d494cdcSFugang Duan struct bufdesc *cur_tx; 4344d494cdcSFugang Duan struct bufdesc *dirty_tx; 4354d494cdcSFugang Duan char *tso_hdrs; 4364d494cdcSFugang Duan dma_addr_t tso_hdrs_dma; 4374d494cdcSFugang Duan }; 4384d494cdcSFugang Duan 4394d494cdcSFugang Duan struct fec_enet_priv_rx_q { 4404d494cdcSFugang Duan int index; 4414d494cdcSFugang Duan struct sk_buff *rx_skbuff[RX_RING_SIZE]; 4424d494cdcSFugang Duan 4434d494cdcSFugang Duan dma_addr_t bd_dma; 4444d494cdcSFugang Duan struct bufdesc *rx_bd_base; 4454d494cdcSFugang Duan uint rx_ring_size; 4464d494cdcSFugang Duan 4474d494cdcSFugang Duan struct bufdesc *cur_rx; 4484d494cdcSFugang Duan }; 4494d494cdcSFugang Duan 450405f257fSFrank Li /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and 451405f257fSFrank Li * tx_bd_base always point to the base of the buffer descriptors. The 452405f257fSFrank Li * cur_rx and cur_tx point to the currently available buffer. 453405f257fSFrank Li * The dirty_tx tracks the current buffer that is being sent by the 454405f257fSFrank Li * controller. The cur_tx and dirty_tx are equal under both completely 455405f257fSFrank Li * empty and completely full conditions. The empty/ready indicator in 456405f257fSFrank Li * the buffer descriptor determines the actual condition. 457405f257fSFrank Li */ 458405f257fSFrank Li struct fec_enet_private { 459405f257fSFrank Li /* Hardware registers of the FEC device */ 460405f257fSFrank Li void __iomem *hwp; 461405f257fSFrank Li 462405f257fSFrank Li struct net_device *netdev; 463405f257fSFrank Li 464405f257fSFrank Li struct clk *clk_ipg; 465405f257fSFrank Li struct clk *clk_ahb; 4669b5330edSFugang Duan struct clk *clk_ref; 467daa7d392SWolfram Sang struct clk *clk_enet_out; 4686605b730SFrank Li struct clk *clk_ptp; 469405f257fSFrank Li 47091c0d987SNimrod Andy bool ptp_clk_on; 47191c0d987SNimrod Andy struct mutex ptp_clk_mutex; 4729fc095f1SFugang Duan unsigned int num_tx_queues; 4739fc095f1SFugang Duan unsigned int num_rx_queues; 47491c0d987SNimrod Andy 475405f257fSFrank Li /* The saved address of a sent-in-place packet/buffer, for skfree(). */ 4764d494cdcSFugang Duan struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS]; 4774d494cdcSFugang Duan struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS]; 478405f257fSFrank Li 4794d494cdcSFugang Duan unsigned int total_tx_ring_size; 4804d494cdcSFugang Duan unsigned int total_rx_ring_size; 4814d494cdcSFugang Duan 4824d494cdcSFugang Duan unsigned long work_tx; 4834d494cdcSFugang Duan unsigned long work_rx; 4844d494cdcSFugang Duan unsigned long work_ts; 4854d494cdcSFugang Duan unsigned long work_mdio; 486405f257fSFrank Li 48761a4427bSNimrod Andy unsigned short bufdesc_size; 48836e24e2eSDuan Fugang-B38611 489405f257fSFrank Li struct platform_device *pdev; 490405f257fSFrank Li 491405f257fSFrank Li int dev_id; 492405f257fSFrank Li 493405f257fSFrank Li /* Phylib and MDIO interface */ 494405f257fSFrank Li struct mii_bus *mii_bus; 495405f257fSFrank Li struct phy_device *phy_dev; 496405f257fSFrank Li int mii_timeout; 497405f257fSFrank Li uint phy_speed; 498405f257fSFrank Li phy_interface_t phy_interface; 499407066f8SUwe Kleine-König struct device_node *phy_node; 500405f257fSFrank Li int link; 501405f257fSFrank Li int full_duplex; 502d97e7497SLucas Stach int speed; 503405f257fSFrank Li struct completion mdio_done; 504405f257fSFrank Li int irq[FEC_IRQ_NUM]; 505217b5844SLothar Waßmann bool bufdesc_ex; 506baa70a5cSFrank Li int pause_flag; 507*6b7e4008SLothar Waßmann u32 quirks; 5086605b730SFrank Li 509dc975382SFrank Li struct napi_struct napi; 5104c09eed9SJim Baxter int csum_flags; 511dc975382SFrank Li 51236cdc743SRussell King struct work_struct tx_timeout_work; 51336cdc743SRussell King 5146605b730SFrank Li struct ptp_clock *ptp_clock; 5156605b730SFrank Li struct ptp_clock_info ptp_caps; 5166605b730SFrank Li unsigned long last_overflow_check; 5176605b730SFrank Li spinlock_t tmreg_lock; 5186605b730SFrank Li struct cyclecounter cc; 5196605b730SFrank Li struct timecounter tc; 5206605b730SFrank Li int rx_hwtstamp_filter; 5216605b730SFrank Li u32 base_incval; 5226605b730SFrank Li u32 cycle_speed; 5236605b730SFrank Li int hwts_rx_en; 5246605b730SFrank Li int hwts_tx_en; 52591c0d987SNimrod Andy struct delayed_work time_keep; 526f4e9f3d2SFabio Estevam struct regulator *reg_phy; 52741ef84ceSFugang Duan 52841ef84ceSFugang Duan unsigned int tx_align; 52941ef84ceSFugang Duan unsigned int rx_align; 530d851b47bSFugang Duan 531d851b47bSFugang Duan /* hw interrupt coalesce */ 532d851b47bSFugang Duan unsigned int rx_pkts_itr; 533d851b47bSFugang Duan unsigned int rx_time_itr; 534d851b47bSFugang Duan unsigned int tx_pkts_itr; 535d851b47bSFugang Duan unsigned int tx_time_itr; 536d851b47bSFugang Duan unsigned int itr_clk_rate; 5371b7bde6dSNimrod Andy 5381b7bde6dSNimrod Andy u32 rx_copybreak; 53989bddcdaSLuwei Zhou 54089bddcdaSLuwei Zhou /* ptp clock period in ns*/ 54189bddcdaSLuwei Zhou unsigned int ptp_inc; 542278d2404SLuwei Zhou 543278d2404SLuwei Zhou /* pps */ 544278d2404SLuwei Zhou int pps_channel; 545278d2404SLuwei Zhou unsigned int reload_period; 546278d2404SLuwei Zhou int pps_enable; 547278d2404SLuwei Zhou unsigned int next_counter; 548405f257fSFrank Li }; 549ec21e2ecSJeff Kirsher 550ca162a82SFabio Estevam void fec_ptp_init(struct platform_device *pdev); 5516605b730SFrank Li void fec_ptp_start_cyclecounter(struct net_device *ndev); 5521d5244d0SBen Hutchings int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr); 5531d5244d0SBen Hutchings int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr); 554278d2404SLuwei Zhou uint fec_ptp_check_pps_event(struct fec_enet_private *fep); 5556605b730SFrank Li 556ec21e2ecSJeff Kirsher /****************************************************************************/ 557ec21e2ecSJeff Kirsher #endif /* FEC_H */ 558