1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2ec21e2ecSJeff Kirsher /****************************************************************************/ 3ec21e2ecSJeff Kirsher 4ec21e2ecSJeff Kirsher /* 5ec21e2ecSJeff Kirsher * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC 6ec21e2ecSJeff Kirsher * processors. 7ec21e2ecSJeff Kirsher * 8ec21e2ecSJeff Kirsher * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com) 9ec21e2ecSJeff Kirsher * (C) Copyright 2000-2001, Lineo (www.lineo.com) 10ec21e2ecSJeff Kirsher */ 11ec21e2ecSJeff Kirsher 12ec21e2ecSJeff Kirsher /****************************************************************************/ 13ec21e2ecSJeff Kirsher #ifndef FEC_H 14ec21e2ecSJeff Kirsher #define FEC_H 15ec21e2ecSJeff Kirsher /****************************************************************************/ 16ec21e2ecSJeff Kirsher 176605b730SFrank Li #include <linux/clocksource.h> 186605b730SFrank Li #include <linux/net_tstamp.h> 196605b730SFrank Li #include <linux/ptp_clock_kernel.h> 2074d23cc7SRichard Cochran #include <linux/timecounter.h> 216605b730SFrank Li 22ec21e2ecSJeff Kirsher #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 23*3f1dcc6aSLucas Stach defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 24*3f1dcc6aSLucas Stach defined(CONFIG_ARM64) 25ec21e2ecSJeff Kirsher /* 26ec21e2ecSJeff Kirsher * Just figures, Motorola would have to change the offsets for 27ec21e2ecSJeff Kirsher * registers in the same peripheral device on different models 28ec21e2ecSJeff Kirsher * of the ColdFire! 29ec21e2ecSJeff Kirsher */ 30ec21e2ecSJeff Kirsher #define FEC_IEVENT 0x004 /* Interrupt event reg */ 31ec21e2ecSJeff Kirsher #define FEC_IMASK 0x008 /* Interrupt mask reg */ 324d494cdcSFugang Duan #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */ 334d494cdcSFugang Duan #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */ 34ec21e2ecSJeff Kirsher #define FEC_ECNTRL 0x024 /* Ethernet control reg */ 35ec21e2ecSJeff Kirsher #define FEC_MII_DATA 0x040 /* MII manage frame reg */ 36ec21e2ecSJeff Kirsher #define FEC_MII_SPEED 0x044 /* MII speed control reg */ 37ec21e2ecSJeff Kirsher #define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */ 38ec21e2ecSJeff Kirsher #define FEC_R_CNTRL 0x084 /* Receive control reg */ 39ec21e2ecSJeff Kirsher #define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */ 40ec21e2ecSJeff Kirsher #define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */ 41ec21e2ecSJeff Kirsher #define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */ 42ec21e2ecSJeff Kirsher #define FEC_OPD 0x0ec /* Opcode + Pause duration */ 43745f42baSLothar Waßmann #define FEC_TXIC0 0x0f0 /* Tx Interrupt Coalescing for ring 0 */ 44745f42baSLothar Waßmann #define FEC_TXIC1 0x0f4 /* Tx Interrupt Coalescing for ring 1 */ 45745f42baSLothar Waßmann #define FEC_TXIC2 0x0f8 /* Tx Interrupt Coalescing for ring 2 */ 46ce99d0d3SFrank Li #define FEC_RXIC0 0x100 /* Rx Interrupt Coalescing for ring 0 */ 47ce99d0d3SFrank Li #define FEC_RXIC1 0x104 /* Rx Interrupt Coalescing for ring 1 */ 48ce99d0d3SFrank Li #define FEC_RXIC2 0x108 /* Rx Interrupt Coalescing for ring 2 */ 49ec21e2ecSJeff Kirsher #define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */ 50ec21e2ecSJeff Kirsher #define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */ 51ec21e2ecSJeff Kirsher #define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */ 52ec21e2ecSJeff Kirsher #define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */ 53ec21e2ecSJeff Kirsher #define FEC_X_WMRK 0x144 /* FIFO transmit water mark */ 54ec21e2ecSJeff Kirsher #define FEC_R_BOUND 0x14c /* FIFO receive bound reg */ 55ec21e2ecSJeff Kirsher #define FEC_R_FSTART 0x150 /* FIFO receive start reg */ 564d494cdcSFugang Duan #define FEC_R_DES_START_1 0x160 /* Receive descriptor ring 1 */ 574d494cdcSFugang Duan #define FEC_X_DES_START_1 0x164 /* Transmit descriptor ring 1 */ 58d543a762SNimrod Andy #define FEC_R_BUFF_SIZE_1 0x168 /* Maximum receive buff ring1 size */ 594d494cdcSFugang Duan #define FEC_R_DES_START_2 0x16c /* Receive descriptor ring 2 */ 604d494cdcSFugang Duan #define FEC_X_DES_START_2 0x170 /* Transmit descriptor ring 2 */ 61d543a762SNimrod Andy #define FEC_R_BUFF_SIZE_2 0x174 /* Maximum receive buff ring2 size */ 624d494cdcSFugang Duan #define FEC_R_DES_START_0 0x180 /* Receive descriptor ring */ 634d494cdcSFugang Duan #define FEC_X_DES_START_0 0x184 /* Transmit descriptor ring */ 64d543a762SNimrod Andy #define FEC_R_BUFF_SIZE_0 0x188 /* Maximum receive buff size */ 65baa70a5cSFrank Li #define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */ 66baa70a5cSFrank Li #define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */ 67baa70a5cSFrank Li #define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */ 68baa70a5cSFrank Li #define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */ 6955cd48c8STroy Kisky #define FEC_FTRL 0x1b0 /* Frame truncation receive length*/ 70745f42baSLothar Waßmann #define FEC_RACC 0x1c4 /* Receive Accelerator function */ 714d494cdcSFugang Duan #define FEC_RCMR_1 0x1c8 /* Receive classification match ring 1 */ 724d494cdcSFugang Duan #define FEC_RCMR_2 0x1cc /* Receive classification match ring 2 */ 734d494cdcSFugang Duan #define FEC_DMA_CFG_1 0x1d8 /* DMA class configuration for ring 1 */ 744d494cdcSFugang Duan #define FEC_DMA_CFG_2 0x1dc /* DMA class Configuration for ring 2 */ 754d494cdcSFugang Duan #define FEC_R_DES_ACTIVE_1 0x1e0 /* Rx descriptor active for ring 1 */ 764d494cdcSFugang Duan #define FEC_X_DES_ACTIVE_1 0x1e4 /* Tx descriptor active for ring 1 */ 774d494cdcSFugang Duan #define FEC_R_DES_ACTIVE_2 0x1e8 /* Rx descriptor active for ring 2 */ 784d494cdcSFugang Duan #define FEC_X_DES_ACTIVE_2 0x1ec /* Tx descriptor active for ring 2 */ 79ce99d0d3SFrank Li #define FEC_QOS_SCHEME 0x1f0 /* Set multi queues Qos scheme */ 80ec21e2ecSJeff Kirsher #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */ 81ec21e2ecSJeff Kirsher #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */ 82ec21e2ecSJeff Kirsher 838d82f219SEric Benard #define BM_MIIGSK_CFGR_MII 0x00 848d82f219SEric Benard #define BM_MIIGSK_CFGR_RMII 0x01 858d82f219SEric Benard #define BM_MIIGSK_CFGR_FRCONT_10M 0x40 868d82f219SEric Benard 8738ae92dcSChris Healy #define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */ 8838ae92dcSChris Healy #define RMON_T_PACKETS 0x204 /* RMON TX packet count */ 8938ae92dcSChris Healy #define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */ 90745f42baSLothar Waßmann #define RMON_T_MC_PKT 0x20c /* RMON TX multicast pkts */ 9138ae92dcSChris Healy #define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */ 9238ae92dcSChris Healy #define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */ 9338ae92dcSChris Healy #define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */ 94745f42baSLothar Waßmann #define RMON_T_FRAG 0x21c /* RMON TX pkts < 64 bytes, bad CRC */ 9538ae92dcSChris Healy #define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */ 9638ae92dcSChris Healy #define RMON_T_COL 0x224 /* RMON TX collision count */ 9738ae92dcSChris Healy #define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */ 98745f42baSLothar Waßmann #define RMON_T_P65TO127 0x22c /* RMON TX 65 to 127 byte pkts */ 9938ae92dcSChris Healy #define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */ 10038ae92dcSChris Healy #define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */ 10138ae92dcSChris Healy #define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */ 102745f42baSLothar Waßmann #define RMON_T_P1024TO2047 0x23c /* RMON TX 1024 to 2047 byte pkts */ 10338ae92dcSChris Healy #define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */ 10438ae92dcSChris Healy #define RMON_T_OCTETS 0x244 /* RMON TX octets */ 10538ae92dcSChris Healy #define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */ 106745f42baSLothar Waßmann #define IEEE_T_FRAME_OK 0x24c /* Frames tx'd OK */ 10738ae92dcSChris Healy #define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */ 10838ae92dcSChris Healy #define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */ 10938ae92dcSChris Healy #define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */ 110745f42baSLothar Waßmann #define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */ 11138ae92dcSChris Healy #define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */ 11238ae92dcSChris Healy #define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */ 11338ae92dcSChris Healy #define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */ 114745f42baSLothar Waßmann #define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */ 11538ae92dcSChris Healy #define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */ 11638ae92dcSChris Healy #define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */ 11738ae92dcSChris Healy #define RMON_R_PACKETS 0x284 /* RMON RX packet count */ 11838ae92dcSChris Healy #define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */ 119745f42baSLothar Waßmann #define RMON_R_MC_PKT 0x28c /* RMON RX multicast pkts */ 12038ae92dcSChris Healy #define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */ 12138ae92dcSChris Healy #define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */ 12238ae92dcSChris Healy #define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */ 123745f42baSLothar Waßmann #define RMON_R_FRAG 0x29c /* RMON RX pkts < 64 bytes, bad CRC */ 124745f42baSLothar Waßmann #define RMON_R_JAB 0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */ 125745f42baSLothar Waßmann #define RMON_R_RESVD_O 0x2a4 /* Reserved */ 126745f42baSLothar Waßmann #define RMON_R_P64 0x2a8 /* RMON RX 64 byte pkts */ 127745f42baSLothar Waßmann #define RMON_R_P65TO127 0x2ac /* RMON RX 65 to 127 byte pkts */ 128745f42baSLothar Waßmann #define RMON_R_P128TO255 0x2b0 /* RMON RX 128 to 255 byte pkts */ 129745f42baSLothar Waßmann #define RMON_R_P256TO511 0x2b4 /* RMON RX 256 to 511 byte pkts */ 130745f42baSLothar Waßmann #define RMON_R_P512TO1023 0x2b8 /* RMON RX 512 to 1023 byte pkts */ 131745f42baSLothar Waßmann #define RMON_R_P1024TO2047 0x2bc /* RMON RX 1024 to 2047 byte pkts */ 132745f42baSLothar Waßmann #define RMON_R_P_GTE2048 0x2c0 /* RMON RX pkts > 2048 bytes */ 133745f42baSLothar Waßmann #define RMON_R_OCTETS 0x2c4 /* RMON RX octets */ 134745f42baSLothar Waßmann #define IEEE_R_DROP 0x2c8 /* Count frames not counted correctly */ 135745f42baSLothar Waßmann #define IEEE_R_FRAME_OK 0x2cc /* Frames rx'd OK */ 136745f42baSLothar Waßmann #define IEEE_R_CRC 0x2d0 /* Frames rx'd with CRC err */ 137745f42baSLothar Waßmann #define IEEE_R_ALIGN 0x2d4 /* Frames rx'd with alignment err */ 138745f42baSLothar Waßmann #define IEEE_R_MACERR 0x2d8 /* Receive FIFO overflow count */ 139745f42baSLothar Waßmann #define IEEE_R_FDXFC 0x2dc /* Flow control pause frames rx'd */ 140745f42baSLothar Waßmann #define IEEE_R_OCTETS_OK 0x2e0 /* Octet cnt for frames rx'd w/o err */ 14138ae92dcSChris Healy 142ec21e2ecSJeff Kirsher #else 143ec21e2ecSJeff Kirsher 144ec21e2ecSJeff Kirsher #define FEC_ECNTRL 0x000 /* Ethernet control reg */ 145ec21e2ecSJeff Kirsher #define FEC_IEVENT 0x004 /* Interrupt even reg */ 146ec21e2ecSJeff Kirsher #define FEC_IMASK 0x008 /* Interrupt mask reg */ 147ec21e2ecSJeff Kirsher #define FEC_IVEC 0x00c /* Interrupt vec status reg */ 148bf3c228dSFrank Li #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */ 149bf3c228dSFrank Li #define FEC_R_DES_ACTIVE_1 FEC_R_DES_ACTIVE_0 150bf3c228dSFrank Li #define FEC_R_DES_ACTIVE_2 FEC_R_DES_ACTIVE_0 151bf3c228dSFrank Li #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */ 152bf3c228dSFrank Li #define FEC_X_DES_ACTIVE_1 FEC_X_DES_ACTIVE_0 153bf3c228dSFrank Li #define FEC_X_DES_ACTIVE_2 FEC_X_DES_ACTIVE_0 154ec21e2ecSJeff Kirsher #define FEC_MII_DATA 0x040 /* MII manage frame reg */ 155ec21e2ecSJeff Kirsher #define FEC_MII_SPEED 0x044 /* MII speed control reg */ 156ec21e2ecSJeff Kirsher #define FEC_R_BOUND 0x08c /* FIFO receive bound reg */ 157ec21e2ecSJeff Kirsher #define FEC_R_FSTART 0x090 /* FIFO receive start reg */ 158ec21e2ecSJeff Kirsher #define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */ 159ec21e2ecSJeff Kirsher #define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */ 160ec21e2ecSJeff Kirsher #define FEC_R_CNTRL 0x104 /* Receive control reg */ 161ec21e2ecSJeff Kirsher #define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */ 162ec21e2ecSJeff Kirsher #define FEC_X_CNTRL 0x144 /* Transmit Control reg */ 163ec21e2ecSJeff Kirsher #define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */ 164ec21e2ecSJeff Kirsher #define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */ 165ec21e2ecSJeff Kirsher #define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */ 166ec21e2ecSJeff Kirsher #define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */ 167bf3c228dSFrank Li #define FEC_R_DES_START_0 0x3d0 /* Receive descriptor ring */ 168bf3c228dSFrank Li #define FEC_R_DES_START_1 FEC_R_DES_START_0 169bf3c228dSFrank Li #define FEC_R_DES_START_2 FEC_R_DES_START_0 170bf3c228dSFrank Li #define FEC_X_DES_START_0 0x3d4 /* Transmit descriptor ring */ 171bf3c228dSFrank Li #define FEC_X_DES_START_1 FEC_X_DES_START_0 172bf3c228dSFrank Li #define FEC_X_DES_START_2 FEC_X_DES_START_0 173d543a762SNimrod Andy #define FEC_R_BUFF_SIZE_0 0x3d8 /* Maximum receive buff size */ 174d543a762SNimrod Andy #define FEC_R_BUFF_SIZE_1 FEC_R_BUFF_SIZE_0 175d543a762SNimrod Andy #define FEC_R_BUFF_SIZE_2 FEC_R_BUFF_SIZE_0 176ec21e2ecSJeff Kirsher #define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */ 177bf3c228dSFrank Li /* Not existed in real chip 178bf3c228dSFrank Li * Just for pass build. 179bf3c228dSFrank Li */ 180745f42baSLothar Waßmann #define FEC_RCMR_1 0xfff 181745f42baSLothar Waßmann #define FEC_RCMR_2 0xfff 182745f42baSLothar Waßmann #define FEC_DMA_CFG_1 0xfff 183745f42baSLothar Waßmann #define FEC_DMA_CFG_2 0xfff 184745f42baSLothar Waßmann #define FEC_TXIC0 0xfff 185745f42baSLothar Waßmann #define FEC_TXIC1 0xfff 186745f42baSLothar Waßmann #define FEC_TXIC2 0xfff 187745f42baSLothar Waßmann #define FEC_RXIC0 0xfff 188745f42baSLothar Waßmann #define FEC_RXIC1 0xfff 189745f42baSLothar Waßmann #define FEC_RXIC2 0xfff 190ec21e2ecSJeff Kirsher #endif /* CONFIG_M5272 */ 191ec21e2ecSJeff Kirsher 192ec21e2ecSJeff Kirsher 193ec21e2ecSJeff Kirsher /* 194ec21e2ecSJeff Kirsher * Define the buffer descriptor structure. 1955cfa3039SJohannes Berg * 1965cfa3039SJohannes Berg * Evidently, ARM SoCs have the FEC block generated in a 19705f3b50eSJohannes Berg * little endian mode so adjust endianness accordingly. 198ec21e2ecSJeff Kirsher */ 199*3f1dcc6aSLucas Stach #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 2005cfa3039SJohannes Berg #define fec32_to_cpu le32_to_cpu 2015cfa3039SJohannes Berg #define fec16_to_cpu le16_to_cpu 2025cfa3039SJohannes Berg #define cpu_to_fec32 cpu_to_le32 2035cfa3039SJohannes Berg #define cpu_to_fec16 cpu_to_le16 2045cfa3039SJohannes Berg #define __fec32 __le32 2055cfa3039SJohannes Berg #define __fec16 __le16 2065cfa3039SJohannes Berg 207ec21e2ecSJeff Kirsher struct bufdesc { 2085cfa3039SJohannes Berg __fec16 cbd_datlen; /* Data length */ 2095cfa3039SJohannes Berg __fec16 cbd_sc; /* Control and status info */ 2105cfa3039SJohannes Berg __fec32 cbd_bufaddr; /* Buffer address */ 211ff43da86SFrank Li }; 212acac8406SFrank Li #else 2135cfa3039SJohannes Berg #define fec32_to_cpu be32_to_cpu 2145cfa3039SJohannes Berg #define fec16_to_cpu be16_to_cpu 2155cfa3039SJohannes Berg #define cpu_to_fec32 cpu_to_be32 2165cfa3039SJohannes Berg #define cpu_to_fec16 cpu_to_be16 2175cfa3039SJohannes Berg #define __fec32 __be32 2185cfa3039SJohannes Berg #define __fec16 __be16 2195cfa3039SJohannes Berg 220acac8406SFrank Li struct bufdesc { 2215cfa3039SJohannes Berg __fec16 cbd_sc; /* Control and status info */ 2225cfa3039SJohannes Berg __fec16 cbd_datlen; /* Data length */ 2235cfa3039SJohannes Berg __fec32 cbd_bufaddr; /* Buffer address */ 224acac8406SFrank Li }; 225acac8406SFrank Li #endif 226ff43da86SFrank Li 227ff43da86SFrank Li struct bufdesc_ex { 228ff43da86SFrank Li struct bufdesc desc; 2295cfa3039SJohannes Berg __fec32 cbd_esc; 2305cfa3039SJohannes Berg __fec32 cbd_prot; 2315cfa3039SJohannes Berg __fec32 cbd_bdu; 2325cfa3039SJohannes Berg __fec32 ts; 2335cfa3039SJohannes Berg __fec16 res0[4]; 234ec21e2ecSJeff Kirsher }; 235ff43da86SFrank Li 236ec21e2ecSJeff Kirsher /* 237ec21e2ecSJeff Kirsher * The following definitions courtesy of commproc.h, which where 238ec21e2ecSJeff Kirsher * Copyright (c) 1997 Dan Malek (dmalek@jlc.net). 239ec21e2ecSJeff Kirsher */ 240ec21e2ecSJeff Kirsher #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ 241ec21e2ecSJeff Kirsher #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 242ec21e2ecSJeff Kirsher #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ 243ec21e2ecSJeff Kirsher #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 244ec21e2ecSJeff Kirsher #define BD_SC_CM ((ushort)0x0200) /* Continuous mode */ 245ec21e2ecSJeff Kirsher #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ 246ec21e2ecSJeff Kirsher #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 247ec21e2ecSJeff Kirsher #define BD_SC_BR ((ushort)0x0020) /* Break received */ 248ec21e2ecSJeff Kirsher #define BD_SC_FR ((ushort)0x0010) /* Framing error */ 249ec21e2ecSJeff Kirsher #define BD_SC_PR ((ushort)0x0008) /* Parity error */ 250ec21e2ecSJeff Kirsher #define BD_SC_OV ((ushort)0x0002) /* Overrun */ 251ec21e2ecSJeff Kirsher #define BD_SC_CD ((ushort)0x0001) /* ?? */ 252ec21e2ecSJeff Kirsher 253ec21e2ecSJeff Kirsher /* Buffer descriptor control/status used by Ethernet receive. 254ec21e2ecSJeff Kirsher */ 255ec21e2ecSJeff Kirsher #define BD_ENET_RX_EMPTY ((ushort)0x8000) 256ec21e2ecSJeff Kirsher #define BD_ENET_RX_WRAP ((ushort)0x2000) 257ec21e2ecSJeff Kirsher #define BD_ENET_RX_INTR ((ushort)0x1000) 258ec21e2ecSJeff Kirsher #define BD_ENET_RX_LAST ((ushort)0x0800) 259ec21e2ecSJeff Kirsher #define BD_ENET_RX_FIRST ((ushort)0x0400) 260ec21e2ecSJeff Kirsher #define BD_ENET_RX_MISS ((ushort)0x0100) 261ec21e2ecSJeff Kirsher #define BD_ENET_RX_LG ((ushort)0x0020) 262ec21e2ecSJeff Kirsher #define BD_ENET_RX_NO ((ushort)0x0010) 263ec21e2ecSJeff Kirsher #define BD_ENET_RX_SH ((ushort)0x0008) 264ec21e2ecSJeff Kirsher #define BD_ENET_RX_CR ((ushort)0x0004) 265ec21e2ecSJeff Kirsher #define BD_ENET_RX_OV ((ushort)0x0002) 266ec21e2ecSJeff Kirsher #define BD_ENET_RX_CL ((ushort)0x0001) 267ec21e2ecSJeff Kirsher #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ 268ec21e2ecSJeff Kirsher 269cdffcf1bSJim Baxter /* Enhanced buffer descriptor control/status used by Ethernet receive */ 270cdffcf1bSJim Baxter #define BD_ENET_RX_VLAN 0x00000004 271cdffcf1bSJim Baxter 272ec21e2ecSJeff Kirsher /* Buffer descriptor control/status used by Ethernet transmit. 273ec21e2ecSJeff Kirsher */ 274ec21e2ecSJeff Kirsher #define BD_ENET_TX_READY ((ushort)0x8000) 275ec21e2ecSJeff Kirsher #define BD_ENET_TX_PAD ((ushort)0x4000) 276ec21e2ecSJeff Kirsher #define BD_ENET_TX_WRAP ((ushort)0x2000) 277ec21e2ecSJeff Kirsher #define BD_ENET_TX_INTR ((ushort)0x1000) 278ec21e2ecSJeff Kirsher #define BD_ENET_TX_LAST ((ushort)0x0800) 279ec21e2ecSJeff Kirsher #define BD_ENET_TX_TC ((ushort)0x0400) 280ec21e2ecSJeff Kirsher #define BD_ENET_TX_DEF ((ushort)0x0200) 281ec21e2ecSJeff Kirsher #define BD_ENET_TX_HB ((ushort)0x0100) 282ec21e2ecSJeff Kirsher #define BD_ENET_TX_LC ((ushort)0x0080) 283ec21e2ecSJeff Kirsher #define BD_ENET_TX_RL ((ushort)0x0040) 284ec21e2ecSJeff Kirsher #define BD_ENET_TX_RCMASK ((ushort)0x003c) 285ec21e2ecSJeff Kirsher #define BD_ENET_TX_UN ((ushort)0x0002) 286ec21e2ecSJeff Kirsher #define BD_ENET_TX_CSL ((ushort)0x0001) 2876e909283SNimrod Andy #define BD_ENET_TX_STATS ((ushort)0x0fff) /* All status bits */ 288ec21e2ecSJeff Kirsher 2894c09eed9SJim Baxter /* enhanced buffer descriptor control/status used by Ethernet transmit */ 290405f257fSFrank Li #define BD_ENET_TX_INT 0x40000000 291405f257fSFrank Li #define BD_ENET_TX_TS 0x20000000 2924c09eed9SJim Baxter #define BD_ENET_TX_PINS 0x10000000 2934c09eed9SJim Baxter #define BD_ENET_TX_IINS 0x08000000 294405f257fSFrank Li 295405f257fSFrank Li 296405f257fSFrank Li /* This device has up to three irqs on some platforms */ 297405f257fSFrank Li #define FEC_IRQ_NUM 3 298405f257fSFrank Li 2994d494cdcSFugang Duan /* Maximum number of queues supported 3004d494cdcSFugang Duan * ENET with AVB IP can support up to 3 independent tx queues and rx queues. 3014d494cdcSFugang Duan * User can point the queue number that is less than or equal to 3. 3024d494cdcSFugang Duan */ 3034d494cdcSFugang Duan #define FEC_ENET_MAX_TX_QS 3 3044d494cdcSFugang Duan #define FEC_ENET_MAX_RX_QS 3 3054d494cdcSFugang Duan 306df406bc9SLothar Waßmann #define FEC_R_DES_START(X) (((X) == 1) ? FEC_R_DES_START_1 : \ 307df406bc9SLothar Waßmann (((X) == 2) ? \ 3084d494cdcSFugang Duan FEC_R_DES_START_2 : FEC_R_DES_START_0)) 309df406bc9SLothar Waßmann #define FEC_X_DES_START(X) (((X) == 1) ? FEC_X_DES_START_1 : \ 310df406bc9SLothar Waßmann (((X) == 2) ? \ 3114d494cdcSFugang Duan FEC_X_DES_START_2 : FEC_X_DES_START_0)) 312d543a762SNimrod Andy #define FEC_R_BUFF_SIZE(X) (((X) == 1) ? FEC_R_BUFF_SIZE_1 : \ 313d543a762SNimrod Andy (((X) == 2) ? \ 314d543a762SNimrod Andy FEC_R_BUFF_SIZE_2 : FEC_R_BUFF_SIZE_0)) 3154d494cdcSFugang Duan 316df406bc9SLothar Waßmann #define FEC_DMA_CFG(X) (((X) == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1) 3174d494cdcSFugang Duan 3184d494cdcSFugang Duan #define DMA_CLASS_EN (1 << 16) 319df406bc9SLothar Waßmann #define FEC_RCMR(X) (((X) == 2) ? FEC_RCMR_2 : FEC_RCMR_1) 320745f42baSLothar Waßmann #define IDLE_SLOPE_MASK 0xffff 3214d494cdcSFugang Duan #define IDLE_SLOPE_1 0x200 /* BW fraction: 0.5 */ 3224d494cdcSFugang Duan #define IDLE_SLOPE_2 0x200 /* BW fraction: 0.5 */ 323df406bc9SLothar Waßmann #define IDLE_SLOPE(X) (((X) == 1) ? \ 324df406bc9SLothar Waßmann (IDLE_SLOPE_1 & IDLE_SLOPE_MASK) : \ 3254d494cdcSFugang Duan (IDLE_SLOPE_2 & IDLE_SLOPE_MASK)) 3264d494cdcSFugang Duan #define RCMR_MATCHEN (0x1 << 16) 327df406bc9SLothar Waßmann #define RCMR_CMP_CFG(v, n) (((v) & 0x7) << (n << 2)) 3284d494cdcSFugang Duan #define RCMR_CMP_1 (RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \ 3294d494cdcSFugang Duan RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3)) 3304d494cdcSFugang Duan #define RCMR_CMP_2 (RCMR_CMP_CFG(4, 0) | RCMR_CMP_CFG(5, 1) | \ 3314d494cdcSFugang Duan RCMR_CMP_CFG(6, 2) | RCMR_CMP_CFG(7, 3)) 332df406bc9SLothar Waßmann #define RCMR_CMP(X) (((X) == 1) ? RCMR_CMP_1 : RCMR_CMP_2) 333df406bc9SLothar Waßmann #define FEC_TX_BD_FTYPE(X) (((X) & 0xf) << 20) 3344d494cdcSFugang Duan 335405f257fSFrank Li /* The number of Tx and Rx buffers. These are allocated from the page 336405f257fSFrank Li * pool. The code may assume these are power of two, so it it best 337405f257fSFrank Li * to keep them that size. 338405f257fSFrank Li * We don't need to allocate pages for the transmitter. We just use 339405f257fSFrank Li * the skbuffer directly. 340405f257fSFrank Li */ 341405f257fSFrank Li 34273e72289SFugang Duan #define FEC_ENET_RX_PAGES 256 343405f257fSFrank Li #define FEC_ENET_RX_FRSIZE 2048 344405f257fSFrank Li #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) 345405f257fSFrank Li #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) 346405f257fSFrank Li #define FEC_ENET_TX_FRSIZE 2048 347405f257fSFrank Li #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) 34855d0218aSNimrod Andy #define TX_RING_SIZE 512 /* Must be power of two */ 34955d0218aSNimrod Andy #define TX_RING_MOD_MASK 511 /* for this to work */ 350405f257fSFrank Li 351405f257fSFrank Li #define BD_ENET_RX_INT 0x00800000 352405f257fSFrank Li #define BD_ENET_RX_PTP ((ushort)0x0400) 3534c09eed9SJim Baxter #define BD_ENET_RX_ICE 0x00000020 3544c09eed9SJim Baxter #define BD_ENET_RX_PCR 0x00000010 3554c09eed9SJim Baxter #define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE | BD_ENET_RX_PCR) 3564c09eed9SJim Baxter #define FLAG_RX_CSUM_ERROR (BD_ENET_RX_ICE | BD_ENET_RX_PCR) 357405f257fSFrank Li 358ce99d0d3SFrank Li /* Interrupt events/masks. */ 359ce99d0d3SFrank Li #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ 360ce99d0d3SFrank Li #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ 361ce99d0d3SFrank Li #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ 362ce99d0d3SFrank Li #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ 363ce99d0d3SFrank Li #define FEC_ENET_TXF_0 ((uint)0x08000000) /* Full frame transmitted */ 364ce99d0d3SFrank Li #define FEC_ENET_TXF_1 ((uint)0x00000008) /* Full frame transmitted */ 365ce99d0d3SFrank Li #define FEC_ENET_TXF_2 ((uint)0x00000080) /* Full frame transmitted */ 366ce99d0d3SFrank Li #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ 367ce99d0d3SFrank Li #define FEC_ENET_RXF_0 ((uint)0x02000000) /* Full frame received */ 368ce99d0d3SFrank Li #define FEC_ENET_RXF_1 ((uint)0x00000002) /* Full frame received */ 369ce99d0d3SFrank Li #define FEC_ENET_RXF_2 ((uint)0x00000020) /* Full frame received */ 370ce99d0d3SFrank Li #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ 371ce99d0d3SFrank Li #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ 372ce99d0d3SFrank Li #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ 373de40ed31SNimrod Andy #define FEC_ENET_WAKEUP ((uint)0x00020000) /* Wakeup request */ 374ce99d0d3SFrank Li #define FEC_ENET_TXF (FEC_ENET_TXF_0 | FEC_ENET_TXF_1 | FEC_ENET_TXF_2) 375ce99d0d3SFrank Li #define FEC_ENET_RXF (FEC_ENET_RXF_0 | FEC_ENET_RXF_1 | FEC_ENET_RXF_2) 376ce99d0d3SFrank Li #define FEC_ENET_TS_AVAIL ((uint)0x00010000) 377ce99d0d3SFrank Li #define FEC_ENET_TS_TIMER ((uint)0x00008000) 378ce99d0d3SFrank Li 3797063c163STroy Kisky #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) 3807063c163STroy Kisky #define FEC_NAPI_IMASK FEC_ENET_MII 381ce99d0d3SFrank Li #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) 382ce99d0d3SFrank Li 383d851b47bSFugang Duan /* ENET interrupt coalescing macro define */ 384d851b47bSFugang Duan #define FEC_ITR_CLK_SEL (0x1 << 30) 385d851b47bSFugang Duan #define FEC_ITR_EN (0x1 << 31) 386df406bc9SLothar Waßmann #define FEC_ITR_ICFT(X) (((X) & 0xff) << 20) 387745f42baSLothar Waßmann #define FEC_ITR_ICTT(X) ((X) & 0xffff) 388d851b47bSFugang Duan #define FEC_ITR_ICFT_DEFAULT 200 /* Set 200 frame count threshold */ 389d851b47bSFugang Duan #define FEC_ITR_ICTT_DEFAULT 1000 /* Set 1000us timer threshold */ 390d851b47bSFugang Duan 391ce99d0d3SFrank Li #define FEC_VLAN_TAG_LEN 0x04 392ce99d0d3SFrank Li #define FEC_ETHTYPE_LEN 0x02 393ce99d0d3SFrank Li 39428b5f058SNimrod Andy /* Controller is ENET-MAC */ 39528b5f058SNimrod Andy #define FEC_QUIRK_ENET_MAC (1 << 0) 39628b5f058SNimrod Andy /* Controller needs driver to swap frame */ 39728b5f058SNimrod Andy #define FEC_QUIRK_SWAP_FRAME (1 << 1) 39828b5f058SNimrod Andy /* Controller uses gasket */ 39928b5f058SNimrod Andy #define FEC_QUIRK_USE_GASKET (1 << 2) 40028b5f058SNimrod Andy /* Controller has GBIT support */ 40128b5f058SNimrod Andy #define FEC_QUIRK_HAS_GBIT (1 << 3) 40228b5f058SNimrod Andy /* Controller has extend desc buffer */ 40328b5f058SNimrod Andy #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) 40428b5f058SNimrod Andy /* Controller has hardware checksum support */ 40528b5f058SNimrod Andy #define FEC_QUIRK_HAS_CSUM (1 << 5) 40628b5f058SNimrod Andy /* Controller has hardware vlan support */ 40728b5f058SNimrod Andy #define FEC_QUIRK_HAS_VLAN (1 << 6) 40828b5f058SNimrod Andy /* ENET IP errata ERR006358 40928b5f058SNimrod Andy * 41028b5f058SNimrod Andy * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously 41128b5f058SNimrod Andy * detected as not set during a prior frame transmission, then the 41228b5f058SNimrod Andy * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs 41328b5f058SNimrod Andy * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in 41428b5f058SNimrod Andy * frames not being transmitted until there is a 0-to-1 transition on 41528b5f058SNimrod Andy * ENET_TDAR[TDAR]. 41628b5f058SNimrod Andy */ 41728b5f058SNimrod Andy #define FEC_QUIRK_ERR006358 (1 << 7) 41828b5f058SNimrod Andy /* ENET IP hw AVB 41928b5f058SNimrod Andy * 42028b5f058SNimrod Andy * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support. 42128b5f058SNimrod Andy * - Two class indicators on receive with configurable priority 42228b5f058SNimrod Andy * - Two class indicators and line speed timer on transmit allowing 42328b5f058SNimrod Andy * implementation class credit based shapers externally 42428b5f058SNimrod Andy * - Additional DMA registers provisioned to allow managing up to 3 42528b5f058SNimrod Andy * independent rings 42628b5f058SNimrod Andy */ 42728b5f058SNimrod Andy #define FEC_QUIRK_HAS_AVB (1 << 8) 42828b5f058SNimrod Andy /* There is a TDAR race condition for mutliQ when the software sets TDAR 42928b5f058SNimrod Andy * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles). 43028b5f058SNimrod Andy * This will cause the udma_tx and udma_tx_arbiter state machines to hang. 43128b5f058SNimrod Andy * The issue exist at i.MX6SX enet IP. 43228b5f058SNimrod Andy */ 43328b5f058SNimrod Andy #define FEC_QUIRK_ERR007885 (1 << 9) 43428b5f058SNimrod Andy /* ENET Block Guide/ Chapter for the iMX6SX (PELE) address one issue: 43528b5f058SNimrod Andy * After set ENET_ATCR[Capture], there need some time cycles before the counter 43628b5f058SNimrod Andy * value is capture in the register clock domain. 43728b5f058SNimrod Andy * The wait-time-cycles is at least 6 clock cycles of the slower clock between 43828b5f058SNimrod Andy * the register clock and the 1588 clock. The 1588 ts_clk is fixed to 25Mhz, 43928b5f058SNimrod Andy * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns 44028b5f058SNimrod Andy * (40ns * 6). 44128b5f058SNimrod Andy */ 44228b5f058SNimrod Andy #define FEC_QUIRK_BUG_CAPTURE (1 << 10) 4433d125f9cSStefan Agner /* Controller has only one MDIO bus */ 4443d125f9cSStefan Agner #define FEC_QUIRK_SINGLE_MDIO (1 << 11) 44518803495SGreg Ungerer /* Controller supports RACC register */ 44618803495SGreg Ungerer #define FEC_QUIRK_HAS_RACC (1 << 12) 447ff7566b8SFugang Duan /* Controller supports interrupt coalesc */ 448ff7566b8SFugang Duan #define FEC_QUIRK_HAS_COALESCE (1 << 13) 44929380905SLucas Stach /* Interrupt doesn't wake CPU from deep idle */ 450fbae5cbbSLinus Torvalds #define FEC_QUIRK_ERR006687 (1 << 14) 4512b30842bSAndrew Lunn /* The MIB counters should be cleared and enabled during 4522b30842bSAndrew Lunn * initialisation. 4532b30842bSAndrew Lunn */ 4542b30842bSAndrew Lunn #define FEC_QUIRK_MIB_CLEAR (1 << 15) 45528b5f058SNimrod Andy 4567355f276STroy Kisky struct bufdesc_prop { 4577355f276STroy Kisky int qid; 4587355f276STroy Kisky /* Address of Rx and Tx buffers */ 4597355f276STroy Kisky struct bufdesc *base; 4607355f276STroy Kisky struct bufdesc *last; 4617355f276STroy Kisky struct bufdesc *cur; 46253bb20d1STroy Kisky void __iomem *reg_desc_active; 4637355f276STroy Kisky dma_addr_t dma; 4647355f276STroy Kisky unsigned short ring_size; 4657355f276STroy Kisky unsigned char dsize; 4667355f276STroy Kisky unsigned char dsize_log2; 4677355f276STroy Kisky }; 4687355f276STroy Kisky 4694d494cdcSFugang Duan struct fec_enet_priv_tx_q { 4707355f276STroy Kisky struct bufdesc_prop bd; 4714d494cdcSFugang Duan unsigned char *tx_bounce[TX_RING_SIZE]; 4724d494cdcSFugang Duan struct sk_buff *tx_skbuff[TX_RING_SIZE]; 4734d494cdcSFugang Duan 4744d494cdcSFugang Duan unsigned short tx_stop_threshold; 4754d494cdcSFugang Duan unsigned short tx_wake_threshold; 4764d494cdcSFugang Duan 4774d494cdcSFugang Duan struct bufdesc *dirty_tx; 4784d494cdcSFugang Duan char *tso_hdrs; 4794d494cdcSFugang Duan dma_addr_t tso_hdrs_dma; 4804d494cdcSFugang Duan }; 4814d494cdcSFugang Duan 4824d494cdcSFugang Duan struct fec_enet_priv_rx_q { 4837355f276STroy Kisky struct bufdesc_prop bd; 4844d494cdcSFugang Duan struct sk_buff *rx_skbuff[RX_RING_SIZE]; 4854d494cdcSFugang Duan }; 4864d494cdcSFugang Duan 487405f257fSFrank Li /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and 488405f257fSFrank Li * tx_bd_base always point to the base of the buffer descriptors. The 489405f257fSFrank Li * cur_rx and cur_tx point to the currently available buffer. 490405f257fSFrank Li * The dirty_tx tracks the current buffer that is being sent by the 491405f257fSFrank Li * controller. The cur_tx and dirty_tx are equal under both completely 492405f257fSFrank Li * empty and completely full conditions. The empty/ready indicator in 493405f257fSFrank Li * the buffer descriptor determines the actual condition. 494405f257fSFrank Li */ 495405f257fSFrank Li struct fec_enet_private { 496405f257fSFrank Li /* Hardware registers of the FEC device */ 497405f257fSFrank Li void __iomem *hwp; 498405f257fSFrank Li 499405f257fSFrank Li struct net_device *netdev; 500405f257fSFrank Li 501405f257fSFrank Li struct clk *clk_ipg; 502405f257fSFrank Li struct clk *clk_ahb; 5039b5330edSFugang Duan struct clk *clk_ref; 504daa7d392SWolfram Sang struct clk *clk_enet_out; 5056605b730SFrank Li struct clk *clk_ptp; 506405f257fSFrank Li 50791c0d987SNimrod Andy bool ptp_clk_on; 50891c0d987SNimrod Andy struct mutex ptp_clk_mutex; 5099fc095f1SFugang Duan unsigned int num_tx_queues; 5109fc095f1SFugang Duan unsigned int num_rx_queues; 51191c0d987SNimrod Andy 512405f257fSFrank Li /* The saved address of a sent-in-place packet/buffer, for skfree(). */ 5134d494cdcSFugang Duan struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS]; 5144d494cdcSFugang Duan struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS]; 515405f257fSFrank Li 5164d494cdcSFugang Duan unsigned int total_tx_ring_size; 5174d494cdcSFugang Duan unsigned int total_rx_ring_size; 5184d494cdcSFugang Duan 5194d494cdcSFugang Duan unsigned long work_tx; 5204d494cdcSFugang Duan unsigned long work_rx; 5214d494cdcSFugang Duan unsigned long work_ts; 5224d494cdcSFugang Duan unsigned long work_mdio; 523405f257fSFrank Li 524405f257fSFrank Li struct platform_device *pdev; 525405f257fSFrank Li 526405f257fSFrank Li int dev_id; 527405f257fSFrank Li 528405f257fSFrank Li /* Phylib and MDIO interface */ 529405f257fSFrank Li struct mii_bus *mii_bus; 530405f257fSFrank Li int mii_timeout; 531405f257fSFrank Li uint phy_speed; 532405f257fSFrank Li phy_interface_t phy_interface; 533407066f8SUwe Kleine-König struct device_node *phy_node; 534405f257fSFrank Li int link; 535405f257fSFrank Li int full_duplex; 536d97e7497SLucas Stach int speed; 537405f257fSFrank Li struct completion mdio_done; 538405f257fSFrank Li int irq[FEC_IRQ_NUM]; 539217b5844SLothar Waßmann bool bufdesc_ex; 540baa70a5cSFrank Li int pause_flag; 541de40ed31SNimrod Andy int wol_flag; 5426b7e4008SLothar Waßmann u32 quirks; 5436605b730SFrank Li 544dc975382SFrank Li struct napi_struct napi; 5454c09eed9SJim Baxter int csum_flags; 546dc975382SFrank Li 54736cdc743SRussell King struct work_struct tx_timeout_work; 54836cdc743SRussell King 5496605b730SFrank Li struct ptp_clock *ptp_clock; 5506605b730SFrank Li struct ptp_clock_info ptp_caps; 5516605b730SFrank Li unsigned long last_overflow_check; 5526605b730SFrank Li spinlock_t tmreg_lock; 5536605b730SFrank Li struct cyclecounter cc; 5546605b730SFrank Li struct timecounter tc; 5556605b730SFrank Li int rx_hwtstamp_filter; 5566605b730SFrank Li u32 base_incval; 5576605b730SFrank Li u32 cycle_speed; 5586605b730SFrank Li int hwts_rx_en; 5596605b730SFrank Li int hwts_tx_en; 56091c0d987SNimrod Andy struct delayed_work time_keep; 561f4e9f3d2SFabio Estevam struct regulator *reg_phy; 56241ef84ceSFugang Duan 56341ef84ceSFugang Duan unsigned int tx_align; 56441ef84ceSFugang Duan unsigned int rx_align; 565d851b47bSFugang Duan 566d851b47bSFugang Duan /* hw interrupt coalesce */ 567d851b47bSFugang Duan unsigned int rx_pkts_itr; 568d851b47bSFugang Duan unsigned int rx_time_itr; 569d851b47bSFugang Duan unsigned int tx_pkts_itr; 570d851b47bSFugang Duan unsigned int tx_time_itr; 571d851b47bSFugang Duan unsigned int itr_clk_rate; 5721b7bde6dSNimrod Andy 5731b7bde6dSNimrod Andy u32 rx_copybreak; 57489bddcdaSLuwei Zhou 57589bddcdaSLuwei Zhou /* ptp clock period in ns*/ 57689bddcdaSLuwei Zhou unsigned int ptp_inc; 577278d2404SLuwei Zhou 578278d2404SLuwei Zhou /* pps */ 579278d2404SLuwei Zhou int pps_channel; 580278d2404SLuwei Zhou unsigned int reload_period; 581278d2404SLuwei Zhou int pps_enable; 582278d2404SLuwei Zhou unsigned int next_counter; 58380cca775SNikita Yushchenko 58480cca775SNikita Yushchenko u64 ethtool_stats[0]; 585405f257fSFrank Li }; 586ec21e2ecSJeff Kirsher 5874ad1ceecSTroy Kisky void fec_ptp_init(struct platform_device *pdev, int irq_idx); 58832cba57bSLucas Stach void fec_ptp_stop(struct platform_device *pdev); 5896605b730SFrank Li void fec_ptp_start_cyclecounter(struct net_device *ndev); 5901d5244d0SBen Hutchings int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr); 5911d5244d0SBen Hutchings int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr); 5926605b730SFrank Li 593ec21e2ecSJeff Kirsher /****************************************************************************/ 594ec21e2ecSJeff Kirsher #endif /* FEC_H */ 595