1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* Copyright 2017-2019 NXP */ 3 4 #include <linux/mdio.h> 5 #include <linux/module.h> 6 #include <linux/fsl/enetc_mdio.h> 7 #include <linux/of_platform.h> 8 #include <linux/of_mdio.h> 9 #include <linux/of_net.h> 10 #include "enetc_ierb.h" 11 #include "enetc_pf.h" 12 13 #define ENETC_DRV_NAME_STR "ENETC PF driver" 14 15 static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr) 16 { 17 u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si)); 18 u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si)); 19 20 *(u32 *)addr = upper; 21 *(u16 *)(addr + 4) = lower; 22 } 23 24 static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si, 25 const u8 *addr) 26 { 27 u32 upper = *(const u32 *)addr; 28 u16 lower = *(const u16 *)(addr + 4); 29 30 __raw_writel(upper, hw->port + ENETC_PSIPMAR0(si)); 31 __raw_writew(lower, hw->port + ENETC_PSIPMAR1(si)); 32 } 33 34 static int enetc_pf_set_mac_addr(struct net_device *ndev, void *addr) 35 { 36 struct enetc_ndev_priv *priv = netdev_priv(ndev); 37 struct sockaddr *saddr = addr; 38 39 if (!is_valid_ether_addr(saddr->sa_data)) 40 return -EADDRNOTAVAIL; 41 42 memcpy(ndev->dev_addr, saddr->sa_data, ndev->addr_len); 43 enetc_pf_set_primary_mac_addr(&priv->si->hw, 0, saddr->sa_data); 44 45 return 0; 46 } 47 48 static void enetc_set_vlan_promisc(struct enetc_hw *hw, char si_map) 49 { 50 u32 val = enetc_port_rd(hw, ENETC_PSIPVMR); 51 52 val &= ~ENETC_PSIPVMR_SET_VP(ENETC_VLAN_PROMISC_MAP_ALL); 53 enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val); 54 } 55 56 static void enetc_enable_si_vlan_promisc(struct enetc_pf *pf, int si_idx) 57 { 58 pf->vlan_promisc_simap |= BIT(si_idx); 59 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap); 60 } 61 62 static void enetc_disable_si_vlan_promisc(struct enetc_pf *pf, int si_idx) 63 { 64 pf->vlan_promisc_simap &= ~BIT(si_idx); 65 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap); 66 } 67 68 static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos) 69 { 70 u32 val = 0; 71 72 if (vlan) 73 val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan; 74 75 enetc_port_wr(hw, ENETC_PSIVLANR(si), val); 76 } 77 78 static int enetc_mac_addr_hash_idx(const u8 *addr) 79 { 80 u64 fold = __swab64(ether_addr_to_u64(addr)) >> 16; 81 u64 mask = 0; 82 int res = 0; 83 int i; 84 85 for (i = 0; i < 8; i++) 86 mask |= BIT_ULL(i * 6); 87 88 for (i = 0; i < 6; i++) 89 res |= (hweight64(fold & (mask << i)) & 0x1) << i; 90 91 return res; 92 } 93 94 static void enetc_reset_mac_addr_filter(struct enetc_mac_filter *filter) 95 { 96 filter->mac_addr_cnt = 0; 97 98 bitmap_zero(filter->mac_hash_table, 99 ENETC_MADDR_HASH_TBL_SZ); 100 } 101 102 static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter, 103 const unsigned char *addr) 104 { 105 /* add exact match addr */ 106 ether_addr_copy(filter->mac_addr, addr); 107 filter->mac_addr_cnt++; 108 } 109 110 static void enetc_add_mac_addr_ht_filter(struct enetc_mac_filter *filter, 111 const unsigned char *addr) 112 { 113 int idx = enetc_mac_addr_hash_idx(addr); 114 115 /* add hash table entry */ 116 __set_bit(idx, filter->mac_hash_table); 117 filter->mac_addr_cnt++; 118 } 119 120 static void enetc_clear_mac_ht_flt(struct enetc_si *si, int si_idx, int type) 121 { 122 bool err = si->errata & ENETC_ERR_UCMCSWP; 123 124 if (type == UC) { 125 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 0); 126 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 0); 127 } else { /* MC */ 128 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 0); 129 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 0); 130 } 131 } 132 133 static void enetc_set_mac_ht_flt(struct enetc_si *si, int si_idx, int type, 134 unsigned long hash) 135 { 136 bool err = si->errata & ENETC_ERR_UCMCSWP; 137 138 if (type == UC) { 139 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 140 lower_32_bits(hash)); 141 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 142 upper_32_bits(hash)); 143 } else { /* MC */ 144 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 145 lower_32_bits(hash)); 146 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 147 upper_32_bits(hash)); 148 } 149 } 150 151 static void enetc_sync_mac_filters(struct enetc_pf *pf) 152 { 153 struct enetc_mac_filter *f = pf->mac_filter; 154 struct enetc_si *si = pf->si; 155 int i, pos; 156 157 pos = EMETC_MAC_ADDR_FILT_RES; 158 159 for (i = 0; i < MADDR_TYPE; i++, f++) { 160 bool em = (f->mac_addr_cnt == 1) && (i == UC); 161 bool clear = !f->mac_addr_cnt; 162 163 if (clear) { 164 if (i == UC) 165 enetc_clear_mac_flt_entry(si, pos); 166 167 enetc_clear_mac_ht_flt(si, 0, i); 168 continue; 169 } 170 171 /* exact match filter */ 172 if (em) { 173 int err; 174 175 enetc_clear_mac_ht_flt(si, 0, UC); 176 177 err = enetc_set_mac_flt_entry(si, pos, f->mac_addr, 178 BIT(0)); 179 if (!err) 180 continue; 181 182 /* fallback to HT filtering */ 183 dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n", 184 err); 185 } 186 187 /* hash table filter, clear EM filter for UC entries */ 188 if (i == UC) 189 enetc_clear_mac_flt_entry(si, pos); 190 191 enetc_set_mac_ht_flt(si, 0, i, *f->mac_hash_table); 192 } 193 } 194 195 static void enetc_pf_set_rx_mode(struct net_device *ndev) 196 { 197 struct enetc_ndev_priv *priv = netdev_priv(ndev); 198 struct enetc_pf *pf = enetc_si_priv(priv->si); 199 struct enetc_hw *hw = &priv->si->hw; 200 bool uprom = false, mprom = false; 201 struct enetc_mac_filter *filter; 202 struct netdev_hw_addr *ha; 203 u32 psipmr = 0; 204 bool em; 205 206 if (ndev->flags & IFF_PROMISC) { 207 /* enable promisc mode for SI0 (PF) */ 208 psipmr = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0); 209 uprom = true; 210 mprom = true; 211 } else if (ndev->flags & IFF_ALLMULTI) { 212 /* enable multi cast promisc mode for SI0 (PF) */ 213 psipmr = ENETC_PSIPMR_SET_MP(0); 214 mprom = true; 215 } 216 217 /* first 2 filter entries belong to PF */ 218 if (!uprom) { 219 /* Update unicast filters */ 220 filter = &pf->mac_filter[UC]; 221 enetc_reset_mac_addr_filter(filter); 222 223 em = (netdev_uc_count(ndev) == 1); 224 netdev_for_each_uc_addr(ha, ndev) { 225 if (em) { 226 enetc_add_mac_addr_em_filter(filter, ha->addr); 227 break; 228 } 229 230 enetc_add_mac_addr_ht_filter(filter, ha->addr); 231 } 232 } 233 234 if (!mprom) { 235 /* Update multicast filters */ 236 filter = &pf->mac_filter[MC]; 237 enetc_reset_mac_addr_filter(filter); 238 239 netdev_for_each_mc_addr(ha, ndev) { 240 if (!is_multicast_ether_addr(ha->addr)) 241 continue; 242 243 enetc_add_mac_addr_ht_filter(filter, ha->addr); 244 } 245 } 246 247 if (!uprom || !mprom) 248 /* update PF entries */ 249 enetc_sync_mac_filters(pf); 250 251 psipmr |= enetc_port_rd(hw, ENETC_PSIPMR) & 252 ~(ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0)); 253 enetc_port_wr(hw, ENETC_PSIPMR, psipmr); 254 } 255 256 static void enetc_set_vlan_ht_filter(struct enetc_hw *hw, int si_idx, 257 unsigned long hash) 258 { 259 enetc_port_wr(hw, ENETC_PSIVHFR0(si_idx), lower_32_bits(hash)); 260 enetc_port_wr(hw, ENETC_PSIVHFR1(si_idx), upper_32_bits(hash)); 261 } 262 263 static int enetc_vid_hash_idx(unsigned int vid) 264 { 265 int res = 0; 266 int i; 267 268 for (i = 0; i < 6; i++) 269 res |= (hweight8(vid & (BIT(i) | BIT(i + 6))) & 0x1) << i; 270 271 return res; 272 } 273 274 static void enetc_sync_vlan_ht_filter(struct enetc_pf *pf, bool rehash) 275 { 276 int i; 277 278 if (rehash) { 279 bitmap_zero(pf->vlan_ht_filter, ENETC_VLAN_HT_SIZE); 280 281 for_each_set_bit(i, pf->active_vlans, VLAN_N_VID) { 282 int hidx = enetc_vid_hash_idx(i); 283 284 __set_bit(hidx, pf->vlan_ht_filter); 285 } 286 } 287 288 enetc_set_vlan_ht_filter(&pf->si->hw, 0, *pf->vlan_ht_filter); 289 } 290 291 static int enetc_vlan_rx_add_vid(struct net_device *ndev, __be16 prot, u16 vid) 292 { 293 struct enetc_ndev_priv *priv = netdev_priv(ndev); 294 struct enetc_pf *pf = enetc_si_priv(priv->si); 295 int idx; 296 297 __set_bit(vid, pf->active_vlans); 298 299 idx = enetc_vid_hash_idx(vid); 300 if (!__test_and_set_bit(idx, pf->vlan_ht_filter)) 301 enetc_sync_vlan_ht_filter(pf, false); 302 303 return 0; 304 } 305 306 static int enetc_vlan_rx_del_vid(struct net_device *ndev, __be16 prot, u16 vid) 307 { 308 struct enetc_ndev_priv *priv = netdev_priv(ndev); 309 struct enetc_pf *pf = enetc_si_priv(priv->si); 310 311 __clear_bit(vid, pf->active_vlans); 312 enetc_sync_vlan_ht_filter(pf, true); 313 314 return 0; 315 } 316 317 static void enetc_set_loopback(struct net_device *ndev, bool en) 318 { 319 struct enetc_ndev_priv *priv = netdev_priv(ndev); 320 struct enetc_hw *hw = &priv->si->hw; 321 u32 reg; 322 323 reg = enetc_port_rd(hw, ENETC_PM0_IF_MODE); 324 if (reg & ENETC_PM0_IFM_RG) { 325 /* RGMII mode */ 326 reg = (reg & ~ENETC_PM0_IFM_RLP) | 327 (en ? ENETC_PM0_IFM_RLP : 0); 328 enetc_port_wr(hw, ENETC_PM0_IF_MODE, reg); 329 } else { 330 /* assume SGMII mode */ 331 reg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG); 332 reg = (reg & ~ENETC_PM0_CMD_XGLP) | 333 (en ? ENETC_PM0_CMD_XGLP : 0); 334 reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) | 335 (en ? ENETC_PM0_CMD_PHY_TX_EN : 0); 336 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, reg); 337 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, reg); 338 } 339 } 340 341 static int enetc_pf_set_vf_mac(struct net_device *ndev, int vf, u8 *mac) 342 { 343 struct enetc_ndev_priv *priv = netdev_priv(ndev); 344 struct enetc_pf *pf = enetc_si_priv(priv->si); 345 struct enetc_vf_state *vf_state; 346 347 if (vf >= pf->total_vfs) 348 return -EINVAL; 349 350 if (!is_valid_ether_addr(mac)) 351 return -EADDRNOTAVAIL; 352 353 vf_state = &pf->vf_state[vf]; 354 vf_state->flags |= ENETC_VF_FLAG_PF_SET_MAC; 355 enetc_pf_set_primary_mac_addr(&priv->si->hw, vf + 1, mac); 356 return 0; 357 } 358 359 static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan, 360 u8 qos, __be16 proto) 361 { 362 struct enetc_ndev_priv *priv = netdev_priv(ndev); 363 struct enetc_pf *pf = enetc_si_priv(priv->si); 364 365 if (priv->si->errata & ENETC_ERR_VLAN_ISOL) 366 return -EOPNOTSUPP; 367 368 if (vf >= pf->total_vfs) 369 return -EINVAL; 370 371 if (proto != htons(ETH_P_8021Q)) 372 /* only C-tags supported for now */ 373 return -EPROTONOSUPPORT; 374 375 enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos); 376 return 0; 377 } 378 379 static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en) 380 { 381 struct enetc_ndev_priv *priv = netdev_priv(ndev); 382 struct enetc_pf *pf = enetc_si_priv(priv->si); 383 u32 cfgr; 384 385 if (vf >= pf->total_vfs) 386 return -EINVAL; 387 388 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1)); 389 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0); 390 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr); 391 392 return 0; 393 } 394 395 static int enetc_setup_mac_address(struct device_node *np, struct enetc_pf *pf, 396 int si) 397 { 398 struct device *dev = &pf->si->pdev->dev; 399 struct enetc_hw *hw = &pf->si->hw; 400 u8 mac_addr[ETH_ALEN] = { 0 }; 401 int err; 402 403 /* (1) try to get the MAC address from the device tree */ 404 if (np) { 405 err = of_get_mac_address(np, mac_addr); 406 if (err == -EPROBE_DEFER) 407 return err; 408 } 409 410 /* (2) bootloader supplied MAC address */ 411 if (is_zero_ether_addr(mac_addr)) 412 enetc_pf_get_primary_mac_addr(hw, si, mac_addr); 413 414 /* (3) choose a random one */ 415 if (is_zero_ether_addr(mac_addr)) { 416 eth_random_addr(mac_addr); 417 dev_info(dev, "no MAC address specified for SI%d, using %pM\n", 418 si, mac_addr); 419 } 420 421 enetc_pf_set_primary_mac_addr(hw, si, mac_addr); 422 423 return 0; 424 } 425 426 static int enetc_setup_mac_addresses(struct device_node *np, 427 struct enetc_pf *pf) 428 { 429 int err, i; 430 431 /* The PF might take its MAC from the device tree */ 432 err = enetc_setup_mac_address(np, pf, 0); 433 if (err) 434 return err; 435 436 for (i = 0; i < pf->total_vfs; i++) { 437 err = enetc_setup_mac_address(NULL, pf, i + 1); 438 if (err) 439 return err; 440 } 441 442 return 0; 443 } 444 445 static void enetc_port_assign_rfs_entries(struct enetc_si *si) 446 { 447 struct enetc_pf *pf = enetc_si_priv(si); 448 struct enetc_hw *hw = &si->hw; 449 int num_entries, vf_entries, i; 450 u32 val; 451 452 /* split RFS entries between functions */ 453 val = enetc_port_rd(hw, ENETC_PRFSCAPR); 454 num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val); 455 vf_entries = num_entries / (pf->total_vfs + 1); 456 457 for (i = 0; i < pf->total_vfs; i++) 458 enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries); 459 enetc_port_wr(hw, ENETC_PSIRFSCFGR(0), 460 num_entries - vf_entries * pf->total_vfs); 461 462 /* enable RFS on port */ 463 enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE); 464 } 465 466 static void enetc_port_si_configure(struct enetc_si *si) 467 { 468 struct enetc_pf *pf = enetc_si_priv(si); 469 struct enetc_hw *hw = &si->hw; 470 int num_rings, i; 471 u32 val; 472 473 val = enetc_port_rd(hw, ENETC_PCAPR0); 474 num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val)); 475 476 val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS); 477 val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS); 478 479 if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) { 480 val = ENETC_PSICFGR0_SET_TXBDR(num_rings); 481 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings); 482 483 dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n", 484 num_rings, ENETC_PF_NUM_RINGS); 485 486 num_rings = 0; 487 } 488 489 /* Add default one-time settings for SI0 (PF) */ 490 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 491 492 enetc_port_wr(hw, ENETC_PSICFGR0(0), val); 493 494 if (num_rings) 495 num_rings -= ENETC_PF_NUM_RINGS; 496 497 /* Configure the SIs for each available VF */ 498 val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 499 val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE; 500 501 if (num_rings) { 502 num_rings /= pf->total_vfs; 503 val |= ENETC_PSICFGR0_SET_TXBDR(num_rings); 504 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings); 505 } 506 507 for (i = 0; i < pf->total_vfs; i++) 508 enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val); 509 510 /* Port level VLAN settings */ 511 val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 512 enetc_port_wr(hw, ENETC_PVCLCTR, val); 513 /* use outer tag for VLAN filtering */ 514 enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS); 515 } 516 517 static void enetc_configure_port_mac(struct enetc_hw *hw) 518 { 519 enetc_port_wr(hw, ENETC_PM0_MAXFRM, 520 ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE)); 521 522 enetc_port_wr(hw, ENETC_PTCMSDUR(0), ENETC_MAC_MAXFRM_SIZE); 523 524 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN | 525 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC); 526 527 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN | 528 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC); 529 530 /* On LS1028A, the MAC RX FIFO defaults to 2, which is too high 531 * and may lead to RX lock-up under traffic. Set it to 1 instead, 532 * as recommended by the hardware team. 533 */ 534 enetc_port_wr(hw, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL); 535 } 536 537 static void enetc_mac_config(struct enetc_hw *hw, phy_interface_t phy_mode) 538 { 539 u32 val; 540 541 if (phy_interface_mode_is_rgmii(phy_mode)) { 542 val = enetc_port_rd(hw, ENETC_PM0_IF_MODE); 543 val &= ~ENETC_PM0_IFM_EN_AUTO; 544 val &= ENETC_PM0_IFM_IFMODE_MASK; 545 val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG; 546 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val); 547 } 548 549 if (phy_mode == PHY_INTERFACE_MODE_USXGMII) { 550 val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII; 551 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val); 552 } 553 } 554 555 static void enetc_mac_enable(struct enetc_hw *hw, bool en) 556 { 557 u32 val = enetc_port_rd(hw, ENETC_PM0_CMD_CFG); 558 559 val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN); 560 val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0; 561 562 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, val); 563 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, val); 564 } 565 566 static void enetc_configure_port_pmac(struct enetc_hw *hw) 567 { 568 u32 temp; 569 570 /* Set pMAC step lock */ 571 temp = enetc_port_rd(hw, ENETC_PFPMR); 572 enetc_port_wr(hw, ENETC_PFPMR, 573 temp | ENETC_PFPMR_PMACE | ENETC_PFPMR_MWLM); 574 575 temp = enetc_port_rd(hw, ENETC_MMCSR); 576 enetc_port_wr(hw, ENETC_MMCSR, temp | ENETC_MMCSR_ME); 577 } 578 579 static void enetc_configure_port(struct enetc_pf *pf) 580 { 581 u8 hash_key[ENETC_RSSHASH_KEY_SIZE]; 582 struct enetc_hw *hw = &pf->si->hw; 583 584 enetc_configure_port_pmac(hw); 585 586 enetc_configure_port_mac(hw); 587 588 enetc_port_si_configure(pf->si); 589 590 /* set up hash key */ 591 get_random_bytes(hash_key, ENETC_RSSHASH_KEY_SIZE); 592 enetc_set_rss_key(hw, hash_key); 593 594 /* split up RFS entries */ 595 enetc_port_assign_rfs_entries(pf->si); 596 597 /* enforce VLAN promisc mode for all SIs */ 598 pf->vlan_promisc_simap = ENETC_VLAN_PROMISC_MAP_ALL; 599 enetc_set_vlan_promisc(hw, pf->vlan_promisc_simap); 600 601 enetc_port_wr(hw, ENETC_PSIPMR, 0); 602 603 /* enable port */ 604 enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN); 605 } 606 607 /* Messaging */ 608 static u16 enetc_msg_pf_set_vf_primary_mac_addr(struct enetc_pf *pf, 609 int vf_id) 610 { 611 struct enetc_vf_state *vf_state = &pf->vf_state[vf_id]; 612 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id]; 613 struct enetc_msg_cmd_set_primary_mac *cmd; 614 struct device *dev = &pf->si->pdev->dev; 615 u16 cmd_id; 616 char *addr; 617 618 cmd = (struct enetc_msg_cmd_set_primary_mac *)msg->vaddr; 619 cmd_id = cmd->header.id; 620 if (cmd_id != ENETC_MSG_CMD_MNG_ADD) 621 return ENETC_MSG_CMD_STATUS_FAIL; 622 623 addr = cmd->mac.sa_data; 624 if (vf_state->flags & ENETC_VF_FLAG_PF_SET_MAC) 625 dev_warn(dev, "Attempt to override PF set mac addr for VF%d\n", 626 vf_id); 627 else 628 enetc_pf_set_primary_mac_addr(&pf->si->hw, vf_id + 1, addr); 629 630 return ENETC_MSG_CMD_STATUS_OK; 631 } 632 633 void enetc_msg_handle_rxmsg(struct enetc_pf *pf, int vf_id, u16 *status) 634 { 635 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id]; 636 struct device *dev = &pf->si->pdev->dev; 637 struct enetc_msg_cmd_header *cmd_hdr; 638 u16 cmd_type; 639 640 *status = ENETC_MSG_CMD_STATUS_OK; 641 cmd_hdr = (struct enetc_msg_cmd_header *)msg->vaddr; 642 cmd_type = cmd_hdr->type; 643 644 switch (cmd_type) { 645 case ENETC_MSG_CMD_MNG_MAC: 646 *status = enetc_msg_pf_set_vf_primary_mac_addr(pf, vf_id); 647 break; 648 default: 649 dev_err(dev, "command not supported (cmd_type: 0x%x)\n", 650 cmd_type); 651 } 652 } 653 654 #ifdef CONFIG_PCI_IOV 655 static int enetc_sriov_configure(struct pci_dev *pdev, int num_vfs) 656 { 657 struct enetc_si *si = pci_get_drvdata(pdev); 658 struct enetc_pf *pf = enetc_si_priv(si); 659 int err; 660 661 if (!num_vfs) { 662 enetc_msg_psi_free(pf); 663 kfree(pf->vf_state); 664 pf->num_vfs = 0; 665 pci_disable_sriov(pdev); 666 } else { 667 pf->num_vfs = num_vfs; 668 669 pf->vf_state = kcalloc(num_vfs, sizeof(struct enetc_vf_state), 670 GFP_KERNEL); 671 if (!pf->vf_state) { 672 pf->num_vfs = 0; 673 return -ENOMEM; 674 } 675 676 err = enetc_msg_psi_init(pf); 677 if (err) { 678 dev_err(&pdev->dev, "enetc_msg_psi_init (%d)\n", err); 679 goto err_msg_psi; 680 } 681 682 err = pci_enable_sriov(pdev, num_vfs); 683 if (err) { 684 dev_err(&pdev->dev, "pci_enable_sriov err %d\n", err); 685 goto err_en_sriov; 686 } 687 } 688 689 return num_vfs; 690 691 err_en_sriov: 692 enetc_msg_psi_free(pf); 693 err_msg_psi: 694 kfree(pf->vf_state); 695 pf->num_vfs = 0; 696 697 return err; 698 } 699 #else 700 #define enetc_sriov_configure(pdev, num_vfs) (void)0 701 #endif 702 703 static int enetc_pf_set_features(struct net_device *ndev, 704 netdev_features_t features) 705 { 706 netdev_features_t changed = ndev->features ^ features; 707 struct enetc_ndev_priv *priv = netdev_priv(ndev); 708 709 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { 710 struct enetc_pf *pf = enetc_si_priv(priv->si); 711 712 if (!!(features & NETIF_F_HW_VLAN_CTAG_FILTER)) 713 enetc_disable_si_vlan_promisc(pf, 0); 714 else 715 enetc_enable_si_vlan_promisc(pf, 0); 716 } 717 718 if (changed & NETIF_F_LOOPBACK) 719 enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK)); 720 721 return enetc_set_features(ndev, features); 722 } 723 724 static const struct net_device_ops enetc_ndev_ops = { 725 .ndo_open = enetc_open, 726 .ndo_stop = enetc_close, 727 .ndo_start_xmit = enetc_xmit, 728 .ndo_get_stats = enetc_get_stats, 729 .ndo_set_mac_address = enetc_pf_set_mac_addr, 730 .ndo_set_rx_mode = enetc_pf_set_rx_mode, 731 .ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid, 732 .ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid, 733 .ndo_set_vf_mac = enetc_pf_set_vf_mac, 734 .ndo_set_vf_vlan = enetc_pf_set_vf_vlan, 735 .ndo_set_vf_spoofchk = enetc_pf_set_vf_spoofchk, 736 .ndo_set_features = enetc_pf_set_features, 737 .ndo_do_ioctl = enetc_ioctl, 738 .ndo_setup_tc = enetc_setup_tc, 739 .ndo_bpf = enetc_setup_bpf, 740 .ndo_xdp_xmit = enetc_xdp_xmit, 741 }; 742 743 static void enetc_pf_netdev_setup(struct enetc_si *si, struct net_device *ndev, 744 const struct net_device_ops *ndev_ops) 745 { 746 struct enetc_ndev_priv *priv = netdev_priv(ndev); 747 748 SET_NETDEV_DEV(ndev, &si->pdev->dev); 749 priv->ndev = ndev; 750 priv->si = si; 751 priv->dev = &si->pdev->dev; 752 si->ndev = ndev; 753 754 priv->msg_enable = (NETIF_MSG_WOL << 1) - 1; 755 ndev->netdev_ops = ndev_ops; 756 enetc_set_ethtool_ops(ndev); 757 ndev->watchdog_timeo = 5 * HZ; 758 ndev->max_mtu = ENETC_MAX_MTU; 759 760 ndev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM | 761 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 762 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_LOOPBACK; 763 ndev->features = NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_RXCSUM | 764 NETIF_F_HW_VLAN_CTAG_TX | 765 NETIF_F_HW_VLAN_CTAG_RX; 766 767 if (si->num_rss) 768 ndev->hw_features |= NETIF_F_RXHASH; 769 770 ndev->priv_flags |= IFF_UNICAST_FLT; 771 772 if (si->hw_features & ENETC_SI_F_QBV) 773 priv->active_offloads |= ENETC_F_QBV; 774 775 if (si->hw_features & ENETC_SI_F_PSFP && !enetc_psfp_enable(priv)) { 776 priv->active_offloads |= ENETC_F_QCI; 777 ndev->features |= NETIF_F_HW_TC; 778 ndev->hw_features |= NETIF_F_HW_TC; 779 } 780 781 /* pick up primary MAC address from SI */ 782 enetc_get_primary_mac_addr(&si->hw, ndev->dev_addr); 783 } 784 785 static int enetc_mdio_probe(struct enetc_pf *pf, struct device_node *np) 786 { 787 struct device *dev = &pf->si->pdev->dev; 788 struct enetc_mdio_priv *mdio_priv; 789 struct mii_bus *bus; 790 int err; 791 792 bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv)); 793 if (!bus) 794 return -ENOMEM; 795 796 bus->name = "Freescale ENETC MDIO Bus"; 797 bus->read = enetc_mdio_read; 798 bus->write = enetc_mdio_write; 799 bus->parent = dev; 800 mdio_priv = bus->priv; 801 mdio_priv->hw = &pf->si->hw; 802 mdio_priv->mdio_base = ENETC_EMDIO_BASE; 803 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev)); 804 805 err = of_mdiobus_register(bus, np); 806 if (err) { 807 dev_err(dev, "cannot register MDIO bus\n"); 808 return err; 809 } 810 811 pf->mdio = bus; 812 813 return 0; 814 } 815 816 static void enetc_mdio_remove(struct enetc_pf *pf) 817 { 818 if (pf->mdio) 819 mdiobus_unregister(pf->mdio); 820 } 821 822 static int enetc_imdio_create(struct enetc_pf *pf) 823 { 824 struct device *dev = &pf->si->pdev->dev; 825 struct enetc_mdio_priv *mdio_priv; 826 struct lynx_pcs *pcs_lynx; 827 struct mdio_device *pcs; 828 struct mii_bus *bus; 829 int err; 830 831 bus = mdiobus_alloc_size(sizeof(*mdio_priv)); 832 if (!bus) 833 return -ENOMEM; 834 835 bus->name = "Freescale ENETC internal MDIO Bus"; 836 bus->read = enetc_mdio_read; 837 bus->write = enetc_mdio_write; 838 bus->parent = dev; 839 bus->phy_mask = ~0; 840 mdio_priv = bus->priv; 841 mdio_priv->hw = &pf->si->hw; 842 mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE; 843 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 844 845 err = mdiobus_register(bus); 846 if (err) { 847 dev_err(dev, "cannot register internal MDIO bus (%d)\n", err); 848 goto free_mdio_bus; 849 } 850 851 pcs = mdio_device_create(bus, 0); 852 if (IS_ERR(pcs)) { 853 err = PTR_ERR(pcs); 854 dev_err(dev, "cannot create pcs (%d)\n", err); 855 goto unregister_mdiobus; 856 } 857 858 pcs_lynx = lynx_pcs_create(pcs); 859 if (!pcs_lynx) { 860 mdio_device_free(pcs); 861 err = -ENOMEM; 862 dev_err(dev, "cannot create lynx pcs (%d)\n", err); 863 goto unregister_mdiobus; 864 } 865 866 pf->imdio = bus; 867 pf->pcs = pcs_lynx; 868 869 return 0; 870 871 unregister_mdiobus: 872 mdiobus_unregister(bus); 873 free_mdio_bus: 874 mdiobus_free(bus); 875 return err; 876 } 877 878 static void enetc_imdio_remove(struct enetc_pf *pf) 879 { 880 if (pf->pcs) { 881 mdio_device_free(pf->pcs->mdio); 882 lynx_pcs_destroy(pf->pcs); 883 } 884 if (pf->imdio) { 885 mdiobus_unregister(pf->imdio); 886 mdiobus_free(pf->imdio); 887 } 888 } 889 890 static bool enetc_port_has_pcs(struct enetc_pf *pf) 891 { 892 return (pf->if_mode == PHY_INTERFACE_MODE_SGMII || 893 pf->if_mode == PHY_INTERFACE_MODE_2500BASEX || 894 pf->if_mode == PHY_INTERFACE_MODE_USXGMII); 895 } 896 897 static int enetc_mdiobus_create(struct enetc_pf *pf, struct device_node *node) 898 { 899 struct device_node *mdio_np; 900 int err; 901 902 mdio_np = of_get_child_by_name(node, "mdio"); 903 if (mdio_np) { 904 err = enetc_mdio_probe(pf, mdio_np); 905 906 of_node_put(mdio_np); 907 if (err) 908 return err; 909 } 910 911 if (enetc_port_has_pcs(pf)) { 912 err = enetc_imdio_create(pf); 913 if (err) { 914 enetc_mdio_remove(pf); 915 return err; 916 } 917 } 918 919 return 0; 920 } 921 922 static void enetc_mdiobus_destroy(struct enetc_pf *pf) 923 { 924 enetc_mdio_remove(pf); 925 enetc_imdio_remove(pf); 926 } 927 928 static void enetc_pl_mac_validate(struct phylink_config *config, 929 unsigned long *supported, 930 struct phylink_link_state *state) 931 { 932 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 933 934 if (state->interface != PHY_INTERFACE_MODE_NA && 935 state->interface != PHY_INTERFACE_MODE_INTERNAL && 936 state->interface != PHY_INTERFACE_MODE_SGMII && 937 state->interface != PHY_INTERFACE_MODE_2500BASEX && 938 state->interface != PHY_INTERFACE_MODE_USXGMII && 939 !phy_interface_mode_is_rgmii(state->interface)) { 940 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 941 return; 942 } 943 944 phylink_set_port_modes(mask); 945 phylink_set(mask, Autoneg); 946 phylink_set(mask, Pause); 947 phylink_set(mask, Asym_Pause); 948 phylink_set(mask, 10baseT_Half); 949 phylink_set(mask, 10baseT_Full); 950 phylink_set(mask, 100baseT_Half); 951 phylink_set(mask, 100baseT_Full); 952 phylink_set(mask, 100baseT_Half); 953 phylink_set(mask, 1000baseT_Half); 954 phylink_set(mask, 1000baseT_Full); 955 956 if (state->interface == PHY_INTERFACE_MODE_INTERNAL || 957 state->interface == PHY_INTERFACE_MODE_2500BASEX || 958 state->interface == PHY_INTERFACE_MODE_USXGMII) { 959 phylink_set(mask, 2500baseT_Full); 960 phylink_set(mask, 2500baseX_Full); 961 } 962 963 bitmap_and(supported, supported, mask, 964 __ETHTOOL_LINK_MODE_MASK_NBITS); 965 bitmap_and(state->advertising, state->advertising, mask, 966 __ETHTOOL_LINK_MODE_MASK_NBITS); 967 } 968 969 static void enetc_pl_mac_config(struct phylink_config *config, 970 unsigned int mode, 971 const struct phylink_link_state *state) 972 { 973 struct enetc_pf *pf = phylink_to_enetc_pf(config); 974 struct enetc_ndev_priv *priv; 975 976 enetc_mac_config(&pf->si->hw, state->interface); 977 978 priv = netdev_priv(pf->si->ndev); 979 if (pf->pcs) 980 phylink_set_pcs(priv->phylink, &pf->pcs->pcs); 981 } 982 983 static void enetc_force_rgmii_mac(struct enetc_hw *hw, int speed, int duplex) 984 { 985 u32 old_val, val; 986 987 old_val = val = enetc_port_rd(hw, ENETC_PM0_IF_MODE); 988 989 if (speed == SPEED_1000) { 990 val &= ~ENETC_PM0_IFM_SSP_MASK; 991 val |= ENETC_PM0_IFM_SSP_1000; 992 } else if (speed == SPEED_100) { 993 val &= ~ENETC_PM0_IFM_SSP_MASK; 994 val |= ENETC_PM0_IFM_SSP_100; 995 } else if (speed == SPEED_10) { 996 val &= ~ENETC_PM0_IFM_SSP_MASK; 997 val |= ENETC_PM0_IFM_SSP_10; 998 } 999 1000 if (duplex == DUPLEX_FULL) 1001 val |= ENETC_PM0_IFM_FULL_DPX; 1002 else 1003 val &= ~ENETC_PM0_IFM_FULL_DPX; 1004 1005 if (val == old_val) 1006 return; 1007 1008 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val); 1009 } 1010 1011 static void enetc_pl_mac_link_up(struct phylink_config *config, 1012 struct phy_device *phy, unsigned int mode, 1013 phy_interface_t interface, int speed, 1014 int duplex, bool tx_pause, bool rx_pause) 1015 { 1016 struct enetc_pf *pf = phylink_to_enetc_pf(config); 1017 u32 pause_off_thresh = 0, pause_on_thresh = 0; 1018 u32 init_quanta = 0, refresh_quanta = 0; 1019 struct enetc_hw *hw = &pf->si->hw; 1020 struct enetc_ndev_priv *priv; 1021 u32 rbmr, cmd_cfg; 1022 int idx; 1023 1024 priv = netdev_priv(pf->si->ndev); 1025 if (priv->active_offloads & ENETC_F_QBV) 1026 enetc_sched_speed_set(priv, speed); 1027 1028 if (!phylink_autoneg_inband(mode) && 1029 phy_interface_mode_is_rgmii(interface)) 1030 enetc_force_rgmii_mac(hw, speed, duplex); 1031 1032 /* Flow control */ 1033 for (idx = 0; idx < priv->num_rx_rings; idx++) { 1034 rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR); 1035 1036 if (tx_pause) 1037 rbmr |= ENETC_RBMR_CM; 1038 else 1039 rbmr &= ~ENETC_RBMR_CM; 1040 1041 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr); 1042 } 1043 1044 if (tx_pause) { 1045 /* When the port first enters congestion, send a PAUSE request 1046 * with the maximum number of quanta. When the port exits 1047 * congestion, it will automatically send a PAUSE frame with 1048 * zero quanta. 1049 */ 1050 init_quanta = 0xffff; 1051 1052 /* Also, set up the refresh timer to send follow-up PAUSE 1053 * frames at half the quanta value, in case the congestion 1054 * condition persists. 1055 */ 1056 refresh_quanta = 0xffff / 2; 1057 1058 /* Start emitting PAUSE frames when 3 large frames (or more 1059 * smaller frames) have accumulated in the FIFO waiting to be 1060 * DMAed to the RX ring. 1061 */ 1062 pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE; 1063 pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE; 1064 } 1065 1066 enetc_port_wr(hw, ENETC_PM0_PAUSE_QUANTA, init_quanta); 1067 enetc_port_wr(hw, ENETC_PM1_PAUSE_QUANTA, init_quanta); 1068 enetc_port_wr(hw, ENETC_PM0_PAUSE_THRESH, refresh_quanta); 1069 enetc_port_wr(hw, ENETC_PM1_PAUSE_THRESH, refresh_quanta); 1070 enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh); 1071 enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh); 1072 1073 cmd_cfg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG); 1074 1075 if (rx_pause) 1076 cmd_cfg &= ~ENETC_PM0_PAUSE_IGN; 1077 else 1078 cmd_cfg |= ENETC_PM0_PAUSE_IGN; 1079 1080 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, cmd_cfg); 1081 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, cmd_cfg); 1082 1083 enetc_mac_enable(hw, true); 1084 } 1085 1086 static void enetc_pl_mac_link_down(struct phylink_config *config, 1087 unsigned int mode, 1088 phy_interface_t interface) 1089 { 1090 struct enetc_pf *pf = phylink_to_enetc_pf(config); 1091 1092 enetc_mac_enable(&pf->si->hw, false); 1093 } 1094 1095 static const struct phylink_mac_ops enetc_mac_phylink_ops = { 1096 .validate = enetc_pl_mac_validate, 1097 .mac_config = enetc_pl_mac_config, 1098 .mac_link_up = enetc_pl_mac_link_up, 1099 .mac_link_down = enetc_pl_mac_link_down, 1100 }; 1101 1102 static int enetc_phylink_create(struct enetc_ndev_priv *priv, 1103 struct device_node *node) 1104 { 1105 struct enetc_pf *pf = enetc_si_priv(priv->si); 1106 struct phylink *phylink; 1107 int err; 1108 1109 pf->phylink_config.dev = &priv->ndev->dev; 1110 pf->phylink_config.type = PHYLINK_NETDEV; 1111 1112 phylink = phylink_create(&pf->phylink_config, of_fwnode_handle(node), 1113 pf->if_mode, &enetc_mac_phylink_ops); 1114 if (IS_ERR(phylink)) { 1115 err = PTR_ERR(phylink); 1116 return err; 1117 } 1118 1119 priv->phylink = phylink; 1120 1121 return 0; 1122 } 1123 1124 static void enetc_phylink_destroy(struct enetc_ndev_priv *priv) 1125 { 1126 if (priv->phylink) 1127 phylink_destroy(priv->phylink); 1128 } 1129 1130 /* Initialize the entire shared memory for the flow steering entries 1131 * of this port (PF + VFs) 1132 */ 1133 static int enetc_init_port_rfs_memory(struct enetc_si *si) 1134 { 1135 struct enetc_cmd_rfse rfse = {0}; 1136 struct enetc_hw *hw = &si->hw; 1137 int num_rfs, i, err = 0; 1138 u32 val; 1139 1140 val = enetc_port_rd(hw, ENETC_PRFSCAPR); 1141 num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val); 1142 1143 for (i = 0; i < num_rfs; i++) { 1144 err = enetc_set_fs_entry(si, &rfse, i); 1145 if (err) 1146 break; 1147 } 1148 1149 return err; 1150 } 1151 1152 static int enetc_init_port_rss_memory(struct enetc_si *si) 1153 { 1154 struct enetc_hw *hw = &si->hw; 1155 int num_rss, err; 1156 int *rss_table; 1157 u32 val; 1158 1159 val = enetc_port_rd(hw, ENETC_PRSSCAPR); 1160 num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val); 1161 if (!num_rss) 1162 return 0; 1163 1164 rss_table = kcalloc(num_rss, sizeof(*rss_table), GFP_KERNEL); 1165 if (!rss_table) 1166 return -ENOMEM; 1167 1168 err = enetc_set_rss_table(si, rss_table, num_rss); 1169 1170 kfree(rss_table); 1171 1172 return err; 1173 } 1174 1175 static int enetc_pf_register_with_ierb(struct pci_dev *pdev) 1176 { 1177 struct device_node *node = pdev->dev.of_node; 1178 struct platform_device *ierb_pdev; 1179 struct device_node *ierb_node; 1180 1181 /* Don't register with the IERB if the PF itself is disabled */ 1182 if (!node || !of_device_is_available(node)) 1183 return 0; 1184 1185 ierb_node = of_find_compatible_node(NULL, NULL, 1186 "fsl,ls1028a-enetc-ierb"); 1187 if (!ierb_node || !of_device_is_available(ierb_node)) 1188 return -ENODEV; 1189 1190 ierb_pdev = of_find_device_by_node(ierb_node); 1191 of_node_put(ierb_node); 1192 1193 if (!ierb_pdev) 1194 return -EPROBE_DEFER; 1195 1196 return enetc_ierb_register_pf(ierb_pdev, pdev); 1197 } 1198 1199 static int enetc_pf_probe(struct pci_dev *pdev, 1200 const struct pci_device_id *ent) 1201 { 1202 struct device_node *node = pdev->dev.of_node; 1203 struct enetc_ndev_priv *priv; 1204 struct net_device *ndev; 1205 struct enetc_si *si; 1206 struct enetc_pf *pf; 1207 int err; 1208 1209 err = enetc_pf_register_with_ierb(pdev); 1210 if (err == -EPROBE_DEFER) 1211 return err; 1212 if (err) 1213 dev_warn(&pdev->dev, 1214 "Could not register with IERB driver: %pe, please update the device tree\n", 1215 ERR_PTR(err)); 1216 1217 err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(*pf)); 1218 if (err) { 1219 dev_err(&pdev->dev, "PCI probing failed\n"); 1220 return err; 1221 } 1222 1223 si = pci_get_drvdata(pdev); 1224 if (!si->hw.port || !si->hw.global) { 1225 err = -ENODEV; 1226 dev_err(&pdev->dev, "could not map PF space, probing a VF?\n"); 1227 goto err_map_pf_space; 1228 } 1229 1230 err = enetc_setup_cbdr(&pdev->dev, &si->hw, ENETC_CBDR_DEFAULT_SIZE, 1231 &si->cbd_ring); 1232 if (err) 1233 goto err_setup_cbdr; 1234 1235 err = enetc_init_port_rfs_memory(si); 1236 if (err) { 1237 dev_err(&pdev->dev, "Failed to initialize RFS memory\n"); 1238 goto err_init_port_rfs; 1239 } 1240 1241 err = enetc_init_port_rss_memory(si); 1242 if (err) { 1243 dev_err(&pdev->dev, "Failed to initialize RSS memory\n"); 1244 goto err_init_port_rss; 1245 } 1246 1247 if (node && !of_device_is_available(node)) { 1248 dev_info(&pdev->dev, "device is disabled, skipping\n"); 1249 err = -ENODEV; 1250 goto err_device_disabled; 1251 } 1252 1253 pf = enetc_si_priv(si); 1254 pf->si = si; 1255 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 1256 1257 err = enetc_setup_mac_addresses(node, pf); 1258 if (err) 1259 goto err_setup_mac_addresses; 1260 1261 enetc_configure_port(pf); 1262 1263 enetc_get_si_caps(si); 1264 1265 ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS); 1266 if (!ndev) { 1267 err = -ENOMEM; 1268 dev_err(&pdev->dev, "netdev creation failed\n"); 1269 goto err_alloc_netdev; 1270 } 1271 1272 enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops); 1273 1274 priv = netdev_priv(ndev); 1275 1276 enetc_init_si_rings_params(priv); 1277 1278 err = enetc_alloc_si_resources(priv); 1279 if (err) { 1280 dev_err(&pdev->dev, "SI resource alloc failed\n"); 1281 goto err_alloc_si_res; 1282 } 1283 1284 err = enetc_configure_si(priv); 1285 if (err) { 1286 dev_err(&pdev->dev, "Failed to configure SI\n"); 1287 goto err_config_si; 1288 } 1289 1290 err = enetc_alloc_msix(priv); 1291 if (err) { 1292 dev_err(&pdev->dev, "MSIX alloc failed\n"); 1293 goto err_alloc_msix; 1294 } 1295 1296 if (!of_get_phy_mode(node, &pf->if_mode)) { 1297 err = enetc_mdiobus_create(pf, node); 1298 if (err) 1299 goto err_mdiobus_create; 1300 1301 err = enetc_phylink_create(priv, node); 1302 if (err) 1303 goto err_phylink_create; 1304 } 1305 1306 err = register_netdev(ndev); 1307 if (err) 1308 goto err_reg_netdev; 1309 1310 return 0; 1311 1312 err_reg_netdev: 1313 enetc_phylink_destroy(priv); 1314 err_phylink_create: 1315 enetc_mdiobus_destroy(pf); 1316 err_mdiobus_create: 1317 enetc_free_msix(priv); 1318 err_config_si: 1319 err_alloc_msix: 1320 enetc_free_si_resources(priv); 1321 err_alloc_si_res: 1322 si->ndev = NULL; 1323 free_netdev(ndev); 1324 err_alloc_netdev: 1325 err_init_port_rss: 1326 err_init_port_rfs: 1327 err_device_disabled: 1328 err_setup_mac_addresses: 1329 enetc_teardown_cbdr(&si->cbd_ring); 1330 err_setup_cbdr: 1331 err_map_pf_space: 1332 enetc_pci_remove(pdev); 1333 1334 return err; 1335 } 1336 1337 static void enetc_pf_remove(struct pci_dev *pdev) 1338 { 1339 struct enetc_si *si = pci_get_drvdata(pdev); 1340 struct enetc_pf *pf = enetc_si_priv(si); 1341 struct enetc_ndev_priv *priv; 1342 1343 priv = netdev_priv(si->ndev); 1344 1345 if (pf->num_vfs) 1346 enetc_sriov_configure(pdev, 0); 1347 1348 unregister_netdev(si->ndev); 1349 1350 enetc_phylink_destroy(priv); 1351 enetc_mdiobus_destroy(pf); 1352 1353 enetc_free_msix(priv); 1354 1355 enetc_free_si_resources(priv); 1356 enetc_teardown_cbdr(&si->cbd_ring); 1357 1358 free_netdev(si->ndev); 1359 1360 enetc_pci_remove(pdev); 1361 } 1362 1363 static const struct pci_device_id enetc_pf_id_table[] = { 1364 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) }, 1365 { 0, } /* End of table. */ 1366 }; 1367 MODULE_DEVICE_TABLE(pci, enetc_pf_id_table); 1368 1369 static struct pci_driver enetc_pf_driver = { 1370 .name = KBUILD_MODNAME, 1371 .id_table = enetc_pf_id_table, 1372 .probe = enetc_pf_probe, 1373 .remove = enetc_pf_remove, 1374 #ifdef CONFIG_PCI_IOV 1375 .sriov_configure = enetc_sriov_configure, 1376 #endif 1377 }; 1378 module_pci_driver(enetc_pf_driver); 1379 1380 MODULE_DESCRIPTION(ENETC_DRV_NAME_STR); 1381 MODULE_LICENSE("Dual BSD/GPL"); 1382